drivers/scsi/lpfc/lpfc_hw4.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2009 Emulex.  All rights reserved.                *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 /* Macros to deal with bit fields. Each bit field must have 3 #defines
  22  * associated with it (_SHIFT, _MASK, and _WORD).
  23  * EG. For a bit field that is in the 7th bit of the "field4" field of a
  24  * structure and is 2 bits in size the following #defines must exist:
  25  *      struct temp {
  26  *              uint32_t        field1;
  27  *              uint32_t        field2;
  28  *              uint32_t        field3;
  29  *              uint32_t        field4;
  30  *      #define example_bit_field_SHIFT         7
  31  *      #define example_bit_field_MASK          0x03
  32  *      #define example_bit_field_WORD          field4
  33  *              uint32_t        field5;
  34  *      };
  35  * Then the macros below may be used to get or set the value of that field.
  36  * EG. To get the value of the bit field from the above example:
  37  *      struct temp t1;
  38  *      value = bf_get(example_bit_field, &t1);
  39  * And then to set that bit field:
  40  *      bf_set(example_bit_field, &t1, 2);
  41  * Or clear that bit field:
  42  *      bf_set(example_bit_field, &t1, 0);
  43  */
  44 #define bf_get_le32(name, ptr) \
  45         ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  46 #define bf_get(name, ptr) \
  47         (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
  48 #define bf_set_le32(name, ptr, value) \
  49         ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
  50         name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
  51         ~(name##_MASK << name##_SHIFT)))))
  52 #define bf_set(name, ptr, value) \
  53         ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
  54                  ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
  55
  56 struct dma_address {
  57         uint32_t addr_lo;
  58         uint32_t addr_hi;
  59 };
  60
  61 struct lpfc_sli_intf {
  62         uint32_t word0;
  63 #define lpfc_sli_intf_valid_SHIFT               29
  64 #define lpfc_sli_intf_valid_MASK                0x00000007
  65 #define lpfc_sli_intf_valid_WORD                word0
  66 #define LPFC_SLI_INTF_VALID             6
  67 #define lpfc_sli_intf_featurelevel2_SHIFT       24
  68 #define lpfc_sli_intf_featurelevel2_MASK        0x0000001F
  69 #define lpfc_sli_intf_featurelevel2_WORD        word0
  70 #define lpfc_sli_intf_featurelevel1_SHIFT       16
  71 #define lpfc_sli_intf_featurelevel1_MASK        0x000000FF
  72 #define lpfc_sli_intf_featurelevel1_WORD        word0
  73 #define LPFC_SLI_INTF_FEATURELEVEL1_1   1
  74 #define LPFC_SLI_INTF_FEATURELEVEL1_2   2
  75 #define lpfc_sli_intf_sli_family_SHIFT          8
  76 #define lpfc_sli_intf_sli_family_MASK           0x000000FF
  77 #define lpfc_sli_intf_sli_family_WORD           word0
  78 #define LPFC_SLI_INTF_FAMILY_BE2        0
  79 #define LPFC_SLI_INTF_FAMILY_BE3        1
  80 #define lpfc_sli_intf_slirev_SHIFT              4
  81 #define lpfc_sli_intf_slirev_MASK               0x0000000F
  82 #define lpfc_sli_intf_slirev_WORD               word0
  83 #define LPFC_SLI_INTF_REV_SLI3          3
  84 #define LPFC_SLI_INTF_REV_SLI4          4
  85 #define lpfc_sli_intf_if_type_SHIFT             0
  86 #define lpfc_sli_intf_if_type_MASK              0x00000007
  87 #define lpfc_sli_intf_if_type_WORD              word0
  88 #define LPFC_SLI_INTF_IF_TYPE_0         0
  89 #define LPFC_SLI_INTF_IF_TYPE_1         1
  90 };
  91
  92 #define LPFC_SLI4_MBX_EMBED     true
  93 #define LPFC_SLI4_MBX_NEMBED    false
  94
  95 #define LPFC_SLI4_MB_WORD_COUNT         64
  96 #define LPFC_MAX_MQ_PAGE                8
  97 #define LPFC_MAX_WQ_PAGE                8
  98 #define LPFC_MAX_CQ_PAGE                4
  99 #define LPFC_MAX_EQ_PAGE                8
 100
 101 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
 102 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
 103 #define LPFC_VFR_PAGE_SIZE      0x1000 /* 4KB BAR2 per-VF register page size */
 104
 105 /* Define SLI4 Alignment requirements. */
 106 #define LPFC_ALIGN_16_BYTE      16
 107 #define LPFC_ALIGN_64_BYTE      64
 108
 109 /* Define SLI4 specific definitions. */
 110 #define LPFC_MQ_CQE_BYTE_OFFSET 256
 111 #define LPFC_MBX_CMD_HDR_LENGTH 16
 112 #define LPFC_MBX_ERROR_RANGE    0x4000
 113 #define LPFC_BMBX_BIT1_ADDR_HI  0x2
 114 #define LPFC_BMBX_BIT1_ADDR_LO  0
 115 #define LPFC_RPI_HDR_COUNT      64
 116 #define LPFC_HDR_TEMPLATE_SIZE  4096
 117 #define LPFC_RPI_ALLOC_ERROR    0xFFFF
 118 #define LPFC_FCF_RECORD_WD_CNT  132
 119 #define LPFC_ENTIRE_FCF_DATABASE 0
 120 #define LPFC_DFLT_FCF_INDEX      0
 121
 122 /* Virtual function numbers */
 123 #define LPFC_VF0                0
 124 #define LPFC_VF1                1
 125 #define LPFC_VF2                2
 126 #define LPFC_VF3                3
 127 #define LPFC_VF4                4
 128 #define LPFC_VF5                5
 129 #define LPFC_VF6                6
 130 #define LPFC_VF7                7
 131 #define LPFC_VF8                8
 132 #define LPFC_VF9                9
 133 #define LPFC_VF10               10
 134 #define LPFC_VF11               11
 135 #define LPFC_VF12               12
 136 #define LPFC_VF13               13
 137 #define LPFC_VF14               14
 138 #define LPFC_VF15               15
 139 #define LPFC_VF16               16
 140 #define LPFC_VF17               17
 141 #define LPFC_VF18               18
 142 #define LPFC_VF19               19
 143 #define LPFC_VF20               20
 144 #define LPFC_VF21               21
 145 #define LPFC_VF22               22
 146 #define LPFC_VF23               23
 147 #define LPFC_VF24               24
 148 #define LPFC_VF25               25
 149 #define LPFC_VF26               26
 150 #define LPFC_VF27               27
 151 #define LPFC_VF28               28
 152 #define LPFC_VF29               29
 153 #define LPFC_VF30               30
 154 #define LPFC_VF31               31
 155
 156 /* PCI function numbers */
 157 #define LPFC_PCI_FUNC0          0
 158 #define LPFC_PCI_FUNC1          1
 159 #define LPFC_PCI_FUNC2          2
 160 #define LPFC_PCI_FUNC3          3
 161 #define LPFC_PCI_FUNC4          4
 162
 163 /* Active interrupt test count */
 164 #define LPFC_ACT_INTR_CNT       4
 165
 166 /* Delay Multiplier constant */
 167 #define LPFC_DMULT_CONST       651042
 168 #define LPFC_MIM_IMAX          636
 169 #define LPFC_FP_DEF_IMAX       10000
 170 #define LPFC_SP_DEF_IMAX       10000
 171
 172 /* PORT_CAPABILITIES constants. */
 173 #define LPFC_MAX_SUPPORTED_PAGES        8
 174
 175 struct ulp_bde64 {
 176         union ULP_BDE_TUS {
 177                 uint32_t w;
 178                 struct {
 179 #ifdef __BIG_ENDIAN_BITFIELD
 180                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 181                                                    VALUE !! */
 182                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 183 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 184                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 185                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 186                                                    VALUE !! */
 187 #endif
 188 #define BUFF_TYPE_BDE_64    0x00        /* BDE (Host_resident) */
 189 #define BUFF_TYPE_BDE_IMMED 0x01        /* Immediate Data BDE */
 190 #define BUFF_TYPE_BDE_64P   0x02        /* BDE (Port-resident) */
 191 #define BUFF_TYPE_BDE_64I   0x08        /* Input BDE (Host-resident) */
 192 #define BUFF_TYPE_BDE_64IP  0x0A        /* Input BDE (Port-resident) */
 193 #define BUFF_TYPE_BLP_64    0x40        /* BLP (Host-resident) */
 194 #define BUFF_TYPE_BLP_64P   0x42        /* BLP (Port-resident) */
 195                 } f;
 196         } tus;
 197         uint32_t addrLow;
 198         uint32_t addrHigh;
 199 };
 200
 201 struct lpfc_sli4_flags {
 202         uint32_t word0;
 203 #define lpfc_fip_flag_SHIFT 0
 204 #define lpfc_fip_flag_MASK 0x00000001
 205 #define lpfc_fip_flag_WORD word0
 206 };
 207
 208 struct sli4_bls_acc {
 209         uint32_t word0_rsvd;      /* Word0 must be reserved */
 210         uint32_t word1;
 211 #define lpfc_abts_orig_SHIFT      0
 212 #define lpfc_abts_orig_MASK       0x00000001
 213 #define lpfc_abts_orig_WORD       word1
 214 #define LPFC_ABTS_UNSOL_RSP       1
 215 #define LPFC_ABTS_UNSOL_INT       0
 216         uint32_t word2;
 217 #define lpfc_abts_rxid_SHIFT      0
 218 #define lpfc_abts_rxid_MASK       0x0000FFFF
 219 #define lpfc_abts_rxid_WORD       word2
 220 #define lpfc_abts_oxid_SHIFT      16
 221 #define lpfc_abts_oxid_MASK       0x0000FFFF
 222 #define lpfc_abts_oxid_WORD       word2
 223         uint32_t word3;
 224         uint32_t word4;
 225         uint32_t word5_rsvd;    /* Word5 must be reserved */
 226 };
 227
 228 /* event queue entry structure */
 229 struct lpfc_eqe {
 230         uint32_t word0;
 231 #define lpfc_eqe_resource_id_SHIFT      16
 232 #define lpfc_eqe_resource_id_MASK       0x000000FF
 233 #define lpfc_eqe_resource_id_WORD       word0
 234 #define lpfc_eqe_minor_code_SHIFT       4
 235 #define lpfc_eqe_minor_code_MASK        0x00000FFF
 236 #define lpfc_eqe_minor_code_WORD        word0
 237 #define lpfc_eqe_major_code_SHIFT       1
 238 #define lpfc_eqe_major_code_MASK        0x00000007
 239 #define lpfc_eqe_major_code_WORD        word0
 240 #define lpfc_eqe_valid_SHIFT            0
 241 #define lpfc_eqe_valid_MASK             0x00000001
 242 #define lpfc_eqe_valid_WORD             word0
 243 };
 244
 245 /* completion queue entry structure (common fields for all cqe types) */
 246 struct lpfc_cqe {
 247         uint32_t reserved0;
 248         uint32_t reserved1;
 249         uint32_t reserved2;
 250         uint32_t word3;
 251 #define lpfc_cqe_valid_SHIFT            31
 252 #define lpfc_cqe_valid_MASK             0x00000001
 253 #define lpfc_cqe_valid_WORD             word3
 254 #define lpfc_cqe_code_SHIFT             16
 255 #define lpfc_cqe_code_MASK              0x000000FF
 256 #define lpfc_cqe_code_WORD              word3
 257 };
 258
 259 /* Completion Queue Entry Status Codes */
 260 #define CQE_STATUS_SUCCESS              0x0
 261 #define CQE_STATUS_FCP_RSP_FAILURE      0x1
 262 #define CQE_STATUS_REMOTE_STOP          0x2
 263 #define CQE_STATUS_LOCAL_REJECT         0x3
 264 #define CQE_STATUS_NPORT_RJT            0x4
 265 #define CQE_STATUS_FABRIC_RJT           0x5
 266 #define CQE_STATUS_NPORT_BSY            0x6
 267 #define CQE_STATUS_FABRIC_BSY           0x7
 268 #define CQE_STATUS_INTERMED_RSP         0x8
 269 #define CQE_STATUS_LS_RJT               0x9
 270 #define CQE_STATUS_CMD_REJECT           0xb
 271 #define CQE_STATUS_FCP_TGT_LENCHECK     0xc
 272 #define CQE_STATUS_NEED_BUFF_ENTRY      0xf
 273
 274 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
 275 #define CQE_HW_STATUS_NO_ERR            0x0
 276 #define CQE_HW_STATUS_UNDERRUN          0x1
 277 #define CQE_HW_STATUS_OVERRUN           0x2
 278
 279 /* Completion Queue Entry Codes */
 280 #define CQE_CODE_COMPL_WQE              0x1
 281 #define CQE_CODE_RELEASE_WQE            0x2
 282 #define CQE_CODE_RECEIVE                0x4
 283 #define CQE_CODE_XRI_ABORTED            0x5
 284
 285 /* completion queue entry for wqe completions */
 286 struct lpfc_wcqe_complete {
 287         uint32_t word0;
 288 #define lpfc_wcqe_c_request_tag_SHIFT   16
 289 #define lpfc_wcqe_c_request_tag_MASK    0x0000FFFF
 290 #define lpfc_wcqe_c_request_tag_WORD    word0
 291 #define lpfc_wcqe_c_status_SHIFT        8
 292 #define lpfc_wcqe_c_status_MASK         0x000000FF
 293 #define lpfc_wcqe_c_status_WORD         word0
 294 #define lpfc_wcqe_c_hw_status_SHIFT     0
 295 #define lpfc_wcqe_c_hw_status_MASK      0x000000FF
 296 #define lpfc_wcqe_c_hw_status_WORD      word0
 297         uint32_t total_data_placed;
 298         uint32_t parameter;
 299         uint32_t word3;
 300 #define lpfc_wcqe_c_valid_SHIFT         lpfc_cqe_valid_SHIFT
 301 #define lpfc_wcqe_c_valid_MASK          lpfc_cqe_valid_MASK
 302 #define lpfc_wcqe_c_valid_WORD          lpfc_cqe_valid_WORD
 303 #define lpfc_wcqe_c_xb_SHIFT            28
 304 #define lpfc_wcqe_c_xb_MASK             0x00000001
 305 #define lpfc_wcqe_c_xb_WORD             word3
 306 #define lpfc_wcqe_c_pv_SHIFT            27
 307 #define lpfc_wcqe_c_pv_MASK             0x00000001
 308 #define lpfc_wcqe_c_pv_WORD             word3
 309 #define lpfc_wcqe_c_priority_SHIFT      24
 310 #define lpfc_wcqe_c_priority_MASK               0x00000007
 311 #define lpfc_wcqe_c_priority_WORD               word3
 312 #define lpfc_wcqe_c_code_SHIFT          lpfc_cqe_code_SHIFT
 313 #define lpfc_wcqe_c_code_MASK           lpfc_cqe_code_MASK
 314 #define lpfc_wcqe_c_code_WORD           lpfc_cqe_code_WORD
 315 };
 316
 317 /* completion queue entry for wqe release */
 318 struct lpfc_wcqe_release {
 319         uint32_t reserved0;
 320         uint32_t reserved1;
 321         uint32_t word2;
 322 #define lpfc_wcqe_r_wq_id_SHIFT         16
 323 #define lpfc_wcqe_r_wq_id_MASK          0x0000FFFF
 324 #define lpfc_wcqe_r_wq_id_WORD          word2
 325 #define lpfc_wcqe_r_wqe_index_SHIFT     0
 326 #define lpfc_wcqe_r_wqe_index_MASK      0x0000FFFF
 327 #define lpfc_wcqe_r_wqe_index_WORD      word2
 328         uint32_t word3;
 329 #define lpfc_wcqe_r_valid_SHIFT         lpfc_cqe_valid_SHIFT
 330 #define lpfc_wcqe_r_valid_MASK          lpfc_cqe_valid_MASK
 331 #define lpfc_wcqe_r_valid_WORD          lpfc_cqe_valid_WORD
 332 #define lpfc_wcqe_r_code_SHIFT          lpfc_cqe_code_SHIFT
 333 #define lpfc_wcqe_r_code_MASK           lpfc_cqe_code_MASK
 334 #define lpfc_wcqe_r_code_WORD           lpfc_cqe_code_WORD
 335 };
 336
 337 struct sli4_wcqe_xri_aborted {
 338         uint32_t word0;
 339 #define lpfc_wcqe_xa_status_SHIFT               8
 340 #define lpfc_wcqe_xa_status_MASK                0x000000FF
 341 #define lpfc_wcqe_xa_status_WORD                word0
 342         uint32_t parameter;
 343         uint32_t word2;
 344 #define lpfc_wcqe_xa_remote_xid_SHIFT   16
 345 #define lpfc_wcqe_xa_remote_xid_MASK    0x0000FFFF
 346 #define lpfc_wcqe_xa_remote_xid_WORD    word2
 347 #define lpfc_wcqe_xa_xri_SHIFT          0
 348 #define lpfc_wcqe_xa_xri_MASK           0x0000FFFF
 349 #define lpfc_wcqe_xa_xri_WORD           word2
 350         uint32_t word3;
 351 #define lpfc_wcqe_xa_valid_SHIFT        lpfc_cqe_valid_SHIFT
 352 #define lpfc_wcqe_xa_valid_MASK         lpfc_cqe_valid_MASK
 353 #define lpfc_wcqe_xa_valid_WORD         lpfc_cqe_valid_WORD
 354 #define lpfc_wcqe_xa_ia_SHIFT           30
 355 #define lpfc_wcqe_xa_ia_MASK            0x00000001
 356 #define lpfc_wcqe_xa_ia_WORD            word3
 357 #define CQE_XRI_ABORTED_IA_REMOTE       0
 358 #define CQE_XRI_ABORTED_IA_LOCAL        1
 359 #define lpfc_wcqe_xa_br_SHIFT           29
 360 #define lpfc_wcqe_xa_br_MASK            0x00000001
 361 #define lpfc_wcqe_xa_br_WORD            word3
 362 #define CQE_XRI_ABORTED_BR_BA_ACC       0
 363 #define CQE_XRI_ABORTED_BR_BA_RJT       1
 364 #define lpfc_wcqe_xa_eo_SHIFT           28
 365 #define lpfc_wcqe_xa_eo_MASK            0x00000001
 366 #define lpfc_wcqe_xa_eo_WORD            word3
 367 #define CQE_XRI_ABORTED_EO_REMOTE       0
 368 #define CQE_XRI_ABORTED_EO_LOCAL        1
 369 #define lpfc_wcqe_xa_code_SHIFT         lpfc_cqe_code_SHIFT
 370 #define lpfc_wcqe_xa_code_MASK          lpfc_cqe_code_MASK
 371 #define lpfc_wcqe_xa_code_WORD          lpfc_cqe_code_WORD
 372 };
 373
 374 /* completion queue entry structure for rqe completion */
 375 struct lpfc_rcqe {
 376         uint32_t word0;
 377 #define lpfc_rcqe_bindex_SHIFT          16
 378 #define lpfc_rcqe_bindex_MASK           0x0000FFF
 379 #define lpfc_rcqe_bindex_WORD           word0
 380 #define lpfc_rcqe_status_SHIFT          8
 381 #define lpfc_rcqe_status_MASK           0x000000FF
 382 #define lpfc_rcqe_status_WORD           word0
 383 #define FC_STATUS_RQ_SUCCESS            0x10 /* Async receive successful */
 384 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED   0x11 /* payload truncated */
 385 #define FC_STATUS_INSUFF_BUF_NEED_BUF   0x12 /* Insufficient buffers */
 386 #define FC_STATUS_INSUFF_BUF_FRM_DISC   0x13 /* Frame Discard */
 387         uint32_t reserved1;
 388         uint32_t word2;
 389 #define lpfc_rcqe_length_SHIFT          16
 390 #define lpfc_rcqe_length_MASK           0x0000FFFF
 391 #define lpfc_rcqe_length_WORD           word2
 392 #define lpfc_rcqe_rq_id_SHIFT           6
 393 #define lpfc_rcqe_rq_id_MASK            0x000003FF
 394 #define lpfc_rcqe_rq_id_WORD            word2
 395 #define lpfc_rcqe_fcf_id_SHIFT          0
 396 #define lpfc_rcqe_fcf_id_MASK           0x0000003F
 397 #define lpfc_rcqe_fcf_id_WORD           word2
 398         uint32_t word3;
 399 #define lpfc_rcqe_valid_SHIFT           lpfc_cqe_valid_SHIFT
 400 #define lpfc_rcqe_valid_MASK            lpfc_cqe_valid_MASK
 401 #define lpfc_rcqe_valid_WORD            lpfc_cqe_valid_WORD
 402 #define lpfc_rcqe_port_SHIFT            30
 403 #define lpfc_rcqe_port_MASK             0x00000001
 404 #define lpfc_rcqe_port_WORD             word3
 405 #define lpfc_rcqe_hdr_length_SHIFT      24
 406 #define lpfc_rcqe_hdr_length_MASK       0x0000001F
 407 #define lpfc_rcqe_hdr_length_WORD       word3
 408 #define lpfc_rcqe_code_SHIFT            lpfc_cqe_code_SHIFT
 409 #define lpfc_rcqe_code_MASK             lpfc_cqe_code_MASK
 410 #define lpfc_rcqe_code_WORD             lpfc_cqe_code_WORD
 411 #define lpfc_rcqe_eof_SHIFT             8
 412 #define lpfc_rcqe_eof_MASK              0x000000FF
 413 #define lpfc_rcqe_eof_WORD              word3
 414 #define FCOE_EOFn       0x41
 415 #define FCOE_EOFt       0x42
 416 #define FCOE_EOFni      0x49
 417 #define FCOE_EOFa       0x50
 418 #define lpfc_rcqe_sof_SHIFT             0
 419 #define lpfc_rcqe_sof_MASK              0x000000FF
 420 #define lpfc_rcqe_sof_WORD              word3
 421 #define FCOE_SOFi2      0x2d
 422 #define FCOE_SOFi3      0x2e
 423 #define FCOE_SOFn2      0x35
 424 #define FCOE_SOFn3      0x36
 425 };
 426
 427 struct lpfc_wqe_generic{
 428         struct ulp_bde64 bde;
 429         uint32_t word3;
 430         uint32_t word4;
 431         uint32_t word5;
 432         uint32_t word6;
 433 #define lpfc_wqe_gen_context_SHIFT      16
 434 #define lpfc_wqe_gen_context_MASK       0x0000FFFF
 435 #define lpfc_wqe_gen_context_WORD       word6
 436 #define lpfc_wqe_gen_xri_SHIFT          0
 437 #define lpfc_wqe_gen_xri_MASK           0x0000FFFF
 438 #define lpfc_wqe_gen_xri_WORD           word6
 439         uint32_t word7;
 440 #define lpfc_wqe_gen_lnk_SHIFT          23
 441 #define lpfc_wqe_gen_lnk_MASK           0x00000001
 442 #define lpfc_wqe_gen_lnk_WORD           word7
 443 #define lpfc_wqe_gen_erp_SHIFT          22
 444 #define lpfc_wqe_gen_erp_MASK           0x00000001
 445 #define lpfc_wqe_gen_erp_WORD           word7
 446 #define lpfc_wqe_gen_pu_SHIFT           20
 447 #define lpfc_wqe_gen_pu_MASK            0x00000003
 448 #define lpfc_wqe_gen_pu_WORD            word7
 449 #define lpfc_wqe_gen_class_SHIFT        16
 450 #define lpfc_wqe_gen_class_MASK         0x00000007
 451 #define lpfc_wqe_gen_class_WORD         word7
 452 #define lpfc_wqe_gen_command_SHIFT      8
 453 #define lpfc_wqe_gen_command_MASK       0x000000FF
 454 #define lpfc_wqe_gen_command_WORD       word7
 455 #define lpfc_wqe_gen_status_SHIFT       4
 456 #define lpfc_wqe_gen_status_MASK        0x0000000F
 457 #define lpfc_wqe_gen_status_WORD        word7
 458 #define lpfc_wqe_gen_ct_SHIFT           2
 459 #define lpfc_wqe_gen_ct_MASK            0x00000003
 460 #define lpfc_wqe_gen_ct_WORD            word7
 461         uint32_t abort_tag;
 462         uint32_t word9;
 463 #define lpfc_wqe_gen_request_tag_SHIFT  0
 464 #define lpfc_wqe_gen_request_tag_MASK   0x0000FFFF
 465 #define lpfc_wqe_gen_request_tag_WORD   word9
 466         uint32_t word10;
 467 #define lpfc_wqe_gen_ccp_SHIFT          24
 468 #define lpfc_wqe_gen_ccp_MASK           0x000000FF
 469 #define lpfc_wqe_gen_ccp_WORD           word10
 470 #define lpfc_wqe_gen_ccpe_SHIFT         23
 471 #define lpfc_wqe_gen_ccpe_MASK          0x00000001
 472 #define lpfc_wqe_gen_ccpe_WORD          word10
 473 #define lpfc_wqe_gen_pv_SHIFT           19
 474 #define lpfc_wqe_gen_pv_MASK            0x00000001
 475 #define lpfc_wqe_gen_pv_WORD            word10
 476 #define lpfc_wqe_gen_pri_SHIFT          16
 477 #define lpfc_wqe_gen_pri_MASK           0x00000007
 478 #define lpfc_wqe_gen_pri_WORD           word10
 479         uint32_t word11;
 480 #define lpfc_wqe_gen_cq_id_SHIFT        16
 481 #define lpfc_wqe_gen_cq_id_MASK         0x0000FFFF
 482 #define lpfc_wqe_gen_cq_id_WORD         word11
 483 #define LPFC_WQE_CQ_ID_DEFAULT  0xffff
 484 #define lpfc_wqe_gen_wqec_SHIFT         7
 485 #define lpfc_wqe_gen_wqec_MASK          0x00000001
 486 #define lpfc_wqe_gen_wqec_WORD          word11
 487 #define ELS_ID_FLOGI 3
 488 #define ELS_ID_FDISC 2
 489 #define ELS_ID_LOGO  1
 490 #define ELS_ID_DEFAULT 0
 491 #define lpfc_wqe_gen_els_id_SHIFT       4
 492 #define lpfc_wqe_gen_els_id_MASK        0x00000003
 493 #define lpfc_wqe_gen_els_id_WORD        word11
 494 #define lpfc_wqe_gen_cmd_type_SHIFT     0
 495 #define lpfc_wqe_gen_cmd_type_MASK      0x0000000F
 496 #define lpfc_wqe_gen_cmd_type_WORD      word11
 497         uint32_t payload[4];
 498 };
 499
 500 struct lpfc_rqe {
 501         uint32_t address_hi;
 502         uint32_t address_lo;
 503 };
 504
 505 /* buffer descriptors */
 506 struct lpfc_bde4 {
 507         uint32_t addr_hi;
 508         uint32_t addr_lo;
 509         uint32_t word2;
 510 #define lpfc_bde4_last_SHIFT            31
 511 #define lpfc_bde4_last_MASK             0x00000001
 512 #define lpfc_bde4_last_WORD             word2
 513 #define lpfc_bde4_sge_offset_SHIFT      0
 514 #define lpfc_bde4_sge_offset_MASK       0x000003FF
 515 #define lpfc_bde4_sge_offset_WORD       word2
 516         uint32_t word3;
 517 #define lpfc_bde4_length_SHIFT          0
 518 #define lpfc_bde4_length_MASK           0x000000FF
 519 #define lpfc_bde4_length_WORD           word3
 520 };
 521
 522 struct lpfc_register {
 523         uint32_t word0;
 524 };
 525
 526 #define LPFC_UERR_STATUS_HI             0x00A4
 527 #define LPFC_UERR_STATUS_LO             0x00A0
 528 #define LPFC_UE_MASK_HI                 0x00AC
 529 #define LPFC_UE_MASK_LO                 0x00A8
 530 #define LPFC_SLI_INTF                   0x0058
 531
 532 /* BAR0 Registers */
 533 #define LPFC_HST_STATE                  0x00AC
 534 #define lpfc_hst_state_perr_SHIFT       31
 535 #define lpfc_hst_state_perr_MASK        0x1
 536 #define lpfc_hst_state_perr_WORD        word0
 537 #define lpfc_hst_state_sfi_SHIFT        30
 538 #define lpfc_hst_state_sfi_MASK         0x1
 539 #define lpfc_hst_state_sfi_WORD         word0
 540 #define lpfc_hst_state_nip_SHIFT        29
 541 #define lpfc_hst_state_nip_MASK         0x1
 542 #define lpfc_hst_state_nip_WORD         word0
 543 #define lpfc_hst_state_ipc_SHIFT        28
 544 #define lpfc_hst_state_ipc_MASK         0x1
 545 #define lpfc_hst_state_ipc_WORD         word0
 546 #define lpfc_hst_state_xrom_SHIFT       27
 547 #define lpfc_hst_state_xrom_MASK        0x1
 548 #define lpfc_hst_state_xrom_WORD        word0
 549 #define lpfc_hst_state_dl_SHIFT         26
 550 #define lpfc_hst_state_dl_MASK          0x1
 551 #define lpfc_hst_state_dl_WORD          word0
 552 #define lpfc_hst_state_port_status_SHIFT        0
 553 #define lpfc_hst_state_port_status_MASK         0xFFFF
 554 #define lpfc_hst_state_port_status_WORD         word0
 555
 556 #define LPFC_POST_STAGE_POWER_ON_RESET                  0x0000
 557 #define LPFC_POST_STAGE_AWAITING_HOST_RDY               0x0001
 558 #define LPFC_POST_STAGE_HOST_RDY                        0x0002
 559 #define LPFC_POST_STAGE_BE_RESET                        0x0003
 560 #define LPFC_POST_STAGE_SEEPROM_CS_START                0x0100
 561 #define LPFC_POST_STAGE_SEEPROM_CS_DONE                 0x0101
 562 #define LPFC_POST_STAGE_DDR_CONFIG_START                0x0200
 563 #define LPFC_POST_STAGE_DDR_CONFIG_DONE                 0x0201
 564 #define LPFC_POST_STAGE_DDR_CALIBRATE_START             0x0300
 565 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE              0x0301
 566 #define LPFC_POST_STAGE_DDR_TEST_START                  0x0400
 567 #define LPFC_POST_STAGE_DDR_TEST_DONE                   0x0401
 568 #define LPFC_POST_STAGE_REDBOOT_INIT_START              0x0600
 569 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE               0x0601
 570 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START             0x0700
 571 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE              0x0701
 572 #define LPFC_POST_STAGE_ARMFW_START                     0x0800
 573 #define LPFC_POST_STAGE_DHCP_QUERY_START                0x0900
 574 #define LPFC_POST_STAGE_DHCP_QUERY_DONE                 0x0901
 575 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START     0x0A00
 576 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE      0x0A01
 577 #define LPFC_POST_STAGE_RC_OPTION_SET                   0x0B00
 578 #define LPFC_POST_STAGE_SWITCH_LINK                     0x0B01
 579 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE               0x0B02
 580 #define LPFC_POST_STAGE_PERFROM_TFTP                    0x0B03
 581 #define LPFC_POST_STAGE_PARSE_XML                       0x0B04
 582 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE                  0x0B05
 583 #define LPFC_POST_STAGE_FLASH_IMAGE                     0x0B06
 584 #define LPFC_POST_STAGE_RC_DONE                         0x0B07
 585 #define LPFC_POST_STAGE_REBOOT_SYSTEM                   0x0B08
 586 #define LPFC_POST_STAGE_MAC_ADDRESS                     0x0C00
 587 #define LPFC_POST_STAGE_ARMFW_READY                     0xC000
 588 #define LPFC_POST_STAGE_ARMFW_UE                        0xF000
 589
 590 /* BAR1 Registers */
 591 #define LPFC_IMR_MASK_ALL       0xFFFFFFFF
 592 #define LPFC_ISCR_CLEAR_ALL     0xFFFFFFFF
 593
 594 #define LPFC_HST_ISR0           0x0C18
 595 #define LPFC_HST_ISR1           0x0C1C
 596 #define LPFC_HST_ISR2           0x0C20
 597 #define LPFC_HST_ISR3           0x0C24
 598 #define LPFC_HST_ISR4           0x0C28
 599
 600 #define LPFC_HST_IMR0           0x0C48
 601 #define LPFC_HST_IMR1           0x0C4C
 602 #define LPFC_HST_IMR2           0x0C50
 603 #define LPFC_HST_IMR3           0x0C54
 604 #define LPFC_HST_IMR4           0x0C58
 605
 606 #define LPFC_HST_ISCR0          0x0C78
 607 #define LPFC_HST_ISCR1          0x0C7C
 608 #define LPFC_HST_ISCR2          0x0C80
 609 #define LPFC_HST_ISCR3          0x0C84
 610 #define LPFC_HST_ISCR4          0x0C88
 611
 612 #define LPFC_SLI4_INTR0                 BIT0
 613 #define LPFC_SLI4_INTR1                 BIT1
 614 #define LPFC_SLI4_INTR2                 BIT2
 615 #define LPFC_SLI4_INTR3                 BIT3
 616 #define LPFC_SLI4_INTR4                 BIT4
 617 #define LPFC_SLI4_INTR5                 BIT5
 618 #define LPFC_SLI4_INTR6                 BIT6
 619 #define LPFC_SLI4_INTR7                 BIT7
 620 #define LPFC_SLI4_INTR8                 BIT8
 621 #define LPFC_SLI4_INTR9                 BIT9
 622 #define LPFC_SLI4_INTR10                BIT10
 623 #define LPFC_SLI4_INTR11                BIT11
 624 #define LPFC_SLI4_INTR12                BIT12
 625 #define LPFC_SLI4_INTR13                BIT13
 626 #define LPFC_SLI4_INTR14                BIT14
 627 #define LPFC_SLI4_INTR15                BIT15
 628 #define LPFC_SLI4_INTR16                BIT16
 629 #define LPFC_SLI4_INTR17                BIT17
 630 #define LPFC_SLI4_INTR18                BIT18
 631 #define LPFC_SLI4_INTR19                BIT19
 632 #define LPFC_SLI4_INTR20                BIT20
 633 #define LPFC_SLI4_INTR21                BIT21
 634 #define LPFC_SLI4_INTR22                BIT22
 635 #define LPFC_SLI4_INTR23                BIT23
 636 #define LPFC_SLI4_INTR24                BIT24
 637 #define LPFC_SLI4_INTR25                BIT25
 638 #define LPFC_SLI4_INTR26                BIT26
 639 #define LPFC_SLI4_INTR27                BIT27
 640 #define LPFC_SLI4_INTR28                BIT28
 641 #define LPFC_SLI4_INTR29                BIT29
 642 #define LPFC_SLI4_INTR30                BIT30
 643 #define LPFC_SLI4_INTR31                BIT31
 644
 645 /* BAR2 Registers */
 646 #define LPFC_RQ_DOORBELL                0x00A0
 647 #define lpfc_rq_doorbell_num_posted_SHIFT       16
 648 #define lpfc_rq_doorbell_num_posted_MASK        0x3FFF
 649 #define lpfc_rq_doorbell_num_posted_WORD        word0
 650 #define LPFC_RQ_POST_BATCH              8       /* RQEs to post at one time */
 651 #define lpfc_rq_doorbell_id_SHIFT               0
 652 #define lpfc_rq_doorbell_id_MASK                0x03FF
 653 #define lpfc_rq_doorbell_id_WORD                word0
 654
 655 #define LPFC_WQ_DOORBELL                0x0040
 656 #define lpfc_wq_doorbell_num_posted_SHIFT       24
 657 #define lpfc_wq_doorbell_num_posted_MASK        0x00FF
 658 #define lpfc_wq_doorbell_num_posted_WORD        word0
 659 #define lpfc_wq_doorbell_index_SHIFT            16
 660 #define lpfc_wq_doorbell_index_MASK             0x00FF
 661 #define lpfc_wq_doorbell_index_WORD             word0
 662 #define lpfc_wq_doorbell_id_SHIFT               0
 663 #define lpfc_wq_doorbell_id_MASK                0xFFFF
 664 #define lpfc_wq_doorbell_id_WORD                word0
 665
 666 #define LPFC_EQCQ_DOORBELL              0x0120
 667 #define lpfc_eqcq_doorbell_arm_SHIFT            29
 668 #define lpfc_eqcq_doorbell_arm_MASK             0x0001
 669 #define lpfc_eqcq_doorbell_arm_WORD             word0
 670 #define lpfc_eqcq_doorbell_num_released_SHIFT   16
 671 #define lpfc_eqcq_doorbell_num_released_MASK    0x1FFF
 672 #define lpfc_eqcq_doorbell_num_released_WORD    word0
 673 #define lpfc_eqcq_doorbell_qt_SHIFT             10
 674 #define lpfc_eqcq_doorbell_qt_MASK              0x0001
 675 #define lpfc_eqcq_doorbell_qt_WORD              word0
 676 #define LPFC_QUEUE_TYPE_COMPLETION      0
 677 #define LPFC_QUEUE_TYPE_EVENT           1
 678 #define lpfc_eqcq_doorbell_eqci_SHIFT           9
 679 #define lpfc_eqcq_doorbell_eqci_MASK            0x0001
 680 #define lpfc_eqcq_doorbell_eqci_WORD            word0
 681 #define lpfc_eqcq_doorbell_cqid_SHIFT           0
 682 #define lpfc_eqcq_doorbell_cqid_MASK            0x03FF
 683 #define lpfc_eqcq_doorbell_cqid_WORD            word0
 684 #define lpfc_eqcq_doorbell_eqid_SHIFT           0
 685 #define lpfc_eqcq_doorbell_eqid_MASK            0x01FF
 686 #define lpfc_eqcq_doorbell_eqid_WORD            word0
 687
 688 #define LPFC_BMBX                       0x0160
 689 #define lpfc_bmbx_addr_SHIFT            2
 690 #define lpfc_bmbx_addr_MASK             0x3FFFFFFF
 691 #define lpfc_bmbx_addr_WORD             word0
 692 #define lpfc_bmbx_hi_SHIFT              1
 693 #define lpfc_bmbx_hi_MASK               0x0001
 694 #define lpfc_bmbx_hi_WORD               word0
 695 #define lpfc_bmbx_rdy_SHIFT             0
 696 #define lpfc_bmbx_rdy_MASK              0x0001
 697 #define lpfc_bmbx_rdy_WORD              word0
 698
 699 #define LPFC_MQ_DOORBELL                        0x0140
 700 #define lpfc_mq_doorbell_num_posted_SHIFT       16
 701 #define lpfc_mq_doorbell_num_posted_MASK        0x3FFF
 702 #define lpfc_mq_doorbell_num_posted_WORD        word0
 703 #define lpfc_mq_doorbell_id_SHIFT               0
 704 #define lpfc_mq_doorbell_id_MASK                0x03FF
 705 #define lpfc_mq_doorbell_id_WORD                word0
 706
 707 struct lpfc_sli4_cfg_mhdr {
 708         uint32_t word1;
 709 #define lpfc_mbox_hdr_emb_SHIFT         0
 710 #define lpfc_mbox_hdr_emb_MASK          0x00000001
 711 #define lpfc_mbox_hdr_emb_WORD          word1
 712 #define lpfc_mbox_hdr_sge_cnt_SHIFT     3
 713 #define lpfc_mbox_hdr_sge_cnt_MASK      0x0000001F
 714 #define lpfc_mbox_hdr_sge_cnt_WORD      word1
 715         uint32_t payload_length;
 716         uint32_t tag_lo;
 717         uint32_t tag_hi;
 718         uint32_t reserved5;
 719 };
 720
 721 union lpfc_sli4_cfg_shdr {
 722         struct {
 723                 uint32_t word6;
 724 #define lpfc_mbox_hdr_opcode_SHIFT              0
 725 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 726 #define lpfc_mbox_hdr_opcode_WORD               word6
 727 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 728 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 729 #define lpfc_mbox_hdr_subsystem_WORD            word6
 730 #define lpfc_mbox_hdr_port_number_SHIFT         16
 731 #define lpfc_mbox_hdr_port_number_MASK          0x000000FF
 732 #define lpfc_mbox_hdr_port_number_WORD          word6
 733 #define lpfc_mbox_hdr_domain_SHIFT              24
 734 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 735 #define lpfc_mbox_hdr_domain_WORD               word6
 736                 uint32_t timeout;
 737                 uint32_t request_length;
 738                 uint32_t reserved9;
 739         } request;
 740         struct {
 741                 uint32_t word6;
 742 #define lpfc_mbox_hdr_opcode_SHIFT              0
 743 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 744 #define lpfc_mbox_hdr_opcode_WORD               word6
 745 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 746 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 747 #define lpfc_mbox_hdr_subsystem_WORD            word6
 748 #define lpfc_mbox_hdr_domain_SHIFT              24
 749 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 750 #define lpfc_mbox_hdr_domain_WORD               word6
 751                 uint32_t word7;
 752 #define lpfc_mbox_hdr_status_SHIFT              0
 753 #define lpfc_mbox_hdr_status_MASK               0x000000FF
 754 #define lpfc_mbox_hdr_status_WORD               word7
 755 #define lpfc_mbox_hdr_add_status_SHIFT          8
 756 #define lpfc_mbox_hdr_add_status_MASK           0x000000FF
 757 #define lpfc_mbox_hdr_add_status_WORD           word7
 758                 uint32_t response_length;
 759                 uint32_t actual_response_length;
 760         } response;
 761 };
 762
 763 /* Mailbox structures */
 764 struct mbox_header {
 765         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 766         union  lpfc_sli4_cfg_shdr cfg_shdr;
 767 };
 768
 769 /* Subsystem Definitions */
 770 #define LPFC_MBOX_SUBSYSTEM_COMMON      0x1
 771 #define LPFC_MBOX_SUBSYSTEM_FCOE        0xC
 772
 773 /* Device Specific Definitions */
 774
 775 /* The HOST ENDIAN defines are in Big Endian format. */
 776 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
 777 #define HOST_ENDIAN_HIGH_WORD1  0xFF7856FF
 778
 779 /* Common Opcodes */
 780 #define LPFC_MBOX_OPCODE_CQ_CREATE              0x0C
 781 #define LPFC_MBOX_OPCODE_EQ_CREATE              0x0D
 782 #define LPFC_MBOX_OPCODE_MQ_CREATE              0x15
 783 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES    0x20
 784 #define LPFC_MBOX_OPCODE_NOP                    0x21
 785 #define LPFC_MBOX_OPCODE_MQ_DESTROY             0x35
 786 #define LPFC_MBOX_OPCODE_CQ_DESTROY             0x36
 787 #define LPFC_MBOX_OPCODE_EQ_DESTROY             0x37
 788 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG           0x3A
 789 #define LPFC_MBOX_OPCODE_FUNCTION_RESET         0x3D
 790 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT          0x5A
 791
 792 /* FCoE Opcodes */
 793 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE                 0x01
 794 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY                0x02
 795 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES            0x03
 796 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES          0x04
 797 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE                 0x05
 798 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY                0x06
 799 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE            0x08
 800 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF                   0x09
 801 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF                0x0A
 802 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE         0x0B
 803 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF            0x10
 804
 805 /* Mailbox command structures */
 806 struct eq_context {
 807         uint32_t word0;
 808 #define lpfc_eq_context_size_SHIFT      31
 809 #define lpfc_eq_context_size_MASK       0x00000001
 810 #define lpfc_eq_context_size_WORD       word0
 811 #define LPFC_EQE_SIZE_4                 0x0
 812 #define LPFC_EQE_SIZE_16                0x1
 813 #define lpfc_eq_context_valid_SHIFT     29
 814 #define lpfc_eq_context_valid_MASK      0x00000001
 815 #define lpfc_eq_context_valid_WORD      word0
 816         uint32_t word1;
 817 #define lpfc_eq_context_count_SHIFT     26
 818 #define lpfc_eq_context_count_MASK      0x00000003
 819 #define lpfc_eq_context_count_WORD      word1
 820 #define LPFC_EQ_CNT_256         0x0
 821 #define LPFC_EQ_CNT_512         0x1
 822 #define LPFC_EQ_CNT_1024        0x2
 823 #define LPFC_EQ_CNT_2048        0x3
 824 #define LPFC_EQ_CNT_4096        0x4
 825         uint32_t word2;
 826 #define lpfc_eq_context_delay_multi_SHIFT       13
 827 #define lpfc_eq_context_delay_multi_MASK        0x000003FF
 828 #define lpfc_eq_context_delay_multi_WORD        word2
 829         uint32_t reserved3;
 830 };
 831
 832 struct sgl_page_pairs {
 833         uint32_t sgl_pg0_addr_lo;
 834         uint32_t sgl_pg0_addr_hi;
 835         uint32_t sgl_pg1_addr_lo;
 836         uint32_t sgl_pg1_addr_hi;
 837 };
 838
 839 struct lpfc_mbx_post_sgl_pages {
 840         struct mbox_header header;
 841         uint32_t word0;
 842 #define lpfc_post_sgl_pages_xri_SHIFT   0
 843 #define lpfc_post_sgl_pages_xri_MASK    0x0000FFFF
 844 #define lpfc_post_sgl_pages_xri_WORD    word0
 845 #define lpfc_post_sgl_pages_xricnt_SHIFT        16
 846 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
 847 #define lpfc_post_sgl_pages_xricnt_WORD word0
 848         struct sgl_page_pairs  sgl_pg_pairs[1];
 849 };
 850
 851 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
 852 struct lpfc_mbx_post_uembed_sgl_page1 {
 853         union  lpfc_sli4_cfg_shdr cfg_shdr;
 854         uint32_t word0;
 855         struct sgl_page_pairs sgl_pg_pairs;
 856 };
 857
 858 struct lpfc_mbx_sge {
 859         uint32_t pa_lo;
 860         uint32_t pa_hi;
 861         uint32_t length;
 862 };
 863
 864 struct lpfc_mbx_nembed_cmd {
 865         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 866 #define LPFC_SLI4_MBX_SGE_MAX_PAGES     19
 867         struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
 868 };
 869
 870 struct lpfc_mbx_nembed_sge_virt {
 871         void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
 872 };
 873
 874 struct lpfc_mbx_eq_create {
 875         struct mbox_header header;
 876         union {
 877                 struct {
 878                         uint32_t word0;
 879 #define lpfc_mbx_eq_create_num_pages_SHIFT      0
 880 #define lpfc_mbx_eq_create_num_pages_MASK       0x0000FFFF
 881 #define lpfc_mbx_eq_create_num_pages_WORD       word0
 882                         struct eq_context context;
 883                         struct dma_address page[LPFC_MAX_EQ_PAGE];
 884                 } request;
 885                 struct {
 886                         uint32_t word0;
 887 #define lpfc_mbx_eq_create_q_id_SHIFT   0
 888 #define lpfc_mbx_eq_create_q_id_MASK    0x0000FFFF
 889 #define lpfc_mbx_eq_create_q_id_WORD    word0
 890                 } response;
 891         } u;
 892 };
 893
 894 struct lpfc_mbx_eq_destroy {
 895         struct mbox_header header;
 896         union {
 897                 struct {
 898                         uint32_t word0;
 899 #define lpfc_mbx_eq_destroy_q_id_SHIFT  0
 900 #define lpfc_mbx_eq_destroy_q_id_MASK   0x0000FFFF
 901 #define lpfc_mbx_eq_destroy_q_id_WORD   word0
 902                 } request;
 903                 struct {
 904                         uint32_t word0;
 905                 } response;
 906         } u;
 907 };
 908
 909 struct lpfc_mbx_nop {
 910         struct mbox_header header;
 911         uint32_t context[2];
 912 };
 913
 914 struct cq_context {
 915         uint32_t word0;
 916 #define lpfc_cq_context_event_SHIFT     31
 917 #define lpfc_cq_context_event_MASK      0x00000001
 918 #define lpfc_cq_context_event_WORD      word0
 919 #define lpfc_cq_context_valid_SHIFT     29
 920 #define lpfc_cq_context_valid_MASK      0x00000001
 921 #define lpfc_cq_context_valid_WORD      word0
 922 #define lpfc_cq_context_count_SHIFT     27
 923 #define lpfc_cq_context_count_MASK      0x00000003
 924 #define lpfc_cq_context_count_WORD      word0
 925 #define LPFC_CQ_CNT_256         0x0
 926 #define LPFC_CQ_CNT_512         0x1
 927 #define LPFC_CQ_CNT_1024        0x2
 928         uint32_t word1;
 929 #define lpfc_cq_eq_id_SHIFT             22
 930 #define lpfc_cq_eq_id_MASK              0x000000FF
 931 #define lpfc_cq_eq_id_WORD              word1
 932         uint32_t reserved0;
 933         uint32_t reserved1;
 934 };
 935
 936 struct lpfc_mbx_cq_create {
 937         struct mbox_header header;
 938         union {
 939                 struct {
 940                         uint32_t word0;
 941 #define lpfc_mbx_cq_create_num_pages_SHIFT      0
 942 #define lpfc_mbx_cq_create_num_pages_MASK       0x0000FFFF
 943 #define lpfc_mbx_cq_create_num_pages_WORD       word0
 944                         struct cq_context context;
 945                         struct dma_address page[LPFC_MAX_CQ_PAGE];
 946                 } request;
 947                 struct {
 948                         uint32_t word0;
 949 #define lpfc_mbx_cq_create_q_id_SHIFT   0
 950 #define lpfc_mbx_cq_create_q_id_MASK    0x0000FFFF
 951 #define lpfc_mbx_cq_create_q_id_WORD    word0
 952                 } response;
 953         } u;
 954 };
 955
 956 struct lpfc_mbx_cq_destroy {
 957         struct mbox_header header;
 958         union {
 959                 struct {
 960                         uint32_t word0;
 961 #define lpfc_mbx_cq_destroy_q_id_SHIFT  0
 962 #define lpfc_mbx_cq_destroy_q_id_MASK   0x0000FFFF
 963 #define lpfc_mbx_cq_destroy_q_id_WORD   word0
 964                 } request;
 965                 struct {
 966                         uint32_t word0;
 967                 } response;
 968         } u;
 969 };
 970
 971 struct wq_context {
 972         uint32_t reserved0;
 973         uint32_t reserved1;
 974         uint32_t reserved2;
 975         uint32_t reserved3;
 976 };
 977
 978 struct lpfc_mbx_wq_create {
 979         struct mbox_header header;
 980         union {
 981                 struct {
 982                         uint32_t word0;
 983 #define lpfc_mbx_wq_create_num_pages_SHIFT      0
 984 #define lpfc_mbx_wq_create_num_pages_MASK       0x0000FFFF
 985 #define lpfc_mbx_wq_create_num_pages_WORD       word0
 986 #define lpfc_mbx_wq_create_cq_id_SHIFT          16
 987 #define lpfc_mbx_wq_create_cq_id_MASK           0x0000FFFF
 988 #define lpfc_mbx_wq_create_cq_id_WORD           word0
 989                         struct dma_address page[LPFC_MAX_WQ_PAGE];
 990                 } request;
 991                 struct {
 992                         uint32_t word0;
 993 #define lpfc_mbx_wq_create_q_id_SHIFT   0
 994 #define lpfc_mbx_wq_create_q_id_MASK    0x0000FFFF
 995 #define lpfc_mbx_wq_create_q_id_WORD    word0
 996                 } response;
 997         } u;
 998 };
 999
1000 struct lpfc_mbx_wq_destroy {
1001         struct mbox_header header;
1002         union {
1003                 struct {
1004                         uint32_t word0;
1005 #define lpfc_mbx_wq_destroy_q_id_SHIFT  0
1006 #define lpfc_mbx_wq_destroy_q_id_MASK   0x0000FFFF
1007 #define lpfc_mbx_wq_destroy_q_id_WORD   word0
1008                 } request;
1009                 struct {
1010                         uint32_t word0;
1011                 } response;
1012         } u;
1013 };
1014
1015 #define LPFC_HDR_BUF_SIZE 128
1016 #define LPFC_DATA_BUF_SIZE 2048
1017 struct rq_context {
1018         uint32_t word0;
1019 #define lpfc_rq_context_rq_size_SHIFT   16
1020 #define lpfc_rq_context_rq_size_MASK    0x0000000F
1021 #define lpfc_rq_context_rq_size_WORD    word0
1022 #define LPFC_RQ_RING_SIZE_512           9       /* 512 entries */
1023 #define LPFC_RQ_RING_SIZE_1024          10      /* 1024 entries */
1024 #define LPFC_RQ_RING_SIZE_2048          11      /* 2048 entries */
1025 #define LPFC_RQ_RING_SIZE_4096          12      /* 4096 entries */
1026         uint32_t reserved1;
1027         uint32_t word2;
1028 #define lpfc_rq_context_cq_id_SHIFT     16
1029 #define lpfc_rq_context_cq_id_MASK      0x000003FF
1030 #define lpfc_rq_context_cq_id_WORD      word2
1031 #define lpfc_rq_context_buf_size_SHIFT  0
1032 #define lpfc_rq_context_buf_size_MASK   0x0000FFFF
1033 #define lpfc_rq_context_buf_size_WORD   word2
1034         uint32_t reserved3;
1035 };
1036
1037 struct lpfc_mbx_rq_create {
1038         struct mbox_header header;
1039         union {
1040                 struct {
1041                         uint32_t word0;
1042 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1043 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1044 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1045                         struct rq_context context;
1046                         struct dma_address page[LPFC_MAX_WQ_PAGE];
1047                 } request;
1048                 struct {
1049                         uint32_t word0;
1050 #define lpfc_mbx_rq_create_q_id_SHIFT   0
1051 #define lpfc_mbx_rq_create_q_id_MASK    0x0000FFFF
1052 #define lpfc_mbx_rq_create_q_id_WORD    word0
1053                 } response;
1054         } u;
1055 };
1056
1057 struct lpfc_mbx_rq_destroy {
1058         struct mbox_header header;
1059         union {
1060                 struct {
1061                         uint32_t word0;
1062 #define lpfc_mbx_rq_destroy_q_id_SHIFT  0
1063 #define lpfc_mbx_rq_destroy_q_id_MASK   0x0000FFFF
1064 #define lpfc_mbx_rq_destroy_q_id_WORD   word0
1065                 } request;
1066                 struct {
1067                         uint32_t word0;
1068                 } response;
1069         } u;
1070 };
1071
1072 struct mq_context {
1073         uint32_t word0;
1074 #define lpfc_mq_context_cq_id_SHIFT     22
1075 #define lpfc_mq_context_cq_id_MASK      0x000003FF
1076 #define lpfc_mq_context_cq_id_WORD      word0
1077 #define lpfc_mq_context_count_SHIFT     16
1078 #define lpfc_mq_context_count_MASK      0x0000000F
1079 #define lpfc_mq_context_count_WORD      word0
1080 #define LPFC_MQ_CNT_16          0x5
1081 #define LPFC_MQ_CNT_32          0x6
1082 #define LPFC_MQ_CNT_64          0x7
1083 #define LPFC_MQ_CNT_128         0x8
1084         uint32_t word1;
1085 #define lpfc_mq_context_valid_SHIFT     31
1086 #define lpfc_mq_context_valid_MASK      0x00000001
1087 #define lpfc_mq_context_valid_WORD      word1
1088         uint32_t reserved2;
1089         uint32_t reserved3;
1090 };
1091
1092 struct lpfc_mbx_mq_create {
1093         struct mbox_header header;
1094         union {
1095                 struct {
1096                         uint32_t word0;
1097 #define lpfc_mbx_mq_create_num_pages_SHIFT      0
1098 #define lpfc_mbx_mq_create_num_pages_MASK       0x0000FFFF
1099 #define lpfc_mbx_mq_create_num_pages_WORD       word0
1100                         struct mq_context context;
1101                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1102                 } request;
1103                 struct {
1104                         uint32_t word0;
1105 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1106 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1107 #define lpfc_mbx_mq_create_q_id_WORD    word0
1108                 } response;
1109         } u;
1110 };
1111
1112 struct lpfc_mbx_mq_create_ext {
1113         struct mbox_header header;
1114         union {
1115                 struct {
1116                         uint32_t word0;
1117 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT          0
1118 #define lpfc_mbx_mq_create_ext_num_pages_MASK           0x0000FFFF
1119 #define lpfc_mbx_mq_create_ext_num_pages_WORD           word0
1120                         uint32_t async_evt_bmap;
1121 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT     LPFC_TRAILER_CODE_LINK
1122 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK      0x00000001
1123 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD      async_evt_bmap
1124 #define lpfc_mbx_mq_create_ext_async_evt_fcfste_SHIFT   LPFC_TRAILER_CODE_FCOE
1125 #define lpfc_mbx_mq_create_ext_async_evt_fcfste_MASK    0x00000001
1126 #define lpfc_mbx_mq_create_ext_async_evt_fcfste_WORD    async_evt_bmap
1127 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT   LPFC_TRAILER_CODE_GRP5
1128 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK    0x00000001
1129 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD    async_evt_bmap
1130                         struct mq_context context;
1131                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1132                 } request;
1133                 struct {
1134                         uint32_t word0;
1135 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1136 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1137 #define lpfc_mbx_mq_create_q_id_WORD    word0
1138                 } response;
1139         } u;
1140 #define LPFC_ASYNC_EVENT_LINK_STATE     0x2
1141 #define LPFC_ASYNC_EVENT_FCF_STATE      0x4
1142 #define LPFC_ASYNC_EVENT_GROUP5         0x20
1143 };
1144
1145 struct lpfc_mbx_mq_destroy {
1146         struct mbox_header header;
1147         union {
1148                 struct {
1149                         uint32_t word0;
1150 #define lpfc_mbx_mq_destroy_q_id_SHIFT  0
1151 #define lpfc_mbx_mq_destroy_q_id_MASK   0x0000FFFF
1152 #define lpfc_mbx_mq_destroy_q_id_WORD   word0
1153                 } request;
1154                 struct {
1155                         uint32_t word0;
1156                 } response;
1157         } u;
1158 };
1159
1160 struct lpfc_mbx_post_hdr_tmpl {
1161         struct mbox_header header;
1162         uint32_t word10;
1163 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
1164 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
1165 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
1166 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
1167 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
1168 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
1169         uint32_t rpi_paddr_lo;
1170         uint32_t rpi_paddr_hi;
1171 };
1172
1173 struct sli4_sge {       /* SLI-4 */
1174         uint32_t addr_hi;
1175         uint32_t addr_lo;
1176
1177         uint32_t word2;
1178 #define lpfc_sli4_sge_offset_SHIFT      0 /* Offset of buffer - Not used*/
1179 #define lpfc_sli4_sge_offset_MASK       0x00FFFFFF
1180 #define lpfc_sli4_sge_offset_WORD       word2
1181 #define lpfc_sli4_sge_last_SHIFT        31 /* Last SEG in the SGL sets
1182                                                 this  flag !! */
1183 #define lpfc_sli4_sge_last_MASK         0x00000001
1184 #define lpfc_sli4_sge_last_WORD         word2
1185         uint32_t sge_len;
1186 };
1187
1188 struct fcf_record {
1189         uint32_t max_rcv_size;
1190         uint32_t fka_adv_period;
1191         uint32_t fip_priority;
1192         uint32_t word3;
1193 #define lpfc_fcf_record_mac_0_SHIFT             0
1194 #define lpfc_fcf_record_mac_0_MASK              0x000000FF
1195 #define lpfc_fcf_record_mac_0_WORD              word3
1196 #define lpfc_fcf_record_mac_1_SHIFT             8
1197 #define lpfc_fcf_record_mac_1_MASK              0x000000FF
1198 #define lpfc_fcf_record_mac_1_WORD              word3
1199 #define lpfc_fcf_record_mac_2_SHIFT             16
1200 #define lpfc_fcf_record_mac_2_MASK              0x000000FF
1201 #define lpfc_fcf_record_mac_2_WORD              word3
1202 #define lpfc_fcf_record_mac_3_SHIFT             24
1203 #define lpfc_fcf_record_mac_3_MASK              0x000000FF
1204 #define lpfc_fcf_record_mac_3_WORD              word3
1205         uint32_t word4;
1206 #define lpfc_fcf_record_mac_4_SHIFT             0
1207 #define lpfc_fcf_record_mac_4_MASK              0x000000FF
1208 #define lpfc_fcf_record_mac_4_WORD              word4
1209 #define lpfc_fcf_record_mac_5_SHIFT             8
1210 #define lpfc_fcf_record_mac_5_MASK              0x000000FF
1211 #define lpfc_fcf_record_mac_5_WORD              word4
1212 #define lpfc_fcf_record_fcf_avail_SHIFT         16
1213 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
1214 #define lpfc_fcf_record_fcf_avail_WORD          word4
1215 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
1216 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
1217 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
1218 #define LPFC_FCF_FPMA           1       /* Fabric Provided MAC Address */
1219 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
1220         uint32_t word5;
1221 #define lpfc_fcf_record_fab_name_0_SHIFT        0
1222 #define lpfc_fcf_record_fab_name_0_MASK         0x000000FF
1223 #define lpfc_fcf_record_fab_name_0_WORD         word5
1224 #define lpfc_fcf_record_fab_name_1_SHIFT        8
1225 #define lpfc_fcf_record_fab_name_1_MASK         0x000000FF
1226 #define lpfc_fcf_record_fab_name_1_WORD         word5
1227 #define lpfc_fcf_record_fab_name_2_SHIFT        16
1228 #define lpfc_fcf_record_fab_name_2_MASK         0x000000FF
1229 #define lpfc_fcf_record_fab_name_2_WORD         word5
1230 #define lpfc_fcf_record_fab_name_3_SHIFT        24
1231 #define lpfc_fcf_record_fab_name_3_MASK         0x000000FF
1232 #define lpfc_fcf_record_fab_name_3_WORD         word5
1233         uint32_t word6;
1234 #define lpfc_fcf_record_fab_name_4_SHIFT        0
1235 #define lpfc_fcf_record_fab_name_4_MASK         0x000000FF
1236 #define lpfc_fcf_record_fab_name_4_WORD         word6
1237 #define lpfc_fcf_record_fab_name_5_SHIFT        8
1238 #define lpfc_fcf_record_fab_name_5_MASK         0x000000FF
1239 #define lpfc_fcf_record_fab_name_5_WORD         word6
1240 #define lpfc_fcf_record_fab_name_6_SHIFT        16
1241 #define lpfc_fcf_record_fab_name_6_MASK         0x000000FF
1242 #define lpfc_fcf_record_fab_name_6_WORD         word6
1243 #define lpfc_fcf_record_fab_name_7_SHIFT        24
1244 #define lpfc_fcf_record_fab_name_7_MASK         0x000000FF
1245 #define lpfc_fcf_record_fab_name_7_WORD         word6
1246         uint32_t word7;
1247 #define lpfc_fcf_record_fc_map_0_SHIFT          0
1248 #define lpfc_fcf_record_fc_map_0_MASK           0x000000FF
1249 #define lpfc_fcf_record_fc_map_0_WORD           word7
1250 #define lpfc_fcf_record_fc_map_1_SHIFT          8
1251 #define lpfc_fcf_record_fc_map_1_MASK           0x000000FF
1252 #define lpfc_fcf_record_fc_map_1_WORD           word7
1253 #define lpfc_fcf_record_fc_map_2_SHIFT          16
1254 #define lpfc_fcf_record_fc_map_2_MASK           0x000000FF
1255 #define lpfc_fcf_record_fc_map_2_WORD           word7
1256 #define lpfc_fcf_record_fcf_valid_SHIFT         24
1257 #define lpfc_fcf_record_fcf_valid_MASK          0x000000FF
1258 #define lpfc_fcf_record_fcf_valid_WORD          word7
1259         uint32_t word8;
1260 #define lpfc_fcf_record_fcf_index_SHIFT         0
1261 #define lpfc_fcf_record_fcf_index_MASK          0x0000FFFF
1262 #define lpfc_fcf_record_fcf_index_WORD          word8
1263 #define lpfc_fcf_record_fcf_state_SHIFT         16
1264 #define lpfc_fcf_record_fcf_state_MASK          0x0000FFFF
1265 #define lpfc_fcf_record_fcf_state_WORD          word8
1266         uint8_t vlan_bitmap[512];
1267         uint32_t word137;
1268 #define lpfc_fcf_record_switch_name_0_SHIFT     0
1269 #define lpfc_fcf_record_switch_name_0_MASK      0x000000FF
1270 #define lpfc_fcf_record_switch_name_0_WORD      word137
1271 #define lpfc_fcf_record_switch_name_1_SHIFT     8
1272 #define lpfc_fcf_record_switch_name_1_MASK      0x000000FF
1273 #define lpfc_fcf_record_switch_name_1_WORD      word137
1274 #define lpfc_fcf_record_switch_name_2_SHIFT     16
1275 #define lpfc_fcf_record_switch_name_2_MASK      0x000000FF
1276 #define lpfc_fcf_record_switch_name_2_WORD      word137
1277 #define lpfc_fcf_record_switch_name_3_SHIFT     24
1278 #define lpfc_fcf_record_switch_name_3_MASK      0x000000FF
1279 #define lpfc_fcf_record_switch_name_3_WORD      word137
1280         uint32_t word138;
1281 #define lpfc_fcf_record_switch_name_4_SHIFT     0
1282 #define lpfc_fcf_record_switch_name_4_MASK      0x000000FF
1283 #define lpfc_fcf_record_switch_name_4_WORD      word138
1284 #define lpfc_fcf_record_switch_name_5_SHIFT     8
1285 #define lpfc_fcf_record_switch_name_5_MASK      0x000000FF
1286 #define lpfc_fcf_record_switch_name_5_WORD      word138
1287 #define lpfc_fcf_record_switch_name_6_SHIFT     16
1288 #define lpfc_fcf_record_switch_name_6_MASK      0x000000FF
1289 #define lpfc_fcf_record_switch_name_6_WORD      word138
1290 #define lpfc_fcf_record_switch_name_7_SHIFT     24
1291 #define lpfc_fcf_record_switch_name_7_MASK      0x000000FF
1292 #define lpfc_fcf_record_switch_name_7_WORD      word138
1293 };
1294
1295 struct lpfc_mbx_read_fcf_tbl {
1296         union lpfc_sli4_cfg_shdr cfg_shdr;
1297         union {
1298                 struct {
1299                         uint32_t word10;
1300 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT        0
1301 #define lpfc_mbx_read_fcf_tbl_indx_MASK         0x0000FFFF
1302 #define lpfc_mbx_read_fcf_tbl_indx_WORD         word10
1303                 } request;
1304                 struct {
1305                         uint32_t eventag;
1306                 } response;
1307         } u;
1308         uint32_t word11;
1309 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT   0
1310 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK    0x0000FFFF
1311 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD    word11
1312 };
1313
1314 struct lpfc_mbx_add_fcf_tbl_entry {
1315         union lpfc_sli4_cfg_shdr cfg_shdr;
1316         uint32_t word10;
1317 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
1318 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
1319 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
1320         struct lpfc_mbx_sge fcf_sge;
1321 };
1322
1323 struct lpfc_mbx_del_fcf_tbl_entry {
1324         struct mbox_header header;
1325         uint32_t word10;
1326 #define lpfc_mbx_del_fcf_tbl_count_SHIFT        0
1327 #define lpfc_mbx_del_fcf_tbl_count_MASK         0x0000FFFF
1328 #define lpfc_mbx_del_fcf_tbl_count_WORD         word10
1329 #define lpfc_mbx_del_fcf_tbl_index_SHIFT        16
1330 #define lpfc_mbx_del_fcf_tbl_index_MASK         0x0000FFFF
1331 #define lpfc_mbx_del_fcf_tbl_index_WORD         word10
1332 };
1333
1334 struct lpfc_mbx_redisc_fcf_tbl {
1335         struct mbox_header header;
1336         uint32_t word10;
1337 #define lpfc_mbx_redisc_fcf_count_SHIFT         0
1338 #define lpfc_mbx_redisc_fcf_count_MASK          0x0000FFFF
1339 #define lpfc_mbx_redisc_fcf_count_WORD          word10
1340         uint32_t resvd;
1341         uint32_t word12;
1342 #define lpfc_mbx_redisc_fcf_index_SHIFT         0
1343 #define lpfc_mbx_redisc_fcf_index_MASK          0x0000FFFF
1344 #define lpfc_mbx_redisc_fcf_index_WORD          word12
1345 };
1346
1347 struct lpfc_mbx_query_fw_cfg {
1348         struct mbox_header header;
1349         uint32_t config_number;
1350         uint32_t asic_rev;
1351         uint32_t phys_port;
1352         uint32_t function_mode;
1353 /* firmware Function Mode */
1354 #define lpfc_function_mode_toe_SHIFT            0
1355 #define lpfc_function_mode_toe_MASK             0x00000001
1356 #define lpfc_function_mode_toe_WORD             function_mode
1357 #define lpfc_function_mode_nic_SHIFT            1
1358 #define lpfc_function_mode_nic_MASK             0x00000001
1359 #define lpfc_function_mode_nic_WORD             function_mode
1360 #define lpfc_function_mode_rdma_SHIFT           2
1361 #define lpfc_function_mode_rdma_MASK            0x00000001
1362 #define lpfc_function_mode_rdma_WORD            function_mode
1363 #define lpfc_function_mode_vm_SHIFT             3
1364 #define lpfc_function_mode_vm_MASK              0x00000001
1365 #define lpfc_function_mode_vm_WORD              function_mode
1366 #define lpfc_function_mode_iscsi_i_SHIFT        4
1367 #define lpfc_function_mode_iscsi_i_MASK         0x00000001
1368 #define lpfc_function_mode_iscsi_i_WORD         function_mode
1369 #define lpfc_function_mode_iscsi_t_SHIFT        5
1370 #define lpfc_function_mode_iscsi_t_MASK         0x00000001
1371 #define lpfc_function_mode_iscsi_t_WORD         function_mode
1372 #define lpfc_function_mode_fcoe_i_SHIFT         6
1373 #define lpfc_function_mode_fcoe_i_MASK          0x00000001
1374 #define lpfc_function_mode_fcoe_i_WORD          function_mode
1375 #define lpfc_function_mode_fcoe_t_SHIFT         7
1376 #define lpfc_function_mode_fcoe_t_MASK          0x00000001
1377 #define lpfc_function_mode_fcoe_t_WORD          function_mode
1378 #define lpfc_function_mode_dal_SHIFT            8
1379 #define lpfc_function_mode_dal_MASK             0x00000001
1380 #define lpfc_function_mode_dal_WORD             function_mode
1381 #define lpfc_function_mode_lro_SHIFT            9
1382 #define lpfc_function_mode_lro_MASK             0x00000001
1383 #define lpfc_function_mode_lro_WORD             function_mode9
1384 #define lpfc_function_mode_flex10_SHIFT         10
1385 #define lpfc_function_mode_flex10_MASK          0x00000001
1386 #define lpfc_function_mode_flex10_WORD          function_mode
1387 #define lpfc_function_mode_ncsi_SHIFT           11
1388 #define lpfc_function_mode_ncsi_MASK            0x00000001
1389 #define lpfc_function_mode_ncsi_WORD            function_mode
1390 };
1391
1392 /* Status field for embedded SLI_CONFIG mailbox command */
1393 #define STATUS_SUCCESS                                  0x0
1394 #define STATUS_FAILED                                   0x1
1395 #define STATUS_ILLEGAL_REQUEST                          0x2
1396 #define STATUS_ILLEGAL_FIELD                            0x3
1397 #define STATUS_INSUFFICIENT_BUFFER                      0x4
1398 #define STATUS_UNAUTHORIZED_REQUEST                     0x5
1399 #define STATUS_FLASHROM_SAVE_FAILED                     0x17
1400 #define STATUS_FLASHROM_RESTORE_FAILED                  0x18
1401 #define STATUS_ICCBINDEX_ALLOC_FAILED                   0x1a
1402 #define STATUS_IOCTLHANDLE_ALLOC_FAILED                 0x1b
1403 #define STATUS_INVALID_PHY_ADDR_FROM_OSM                0x1c
1404 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM            0x1d
1405 #define STATUS_ASSERT_FAILED                            0x1e
1406 #define STATUS_INVALID_SESSION                          0x1f
1407 #define STATUS_INVALID_CONNECTION                       0x20
1408 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT               0x21
1409 #define STATUS_BTL_NO_FREE_SLOT_PATH                    0x24
1410 #define STATUS_BTL_NO_FREE_SLOT_TGTID                   0x25
1411 #define STATUS_OSM_DEVSLOT_NOT_FOUND                    0x26
1412 #define STATUS_FLASHROM_READ_FAILED                     0x27
1413 #define STATUS_POLL_IOCTL_TIMEOUT                       0x28
1414 #define STATUS_ERROR_ACITMAIN                           0x2a
1415 #define STATUS_REBOOT_REQUIRED                          0x2c
1416 #define STATUS_FCF_IN_USE                               0x3a
1417 #define STATUS_FCF_TABLE_EMPTY                          0x43
1418
1419 struct lpfc_mbx_sli4_config {
1420         struct mbox_header header;
1421 };
1422
1423 struct lpfc_mbx_init_vfi {
1424         uint32_t word1;
1425 #define lpfc_init_vfi_vr_SHIFT          31
1426 #define lpfc_init_vfi_vr_MASK           0x00000001
1427 #define lpfc_init_vfi_vr_WORD           word1
1428 #define lpfc_init_vfi_vt_SHIFT          30
1429 #define lpfc_init_vfi_vt_MASK           0x00000001
1430 #define lpfc_init_vfi_vt_WORD           word1
1431 #define lpfc_init_vfi_vf_SHIFT          29
1432 #define lpfc_init_vfi_vf_MASK           0x00000001
1433 #define lpfc_init_vfi_vf_WORD           word1
1434 #define lpfc_init_vfi_vfi_SHIFT         0
1435 #define lpfc_init_vfi_vfi_MASK          0x0000FFFF
1436 #define lpfc_init_vfi_vfi_WORD          word1
1437         uint32_t word2;
1438 #define lpfc_init_vfi_fcfi_SHIFT        0
1439 #define lpfc_init_vfi_fcfi_MASK         0x0000FFFF
1440 #define lpfc_init_vfi_fcfi_WORD         word2
1441         uint32_t word3;
1442 #define lpfc_init_vfi_pri_SHIFT         13
1443 #define lpfc_init_vfi_pri_MASK          0x00000007
1444 #define lpfc_init_vfi_pri_WORD          word3
1445 #define lpfc_init_vfi_vf_id_SHIFT       1
1446 #define lpfc_init_vfi_vf_id_MASK        0x00000FFF
1447 #define lpfc_init_vfi_vf_id_WORD        word3
1448         uint32_t word4;
1449 #define lpfc_init_vfi_hop_count_SHIFT   24
1450 #define lpfc_init_vfi_hop_count_MASK    0x000000FF
1451 #define lpfc_init_vfi_hop_count_WORD    word4
1452 };
1453
1454 struct lpfc_mbx_reg_vfi {
1455         uint32_t word1;
1456 #define lpfc_reg_vfi_vp_SHIFT           28
1457 #define lpfc_reg_vfi_vp_MASK            0x00000001
1458 #define lpfc_reg_vfi_vp_WORD            word1
1459 #define lpfc_reg_vfi_vfi_SHIFT          0
1460 #define lpfc_reg_vfi_vfi_MASK           0x0000FFFF
1461 #define lpfc_reg_vfi_vfi_WORD           word1
1462         uint32_t word2;
1463 #define lpfc_reg_vfi_vpi_SHIFT          16
1464 #define lpfc_reg_vfi_vpi_MASK           0x0000FFFF
1465 #define lpfc_reg_vfi_vpi_WORD           word2
1466 #define lpfc_reg_vfi_fcfi_SHIFT         0
1467 #define lpfc_reg_vfi_fcfi_MASK          0x0000FFFF
1468 #define lpfc_reg_vfi_fcfi_WORD          word2
1469         uint32_t wwn[2];
1470         struct ulp_bde64 bde;
1471         uint32_t e_d_tov;
1472         uint32_t r_a_tov;
1473         uint32_t word10;
1474 #define lpfc_reg_vfi_nport_id_SHIFT             0
1475 #define lpfc_reg_vfi_nport_id_MASK              0x00FFFFFF
1476 #define lpfc_reg_vfi_nport_id_WORD              word10
1477 };
1478
1479 struct lpfc_mbx_init_vpi {
1480         uint32_t word1;
1481 #define lpfc_init_vpi_vfi_SHIFT         16
1482 #define lpfc_init_vpi_vfi_MASK          0x0000FFFF
1483 #define lpfc_init_vpi_vfi_WORD          word1
1484 #define lpfc_init_vpi_vpi_SHIFT         0
1485 #define lpfc_init_vpi_vpi_MASK          0x0000FFFF
1486 #define lpfc_init_vpi_vpi_WORD          word1
1487 };
1488
1489 struct lpfc_mbx_read_vpi {
1490         uint32_t word1_rsvd;
1491         uint32_t word2;
1492 #define lpfc_mbx_read_vpi_vnportid_SHIFT        0
1493 #define lpfc_mbx_read_vpi_vnportid_MASK         0x00FFFFFF
1494 #define lpfc_mbx_read_vpi_vnportid_WORD         word2
1495         uint32_t word3_rsvd;
1496         uint32_t word4;
1497 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT        0
1498 #define lpfc_mbx_read_vpi_acq_alpa_MASK         0x000000FF
1499 #define lpfc_mbx_read_vpi_acq_alpa_WORD         word4
1500 #define lpfc_mbx_read_vpi_pb_SHIFT              15
1501 #define lpfc_mbx_read_vpi_pb_MASK               0x00000001
1502 #define lpfc_mbx_read_vpi_pb_WORD               word4
1503 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT       16
1504 #define lpfc_mbx_read_vpi_spec_alpa_MASK        0x000000FF
1505 #define lpfc_mbx_read_vpi_spec_alpa_WORD        word4
1506 #define lpfc_mbx_read_vpi_ns_SHIFT              30
1507 #define lpfc_mbx_read_vpi_ns_MASK               0x00000001
1508 #define lpfc_mbx_read_vpi_ns_WORD               word4
1509 #define lpfc_mbx_read_vpi_hl_SHIFT              31
1510 #define lpfc_mbx_read_vpi_hl_MASK               0x00000001
1511 #define lpfc_mbx_read_vpi_hl_WORD               word4
1512         uint32_t word5_rsvd;
1513         uint32_t word6;
1514 #define lpfc_mbx_read_vpi_vpi_SHIFT             0
1515 #define lpfc_mbx_read_vpi_vpi_MASK              0x0000FFFF
1516 #define lpfc_mbx_read_vpi_vpi_WORD              word6
1517         uint32_t word7;
1518 #define lpfc_mbx_read_vpi_mac_0_SHIFT           0
1519 #define lpfc_mbx_read_vpi_mac_0_MASK            0x000000FF
1520 #define lpfc_mbx_read_vpi_mac_0_WORD            word7
1521 #define lpfc_mbx_read_vpi_mac_1_SHIFT           8
1522 #define lpfc_mbx_read_vpi_mac_1_MASK            0x000000FF
1523 #define lpfc_mbx_read_vpi_mac_1_WORD            word7
1524 #define lpfc_mbx_read_vpi_mac_2_SHIFT           16
1525 #define lpfc_mbx_read_vpi_mac_2_MASK            0x000000FF
1526 #define lpfc_mbx_read_vpi_mac_2_WORD            word7
1527 #define lpfc_mbx_read_vpi_mac_3_SHIFT           24
1528 #define lpfc_mbx_read_vpi_mac_3_MASK            0x000000FF
1529 #define lpfc_mbx_read_vpi_mac_3_WORD            word7
1530         uint32_t word8;
1531 #define lpfc_mbx_read_vpi_mac_4_SHIFT           0
1532 #define lpfc_mbx_read_vpi_mac_4_MASK            0x000000FF
1533 #define lpfc_mbx_read_vpi_mac_4_WORD            word8
1534 #define lpfc_mbx_read_vpi_mac_5_SHIFT           8
1535 #define lpfc_mbx_read_vpi_mac_5_MASK            0x000000FF
1536 #define lpfc_mbx_read_vpi_mac_5_WORD            word8
1537 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT        16
1538 #define lpfc_mbx_read_vpi_vlan_tag_MASK         0x00000FFF
1539 #define lpfc_mbx_read_vpi_vlan_tag_WORD         word8
1540 #define lpfc_mbx_read_vpi_vv_SHIFT              28
1541 #define lpfc_mbx_read_vpi_vv_MASK               0x0000001
1542 #define lpfc_mbx_read_vpi_vv_WORD               word8
1543 };
1544
1545 struct lpfc_mbx_unreg_vfi {
1546         uint32_t word1_rsvd;
1547         uint32_t word2;
1548 #define lpfc_unreg_vfi_vfi_SHIFT        0
1549 #define lpfc_unreg_vfi_vfi_MASK         0x0000FFFF
1550 #define lpfc_unreg_vfi_vfi_WORD         word2
1551 };
1552
1553 struct lpfc_mbx_resume_rpi {
1554         uint32_t word1;
1555 #define lpfc_resume_rpi_index_SHIFT     0
1556 #define lpfc_resume_rpi_index_MASK      0x0000FFFF
1557 #define lpfc_resume_rpi_index_WORD      word1
1558 #define lpfc_resume_rpi_ii_SHIFT        30
1559 #define lpfc_resume_rpi_ii_MASK         0x00000003
1560 #define lpfc_resume_rpi_ii_WORD         word1
1561 #define RESUME_INDEX_RPI                0
1562 #define RESUME_INDEX_VPI                1
1563 #define RESUME_INDEX_VFI                2
1564 #define RESUME_INDEX_FCFI               3
1565         uint32_t event_tag;
1566 };
1567
1568 #define REG_FCF_INVALID_QID     0xFFFF
1569 struct lpfc_mbx_reg_fcfi {
1570         uint32_t word1;
1571 #define lpfc_reg_fcfi_info_index_SHIFT  0
1572 #define lpfc_reg_fcfi_info_index_MASK   0x0000FFFF
1573 #define lpfc_reg_fcfi_info_index_WORD   word1
1574 #define lpfc_reg_fcfi_fcfi_SHIFT        16
1575 #define lpfc_reg_fcfi_fcfi_MASK         0x0000FFFF
1576 #define lpfc_reg_fcfi_fcfi_WORD         word1
1577         uint32_t word2;
1578 #define lpfc_reg_fcfi_rq_id1_SHIFT      0
1579 #define lpfc_reg_fcfi_rq_id1_MASK       0x0000FFFF
1580 #define lpfc_reg_fcfi_rq_id1_WORD       word2
1581 #define lpfc_reg_fcfi_rq_id0_SHIFT      16
1582 #define lpfc_reg_fcfi_rq_id0_MASK       0x0000FFFF
1583 #define lpfc_reg_fcfi_rq_id0_WORD       word2
1584         uint32_t word3;
1585 #define lpfc_reg_fcfi_rq_id3_SHIFT      0
1586 #define lpfc_reg_fcfi_rq_id3_MASK       0x0000FFFF
1587 #define lpfc_reg_fcfi_rq_id3_WORD       word3
1588 #define lpfc_reg_fcfi_rq_id2_SHIFT      16
1589 #define lpfc_reg_fcfi_rq_id2_MASK       0x0000FFFF
1590 #define lpfc_reg_fcfi_rq_id2_WORD       word3
1591         uint32_t word4;
1592 #define lpfc_reg_fcfi_type_match0_SHIFT 24
1593 #define lpfc_reg_fcfi_type_match0_MASK  0x000000FF
1594 #define lpfc_reg_fcfi_type_match0_WORD  word4
1595 #define lpfc_reg_fcfi_type_mask0_SHIFT  16
1596 #define lpfc_reg_fcfi_type_mask0_MASK   0x000000FF
1597 #define lpfc_reg_fcfi_type_mask0_WORD   word4
1598 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
1599 #define lpfc_reg_fcfi_rctl_match0_MASK  0x000000FF
1600 #define lpfc_reg_fcfi_rctl_match0_WORD  word4
1601 #define lpfc_reg_fcfi_rctl_mask0_SHIFT  0
1602 #define lpfc_reg_fcfi_rctl_mask0_MASK   0x000000FF
1603 #define lpfc_reg_fcfi_rctl_mask0_WORD   word4
1604         uint32_t word5;
1605 #define lpfc_reg_fcfi_type_match1_SHIFT 24
1606 #define lpfc_reg_fcfi_type_match1_MASK  0x000000FF
1607 #define lpfc_reg_fcfi_type_match1_WORD  word5
1608 #define lpfc_reg_fcfi_type_mask1_SHIFT  16
1609 #define lpfc_reg_fcfi_type_mask1_MASK   0x000000FF
1610 #define lpfc_reg_fcfi_type_mask1_WORD   word5
1611 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
1612 #define lpfc_reg_fcfi_rctl_match1_MASK  0x000000FF
1613 #define lpfc_reg_fcfi_rctl_match1_WORD  word5
1614 #define lpfc_reg_fcfi_rctl_mask1_SHIFT  0
1615 #define lpfc_reg_fcfi_rctl_mask1_MASK   0x000000FF
1616 #define lpfc_reg_fcfi_rctl_mask1_WORD   word5
1617         uint32_t word6;
1618 #define lpfc_reg_fcfi_type_match2_SHIFT 24
1619 #define lpfc_reg_fcfi_type_match2_MASK  0x000000FF
1620 #define lpfc_reg_fcfi_type_match2_WORD  word6
1621 #define lpfc_reg_fcfi_type_mask2_SHIFT  16
1622 #define lpfc_reg_fcfi_type_mask2_MASK   0x000000FF
1623 #define lpfc_reg_fcfi_type_mask2_WORD   word6
1624 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
1625 #define lpfc_reg_fcfi_rctl_match2_MASK  0x000000FF
1626 #define lpfc_reg_fcfi_rctl_match2_WORD  word6
1627 #define lpfc_reg_fcfi_rctl_mask2_SHIFT  0
1628 #define lpfc_reg_fcfi_rctl_mask2_MASK   0x000000FF
1629 #define lpfc_reg_fcfi_rctl_mask2_WORD   word6
1630         uint32_t word7;
1631 #define lpfc_reg_fcfi_type_match3_SHIFT 24
1632 #define lpfc_reg_fcfi_type_match3_MASK  0x000000FF
1633 #define lpfc_reg_fcfi_type_match3_WORD  word7
1634 #define lpfc_reg_fcfi_type_mask3_SHIFT  16
1635 #define lpfc_reg_fcfi_type_mask3_MASK   0x000000FF
1636 #define lpfc_reg_fcfi_type_mask3_WORD   word7
1637 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
1638 #define lpfc_reg_fcfi_rctl_match3_MASK  0x000000FF
1639 #define lpfc_reg_fcfi_rctl_match3_WORD  word7
1640 #define lpfc_reg_fcfi_rctl_mask3_SHIFT  0
1641 #define lpfc_reg_fcfi_rctl_mask3_MASK   0x000000FF
1642 #define lpfc_reg_fcfi_rctl_mask3_WORD   word7
1643         uint32_t word8;
1644 #define lpfc_reg_fcfi_mam_SHIFT         13
1645 #define lpfc_reg_fcfi_mam_MASK          0x00000003
1646 #define lpfc_reg_fcfi_mam_WORD          word8
1647 #define LPFC_MAM_BOTH           0       /* Both SPMA and FPMA */
1648 #define LPFC_MAM_SPMA           1       /* Server Provided MAC Address */
1649 #define LPFC_MAM_FPMA           2       /* Fabric Provided MAC Address */
1650 #define lpfc_reg_fcfi_vv_SHIFT          12
1651 #define lpfc_reg_fcfi_vv_MASK           0x00000001
1652 #define lpfc_reg_fcfi_vv_WORD           word8
1653 #define lpfc_reg_fcfi_vlan_tag_SHIFT    0
1654 #define lpfc_reg_fcfi_vlan_tag_MASK     0x00000FFF
1655 #define lpfc_reg_fcfi_vlan_tag_WORD     word8
1656 };
1657
1658 struct lpfc_mbx_unreg_fcfi {
1659         uint32_t word1_rsv;
1660         uint32_t word2;
1661 #define lpfc_unreg_fcfi_SHIFT           0
1662 #define lpfc_unreg_fcfi_MASK            0x0000FFFF
1663 #define lpfc_unreg_fcfi_WORD            word2
1664 };
1665
1666 struct lpfc_mbx_read_rev {
1667         uint32_t word1;
1668 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT           16
1669 #define lpfc_mbx_rd_rev_sli_lvl_MASK            0x0000000F
1670 #define lpfc_mbx_rd_rev_sli_lvl_WORD            word1
1671 #define lpfc_mbx_rd_rev_fcoe_SHIFT              20
1672 #define lpfc_mbx_rd_rev_fcoe_MASK               0x00000001
1673 #define lpfc_mbx_rd_rev_fcoe_WORD               word1
1674 #define lpfc_mbx_rd_rev_cee_ver_SHIFT           21
1675 #define lpfc_mbx_rd_rev_cee_ver_MASK            0x00000003
1676 #define lpfc_mbx_rd_rev_cee_ver_WORD            word1
1677 #define LPFC_PREDCBX_CEE_MODE   0
1678 #define LPFC_DCBX_CEE_MODE      1
1679 #define lpfc_mbx_rd_rev_vpd_SHIFT               29
1680 #define lpfc_mbx_rd_rev_vpd_MASK                0x00000001
1681 #define lpfc_mbx_rd_rev_vpd_WORD                word1
1682         uint32_t first_hw_rev;
1683         uint32_t second_hw_rev;
1684         uint32_t word4_rsvd;
1685         uint32_t third_hw_rev;
1686         uint32_t word6;
1687 #define lpfc_mbx_rd_rev_fcph_low_SHIFT          0
1688 #define lpfc_mbx_rd_rev_fcph_low_MASK           0x000000FF
1689 #define lpfc_mbx_rd_rev_fcph_low_WORD           word6
1690 #define lpfc_mbx_rd_rev_fcph_high_SHIFT         8
1691 #define lpfc_mbx_rd_rev_fcph_high_MASK          0x000000FF
1692 #define lpfc_mbx_rd_rev_fcph_high_WORD          word6
1693 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT       16
1694 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK        0x000000FF
1695 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD        word6
1696 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT      24
1697 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK       0x000000FF
1698 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD       word6
1699         uint32_t word7_rsvd;
1700         uint32_t fw_id_rev;
1701         uint8_t  fw_name[16];
1702         uint32_t ulp_fw_id_rev;
1703         uint8_t  ulp_fw_name[16];
1704         uint32_t word18_47_rsvd[30];
1705         uint32_t word48;
1706 #define lpfc_mbx_rd_rev_avail_len_SHIFT         0
1707 #define lpfc_mbx_rd_rev_avail_len_MASK          0x00FFFFFF
1708 #define lpfc_mbx_rd_rev_avail_len_WORD          word48
1709         uint32_t vpd_paddr_low;
1710         uint32_t vpd_paddr_high;
1711         uint32_t avail_vpd_len;
1712         uint32_t rsvd_52_63[12];
1713 };
1714
1715 struct lpfc_mbx_read_config {
1716         uint32_t word1;
1717 #define lpfc_mbx_rd_conf_max_bbc_SHIFT          0
1718 #define lpfc_mbx_rd_conf_max_bbc_MASK           0x000000FF
1719 #define lpfc_mbx_rd_conf_max_bbc_WORD           word1
1720 #define lpfc_mbx_rd_conf_init_bbc_SHIFT         8
1721 #define lpfc_mbx_rd_conf_init_bbc_MASK          0x000000FF
1722 #define lpfc_mbx_rd_conf_init_bbc_WORD          word1
1723         uint32_t word2;
1724 #define lpfc_mbx_rd_conf_nport_did_SHIFT        0
1725 #define lpfc_mbx_rd_conf_nport_did_MASK         0x00FFFFFF
1726 #define lpfc_mbx_rd_conf_nport_did_WORD         word2
1727 #define lpfc_mbx_rd_conf_topology_SHIFT         24
1728 #define lpfc_mbx_rd_conf_topology_MASK          0x000000FF
1729 #define lpfc_mbx_rd_conf_topology_WORD          word2
1730         uint32_t word3;
1731 #define lpfc_mbx_rd_conf_ao_SHIFT               0
1732 #define lpfc_mbx_rd_conf_ao_MASK                0x00000001
1733 #define lpfc_mbx_rd_conf_ao_WORD                word3
1734 #define lpfc_mbx_rd_conf_bb_scn_SHIFT           8
1735 #define lpfc_mbx_rd_conf_bb_scn_MASK            0x0000000F
1736 #define lpfc_mbx_rd_conf_bb_scn_WORD            word3
1737 #define lpfc_mbx_rd_conf_cbb_scn_SHIFT          12
1738 #define lpfc_mbx_rd_conf_cbb_scn_MASK           0x0000000F
1739 #define lpfc_mbx_rd_conf_cbb_scn_WORD           word3
1740 #define lpfc_mbx_rd_conf_mc_SHIFT               29
1741 #define lpfc_mbx_rd_conf_mc_MASK                0x00000001
1742 #define lpfc_mbx_rd_conf_mc_WORD                word3
1743         uint32_t word4;
1744 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT          0
1745 #define lpfc_mbx_rd_conf_e_d_tov_MASK           0x0000FFFF
1746 #define lpfc_mbx_rd_conf_e_d_tov_WORD           word4
1747         uint32_t word5;
1748 #define lpfc_mbx_rd_conf_lp_tov_SHIFT           0
1749 #define lpfc_mbx_rd_conf_lp_tov_MASK            0x0000FFFF
1750 #define lpfc_mbx_rd_conf_lp_tov_WORD            word5
1751         uint32_t word6;
1752 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT          0
1753 #define lpfc_mbx_rd_conf_r_a_tov_MASK           0x0000FFFF
1754 #define lpfc_mbx_rd_conf_r_a_tov_WORD           word6
1755         uint32_t word7;
1756 #define lpfc_mbx_rd_conf_r_t_tov_SHIFT          0
1757 #define lpfc_mbx_rd_conf_r_t_tov_MASK           0x000000FF
1758 #define lpfc_mbx_rd_conf_r_t_tov_WORD           word7
1759         uint32_t word8;
1760 #define lpfc_mbx_rd_conf_al_tov_SHIFT           0
1761 #define lpfc_mbx_rd_conf_al_tov_MASK            0x0000000F
1762 #define lpfc_mbx_rd_conf_al_tov_WORD            word8
1763         uint32_t word9;
1764 #define lpfc_mbx_rd_conf_lmt_SHIFT              0
1765 #define lpfc_mbx_rd_conf_lmt_MASK               0x0000FFFF
1766 #define lpfc_mbx_rd_conf_lmt_WORD               word9
1767         uint32_t word10;
1768 #define lpfc_mbx_rd_conf_max_alpa_SHIFT         0
1769 #define lpfc_mbx_rd_conf_max_alpa_MASK          0x000000FF
1770 #define lpfc_mbx_rd_conf_max_alpa_WORD          word10
1771         uint32_t word11_rsvd;
1772         uint32_t word12;
1773 #define lpfc_mbx_rd_conf_xri_base_SHIFT         0
1774 #define lpfc_mbx_rd_conf_xri_base_MASK          0x0000FFFF
1775 #define lpfc_mbx_rd_conf_xri_base_WORD          word12
1776 #define lpfc_mbx_rd_conf_xri_count_SHIFT        16
1777 #define lpfc_mbx_rd_conf_xri_count_MASK         0x0000FFFF
1778 #define lpfc_mbx_rd_conf_xri_count_WORD         word12
1779         uint32_t word13;
1780 #define lpfc_mbx_rd_conf_rpi_base_SHIFT         0
1781 #define lpfc_mbx_rd_conf_rpi_base_MASK          0x0000FFFF
1782 #define lpfc_mbx_rd_conf_rpi_base_WORD          word13
1783 #define lpfc_mbx_rd_conf_rpi_count_SHIFT        16
1784 #define lpfc_mbx_rd_conf_rpi_count_MASK         0x0000FFFF
1785 #define lpfc_mbx_rd_conf_rpi_count_WORD         word13
1786         uint32_t word14;
1787 #define lpfc_mbx_rd_conf_vpi_base_SHIFT         0
1788 #define lpfc_mbx_rd_conf_vpi_base_MASK          0x0000FFFF
1789 #define lpfc_mbx_rd_conf_vpi_base_WORD          word14
1790 #define lpfc_mbx_rd_conf_vpi_count_SHIFT        16
1791 #define lpfc_mbx_rd_conf_vpi_count_MASK         0x0000FFFF
1792 #define lpfc_mbx_rd_conf_vpi_count_WORD         word14
1793         uint32_t word15;
1794 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
1795 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
1796 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
1797 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
1798 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
1799 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
1800         uint32_t word16;
1801 #define lpfc_mbx_rd_conf_fcfi_base_SHIFT        0
1802 #define lpfc_mbx_rd_conf_fcfi_base_MASK         0x0000FFFF
1803 #define lpfc_mbx_rd_conf_fcfi_base_WORD         word16
1804 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT       16
1805 #define lpfc_mbx_rd_conf_fcfi_count_MASK        0x0000FFFF
1806 #define lpfc_mbx_rd_conf_fcfi_count_WORD        word16
1807         uint32_t word17;
1808 #define lpfc_mbx_rd_conf_rq_count_SHIFT         0
1809 #define lpfc_mbx_rd_conf_rq_count_MASK          0x0000FFFF
1810 #define lpfc_mbx_rd_conf_rq_count_WORD          word17
1811 #define lpfc_mbx_rd_conf_eq_count_SHIFT         16
1812 #define lpfc_mbx_rd_conf_eq_count_MASK          0x0000FFFF
1813 #define lpfc_mbx_rd_conf_eq_count_WORD          word17
1814         uint32_t word18;
1815 #define lpfc_mbx_rd_conf_wq_count_SHIFT         0
1816 #define lpfc_mbx_rd_conf_wq_count_MASK          0x0000FFFF
1817 #define lpfc_mbx_rd_conf_wq_count_WORD          word18
1818 #define lpfc_mbx_rd_conf_cq_count_SHIFT         16
1819 #define lpfc_mbx_rd_conf_cq_count_MASK          0x0000FFFF
1820 #define lpfc_mbx_rd_conf_cq_count_WORD          word18
1821 };
1822
1823 struct lpfc_mbx_request_features {
1824         uint32_t word1;
1825 #define lpfc_mbx_rq_ftr_qry_SHIFT               0
1826 #define lpfc_mbx_rq_ftr_qry_MASK                0x00000001
1827 #define lpfc_mbx_rq_ftr_qry_WORD                word1
1828         uint32_t word2;
1829 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT           0
1830 #define lpfc_mbx_rq_ftr_rq_iaab_MASK            0x00000001
1831 #define lpfc_mbx_rq_ftr_rq_iaab_WORD            word2
1832 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT           1
1833 #define lpfc_mbx_rq_ftr_rq_npiv_MASK            0x00000001
1834 #define lpfc_mbx_rq_ftr_rq_npiv_WORD            word2
1835 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT            2
1836 #define lpfc_mbx_rq_ftr_rq_dif_MASK             0x00000001
1837 #define lpfc_mbx_rq_ftr_rq_dif_WORD             word2
1838 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT             3
1839 #define lpfc_mbx_rq_ftr_rq_vf_MASK              0x00000001
1840 #define lpfc_mbx_rq_ftr_rq_vf_WORD              word2
1841 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT           4
1842 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK            0x00000001
1843 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD            word2
1844 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT           5
1845 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK            0x00000001
1846 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD            word2
1847 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT           6
1848 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK            0x00000001
1849 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD            word2
1850 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT           7
1851 #define lpfc_mbx_rq_ftr_rq_ifip_MASK            0x00000001
1852 #define lpfc_mbx_rq_ftr_rq_ifip_WORD            word2
1853         uint32_t word3;
1854 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT          0
1855 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK           0x00000001
1856 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD           word3
1857 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT          1
1858 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK           0x00000001
1859 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD           word3
1860 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT           2
1861 #define lpfc_mbx_rq_ftr_rsp_dif_MASK            0x00000001
1862 #define lpfc_mbx_rq_ftr_rsp_dif_WORD            word3
1863 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT            3
1864 #define lpfc_mbx_rq_ftr_rsp_vf__MASK            0x00000001
1865 #define lpfc_mbx_rq_ftr_rsp_vf_WORD             word3
1866 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT          4
1867 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK           0x00000001
1868 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD           word3
1869 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT          5
1870 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK           0x00000001
1871 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD           word3
1872 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT          6
1873 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK           0x00000001
1874 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD           word3
1875 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT          7
1876 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK           0x00000001
1877 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD           word3
1878 };
1879
1880 struct lpfc_mbx_supp_pages {
1881         uint32_t word1;
1882 #define qs_SHIFT                                0
1883 #define qs_MASK                                 0x00000001
1884 #define qs_WORD                                 word1
1885 #define wr_SHIFT                                1
1886 #define wr_MASK                                 0x00000001
1887 #define wr_WORD                                 word1
1888 #define pf_SHIFT                                8
1889 #define pf_MASK                                 0x000000ff
1890 #define pf_WORD                                 word1
1891 #define cpn_SHIFT                               16
1892 #define cpn_MASK                                0x000000ff
1893 #define cpn_WORD                                word1
1894         uint32_t word2;
1895 #define list_offset_SHIFT                       0
1896 #define list_offset_MASK                        0x000000ff
1897 #define list_offset_WORD                        word2
1898 #define next_offset_SHIFT                       8
1899 #define next_offset_MASK                        0x000000ff
1900 #define next_offset_WORD                        word2
1901 #define elem_cnt_SHIFT                          16
1902 #define elem_cnt_MASK                           0x000000ff
1903 #define elem_cnt_WORD                           word2
1904         uint32_t word3;
1905 #define pn_0_SHIFT                              24
1906 #define pn_0_MASK                               0x000000ff
1907 #define pn_0_WORD                               word3
1908 #define pn_1_SHIFT                              16
1909 #define pn_1_MASK                               0x000000ff
1910 #define pn_1_WORD                               word3
1911 #define pn_2_SHIFT                              8
1912 #define pn_2_MASK                               0x000000ff
1913 #define pn_2_WORD                               word3
1914 #define pn_3_SHIFT                              0
1915 #define pn_3_MASK                               0x000000ff
1916 #define pn_3_WORD                               word3
1917         uint32_t word4;
1918 #define pn_4_SHIFT                              24
1919 #define pn_4_MASK                               0x000000ff
1920 #define pn_4_WORD                               word4
1921 #define pn_5_SHIFT                              16
1922 #define pn_5_MASK                               0x000000ff
1923 #define pn_5_WORD                               word4
1924 #define pn_6_SHIFT                              8
1925 #define pn_6_MASK                               0x000000ff
1926 #define pn_6_WORD                               word4
1927 #define pn_7_SHIFT                              0
1928 #define pn_7_MASK                               0x000000ff
1929 #define pn_7_WORD                               word4
1930         uint32_t rsvd[27];
1931 #define LPFC_SUPP_PAGES                 0
1932 #define LPFC_BLOCK_GUARD_PROFILES       1
1933 #define LPFC_SLI4_PARAMETERS            2
1934 };
1935
1936 struct lpfc_mbx_sli4_params {
1937         uint32_t word1;
1938 #define qs_SHIFT                                0
1939 #define qs_MASK                                 0x00000001
1940 #define qs_WORD                                 word1
1941 #define wr_SHIFT                                1
1942 #define wr_MASK                                 0x00000001
1943 #define wr_WORD                                 word1
1944 #define pf_SHIFT                                8
1945 #define pf_MASK                                 0x000000ff
1946 #define pf_WORD                                 word1
1947 #define cpn_SHIFT                               16
1948 #define cpn_MASK                                0x000000ff
1949 #define cpn_WORD                                word1
1950         uint32_t word2;
1951 #define if_type_SHIFT                           0
1952 #define if_type_MASK                            0x00000007
1953 #define if_type_WORD                            word2
1954 #define sli_rev_SHIFT                           4
1955 #define sli_rev_MASK                            0x0000000f
1956 #define sli_rev_WORD                            word2
1957 #define sli_family_SHIFT                        8
1958 #define sli_family_MASK                         0x000000ff
1959 #define sli_family_WORD                         word2
1960 #define featurelevel_1_SHIFT                    16
1961 #define featurelevel_1_MASK                     0x000000ff
1962 #define featurelevel_1_WORD                     word2
1963 #define featurelevel_2_SHIFT                    24
1964 #define featurelevel_2_MASK                     0x0000001f
1965 #define featurelevel_2_WORD                     word2
1966         uint32_t word3;
1967 #define fcoe_SHIFT                              0
1968 #define fcoe_MASK                               0x00000001
1969 #define fcoe_WORD                               word3
1970 #define fc_SHIFT                                1
1971 #define fc_MASK                                 0x00000001
1972 #define fc_WORD                                 word3
1973 #define nic_SHIFT                               2
1974 #define nic_MASK                                0x00000001
1975 #define nic_WORD                                word3
1976 #define iscsi_SHIFT                             3
1977 #define iscsi_MASK                              0x00000001
1978 #define iscsi_WORD                              word3
1979 #define rdma_SHIFT                              4
1980 #define rdma_MASK                               0x00000001
1981 #define rdma_WORD                               word3
1982         uint32_t sge_supp_len;
1983 #define SLI4_PAGE_SIZE 4096
1984         uint32_t word5;
1985 #define if_page_sz_SHIFT                        0
1986 #define if_page_sz_MASK                         0x0000ffff
1987 #define if_page_sz_WORD                         word5
1988 #define loopbk_scope_SHIFT                      24
1989 #define loopbk_scope_MASK                       0x0000000f
1990 #define loopbk_scope_WORD                       word5
1991 #define rq_db_window_SHIFT                      28
1992 #define rq_db_window_MASK                       0x0000000f
1993 #define rq_db_window_WORD                       word5
1994         uint32_t word6;
1995 #define eq_pages_SHIFT                          0
1996 #define eq_pages_MASK                           0x0000000f
1997 #define eq_pages_WORD                           word6
1998 #define eqe_size_SHIFT                          8
1999 #define eqe_size_MASK                           0x000000ff
2000 #define eqe_size_WORD                           word6
2001         uint32_t word7;
2002 #define cq_pages_SHIFT                          0
2003 #define cq_pages_MASK                           0x0000000f
2004 #define cq_pages_WORD                           word7
2005 #define cqe_size_SHIFT                          8
2006 #define cqe_size_MASK                           0x000000ff
2007 #define cqe_size_WORD                           word7
2008         uint32_t word8;
2009 #define mq_pages_SHIFT                          0
2010 #define mq_pages_MASK                           0x0000000f
2011 #define mq_pages_WORD                           word8
2012 #define mqe_size_SHIFT                          8
2013 #define mqe_size_MASK                           0x000000ff
2014 #define mqe_size_WORD                           word8
2015 #define mq_elem_cnt_SHIFT                       16
2016 #define mq_elem_cnt_MASK                        0x000000ff
2017 #define mq_elem_cnt_WORD                        word8
2018         uint32_t word9;
2019 #define wq_pages_SHIFT                          0
2020 #define wq_pages_MASK                           0x0000ffff
2021 #define wq_pages_WORD                           word9
2022 #define wqe_size_SHIFT                          8
2023 #define wqe_size_MASK                           0x000000ff
2024 #define wqe_size_WORD                           word9
2025         uint32_t word10;
2026 #define rq_pages_SHIFT                          0
2027 #define rq_pages_MASK                           0x0000ffff
2028 #define rq_pages_WORD                           word10
2029 #define rqe_size_SHIFT                          8
2030 #define rqe_size_MASK                           0x000000ff
2031 #define rqe_size_WORD                           word10
2032         uint32_t word11;
2033 #define hdr_pages_SHIFT                         0
2034 #define hdr_pages_MASK                          0x0000000f
2035 #define hdr_pages_WORD                          word11
2036 #define hdr_size_SHIFT                          8
2037 #define hdr_size_MASK                           0x0000000f
2038 #define hdr_size_WORD                           word11
2039 #define hdr_pp_align_SHIFT                      16
2040 #define hdr_pp_align_MASK                       0x0000ffff
2041 #define hdr_pp_align_WORD                       word11
2042         uint32_t word12;
2043 #define sgl_pages_SHIFT                         0
2044 #define sgl_pages_MASK                          0x0000000f
2045 #define sgl_pages_WORD                          word12
2046 #define sgl_pp_align_SHIFT                      16
2047 #define sgl_pp_align_MASK                       0x0000ffff
2048 #define sgl_pp_align_WORD                       word12
2049         uint32_t rsvd_13_63[51];
2050 };
2051
2052 /* Mailbox Completion Queue Error Messages */
2053 #define MB_CQE_STATUS_SUCCESS                   0x0
2054 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES   0x1
2055 #define MB_CQE_STATUS_INVALID_PARAMETER         0x2
2056 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES    0x3
2057 #define MB_CEQ_STATUS_QUEUE_FLUSHING            0x4
2058 #define MB_CQE_STATUS_DMA_FAILED                0x5
2059
2060 /* mailbox queue entry structure */
2061 struct lpfc_mqe {
2062         uint32_t word0;
2063 #define lpfc_mqe_status_SHIFT           16
2064 #define lpfc_mqe_status_MASK            0x0000FFFF
2065 #define lpfc_mqe_status_WORD            word0
2066 #define lpfc_mqe_command_SHIFT          8
2067 #define lpfc_mqe_command_MASK           0x000000FF
2068 #define lpfc_mqe_command_WORD           word0
2069         union {
2070                 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
2071                 /* sli4 mailbox commands */
2072                 struct lpfc_mbx_sli4_config sli4_config;
2073                 struct lpfc_mbx_init_vfi init_vfi;
2074                 struct lpfc_mbx_reg_vfi reg_vfi;
2075                 struct lpfc_mbx_reg_vfi unreg_vfi;
2076                 struct lpfc_mbx_init_vpi init_vpi;
2077                 struct lpfc_mbx_resume_rpi resume_rpi;
2078                 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
2079                 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
2080                 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
2081                 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
2082                 struct lpfc_mbx_reg_fcfi reg_fcfi;
2083                 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
2084                 struct lpfc_mbx_mq_create mq_create;
2085                 struct lpfc_mbx_mq_create_ext mq_create_ext;
2086                 struct lpfc_mbx_eq_create eq_create;
2087                 struct lpfc_mbx_cq_create cq_create;
2088                 struct lpfc_mbx_wq_create wq_create;
2089                 struct lpfc_mbx_rq_create rq_create;
2090                 struct lpfc_mbx_mq_destroy mq_destroy;
2091                 struct lpfc_mbx_eq_destroy eq_destroy;
2092                 struct lpfc_mbx_cq_destroy cq_destroy;
2093                 struct lpfc_mbx_wq_destroy wq_destroy;
2094                 struct lpfc_mbx_rq_destroy rq_destroy;
2095                 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
2096                 struct lpfc_mbx_nembed_cmd nembed_cmd;
2097                 struct lpfc_mbx_read_rev read_rev;
2098                 struct lpfc_mbx_read_vpi read_vpi;
2099                 struct lpfc_mbx_read_config rd_config;
2100                 struct lpfc_mbx_request_features req_ftrs;
2101                 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
2102                 struct lpfc_mbx_query_fw_cfg query_fw_cfg;
2103                 struct lpfc_mbx_supp_pages supp_pages;
2104                 struct lpfc_mbx_sli4_params sli4_params;
2105                 struct lpfc_mbx_nop nop;
2106         } un;
2107 };
2108
2109 struct lpfc_mcqe {
2110         uint32_t word0;
2111 #define lpfc_mcqe_status_SHIFT          0
2112 #define lpfc_mcqe_status_MASK           0x0000FFFF
2113 #define lpfc_mcqe_status_WORD           word0
2114 #define lpfc_mcqe_ext_status_SHIFT      16
2115 #define lpfc_mcqe_ext_status_MASK       0x0000FFFF
2116 #define lpfc_mcqe_ext_status_WORD       word0
2117         uint32_t mcqe_tag0;
2118         uint32_t mcqe_tag1;
2119         uint32_t trailer;
2120 #define lpfc_trailer_valid_SHIFT        31
2121 #define lpfc_trailer_valid_MASK         0x00000001
2122 #define lpfc_trailer_valid_WORD         trailer
2123 #define lpfc_trailer_async_SHIFT        30
2124 #define lpfc_trailer_async_MASK         0x00000001
2125 #define lpfc_trailer_async_WORD         trailer
2126 #define lpfc_trailer_hpi_SHIFT          29
2127 #define lpfc_trailer_hpi_MASK           0x00000001
2128 #define lpfc_trailer_hpi_WORD           trailer
2129 #define lpfc_trailer_completed_SHIFT    28
2130 #define lpfc_trailer_completed_MASK     0x00000001
2131 #define lpfc_trailer_completed_WORD     trailer
2132 #define lpfc_trailer_consumed_SHIFT     27
2133 #define lpfc_trailer_consumed_MASK      0x00000001
2134 #define lpfc_trailer_consumed_WORD      trailer
2135 #define lpfc_trailer_type_SHIFT         16
2136 #define lpfc_trailer_type_MASK          0x000000FF
2137 #define lpfc_trailer_type_WORD          trailer
2138 #define lpfc_trailer_code_SHIFT         8
2139 #define lpfc_trailer_code_MASK          0x000000FF
2140 #define lpfc_trailer_code_WORD          trailer
2141 #define LPFC_TRAILER_CODE_LINK  0x1
2142 #define LPFC_TRAILER_CODE_FCOE  0x2
2143 #define LPFC_TRAILER_CODE_DCBX  0x3
2144 #define LPFC_TRAILER_CODE_GRP5  0x5
2145 };
2146
2147 struct lpfc_acqe_link {
2148         uint32_t word0;
2149 #define lpfc_acqe_link_speed_SHIFT              24
2150 #define lpfc_acqe_link_speed_MASK               0x000000FF
2151 #define lpfc_acqe_link_speed_WORD               word0
2152 #define LPFC_ASYNC_LINK_SPEED_ZERO              0x0
2153 #define LPFC_ASYNC_LINK_SPEED_10MBPS            0x1
2154 #define LPFC_ASYNC_LINK_SPEED_100MBPS           0x2
2155 #define LPFC_ASYNC_LINK_SPEED_1GBPS             0x3
2156 #define LPFC_ASYNC_LINK_SPEED_10GBPS            0x4
2157 #define lpfc_acqe_link_duplex_SHIFT             16
2158 #define lpfc_acqe_link_duplex_MASK              0x000000FF
2159 #define lpfc_acqe_link_duplex_WORD              word0
2160 #define LPFC_ASYNC_LINK_DUPLEX_NONE             0x0
2161 #define LPFC_ASYNC_LINK_DUPLEX_HALF             0x1
2162 #define LPFC_ASYNC_LINK_DUPLEX_FULL             0x2
2163 #define lpfc_acqe_link_status_SHIFT             8
2164 #define lpfc_acqe_link_status_MASK              0x000000FF
2165 #define lpfc_acqe_link_status_WORD              word0
2166 #define LPFC_ASYNC_LINK_STATUS_DOWN             0x0
2167 #define LPFC_ASYNC_LINK_STATUS_UP               0x1
2168 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN     0x2
2169 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP       0x3
2170 #define lpfc_acqe_link_physical_SHIFT           0
2171 #define lpfc_acqe_link_physical_MASK            0x000000FF
2172 #define lpfc_acqe_link_physical_WORD            word0
2173 #define LPFC_ASYNC_LINK_PORT_A                  0x0
2174 #define LPFC_ASYNC_LINK_PORT_B                  0x1
2175         uint32_t word1;
2176 #define lpfc_acqe_link_fault_SHIFT      0
2177 #define lpfc_acqe_link_fault_MASK       0x000000FF
2178 #define lpfc_acqe_link_fault_WORD       word1
2179 #define LPFC_ASYNC_LINK_FAULT_NONE      0x0
2180 #define LPFC_ASYNC_LINK_FAULT_LOCAL     0x1
2181 #define LPFC_ASYNC_LINK_FAULT_REMOTE    0x2
2182 #define lpfc_acqe_qos_link_speed_SHIFT  16
2183 #define lpfc_acqe_qos_link_speed_MASK   0x0000FFFF
2184 #define lpfc_acqe_qos_link_speed_WORD   word1
2185         uint32_t event_tag;
2186         uint32_t trailer;
2187 };
2188
2189 struct lpfc_acqe_fcoe {
2190         uint32_t index;
2191         uint32_t word1;
2192 #define lpfc_acqe_fcoe_fcf_count_SHIFT          0
2193 #define lpfc_acqe_fcoe_fcf_count_MASK           0x0000FFFF
2194 #define lpfc_acqe_fcoe_fcf_count_WORD           word1
2195 #define lpfc_acqe_fcoe_event_type_SHIFT         16
2196 #define lpfc_acqe_fcoe_event_type_MASK          0x0000FFFF
2197 #define lpfc_acqe_fcoe_event_type_WORD          word1
2198 #define LPFC_FCOE_EVENT_TYPE_NEW_FCF            0x1
2199 #define LPFC_FCOE_EVENT_TYPE_FCF_TABLE_FULL     0x2
2200 #define LPFC_FCOE_EVENT_TYPE_FCF_DEAD           0x3
2201 #define LPFC_FCOE_EVENT_TYPE_CVL                0x4
2202 #define LPFC_FCOE_EVENT_TYPE_FCF_PARAM_MOD      0x5
2203         uint32_t event_tag;
2204         uint32_t trailer;
2205 };
2206
2207 struct lpfc_acqe_dcbx {
2208         uint32_t tlv_ttl;
2209         uint32_t reserved;
2210         uint32_t event_tag;
2211         uint32_t trailer;
2212 };
2213
2214 struct lpfc_acqe_grp5 {
2215         uint32_t word0;
2216 #define lpfc_acqe_grp5_pport_SHIFT      0
2217 #define lpfc_acqe_grp5_pport_MASK       0x000000FF
2218 #define lpfc_acqe_grp5_pport_WORD       word0
2219         uint32_t word1;
2220 #define lpfc_acqe_grp5_llink_spd_SHIFT  16
2221 #define lpfc_acqe_grp5_llink_spd_MASK   0x0000FFFF
2222 #define lpfc_acqe_grp5_llink_spd_WORD   word1
2223         uint32_t event_tag;
2224         uint32_t trailer;
2225 };
2226
2227 /*
2228  * Define the bootstrap mailbox (bmbx) region used to communicate
2229  * mailbox command between the host and port. The mailbox consists
2230  * of a payload area of 256 bytes and a completion queue of length
2231  * 16 bytes.
2232  */
2233 struct lpfc_bmbx_create {
2234         struct lpfc_mqe mqe;
2235         struct lpfc_mcqe mcqe;
2236 };
2237
2238 #define SGL_ALIGN_SZ 64
2239 #define SGL_PAGE_SIZE 4096
2240 /* align SGL addr on a size boundary - adjust address up */
2241 #define NO_XRI  ((uint16_t)-1)
2242
2243 struct wqe_common {
2244         uint32_t word6;
2245 #define wqe_xri_tag_SHIFT     0
2246 #define wqe_xri_tag_MASK      0x0000FFFF
2247 #define wqe_xri_tag_WORD      word6
2248 #define wqe_ctxt_tag_SHIFT    16
2249 #define wqe_ctxt_tag_MASK     0x0000FFFF
2250 #define wqe_ctxt_tag_WORD     word6
2251         uint32_t word7;
2252 #define wqe_ct_SHIFT          2
2253 #define wqe_ct_MASK           0x00000003
2254 #define wqe_ct_WORD           word7
2255 #define wqe_status_SHIFT      4
2256 #define wqe_status_MASK       0x0000000f
2257 #define wqe_status_WORD       word7
2258 #define wqe_cmnd_SHIFT        8
2259 #define wqe_cmnd_MASK         0x000000ff
2260 #define wqe_cmnd_WORD         word7
2261 #define wqe_class_SHIFT       16
2262 #define wqe_class_MASK        0x00000007
2263 #define wqe_class_WORD        word7
2264 #define wqe_pu_SHIFT          20
2265 #define wqe_pu_MASK           0x00000003
2266 #define wqe_pu_WORD           word7
2267 #define wqe_erp_SHIFT         22
2268 #define wqe_erp_MASK          0x00000001
2269 #define wqe_erp_WORD          word7
2270 #define wqe_lnk_SHIFT         23
2271 #define wqe_lnk_MASK          0x00000001
2272 #define wqe_lnk_WORD          word7
2273 #define wqe_tmo_SHIFT         24
2274 #define wqe_tmo_MASK          0x000000ff
2275 #define wqe_tmo_WORD          word7
2276         uint32_t abort_tag; /* word 8 in WQE */
2277         uint32_t word9;
2278 #define wqe_reqtag_SHIFT      0
2279 #define wqe_reqtag_MASK       0x0000FFFF
2280 #define wqe_reqtag_WORD       word9
2281 #define wqe_rcvoxid_SHIFT     16
2282 #define wqe_rcvoxid_MASK       0x0000FFFF
2283 #define wqe_rcvoxid_WORD       word9
2284         uint32_t word10;
2285 #define wqe_pri_SHIFT         16
2286 #define wqe_pri_MASK          0x00000007
2287 #define wqe_pri_WORD          word10
2288 #define wqe_pv_SHIFT          19
2289 #define wqe_pv_MASK           0x00000001
2290 #define wqe_pv_WORD           word10
2291 #define wqe_xc_SHIFT          21
2292 #define wqe_xc_MASK           0x00000001
2293 #define wqe_xc_WORD           word10
2294 #define wqe_ccpe_SHIFT        23
2295 #define wqe_ccpe_MASK         0x00000001
2296 #define wqe_ccpe_WORD         word10
2297 #define wqe_ccp_SHIFT         24
2298 #define wqe_ccp_MASK         0x000000ff
2299 #define wqe_ccp_WORD         word10
2300         uint32_t word11;
2301 #define wqe_cmd_type_SHIFT  0
2302 #define wqe_cmd_type_MASK   0x0000000f
2303 #define wqe_cmd_type_WORD   word11
2304 #define wqe_wqec_SHIFT      7
2305 #define wqe_wqec_MASK       0x00000001
2306 #define wqe_wqec_WORD       word11
2307 #define wqe_cqid_SHIFT      16
2308 #define wqe_cqid_MASK       0x0000ffff
2309 #define wqe_cqid_WORD       word11
2310 };
2311
2312 struct wqe_did {
2313         uint32_t word5;
2314 #define wqe_els_did_SHIFT         0
2315 #define wqe_els_did_MASK          0x00FFFFFF
2316 #define wqe_els_did_WORD          word5
2317 #define wqe_xmit_bls_pt_SHIFT         28
2318 #define wqe_xmit_bls_pt_MASK          0x00000003
2319 #define wqe_xmit_bls_pt_WORD          word5
2320 #define wqe_xmit_bls_ar_SHIFT         30
2321 #define wqe_xmit_bls_ar_MASK          0x00000001
2322 #define wqe_xmit_bls_ar_WORD          word5
2323 #define wqe_xmit_bls_xo_SHIFT         31
2324 #define wqe_xmit_bls_xo_MASK          0x00000001
2325 #define wqe_xmit_bls_xo_WORD          word5
2326 };
2327
2328 struct els_request64_wqe {
2329         struct ulp_bde64 bde;
2330         uint32_t payload_len;
2331         uint32_t word4;
2332 #define els_req64_sid_SHIFT         0
2333 #define els_req64_sid_MASK          0x00FFFFFF
2334 #define els_req64_sid_WORD          word4
2335 #define els_req64_sp_SHIFT          24
2336 #define els_req64_sp_MASK           0x00000001
2337 #define els_req64_sp_WORD           word4
2338 #define els_req64_vf_SHIFT          25
2339 #define els_req64_vf_MASK           0x00000001
2340 #define els_req64_vf_WORD           word4
2341         struct wqe_did  wqe_dest;
2342         struct wqe_common wqe_com; /* words 6-11 */
2343         uint32_t word12;
2344 #define els_req64_vfid_SHIFT        1
2345 #define els_req64_vfid_MASK         0x00000FFF
2346 #define els_req64_vfid_WORD         word12
2347 #define els_req64_pri_SHIFT         13
2348 #define els_req64_pri_MASK          0x00000007
2349 #define els_req64_pri_WORD          word12
2350         uint32_t word13;
2351 #define els_req64_hopcnt_SHIFT      24
2352 #define els_req64_hopcnt_MASK       0x000000ff
2353 #define els_req64_hopcnt_WORD       word13
2354         uint32_t reserved[2];
2355 };
2356
2357 struct xmit_els_rsp64_wqe {
2358         struct ulp_bde64 bde;
2359         uint32_t rsvd3;
2360         uint32_t rsvd4;
2361         struct wqe_did  wqe_dest;
2362         struct wqe_common wqe_com; /* words 6-11 */
2363         uint32_t rsvd_12_15[4];
2364 };
2365
2366 struct xmit_bls_rsp64_wqe {
2367         uint32_t payload0;
2368 /* Payload0 for BA_ACC */
2369 #define xmit_bls_rsp64_acc_seq_id_SHIFT        16
2370 #define xmit_bls_rsp64_acc_seq_id_MASK         0x000000ff
2371 #define xmit_bls_rsp64_acc_seq_id_WORD         payload0
2372 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT   24
2373 #define xmit_bls_rsp64_acc_seq_id_vald_MASK    0x000000ff
2374 #define xmit_bls_rsp64_acc_seq_id_vald_WORD    payload0
2375 /* Payload0 for BA_RJT */
2376 #define xmit_bls_rsp64_rjt_vspec_SHIFT   0
2377 #define xmit_bls_rsp64_rjt_vspec_MASK    0x000000ff
2378 #define xmit_bls_rsp64_rjt_vspec_WORD    payload0
2379 #define xmit_bls_rsp64_rjt_expc_SHIFT    8
2380 #define xmit_bls_rsp64_rjt_expc_MASK     0x000000ff
2381 #define xmit_bls_rsp64_rjt_expc_WORD     payload0
2382 #define xmit_bls_rsp64_rjt_rsnc_SHIFT    16
2383 #define xmit_bls_rsp64_rjt_rsnc_MASK     0x000000ff
2384 #define xmit_bls_rsp64_rjt_rsnc_WORD     payload0
2385         uint32_t word1;
2386 #define xmit_bls_rsp64_rxid_SHIFT  0
2387 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
2388 #define xmit_bls_rsp64_rxid_WORD   word1
2389 #define xmit_bls_rsp64_oxid_SHIFT  16
2390 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
2391 #define xmit_bls_rsp64_oxid_WORD   word1
2392         uint32_t word2;
2393 #define xmit_bls_rsp64_seqcnthi_SHIFT  0
2394 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
2395 #define xmit_bls_rsp64_seqcnthi_WORD   word2
2396 #define xmit_bls_rsp64_seqcntlo_SHIFT  16
2397 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
2398 #define xmit_bls_rsp64_seqcntlo_WORD   word2
2399         uint32_t rsrvd3;
2400         uint32_t rsrvd4;
2401         struct wqe_did  wqe_dest;
2402         struct wqe_common wqe_com; /* words 6-11 */
2403         uint32_t rsvd_12_15[4];
2404 };
2405
2406 struct wqe_rctl_dfctl {
2407         uint32_t word5;
2408 #define wqe_si_SHIFT 2
2409 #define wqe_si_MASK  0x000000001
2410 #define wqe_si_WORD  word5
2411 #define wqe_la_SHIFT 3
2412 #define wqe_la_MASK  0x000000001
2413 #define wqe_la_WORD  word5
2414 #define wqe_ls_SHIFT 7
2415 #define wqe_ls_MASK  0x000000001
2416 #define wqe_ls_WORD  word5
2417 #define wqe_dfctl_SHIFT 8
2418 #define wqe_dfctl_MASK  0x0000000ff
2419 #define wqe_dfctl_WORD  word5
2420 #define wqe_type_SHIFT 16
2421 #define wqe_type_MASK  0x0000000ff
2422 #define wqe_type_WORD  word5
2423 #define wqe_rctl_SHIFT 24
2424 #define wqe_rctl_MASK  0x0000000ff
2425 #define wqe_rctl_WORD  word5
2426 };
2427
2428 struct xmit_seq64_wqe {
2429         struct ulp_bde64 bde;
2430         uint32_t paylaod_offset;
2431         uint32_t relative_offset;
2432         struct wqe_rctl_dfctl wge_ctl;
2433         struct wqe_common wqe_com; /* words 6-11 */
2434         /* Note: word10 different REVISIT */
2435         uint32_t xmit_len;
2436         uint32_t rsvd_12_15[3];
2437 };
2438 struct xmit_bcast64_wqe {
2439         struct ulp_bde64 bde;
2440         uint32_t paylaod_len;
2441         uint32_t rsvd4;
2442         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2443         struct wqe_common wqe_com;     /* words 6-11 */
2444         uint32_t rsvd_12_15[4];
2445 };
2446
2447 struct gen_req64_wqe {
2448         struct ulp_bde64 bde;
2449         uint32_t command_len;
2450         uint32_t payload_len;
2451         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2452         struct wqe_common wqe_com;     /* words 6-11 */
2453         uint32_t rsvd_12_15[4];
2454 };
2455
2456 struct create_xri_wqe {
2457         uint32_t rsrvd[5];           /* words 0-4 */
2458         struct wqe_did  wqe_dest;  /* word 5 */
2459         struct wqe_common wqe_com; /* words 6-11 */
2460         uint32_t rsvd_12_15[4];         /* word 12-15 */
2461 };
2462
2463 #define T_REQUEST_TAG 3
2464 #define T_XRI_TAG 1
2465
2466 struct abort_cmd_wqe {
2467         uint32_t rsrvd[3];
2468         uint32_t word3;
2469 #define abort_cmd_ia_SHIFT  0
2470 #define abort_cmd_ia_MASK  0x000000001
2471 #define abort_cmd_ia_WORD  word3
2472 #define abort_cmd_criteria_SHIFT  8
2473 #define abort_cmd_criteria_MASK  0x0000000ff
2474 #define abort_cmd_criteria_WORD  word3
2475         uint32_t rsrvd4;
2476         uint32_t rsrvd5;
2477         struct wqe_common wqe_com;     /* words 6-11 */
2478         uint32_t rsvd_12_15[4];         /* word 12-15 */
2479 };
2480
2481 struct fcp_iwrite64_wqe {
2482         struct ulp_bde64 bde;
2483         uint32_t payload_len;
2484         uint32_t total_xfer_len;
2485         uint32_t initial_xfer_len;
2486         struct wqe_common wqe_com;     /* words 6-11 */
2487         uint32_t rsvd_12_15[4];         /* word 12-15 */
2488 };
2489
2490 struct fcp_iread64_wqe {
2491         struct ulp_bde64 bde;
2492         uint32_t payload_len;          /* word 3 */
2493         uint32_t total_xfer_len;       /* word 4 */
2494         uint32_t rsrvd5;               /* word 5 */
2495         struct wqe_common wqe_com;     /* words 6-11 */
2496         uint32_t rsvd_12_15[4];         /* word 12-15 */
2497 };
2498
2499 struct fcp_icmnd64_wqe {
2500         struct ulp_bde64 bde;    /* words 0-2 */
2501         uint32_t rsrvd[3];             /* words 3-5 */
2502         struct wqe_common wqe_com;     /* words 6-11 */
2503         uint32_t rsvd_12_15[4];         /* word 12-15 */
2504 };
2505
2506
2507 union lpfc_wqe {
2508         uint32_t words[16];
2509         struct lpfc_wqe_generic generic;
2510         struct fcp_icmnd64_wqe fcp_icmd;
2511         struct fcp_iread64_wqe fcp_iread;
2512         struct fcp_iwrite64_wqe fcp_iwrite;
2513         struct abort_cmd_wqe abort_cmd;
2514         struct create_xri_wqe create_xri;
2515         struct xmit_bcast64_wqe xmit_bcast64;
2516         struct xmit_seq64_wqe xmit_sequence;
2517         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
2518         struct xmit_els_rsp64_wqe xmit_els_rsp;
2519         struct els_request64_wqe els_req;
2520         struct gen_req64_wqe gen_req;
2521 };
2522
2523 #define FCP_COMMAND 0x0
2524 #define FCP_COMMAND_DATA_OUT 0x1
2525 #define ELS_COMMAND_NON_FIP 0xC
2526 #define ELS_COMMAND_FIP 0xD
2527 #define OTHER_COMMAND 0x8
2528