drivers/pci/intr_remapping.c

   1 #include <linux/interrupt.h>
   2 #include <linux/dmar.h>
   3 #include <linux/spinlock.h>
   4 #include <linux/jiffies.h>
   5 #include <linux/hpet.h>
   6 #include <linux/pci.h>
   7 #include <linux/irq.h>
   8 #include <asm/io_apic.h>
   9 #include <asm/smp.h>
  10 #include <asm/cpu.h>
  11 #include <linux/intel-iommu.h>
  12 #include "intr_remapping.h"
  13 #include <acpi/acpi.h>
  14 #include <asm/pci-direct.h>
  15 #include "pci.h"
  16
  17 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  18 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
  19 static int ir_ioapic_num, ir_hpet_num;
  20 int intr_remapping_enabled;
  21
  22 static int disable_intremap;
  23 static __init int setup_nointremap(char *str)
  24 {
  25         disable_intremap = 1;
  26         return 0;
  27 }
  28 early_param("nointremap", setup_nointremap);
  29
  30 struct irq_2_iommu {
  31         struct intel_iommu *iommu;
  32         u16 irte_index;
  33         u16 sub_handle;
  34         u8  irte_mask;
  35 };
  36
  37 #ifdef CONFIG_GENERIC_HARDIRQS
  38 static struct irq_2_iommu *get_one_free_irq_2_iommu(int node)
  39 {
  40         struct irq_2_iommu *iommu;
  41
  42         iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node);
  43         printk(KERN_DEBUG "alloc irq_2_iommu on node %d\n", node);
  44
  45         return iommu;
  46 }
  47
  48 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  49 {
  50         struct irq_desc *desc;
  51
  52         desc = irq_to_desc(irq);
  53
  54         if (WARN_ON_ONCE(!desc))
  55                 return NULL;
  56
  57         return desc->irq_2_iommu;
  58 }
  59
  60 static struct irq_2_iommu *irq_2_iommu_alloc_node(unsigned int irq, int node)
  61 {
  62         struct irq_desc *desc;
  63         struct irq_2_iommu *irq_iommu;
  64
  65         /*
  66          * alloc irq desc if not allocated already.
  67          */
  68         desc = irq_to_desc_alloc_node(irq, node);
  69         if (!desc) {
  70                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
  71                 return NULL;
  72         }
  73
  74         irq_iommu = desc->irq_2_iommu;
  75
  76         if (!irq_iommu)
  77                 desc->irq_2_iommu = get_one_free_irq_2_iommu(node);
  78
  79         return desc->irq_2_iommu;
  80 }
  81
  82 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  83 {
  84         return irq_2_iommu_alloc_node(irq, cpu_to_node(boot_cpu_id));
  85 }
  86
  87 #else /* !CONFIG_SPARSE_IRQ */
  88
  89 static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
  90
  91 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  92 {
  93         if (irq < nr_irqs)
  94                 return &irq_2_iommuX[irq];
  95
  96         return NULL;
  97 }
  98 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  99 {
 100         return irq_2_iommu(irq);
 101 }
 102 #endif
 103
 104 static DEFINE_SPINLOCK(irq_2_ir_lock);
 105
 106 static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
 107 {
 108         struct irq_2_iommu *irq_iommu;
 109
 110         irq_iommu = irq_2_iommu(irq);
 111
 112         if (!irq_iommu)
 113                 return NULL;
 114
 115         if (!irq_iommu->iommu)
 116                 return NULL;
 117
 118         return irq_iommu;
 119 }
 120
 121 int irq_remapped(int irq)
 122 {
 123         return valid_irq_2_iommu(irq) != NULL;
 124 }
 125
 126 int get_irte(int irq, struct irte *entry)
 127 {
 128         int index;
 129         struct irq_2_iommu *irq_iommu;
 130         unsigned long flags;
 131
 132         if (!entry)
 133                 return -1;
 134
 135         spin_lock_irqsave(&irq_2_ir_lock, flags);
 136         irq_iommu = valid_irq_2_iommu(irq);
 137         if (!irq_iommu) {
 138                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 139                 return -1;
 140         }
 141
 142         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 143         *entry = *(irq_iommu->iommu->ir_table->base + index);
 144
 145         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 146         return 0;
 147 }
 148
 149 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
 150 {
 151         struct ir_table *table = iommu->ir_table;
 152         struct irq_2_iommu *irq_iommu;
 153         u16 index, start_index;
 154         unsigned int mask = 0;
 155         unsigned long flags;
 156         int i;
 157
 158         if (!count)
 159                 return -1;
 160
 161 #ifndef CONFIG_SPARSE_IRQ
 162         /* protect irq_2_iommu_alloc later */
 163         if (irq >= nr_irqs)
 164                 return -1;
 165 #endif
 166
 167         /*
 168          * start the IRTE search from index 0.
 169          */
 170         index = start_index = 0;
 171
 172         if (count > 1) {
 173                 count = __roundup_pow_of_two(count);
 174                 mask = ilog2(count);
 175         }
 176
 177         if (mask > ecap_max_handle_mask(iommu->ecap)) {
 178                 printk(KERN_ERR
 179                        "Requested mask %x exceeds the max invalidation handle"
 180                        " mask value %Lx\n", mask,
 181                        ecap_max_handle_mask(iommu->ecap));
 182                 return -1;
 183         }
 184
 185         spin_lock_irqsave(&irq_2_ir_lock, flags);
 186         do {
 187                 for (i = index; i < index + count; i++)
 188                         if  (table->base[i].present)
 189                                 break;
 190                 /* empty index found */
 191                 if (i == index + count)
 192                         break;
 193
 194                 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
 195
 196                 if (index == start_index) {
 197                         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 198                         printk(KERN_ERR "can't allocate an IRTE\n");
 199                         return -1;
 200                 }
 201         } while (1);
 202
 203         for (i = index; i < index + count; i++)
 204                 table->base[i].present = 1;
 205
 206         irq_iommu = irq_2_iommu_alloc(irq);
 207         if (!irq_iommu) {
 208                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 209                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 210                 return -1;
 211         }
 212
 213         irq_iommu->iommu = iommu;
 214         irq_iommu->irte_index =  index;
 215         irq_iommu->sub_handle = 0;
 216         irq_iommu->irte_mask = mask;
 217
 218         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 219
 220         return index;
 221 }
 222
 223 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
 224 {
 225         struct qi_desc desc;
 226
 227         desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
 228                    | QI_IEC_SELECTIVE;
 229         desc.high = 0;
 230
 231         return qi_submit_sync(&desc, iommu);
 232 }
 233
 234 int map_irq_to_irte_handle(int irq, u16 *sub_handle)
 235 {
 236         int index;
 237         struct irq_2_iommu *irq_iommu;
 238         unsigned long flags;
 239
 240         spin_lock_irqsave(&irq_2_ir_lock, flags);
 241         irq_iommu = valid_irq_2_iommu(irq);
 242         if (!irq_iommu) {
 243                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 244                 return -1;
 245         }
 246
 247         *sub_handle = irq_iommu->sub_handle;
 248         index = irq_iommu->irte_index;
 249         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 250         return index;
 251 }
 252
 253 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
 254 {
 255         struct irq_2_iommu *irq_iommu;
 256         unsigned long flags;
 257
 258         spin_lock_irqsave(&irq_2_ir_lock, flags);
 259
 260         irq_iommu = irq_2_iommu_alloc(irq);
 261
 262         if (!irq_iommu) {
 263                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 264                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 265                 return -1;
 266         }
 267
 268         irq_iommu->iommu = iommu;
 269         irq_iommu->irte_index = index;
 270         irq_iommu->sub_handle = subhandle;
 271         irq_iommu->irte_mask = 0;
 272
 273         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 274
 275         return 0;
 276 }
 277
 278 int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
 279 {
 280         struct irq_2_iommu *irq_iommu;
 281         unsigned long flags;
 282
 283         spin_lock_irqsave(&irq_2_ir_lock, flags);
 284         irq_iommu = valid_irq_2_iommu(irq);
 285         if (!irq_iommu) {
 286                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 287                 return -1;
 288         }
 289
 290         irq_iommu->iommu = NULL;
 291         irq_iommu->irte_index = 0;
 292         irq_iommu->sub_handle = 0;
 293         irq_2_iommu(irq)->irte_mask = 0;
 294
 295         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 296
 297         return 0;
 298 }
 299
 300 int modify_irte(int irq, struct irte *irte_modified)
 301 {
 302         int rc;
 303         int index;
 304         struct irte *irte;
 305         struct intel_iommu *iommu;
 306         struct irq_2_iommu *irq_iommu;
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&irq_2_ir_lock, flags);
 310         irq_iommu = valid_irq_2_iommu(irq);
 311         if (!irq_iommu) {
 312                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 313                 return -1;
 314         }
 315
 316         iommu = irq_iommu->iommu;
 317
 318         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 319         irte = &iommu->ir_table->base[index];
 320
 321         set_64bit((unsigned long *)&irte->low, irte_modified->low);
 322         set_64bit((unsigned long *)&irte->high, irte_modified->high);
 323         __iommu_flush_cache(iommu, irte, sizeof(*irte));
 324
 325         rc = qi_flush_iec(iommu, index, 0);
 326         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 327
 328         return rc;
 329 }
 330
 331 int flush_irte(int irq)
 332 {
 333         int rc;
 334         int index;
 335         struct intel_iommu *iommu;
 336         struct irq_2_iommu *irq_iommu;
 337         unsigned long flags;
 338
 339         spin_lock_irqsave(&irq_2_ir_lock, flags);
 340         irq_iommu = valid_irq_2_iommu(irq);
 341         if (!irq_iommu) {
 342                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 343                 return -1;
 344         }
 345
 346         iommu = irq_iommu->iommu;
 347
 348         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 349
 350         rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 351         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 352
 353         return rc;
 354 }
 355
 356 struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
 357 {
 358         int i;
 359
 360         for (i = 0; i < MAX_HPET_TBS; i++)
 361                 if (ir_hpet[i].id == hpet_id)
 362                         return ir_hpet[i].iommu;
 363         return NULL;
 364 }
 365
 366 struct intel_iommu *map_ioapic_to_ir(int apic)
 367 {
 368         int i;
 369
 370         for (i = 0; i < MAX_IO_APICS; i++)
 371                 if (ir_ioapic[i].id == apic)
 372                         return ir_ioapic[i].iommu;
 373         return NULL;
 374 }
 375
 376 struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
 377 {
 378         struct dmar_drhd_unit *drhd;
 379
 380         drhd = dmar_find_matched_drhd_unit(dev);
 381         if (!drhd)
 382                 return NULL;
 383
 384         return drhd->iommu;
 385 }
 386
 387 static int clear_entries(struct irq_2_iommu *irq_iommu)
 388 {
 389         struct irte *start, *entry, *end;
 390         struct intel_iommu *iommu;
 391         int index;
 392
 393         if (irq_iommu->sub_handle)
 394                 return 0;
 395
 396         iommu = irq_iommu->iommu;
 397         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 398
 399         start = iommu->ir_table->base + index;
 400         end = start + (1 << irq_iommu->irte_mask);
 401
 402         for (entry = start; entry < end; entry++) {
 403                 set_64bit((unsigned long *)&entry->low, 0);
 404                 set_64bit((unsigned long *)&entry->high, 0);
 405         }
 406
 407         return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 408 }
 409
 410 int free_irte(int irq)
 411 {
 412         int rc = 0;
 413         struct irq_2_iommu *irq_iommu;
 414         unsigned long flags;
 415
 416         spin_lock_irqsave(&irq_2_ir_lock, flags);
 417         irq_iommu = valid_irq_2_iommu(irq);
 418         if (!irq_iommu) {
 419                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 420                 return -1;
 421         }
 422
 423         rc = clear_entries(irq_iommu);
 424
 425         irq_iommu->iommu = NULL;
 426         irq_iommu->irte_index = 0;
 427         irq_iommu->sub_handle = 0;
 428         irq_iommu->irte_mask = 0;
 429
 430         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 431
 432         return rc;
 433 }
 434
 435 /*
 436  * source validation type
 437  */
 438 #define SVT_NO_VERIFY           0x0  /* no verification is required */
 439 #define SVT_VERIFY_SID_SQ       0x1  /* verify using SID and SQ fiels */
 440 #define SVT_VERIFY_BUS          0x2  /* verify bus of request-id */
 441
 442 /*
 443  * source-id qualifier
 444  */
 445 #define SQ_ALL_16       0x0  /* verify all 16 bits of request-id */
 446 #define SQ_13_IGNORE_1  0x1  /* verify most significant 13 bits, ignore
 447                               * the third least significant bit
 448                               */
 449 #define SQ_13_IGNORE_2  0x2  /* verify most significant 13 bits, ignore
 450                               * the second and third least significant bits
 451                               */
 452 #define SQ_13_IGNORE_3  0x3  /* verify most significant 13 bits, ignore
 453                               * the least three significant bits
 454                               */
 455
 456 /*
 457  * set SVT, SQ and SID fields of irte to verify
 458  * source ids of interrupt requests
 459  */
 460 static void set_irte_sid(struct irte *irte, unsigned int svt,
 461                          unsigned int sq, unsigned int sid)
 462 {
 463         irte->svt = svt;
 464         irte->sq = sq;
 465         irte->sid = sid;
 466 }
 467
 468 int set_ioapic_sid(struct irte *irte, int apic)
 469 {
 470         int i;
 471         u16 sid = 0;
 472
 473         if (!irte)
 474                 return -1;
 475
 476         for (i = 0; i < MAX_IO_APICS; i++) {
 477                 if (ir_ioapic[i].id == apic) {
 478                         sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
 479                         break;
 480                 }
 481         }
 482
 483         if (sid == 0) {
 484                 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
 485                 return -1;
 486         }
 487
 488         set_irte_sid(irte, 1, 0, sid);
 489
 490         return 0;
 491 }
 492
 493 int set_hpet_sid(struct irte *irte, u8 id)
 494 {
 495         int i;
 496         u16 sid = 0;
 497
 498         if (!irte)
 499                 return -1;
 500
 501         for (i = 0; i < MAX_HPET_TBS; i++) {
 502                 if (ir_hpet[i].id == id) {
 503                         sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
 504                         break;
 505                 }
 506         }
 507
 508         if (sid == 0) {
 509                 pr_warning("Failed to set source-id of HPET block (%d)\n", id);
 510                 return -1;
 511         }
 512
 513         /*
 514          * Should really use SQ_ALL_16. Some platforms are broken.
 515          * While we figure out the right quirks for these broken platforms, use
 516          * SQ_13_IGNORE_3 for now.
 517          */
 518         set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
 519
 520         return 0;
 521 }
 522
 523 int set_msi_sid(struct irte *irte, struct pci_dev *dev)
 524 {
 525         struct pci_dev *bridge;
 526
 527         if (!irte || !dev)
 528                 return -1;
 529
 530         /* PCIe device or Root Complex integrated PCI device */
 531         if (dev->is_pcie || !dev->bus->parent) {
 532                 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
 533                              (dev->bus->number << 8) | dev->devfn);
 534                 return 0;
 535         }
 536
 537         bridge = pci_find_upstream_pcie_bridge(dev);
 538         if (bridge) {
 539                 if (bridge->is_pcie) /* this is a PCIE-to-PCI/PCIX bridge */
 540                         set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
 541                                 (bridge->bus->number << 8) | dev->bus->number);
 542                 else /* this is a legacy PCI bridge */
 543                         set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
 544                                 (bridge->bus->number << 8) | bridge->devfn);
 545         }
 546
 547         return 0;
 548 }
 549
 550 static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 551 {
 552         u64 addr;
 553         u32 sts;
 554         unsigned long flags;
 555
 556         addr = virt_to_phys((void *)iommu->ir_table->base);
 557
 558         spin_lock_irqsave(&iommu->register_lock, flags);
 559
 560         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
 561                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
 562
 563         /* Set interrupt-remapping table pointer */
 564         iommu->gcmd |= DMA_GCMD_SIRTP;
 565         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 566
 567         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 568                       readl, (sts & DMA_GSTS_IRTPS), sts);
 569         spin_unlock_irqrestore(&iommu->register_lock, flags);
 570
 571         /*
 572          * global invalidation of interrupt entry cache before enabling
 573          * interrupt-remapping.
 574          */
 575         qi_global_iec(iommu);
 576
 577         spin_lock_irqsave(&iommu->register_lock, flags);
 578
 579         /* Enable interrupt-remapping */
 580         iommu->gcmd |= DMA_GCMD_IRE;
 581         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 582
 583         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 584                       readl, (sts & DMA_GSTS_IRES), sts);
 585
 586         spin_unlock_irqrestore(&iommu->register_lock, flags);
 587 }
 588
 589
 590 static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
 591 {
 592         struct ir_table *ir_table;
 593         struct page *pages;
 594
 595         ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
 596                                              GFP_ATOMIC);
 597
 598         if (!iommu->ir_table)
 599                 return -ENOMEM;
 600
 601         pages = alloc_pages(GFP_ATOMIC | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
 602
 603         if (!pages) {
 604                 printk(KERN_ERR "failed to allocate pages of order %d\n",
 605                        INTR_REMAP_PAGE_ORDER);
 606                 kfree(iommu->ir_table);
 607                 return -ENOMEM;
 608         }
 609
 610         ir_table->base = page_address(pages);
 611
 612         iommu_set_intr_remapping(iommu, mode);
 613         return 0;
 614 }
 615
 616 /*
 617  * Disable Interrupt Remapping.
 618  */
 619 static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
 620 {
 621         unsigned long flags;
 622         u32 sts;
 623
 624         if (!ecap_ir_support(iommu->ecap))
 625                 return;
 626
 627         /*
 628          * global invalidation of interrupt entry cache before disabling
 629          * interrupt-remapping.
 630          */
 631         qi_global_iec(iommu);
 632
 633         spin_lock_irqsave(&iommu->register_lock, flags);
 634
 635         sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
 636         if (!(sts & DMA_GSTS_IRES))
 637                 goto end;
 638
 639         iommu->gcmd &= ~DMA_GCMD_IRE;
 640         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 641
 642         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 643                       readl, !(sts & DMA_GSTS_IRES), sts);
 644
 645 end:
 646         spin_unlock_irqrestore(&iommu->register_lock, flags);
 647 }
 648
 649 int __init intr_remapping_supported(void)
 650 {
 651         struct dmar_drhd_unit *drhd;
 652
 653         if (disable_intremap)
 654                 return 0;
 655
 656         for_each_drhd_unit(drhd) {
 657                 struct intel_iommu *iommu = drhd->iommu;
 658
 659                 if (!ecap_ir_support(iommu->ecap))
 660                         return 0;
 661         }
 662
 663         return 1;
 664 }
 665
 666 int __init enable_intr_remapping(int eim)
 667 {
 668         struct dmar_drhd_unit *drhd;
 669         int setup = 0;
 670
 671         for_each_drhd_unit(drhd) {
 672                 struct intel_iommu *iommu = drhd->iommu;
 673
 674                 /*
 675                  * If the queued invalidation is already initialized,
 676                  * shouldn't disable it.
 677                  */
 678                 if (iommu->qi)
 679                         continue;
 680
 681                 /*
 682                  * Clear previous faults.
 683                  */
 684                 dmar_fault(-1, iommu);
 685
 686                 /*
 687                  * Disable intr remapping and queued invalidation, if already
 688                  * enabled prior to OS handover.
 689                  */
 690                 iommu_disable_intr_remapping(iommu);
 691
 692                 dmar_disable_qi(iommu);
 693         }
 694
 695         /*
 696          * check for the Interrupt-remapping support
 697          */
 698         for_each_drhd_unit(drhd) {
 699                 struct intel_iommu *iommu = drhd->iommu;
 700
 701                 if (!ecap_ir_support(iommu->ecap))
 702                         continue;
 703
 704                 if (eim && !ecap_eim_support(iommu->ecap)) {
 705                         printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
 706                                " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
 707                         return -1;
 708                 }
 709         }
 710
 711         /*
 712          * Enable queued invalidation for all the DRHD's.
 713          */
 714         for_each_drhd_unit(drhd) {
 715                 int ret;
 716                 struct intel_iommu *iommu = drhd->iommu;
 717                 ret = dmar_enable_qi(iommu);
 718
 719                 if (ret) {
 720                         printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
 721                                " invalidation, ecap %Lx, ret %d\n",
 722                                drhd->reg_base_addr, iommu->ecap, ret);
 723                         return -1;
 724                 }
 725         }
 726
 727         /*
 728          * Setup Interrupt-remapping for all the DRHD's now.
 729          */
 730         for_each_drhd_unit(drhd) {
 731                 struct intel_iommu *iommu = drhd->iommu;
 732
 733                 if (!ecap_ir_support(iommu->ecap))
 734                         continue;
 735
 736                 if (setup_intr_remapping(iommu, eim))
 737                         goto error;
 738
 739                 setup = 1;
 740         }
 741
 742         if (!setup)
 743                 goto error;
 744
 745         intr_remapping_enabled = 1;
 746
 747         return 0;
 748
 749 error:
 750         /*
 751          * handle error condition gracefully here!
 752          */
 753         return -1;
 754 }
 755
 756 static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
 757                                       struct intel_iommu *iommu)
 758 {
 759         struct acpi_dmar_pci_path *path;
 760         u8 bus;
 761         int count;
 762
 763         bus = scope->bus;
 764         path = (struct acpi_dmar_pci_path *)(scope + 1);
 765         count = (scope->length - sizeof(struct acpi_dmar_device_scope))
 766                 / sizeof(struct acpi_dmar_pci_path);
 767
 768         while (--count > 0) {
 769                 /*
 770                  * Access PCI directly due to the PCI
 771                  * subsystem isn't initialized yet.
 772                  */
 773                 bus = read_pci_config_byte(bus, path->dev, path->fn,
 774                                            PCI_SECONDARY_BUS);
 775                 path++;
 776         }
 777         ir_hpet[ir_hpet_num].bus   = bus;
 778         ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn);
 779         ir_hpet[ir_hpet_num].iommu = iommu;
 780         ir_hpet[ir_hpet_num].id    = scope->enumeration_id;
 781         ir_hpet_num++;
 782 }
 783
 784 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
 785                                       struct intel_iommu *iommu)
 786 {
 787         struct acpi_dmar_pci_path *path;
 788         u8 bus;
 789         int count;
 790
 791         bus = scope->bus;
 792         path = (struct acpi_dmar_pci_path *)(scope + 1);
 793         count = (scope->length - sizeof(struct acpi_dmar_device_scope))
 794                 / sizeof(struct acpi_dmar_pci_path);
 795
 796         while (--count > 0) {
 797                 /*
 798                  * Access PCI directly due to the PCI
 799                  * subsystem isn't initialized yet.
 800                  */
 801                 bus = read_pci_config_byte(bus, path->dev, path->fn,
 802                                            PCI_SECONDARY_BUS);
 803                 path++;
 804         }
 805
 806         ir_ioapic[ir_ioapic_num].bus   = bus;
 807         ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn);
 808         ir_ioapic[ir_ioapic_num].iommu = iommu;
 809         ir_ioapic[ir_ioapic_num].id    = scope->enumeration_id;
 810         ir_ioapic_num++;
 811 }
 812
 813 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
 814                                       struct intel_iommu *iommu)
 815 {
 816         struct acpi_dmar_hardware_unit *drhd;
 817         struct acpi_dmar_device_scope *scope;
 818         void *start, *end;
 819
 820         drhd = (struct acpi_dmar_hardware_unit *)header;
 821
 822         start = (void *)(drhd + 1);
 823         end = ((void *)drhd) + header->length;
 824
 825         while (start < end) {
 826                 scope = start;
 827                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
 828                         if (ir_ioapic_num == MAX_IO_APICS) {
 829                                 printk(KERN_WARNING "Exceeded Max IO APICS\n");
 830                                 return -1;
 831                         }
 832
 833                         printk(KERN_INFO "IOAPIC id %d under DRHD base"
 834                                " 0x%Lx\n", scope->enumeration_id,
 835                                drhd->address);
 836
 837                         ir_parse_one_ioapic_scope(scope, iommu);
 838                 } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
 839                         if (ir_hpet_num == MAX_HPET_TBS) {
 840                                 printk(KERN_WARNING "Exceeded Max HPET blocks\n");
 841                                 return -1;
 842                         }
 843
 844                         printk(KERN_INFO "HPET id %d under DRHD base"
 845                                " 0x%Lx\n", scope->enumeration_id,
 846                                drhd->address);
 847
 848                         ir_parse_one_hpet_scope(scope, iommu);
 849                 }
 850                 start += scope->length;
 851         }
 852
 853         return 0;
 854 }
 855
 856 /*
 857  * Finds the assocaition between IOAPIC's and its Interrupt-remapping
 858  * hardware unit.
 859  */
 860 int __init parse_ioapics_under_ir(void)
 861 {
 862         struct dmar_drhd_unit *drhd;
 863         int ir_supported = 0;
 864
 865         for_each_drhd_unit(drhd) {
 866                 struct intel_iommu *iommu = drhd->iommu;
 867
 868                 if (ecap_ir_support(iommu->ecap)) {
 869                         if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
 870                                 return -1;
 871
 872                         ir_supported = 1;
 873                 }
 874         }
 875
 876         if (ir_supported && ir_ioapic_num != nr_ioapics) {
 877                 printk(KERN_WARNING
 878                        "Not all IO-APIC's listed under remapping hardware\n");
 879                 return -1;
 880         }
 881
 882         return ir_supported;
 883 }
 884
 885 void disable_intr_remapping(void)
 886 {
 887         struct dmar_drhd_unit *drhd;
 888         struct intel_iommu *iommu = NULL;
 889
 890         /*
 891          * Disable Interrupt-remapping for all the DRHD's now.
 892          */
 893         for_each_iommu(iommu, drhd) {
 894                 if (!ecap_ir_support(iommu->ecap))
 895                         continue;
 896
 897                 iommu_disable_intr_remapping(iommu);
 898         }
 899 }
 900
 901 int reenable_intr_remapping(int eim)
 902 {
 903         struct dmar_drhd_unit *drhd;
 904         int setup = 0;
 905         struct intel_iommu *iommu = NULL;
 906
 907         for_each_iommu(iommu, drhd)
 908                 if (iommu->qi)
 909                         dmar_reenable_qi(iommu);
 910
 911         /*
 912          * Setup Interrupt-remapping for all the DRHD's now.
 913          */
 914         for_each_iommu(iommu, drhd) {
 915                 if (!ecap_ir_support(iommu->ecap))
 916                         continue;
 917
 918                 /* Set up interrupt remapping for iommu.*/
 919                 iommu_set_intr_remapping(iommu, eim);
 920                 setup = 1;
 921         }
 922
 923         if (!setup)
 924                 goto error;
 925
 926         return 0;
 927
 928 error:
 929         /*
 930          * handle error condition gracefully here!
 931          */
 932         return -1;
 933 }
 934