drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   3         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   4
   5         Based on the original rt2800pci.c and rt2800usb.c.
   6           Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   7           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   8           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   9           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  10           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  11           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  12           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  13           <http://rt2x00.serialmonkey.com>
  14
  15         This program is free software; you can redistribute it and/or modify
  16         it under the terms of the GNU General Public License as published by
  17         the Free Software Foundation; either version 2 of the License, or
  18         (at your option) any later version.
  19
  20         This program is distributed in the hope that it will be useful,
  21         but WITHOUT ANY WARRANTY; without even the implied warranty of
  22         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23         GNU General Public License for more details.
  24
  25         You should have received a copy of the GNU General Public License
  26         along with this program; if not, write to the
  27         Free Software Foundation, Inc.,
  28         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 /*
  32         Module: rt2800lib
  33         Abstract: rt2800 generic device routines.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38
  39 #include "rt2x00.h"
  40 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  41 #include "rt2x00usb.h"
  42 #endif
  43 #if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE)
  44 #include "rt2x00pci.h"
  45 #endif
  46 #include "rt2800lib.h"
  47 #include "rt2800.h"
  48 #include "rt2800usb.h"
  49
  50 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  51 MODULE_DESCRIPTION("rt2800 library");
  52 MODULE_LICENSE("GPL");
  53
  54 /*
  55  * Register access.
  56  * All access to the CSR registers will go through the methods
  57  * rt2800_register_read and rt2800_register_write.
  58  * BBP and RF register require indirect register access,
  59  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  60  * These indirect registers work with busy bits,
  61  * and we will try maximal REGISTER_BUSY_COUNT times to access
  62  * the register while taking a REGISTER_BUSY_DELAY us delay
  63  * between each attampt. When the busy bit is still set at that time,
  64  * the access attempt is considered to have failed,
  65  * and we will print an error.
  66  * The _lock versions must be used if you already hold the csr_mutex
  67  */
  68 #define WAIT_FOR_BBP(__dev, __reg) \
  69         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  70 #define WAIT_FOR_RFCSR(__dev, __reg) \
  71         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  72 #define WAIT_FOR_RF(__dev, __reg) \
  73         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  74 #define WAIT_FOR_MCU(__dev, __reg) \
  75         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  76                             H2M_MAILBOX_CSR_OWNER, (__reg))
  77
  78 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  79                              const unsigned int word, const u8 value)
  80 {
  81         u32 reg;
  82
  83         mutex_lock(&rt2x00dev->csr_mutex);
  84
  85         /*
  86          * Wait until the BBP becomes available, afterwards we
  87          * can safely write the new data into the register.
  88          */
  89         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  90                 reg = 0;
  91                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  92                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  93                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  94                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  95                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  96                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  97
  98                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  99         }
 100
 101         mutex_unlock(&rt2x00dev->csr_mutex);
 102 }
 103
 104 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 105                             const unsigned int word, u8 *value)
 106 {
 107         u32 reg;
 108
 109         mutex_lock(&rt2x00dev->csr_mutex);
 110
 111         /*
 112          * Wait until the BBP becomes available, afterwards we
 113          * can safely write the read request into the register.
 114          * After the data has been written, we wait until hardware
 115          * returns the correct value, if at any time the register
 116          * doesn't become available in time, reg will be 0xffffffff
 117          * which means we return 0xff to the caller.
 118          */
 119         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 120                 reg = 0;
 121                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 122                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 123                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 124                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 125                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 126
 127                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 128
 129                 WAIT_FOR_BBP(rt2x00dev, &reg);
 130         }
 131
 132         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 133
 134         mutex_unlock(&rt2x00dev->csr_mutex);
 135 }
 136
 137 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 138                                const unsigned int word, const u8 value)
 139 {
 140         u32 reg;
 141
 142         mutex_lock(&rt2x00dev->csr_mutex);
 143
 144         /*
 145          * Wait until the RFCSR becomes available, afterwards we
 146          * can safely write the new data into the register.
 147          */
 148         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 149                 reg = 0;
 150                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 151                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 152                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 153                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 154
 155                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 156         }
 157
 158         mutex_unlock(&rt2x00dev->csr_mutex);
 159 }
 160
 161 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 162                               const unsigned int word, u8 *value)
 163 {
 164         u32 reg;
 165
 166         mutex_lock(&rt2x00dev->csr_mutex);
 167
 168         /*
 169          * Wait until the RFCSR becomes available, afterwards we
 170          * can safely write the read request into the register.
 171          * After the data has been written, we wait until hardware
 172          * returns the correct value, if at any time the register
 173          * doesn't become available in time, reg will be 0xffffffff
 174          * which means we return 0xff to the caller.
 175          */
 176         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 177                 reg = 0;
 178                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 179                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 180                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 181
 182                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 183
 184                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 185         }
 186
 187         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 188
 189         mutex_unlock(&rt2x00dev->csr_mutex);
 190 }
 191
 192 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 193                             const unsigned int word, const u32 value)
 194 {
 195         u32 reg;
 196
 197         mutex_lock(&rt2x00dev->csr_mutex);
 198
 199         /*
 200          * Wait until the RF becomes available, afterwards we
 201          * can safely write the new data into the register.
 202          */
 203         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 204                 reg = 0;
 205                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 206                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 207                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 208                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 209
 210                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 211                 rt2x00_rf_write(rt2x00dev, word, value);
 212         }
 213
 214         mutex_unlock(&rt2x00dev->csr_mutex);
 215 }
 216
 217 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 218                         const u8 command, const u8 token,
 219                         const u8 arg0, const u8 arg1)
 220 {
 221         u32 reg;
 222
 223         /*
 224          * SOC devices don't support MCU requests.
 225          */
 226         if (rt2x00_is_soc(rt2x00dev))
 227                 return;
 228
 229         mutex_lock(&rt2x00dev->csr_mutex);
 230
 231         /*
 232          * Wait until the MCU becomes available, afterwards we
 233          * can safely write the new data into the register.
 234          */
 235         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 236                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 237                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 238                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 239                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 240                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 241
 242                 reg = 0;
 243                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 244                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 245         }
 246
 247         mutex_unlock(&rt2x00dev->csr_mutex);
 248 }
 249 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 250
 251 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 252 {
 253         unsigned int i;
 254         u32 reg;
 255
 256         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 257                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 258                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 259                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 260                         return 0;
 261
 262                 msleep(1);
 263         }
 264
 265         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 266         return -EACCES;
 267 }
 268 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 269
 270 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 271 const struct rt2x00debug rt2800_rt2x00debug = {
 272         .owner  = THIS_MODULE,
 273         .csr    = {
 274                 .read           = rt2800_register_read,
 275                 .write          = rt2800_register_write,
 276                 .flags          = RT2X00DEBUGFS_OFFSET,
 277                 .word_base      = CSR_REG_BASE,
 278                 .word_size      = sizeof(u32),
 279                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 280         },
 281         .eeprom = {
 282                 .read           = rt2x00_eeprom_read,
 283                 .write          = rt2x00_eeprom_write,
 284                 .word_base      = EEPROM_BASE,
 285                 .word_size      = sizeof(u16),
 286                 .word_count     = EEPROM_SIZE / sizeof(u16),
 287         },
 288         .bbp    = {
 289                 .read           = rt2800_bbp_read,
 290                 .write          = rt2800_bbp_write,
 291                 .word_base      = BBP_BASE,
 292                 .word_size      = sizeof(u8),
 293                 .word_count     = BBP_SIZE / sizeof(u8),
 294         },
 295         .rf     = {
 296                 .read           = rt2x00_rf_read,
 297                 .write          = rt2800_rf_write,
 298                 .word_base      = RF_BASE,
 299                 .word_size      = sizeof(u32),
 300                 .word_count     = RF_SIZE / sizeof(u32),
 301         },
 302 };
 303 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 304 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 305
 306 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 307 {
 308         u32 reg;
 309
 310         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 311         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 312 }
 313 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 314
 315 #ifdef CONFIG_RT2X00_LIB_LEDS
 316 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 317                                   enum led_brightness brightness)
 318 {
 319         struct rt2x00_led *led =
 320             container_of(led_cdev, struct rt2x00_led, led_dev);
 321         unsigned int enabled = brightness != LED_OFF;
 322         unsigned int bg_mode =
 323             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 324         unsigned int polarity =
 325                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 326                                    EEPROM_FREQ_LED_POLARITY);
 327         unsigned int ledmode =
 328                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 329                                    EEPROM_FREQ_LED_MODE);
 330
 331         if (led->type == LED_TYPE_RADIO) {
 332                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 333                                       enabled ? 0x20 : 0);
 334         } else if (led->type == LED_TYPE_ASSOC) {
 335                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 336                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 337         } else if (led->type == LED_TYPE_QUALITY) {
 338                 /*
 339                  * The brightness is divided into 6 levels (0 - 5),
 340                  * The specs tell us the following levels:
 341                  *      0, 1 ,3, 7, 15, 31
 342                  * to determine the level in a simple way we can simply
 343                  * work with bitshifting:
 344                  *      (1 << level) - 1
 345                  */
 346                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 347                                       (1 << brightness / (LED_FULL / 6)) - 1,
 348                                       polarity);
 349         }
 350 }
 351
 352 static int rt2800_blink_set(struct led_classdev *led_cdev,
 353                             unsigned long *delay_on, unsigned long *delay_off)
 354 {
 355         struct rt2x00_led *led =
 356             container_of(led_cdev, struct rt2x00_led, led_dev);
 357         u32 reg;
 358
 359         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 360         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 361         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 362         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 363
 364         return 0;
 365 }
 366
 367 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 368                      struct rt2x00_led *led, enum led_type type)
 369 {
 370         led->rt2x00dev = rt2x00dev;
 371         led->type = type;
 372         led->led_dev.brightness_set = rt2800_brightness_set;
 373         led->led_dev.blink_set = rt2800_blink_set;
 374         led->flags = LED_INITIALIZED;
 375 }
 376 #endif /* CONFIG_RT2X00_LIB_LEDS */
 377
 378 /*
 379  * Configuration handlers.
 380  */
 381 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 382                                     struct rt2x00lib_crypto *crypto,
 383                                     struct ieee80211_key_conf *key)
 384 {
 385         struct mac_wcid_entry wcid_entry;
 386         struct mac_iveiv_entry iveiv_entry;
 387         u32 offset;
 388         u32 reg;
 389
 390         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 391
 392         rt2800_register_read(rt2x00dev, offset, &reg);
 393         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 394                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 395         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 396                            (crypto->cmd == SET_KEY) * crypto->cipher);
 397         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 398                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 399         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 400         rt2800_register_write(rt2x00dev, offset, reg);
 401
 402         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 403
 404         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 405         if ((crypto->cipher == CIPHER_TKIP) ||
 406             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 407             (crypto->cipher == CIPHER_AES))
 408                 iveiv_entry.iv[3] |= 0x20;
 409         iveiv_entry.iv[3] |= key->keyidx << 6;
 410         rt2800_register_multiwrite(rt2x00dev, offset,
 411                                       &iveiv_entry, sizeof(iveiv_entry));
 412
 413         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 414
 415         memset(&wcid_entry, 0, sizeof(wcid_entry));
 416         if (crypto->cmd == SET_KEY)
 417                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 418         rt2800_register_multiwrite(rt2x00dev, offset,
 419                                       &wcid_entry, sizeof(wcid_entry));
 420 }
 421
 422 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 423                              struct rt2x00lib_crypto *crypto,
 424                              struct ieee80211_key_conf *key)
 425 {
 426         struct hw_key_entry key_entry;
 427         struct rt2x00_field32 field;
 428         u32 offset;
 429         u32 reg;
 430
 431         if (crypto->cmd == SET_KEY) {
 432                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 433
 434                 memcpy(key_entry.key, crypto->key,
 435                        sizeof(key_entry.key));
 436                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 437                        sizeof(key_entry.tx_mic));
 438                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 439                        sizeof(key_entry.rx_mic));
 440
 441                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 442                 rt2800_register_multiwrite(rt2x00dev, offset,
 443                                               &key_entry, sizeof(key_entry));
 444         }
 445
 446         /*
 447          * The cipher types are stored over multiple registers
 448          * starting with SHARED_KEY_MODE_BASE each word will have
 449          * 32 bits and contains the cipher types for 2 bssidx each.
 450          * Using the correct defines correctly will cause overhead,
 451          * so just calculate the correct offset.
 452          */
 453         field.bit_offset = 4 * (key->hw_key_idx % 8);
 454         field.bit_mask = 0x7 << field.bit_offset;
 455
 456         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 457
 458         rt2800_register_read(rt2x00dev, offset, &reg);
 459         rt2x00_set_field32(&reg, field,
 460                            (crypto->cmd == SET_KEY) * crypto->cipher);
 461         rt2800_register_write(rt2x00dev, offset, reg);
 462
 463         /*
 464          * Update WCID information
 465          */
 466         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 467
 468         return 0;
 469 }
 470 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 471
 472 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 473                                struct rt2x00lib_crypto *crypto,
 474                                struct ieee80211_key_conf *key)
 475 {
 476         struct hw_key_entry key_entry;
 477         u32 offset;
 478
 479         if (crypto->cmd == SET_KEY) {
 480                 /*
 481                  * 1 pairwise key is possible per AID, this means that the AID
 482                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 483                  * last possible shared key entry.
 484                  */
 485                 if (crypto->aid > (256 - 32))
 486                         return -ENOSPC;
 487
 488                 key->hw_key_idx = 32 + crypto->aid;
 489
 490                 memcpy(key_entry.key, crypto->key,
 491                        sizeof(key_entry.key));
 492                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 493                        sizeof(key_entry.tx_mic));
 494                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 495                        sizeof(key_entry.rx_mic));
 496
 497                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 498                 rt2800_register_multiwrite(rt2x00dev, offset,
 499                                               &key_entry, sizeof(key_entry));
 500         }
 501
 502         /*
 503          * Update WCID information
 504          */
 505         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 506
 507         return 0;
 508 }
 509 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
 510
 511 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
 512                           const unsigned int filter_flags)
 513 {
 514         u32 reg;
 515
 516         /*
 517          * Start configuration steps.
 518          * Note that the version error will always be dropped
 519          * and broadcast frames will always be accepted since
 520          * there is no filter for it at this time.
 521          */
 522         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 523         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 524                            !(filter_flags & FIF_FCSFAIL));
 525         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 526                            !(filter_flags & FIF_PLCPFAIL));
 527         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 528                            !(filter_flags & FIF_PROMISC_IN_BSS));
 529         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 530         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 531         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 532                            !(filter_flags & FIF_ALLMULTI));
 533         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 534         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 535         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 536                            !(filter_flags & FIF_CONTROL));
 537         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 538                            !(filter_flags & FIF_CONTROL));
 539         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 540                            !(filter_flags & FIF_CONTROL));
 541         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 542                            !(filter_flags & FIF_CONTROL));
 543         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 544                            !(filter_flags & FIF_CONTROL));
 545         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 546                            !(filter_flags & FIF_PSPOLL));
 547         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 548         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 549         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 550                            !(filter_flags & FIF_CONTROL));
 551         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 552 }
 553 EXPORT_SYMBOL_GPL(rt2800_config_filter);
 554
 555 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
 556                         struct rt2x00intf_conf *conf, const unsigned int flags)
 557 {
 558         unsigned int beacon_base;
 559         u32 reg;
 560
 561         if (flags & CONFIG_UPDATE_TYPE) {
 562                 /*
 563                  * Clear current synchronisation setup.
 564                  * For the Beacon base registers we only need to clear
 565                  * the first byte since that byte contains the VALID and OWNER
 566                  * bits which (when set to 0) will invalidate the entire beacon.
 567                  */
 568                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 569                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 570
 571                 /*
 572                  * Enable synchronisation.
 573                  */
 574                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 575                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 576                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 577                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
 578                                    (conf->sync == TSF_SYNC_BEACON));
 579                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 580         }
 581
 582         if (flags & CONFIG_UPDATE_MAC) {
 583                 reg = le32_to_cpu(conf->mac[1]);
 584                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 585                 conf->mac[1] = cpu_to_le32(reg);
 586
 587                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 588                                               conf->mac, sizeof(conf->mac));
 589         }
 590
 591         if (flags & CONFIG_UPDATE_BSSID) {
 592                 reg = le32_to_cpu(conf->bssid[1]);
 593                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 594                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 595                 conf->bssid[1] = cpu_to_le32(reg);
 596
 597                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 598                                               conf->bssid, sizeof(conf->bssid));
 599         }
 600 }
 601 EXPORT_SYMBOL_GPL(rt2800_config_intf);
 602
 603 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
 604 {
 605         u32 reg;
 606
 607         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 608         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 609                            !!erp->short_preamble);
 610         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 611                            !!erp->short_preamble);
 612         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 613
 614         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 615         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 616                            erp->cts_protection ? 2 : 0);
 617         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 618
 619         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 620                                  erp->basic_rates);
 621         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 622
 623         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 624         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 625         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 626
 627         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 628         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 629         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 630         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 631         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 632
 633         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 634         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 635                            erp->beacon_int * 16);
 636         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 637 }
 638 EXPORT_SYMBOL_GPL(rt2800_config_erp);
 639
 640 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 641 {
 642         u8 r1;
 643         u8 r3;
 644
 645         rt2800_bbp_read(rt2x00dev, 1, &r1);
 646         rt2800_bbp_read(rt2x00dev, 3, &r3);
 647
 648         /*
 649          * Configure the TX antenna.
 650          */
 651         switch ((int)ant->tx) {
 652         case 1:
 653                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 654                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 655                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 656                 break;
 657         case 2:
 658                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 659                 break;
 660         case 3:
 661                 /* Do nothing */
 662                 break;
 663         }
 664
 665         /*
 666          * Configure the RX antenna.
 667          */
 668         switch ((int)ant->rx) {
 669         case 1:
 670                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 671                 break;
 672         case 2:
 673                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 674                 break;
 675         case 3:
 676                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 677                 break;
 678         }
 679
 680         rt2800_bbp_write(rt2x00dev, 3, r3);
 681         rt2800_bbp_write(rt2x00dev, 1, r1);
 682 }
 683 EXPORT_SYMBOL_GPL(rt2800_config_ant);
 684
 685 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 686                                    struct rt2x00lib_conf *libconf)
 687 {
 688         u16 eeprom;
 689         short lna_gain;
 690
 691         if (libconf->rf.channel <= 14) {
 692                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 693                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 694         } else if (libconf->rf.channel <= 64) {
 695                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 696                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 697         } else if (libconf->rf.channel <= 128) {
 698                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 699                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 700         } else {
 701                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 702                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 703         }
 704
 705         rt2x00dev->lna_gain = lna_gain;
 706 }
 707
 708 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
 709                                          struct ieee80211_conf *conf,
 710                                          struct rf_channel *rf,
 711                                          struct channel_info *info)
 712 {
 713         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 714
 715         if (rt2x00dev->default_ant.tx == 1)
 716                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 717
 718         if (rt2x00dev->default_ant.rx == 1) {
 719                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 720                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 721         } else if (rt2x00dev->default_ant.rx == 2)
 722                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 723
 724         if (rf->channel > 14) {
 725                 /*
 726                  * When TX power is below 0, we should increase it by 7 to
 727                  * make it a positive value (Minumum value is -7).
 728                  * However this means that values between 0 and 7 have
 729                  * double meaning, and we should set a 7DBm boost flag.
 730                  */
 731                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 732                                    (info->tx_power1 >= 0));
 733
 734                 if (info->tx_power1 < 0)
 735                         info->tx_power1 += 7;
 736
 737                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 738                                    TXPOWER_A_TO_DEV(info->tx_power1));
 739
 740                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 741                                    (info->tx_power2 >= 0));
 742
 743                 if (info->tx_power2 < 0)
 744                         info->tx_power2 += 7;
 745
 746                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 747                                    TXPOWER_A_TO_DEV(info->tx_power2));
 748         } else {
 749                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 750                                    TXPOWER_G_TO_DEV(info->tx_power1));
 751                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 752                                    TXPOWER_G_TO_DEV(info->tx_power2));
 753         }
 754
 755         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 756
 757         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 758         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 759         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 760         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 761
 762         udelay(200);
 763
 764         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 765         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 766         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 767         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 768
 769         udelay(200);
 770
 771         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 772         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 773         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 774         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 775 }
 776
 777 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
 778                                          struct ieee80211_conf *conf,
 779                                          struct rf_channel *rf,
 780                                          struct channel_info *info)
 781 {
 782         u8 rfcsr;
 783
 784         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 785         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
 786
 787         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 788         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
 789         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 790
 791         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 792         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 793                           TXPOWER_G_TO_DEV(info->tx_power1));
 794         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 795
 796         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 797         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 798         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 799
 800         rt2800_rfcsr_write(rt2x00dev, 24,
 801                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 802
 803         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
 804         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 805         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
 806 }
 807
 808 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 809                                   struct ieee80211_conf *conf,
 810                                   struct rf_channel *rf,
 811                                   struct channel_info *info)
 812 {
 813         u32 reg;
 814         unsigned int tx_pin;
 815         u8 bbp;
 816
 817         if (rt2x00_rf(rt2x00dev, RF2020) ||
 818             rt2x00_rf(rt2x00dev, RF3020) ||
 819             rt2x00_rf(rt2x00dev, RF3021) ||
 820             rt2x00_rf(rt2x00dev, RF3022))
 821                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
 822         else
 823                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
 824
 825         /*
 826          * Change BBP settings
 827          */
 828         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 829         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 830         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 831         rt2800_bbp_write(rt2x00dev, 86, 0);
 832
 833         if (rf->channel <= 14) {
 834                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 835                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 836                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 837                 } else {
 838                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 839                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 840                 }
 841         } else {
 842                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 843
 844                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 845                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 846                 else
 847                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 848         }
 849
 850         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 851         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 852         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 853         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 854         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 855
 856         tx_pin = 0;
 857
 858         /* Turn on unused PA or LNA when not using 1T or 1R */
 859         if (rt2x00dev->default_ant.tx != 1) {
 860                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 861                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 862         }
 863
 864         /* Turn on unused PA or LNA when not using 1T or 1R */
 865         if (rt2x00dev->default_ant.rx != 1) {
 866                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 867                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 868         }
 869
 870         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 871         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 872         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 873         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 874         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 875         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 876
 877         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 878
 879         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 880         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 881         rt2800_bbp_write(rt2x00dev, 4, bbp);
 882
 883         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 884         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 885         rt2800_bbp_write(rt2x00dev, 3, bbp);
 886
 887         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
 888                 if (conf_is_ht40(conf)) {
 889                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 890                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 891                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 892                 } else {
 893                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 894                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 895                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 896                 }
 897         }
 898
 899         msleep(1);
 900 }
 901
 902 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 903                                   const int txpower)
 904 {
 905         u32 reg;
 906         u32 value = TXPOWER_G_TO_DEV(txpower);
 907         u8 r1;
 908
 909         rt2800_bbp_read(rt2x00dev, 1, &r1);
 910         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 911         rt2800_bbp_write(rt2x00dev, 1, r1);
 912
 913         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 914         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 915         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 916         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 917         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 920         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 921         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 922         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 923
 924         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 925         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 926         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 927         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 928         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 933         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 934
 935         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 937         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 938         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 939         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 942         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 943         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 944         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 945
 946         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 947         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 948         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 949         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 950         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 951         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 952         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 953         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 954         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 955         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 956
 957         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 958         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 959         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 960         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 961         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 962         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 963 }
 964
 965 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 966                                       struct rt2x00lib_conf *libconf)
 967 {
 968         u32 reg;
 969
 970         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 971         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 972                            libconf->conf->short_frame_max_tx_count);
 973         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 974                            libconf->conf->long_frame_max_tx_count);
 975         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 976 }
 977
 978 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
 979                              struct rt2x00lib_conf *libconf)
 980 {
 981         enum dev_state state =
 982             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 983                 STATE_SLEEP : STATE_AWAKE;
 984         u32 reg;
 985
 986         if (state == STATE_SLEEP) {
 987                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 988
 989                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 990                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 991                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 992                                    libconf->conf->listen_interval - 1);
 993                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
 994                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 995
 996                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 997         } else {
 998                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 999                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1000                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1001                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1002                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1003
1004                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1005         }
1006 }
1007
1008 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1009                    struct rt2x00lib_conf *libconf,
1010                    const unsigned int flags)
1011 {
1012         /* Always recalculate LNA gain before changing configuration */
1013         rt2800_config_lna_gain(rt2x00dev, libconf);
1014
1015         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1016                 rt2800_config_channel(rt2x00dev, libconf->conf,
1017                                       &libconf->rf, &libconf->channel);
1018         if (flags & IEEE80211_CONF_CHANGE_POWER)
1019                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1020         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1021                 rt2800_config_retry_limit(rt2x00dev, libconf);
1022         if (flags & IEEE80211_CONF_CHANGE_PS)
1023                 rt2800_config_ps(rt2x00dev, libconf);
1024 }
1025 EXPORT_SYMBOL_GPL(rt2800_config);
1026
1027 /*
1028  * Link tuning
1029  */
1030 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1031 {
1032         u32 reg;
1033
1034         /*
1035          * Update FCS error count from register.
1036          */
1037         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1038         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1039 }
1040 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1041
1042 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1043 {
1044         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1045                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1046                     rt2x00_rt(rt2x00dev, RT3071) ||
1047                     rt2x00_rt(rt2x00dev, RT3090))
1048                         return 0x1c + (2 * rt2x00dev->lna_gain);
1049                 else
1050                         return 0x2e + rt2x00dev->lna_gain;
1051         }
1052
1053         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1054                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1055         else
1056                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1057 }
1058
1059 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1060                                   struct link_qual *qual, u8 vgc_level)
1061 {
1062         if (qual->vgc_level != vgc_level) {
1063                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1064                 qual->vgc_level = vgc_level;
1065                 qual->vgc_level_reg = vgc_level;
1066         }
1067 }
1068
1069 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1070 {
1071         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1072 }
1073 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1074
1075 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1076                        const u32 count)
1077 {
1078         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1079                 return;
1080
1081         /*
1082          * When RSSI is better then -80 increase VGC level with 0x10
1083          */
1084         rt2800_set_vgc(rt2x00dev, qual,
1085                        rt2800_get_default_vgc(rt2x00dev) +
1086                        ((qual->rssi > -80) * 0x10));
1087 }
1088 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1089
1090 /*
1091  * Initialization functions.
1092  */
1093 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1094 {
1095         u32 reg;
1096         u16 eeprom;
1097         unsigned int i;
1098
1099         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1100         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1101         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1102         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1103         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1104         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1105         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1106
1107         if (rt2x00_is_usb(rt2x00dev)) {
1108                 /*
1109                  * Wait until BBP and RF are ready.
1110                  */
1111                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1112                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1113                         if (reg && reg != ~0)
1114                                 break;
1115                         msleep(1);
1116                 }
1117
1118                 if (i == REGISTER_BUSY_COUNT) {
1119                         ERROR(rt2x00dev, "Unstable hardware.\n");
1120                         return -EBUSY;
1121                 }
1122
1123                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1124                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1125                                       reg & ~0x00002000);
1126         } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1127                 /*
1128                  * Reset DMA indexes
1129                  */
1130                 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1131                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1132                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1133                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1134                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1135                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1136                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1137                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1138                 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1139
1140                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1141                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1142
1143                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1144         }
1145
1146         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1147         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1148         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1149         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1150
1151         if (rt2x00_is_usb(rt2x00dev)) {
1152                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1153 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1154                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1155                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1156 #endif
1157         }
1158
1159         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1160
1161         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1162         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1163         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1164         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1165         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1166         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1167
1168         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1169         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1170         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1171         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1172         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1173         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1174
1175         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1176         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1177
1178         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1179
1180         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1181         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1182         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1183         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1184         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1185         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1186         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1187         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1188
1189         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1190
1191         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1192         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1193         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1194         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1195
1196         if (rt2x00_rt(rt2x00dev, RT3071) ||
1197             rt2x00_rt(rt2x00dev, RT3090)) {
1198                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1199                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1200                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1201                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1202                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1203                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1204                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1205                                                       0x0000002c);
1206                         else
1207                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1208                                                       0x0000000f);
1209                 } else {
1210                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1211                 }
1212                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
1213         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1214                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1215
1216                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1217                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1218                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1219                 } else {
1220                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1221                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1222                 }
1223         } else {
1224                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1225                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1226         }
1227
1228         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1229         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1230         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1231         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1232         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1233         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1234         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1235         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1236         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1237         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1238
1239         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1240         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1241         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1242         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1243         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1244
1245         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1246         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1247         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1248             rt2x00_rt(rt2x00dev, RT2883) ||
1249             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1250                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1251         else
1252                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1253         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1254         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1255         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1256
1257         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1258         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1259         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1260         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1261         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1262         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1263         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1264         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1265         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1266
1267         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1268
1269         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1270         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1271         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1272         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1273         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1274         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1275         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1276         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1277
1278         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1279         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1280         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1281         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1282         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1283         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1284         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1285         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1286         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1287
1288         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1289         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1290         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1291         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1292         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1293         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1294         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1295         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1296         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1297         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1298         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1299         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1300
1301         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1302         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1303         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1304         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1305         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1306         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1307         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1308         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1309         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1310         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1311         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1312         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1313
1314         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1315         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1316         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1317         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1318         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1319         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1320         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1321         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1322         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1323         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1324         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1325         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1326
1327         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1328         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1329         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1330                            !rt2x00_is_usb(rt2x00dev));
1331         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1332         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1333         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1334         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1335         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1336         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1337         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1338         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1339         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1340
1341         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1342         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1343         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1344         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1345         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1346         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1347         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1348         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1349         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1350         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1351         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1352         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1353
1354         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1355         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1356         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1357         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1358         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1359         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1360         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1361         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1362         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1363         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1364         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1365         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1366
1367         if (rt2x00_is_usb(rt2x00dev)) {
1368                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1369
1370                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1371                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1372                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1373                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1374                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1375                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1376                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1377                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1378                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1379                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1380                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1381         }
1382
1383         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1384         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1385
1386         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1387         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1388         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1389                            IEEE80211_MAX_RTS_THRESHOLD);
1390         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1391         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1392
1393         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1394
1395         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1396         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 32);
1397         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 32);
1398         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1399         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1400         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1401         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1402
1403         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1404
1405         /*
1406          * ASIC will keep garbage value after boot, clear encryption keys.
1407          */
1408         for (i = 0; i < 4; i++)
1409                 rt2800_register_write(rt2x00dev,
1410                                          SHARED_KEY_MODE_ENTRY(i), 0);
1411
1412         for (i = 0; i < 256; i++) {
1413                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1414                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1415                                               wcid, sizeof(wcid));
1416
1417                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1418                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1419         }
1420
1421         /*
1422          * Clear all beacons
1423          * For the Beacon base registers we only need to clear
1424          * the first byte since that byte contains the VALID and OWNER
1425          * bits which (when set to 0) will invalidate the entire beacon.
1426          */
1427         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1428         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1429         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1430         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1431         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1432         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1433         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1434         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1435
1436         if (rt2x00_is_usb(rt2x00dev)) {
1437                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1438                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1439                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1440         }
1441
1442         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1443         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1444         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1445         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1446         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1447         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1448         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1449         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1450         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1451         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1452
1453         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1454         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1455         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1456         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1457         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1458         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1459         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1460         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1461         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1462         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1463
1464         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1465         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1466         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1467         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1468         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1469         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1470         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1471         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1472         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1473         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1474
1475         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1476         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1477         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1478         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1479         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1480         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1481
1482         /*
1483          * We must clear the error counters.
1484          * These registers are cleared on read,
1485          * so we may pass a useless variable to store the value.
1486          */
1487         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1488         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1489         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1490         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1491         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1492         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1493
1494         return 0;
1495 }
1496 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1497
1498 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1499 {
1500         unsigned int i;
1501         u32 reg;
1502
1503         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1504                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1505                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1506                         return 0;
1507
1508                 udelay(REGISTER_BUSY_DELAY);
1509         }
1510
1511         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1512         return -EACCES;
1513 }
1514
1515 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1516 {
1517         unsigned int i;
1518         u8 value;
1519
1520         /*
1521          * BBP was enabled after firmware was loaded,
1522          * but we need to reactivate it now.
1523          */
1524         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1525         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1526         msleep(1);
1527
1528         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1529                 rt2800_bbp_read(rt2x00dev, 0, &value);
1530                 if ((value != 0xff) && (value != 0x00))
1531                         return 0;
1532                 udelay(REGISTER_BUSY_DELAY);
1533         }
1534
1535         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1536         return -EACCES;
1537 }
1538
1539 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1540 {
1541         unsigned int i;
1542         u16 eeprom;
1543         u8 reg_id;
1544         u8 value;
1545
1546         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1547                      rt2800_wait_bbp_ready(rt2x00dev)))
1548                 return -EACCES;
1549
1550         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1551         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1552
1553         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1554                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1555                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1556         } else {
1557                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1558                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1559         }
1560
1561         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1562
1563         if (rt2x00_rt(rt2x00dev, RT3070) ||
1564             rt2x00_rt(rt2x00dev, RT3071) ||
1565             rt2x00_rt(rt2x00dev, RT3090)) {
1566                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1567                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1568                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1569         } else {
1570                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1571         }
1572
1573         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1574         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1575
1576         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) ||
1577             rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D))
1578                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1579         else
1580                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1581
1582         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1583         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1584         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1585
1586         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
1587             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
1588             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
1589                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1590         else
1591                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1592
1593         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1594         rt2800_bbp_write(rt2x00dev, 106, 0x35);
1595
1596         if (rt2x00_rt(rt2x00dev, RT3071) ||
1597             rt2x00_rt(rt2x00dev, RT3090)) {
1598                 rt2800_bbp_read(rt2x00dev, 138, &value);
1599
1600                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1601                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1602                         value |= 0x20;
1603                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1604                         value &= ~0x02;
1605
1606                 rt2800_bbp_write(rt2x00dev, 138, value);
1607         }
1608
1609         if (rt2x00_rt(rt2x00dev, RT2872)) {
1610                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1611                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1612                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1613         }
1614
1615         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1616                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1617
1618                 if (eeprom != 0xffff && eeprom != 0x0000) {
1619                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1620                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1621                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1622                 }
1623         }
1624
1625         return 0;
1626 }
1627 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1628
1629 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1630                                 bool bw40, u8 rfcsr24, u8 filter_target)
1631 {
1632         unsigned int i;
1633         u8 bbp;
1634         u8 rfcsr;
1635         u8 passband;
1636         u8 stopband;
1637         u8 overtuned = 0;
1638
1639         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1640
1641         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1642         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1643         rt2800_bbp_write(rt2x00dev, 4, bbp);
1644
1645         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1646         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1647         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1648
1649         /*
1650          * Set power & frequency of passband test tone
1651          */
1652         rt2800_bbp_write(rt2x00dev, 24, 0);
1653
1654         for (i = 0; i < 100; i++) {
1655                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1656                 msleep(1);
1657
1658                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1659                 if (passband)
1660                         break;
1661         }
1662
1663         /*
1664          * Set power & frequency of stopband test tone
1665          */
1666         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1667
1668         for (i = 0; i < 100; i++) {
1669                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1670                 msleep(1);
1671
1672                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1673
1674                 if ((passband - stopband) <= filter_target) {
1675                         rfcsr24++;
1676                         overtuned += ((passband - stopband) == filter_target);
1677                 } else
1678                         break;
1679
1680                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1681         }
1682
1683         rfcsr24 -= !!overtuned;
1684
1685         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1686         return rfcsr24;
1687 }
1688
1689 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1690 {
1691         u8 rfcsr;
1692         u8 bbp;
1693         u32 reg;
1694         u16 eeprom;
1695
1696         if (!rt2x00_rt(rt2x00dev, RT3070) &&
1697             !rt2x00_rt(rt2x00dev, RT3071) &&
1698             !rt2x00_rt(rt2x00dev, RT3090))
1699                 return 0;
1700
1701         /*
1702          * Init RF calibration.
1703          */
1704         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1705         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1706         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1707         msleep(1);
1708         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1709         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1710
1711         if (rt2x00_rt(rt2x00dev, RT3070) ||
1712             rt2x00_rt(rt2x00dev, RT3071) ||
1713             rt2x00_rt(rt2x00dev, RT3090)) {
1714                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1715                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1716                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1717                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1718                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1719                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
1720                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1721                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1722                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1723                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1724                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1725                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1726                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1727                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1728                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1729                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1730                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1731                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1732                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1733         }
1734
1735         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1736                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1737                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1738                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1739                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1740         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1741                    rt2x00_rt(rt2x00dev, RT3090)) {
1742                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1743                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1744                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1745
1746                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1747
1748                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1749                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1750                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1751                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1752                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1753                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1754                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1755                         else
1756                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1757                 }
1758                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1759         }
1760
1761         /*
1762          * Set RX Filter calibration for 20MHz and 40MHz
1763          */
1764         if (rt2x00_rt(rt2x00dev, RT3070)) {
1765                 rt2x00dev->calibration[0] =
1766                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1767                 rt2x00dev->calibration[1] =
1768                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1769         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1770                    rt2x00_rt(rt2x00dev, RT3090)) {
1771                 rt2x00dev->calibration[0] =
1772                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1773                 rt2x00dev->calibration[1] =
1774                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
1775         }
1776
1777         /*
1778          * Set back to initial state
1779          */
1780         rt2800_bbp_write(rt2x00dev, 24, 0);
1781
1782         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1783         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1784         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1785
1786         /*
1787          * set BBP back to BW20
1788          */
1789         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1790         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1791         rt2800_bbp_write(rt2x00dev, 4, bbp);
1792
1793         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1794             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1795             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
1796                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1797
1798         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
1799         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
1800         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
1801
1802         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1803         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
1804         if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1805             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1806                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1807                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1808                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
1809         }
1810         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
1811         if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
1812                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
1813                                   rt2x00_get_field16(eeprom,
1814                                                    EEPROM_TXMIXER_GAIN_BG_VAL));
1815         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1816
1817         if (rt2x00_rt(rt2x00dev, RT3090)) {
1818                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
1819
1820                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1821                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1822                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
1823                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1824                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
1825
1826                 rt2800_bbp_write(rt2x00dev, 138, bbp);
1827         }
1828
1829         if (rt2x00_rt(rt2x00dev, RT3071) ||
1830             rt2x00_rt(rt2x00dev, RT3090)) {
1831                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1832                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1833                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1834                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1835                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1836                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1837                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1838
1839                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
1840                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
1841                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
1842
1843                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
1844                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
1845                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
1846
1847                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
1848                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
1849                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
1850         }
1851
1852         if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
1853                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
1854                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1855                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
1856                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
1857                 else
1858                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
1859                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
1860                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
1861                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
1862                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
1863         }
1864
1865         return 0;
1866 }
1867 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1868
1869 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1870 {
1871         u32 reg;
1872
1873         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1874
1875         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1876 }
1877 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1878
1879 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1880 {
1881         u32 reg;
1882
1883         mutex_lock(&rt2x00dev->csr_mutex);
1884
1885         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
1886         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1887         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1888         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1889         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
1890
1891         /* Wait until the EEPROM has been loaded */
1892         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1893
1894         /* Apparently the data is read from end to start */
1895         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
1896                                         (u32 *)&rt2x00dev->eeprom[i]);
1897         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
1898                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
1899         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
1900                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
1901         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
1902                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
1903
1904         mutex_unlock(&rt2x00dev->csr_mutex);
1905 }
1906
1907 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1908 {
1909         unsigned int i;
1910
1911         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1912                 rt2800_efuse_read(rt2x00dev, i);
1913 }
1914 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1915
1916 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1917 {
1918         u16 word;
1919         u8 *mac;
1920         u8 default_lna_gain;
1921
1922         /*
1923          * Start validation of the data that has been read.
1924          */
1925         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1926         if (!is_valid_ether_addr(mac)) {
1927                 random_ether_addr(mac);
1928                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1929         }
1930
1931         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1932         if (word == 0xffff) {
1933                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1934                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1935                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1936                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1937                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1938         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
1939                    rt2x00_rt(rt2x00dev, RT2870) ||
1940                    rt2x00_rt(rt2x00dev, RT2872) ||
1941                    rt2x00_rt(rt2x00dev, RT2872)) {
1942                 /*
1943                  * There is a max of 2 RX streams for RT28x0 series
1944                  */
1945                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1946                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1947                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1948         }
1949
1950         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1951         if (word == 0xffff) {
1952                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1953                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1954                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1955                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1956                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1957                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1958                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1959                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1960                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1961                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1962                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1963                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1964         }
1965
1966         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1967         if ((word & 0x00ff) == 0x00ff) {
1968                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1969                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1970                                    LED_MODE_TXRX_ACTIVITY);
1971                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1972                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1973                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1974                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1975                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1976                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1977         }
1978
1979         /*
1980          * During the LNA validation we are going to use
1981          * lna0 as correct value. Note that EEPROM_LNA
1982          * is never validated.
1983          */
1984         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1985         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1986
1987         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1988         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1989                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1990         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1991                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1992         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1993
1994         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1995         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1996                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1997         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1998             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1999                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2000                                    default_lna_gain);
2001         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2002
2003         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2004         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2005                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2006         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2007                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2008         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2009
2010         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2011         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2012                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2013         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2014             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2015                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2016                                    default_lna_gain);
2017         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2018
2019         return 0;
2020 }
2021 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2022
2023 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2024 {
2025         u32 reg;
2026         u16 value;
2027         u16 eeprom;
2028
2029         /*
2030          * Read EEPROM word for configuration.
2031          */
2032         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2033
2034         /*
2035          * Identify RF chipset.
2036          */
2037         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2038         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2039
2040         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2041                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2042
2043         if (!rt2x00_rt(rt2x00dev, RT2860) &&
2044             !rt2x00_rt(rt2x00dev, RT2870) &&
2045             !rt2x00_rt(rt2x00dev, RT2872) &&
2046             !rt2x00_rt(rt2x00dev, RT2883) &&
2047             !rt2x00_rt(rt2x00dev, RT3070) &&
2048             !rt2x00_rt(rt2x00dev, RT3071) &&
2049             !rt2x00_rt(rt2x00dev, RT3090) &&
2050             !rt2x00_rt(rt2x00dev, RT3390) &&
2051             !rt2x00_rt(rt2x00dev, RT3572)) {
2052                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2053                 return -ENODEV;
2054         }
2055
2056         if (!rt2x00_rf(rt2x00dev, RF2820) &&
2057             !rt2x00_rf(rt2x00dev, RF2850) &&
2058             !rt2x00_rf(rt2x00dev, RF2720) &&
2059             !rt2x00_rf(rt2x00dev, RF2750) &&
2060             !rt2x00_rf(rt2x00dev, RF3020) &&
2061             !rt2x00_rf(rt2x00dev, RF2020) &&
2062             !rt2x00_rf(rt2x00dev, RF3021) &&
2063             !rt2x00_rf(rt2x00dev, RF3022) &&
2064             !rt2x00_rf(rt2x00dev, RF3052)) {
2065                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2066                 return -ENODEV;
2067         }
2068
2069         /*
2070          * Identify default antenna configuration.
2071          */
2072         rt2x00dev->default_ant.tx =
2073             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2074         rt2x00dev->default_ant.rx =
2075             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2076
2077         /*
2078          * Read frequency offset and RF programming sequence.
2079          */
2080         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2081         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2082
2083         /*
2084          * Read external LNA informations.
2085          */
2086         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2087
2088         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2089                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2090         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2091                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2092
2093         /*
2094          * Detect if this device has an hardware controlled radio.
2095          */
2096         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2097                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2098
2099         /*
2100          * Store led settings, for correct led behaviour.
2101          */
2102 #ifdef CONFIG_RT2X00_LIB_LEDS
2103         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2104         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2105         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2106
2107         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2108 #endif /* CONFIG_RT2X00_LIB_LEDS */
2109
2110         return 0;
2111 }
2112 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2113
2114 /*
2115  * RF value list for rt28x0
2116  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2117  */
2118 static const struct rf_channel rf_vals[] = {
2119         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2120         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2121         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2122         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2123         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2124         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2125         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2126         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2127         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2128         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2129         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2130         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2131         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2132         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2133
2134         /* 802.11 UNI / HyperLan 2 */
2135         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2136         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2137         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2138         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2139         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2140         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2141         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2142         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2143         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2144         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2145         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2146         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2147
2148         /* 802.11 HyperLan 2 */
2149         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2150         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2151         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2152         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2153         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2154         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2155         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2156         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2157         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2158         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2159         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2160         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2161         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2162         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2163         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2164         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2165
2166         /* 802.11 UNII */
2167         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2168         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2169         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2170         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2171         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2172         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2173         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2174         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2175         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2176         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2177         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2178
2179         /* 802.11 Japan */
2180         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2181         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2182         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2183         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2184         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2185         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2186         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2187 };
2188
2189 /*
2190  * RF value list for rt3070
2191  * Supports: 2.4 GHz
2192  */
2193 static const struct rf_channel rf_vals_302x[] = {
2194         {1,  241, 2, 2 },
2195         {2,  241, 2, 7 },
2196         {3,  242, 2, 2 },
2197         {4,  242, 2, 7 },
2198         {5,  243, 2, 2 },
2199         {6,  243, 2, 7 },
2200         {7,  244, 2, 2 },
2201         {8,  244, 2, 7 },
2202         {9,  245, 2, 2 },
2203         {10, 245, 2, 7 },
2204         {11, 246, 2, 2 },
2205         {12, 246, 2, 7 },
2206         {13, 247, 2, 2 },
2207         {14, 248, 2, 4 },
2208 };
2209
2210 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2211 {
2212         struct hw_mode_spec *spec = &rt2x00dev->spec;
2213         struct channel_info *info;
2214         char *tx_power1;
2215         char *tx_power2;
2216         unsigned int i;
2217         u16 eeprom;
2218
2219         /*
2220          * Disable powersaving as default on PCI devices.
2221          */
2222         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2223                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2224
2225         /*
2226          * Initialize all hw fields.
2227          */
2228         rt2x00dev->hw->flags =
2229             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2230             IEEE80211_HW_SIGNAL_DBM |
2231             IEEE80211_HW_SUPPORTS_PS |
2232             IEEE80211_HW_PS_NULLFUNC_STACK;
2233
2234         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2235         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2236                                 rt2x00_eeprom_addr(rt2x00dev,
2237                                                    EEPROM_MAC_ADDR_0));
2238
2239         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2240
2241         /*
2242          * Initialize hw_mode information.
2243          */
2244         spec->supported_bands = SUPPORT_BAND_2GHZ;
2245         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2246
2247         if (rt2x00_rf(rt2x00dev, RF2820) ||
2248             rt2x00_rf(rt2x00dev, RF2720) ||
2249             rt2x00_rf(rt2x00dev, RF3052)) {
2250                 spec->num_channels = 14;
2251                 spec->channels = rf_vals;
2252         } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
2253                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2254                 spec->num_channels = ARRAY_SIZE(rf_vals);
2255                 spec->channels = rf_vals;
2256         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2257                    rt2x00_rf(rt2x00dev, RF2020) ||
2258                    rt2x00_rf(rt2x00dev, RF3021) ||
2259                    rt2x00_rf(rt2x00dev, RF3022)) {
2260                 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2261                 spec->channels = rf_vals_302x;
2262         }
2263
2264         /*
2265          * Initialize HT information.
2266          */
2267         if (!rt2x00_rf(rt2x00dev, RF2020))
2268                 spec->ht.ht_supported = true;
2269         else
2270                 spec->ht.ht_supported = false;
2271
2272         spec->ht.cap =
2273             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2274             IEEE80211_HT_CAP_GRN_FLD |
2275             IEEE80211_HT_CAP_SGI_20 |
2276             IEEE80211_HT_CAP_SGI_40 |
2277             IEEE80211_HT_CAP_TX_STBC |
2278             IEEE80211_HT_CAP_RX_STBC;
2279         spec->ht.ampdu_factor = 3;
2280         spec->ht.ampdu_density = 4;
2281         spec->ht.mcs.tx_params =
2282             IEEE80211_HT_MCS_TX_DEFINED |
2283             IEEE80211_HT_MCS_TX_RX_DIFF |
2284             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2285                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2286
2287         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2288         case 3:
2289                 spec->ht.mcs.rx_mask[2] = 0xff;
2290         case 2:
2291                 spec->ht.mcs.rx_mask[1] = 0xff;
2292         case 1:
2293                 spec->ht.mcs.rx_mask[0] = 0xff;
2294                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2295                 break;
2296         }
2297
2298         /*
2299          * Create channel information array
2300          */
2301         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2302         if (!info)
2303                 return -ENOMEM;
2304
2305         spec->channels_info = info;
2306
2307         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2308         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2309
2310         for (i = 0; i < 14; i++) {
2311                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2312                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2313         }
2314
2315         if (spec->num_channels > 14) {
2316                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2317                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2318
2319                 for (i = 14; i < spec->num_channels; i++) {
2320                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2321                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2322                 }
2323         }
2324
2325         return 0;
2326 }
2327 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2328
2329 /*
2330  * IEEE80211 stack callback functions.
2331  */
2332 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2333                                 u32 *iv32, u16 *iv16)
2334 {
2335         struct rt2x00_dev *rt2x00dev = hw->priv;
2336         struct mac_iveiv_entry iveiv_entry;
2337         u32 offset;
2338
2339         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2340         rt2800_register_multiread(rt2x00dev, offset,
2341                                       &iveiv_entry, sizeof(iveiv_entry));
2342
2343         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2344         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2345 }
2346
2347 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2348 {
2349         struct rt2x00_dev *rt2x00dev = hw->priv;
2350         u32 reg;
2351         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2352
2353         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2354         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2355         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2356
2357         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2358         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2359         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2360
2361         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2362         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2363         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2364
2365         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2366         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2367         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2368
2369         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2370         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2371         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2372
2373         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2374         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2375         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2376
2377         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2378         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2379         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2380
2381         return 0;
2382 }
2383
2384 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2385                           const struct ieee80211_tx_queue_params *params)
2386 {
2387         struct rt2x00_dev *rt2x00dev = hw->priv;
2388         struct data_queue *queue;
2389         struct rt2x00_field32 field;
2390         int retval;
2391         u32 reg;
2392         u32 offset;
2393
2394         /*
2395          * First pass the configuration through rt2x00lib, that will
2396          * update the queue settings and validate the input. After that
2397          * we are free to update the registers based on the value
2398          * in the queue parameter.
2399          */
2400         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2401         if (retval)
2402                 return retval;
2403
2404         /*
2405          * We only need to perform additional register initialization
2406          * for WMM queues/
2407          */
2408         if (queue_idx >= 4)
2409                 return 0;
2410
2411         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2412
2413         /* Update WMM TXOP register */
2414         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2415         field.bit_offset = (queue_idx & 1) * 16;
2416         field.bit_mask = 0xffff << field.bit_offset;
2417
2418         rt2800_register_read(rt2x00dev, offset, &reg);
2419         rt2x00_set_field32(&reg, field, queue->txop);
2420         rt2800_register_write(rt2x00dev, offset, reg);
2421
2422         /* Update WMM registers */
2423         field.bit_offset = queue_idx * 4;
2424         field.bit_mask = 0xf << field.bit_offset;
2425
2426         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2427         rt2x00_set_field32(&reg, field, queue->aifs);
2428         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2429
2430         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2431         rt2x00_set_field32(&reg, field, queue->cw_min);
2432         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2433
2434         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2435         rt2x00_set_field32(&reg, field, queue->cw_max);
2436         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2437
2438         /* Update EDCA registers */
2439         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2440
2441         rt2800_register_read(rt2x00dev, offset, &reg);
2442         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2443         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2444         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2445         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2446         rt2800_register_write(rt2x00dev, offset, reg);
2447
2448         return 0;
2449 }
2450
2451 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2452 {
2453         struct rt2x00_dev *rt2x00dev = hw->priv;
2454         u64 tsf;
2455         u32 reg;
2456
2457         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2458         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2459         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2460         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2461
2462         return tsf;
2463 }
2464
2465 const struct ieee80211_ops rt2800_mac80211_ops = {
2466         .tx                     = rt2x00mac_tx,
2467         .start                  = rt2x00mac_start,
2468         .stop                   = rt2x00mac_stop,
2469         .add_interface          = rt2x00mac_add_interface,
2470         .remove_interface       = rt2x00mac_remove_interface,
2471         .config                 = rt2x00mac_config,
2472         .configure_filter       = rt2x00mac_configure_filter,
2473         .set_tim                = rt2x00mac_set_tim,
2474         .set_key                = rt2x00mac_set_key,
2475         .get_stats              = rt2x00mac_get_stats,
2476         .get_tkip_seq           = rt2800_get_tkip_seq,
2477         .set_rts_threshold      = rt2800_set_rts_threshold,
2478         .bss_info_changed       = rt2x00mac_bss_info_changed,
2479         .conf_tx                = rt2800_conf_tx,
2480         .get_tsf                = rt2800_get_tsf,
2481         .rfkill_poll            = rt2x00mac_rfkill_poll,
2482 };
2483 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);