drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-calib.h"
  61 #include "iwl-agn.h"
  62
  63
  64 /******************************************************************************
  65  *
  66  * module boiler plate
  67  *
  68  ******************************************************************************/
  69
  70 /*
  71  * module name, copyright, version, etc.
  72  */
  73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  74
  75 #ifdef CONFIG_IWLWIFI_DEBUG
  76 #define VD "d"
  77 #else
  78 #define VD
  79 #endif
  80
  81 #define DRV_VERSION     IWLWIFI_VERSION VD
  82
  83
  84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  85 MODULE_VERSION(DRV_VERSION);
  86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  87 MODULE_LICENSE("GPL");
  88 MODULE_ALIAS("iwl4965");
  89
  90 static int iwlagn_ant_coupling;
  91 static bool iwlagn_bt_ch_announce = 1;
  92
  93 /**
  94  * iwl_commit_rxon - commit staging_rxon to hardware
  95  *
  96  * The RXON command in staging_rxon is committed to the hardware and
  97  * the active_rxon structure is updated with the new data.  This
  98  * function correctly transitions out of the RXON_ASSOC_MSK state if
  99  * a HW tune is required based on the RXON structure changes.
 100  */
 101 int iwl_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
 102 {
 103         /* cast away the const for active_rxon in this function */
 104         struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
 105         int ret;
 106         bool new_assoc =
 107                 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
 108         bool old_assoc = !!(ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK);
 109
 110         if (!iwl_is_alive(priv))
 111                 return -EBUSY;
 112
 113         if (!ctx->is_active)
 114                 return 0;
 115
 116         /* always get timestamp with Rx frame */
 117         ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
 118
 119         ret = iwl_check_rxon_cmd(priv, ctx);
 120         if (ret) {
 121                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
 122                 return -EINVAL;
 123         }
 124
 125         /*
 126          * receive commit_rxon request
 127          * abort any previous channel switch if still in process
 128          */
 129         if (priv->switch_rxon.switch_in_progress &&
 130             (priv->switch_rxon.channel != ctx->staging.channel)) {
 131                 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
 132                       le16_to_cpu(priv->switch_rxon.channel));
 133                 iwl_chswitch_done(priv, false);
 134         }
 135
 136         /* If we don't need to send a full RXON, we can use
 137          * iwl_rxon_assoc_cmd which is used to reconfigure filter
 138          * and other flags for the current radio configuration. */
 139         if (!iwl_full_rxon_required(priv, ctx)) {
 140                 ret = iwl_send_rxon_assoc(priv, ctx);
 141                 if (ret) {
 142                         IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
 143                         return ret;
 144                 }
 145
 146                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 147                 iwl_print_rx_config_cmd(priv, ctx);
 148                 return 0;
 149         }
 150
 151         /* If we are currently associated and the new config requires
 152          * an RXON_ASSOC and the new config wants the associated mask enabled,
 153          * we must clear the associated from the active configuration
 154          * before we apply the new config */
 155         if (iwl_is_associated_ctx(ctx) && new_assoc) {
 156                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
 157                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
 158
 159                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 160                                        sizeof(struct iwl_rxon_cmd),
 161                                        active_rxon);
 162
 163                 /* If the mask clearing failed then we set
 164                  * active_rxon back to what it was previously */
 165                 if (ret) {
 166                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
 167                         IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
 168                         return ret;
 169                 }
 170                 iwl_clear_ucode_stations(priv, ctx);
 171                 iwl_restore_stations(priv, ctx);
 172                 ret = iwl_restore_default_wep_keys(priv, ctx);
 173                 if (ret) {
 174                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
 175                         return ret;
 176                 }
 177         }
 178
 179         IWL_DEBUG_INFO(priv, "Sending RXON\n"
 180                        "* with%s RXON_FILTER_ASSOC_MSK\n"
 181                        "* channel = %d\n"
 182                        "* bssid = %pM\n",
 183                        (new_assoc ? "" : "out"),
 184                        le16_to_cpu(ctx->staging.channel),
 185                        ctx->staging.bssid_addr);
 186
 187         iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
 188
 189         if (!old_assoc) {
 190                 /*
 191                  * First of all, before setting associated, we need to
 192                  * send RXON timing so the device knows about the DTIM
 193                  * period and other timing values
 194                  */
 195                 ret = iwl_send_rxon_timing(priv, ctx);
 196                 if (ret) {
 197                         IWL_ERR(priv, "Error setting RXON timing!\n");
 198                         return ret;
 199                 }
 200         }
 201
 202         if (priv->cfg->ops->hcmd->set_pan_params) {
 203                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
 204                 if (ret)
 205                         return ret;
 206         }
 207
 208         /* Apply the new configuration
 209          * RXON unassoc clears the station table in uCode so restoration of
 210          * stations is needed after it (the RXON command) completes
 211          */
 212         if (!new_assoc) {
 213                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 214                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
 215                 if (ret) {
 216                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
 217                         return ret;
 218                 }
 219                 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
 220                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 221                 iwl_clear_ucode_stations(priv, ctx);
 222                 iwl_restore_stations(priv, ctx);
 223                 ret = iwl_restore_default_wep_keys(priv, ctx);
 224                 if (ret) {
 225                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
 226                         return ret;
 227                 }
 228         }
 229         if (new_assoc) {
 230                 priv->start_calib = 0;
 231                 /* Apply the new configuration
 232                  * RXON assoc doesn't clear the station table in uCode,
 233                  */
 234                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 235                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
 236                 if (ret) {
 237                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
 238                         return ret;
 239                 }
 240                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 241         }
 242         iwl_print_rx_config_cmd(priv, ctx);
 243
 244         iwl_init_sensitivity(priv);
 245
 246         /* If we issue a new RXON command which required a tune then we must
 247          * send a new TXPOWER command or we won't be able to Tx any frames */
 248         ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
 249         if (ret) {
 250                 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
 251                 return ret;
 252         }
 253
 254         return 0;
 255 }
 256
 257 void iwl_update_chain_flags(struct iwl_priv *priv)
 258 {
 259         struct iwl_rxon_context *ctx;
 260
 261         if (priv->cfg->ops->hcmd->set_rxon_chain) {
 262                 for_each_context(priv, ctx) {
 263                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 264                         iwlcore_commit_rxon(priv, ctx);
 265                 }
 266         }
 267 }
 268
 269 static void iwl_clear_free_frames(struct iwl_priv *priv)
 270 {
 271         struct list_head *element;
 272
 273         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 274                        priv->frames_count);
 275
 276         while (!list_empty(&priv->free_frames)) {
 277                 element = priv->free_frames.next;
 278                 list_del(element);
 279                 kfree(list_entry(element, struct iwl_frame, list));
 280                 priv->frames_count--;
 281         }
 282
 283         if (priv->frames_count) {
 284                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 285                             priv->frames_count);
 286                 priv->frames_count = 0;
 287         }
 288 }
 289
 290 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 291 {
 292         struct iwl_frame *frame;
 293         struct list_head *element;
 294         if (list_empty(&priv->free_frames)) {
 295                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 296                 if (!frame) {
 297                         IWL_ERR(priv, "Could not allocate frame!\n");
 298                         return NULL;
 299                 }
 300
 301                 priv->frames_count++;
 302                 return frame;
 303         }
 304
 305         element = priv->free_frames.next;
 306         list_del(element);
 307         return list_entry(element, struct iwl_frame, list);
 308 }
 309
 310 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 311 {
 312         memset(frame, 0, sizeof(*frame));
 313         list_add(&frame->list, &priv->free_frames);
 314 }
 315
 316 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 317                                           struct ieee80211_hdr *hdr,
 318                                           int left)
 319 {
 320         if (!priv->ibss_beacon)
 321                 return 0;
 322
 323         if (priv->ibss_beacon->len > left)
 324                 return 0;
 325
 326         memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
 327
 328         return priv->ibss_beacon->len;
 329 }
 330
 331 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 332 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 333                 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 334                 u8 *beacon, u32 frame_size)
 335 {
 336         u16 tim_idx;
 337         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 338
 339         /*
 340          * The index is relative to frame start but we start looking at the
 341          * variable-length part of the beacon.
 342          */
 343         tim_idx = mgmt->u.beacon.variable - beacon;
 344
 345         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 346         while ((tim_idx < (frame_size - 2)) &&
 347                         (beacon[tim_idx] != WLAN_EID_TIM))
 348                 tim_idx += beacon[tim_idx+1] + 2;
 349
 350         /* If TIM field was found, set variables */
 351         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 352                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 353                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 354         } else
 355                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 356 }
 357
 358 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 359                                        struct iwl_frame *frame)
 360 {
 361         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 362         u32 frame_size;
 363         u32 rate_flags;
 364         u32 rate;
 365         /*
 366          * We have to set up the TX command, the TX Beacon command, and the
 367          * beacon contents.
 368          */
 369
 370         lockdep_assert_held(&priv->mutex);
 371
 372         if (!priv->beacon_ctx) {
 373                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 374                 return 0;
 375         }
 376
 377         /* Initialize memory */
 378         tx_beacon_cmd = &frame->u.beacon;
 379         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 380
 381         /* Set up TX beacon contents */
 382         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 383                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 384         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 385                 return 0;
 386
 387         /* Set up TX command fields */
 388         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 389         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 390         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 391         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 392                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 393
 394         /* Set up TX beacon command fields */
 395         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 396                         frame_size);
 397
 398         /* Set up packet rate and flags */
 399         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 400         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 401                                               priv->hw_params.valid_tx_ant);
 402         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 403         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 404                 rate_flags |= RATE_MCS_CCK_MSK;
 405         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 406                         rate_flags);
 407
 408         return sizeof(*tx_beacon_cmd) + frame_size;
 409 }
 410 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
 411 {
 412         struct iwl_frame *frame;
 413         unsigned int frame_size;
 414         int rc;
 415
 416         frame = iwl_get_free_frame(priv);
 417         if (!frame) {
 418                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 419                           "command.\n");
 420                 return -ENOMEM;
 421         }
 422
 423         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 424         if (!frame_size) {
 425                 IWL_ERR(priv, "Error configuring the beacon command\n");
 426                 iwl_free_frame(priv, frame);
 427                 return -EINVAL;
 428         }
 429
 430         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 431                               &frame->u.cmd[0]);
 432
 433         iwl_free_frame(priv, frame);
 434
 435         return rc;
 436 }
 437
 438 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 439 {
 440         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 441
 442         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 443         if (sizeof(dma_addr_t) > sizeof(u32))
 444                 addr |=
 445                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 446
 447         return addr;
 448 }
 449
 450 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 451 {
 452         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 453
 454         return le16_to_cpu(tb->hi_n_len) >> 4;
 455 }
 456
 457 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 458                                   dma_addr_t addr, u16 len)
 459 {
 460         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 461         u16 hi_n_len = len << 4;
 462
 463         put_unaligned_le32(addr, &tb->lo);
 464         if (sizeof(dma_addr_t) > sizeof(u32))
 465                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 466
 467         tb->hi_n_len = cpu_to_le16(hi_n_len);
 468
 469         tfd->num_tbs = idx + 1;
 470 }
 471
 472 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 473 {
 474         return tfd->num_tbs & 0x1f;
 475 }
 476
 477 /**
 478  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 479  * @priv - driver private data
 480  * @txq - tx queue
 481  *
 482  * Does NOT advance any TFD circular buffer read/write indexes
 483  * Does NOT free the TFD itself (which is within circular buffer)
 484  */
 485 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 486 {
 487         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 488         struct iwl_tfd *tfd;
 489         struct pci_dev *dev = priv->pci_dev;
 490         int index = txq->q.read_ptr;
 491         int i;
 492         int num_tbs;
 493
 494         tfd = &tfd_tmp[index];
 495
 496         /* Sanity check on number of chunks */
 497         num_tbs = iwl_tfd_get_num_tbs(tfd);
 498
 499         if (num_tbs >= IWL_NUM_OF_TBS) {
 500                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 501                 /* @todo issue fatal error, it is quite serious situation */
 502                 return;
 503         }
 504
 505         /* Unmap tx_cmd */
 506         if (num_tbs)
 507                 pci_unmap_single(dev,
 508                                 dma_unmap_addr(&txq->meta[index], mapping),
 509                                 dma_unmap_len(&txq->meta[index], len),
 510                                 PCI_DMA_BIDIRECTIONAL);
 511
 512         /* Unmap chunks, if any. */
 513         for (i = 1; i < num_tbs; i++)
 514                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 515                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 516
 517         /* free SKB */
 518         if (txq->txb) {
 519                 struct sk_buff *skb;
 520
 521                 skb = txq->txb[txq->q.read_ptr].skb;
 522
 523                 /* can be called from irqs-disabled context */
 524                 if (skb) {
 525                         dev_kfree_skb_any(skb);
 526                         txq->txb[txq->q.read_ptr].skb = NULL;
 527                 }
 528         }
 529 }
 530
 531 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 532                                  struct iwl_tx_queue *txq,
 533                                  dma_addr_t addr, u16 len,
 534                                  u8 reset, u8 pad)
 535 {
 536         struct iwl_queue *q;
 537         struct iwl_tfd *tfd, *tfd_tmp;
 538         u32 num_tbs;
 539
 540         q = &txq->q;
 541         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 542         tfd = &tfd_tmp[q->write_ptr];
 543
 544         if (reset)
 545                 memset(tfd, 0, sizeof(*tfd));
 546
 547         num_tbs = iwl_tfd_get_num_tbs(tfd);
 548
 549         /* Each TFD can point to a maximum 20 Tx buffers */
 550         if (num_tbs >= IWL_NUM_OF_TBS) {
 551                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 552                           IWL_NUM_OF_TBS);
 553                 return -EINVAL;
 554         }
 555
 556         BUG_ON(addr & ~DMA_BIT_MASK(36));
 557         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 558                 IWL_ERR(priv, "Unaligned address = %llx\n",
 559                           (unsigned long long)addr);
 560
 561         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 562
 563         return 0;
 564 }
 565
 566 /*
 567  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 568  * given Tx queue, and enable the DMA channel used for that queue.
 569  *
 570  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 571  * channels supported in hardware.
 572  */
 573 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 574                          struct iwl_tx_queue *txq)
 575 {
 576         int txq_id = txq->q.id;
 577
 578         /* Circular buffer (TFD queue in DRAM) physical base address */
 579         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 580                              txq->q.dma_addr >> 8);
 581
 582         return 0;
 583 }
 584
 585 /******************************************************************************
 586  *
 587  * Generic RX handler implementations
 588  *
 589  ******************************************************************************/
 590 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 591                                 struct iwl_rx_mem_buffer *rxb)
 592 {
 593         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 594         struct iwl_alive_resp *palive;
 595         struct delayed_work *pwork;
 596
 597         palive = &pkt->u.alive_frame;
 598
 599         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 600                        "0x%01X 0x%01X\n",
 601                        palive->is_valid, palive->ver_type,
 602                        palive->ver_subtype);
 603
 604         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 605                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 606                 memcpy(&priv->card_alive_init,
 607                        &pkt->u.alive_frame,
 608                        sizeof(struct iwl_init_alive_resp));
 609                 pwork = &priv->init_alive_start;
 610         } else {
 611                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 612                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 613                        sizeof(struct iwl_alive_resp));
 614                 pwork = &priv->alive_start;
 615         }
 616
 617         /* We delay the ALIVE response by 5ms to
 618          * give the HW RF Kill time to activate... */
 619         if (palive->is_valid == UCODE_VALID_OK)
 620                 queue_delayed_work(priv->workqueue, pwork,
 621                                    msecs_to_jiffies(5));
 622         else
 623                 IWL_WARN(priv, "uCode did not respond OK.\n");
 624 }
 625
 626 static void iwl_bg_beacon_update(struct work_struct *work)
 627 {
 628         struct iwl_priv *priv =
 629                 container_of(work, struct iwl_priv, beacon_update);
 630         struct sk_buff *beacon;
 631
 632         mutex_lock(&priv->mutex);
 633         if (!priv->beacon_ctx) {
 634                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 635                 goto out;
 636         }
 637
 638         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 639                 /*
 640                  * The ucode will send beacon notifications even in
 641                  * IBSS mode, but we don't want to process them. But
 642                  * we need to defer the type check to here due to
 643                  * requiring locking around the beacon_ctx access.
 644                  */
 645                 goto out;
 646         }
 647
 648         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 649         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 650         if (!beacon) {
 651                 IWL_ERR(priv, "update beacon failed\n");
 652                 goto out;
 653         }
 654
 655         /* new beacon skb is allocated every time; dispose previous.*/
 656         if (priv->ibss_beacon)
 657                 dev_kfree_skb(priv->ibss_beacon);
 658
 659         priv->ibss_beacon = beacon;
 660
 661         iwl_send_beacon_cmd(priv);
 662  out:
 663         mutex_unlock(&priv->mutex);
 664 }
 665
 666 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 667 {
 668         struct iwl_priv *priv =
 669                 container_of(work, struct iwl_priv, bt_runtime_config);
 670
 671         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 672                 return;
 673
 674         /* dont send host command if rf-kill is on */
 675         if (!iwl_is_ready_rf(priv))
 676                 return;
 677         priv->cfg->ops->hcmd->send_bt_config(priv);
 678 }
 679
 680 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 681 {
 682         struct iwl_priv *priv =
 683                 container_of(work, struct iwl_priv, bt_full_concurrency);
 684         struct iwl_rxon_context *ctx;
 685
 686         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 687                 return;
 688
 689         /* dont send host command if rf-kill is on */
 690         if (!iwl_is_ready_rf(priv))
 691                 return;
 692
 693         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 694                        priv->bt_full_concurrent ?
 695                        "full concurrency" : "3-wire");
 696
 697         /*
 698          * LQ & RXON updated cmds must be sent before BT Config cmd
 699          * to avoid 3-wire collisions
 700          */
 701         mutex_lock(&priv->mutex);
 702         for_each_context(priv, ctx) {
 703                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 704                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 705                 iwlcore_commit_rxon(priv, ctx);
 706         }
 707         mutex_unlock(&priv->mutex);
 708
 709         priv->cfg->ops->hcmd->send_bt_config(priv);
 710 }
 711
 712 /**
 713  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 714  *
 715  * This callback is provided in order to send a statistics request.
 716  *
 717  * This timer function is continually reset to execute within
 718  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 719  * was received.  We need to ensure we receive the statistics in order
 720  * to update the temperature used for calibrating the TXPOWER.
 721  */
 722 static void iwl_bg_statistics_periodic(unsigned long data)
 723 {
 724         struct iwl_priv *priv = (struct iwl_priv *)data;
 725
 726         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 727                 return;
 728
 729         /* dont send host command if rf-kill is on */
 730         if (!iwl_is_ready_rf(priv))
 731                 return;
 732
 733         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 734 }
 735
 736
 737 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 738                                         u32 start_idx, u32 num_events,
 739                                         u32 mode)
 740 {
 741         u32 i;
 742         u32 ptr;        /* SRAM byte address of log data */
 743         u32 ev, time, data; /* event log data */
 744         unsigned long reg_flags;
 745
 746         if (mode == 0)
 747                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 748         else
 749                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 750
 751         /* Make sure device is powered up for SRAM reads */
 752         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 753         if (iwl_grab_nic_access(priv)) {
 754                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 755                 return;
 756         }
 757
 758         /* Set starting address; reads will auto-increment */
 759         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 760         rmb();
 761
 762         /*
 763          * "time" is actually "data" for mode 0 (no timestamp).
 764          * place event id # at far right for easier visual parsing.
 765          */
 766         for (i = 0; i < num_events; i++) {
 767                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 768                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 769                 if (mode == 0) {
 770                         trace_iwlwifi_dev_ucode_cont_event(priv,
 771                                                         0, time, ev);
 772                 } else {
 773                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 774                         trace_iwlwifi_dev_ucode_cont_event(priv,
 775                                                 time, data, ev);
 776                 }
 777         }
 778         /* Allow device to power down */
 779         iwl_release_nic_access(priv);
 780         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 781 }
 782
 783 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 784 {
 785         u32 capacity;   /* event log capacity in # entries */
 786         u32 base;       /* SRAM byte address of event log header */
 787         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 788         u32 num_wraps;  /* # times uCode wrapped to top of log */
 789         u32 next_entry; /* index of next entry to be written by uCode */
 790
 791         if (priv->ucode_type == UCODE_INIT)
 792                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 793         else
 794                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 795         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 796                 capacity = iwl_read_targ_mem(priv, base);
 797                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 798                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 799                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 800         } else
 801                 return;
 802
 803         if (num_wraps == priv->event_log.num_wraps) {
 804                 iwl_print_cont_event_trace(priv,
 805                                        base, priv->event_log.next_entry,
 806                                        next_entry - priv->event_log.next_entry,
 807                                        mode);
 808                 priv->event_log.non_wraps_count++;
 809         } else {
 810                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 811                         priv->event_log.wraps_more_count++;
 812                 else
 813                         priv->event_log.wraps_once_count++;
 814                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 815                                 num_wraps - priv->event_log.num_wraps,
 816                                 next_entry, priv->event_log.next_entry);
 817                 if (next_entry < priv->event_log.next_entry) {
 818                         iwl_print_cont_event_trace(priv, base,
 819                                priv->event_log.next_entry,
 820                                capacity - priv->event_log.next_entry,
 821                                mode);
 822
 823                         iwl_print_cont_event_trace(priv, base, 0,
 824                                 next_entry, mode);
 825                 } else {
 826                         iwl_print_cont_event_trace(priv, base,
 827                                next_entry, capacity - next_entry,
 828                                mode);
 829
 830                         iwl_print_cont_event_trace(priv, base, 0,
 831                                 next_entry, mode);
 832                 }
 833         }
 834         priv->event_log.num_wraps = num_wraps;
 835         priv->event_log.next_entry = next_entry;
 836 }
 837
 838 /**
 839  * iwl_bg_ucode_trace - Timer callback to log ucode event
 840  *
 841  * The timer is continually set to execute every
 842  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 843  * this function is to perform continuous uCode event logging operation
 844  * if enabled
 845  */
 846 static void iwl_bg_ucode_trace(unsigned long data)
 847 {
 848         struct iwl_priv *priv = (struct iwl_priv *)data;
 849
 850         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 851                 return;
 852
 853         if (priv->event_log.ucode_trace) {
 854                 iwl_continuous_event_trace(priv);
 855                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 856                 mod_timer(&priv->ucode_trace,
 857                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 858         }
 859 }
 860
 861 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
 862                                 struct iwl_rx_mem_buffer *rxb)
 863 {
 864         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 865         struct iwl4965_beacon_notif *beacon =
 866                 (struct iwl4965_beacon_notif *)pkt->u.raw;
 867 #ifdef CONFIG_IWLWIFI_DEBUG
 868         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 869
 870         IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
 871                 "tsf %d %d rate %d\n",
 872                 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
 873                 beacon->beacon_notify_hdr.failure_frame,
 874                 le32_to_cpu(beacon->ibss_mgr_status),
 875                 le32_to_cpu(beacon->high_tsf),
 876                 le32_to_cpu(beacon->low_tsf), rate);
 877 #endif
 878
 879         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 880
 881         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 882                 queue_work(priv->workqueue, &priv->beacon_update);
 883 }
 884
 885 /* Handle notification from uCode that card's power state is changing
 886  * due to software, hardware, or critical temperature RFKILL */
 887 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 888                                     struct iwl_rx_mem_buffer *rxb)
 889 {
 890         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 891         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 892         unsigned long status = priv->status;
 893
 894         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 895                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 896                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 897                           (flags & CT_CARD_DISABLED) ?
 898                           "Reached" : "Not reached");
 899
 900         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 901                      CT_CARD_DISABLED)) {
 902
 903                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 904                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 905
 906                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 907                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 908
 909                 if (!(flags & RXON_CARD_DISABLED)) {
 910                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 911                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 912                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 913                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 914                 }
 915                 if (flags & CT_CARD_DISABLED)
 916                         iwl_tt_enter_ct_kill(priv);
 917         }
 918         if (!(flags & CT_CARD_DISABLED))
 919                 iwl_tt_exit_ct_kill(priv);
 920
 921         if (flags & HW_CARD_DISABLED)
 922                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 923         else
 924                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 925
 926
 927         if (!(flags & RXON_CARD_DISABLED))
 928                 iwl_scan_cancel(priv);
 929
 930         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 931              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 932                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 933                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 934         else
 935                 wake_up_interruptible(&priv->wait_command_queue);
 936 }
 937
 938 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 939 {
 940         if (src == IWL_PWR_SRC_VAUX) {
 941                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 942                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 943                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 944                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 945         } else {
 946                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 947                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 948                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 949         }
 950
 951         return 0;
 952 }
 953
 954 static void iwl_bg_tx_flush(struct work_struct *work)
 955 {
 956         struct iwl_priv *priv =
 957                 container_of(work, struct iwl_priv, tx_flush);
 958
 959         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 960                 return;
 961
 962         /* do nothing if rf-kill is on */
 963         if (!iwl_is_ready_rf(priv))
 964                 return;
 965
 966         if (priv->cfg->ops->lib->txfifo_flush) {
 967                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 968                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 969         }
 970 }
 971
 972 /**
 973  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 974  *
 975  * Setup the RX handlers for each of the reply types sent from the uCode
 976  * to the host.
 977  *
 978  * This function chains into the hardware specific files for them to setup
 979  * any hardware specific handlers as well.
 980  */
 981 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 982 {
 983         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 984         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 985         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 986         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 987                         iwl_rx_spectrum_measure_notif;
 988         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 989         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 990             iwl_rx_pm_debug_statistics_notif;
 991         priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
 992
 993         /*
 994          * The same handler is used for both the REPLY to a discrete
 995          * statistics request from the host as well as for the periodic
 996          * statistics notifications (after received beacons) from the uCode.
 997          */
 998         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 999         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
1000
1001         iwl_setup_rx_scan_handlers(priv);
1002
1003         /* status change handler */
1004         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
1005
1006         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
1007             iwl_rx_missed_beacon_notif;
1008         /* Rx handlers */
1009         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
1010         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
1011         /* block ack */
1012         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
1013         /* Set up hardware specific Rx handlers */
1014         priv->cfg->ops->lib->rx_handler_setup(priv);
1015 }
1016
1017 /**
1018  * iwl_rx_handle - Main entry function for receiving responses from uCode
1019  *
1020  * Uses the priv->rx_handlers callback function array to invoke
1021  * the appropriate handlers, including command responses,
1022  * frame-received notifications, and other notifications.
1023  */
1024 void iwl_rx_handle(struct iwl_priv *priv)
1025 {
1026         struct iwl_rx_mem_buffer *rxb;
1027         struct iwl_rx_packet *pkt;
1028         struct iwl_rx_queue *rxq = &priv->rxq;
1029         u32 r, i;
1030         int reclaim;
1031         unsigned long flags;
1032         u8 fill_rx = 0;
1033         u32 count = 8;
1034         int total_empty;
1035
1036         /* uCode's read index (stored in shared DRAM) indicates the last Rx
1037          * buffer that the driver may process (last buffer filled by ucode). */
1038         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
1039         i = rxq->read;
1040
1041         /* Rx interrupt, but nothing sent from uCode */
1042         if (i == r)
1043                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
1044
1045         /* calculate total frames need to be restock after handling RX */
1046         total_empty = r - rxq->write_actual;
1047         if (total_empty < 0)
1048                 total_empty += RX_QUEUE_SIZE;
1049
1050         if (total_empty > (RX_QUEUE_SIZE / 2))
1051                 fill_rx = 1;
1052
1053         while (i != r) {
1054                 int len;
1055
1056                 rxb = rxq->queue[i];
1057
1058                 /* If an RXB doesn't have a Rx queue slot associated with it,
1059                  * then a bug has been introduced in the queue refilling
1060                  * routines -- catch it here */
1061                 BUG_ON(rxb == NULL);
1062
1063                 rxq->queue[i] = NULL;
1064
1065                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1066                                PAGE_SIZE << priv->hw_params.rx_page_order,
1067                                PCI_DMA_FROMDEVICE);
1068                 pkt = rxb_addr(rxb);
1069
1070                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1071                 len += sizeof(u32); /* account for status word */
1072                 trace_iwlwifi_dev_rx(priv, pkt, len);
1073
1074                 /* Reclaim a command buffer only if this packet is a response
1075                  *   to a (driver-originated) command.
1076                  * If the packet (e.g. Rx frame) originated from uCode,
1077                  *   there is no command buffer to reclaim.
1078                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1079                  *   but apparently a few don't get set; catch them here. */
1080                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1081                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
1082                         (pkt->hdr.cmd != REPLY_RX) &&
1083                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
1084                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
1085                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1086                         (pkt->hdr.cmd != REPLY_TX);
1087
1088                 /* Based on type of command response or notification,
1089                  *   handle those that need handling via function in
1090                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
1091                 if (priv->rx_handlers[pkt->hdr.cmd]) {
1092                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
1093                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1094                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
1095                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
1096                 } else {
1097                         /* No handling needed */
1098                         IWL_DEBUG_RX(priv,
1099                                 "r %d i %d No handler needed for %s, 0x%02x\n",
1100                                 r, i, get_cmd_string(pkt->hdr.cmd),
1101                                 pkt->hdr.cmd);
1102                 }
1103
1104                 /*
1105                  * XXX: After here, we should always check rxb->page
1106                  * against NULL before touching it or its virtual
1107                  * memory (pkt). Because some rx_handler might have
1108                  * already taken or freed the pages.
1109                  */
1110
1111                 if (reclaim) {
1112                         /* Invoke any callbacks, transfer the buffer to caller,
1113                          * and fire off the (possibly) blocking iwl_send_cmd()
1114                          * as we reclaim the driver command queue */
1115                         if (rxb->page)
1116                                 iwl_tx_cmd_complete(priv, rxb);
1117                         else
1118                                 IWL_WARN(priv, "Claim null rxb?\n");
1119                 }
1120
1121                 /* Reuse the page if possible. For notification packets and
1122                  * SKBs that fail to Rx correctly, add them back into the
1123                  * rx_free list for reuse later. */
1124                 spin_lock_irqsave(&rxq->lock, flags);
1125                 if (rxb->page != NULL) {
1126                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1127                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1128                                 PCI_DMA_FROMDEVICE);
1129                         list_add_tail(&rxb->list, &rxq->rx_free);
1130                         rxq->free_count++;
1131                 } else
1132                         list_add_tail(&rxb->list, &rxq->rx_used);
1133
1134                 spin_unlock_irqrestore(&rxq->lock, flags);
1135
1136                 i = (i + 1) & RX_QUEUE_MASK;
1137                 /* If there are a lot of unused frames,
1138                  * restock the Rx queue so ucode wont assert. */
1139                 if (fill_rx) {
1140                         count++;
1141                         if (count >= 8) {
1142                                 rxq->read = i;
1143                                 iwlagn_rx_replenish_now(priv);
1144                                 count = 0;
1145                         }
1146                 }
1147         }
1148
1149         /* Backtrack one entry */
1150         rxq->read = i;
1151         if (fill_rx)
1152                 iwlagn_rx_replenish_now(priv);
1153         else
1154                 iwlagn_rx_queue_restock(priv);
1155 }
1156
1157 /* call this function to flush any scheduled tasklet */
1158 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1159 {
1160         /* wait to make sure we flush pending tasklet*/
1161         synchronize_irq(priv->pci_dev->irq);
1162         tasklet_kill(&priv->irq_tasklet);
1163 }
1164
1165 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1166 {
1167         u32 inta, handled = 0;
1168         u32 inta_fh;
1169         unsigned long flags;
1170         u32 i;
1171 #ifdef CONFIG_IWLWIFI_DEBUG
1172         u32 inta_mask;
1173 #endif
1174
1175         spin_lock_irqsave(&priv->lock, flags);
1176
1177         /* Ack/clear/reset pending uCode interrupts.
1178          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1179          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1180         inta = iwl_read32(priv, CSR_INT);
1181         iwl_write32(priv, CSR_INT, inta);
1182
1183         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1184          * Any new interrupts that happen after this, either while we're
1185          * in this tasklet, or later, will show up in next ISR/tasklet. */
1186         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1187         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1188
1189 #ifdef CONFIG_IWLWIFI_DEBUG
1190         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1191                 /* just for debug */
1192                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1193                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1194                               inta, inta_mask, inta_fh);
1195         }
1196 #endif
1197
1198         spin_unlock_irqrestore(&priv->lock, flags);
1199
1200         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1201          * atomic, make sure that inta covers all the interrupts that
1202          * we've discovered, even if FH interrupt came in just after
1203          * reading CSR_INT. */
1204         if (inta_fh & CSR49_FH_INT_RX_MASK)
1205                 inta |= CSR_INT_BIT_FH_RX;
1206         if (inta_fh & CSR49_FH_INT_TX_MASK)
1207                 inta |= CSR_INT_BIT_FH_TX;
1208
1209         /* Now service all interrupt bits discovered above. */
1210         if (inta & CSR_INT_BIT_HW_ERR) {
1211                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1212
1213                 /* Tell the device to stop sending interrupts */
1214                 iwl_disable_interrupts(priv);
1215
1216                 priv->isr_stats.hw++;
1217                 iwl_irq_handle_error(priv);
1218
1219                 handled |= CSR_INT_BIT_HW_ERR;
1220
1221                 return;
1222         }
1223
1224 #ifdef CONFIG_IWLWIFI_DEBUG
1225         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1226                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1227                 if (inta & CSR_INT_BIT_SCD) {
1228                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1229                                       "the frame/frames.\n");
1230                         priv->isr_stats.sch++;
1231                 }
1232
1233                 /* Alive notification via Rx interrupt will do the real work */
1234                 if (inta & CSR_INT_BIT_ALIVE) {
1235                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1236                         priv->isr_stats.alive++;
1237                 }
1238         }
1239 #endif
1240         /* Safely ignore these bits for debug checks below */
1241         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1242
1243         /* HW RF KILL switch toggled */
1244         if (inta & CSR_INT_BIT_RF_KILL) {
1245                 int hw_rf_kill = 0;
1246                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1247                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1248                         hw_rf_kill = 1;
1249
1250                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1251                                 hw_rf_kill ? "disable radio" : "enable radio");
1252
1253                 priv->isr_stats.rfkill++;
1254
1255                 /* driver only loads ucode once setting the interface up.
1256                  * the driver allows loading the ucode even if the radio
1257                  * is killed. Hence update the killswitch state here. The
1258                  * rfkill handler will care about restarting if needed.
1259                  */
1260                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1261                         if (hw_rf_kill)
1262                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1263                         else
1264                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1265                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1266                 }
1267
1268                 handled |= CSR_INT_BIT_RF_KILL;
1269         }
1270
1271         /* Chip got too hot and stopped itself */
1272         if (inta & CSR_INT_BIT_CT_KILL) {
1273                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1274                 priv->isr_stats.ctkill++;
1275                 handled |= CSR_INT_BIT_CT_KILL;
1276         }
1277
1278         /* Error detected by uCode */
1279         if (inta & CSR_INT_BIT_SW_ERR) {
1280                 IWL_ERR(priv, "Microcode SW error detected. "
1281                         " Restarting 0x%X.\n", inta);
1282                 priv->isr_stats.sw++;
1283                 iwl_irq_handle_error(priv);
1284                 handled |= CSR_INT_BIT_SW_ERR;
1285         }
1286
1287         /*
1288          * uCode wakes up after power-down sleep.
1289          * Tell device about any new tx or host commands enqueued,
1290          * and about any Rx buffers made available while asleep.
1291          */
1292         if (inta & CSR_INT_BIT_WAKEUP) {
1293                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1294                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1295                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1296                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1297                 priv->isr_stats.wakeup++;
1298                 handled |= CSR_INT_BIT_WAKEUP;
1299         }
1300
1301         /* All uCode command responses, including Tx command responses,
1302          * Rx "responses" (frame-received notification), and other
1303          * notifications from uCode come through here*/
1304         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1305                 iwl_rx_handle(priv);
1306                 priv->isr_stats.rx++;
1307                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1308         }
1309
1310         /* This "Tx" DMA channel is used only for loading uCode */
1311         if (inta & CSR_INT_BIT_FH_TX) {
1312                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1313                 priv->isr_stats.tx++;
1314                 handled |= CSR_INT_BIT_FH_TX;
1315                 /* Wake up uCode load routine, now that load is complete */
1316                 priv->ucode_write_complete = 1;
1317                 wake_up_interruptible(&priv->wait_command_queue);
1318         }
1319
1320         if (inta & ~handled) {
1321                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1322                 priv->isr_stats.unhandled++;
1323         }
1324
1325         if (inta & ~(priv->inta_mask)) {
1326                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1327                          inta & ~priv->inta_mask);
1328                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1329         }
1330
1331         /* Re-enable all interrupts */
1332         /* only Re-enable if diabled by irq */
1333         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1334                 iwl_enable_interrupts(priv);
1335
1336 #ifdef CONFIG_IWLWIFI_DEBUG
1337         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1338                 inta = iwl_read32(priv, CSR_INT);
1339                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1340                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1341                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1342                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1343         }
1344 #endif
1345 }
1346
1347 /* tasklet for iwlagn interrupt */
1348 static void iwl_irq_tasklet(struct iwl_priv *priv)
1349 {
1350         u32 inta = 0;
1351         u32 handled = 0;
1352         unsigned long flags;
1353         u32 i;
1354 #ifdef CONFIG_IWLWIFI_DEBUG
1355         u32 inta_mask;
1356 #endif
1357
1358         spin_lock_irqsave(&priv->lock, flags);
1359
1360         /* Ack/clear/reset pending uCode interrupts.
1361          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1362          */
1363         /* There is a hardware bug in the interrupt mask function that some
1364          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1365          * they are disabled in the CSR_INT_MASK register. Furthermore the
1366          * ICT interrupt handling mechanism has another bug that might cause
1367          * these unmasked interrupts fail to be detected. We workaround the
1368          * hardware bugs here by ACKing all the possible interrupts so that
1369          * interrupt coalescing can still be achieved.
1370          */
1371         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1372
1373         inta = priv->_agn.inta;
1374
1375 #ifdef CONFIG_IWLWIFI_DEBUG
1376         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1377                 /* just for debug */
1378                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1379                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1380                                 inta, inta_mask);
1381         }
1382 #endif
1383
1384         spin_unlock_irqrestore(&priv->lock, flags);
1385
1386         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1387         priv->_agn.inta = 0;
1388
1389         /* Now service all interrupt bits discovered above. */
1390         if (inta & CSR_INT_BIT_HW_ERR) {
1391                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1392
1393                 /* Tell the device to stop sending interrupts */
1394                 iwl_disable_interrupts(priv);
1395
1396                 priv->isr_stats.hw++;
1397                 iwl_irq_handle_error(priv);
1398
1399                 handled |= CSR_INT_BIT_HW_ERR;
1400
1401                 return;
1402         }
1403
1404 #ifdef CONFIG_IWLWIFI_DEBUG
1405         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1406                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1407                 if (inta & CSR_INT_BIT_SCD) {
1408                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1409                                       "the frame/frames.\n");
1410                         priv->isr_stats.sch++;
1411                 }
1412
1413                 /* Alive notification via Rx interrupt will do the real work */
1414                 if (inta & CSR_INT_BIT_ALIVE) {
1415                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1416                         priv->isr_stats.alive++;
1417                 }
1418         }
1419 #endif
1420         /* Safely ignore these bits for debug checks below */
1421         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1422
1423         /* HW RF KILL switch toggled */
1424         if (inta & CSR_INT_BIT_RF_KILL) {
1425                 int hw_rf_kill = 0;
1426                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1427                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1428                         hw_rf_kill = 1;
1429
1430                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1431                                 hw_rf_kill ? "disable radio" : "enable radio");
1432
1433                 priv->isr_stats.rfkill++;
1434
1435                 /* driver only loads ucode once setting the interface up.
1436                  * the driver allows loading the ucode even if the radio
1437                  * is killed. Hence update the killswitch state here. The
1438                  * rfkill handler will care about restarting if needed.
1439                  */
1440                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1441                         if (hw_rf_kill)
1442                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1443                         else
1444                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1445                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1446                 }
1447
1448                 handled |= CSR_INT_BIT_RF_KILL;
1449         }
1450
1451         /* Chip got too hot and stopped itself */
1452         if (inta & CSR_INT_BIT_CT_KILL) {
1453                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1454                 priv->isr_stats.ctkill++;
1455                 handled |= CSR_INT_BIT_CT_KILL;
1456         }
1457
1458         /* Error detected by uCode */
1459         if (inta & CSR_INT_BIT_SW_ERR) {
1460                 IWL_ERR(priv, "Microcode SW error detected. "
1461                         " Restarting 0x%X.\n", inta);
1462                 priv->isr_stats.sw++;
1463                 iwl_irq_handle_error(priv);
1464                 handled |= CSR_INT_BIT_SW_ERR;
1465         }
1466
1467         /* uCode wakes up after power-down sleep */
1468         if (inta & CSR_INT_BIT_WAKEUP) {
1469                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1470                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1471                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1472                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1473
1474                 priv->isr_stats.wakeup++;
1475
1476                 handled |= CSR_INT_BIT_WAKEUP;
1477         }
1478
1479         /* All uCode command responses, including Tx command responses,
1480          * Rx "responses" (frame-received notification), and other
1481          * notifications from uCode come through here*/
1482         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1483                         CSR_INT_BIT_RX_PERIODIC)) {
1484                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1485                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1486                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1487                         iwl_write32(priv, CSR_FH_INT_STATUS,
1488                                         CSR49_FH_INT_RX_MASK);
1489                 }
1490                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1491                         handled |= CSR_INT_BIT_RX_PERIODIC;
1492                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1493                 }
1494                 /* Sending RX interrupt require many steps to be done in the
1495                  * the device:
1496                  * 1- write interrupt to current index in ICT table.
1497                  * 2- dma RX frame.
1498                  * 3- update RX shared data to indicate last write index.
1499                  * 4- send interrupt.
1500                  * This could lead to RX race, driver could receive RX interrupt
1501                  * but the shared data changes does not reflect this;
1502                  * periodic interrupt will detect any dangling Rx activity.
1503                  */
1504
1505                 /* Disable periodic interrupt; we use it as just a one-shot. */
1506                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1507                             CSR_INT_PERIODIC_DIS);
1508                 iwl_rx_handle(priv);
1509
1510                 /*
1511                  * Enable periodic interrupt in 8 msec only if we received
1512                  * real RX interrupt (instead of just periodic int), to catch
1513                  * any dangling Rx interrupt.  If it was just the periodic
1514                  * interrupt, there was no dangling Rx activity, and no need
1515                  * to extend the periodic interrupt; one-shot is enough.
1516                  */
1517                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1518                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1519                                     CSR_INT_PERIODIC_ENA);
1520
1521                 priv->isr_stats.rx++;
1522         }
1523
1524         /* This "Tx" DMA channel is used only for loading uCode */
1525         if (inta & CSR_INT_BIT_FH_TX) {
1526                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1527                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1528                 priv->isr_stats.tx++;
1529                 handled |= CSR_INT_BIT_FH_TX;
1530                 /* Wake up uCode load routine, now that load is complete */
1531                 priv->ucode_write_complete = 1;
1532                 wake_up_interruptible(&priv->wait_command_queue);
1533         }
1534
1535         if (inta & ~handled) {
1536                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1537                 priv->isr_stats.unhandled++;
1538         }
1539
1540         if (inta & ~(priv->inta_mask)) {
1541                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1542                          inta & ~priv->inta_mask);
1543         }
1544
1545         /* Re-enable all interrupts */
1546         /* only Re-enable if diabled by irq */
1547         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1548                 iwl_enable_interrupts(priv);
1549 }
1550
1551 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1552 #define ACK_CNT_RATIO (50)
1553 #define BA_TIMEOUT_CNT (5)
1554 #define BA_TIMEOUT_MAX (16)
1555
1556 /**
1557  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1558  *
1559  * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1560  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1561  * operation state.
1562  */
1563 bool iwl_good_ack_health(struct iwl_priv *priv,
1564                                 struct iwl_rx_packet *pkt)
1565 {
1566         bool rc = true;
1567         int actual_ack_cnt_delta, expected_ack_cnt_delta;
1568         int ba_timeout_delta;
1569
1570         actual_ack_cnt_delta =
1571                 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1572                 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1573         expected_ack_cnt_delta =
1574                 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1575                 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1576         ba_timeout_delta =
1577                 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1578                 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1579         if ((priv->_agn.agg_tids_count > 0) &&
1580             (expected_ack_cnt_delta > 0) &&
1581             (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1582                 < ACK_CNT_RATIO) &&
1583             (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1584                 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1585                                 " expected_ack_cnt = %d\n",
1586                                 actual_ack_cnt_delta, expected_ack_cnt_delta);
1587
1588 #ifdef CONFIG_IWLWIFI_DEBUGFS
1589                 /*
1590                  * This is ifdef'ed on DEBUGFS because otherwise the
1591                  * statistics aren't available. If DEBUGFS is set but
1592                  * DEBUG is not, these will just compile out.
1593                  */
1594                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1595                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1596                 IWL_DEBUG_RADIO(priv,
1597                                 "ack_or_ba_timeout_collision delta = %d\n",
1598                                 priv->_agn.delta_statistics.tx.
1599                                 ack_or_ba_timeout_collision);
1600 #endif
1601                 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1602                                 ba_timeout_delta);
1603                 if (!actual_ack_cnt_delta &&
1604                     (ba_timeout_delta >= BA_TIMEOUT_MAX))
1605                         rc = false;
1606         }
1607         return rc;
1608 }
1609
1610
1611 /*****************************************************************************
1612  *
1613  * sysfs attributes
1614  *
1615  *****************************************************************************/
1616
1617 #ifdef CONFIG_IWLWIFI_DEBUG
1618
1619 /*
1620  * The following adds a new attribute to the sysfs representation
1621  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1622  * used for controlling the debug level.
1623  *
1624  * See the level definitions in iwl for details.
1625  *
1626  * The debug_level being managed using sysfs below is a per device debug
1627  * level that is used instead of the global debug level if it (the per
1628  * device debug level) is set.
1629  */
1630 static ssize_t show_debug_level(struct device *d,
1631                                 struct device_attribute *attr, char *buf)
1632 {
1633         struct iwl_priv *priv = dev_get_drvdata(d);
1634         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1635 }
1636 static ssize_t store_debug_level(struct device *d,
1637                                 struct device_attribute *attr,
1638                                  const char *buf, size_t count)
1639 {
1640         struct iwl_priv *priv = dev_get_drvdata(d);
1641         unsigned long val;
1642         int ret;
1643
1644         ret = strict_strtoul(buf, 0, &val);
1645         if (ret)
1646                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1647         else {
1648                 priv->debug_level = val;
1649                 if (iwl_alloc_traffic_mem(priv))
1650                         IWL_ERR(priv,
1651                                 "Not enough memory to generate traffic log\n");
1652         }
1653         return strnlen(buf, count);
1654 }
1655
1656 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1657                         show_debug_level, store_debug_level);
1658
1659
1660 #endif /* CONFIG_IWLWIFI_DEBUG */
1661
1662
1663 static ssize_t show_temperature(struct device *d,
1664                                 struct device_attribute *attr, char *buf)
1665 {
1666         struct iwl_priv *priv = dev_get_drvdata(d);
1667
1668         if (!iwl_is_alive(priv))
1669                 return -EAGAIN;
1670
1671         return sprintf(buf, "%d\n", priv->temperature);
1672 }
1673
1674 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1675
1676 static ssize_t show_tx_power(struct device *d,
1677                              struct device_attribute *attr, char *buf)
1678 {
1679         struct iwl_priv *priv = dev_get_drvdata(d);
1680
1681         if (!iwl_is_ready_rf(priv))
1682                 return sprintf(buf, "off\n");
1683         else
1684                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1685 }
1686
1687 static ssize_t store_tx_power(struct device *d,
1688                               struct device_attribute *attr,
1689                               const char *buf, size_t count)
1690 {
1691         struct iwl_priv *priv = dev_get_drvdata(d);
1692         unsigned long val;
1693         int ret;
1694
1695         ret = strict_strtoul(buf, 10, &val);
1696         if (ret)
1697                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1698         else {
1699                 ret = iwl_set_tx_power(priv, val, false);
1700                 if (ret)
1701                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1702                                 ret);
1703                 else
1704                         ret = count;
1705         }
1706         return ret;
1707 }
1708
1709 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1710
1711 static struct attribute *iwl_sysfs_entries[] = {
1712         &dev_attr_temperature.attr,
1713         &dev_attr_tx_power.attr,
1714 #ifdef CONFIG_IWLWIFI_DEBUG
1715         &dev_attr_debug_level.attr,
1716 #endif
1717         NULL
1718 };
1719
1720 static struct attribute_group iwl_attribute_group = {
1721         .name = NULL,           /* put in device directory */
1722         .attrs = iwl_sysfs_entries,
1723 };
1724
1725 /******************************************************************************
1726  *
1727  * uCode download functions
1728  *
1729  ******************************************************************************/
1730
1731 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1732 {
1733         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1734         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1735         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1736         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1737         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1738         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1739 }
1740
1741 static void iwl_nic_start(struct iwl_priv *priv)
1742 {
1743         /* Remove all resets to allow NIC to operate */
1744         iwl_write32(priv, CSR_RESET, 0);
1745 }
1746
1747 struct iwlagn_ucode_capabilities {
1748         u32 max_probe_length;
1749         u32 standard_phy_calibration_size;
1750         bool pan;
1751 };
1752
1753 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1754 static int iwl_mac_setup_register(struct iwl_priv *priv,
1755                                   struct iwlagn_ucode_capabilities *capa);
1756
1757 #define UCODE_EXPERIMENTAL_INDEX        100
1758 #define UCODE_EXPERIMENTAL_TAG          "exp"
1759
1760 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1761 {
1762         const char *name_pre = priv->cfg->fw_name_pre;
1763         char tag[8];
1764
1765         if (first) {
1766 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1767                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1768                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1769         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1770 #endif
1771                 priv->fw_index = priv->cfg->ucode_api_max;
1772                 sprintf(tag, "%d", priv->fw_index);
1773         } else {
1774                 priv->fw_index--;
1775                 sprintf(tag, "%d", priv->fw_index);
1776         }
1777
1778         if (priv->fw_index < priv->cfg->ucode_api_min) {
1779                 IWL_ERR(priv, "no suitable firmware found!\n");
1780                 return -ENOENT;
1781         }
1782
1783         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1784
1785         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1786                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1787                                 ? "EXPERIMENTAL " : "",
1788                        priv->firmware_name);
1789
1790         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1791                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1792                                        iwl_ucode_callback);
1793 }
1794
1795 struct iwlagn_firmware_pieces {
1796         const void *inst, *data, *init, *init_data, *boot;
1797         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1798
1799         u32 build;
1800
1801         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1802         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1803 };
1804
1805 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1806                                        const struct firmware *ucode_raw,
1807                                        struct iwlagn_firmware_pieces *pieces)
1808 {
1809         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1810         u32 api_ver, hdr_size;
1811         const u8 *src;
1812
1813         priv->ucode_ver = le32_to_cpu(ucode->ver);
1814         api_ver = IWL_UCODE_API(priv->ucode_ver);
1815
1816         switch (api_ver) {
1817         default:
1818                 /*
1819                  * 4965 doesn't revision the firmware file format
1820                  * along with the API version, it always uses v1
1821                  * file format.
1822                  */
1823                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1824                                 CSR_HW_REV_TYPE_4965) {
1825                         hdr_size = 28;
1826                         if (ucode_raw->size < hdr_size) {
1827                                 IWL_ERR(priv, "File size too small!\n");
1828                                 return -EINVAL;
1829                         }
1830                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1831                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1832                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1833                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1834                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1835                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1836                         src = ucode->u.v2.data;
1837                         break;
1838                 }
1839                 /* fall through for 4965 */
1840         case 0:
1841         case 1:
1842         case 2:
1843                 hdr_size = 24;
1844                 if (ucode_raw->size < hdr_size) {
1845                         IWL_ERR(priv, "File size too small!\n");
1846                         return -EINVAL;
1847                 }
1848                 pieces->build = 0;
1849                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1850                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1851                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1852                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1853                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1854                 src = ucode->u.v1.data;
1855                 break;
1856         }
1857
1858         /* Verify size of file vs. image size info in file's header */
1859         if (ucode_raw->size != hdr_size + pieces->inst_size +
1860                                 pieces->data_size + pieces->init_size +
1861                                 pieces->init_data_size + pieces->boot_size) {
1862
1863                 IWL_ERR(priv,
1864                         "uCode file size %d does not match expected size\n",
1865                         (int)ucode_raw->size);
1866                 return -EINVAL;
1867         }
1868
1869         pieces->inst = src;
1870         src += pieces->inst_size;
1871         pieces->data = src;
1872         src += pieces->data_size;
1873         pieces->init = src;
1874         src += pieces->init_size;
1875         pieces->init_data = src;
1876         src += pieces->init_data_size;
1877         pieces->boot = src;
1878         src += pieces->boot_size;
1879
1880         return 0;
1881 }
1882
1883 static int iwlagn_wanted_ucode_alternative = 1;
1884
1885 static int iwlagn_load_firmware(struct iwl_priv *priv,
1886                                 const struct firmware *ucode_raw,
1887                                 struct iwlagn_firmware_pieces *pieces,
1888                                 struct iwlagn_ucode_capabilities *capa)
1889 {
1890         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1891         struct iwl_ucode_tlv *tlv;
1892         size_t len = ucode_raw->size;
1893         const u8 *data;
1894         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1895         u64 alternatives;
1896         u32 tlv_len;
1897         enum iwl_ucode_tlv_type tlv_type;
1898         const u8 *tlv_data;
1899
1900         if (len < sizeof(*ucode)) {
1901                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1902                 return -EINVAL;
1903         }
1904
1905         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1906                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1907                         le32_to_cpu(ucode->magic));
1908                 return -EINVAL;
1909         }
1910
1911         /*
1912          * Check which alternatives are present, and "downgrade"
1913          * when the chosen alternative is not present, warning
1914          * the user when that happens. Some files may not have
1915          * any alternatives, so don't warn in that case.
1916          */
1917         alternatives = le64_to_cpu(ucode->alternatives);
1918         tmp = wanted_alternative;
1919         if (wanted_alternative > 63)
1920                 wanted_alternative = 63;
1921         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1922                 wanted_alternative--;
1923         if (wanted_alternative && wanted_alternative != tmp)
1924                 IWL_WARN(priv,
1925                          "uCode alternative %d not available, choosing %d\n",
1926                          tmp, wanted_alternative);
1927
1928         priv->ucode_ver = le32_to_cpu(ucode->ver);
1929         pieces->build = le32_to_cpu(ucode->build);
1930         data = ucode->data;
1931
1932         len -= sizeof(*ucode);
1933
1934         while (len >= sizeof(*tlv)) {
1935                 u16 tlv_alt;
1936
1937                 len -= sizeof(*tlv);
1938                 tlv = (void *)data;
1939
1940                 tlv_len = le32_to_cpu(tlv->length);
1941                 tlv_type = le16_to_cpu(tlv->type);
1942                 tlv_alt = le16_to_cpu(tlv->alternative);
1943                 tlv_data = tlv->data;
1944
1945                 if (len < tlv_len) {
1946                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1947                                 len, tlv_len);
1948                         return -EINVAL;
1949                 }
1950                 len -= ALIGN(tlv_len, 4);
1951                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1952
1953                 /*
1954                  * Alternative 0 is always valid.
1955                  *
1956                  * Skip alternative TLVs that are not selected.
1957                  */
1958                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1959                         continue;
1960
1961                 switch (tlv_type) {
1962                 case IWL_UCODE_TLV_INST:
1963                         pieces->inst = tlv_data;
1964                         pieces->inst_size = tlv_len;
1965                         break;
1966                 case IWL_UCODE_TLV_DATA:
1967                         pieces->data = tlv_data;
1968                         pieces->data_size = tlv_len;
1969                         break;
1970                 case IWL_UCODE_TLV_INIT:
1971                         pieces->init = tlv_data;
1972                         pieces->init_size = tlv_len;
1973                         break;
1974                 case IWL_UCODE_TLV_INIT_DATA:
1975                         pieces->init_data = tlv_data;
1976                         pieces->init_data_size = tlv_len;
1977                         break;
1978                 case IWL_UCODE_TLV_BOOT:
1979                         pieces->boot = tlv_data;
1980                         pieces->boot_size = tlv_len;
1981                         break;
1982                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1983                         if (tlv_len != sizeof(u32))
1984                                 goto invalid_tlv_len;
1985                         capa->max_probe_length =
1986                                         le32_to_cpup((__le32 *)tlv_data);
1987                         break;
1988                 case IWL_UCODE_TLV_PAN:
1989                         if (tlv_len)
1990                                 goto invalid_tlv_len;
1991                         capa->pan = true;
1992                         break;
1993                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1994                         if (tlv_len != sizeof(u32))
1995                                 goto invalid_tlv_len;
1996                         pieces->init_evtlog_ptr =
1997                                         le32_to_cpup((__le32 *)tlv_data);
1998                         break;
1999                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
2000                         if (tlv_len != sizeof(u32))
2001                                 goto invalid_tlv_len;
2002                         pieces->init_evtlog_size =
2003                                         le32_to_cpup((__le32 *)tlv_data);
2004                         break;
2005                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
2006                         if (tlv_len != sizeof(u32))
2007                                 goto invalid_tlv_len;
2008                         pieces->init_errlog_ptr =
2009                                         le32_to_cpup((__le32 *)tlv_data);
2010                         break;
2011                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
2012                         if (tlv_len != sizeof(u32))
2013                                 goto invalid_tlv_len;
2014                         pieces->inst_evtlog_ptr =
2015                                         le32_to_cpup((__le32 *)tlv_data);
2016                         break;
2017                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
2018                         if (tlv_len != sizeof(u32))
2019                                 goto invalid_tlv_len;
2020                         pieces->inst_evtlog_size =
2021                                         le32_to_cpup((__le32 *)tlv_data);
2022                         break;
2023                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
2024                         if (tlv_len != sizeof(u32))
2025                                 goto invalid_tlv_len;
2026                         pieces->inst_errlog_ptr =
2027                                         le32_to_cpup((__le32 *)tlv_data);
2028                         break;
2029                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
2030                         if (tlv_len)
2031                                 goto invalid_tlv_len;
2032                         priv->enhance_sensitivity_table = true;
2033                         break;
2034                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
2035                         if (tlv_len != sizeof(u32))
2036                                 goto invalid_tlv_len;
2037                         capa->standard_phy_calibration_size =
2038                                         le32_to_cpup((__le32 *)tlv_data);
2039                         break;
2040                 default:
2041                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
2042                         break;
2043                 }
2044         }
2045
2046         if (len) {
2047                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2048                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
2049                 return -EINVAL;
2050         }
2051
2052         return 0;
2053
2054  invalid_tlv_len:
2055         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2056         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2057
2058         return -EINVAL;
2059 }
2060
2061 /**
2062  * iwl_ucode_callback - callback when firmware was loaded
2063  *
2064  * If loaded successfully, copies the firmware into buffers
2065  * for the card to fetch (via DMA).
2066  */
2067 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
2068 {
2069         struct iwl_priv *priv = context;
2070         struct iwl_ucode_header *ucode;
2071         int err;
2072         struct iwlagn_firmware_pieces pieces;
2073         const unsigned int api_max = priv->cfg->ucode_api_max;
2074         const unsigned int api_min = priv->cfg->ucode_api_min;
2075         u32 api_ver;
2076         char buildstr[25];
2077         u32 build;
2078         struct iwlagn_ucode_capabilities ucode_capa = {
2079                 .max_probe_length = 200,
2080                 .standard_phy_calibration_size =
2081                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
2082         };
2083
2084         memset(&pieces, 0, sizeof(pieces));
2085
2086         if (!ucode_raw) {
2087                 if (priv->fw_index <= priv->cfg->ucode_api_max)
2088                         IWL_ERR(priv,
2089                                 "request for firmware file '%s' failed.\n",
2090                                 priv->firmware_name);
2091                 goto try_again;
2092         }
2093
2094         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2095                        priv->firmware_name, ucode_raw->size);
2096
2097         /* Make sure that we got at least the API version number */
2098         if (ucode_raw->size < 4) {
2099                 IWL_ERR(priv, "File size way too small!\n");
2100                 goto try_again;
2101         }
2102
2103         /* Data from ucode file:  header followed by uCode images */
2104         ucode = (struct iwl_ucode_header *)ucode_raw->data;
2105
2106         if (ucode->ver)
2107                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2108         else
2109                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2110                                            &ucode_capa);
2111
2112         if (err)
2113                 goto try_again;
2114
2115         api_ver = IWL_UCODE_API(priv->ucode_ver);
2116         build = pieces.build;
2117
2118         /*
2119          * api_ver should match the api version forming part of the
2120          * firmware filename ... but we don't check for that and only rely
2121          * on the API version read from firmware header from here on forward
2122          */
2123         if (api_ver < api_min || api_ver > api_max) {
2124                 IWL_ERR(priv, "Driver unable to support your firmware API. "
2125                           "Driver supports v%u, firmware is v%u.\n",
2126                           api_max, api_ver);
2127                 goto try_again;
2128         }
2129
2130         if (api_ver != api_max)
2131                 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
2132                           "got v%u. New firmware can be obtained "
2133                           "from http://www.intellinuxwireless.org.\n",
2134                           api_max, api_ver);
2135
2136         if (build)
2137                 sprintf(buildstr, " build %u%s", build,
2138                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2139                                 ? " (EXP)" : "");
2140         else
2141                 buildstr[0] = '\0';
2142
2143         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2144                  IWL_UCODE_MAJOR(priv->ucode_ver),
2145                  IWL_UCODE_MINOR(priv->ucode_ver),
2146                  IWL_UCODE_API(priv->ucode_ver),
2147                  IWL_UCODE_SERIAL(priv->ucode_ver),
2148                  buildstr);
2149
2150         snprintf(priv->hw->wiphy->fw_version,
2151                  sizeof(priv->hw->wiphy->fw_version),
2152                  "%u.%u.%u.%u%s",
2153                  IWL_UCODE_MAJOR(priv->ucode_ver),
2154                  IWL_UCODE_MINOR(priv->ucode_ver),
2155                  IWL_UCODE_API(priv->ucode_ver),
2156                  IWL_UCODE_SERIAL(priv->ucode_ver),
2157                  buildstr);
2158
2159         /*
2160          * For any of the failures below (before allocating pci memory)
2161          * we will try to load a version with a smaller API -- maybe the
2162          * user just got a corrupted version of the latest API.
2163          */
2164
2165         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2166                        priv->ucode_ver);
2167         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2168                        pieces.inst_size);
2169         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2170                        pieces.data_size);
2171         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2172                        pieces.init_size);
2173         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2174                        pieces.init_data_size);
2175         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2176                        pieces.boot_size);
2177
2178         /* Verify that uCode images will fit in card's SRAM */
2179         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2180                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2181                         pieces.inst_size);
2182                 goto try_again;
2183         }
2184
2185         if (pieces.data_size > priv->hw_params.max_data_size) {
2186                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2187                         pieces.data_size);
2188                 goto try_again;
2189         }
2190
2191         if (pieces.init_size > priv->hw_params.max_inst_size) {
2192                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2193                         pieces.init_size);
2194                 goto try_again;
2195         }
2196
2197         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2198                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2199                         pieces.init_data_size);
2200                 goto try_again;
2201         }
2202
2203         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2204                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2205                         pieces.boot_size);
2206                 goto try_again;
2207         }
2208
2209         /* Allocate ucode buffers for card's bus-master loading ... */
2210
2211         /* Runtime instructions and 2 copies of data:
2212          * 1) unmodified from disk
2213          * 2) backup cache for save/restore during power-downs */
2214         priv->ucode_code.len = pieces.inst_size;
2215         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2216
2217         priv->ucode_data.len = pieces.data_size;
2218         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2219
2220         priv->ucode_data_backup.len = pieces.data_size;
2221         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2222
2223         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2224             !priv->ucode_data_backup.v_addr)
2225                 goto err_pci_alloc;
2226
2227         /* Initialization instructions and data */
2228         if (pieces.init_size && pieces.init_data_size) {
2229                 priv->ucode_init.len = pieces.init_size;
2230                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2231
2232                 priv->ucode_init_data.len = pieces.init_data_size;
2233                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2234
2235                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2236                         goto err_pci_alloc;
2237         }
2238
2239         /* Bootstrap (instructions only, no data) */
2240         if (pieces.boot_size) {
2241                 priv->ucode_boot.len = pieces.boot_size;
2242                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2243
2244                 if (!priv->ucode_boot.v_addr)
2245                         goto err_pci_alloc;
2246         }
2247
2248         /* Now that we can no longer fail, copy information */
2249
2250         /*
2251          * The (size - 16) / 12 formula is based on the information recorded
2252          * for each event, which is of mode 1 (including timestamp) for all
2253          * new microcodes that include this information.
2254          */
2255         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2256         if (pieces.init_evtlog_size)
2257                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2258         else
2259                 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2260         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2261         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2262         if (pieces.inst_evtlog_size)
2263                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2264         else
2265                 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2266         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2267
2268         if (ucode_capa.pan) {
2269                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2270                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2271         } else
2272                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2273
2274         /* Copy images into buffers for card's bus-master reads ... */
2275
2276         /* Runtime instructions (first block of data in file) */
2277         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2278                         pieces.inst_size);
2279         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2280
2281         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2282                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2283
2284         /*
2285          * Runtime data
2286          * NOTE:  Copy into backup buffer will be done in iwl_up()
2287          */
2288         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2289                         pieces.data_size);
2290         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2291         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2292
2293         /* Initialization instructions */
2294         if (pieces.init_size) {
2295                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2296                                 pieces.init_size);
2297                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2298         }
2299
2300         /* Initialization data */
2301         if (pieces.init_data_size) {
2302                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2303                                pieces.init_data_size);
2304                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2305                        pieces.init_data_size);
2306         }
2307
2308         /* Bootstrap instructions */
2309         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2310                         pieces.boot_size);
2311         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2312
2313         /*
2314          * figure out the offset of chain noise reset and gain commands
2315          * base on the size of standard phy calibration commands table size
2316          */
2317         if (ucode_capa.standard_phy_calibration_size >
2318             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2319                 ucode_capa.standard_phy_calibration_size =
2320                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2321
2322         priv->_agn.phy_calib_chain_noise_reset_cmd =
2323                 ucode_capa.standard_phy_calibration_size;
2324         priv->_agn.phy_calib_chain_noise_gain_cmd =
2325                 ucode_capa.standard_phy_calibration_size + 1;
2326
2327         /**************************************************
2328          * This is still part of probe() in a sense...
2329          *
2330          * 9. Setup and register with mac80211 and debugfs
2331          **************************************************/
2332         err = iwl_mac_setup_register(priv, &ucode_capa);
2333         if (err)
2334                 goto out_unbind;
2335
2336         err = iwl_dbgfs_register(priv, DRV_NAME);
2337         if (err)
2338                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2339
2340         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2341                                         &iwl_attribute_group);
2342         if (err) {
2343                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2344                 goto out_unbind;
2345         }
2346
2347         /* We have our copies now, allow OS release its copies */
2348         release_firmware(ucode_raw);
2349         complete(&priv->_agn.firmware_loading_complete);
2350         return;
2351
2352  try_again:
2353         /* try next, if any */
2354         if (iwl_request_firmware(priv, false))
2355                 goto out_unbind;
2356         release_firmware(ucode_raw);
2357         return;
2358
2359  err_pci_alloc:
2360         IWL_ERR(priv, "failed to allocate pci memory\n");
2361         iwl_dealloc_ucode_pci(priv);
2362  out_unbind:
2363         complete(&priv->_agn.firmware_loading_complete);
2364         device_release_driver(&priv->pci_dev->dev);
2365         release_firmware(ucode_raw);
2366 }
2367
2368 static const char *desc_lookup_text[] = {
2369         "OK",
2370         "FAIL",
2371         "BAD_PARAM",
2372         "BAD_CHECKSUM",
2373         "NMI_INTERRUPT_WDG",
2374         "SYSASSERT",
2375         "FATAL_ERROR",
2376         "BAD_COMMAND",
2377         "HW_ERROR_TUNE_LOCK",
2378         "HW_ERROR_TEMPERATURE",
2379         "ILLEGAL_CHAN_FREQ",
2380         "VCC_NOT_STABLE",
2381         "FH_ERROR",
2382         "NMI_INTERRUPT_HOST",
2383         "NMI_INTERRUPT_ACTION_PT",
2384         "NMI_INTERRUPT_UNKNOWN",
2385         "UCODE_VERSION_MISMATCH",
2386         "HW_ERROR_ABS_LOCK",
2387         "HW_ERROR_CAL_LOCK_FAIL",
2388         "NMI_INTERRUPT_INST_ACTION_PT",
2389         "NMI_INTERRUPT_DATA_ACTION_PT",
2390         "NMI_TRM_HW_ER",
2391         "NMI_INTERRUPT_TRM",
2392         "NMI_INTERRUPT_BREAK_POINT"
2393         "DEBUG_0",
2394         "DEBUG_1",
2395         "DEBUG_2",
2396         "DEBUG_3",
2397 };
2398
2399 static struct { char *name; u8 num; } advanced_lookup[] = {
2400         { "NMI_INTERRUPT_WDG", 0x34 },
2401         { "SYSASSERT", 0x35 },
2402         { "UCODE_VERSION_MISMATCH", 0x37 },
2403         { "BAD_COMMAND", 0x38 },
2404         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2405         { "FATAL_ERROR", 0x3D },
2406         { "NMI_TRM_HW_ERR", 0x46 },
2407         { "NMI_INTERRUPT_TRM", 0x4C },
2408         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2409         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2410         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2411         { "NMI_INTERRUPT_HOST", 0x66 },
2412         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2413         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2414         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2415         { "ADVANCED_SYSASSERT", 0 },
2416 };
2417
2418 static const char *desc_lookup(u32 num)
2419 {
2420         int i;
2421         int max = ARRAY_SIZE(desc_lookup_text);
2422
2423         if (num < max)
2424                 return desc_lookup_text[num];
2425
2426         max = ARRAY_SIZE(advanced_lookup) - 1;
2427         for (i = 0; i < max; i++) {
2428                 if (advanced_lookup[i].num == num)
2429                         break;;
2430         }
2431         return advanced_lookup[i].name;
2432 }
2433
2434 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2435 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2436
2437 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2438 {
2439         u32 data2, line;
2440         u32 desc, time, count, base, data1;
2441         u32 blink1, blink2, ilink1, ilink2;
2442         u32 pc, hcmd;
2443
2444         if (priv->ucode_type == UCODE_INIT) {
2445                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2446                 if (!base)
2447                         base = priv->_agn.init_errlog_ptr;
2448         } else {
2449                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2450                 if (!base)
2451                         base = priv->_agn.inst_errlog_ptr;
2452         }
2453
2454         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2455                 IWL_ERR(priv,
2456                         "Not valid error log pointer 0x%08X for %s uCode\n",
2457                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2458                 return;
2459         }
2460
2461         count = iwl_read_targ_mem(priv, base);
2462
2463         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2464                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2465                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2466                         priv->status, count);
2467         }
2468
2469         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2470         priv->isr_stats.err_code = desc;
2471         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2472         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2473         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2474         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2475         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2476         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2477         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2478         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2479         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2480         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2481
2482         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2483                                       blink1, blink2, ilink1, ilink2);
2484
2485         IWL_ERR(priv, "Desc                                  Time       "
2486                 "data1      data2      line\n");
2487         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2488                 desc_lookup(desc), desc, time, data1, data2, line);
2489         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2490         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2491                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2492 }
2493
2494 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2495
2496 /**
2497  * iwl_print_event_log - Dump error event log to syslog
2498  *
2499  */
2500 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2501                                u32 num_events, u32 mode,
2502                                int pos, char **buf, size_t bufsz)
2503 {
2504         u32 i;
2505         u32 base;       /* SRAM byte address of event log header */
2506         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2507         u32 ptr;        /* SRAM byte address of log data */
2508         u32 ev, time, data; /* event log data */
2509         unsigned long reg_flags;
2510
2511         if (num_events == 0)
2512                 return pos;
2513
2514         if (priv->ucode_type == UCODE_INIT) {
2515                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2516                 if (!base)
2517                         base = priv->_agn.init_evtlog_ptr;
2518         } else {
2519                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2520                 if (!base)
2521                         base = priv->_agn.inst_evtlog_ptr;
2522         }
2523
2524         if (mode == 0)
2525                 event_size = 2 * sizeof(u32);
2526         else
2527                 event_size = 3 * sizeof(u32);
2528
2529         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2530
2531         /* Make sure device is powered up for SRAM reads */
2532         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2533         iwl_grab_nic_access(priv);
2534
2535         /* Set starting address; reads will auto-increment */
2536         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2537         rmb();
2538
2539         /* "time" is actually "data" for mode 0 (no timestamp).
2540         * place event id # at far right for easier visual parsing. */
2541         for (i = 0; i < num_events; i++) {
2542                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2543                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2544                 if (mode == 0) {
2545                         /* data, ev */
2546                         if (bufsz) {
2547                                 pos += scnprintf(*buf + pos, bufsz - pos,
2548                                                 "EVT_LOG:0x%08x:%04u\n",
2549                                                 time, ev);
2550                         } else {
2551                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2552                                         time, ev);
2553                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2554                                         time, ev);
2555                         }
2556                 } else {
2557                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2558                         if (bufsz) {
2559                                 pos += scnprintf(*buf + pos, bufsz - pos,
2560                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2561                                                  time, data, ev);
2562                         } else {
2563                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2564                                         time, data, ev);
2565                                 trace_iwlwifi_dev_ucode_event(priv, time,
2566                                         data, ev);
2567                         }
2568                 }
2569         }
2570
2571         /* Allow device to power down */
2572         iwl_release_nic_access(priv);
2573         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2574         return pos;
2575 }
2576
2577 /**
2578  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2579  */
2580 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2581                                     u32 num_wraps, u32 next_entry,
2582                                     u32 size, u32 mode,
2583                                     int pos, char **buf, size_t bufsz)
2584 {
2585         /*
2586          * display the newest DEFAULT_LOG_ENTRIES entries
2587          * i.e the entries just before the next ont that uCode would fill.
2588          */
2589         if (num_wraps) {
2590                 if (next_entry < size) {
2591                         pos = iwl_print_event_log(priv,
2592                                                 capacity - (size - next_entry),
2593                                                 size - next_entry, mode,
2594                                                 pos, buf, bufsz);
2595                         pos = iwl_print_event_log(priv, 0,
2596                                                   next_entry, mode,
2597                                                   pos, buf, bufsz);
2598                 } else
2599                         pos = iwl_print_event_log(priv, next_entry - size,
2600                                                   size, mode, pos, buf, bufsz);
2601         } else {
2602                 if (next_entry < size) {
2603                         pos = iwl_print_event_log(priv, 0, next_entry,
2604                                                   mode, pos, buf, bufsz);
2605                 } else {
2606                         pos = iwl_print_event_log(priv, next_entry - size,
2607                                                   size, mode, pos, buf, bufsz);
2608                 }
2609         }
2610         return pos;
2611 }
2612
2613 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2614
2615 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2616                             char **buf, bool display)
2617 {
2618         u32 base;       /* SRAM byte address of event log header */
2619         u32 capacity;   /* event log capacity in # entries */
2620         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2621         u32 num_wraps;  /* # times uCode wrapped to top of log */
2622         u32 next_entry; /* index of next entry to be written by uCode */
2623         u32 size;       /* # entries that we'll print */
2624         u32 logsize;
2625         int pos = 0;
2626         size_t bufsz = 0;
2627
2628         if (priv->ucode_type == UCODE_INIT) {
2629                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2630                 logsize = priv->_agn.init_evtlog_size;
2631                 if (!base)
2632                         base = priv->_agn.init_evtlog_ptr;
2633         } else {
2634                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2635                 logsize = priv->_agn.inst_evtlog_size;
2636                 if (!base)
2637                         base = priv->_agn.inst_evtlog_ptr;
2638         }
2639
2640         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2641                 IWL_ERR(priv,
2642                         "Invalid event log pointer 0x%08X for %s uCode\n",
2643                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2644                 return -EINVAL;
2645         }
2646
2647         /* event log header */
2648         capacity = iwl_read_targ_mem(priv, base);
2649         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2650         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2651         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2652
2653         if (capacity > logsize) {
2654                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2655                         capacity, logsize);
2656                 capacity = logsize;
2657         }
2658
2659         if (next_entry > logsize) {
2660                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2661                         next_entry, logsize);
2662                 next_entry = logsize;
2663         }
2664
2665         size = num_wraps ? capacity : next_entry;
2666
2667         /* bail out if nothing in log */
2668         if (size == 0) {
2669                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2670                 return pos;
2671         }
2672
2673         /* enable/disable bt channel announcement */
2674         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2675
2676 #ifdef CONFIG_IWLWIFI_DEBUG
2677         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2678                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2679                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2680 #else
2681         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2682                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2683 #endif
2684         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2685                 size);
2686
2687 #ifdef CONFIG_IWLWIFI_DEBUG
2688         if (display) {
2689                 if (full_log)
2690                         bufsz = capacity * 48;
2691                 else
2692                         bufsz = size * 48;
2693                 *buf = kmalloc(bufsz, GFP_KERNEL);
2694                 if (!*buf)
2695                         return -ENOMEM;
2696         }
2697         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2698                 /*
2699                  * if uCode has wrapped back to top of log,
2700                  * start at the oldest entry,
2701                  * i.e the next one that uCode would fill.
2702                  */
2703                 if (num_wraps)
2704                         pos = iwl_print_event_log(priv, next_entry,
2705                                                 capacity - next_entry, mode,
2706                                                 pos, buf, bufsz);
2707                 /* (then/else) start at top of log */
2708                 pos = iwl_print_event_log(priv, 0,
2709                                           next_entry, mode, pos, buf, bufsz);
2710         } else
2711                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2712                                                 next_entry, size, mode,
2713                                                 pos, buf, bufsz);
2714 #else
2715         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2716                                         next_entry, size, mode,
2717                                         pos, buf, bufsz);
2718 #endif
2719         return pos;
2720 }
2721
2722 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2723 {
2724         struct iwl_ct_kill_config cmd;
2725         struct iwl_ct_kill_throttling_config adv_cmd;
2726         unsigned long flags;
2727         int ret = 0;
2728
2729         spin_lock_irqsave(&priv->lock, flags);
2730         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2731                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2732         spin_unlock_irqrestore(&priv->lock, flags);
2733         priv->thermal_throttle.ct_kill_toggle = false;
2734
2735         if (priv->cfg->support_ct_kill_exit) {
2736                 adv_cmd.critical_temperature_enter =
2737                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2738                 adv_cmd.critical_temperature_exit =
2739                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2740
2741                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2742                                        sizeof(adv_cmd), &adv_cmd);
2743                 if (ret)
2744                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2745                 else
2746                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2747                                         "succeeded, "
2748                                         "critical temperature enter is %d,"
2749                                         "exit is %d\n",
2750                                        priv->hw_params.ct_kill_threshold,
2751                                        priv->hw_params.ct_kill_exit_threshold);
2752         } else {
2753                 cmd.critical_temperature_R =
2754                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2755
2756                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2757                                        sizeof(cmd), &cmd);
2758                 if (ret)
2759                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2760                 else
2761                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2762                                         "succeeded, "
2763                                         "critical temperature is %d\n",
2764                                         priv->hw_params.ct_kill_threshold);
2765         }
2766 }
2767
2768 /**
2769  * iwl_alive_start - called after REPLY_ALIVE notification received
2770  *                   from protocol/runtime uCode (initialization uCode's
2771  *                   Alive gets handled by iwl_init_alive_start()).
2772  */
2773 static void iwl_alive_start(struct iwl_priv *priv)
2774 {
2775         int ret = 0;
2776         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2777
2778         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2779
2780         if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2781                 /* We had an error bringing up the hardware, so take it
2782                  * all the way back down so we can try again */
2783                 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2784                 goto restart;
2785         }
2786
2787         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2788          * This is a paranoid check, because we would not have gotten the
2789          * "runtime" alive if code weren't properly loaded.  */
2790         if (iwl_verify_ucode(priv)) {
2791                 /* Runtime instruction load was bad;
2792                  * take it all the way back down so we can try again */
2793                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2794                 goto restart;
2795         }
2796
2797         ret = priv->cfg->ops->lib->alive_notify(priv);
2798         if (ret) {
2799                 IWL_WARN(priv,
2800                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2801                 goto restart;
2802         }
2803
2804         /* After the ALIVE response, we can send host commands to the uCode */
2805         set_bit(STATUS_ALIVE, &priv->status);
2806
2807         if (priv->cfg->ops->lib->recover_from_tx_stall) {
2808                 /* Enable timer to monitor the driver queues */
2809                 mod_timer(&priv->monitor_recover,
2810                         jiffies +
2811                         msecs_to_jiffies(priv->cfg->monitor_recover_period));
2812         }
2813
2814         if (iwl_is_rfkill(priv))
2815                 return;
2816
2817         if (priv->cfg->advanced_bt_coexist) {
2818                 /* Configure Bluetooth device coexistence support */
2819                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2820                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2821                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2822                 priv->cfg->ops->hcmd->send_bt_config(priv);
2823                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2824                 if (bt_coex_active && priv->iw_mode != NL80211_IFTYPE_ADHOC)
2825                         iwlagn_send_prio_tbl(priv);
2826
2827                 /* FIXME: w/a to force change uCode BT state machine */
2828                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2829                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2830                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2831                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2832         }
2833         ieee80211_wake_queues(priv->hw);
2834
2835         priv->active_rate = IWL_RATES_MASK;
2836
2837         /* Configure Tx antenna selection based on H/W config */
2838         if (priv->cfg->ops->hcmd->set_tx_ant)
2839                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2840
2841         if (iwl_is_associated_ctx(ctx)) {
2842                 struct iwl_rxon_cmd *active_rxon =
2843                                 (struct iwl_rxon_cmd *)&ctx->active;
2844                 /* apply any changes in staging */
2845                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2846                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2847         } else {
2848                 struct iwl_rxon_context *tmp;
2849                 /* Initialize our rx_config data */
2850                 for_each_context(priv, tmp)
2851                         iwl_connection_init_rx_config(priv, tmp);
2852
2853                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2854                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2855         }
2856
2857         if (!priv->cfg->advanced_bt_coexist) {
2858                 /* Configure Bluetooth device coexistence support */
2859                 priv->cfg->ops->hcmd->send_bt_config(priv);
2860         }
2861
2862         iwl_reset_run_time_calib(priv);
2863
2864         /* Configure the adapter for unassociated operation */
2865         iwlcore_commit_rxon(priv, ctx);
2866
2867         /* At this point, the NIC is initialized and operational */
2868         iwl_rf_kill_ct_config(priv);
2869
2870         iwl_leds_init(priv);
2871
2872         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2873         set_bit(STATUS_READY, &priv->status);
2874         wake_up_interruptible(&priv->wait_command_queue);
2875
2876         iwl_power_update_mode(priv, true);
2877         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2878
2879
2880         return;
2881
2882  restart:
2883         queue_work(priv->workqueue, &priv->restart);
2884 }
2885
2886 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2887
2888 static void __iwl_down(struct iwl_priv *priv)
2889 {
2890         unsigned long flags;
2891         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2892
2893         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2894
2895         iwl_scan_cancel_timeout(priv, 200);
2896
2897         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2898
2899         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2900          * to prevent rearm timer */
2901         if (priv->cfg->ops->lib->recover_from_tx_stall)
2902                 del_timer_sync(&priv->monitor_recover);
2903
2904         iwl_clear_ucode_stations(priv, NULL);
2905         iwl_dealloc_bcast_stations(priv);
2906         iwl_clear_driver_stations(priv);
2907
2908         /* reset BT coex data */
2909         priv->bt_status = 0;
2910         priv->bt_traffic_load = priv->cfg->bt_init_traffic_load;
2911         priv->bt_sco_active = false;
2912         priv->bt_full_concurrent = false;
2913         priv->bt_ci_compliance = 0;
2914
2915         /* Unblock any waiting calls */
2916         wake_up_interruptible_all(&priv->wait_command_queue);
2917
2918         /* Wipe out the EXIT_PENDING status bit if we are not actually
2919          * exiting the module */
2920         if (!exit_pending)
2921                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2922
2923         /* stop and reset the on-board processor */
2924         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2925
2926         /* tell the device to stop sending interrupts */
2927         spin_lock_irqsave(&priv->lock, flags);
2928         iwl_disable_interrupts(priv);
2929         spin_unlock_irqrestore(&priv->lock, flags);
2930         iwl_synchronize_irq(priv);
2931
2932         if (priv->mac80211_registered)
2933                 ieee80211_stop_queues(priv->hw);
2934
2935         /* If we have not previously called iwl_init() then
2936          * clear all bits but the RF Kill bit and return */
2937         if (!iwl_is_init(priv)) {
2938                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2939                                         STATUS_RF_KILL_HW |
2940                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2941                                         STATUS_GEO_CONFIGURED |
2942                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2943                                         STATUS_EXIT_PENDING;
2944                 goto exit;
2945         }
2946
2947         /* ...otherwise clear out all the status bits but the RF Kill
2948          * bit and continue taking the NIC down. */
2949         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2950                                 STATUS_RF_KILL_HW |
2951                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2952                                 STATUS_GEO_CONFIGURED |
2953                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2954                                 STATUS_FW_ERROR |
2955                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2956                                 STATUS_EXIT_PENDING;
2957
2958         /* device going down, Stop using ICT table */
2959         iwl_disable_ict(priv);
2960
2961         iwlagn_txq_ctx_stop(priv);
2962         iwlagn_rxq_stop(priv);
2963
2964         /* Power-down device's busmaster DMA clocks */
2965         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2966         udelay(5);
2967
2968         /* Make sure (redundant) we've released our request to stay awake */
2969         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2970
2971         /* Stop the device, and put it in low power state */
2972         priv->cfg->ops->lib->apm_ops.stop(priv);
2973
2974  exit:
2975         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2976
2977         if (priv->ibss_beacon)
2978                 dev_kfree_skb(priv->ibss_beacon);
2979         priv->ibss_beacon = NULL;
2980
2981         /* clear out any free frames */
2982         iwl_clear_free_frames(priv);
2983 }
2984
2985 static void iwl_down(struct iwl_priv *priv)
2986 {
2987         mutex_lock(&priv->mutex);
2988         __iwl_down(priv);
2989         mutex_unlock(&priv->mutex);
2990
2991         iwl_cancel_deferred_work(priv);
2992 }
2993
2994 #define HW_READY_TIMEOUT (50)
2995
2996 static int iwl_set_hw_ready(struct iwl_priv *priv)
2997 {
2998         int ret = 0;
2999
3000         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3001                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
3002
3003         /* See if we got it */
3004         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3005                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3006                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3007                                 HW_READY_TIMEOUT);
3008         if (ret != -ETIMEDOUT)
3009                 priv->hw_ready = true;
3010         else
3011                 priv->hw_ready = false;
3012
3013         IWL_DEBUG_INFO(priv, "hardware %s\n",
3014                       (priv->hw_ready == 1) ? "ready" : "not ready");
3015         return ret;
3016 }
3017
3018 static int iwl_prepare_card_hw(struct iwl_priv *priv)
3019 {
3020         int ret = 0;
3021
3022         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
3023
3024         ret = iwl_set_hw_ready(priv);
3025         if (priv->hw_ready)
3026                 return ret;
3027
3028         /* If HW is not ready, prepare the conditions to check again */
3029         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3030                         CSR_HW_IF_CONFIG_REG_PREPARE);
3031
3032         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3033                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
3034                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
3035
3036         /* HW should be ready by now, check again. */
3037         if (ret != -ETIMEDOUT)
3038                 iwl_set_hw_ready(priv);
3039
3040         return ret;
3041 }
3042
3043 #define MAX_HW_RESTARTS 5
3044
3045 static int __iwl_up(struct iwl_priv *priv)
3046 {
3047         struct iwl_rxon_context *ctx;
3048         int i;
3049         int ret;
3050
3051         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3052                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
3053                 return -EIO;
3054         }
3055
3056         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
3057                 IWL_ERR(priv, "ucode not available for device bringup\n");
3058                 return -EIO;
3059         }
3060
3061         for_each_context(priv, ctx) {
3062                 ret = iwl_alloc_bcast_station(priv, ctx, true);
3063                 if (ret) {
3064                         iwl_dealloc_bcast_stations(priv);
3065                         return ret;
3066                 }
3067         }
3068
3069         iwl_prepare_card_hw(priv);
3070
3071         if (!priv->hw_ready) {
3072                 IWL_WARN(priv, "Exit HW not ready\n");
3073                 return -EIO;
3074         }
3075
3076         /* If platform's RF_KILL switch is NOT set to KILL */
3077         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3078                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3079         else
3080                 set_bit(STATUS_RF_KILL_HW, &priv->status);
3081
3082         if (iwl_is_rfkill(priv)) {
3083                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3084
3085                 iwl_enable_interrupts(priv);
3086                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
3087                 return 0;
3088         }
3089
3090         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3091
3092         /* must be initialised before iwl_hw_nic_init */
3093         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3094                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3095         else
3096                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
3097
3098         ret = iwlagn_hw_nic_init(priv);
3099         if (ret) {
3100                 IWL_ERR(priv, "Unable to init nic\n");
3101                 return ret;
3102         }
3103
3104         /* make sure rfkill handshake bits are cleared */
3105         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3106         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
3107                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3108
3109         /* clear (again), then enable host interrupts */
3110         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3111         iwl_enable_interrupts(priv);
3112
3113         /* really make sure rfkill handshake bits are cleared */
3114         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3115         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3116
3117         /* Copy original ucode data image from disk into backup cache.
3118          * This will be used to initialize the on-board processor's
3119          * data SRAM for a clean start when the runtime program first loads. */
3120         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
3121                priv->ucode_data.len);
3122
3123         for (i = 0; i < MAX_HW_RESTARTS; i++) {
3124
3125                 /* load bootstrap state machine,
3126                  * load bootstrap program into processor's memory,
3127                  * prepare to load the "initialize" uCode */
3128                 ret = priv->cfg->ops->lib->load_ucode(priv);
3129
3130                 if (ret) {
3131                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3132                                 ret);
3133                         continue;
3134                 }
3135
3136                 /* start card; "initialize" will load runtime ucode */
3137                 iwl_nic_start(priv);
3138
3139                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3140
3141                 return 0;
3142         }
3143
3144         set_bit(STATUS_EXIT_PENDING, &priv->status);
3145         __iwl_down(priv);
3146         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3147
3148         /* tried to restart and config the device for as long as our
3149          * patience could withstand */
3150         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3151         return -EIO;
3152 }
3153
3154
3155 /*****************************************************************************
3156  *
3157  * Workqueue callbacks
3158  *
3159  *****************************************************************************/
3160
3161 static void iwl_bg_init_alive_start(struct work_struct *data)
3162 {
3163         struct iwl_priv *priv =
3164             container_of(data, struct iwl_priv, init_alive_start.work);
3165
3166         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3167                 return;
3168
3169         mutex_lock(&priv->mutex);
3170         priv->cfg->ops->lib->init_alive_start(priv);
3171         mutex_unlock(&priv->mutex);
3172 }
3173
3174 static void iwl_bg_alive_start(struct work_struct *data)
3175 {
3176         struct iwl_priv *priv =
3177             container_of(data, struct iwl_priv, alive_start.work);
3178
3179         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3180                 return;
3181
3182         /* enable dram interrupt */
3183         iwl_reset_ict(priv);
3184
3185         mutex_lock(&priv->mutex);
3186         iwl_alive_start(priv);
3187         mutex_unlock(&priv->mutex);
3188 }
3189
3190 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3191 {
3192         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3193                         run_time_calib_work);
3194
3195         mutex_lock(&priv->mutex);
3196
3197         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3198             test_bit(STATUS_SCANNING, &priv->status)) {
3199                 mutex_unlock(&priv->mutex);
3200                 return;
3201         }
3202
3203         if (priv->start_calib) {
3204                 if (priv->cfg->bt_statistics) {
3205                         iwl_chain_noise_calibration(priv,
3206                                         (void *)&priv->_agn.statistics_bt);
3207                         iwl_sensitivity_calibration(priv,
3208                                         (void *)&priv->_agn.statistics_bt);
3209                 } else {
3210                         iwl_chain_noise_calibration(priv,
3211                                         (void *)&priv->_agn.statistics);
3212                         iwl_sensitivity_calibration(priv,
3213                                         (void *)&priv->_agn.statistics);
3214                 }
3215         }
3216
3217         mutex_unlock(&priv->mutex);
3218 }
3219
3220 static void iwl_bg_restart(struct work_struct *data)
3221 {
3222         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3223
3224         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3225                 return;
3226
3227         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3228                 struct iwl_rxon_context *ctx;
3229                 bool bt_sco, bt_full_concurrent;
3230                 u8 bt_ci_compliance;
3231                 u8 bt_load;
3232                 u8 bt_status;
3233
3234                 mutex_lock(&priv->mutex);
3235                 for_each_context(priv, ctx)
3236                         ctx->vif = NULL;
3237                 priv->is_open = 0;
3238
3239                 /*
3240                  * __iwl_down() will clear the BT status variables,
3241                  * which is correct, but when we restart we really
3242                  * want to keep them so restore them afterwards.
3243                  *
3244                  * The restart process will later pick them up and
3245                  * re-configure the hw when we reconfigure the BT
3246                  * command.
3247                  */
3248                 bt_sco = priv->bt_sco_active;
3249                 bt_full_concurrent = priv->bt_full_concurrent;
3250                 bt_ci_compliance = priv->bt_ci_compliance;
3251                 bt_load = priv->bt_traffic_load;
3252                 bt_status = priv->bt_status;
3253
3254                 __iwl_down(priv);
3255
3256                 priv->bt_sco_active = bt_sco;
3257                 priv->bt_full_concurrent = bt_full_concurrent;
3258                 priv->bt_ci_compliance = bt_ci_compliance;
3259                 priv->bt_traffic_load = bt_load;
3260                 priv->bt_status = bt_status;
3261
3262                 mutex_unlock(&priv->mutex);
3263                 iwl_cancel_deferred_work(priv);
3264                 ieee80211_restart_hw(priv->hw);
3265         } else {
3266                 iwl_down(priv);
3267
3268                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3269                         return;
3270
3271                 mutex_lock(&priv->mutex);
3272                 __iwl_up(priv);
3273                 mutex_unlock(&priv->mutex);
3274         }
3275 }
3276
3277 static void iwl_bg_rx_replenish(struct work_struct *data)
3278 {
3279         struct iwl_priv *priv =
3280             container_of(data, struct iwl_priv, rx_replenish);
3281
3282         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3283                 return;
3284
3285         mutex_lock(&priv->mutex);
3286         iwlagn_rx_replenish(priv);
3287         mutex_unlock(&priv->mutex);
3288 }
3289
3290 #define IWL_DELAY_NEXT_SCAN (HZ*2)
3291
3292 void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
3293 {
3294         struct iwl_rxon_context *ctx;
3295         struct ieee80211_conf *conf = NULL;
3296         int ret = 0;
3297
3298         if (!vif || !priv->is_open)
3299                 return;
3300
3301         ctx = iwl_rxon_ctx_from_vif(vif);
3302
3303         if (vif->type == NL80211_IFTYPE_AP) {
3304                 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
3305                 return;
3306         }
3307
3308         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3309                 return;
3310
3311         iwl_scan_cancel_timeout(priv, 200);
3312
3313         conf = ieee80211_get_hw_conf(priv->hw);
3314
3315         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3316         iwlcore_commit_rxon(priv, ctx);
3317
3318         ret = iwl_send_rxon_timing(priv, ctx);
3319         if (ret)
3320                 IWL_WARN(priv, "RXON timing - "
3321                             "Attempting to continue.\n");
3322
3323         ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3324
3325         iwl_set_rxon_ht(priv, &priv->current_ht_config);
3326
3327         if (priv->cfg->ops->hcmd->set_rxon_chain)
3328                 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3329
3330         ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
3331
3332         IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
3333                         vif->bss_conf.aid, vif->bss_conf.beacon_int);
3334
3335         if (vif->bss_conf.use_short_preamble)
3336                 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3337         else
3338                 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3339
3340         if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3341                 if (vif->bss_conf.use_short_slot)
3342                         ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
3343                 else
3344                         ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3345         }
3346
3347         iwlcore_commit_rxon(priv, ctx);
3348
3349         IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
3350                         vif->bss_conf.aid, ctx->active.bssid_addr);
3351
3352         switch (vif->type) {
3353         case NL80211_IFTYPE_STATION:
3354                 break;
3355         case NL80211_IFTYPE_ADHOC:
3356                 iwl_send_beacon_cmd(priv);
3357                 break;
3358         default:
3359                 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3360                           __func__, vif->type);
3361                 break;
3362         }
3363
3364         /* the chain noise calibration will enabled PM upon completion
3365          * If chain noise has already been run, then we need to enable
3366          * power management here */
3367         if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
3368                 iwl_power_update_mode(priv, false);
3369
3370         /* Enable Rx differential gain and sensitivity calibrations */
3371         iwl_chain_noise_reset(priv);
3372         priv->start_calib = 1;
3373
3374 }
3375
3376 /*****************************************************************************
3377  *
3378  * mac80211 entry point functions
3379  *
3380  *****************************************************************************/
3381
3382 #define UCODE_READY_TIMEOUT     (4 * HZ)
3383
3384 /*
3385  * Not a mac80211 entry point function, but it fits in with all the
3386  * other mac80211 functions grouped here.
3387  */
3388 static int iwl_mac_setup_register(struct iwl_priv *priv,
3389                                   struct iwlagn_ucode_capabilities *capa)
3390 {
3391         int ret;
3392         struct ieee80211_hw *hw = priv->hw;
3393         struct iwl_rxon_context *ctx;
3394
3395         hw->rate_control_algorithm = "iwl-agn-rs";
3396
3397         /* Tell mac80211 our characteristics */
3398         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3399                     IEEE80211_HW_AMPDU_AGGREGATION |
3400                     IEEE80211_HW_NEED_DTIM_PERIOD |
3401                     IEEE80211_HW_SPECTRUM_MGMT;
3402
3403         if (!priv->cfg->broken_powersave)
3404                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3405                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3406
3407         if (priv->cfg->sku & IWL_SKU_N)
3408                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3409                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3410
3411         hw->sta_data_size = sizeof(struct iwl_station_priv);
3412         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3413
3414         for_each_context(priv, ctx) {
3415                 hw->wiphy->interface_modes |= ctx->interface_modes;
3416                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3417         }
3418
3419         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3420                             WIPHY_FLAG_DISABLE_BEACON_HINTS;
3421
3422         /*
3423          * For now, disable PS by default because it affects
3424          * RX performance significantly.
3425          */
3426         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3427
3428         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3429         /* we create the 802.11 header and a zero-length SSID element */
3430         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3431
3432         /* Default value; 4 EDCA QOS priorities */
3433         hw->queues = 4;
3434
3435         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3436
3437         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3438                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3439                         &priv->bands[IEEE80211_BAND_2GHZ];
3440         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3441                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3442                         &priv->bands[IEEE80211_BAND_5GHZ];
3443
3444         ret = ieee80211_register_hw(priv->hw);
3445         if (ret) {
3446                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3447                 return ret;
3448         }
3449         priv->mac80211_registered = 1;
3450
3451         return 0;
3452 }
3453
3454
3455 static int iwl_mac_start(struct ieee80211_hw *hw)
3456 {
3457         struct iwl_priv *priv = hw->priv;
3458         int ret;
3459
3460         IWL_DEBUG_MAC80211(priv, "enter\n");
3461
3462         /* we should be verifying the device is ready to be opened */
3463         mutex_lock(&priv->mutex);
3464         ret = __iwl_up(priv);
3465         mutex_unlock(&priv->mutex);
3466
3467         if (ret)
3468                 return ret;
3469
3470         if (iwl_is_rfkill(priv))
3471                 goto out;
3472
3473         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3474
3475         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3476          * mac80211 will not be run successfully. */
3477         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3478                         test_bit(STATUS_READY, &priv->status),
3479                         UCODE_READY_TIMEOUT);
3480         if (!ret) {
3481                 if (!test_bit(STATUS_READY, &priv->status)) {
3482                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3483                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3484                         return -ETIMEDOUT;
3485                 }
3486         }
3487
3488         iwl_led_start(priv);
3489
3490 out:
3491         priv->is_open = 1;
3492         IWL_DEBUG_MAC80211(priv, "leave\n");
3493         return 0;
3494 }
3495
3496 static void iwl_mac_stop(struct ieee80211_hw *hw)
3497 {
3498         struct iwl_priv *priv = hw->priv;
3499
3500         IWL_DEBUG_MAC80211(priv, "enter\n");
3501
3502         if (!priv->is_open)
3503                 return;
3504
3505         priv->is_open = 0;
3506
3507         iwl_down(priv);
3508
3509         flush_workqueue(priv->workqueue);
3510
3511         /* enable interrupts again in order to receive rfkill changes */
3512         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3513         iwl_enable_interrupts(priv);
3514
3515         IWL_DEBUG_MAC80211(priv, "leave\n");
3516 }
3517
3518 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3519 {
3520         struct iwl_priv *priv = hw->priv;
3521
3522         IWL_DEBUG_MACDUMP(priv, "enter\n");
3523
3524         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3525                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3526
3527         if (iwlagn_tx_skb(priv, skb))
3528                 dev_kfree_skb_any(skb);
3529
3530         IWL_DEBUG_MACDUMP(priv, "leave\n");
3531         return NETDEV_TX_OK;
3532 }
3533
3534 void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
3535 {
3536         struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
3537         int ret = 0;
3538
3539         lockdep_assert_held(&priv->mutex);
3540
3541         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3542                 return;
3543
3544         /* The following should be done only at AP bring up */
3545         if (!iwl_is_associated_ctx(ctx)) {
3546
3547                 /* RXON - unassoc (to set timing command) */
3548                 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3549                 iwlcore_commit_rxon(priv, ctx);
3550
3551                 /* RXON Timing */
3552                 ret = iwl_send_rxon_timing(priv, ctx);
3553                 if (ret)
3554                         IWL_WARN(priv, "RXON timing failed - "
3555                                         "Attempting to continue.\n");
3556
3557                 /* AP has all antennas */
3558                 priv->chain_noise_data.active_chains =
3559                         priv->hw_params.valid_rx_ant;
3560                 iwl_set_rxon_ht(priv, &priv->current_ht_config);
3561                 if (priv->cfg->ops->hcmd->set_rxon_chain)
3562                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3563
3564                 ctx->staging.assoc_id = 0;
3565
3566                 if (vif->bss_conf.use_short_preamble)
3567                         ctx->staging.flags |=
3568                                 RXON_FLG_SHORT_PREAMBLE_MSK;
3569                 else
3570                         ctx->staging.flags &=
3571                                 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3572
3573                 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3574                         if (vif->bss_conf.use_short_slot)
3575                                 ctx->staging.flags |=
3576                                         RXON_FLG_SHORT_SLOT_MSK;
3577                         else
3578                                 ctx->staging.flags &=
3579                                         ~RXON_FLG_SHORT_SLOT_MSK;
3580                 }
3581                 /* need to send beacon cmd before committing assoc RXON! */
3582                 iwl_send_beacon_cmd(priv);
3583                 /* restore RXON assoc */
3584                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3585                 iwlcore_commit_rxon(priv, ctx);
3586         }
3587         iwl_send_beacon_cmd(priv);
3588
3589         /* FIXME - we need to add code here to detect a totally new
3590          * configuration, reset the AP, unassoc, rxon timing, assoc,
3591          * clear sta table, add BCAST sta... */
3592 }
3593
3594 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
3595                                     struct ieee80211_vif *vif,
3596                                     struct ieee80211_key_conf *keyconf,
3597                                     struct ieee80211_sta *sta,
3598                                     u32 iv32, u16 *phase1key)
3599 {
3600
3601         struct iwl_priv *priv = hw->priv;
3602         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3603
3604         IWL_DEBUG_MAC80211(priv, "enter\n");
3605
3606         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3607                             iv32, phase1key);
3608
3609         IWL_DEBUG_MAC80211(priv, "leave\n");
3610 }
3611
3612 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3613                            struct ieee80211_vif *vif,
3614                            struct ieee80211_sta *sta,
3615                            struct ieee80211_key_conf *key)
3616 {
3617         struct iwl_priv *priv = hw->priv;
3618         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3619         struct iwl_rxon_context *ctx = vif_priv->ctx;
3620         int ret;
3621         u8 sta_id;
3622         bool is_default_wep_key = false;
3623
3624         IWL_DEBUG_MAC80211(priv, "enter\n");
3625
3626         if (priv->cfg->mod_params->sw_crypto) {
3627                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3628                 return -EOPNOTSUPP;
3629         }
3630
3631         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3632         if (sta_id == IWL_INVALID_STATION)
3633                 return -EINVAL;
3634
3635         mutex_lock(&priv->mutex);
3636         iwl_scan_cancel_timeout(priv, 100);
3637
3638         /*
3639          * If we are getting WEP group key and we didn't receive any key mapping
3640          * so far, we are in legacy wep mode (group key only), otherwise we are
3641          * in 1X mode.
3642          * In legacy wep mode, we use another host command to the uCode.
3643          */
3644         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3645              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3646             !sta) {
3647                 if (cmd == SET_KEY)
3648                         is_default_wep_key = !ctx->key_mapping_keys;
3649                 else
3650                         is_default_wep_key =
3651                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3652         }
3653
3654         switch (cmd) {
3655         case SET_KEY:
3656                 if (is_default_wep_key)
3657                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3658                 else
3659                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3660                                                   key, sta_id);
3661
3662                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3663                 break;
3664         case DISABLE_KEY:
3665                 if (is_default_wep_key)
3666                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3667                 else
3668                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3669
3670                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3671                 break;
3672         default:
3673                 ret = -EINVAL;
3674         }
3675
3676         mutex_unlock(&priv->mutex);
3677         IWL_DEBUG_MAC80211(priv, "leave\n");
3678
3679         return ret;
3680 }
3681
3682 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
3683                                 struct ieee80211_vif *vif,
3684                                 enum ieee80211_ampdu_mlme_action action,
3685                                 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3686 {
3687         struct iwl_priv *priv = hw->priv;
3688         int ret = -EINVAL;
3689
3690         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3691                      sta->addr, tid);
3692
3693         if (!(priv->cfg->sku & IWL_SKU_N))
3694                 return -EACCES;
3695
3696         mutex_lock(&priv->mutex);
3697
3698         switch (action) {
3699         case IEEE80211_AMPDU_RX_START:
3700                 IWL_DEBUG_HT(priv, "start Rx\n");
3701                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3702                 break;
3703         case IEEE80211_AMPDU_RX_STOP:
3704                 IWL_DEBUG_HT(priv, "stop Rx\n");
3705                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3706                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3707                         ret = 0;
3708                 break;
3709         case IEEE80211_AMPDU_TX_START:
3710                 IWL_DEBUG_HT(priv, "start Tx\n");
3711                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3712                 if (ret == 0) {
3713                         priv->_agn.agg_tids_count++;
3714                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3715                                      priv->_agn.agg_tids_count);
3716                 }
3717                 break;
3718         case IEEE80211_AMPDU_TX_STOP:
3719                 IWL_DEBUG_HT(priv, "stop Tx\n");
3720                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3721                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3722                         priv->_agn.agg_tids_count--;
3723                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3724                                      priv->_agn.agg_tids_count);
3725                 }
3726                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3727                         ret = 0;
3728                 if (priv->cfg->use_rts_for_aggregation) {
3729                         struct iwl_station_priv *sta_priv =
3730                                 (void *) sta->drv_priv;
3731                         /*
3732                          * switch off RTS/CTS if it was previously enabled
3733                          */
3734
3735                         sta_priv->lq_sta.lq.general_params.flags &=
3736                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3737                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3738                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3739                 }
3740                 break;
3741         case IEEE80211_AMPDU_TX_OPERATIONAL:
3742                 if (priv->cfg->use_rts_for_aggregation) {
3743                         struct iwl_station_priv *sta_priv =
3744                                 (void *) sta->drv_priv;
3745
3746                         /*
3747                          * switch to RTS/CTS if it is the prefer protection
3748                          * method for HT traffic
3749                          */
3750
3751                         sta_priv->lq_sta.lq.general_params.flags |=
3752                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3753                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3754                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3755                 }
3756                 ret = 0;
3757                 break;
3758         }
3759         mutex_unlock(&priv->mutex);
3760
3761         return ret;
3762 }
3763
3764 static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3765                                struct ieee80211_vif *vif,
3766                                enum sta_notify_cmd cmd,
3767                                struct ieee80211_sta *sta)
3768 {
3769         struct iwl_priv *priv = hw->priv;
3770         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3771         int sta_id;
3772
3773         switch (cmd) {
3774         case STA_NOTIFY_SLEEP:
3775                 WARN_ON(!sta_priv->client);
3776                 sta_priv->asleep = true;
3777                 if (atomic_read(&sta_priv->pending_frames) > 0)
3778                         ieee80211_sta_block_awake(hw, sta, true);
3779                 break;
3780         case STA_NOTIFY_AWAKE:
3781                 WARN_ON(!sta_priv->client);
3782                 if (!sta_priv->asleep)
3783                         break;
3784                 sta_priv->asleep = false;
3785                 sta_id = iwl_sta_id(sta);
3786                 if (sta_id != IWL_INVALID_STATION)
3787                         iwl_sta_modify_ps_wake(priv, sta_id);
3788                 break;
3789         default:
3790                 break;
3791         }
3792 }
3793
3794 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3795                               struct ieee80211_vif *vif,
3796                               struct ieee80211_sta *sta)
3797 {
3798         struct iwl_priv *priv = hw->priv;
3799         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3800         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3801         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3802         int ret;
3803         u8 sta_id;
3804
3805         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3806                         sta->addr);
3807         mutex_lock(&priv->mutex);
3808         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3809                         sta->addr);
3810         sta_priv->common.sta_id = IWL_INVALID_STATION;
3811
3812         atomic_set(&sta_priv->pending_frames, 0);
3813         if (vif->type == NL80211_IFTYPE_AP)
3814                 sta_priv->client = true;
3815
3816         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3817                                      is_ap, sta, &sta_id);
3818         if (ret) {
3819                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3820                         sta->addr, ret);
3821                 /* Should we return success if return code is EEXIST ? */
3822                 mutex_unlock(&priv->mutex);
3823                 return ret;
3824         }
3825
3826         sta_priv->common.sta_id = sta_id;
3827
3828         /* Initialize rate scaling */
3829         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3830                        sta->addr);
3831         iwl_rs_rate_init(priv, sta, sta_id);
3832         mutex_unlock(&priv->mutex);
3833
3834         return 0;
3835 }
3836
3837 static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3838                                    struct ieee80211_channel_switch *ch_switch)
3839 {
3840         struct iwl_priv *priv = hw->priv;
3841         const struct iwl_channel_info *ch_info;
3842         struct ieee80211_conf *conf = &hw->conf;
3843         struct ieee80211_channel *channel = ch_switch->channel;
3844         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3845         /*
3846          * MULTI-FIXME
3847          * When we add support for multiple interfaces, we need to
3848          * revisit this. The channel switch command in the device
3849          * only affects the BSS context, but what does that really
3850          * mean? And what if we get a CSA on the second interface?
3851          * This needs a lot of work.
3852          */
3853         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3854         u16 ch;
3855         unsigned long flags = 0;
3856
3857         IWL_DEBUG_MAC80211(priv, "enter\n");
3858
3859         if (iwl_is_rfkill(priv))
3860                 goto out_exit;
3861
3862         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3863             test_bit(STATUS_SCANNING, &priv->status))
3864                 goto out_exit;
3865
3866         if (!iwl_is_associated_ctx(ctx))
3867                 goto out_exit;
3868
3869         /* channel switch in progress */
3870         if (priv->switch_rxon.switch_in_progress == true)
3871                 goto out_exit;
3872
3873         mutex_lock(&priv->mutex);
3874         if (priv->cfg->ops->lib->set_channel_switch) {
3875
3876                 ch = channel->hw_value;
3877                 if (le16_to_cpu(ctx->active.channel) != ch) {
3878                         ch_info = iwl_get_channel_info(priv,
3879                                                        channel->band,
3880                                                        ch);
3881                         if (!is_channel_valid(ch_info)) {
3882                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3883                                 goto out;
3884                         }
3885                         spin_lock_irqsave(&priv->lock, flags);
3886
3887                         priv->current_ht_config.smps = conf->smps_mode;
3888
3889                         /* Configure HT40 channels */
3890                         ctx->ht.enabled = conf_is_ht(conf);
3891                         if (ctx->ht.enabled) {
3892                                 if (conf_is_ht40_minus(conf)) {
3893                                         ctx->ht.extension_chan_offset =
3894                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3895                                         ctx->ht.is_40mhz = true;
3896                                 } else if (conf_is_ht40_plus(conf)) {
3897                                         ctx->ht.extension_chan_offset =
3898                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3899                                         ctx->ht.is_40mhz = true;
3900                                 } else {
3901                                         ctx->ht.extension_chan_offset =
3902                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3903                                         ctx->ht.is_40mhz = false;
3904                                 }
3905                         } else
3906                                 ctx->ht.is_40mhz = false;
3907
3908                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3909                                 ctx->staging.flags = 0;
3910
3911                         iwl_set_rxon_channel(priv, channel, ctx);
3912                         iwl_set_rxon_ht(priv, ht_conf);
3913                         iwl_set_flags_for_band(priv, ctx, channel->band,
3914                                                ctx->vif);
3915                         spin_unlock_irqrestore(&priv->lock, flags);
3916
3917                         iwl_set_rate(priv);
3918                         /*
3919                          * at this point, staging_rxon has the
3920                          * configuration for channel switch
3921                          */
3922                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3923                                                                     ch_switch))
3924                                 priv->switch_rxon.switch_in_progress = false;
3925                 }
3926         }
3927 out:
3928         mutex_unlock(&priv->mutex);
3929 out_exit:
3930         if (!priv->switch_rxon.switch_in_progress)
3931                 ieee80211_chswitch_done(ctx->vif, false);
3932         IWL_DEBUG_MAC80211(priv, "leave\n");
3933 }
3934
3935 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3936                                     unsigned int changed_flags,
3937                                     unsigned int *total_flags,
3938                                     u64 multicast)
3939 {
3940         struct iwl_priv *priv = hw->priv;
3941         __le32 filter_or = 0, filter_nand = 0;
3942         struct iwl_rxon_context *ctx;
3943
3944 #define CHK(test, flag) do { \
3945         if (*total_flags & (test))              \
3946                 filter_or |= (flag);            \
3947         else                                    \
3948                 filter_nand |= (flag);          \
3949         } while (0)
3950
3951         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3952                         changed_flags, *total_flags);
3953
3954         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3955         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3956         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3957
3958 #undef CHK
3959
3960         mutex_lock(&priv->mutex);
3961
3962         for_each_context(priv, ctx) {
3963                 ctx->staging.filter_flags &= ~filter_nand;
3964                 ctx->staging.filter_flags |= filter_or;
3965                 iwlcore_commit_rxon(priv, ctx);
3966         }
3967
3968         mutex_unlock(&priv->mutex);
3969
3970         /*
3971          * Receiving all multicast frames is always enabled by the
3972          * default flags setup in iwl_connection_init_rx_config()
3973          * since we currently do not support programming multicast
3974          * filters into the device.
3975          */
3976         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3977                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3978 }
3979
3980 static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3981 {
3982         struct iwl_priv *priv = hw->priv;
3983
3984         mutex_lock(&priv->mutex);
3985         IWL_DEBUG_MAC80211(priv, "enter\n");
3986
3987         /* do not support "flush" */
3988         if (!priv->cfg->ops->lib->txfifo_flush)
3989                 goto done;
3990
3991         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3992                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3993                 goto done;
3994         }
3995         if (iwl_is_rfkill(priv)) {
3996                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3997                 goto done;
3998         }
3999
4000         /*
4001          * mac80211 will not push any more frames for transmit
4002          * until the flush is completed
4003          */
4004         if (drop) {
4005                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
4006                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
4007                         IWL_ERR(priv, "flush request fail\n");
4008                         goto done;
4009                 }
4010         }
4011         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
4012         iwlagn_wait_tx_queue_empty(priv);
4013 done:
4014         mutex_unlock(&priv->mutex);
4015         IWL_DEBUG_MAC80211(priv, "leave\n");
4016 }
4017
4018 /*****************************************************************************
4019  *
4020  * driver setup and teardown
4021  *
4022  *****************************************************************************/
4023
4024 static void iwl_setup_deferred_work(struct iwl_priv *priv)
4025 {
4026         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
4027
4028         init_waitqueue_head(&priv->wait_command_queue);
4029
4030         INIT_WORK(&priv->restart, iwl_bg_restart);
4031         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
4032         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
4033         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4034         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
4035         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
4036         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4037         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
4038         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
4039
4040         iwl_setup_scan_deferred_work(priv);
4041
4042         if (priv->cfg->ops->lib->setup_deferred_work)
4043                 priv->cfg->ops->lib->setup_deferred_work(priv);
4044
4045         init_timer(&priv->statistics_periodic);
4046         priv->statistics_periodic.data = (unsigned long)priv;
4047         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
4048
4049         init_timer(&priv->ucode_trace);
4050         priv->ucode_trace.data = (unsigned long)priv;
4051         priv->ucode_trace.function = iwl_bg_ucode_trace;
4052
4053         if (priv->cfg->ops->lib->recover_from_tx_stall) {
4054                 init_timer(&priv->monitor_recover);
4055                 priv->monitor_recover.data = (unsigned long)priv;
4056                 priv->monitor_recover.function =
4057                         priv->cfg->ops->lib->recover_from_tx_stall;
4058         }
4059
4060         if (!priv->cfg->use_isr_legacy)
4061                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4062                         iwl_irq_tasklet, (unsigned long)priv);
4063         else
4064                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4065                         iwl_irq_tasklet_legacy, (unsigned long)priv);
4066 }
4067
4068 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
4069 {
4070         if (priv->cfg->ops->lib->cancel_deferred_work)
4071                 priv->cfg->ops->lib->cancel_deferred_work(priv);
4072
4073         cancel_delayed_work_sync(&priv->init_alive_start);
4074         cancel_delayed_work(&priv->alive_start);
4075         cancel_work_sync(&priv->run_time_calib_work);
4076         cancel_work_sync(&priv->beacon_update);
4077
4078         iwl_cancel_scan_deferred_work(priv);
4079
4080         cancel_work_sync(&priv->bt_full_concurrency);
4081         cancel_work_sync(&priv->bt_runtime_config);
4082
4083         del_timer_sync(&priv->statistics_periodic);
4084         del_timer_sync(&priv->ucode_trace);
4085 }
4086
4087 static void iwl_init_hw_rates(struct iwl_priv *priv,
4088                               struct ieee80211_rate *rates)
4089 {
4090         int i;
4091
4092         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4093                 rates[i].bitrate = iwl_rates[i].ieee * 5;
4094                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4095                 rates[i].hw_value_short = i;
4096                 rates[i].flags = 0;
4097                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4098                         /*
4099                          * If CCK != 1M then set short preamble rate flag.
4100                          */
4101                         rates[i].flags |=
4102                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4103                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
4104                 }
4105         }
4106 }
4107
4108 static int iwl_init_drv(struct iwl_priv *priv)
4109 {
4110         int ret;
4111
4112         priv->ibss_beacon = NULL;
4113
4114         spin_lock_init(&priv->sta_lock);
4115         spin_lock_init(&priv->hcmd_lock);
4116
4117         INIT_LIST_HEAD(&priv->free_frames);
4118
4119         mutex_init(&priv->mutex);
4120         mutex_init(&priv->sync_cmd_mutex);
4121
4122         priv->ieee_channels = NULL;
4123         priv->ieee_rates = NULL;
4124         priv->band = IEEE80211_BAND_2GHZ;
4125
4126         priv->iw_mode = NL80211_IFTYPE_STATION;
4127         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
4128         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
4129         priv->_agn.agg_tids_count = 0;
4130
4131         /* initialize force reset */
4132         priv->force_reset[IWL_RF_RESET].reset_duration =
4133                 IWL_DELAY_NEXT_FORCE_RF_RESET;
4134         priv->force_reset[IWL_FW_RESET].reset_duration =
4135                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
4136
4137         /* Choose which receivers/antennas to use */
4138         if (priv->cfg->ops->hcmd->set_rxon_chain)
4139                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4140                                         &priv->contexts[IWL_RXON_CTX_BSS]);
4141
4142         iwl_init_scan_params(priv);
4143
4144         /* init bt coex */
4145         if (priv->cfg->advanced_bt_coexist) {
4146                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4147                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4148                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
4149                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4150                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4151                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4152                 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4153         }
4154
4155         /* Set the tx_power_user_lmt to the lowest power level
4156          * this value will get overwritten by channel max power avg
4157          * from eeprom */
4158         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
4159
4160         ret = iwl_init_channel_map(priv);
4161         if (ret) {
4162                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4163                 goto err;
4164         }
4165
4166         ret = iwlcore_init_geos(priv);
4167         if (ret) {
4168                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4169                 goto err_free_channel_map;
4170         }
4171         iwl_init_hw_rates(priv, priv->ieee_rates);
4172
4173         return 0;
4174
4175 err_free_channel_map:
4176         iwl_free_channel_map(priv);
4177 err:
4178         return ret;
4179 }
4180
4181 static void iwl_uninit_drv(struct iwl_priv *priv)
4182 {
4183         iwl_calib_free_results(priv);
4184         iwlcore_free_geos(priv);
4185         iwl_free_channel_map(priv);
4186         kfree(priv->scan_cmd);
4187 }
4188
4189 static struct ieee80211_ops iwl_hw_ops = {
4190         .tx = iwl_mac_tx,
4191         .start = iwl_mac_start,
4192         .stop = iwl_mac_stop,
4193         .add_interface = iwl_mac_add_interface,
4194         .remove_interface = iwl_mac_remove_interface,
4195         .config = iwl_mac_config,
4196         .configure_filter = iwlagn_configure_filter,
4197         .set_key = iwl_mac_set_key,
4198         .update_tkip_key = iwl_mac_update_tkip_key,
4199         .conf_tx = iwl_mac_conf_tx,
4200         .reset_tsf = iwl_mac_reset_tsf,
4201         .bss_info_changed = iwl_bss_info_changed,
4202         .ampdu_action = iwl_mac_ampdu_action,
4203         .hw_scan = iwl_mac_hw_scan,
4204         .sta_notify = iwl_mac_sta_notify,
4205         .sta_add = iwlagn_mac_sta_add,
4206         .sta_remove = iwl_mac_sta_remove,
4207         .channel_switch = iwl_mac_channel_switch,
4208         .flush = iwl_mac_flush,
4209         .tx_last_beacon = iwl_mac_tx_last_beacon,
4210 };
4211
4212 static void iwl_hw_detect(struct iwl_priv *priv)
4213 {
4214         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4215         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4216         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4217         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4218 }
4219
4220 static int iwl_set_hw_params(struct iwl_priv *priv)
4221 {
4222         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4223         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4224         if (priv->cfg->mod_params->amsdu_size_8K)
4225                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4226         else
4227                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4228
4229         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4230
4231         if (priv->cfg->mod_params->disable_11n)
4232                 priv->cfg->sku &= ~IWL_SKU_N;
4233
4234         /* Device-specific setup */
4235         return priv->cfg->ops->lib->set_hw_params(priv);
4236 }
4237
4238 static const u8 iwlagn_bss_ac_to_fifo[] = {
4239         IWL_TX_FIFO_VO,
4240         IWL_TX_FIFO_VI,
4241         IWL_TX_FIFO_BE,
4242         IWL_TX_FIFO_BK,
4243 };
4244
4245 static const u8 iwlagn_bss_ac_to_queue[] = {
4246         0, 1, 2, 3,
4247 };
4248
4249 static const u8 iwlagn_pan_ac_to_fifo[] = {
4250         IWL_TX_FIFO_VO_IPAN,
4251         IWL_TX_FIFO_VI_IPAN,
4252         IWL_TX_FIFO_BE_IPAN,
4253         IWL_TX_FIFO_BK_IPAN,
4254 };
4255
4256 static const u8 iwlagn_pan_ac_to_queue[] = {
4257         7, 6, 5, 4,
4258 };
4259
4260 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4261 {
4262         int err = 0, i;
4263         struct iwl_priv *priv;
4264         struct ieee80211_hw *hw;
4265         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4266         unsigned long flags;
4267         u16 pci_cmd, num_mac;
4268
4269         /************************
4270          * 1. Allocating HW data
4271          ************************/
4272
4273         /* Disabling hardware scan means that mac80211 will perform scans
4274          * "the hard way", rather than using device's scan. */
4275         if (cfg->mod_params->disable_hw_scan) {
4276                 if (iwl_debug_level & IWL_DL_INFO)
4277                         dev_printk(KERN_DEBUG, &(pdev->dev),
4278                                    "Disabling hw_scan\n");
4279                 iwl_hw_ops.hw_scan = NULL;
4280         }
4281
4282         hw = iwl_alloc_all(cfg, &iwl_hw_ops);
4283         if (!hw) {
4284                 err = -ENOMEM;
4285                 goto out;
4286         }
4287         priv = hw->priv;
4288         /* At this point both hw and priv are allocated. */
4289
4290         /*
4291          * The default context is always valid,
4292          * more may be discovered when firmware
4293          * is loaded.
4294          */
4295         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4296
4297         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4298                 priv->contexts[i].ctxid = i;
4299
4300         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4301         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
4302         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4303         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4304         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4305         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4306         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4307         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4308         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4309         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4310         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4311                 BIT(NL80211_IFTYPE_ADHOC);
4312         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4313                 BIT(NL80211_IFTYPE_STATION);
4314         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4315         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4316         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4317
4318         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4319         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4320         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4321         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4322         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4323         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4324         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4325         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4326         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4327         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4328         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4329         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4330                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4331         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4332         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4333         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4334
4335         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4336
4337         SET_IEEE80211_DEV(hw, &pdev->dev);
4338
4339         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4340         priv->cfg = cfg;
4341         priv->pci_dev = pdev;
4342         priv->inta_mask = CSR_INI_SET_MASK;
4343
4344         /* is antenna coupling more than 35dB ? */
4345         priv->bt_ant_couple_ok =
4346                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4347                 true : false;
4348
4349         /* enable/disable bt channel announcement */
4350         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4351
4352         if (iwl_alloc_traffic_mem(priv))
4353                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4354
4355         /**************************
4356          * 2. Initializing PCI bus
4357          **************************/
4358         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4359                                 PCIE_LINK_STATE_CLKPM);
4360
4361         if (pci_enable_device(pdev)) {
4362                 err = -ENODEV;
4363                 goto out_ieee80211_free_hw;
4364         }
4365
4366         pci_set_master(pdev);
4367
4368         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4369         if (!err)
4370                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4371         if (err) {
4372                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4373                 if (!err)
4374                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4375                 /* both attempts failed: */
4376                 if (err) {
4377                         IWL_WARN(priv, "No suitable DMA available.\n");
4378                         goto out_pci_disable_device;
4379                 }
4380         }
4381
4382         err = pci_request_regions(pdev, DRV_NAME);
4383         if (err)
4384                 goto out_pci_disable_device;
4385
4386         pci_set_drvdata(pdev, priv);
4387
4388
4389         /***********************
4390          * 3. Read REV register
4391          ***********************/
4392         priv->hw_base = pci_iomap(pdev, 0, 0);
4393         if (!priv->hw_base) {
4394                 err = -ENODEV;
4395                 goto out_pci_release_regions;
4396         }
4397
4398         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4399                 (unsigned long long) pci_resource_len(pdev, 0));
4400         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4401
4402         /* these spin locks will be used in apm_ops.init and EEPROM access
4403          * we should init now
4404          */
4405         spin_lock_init(&priv->reg_lock);
4406         spin_lock_init(&priv->lock);
4407
4408         /*
4409          * stop and reset the on-board processor just in case it is in a
4410          * strange state ... like being left stranded by a primary kernel
4411          * and this is now the kdump kernel trying to start up
4412          */
4413         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4414
4415         iwl_hw_detect(priv);
4416         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4417                 priv->cfg->name, priv->hw_rev);
4418
4419         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4420          * PCI Tx retries from interfering with C3 CPU state */
4421         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4422
4423         iwl_prepare_card_hw(priv);
4424         if (!priv->hw_ready) {
4425                 IWL_WARN(priv, "Failed, HW not ready\n");
4426                 goto out_iounmap;
4427         }
4428
4429         /*****************
4430          * 4. Read EEPROM
4431          *****************/
4432         /* Read the EEPROM */
4433         err = iwl_eeprom_init(priv);
4434         if (err) {
4435                 IWL_ERR(priv, "Unable to init EEPROM\n");
4436                 goto out_iounmap;
4437         }
4438         err = iwl_eeprom_check_version(priv);
4439         if (err)
4440                 goto out_free_eeprom;
4441
4442         /* extract MAC Address */
4443         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4444         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4445         priv->hw->wiphy->addresses = priv->addresses;
4446         priv->hw->wiphy->n_addresses = 1;
4447         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4448         if (num_mac > 1) {
4449                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4450                        ETH_ALEN);
4451                 priv->addresses[1].addr[5]++;
4452                 priv->hw->wiphy->n_addresses++;
4453         }
4454
4455         /************************
4456          * 5. Setup HW constants
4457          ************************/
4458         if (iwl_set_hw_params(priv)) {
4459                 IWL_ERR(priv, "failed to set hw parameters\n");
4460                 goto out_free_eeprom;
4461         }
4462
4463         /*******************
4464          * 6. Setup priv
4465          *******************/
4466
4467         err = iwl_init_drv(priv);
4468         if (err)
4469                 goto out_free_eeprom;
4470         /* At this point both hw and priv are initialized. */
4471
4472         /********************
4473          * 7. Setup services
4474          ********************/
4475         spin_lock_irqsave(&priv->lock, flags);
4476         iwl_disable_interrupts(priv);
4477         spin_unlock_irqrestore(&priv->lock, flags);
4478
4479         pci_enable_msi(priv->pci_dev);
4480
4481         iwl_alloc_isr_ict(priv);
4482         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4483                           IRQF_SHARED, DRV_NAME, priv);
4484         if (err) {
4485                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4486                 goto out_disable_msi;
4487         }
4488
4489         iwl_setup_deferred_work(priv);
4490         iwl_setup_rx_handlers(priv);
4491
4492         /*********************************************
4493          * 8. Enable interrupts and read RFKILL state
4494          *********************************************/
4495
4496         /* enable interrupts if needed: hw bug w/a */
4497         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4498         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4499                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4500                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4501         }
4502
4503         iwl_enable_interrupts(priv);
4504
4505         /* If platform's RF_KILL switch is NOT set to KILL */
4506         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4507                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4508         else
4509                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4510
4511         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4512                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4513
4514         iwl_power_initialize(priv);
4515         iwl_tt_initialize(priv);
4516
4517         init_completion(&priv->_agn.firmware_loading_complete);
4518
4519         err = iwl_request_firmware(priv, true);
4520         if (err)
4521                 goto out_destroy_workqueue;
4522
4523         return 0;
4524
4525  out_destroy_workqueue:
4526         destroy_workqueue(priv->workqueue);
4527         priv->workqueue = NULL;
4528         free_irq(priv->pci_dev->irq, priv);
4529         iwl_free_isr_ict(priv);
4530  out_disable_msi:
4531         pci_disable_msi(priv->pci_dev);
4532         iwl_uninit_drv(priv);
4533  out_free_eeprom:
4534         iwl_eeprom_free(priv);
4535  out_iounmap:
4536         pci_iounmap(pdev, priv->hw_base);
4537  out_pci_release_regions:
4538         pci_set_drvdata(pdev, NULL);
4539         pci_release_regions(pdev);
4540  out_pci_disable_device:
4541         pci_disable_device(pdev);
4542  out_ieee80211_free_hw:
4543         iwl_free_traffic_mem(priv);
4544         ieee80211_free_hw(priv->hw);
4545  out:
4546         return err;
4547 }
4548
4549 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4550 {
4551         struct iwl_priv *priv = pci_get_drvdata(pdev);
4552         unsigned long flags;
4553
4554         if (!priv)
4555                 return;
4556
4557         wait_for_completion(&priv->_agn.firmware_loading_complete);
4558
4559         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4560
4561         iwl_dbgfs_unregister(priv);
4562         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4563
4564         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4565          * to be called and iwl_down since we are removing the device
4566          * we need to set STATUS_EXIT_PENDING bit.
4567          */
4568         set_bit(STATUS_EXIT_PENDING, &priv->status);
4569         if (priv->mac80211_registered) {
4570                 ieee80211_unregister_hw(priv->hw);
4571                 priv->mac80211_registered = 0;
4572         } else {
4573                 iwl_down(priv);
4574         }
4575
4576         /*
4577          * Make sure device is reset to low power before unloading driver.
4578          * This may be redundant with iwl_down(), but there are paths to
4579          * run iwl_down() without calling apm_ops.stop(), and there are
4580          * paths to avoid running iwl_down() at all before leaving driver.
4581          * This (inexpensive) call *makes sure* device is reset.
4582          */
4583         priv->cfg->ops->lib->apm_ops.stop(priv);
4584
4585         iwl_tt_exit(priv);
4586
4587         /* make sure we flush any pending irq or
4588          * tasklet for the driver
4589          */
4590         spin_lock_irqsave(&priv->lock, flags);
4591         iwl_disable_interrupts(priv);
4592         spin_unlock_irqrestore(&priv->lock, flags);
4593
4594         iwl_synchronize_irq(priv);
4595
4596         iwl_dealloc_ucode_pci(priv);
4597
4598         if (priv->rxq.bd)
4599                 iwlagn_rx_queue_free(priv, &priv->rxq);
4600         iwlagn_hw_txq_ctx_free(priv);
4601
4602         iwl_eeprom_free(priv);
4603
4604
4605         /*netif_stop_queue(dev); */
4606         flush_workqueue(priv->workqueue);
4607
4608         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4609          * priv->workqueue... so we can't take down the workqueue
4610          * until now... */
4611         destroy_workqueue(priv->workqueue);
4612         priv->workqueue = NULL;
4613         iwl_free_traffic_mem(priv);
4614
4615         free_irq(priv->pci_dev->irq, priv);
4616         pci_disable_msi(priv->pci_dev);
4617         pci_iounmap(pdev, priv->hw_base);
4618         pci_release_regions(pdev);
4619         pci_disable_device(pdev);
4620         pci_set_drvdata(pdev, NULL);
4621
4622         iwl_uninit_drv(priv);
4623
4624         iwl_free_isr_ict(priv);
4625
4626         if (priv->ibss_beacon)
4627                 dev_kfree_skb(priv->ibss_beacon);
4628
4629         ieee80211_free_hw(priv->hw);
4630 }
4631
4632
4633 /*****************************************************************************
4634  *
4635  * driver and module entry point
4636  *
4637  *****************************************************************************/
4638
4639 /* Hardware specific file defines the PCI IDs table for that hardware module */
4640 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4641 #ifdef CONFIG_IWL4965
4642         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4643         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4644 #endif /* CONFIG_IWL4965 */
4645 #ifdef CONFIG_IWL5000
4646 /* 5100 Series WiFi */
4647         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4648         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4649         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4650         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4651         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4652         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4653         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4654         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4655         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4656         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4657         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4658         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4659         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4660         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4661         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4662         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4663         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4664         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4665         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4666         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4667         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4668         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4669         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4670         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4671
4672 /* 5300 Series WiFi */
4673         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4674         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4675         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4676         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4677         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4678         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4679         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4680         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4681         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4682         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4683         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4684         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4685
4686 /* 5350 Series WiFi/WiMax */
4687         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4688         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4689         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4690
4691 /* 5150 Series Wifi/WiMax */
4692         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4693         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4694         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4695         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4696         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4697         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4698
4699         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4700         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4701         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4702         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4703
4704 /* 6x00 Series */
4705         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4706         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4707         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4708         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4709         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4710         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4711         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4712         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4713         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4714         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4715
4716 /* 6x00 Series Gen2a */
4717         {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4718         {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4719         {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
4720         {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4721         {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4722         {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4723         {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
4724         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4725         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4726         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4727         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4728         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4729         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4730         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
4731
4732 /* 6x00 Series Gen2b */
4733         {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4734         {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4735         {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4736         {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4737         {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4738         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4739         {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4740         {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4741         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4742         {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4743         {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
4744         {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4745         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4746         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4747         {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4748         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4749         {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4750         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4751         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4752         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4753         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4754         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4755         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4756         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4757         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4758         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4759         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4760         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
4761
4762 /* 6x50 WiFi/WiMax Series */
4763         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4764         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4765         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4766         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4767         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4768         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4769
4770 /* 6x50 WiFi/WiMax Series Gen2 */
4771         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4772         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4773         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4774         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4775         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4776         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4777
4778 /* 1000 Series WiFi */
4779         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4780         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4781         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4782         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4783         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4784         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4785         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4786         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4787         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4788         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4789         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4790         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4791 #endif /* CONFIG_IWL5000 */
4792
4793         {0}
4794 };
4795 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4796
4797 static struct pci_driver iwl_driver = {
4798         .name = DRV_NAME,
4799         .id_table = iwl_hw_card_ids,
4800         .probe = iwl_pci_probe,
4801         .remove = __devexit_p(iwl_pci_remove),
4802 #ifdef CONFIG_PM
4803         .suspend = iwl_pci_suspend,
4804         .resume = iwl_pci_resume,
4805 #endif
4806 };
4807
4808 static int __init iwl_init(void)
4809 {
4810
4811         int ret;
4812         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4813         pr_info(DRV_COPYRIGHT "\n");
4814
4815         ret = iwlagn_rate_control_register();
4816         if (ret) {
4817                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4818                 return ret;
4819         }
4820
4821         ret = pci_register_driver(&iwl_driver);
4822         if (ret) {
4823                 pr_err("Unable to initialize PCI module\n");
4824                 goto error_register;
4825         }
4826
4827         return ret;
4828
4829 error_register:
4830         iwlagn_rate_control_unregister();
4831         return ret;
4832 }
4833
4834 static void __exit iwl_exit(void)
4835 {
4836         pci_unregister_driver(&iwl_driver);
4837         iwlagn_rate_control_unregister();
4838 }
4839
4840 module_exit(iwl_exit);
4841 module_init(iwl_init);
4842
4843 #ifdef CONFIG_IWLWIFI_DEBUG
4844 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4845 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4846 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4847 MODULE_PARM_DESC(debug, "debug output mask");
4848 #endif
4849
4850 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4851 MODULE_PARM_DESC(swcrypto50,
4852                  "using crypto in software (default 0 [hardware]) (deprecated)");
4853 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4854 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4855 module_param_named(queues_num50,
4856                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4857 MODULE_PARM_DESC(queues_num50,
4858                  "number of hw queues in 50xx series (deprecated)");
4859 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4860 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4861 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4862 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4863 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4864 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4865 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4866                    int, S_IRUGO);
4867 MODULE_PARM_DESC(amsdu_size_8K50,
4868                  "enable 8K amsdu size in 50XX series (deprecated)");
4869 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4870                    int, S_IRUGO);
4871 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4872 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4873 MODULE_PARM_DESC(fw_restart50,
4874                  "restart firmware in case of error (deprecated)");
4875 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4876 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4877 module_param_named(
4878         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4879 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4880
4881 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4882                    S_IRUGO);
4883 MODULE_PARM_DESC(ucode_alternative,
4884                  "specify ucode alternative to use from ucode file");
4885
4886 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4887 MODULE_PARM_DESC(antenna_coupling,
4888                  "specify antenna coupling in dB (defualt: 0 dB)");
4889
4890 module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4891 MODULE_PARM_DESC(bt_ch_announce,
4892                  "Enable BT channel announcement mode (default: enable)");