1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *****************************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/sched.h>
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/wireless.h>
38 #include <linux/firmware.h>
39 #include <linux/etherdevice.h>
40 #include <asm/unaligned.h>
41 #include <net/mac80211.h>
44 #include "iwl-3945-fh.h"
45 #include "iwl-commands.h"
48 #include "iwl-eeprom.h"
50 #include "iwl-helpers.h"
52 #include "iwl-3945-led.h"
53 #include "iwl-3945-debugfs.h"
55 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
56 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
57 IWL_RATE_##r##M_IEEE, \
58 IWL_RATE_##ip##M_INDEX, \
59 IWL_RATE_##in##M_INDEX, \
60 IWL_RATE_##rp##M_INDEX, \
61 IWL_RATE_##rn##M_INDEX, \
62 IWL_RATE_##pp##M_INDEX, \
63 IWL_RATE_##np##M_INDEX, \
64 IWL_RATE_##r##M_INDEX_TABLE, \
65 IWL_RATE_##ip##M_INDEX_TABLE }
69 * rate, prev rate, next rate, prev tgg rate, next tgg rate
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
75 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
76 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
80 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
90 static inline u8 iwl3945_get_prev_ieee_rate(u8 rate_index)
92 u8 rate = iwl3945_rates[rate_index].prev_ieee;
94 if (rate == IWL_RATE_INVALID)
99 /* 1 = enable the iwl3945_disable_events() function */
100 #define IWL_EVT_DISABLE (0)
101 #define IWL_EVT_DISABLE_SIZE (1532/32)
104 * iwl3945_disable_events - Disable selected events in uCode event log
106 * Disable an event by writing "1"s into "disable"
107 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
108 * Default values of 0 enable uCode events to be logged.
109 * Use for only special debugging. This function is just a placeholder as-is,
110 * you'll need to provide the special bits! ...
111 * ... and set IWL_EVT_DISABLE to 1. */
112 void iwl3945_disable_events(struct iwl_priv *priv)
115 u32 base; /* SRAM address of event log header */
116 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
117 u32 array_size; /* # of u32 entries in array */
118 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
119 0x00000000, /* 31 - 0 Event id numbers */
120 0x00000000, /* 63 - 32 */
121 0x00000000, /* 95 - 64 */
122 0x00000000, /* 127 - 96 */
123 0x00000000, /* 159 - 128 */
124 0x00000000, /* 191 - 160 */
125 0x00000000, /* 223 - 192 */
126 0x00000000, /* 255 - 224 */
127 0x00000000, /* 287 - 256 */
128 0x00000000, /* 319 - 288 */
129 0x00000000, /* 351 - 320 */
130 0x00000000, /* 383 - 352 */
131 0x00000000, /* 415 - 384 */
132 0x00000000, /* 447 - 416 */
133 0x00000000, /* 479 - 448 */
134 0x00000000, /* 511 - 480 */
135 0x00000000, /* 543 - 512 */
136 0x00000000, /* 575 - 544 */
137 0x00000000, /* 607 - 576 */
138 0x00000000, /* 639 - 608 */
139 0x00000000, /* 671 - 640 */
140 0x00000000, /* 703 - 672 */
141 0x00000000, /* 735 - 704 */
142 0x00000000, /* 767 - 736 */
143 0x00000000, /* 799 - 768 */
144 0x00000000, /* 831 - 800 */
145 0x00000000, /* 863 - 832 */
146 0x00000000, /* 895 - 864 */
147 0x00000000, /* 927 - 896 */
148 0x00000000, /* 959 - 928 */
149 0x00000000, /* 991 - 960 */
150 0x00000000, /* 1023 - 992 */
151 0x00000000, /* 1055 - 1024 */
152 0x00000000, /* 1087 - 1056 */
153 0x00000000, /* 1119 - 1088 */
154 0x00000000, /* 1151 - 1120 */
155 0x00000000, /* 1183 - 1152 */
156 0x00000000, /* 1215 - 1184 */
157 0x00000000, /* 1247 - 1216 */
158 0x00000000, /* 1279 - 1248 */
159 0x00000000, /* 1311 - 1280 */
160 0x00000000, /* 1343 - 1312 */
161 0x00000000, /* 1375 - 1344 */
162 0x00000000, /* 1407 - 1376 */
163 0x00000000, /* 1439 - 1408 */
164 0x00000000, /* 1471 - 1440 */
165 0x00000000, /* 1503 - 1472 */
168 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
169 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
170 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
174 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
175 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
177 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
178 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
180 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
181 iwl_write_targ_mem(priv,
182 disable_ptr + (i * sizeof(u32)),
186 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
187 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
188 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
189 disable_ptr, array_size);
194 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
198 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
199 if (iwl3945_rates[idx].plcp == plcp)
204 #ifdef CONFIG_IWLWIFI_DEBUG
205 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
207 static const char *iwl3945_get_tx_fail_reason(u32 status)
209 switch (status & TX_STATUS_MSK) {
210 case TX_3945_STATUS_SUCCESS:
212 TX_STATUS_ENTRY(SHORT_LIMIT);
213 TX_STATUS_ENTRY(LONG_LIMIT);
214 TX_STATUS_ENTRY(FIFO_UNDERRUN);
215 TX_STATUS_ENTRY(MGMNT_ABORT);
216 TX_STATUS_ENTRY(NEXT_FRAG);
217 TX_STATUS_ENTRY(LIFE_EXPIRE);
218 TX_STATUS_ENTRY(DEST_PS);
219 TX_STATUS_ENTRY(ABORTED);
220 TX_STATUS_ENTRY(BT_RETRY);
221 TX_STATUS_ENTRY(STA_INVALID);
222 TX_STATUS_ENTRY(FRAG_DROPPED);
223 TX_STATUS_ENTRY(TID_DISABLE);
224 TX_STATUS_ENTRY(FRAME_FLUSHED);
225 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
226 TX_STATUS_ENTRY(TX_LOCKED);
227 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
233 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
240 * get ieee prev rate from rate scale table.
241 * for A and B mode we need to overright prev
244 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
246 int next_rate = iwl3945_get_prev_ieee_rate(rate);
248 switch (priv->band) {
249 case IEEE80211_BAND_5GHZ:
250 if (rate == IWL_RATE_12M_INDEX)
251 next_rate = IWL_RATE_9M_INDEX;
252 else if (rate == IWL_RATE_6M_INDEX)
253 next_rate = IWL_RATE_6M_INDEX;
255 case IEEE80211_BAND_2GHZ:
256 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
257 iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
258 if (rate == IWL_RATE_11M_INDEX)
259 next_rate = IWL_RATE_5M_INDEX;
272 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
274 * When FW advances 'R' index, all entries between old and new 'R' index
275 * need to be reclaimed. As result, some free space forms. If there is
276 * enough free space (> low mark), wake the stack that feeds us.
278 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
279 int txq_id, int index)
281 struct iwl_tx_queue *txq = &priv->txq[txq_id];
282 struct iwl_queue *q = &txq->q;
283 struct iwl_tx_info *tx_info;
285 BUG_ON(txq_id == IWL39_CMD_QUEUE_NUM);
287 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
288 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
290 tx_info = &txq->txb[txq->q.read_ptr];
291 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
293 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
296 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
297 (txq_id != IWL39_CMD_QUEUE_NUM) &&
298 priv->mac80211_registered)
299 iwl_wake_queue(priv, txq_id);
303 * iwl3945_rx_reply_tx - Handle Tx response
305 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
306 struct iwl_rx_mem_buffer *rxb)
308 struct iwl_rx_packet *pkt = rxb_addr(rxb);
309 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
310 int txq_id = SEQ_TO_QUEUE(sequence);
311 int index = SEQ_TO_INDEX(sequence);
312 struct iwl_tx_queue *txq = &priv->txq[txq_id];
313 struct ieee80211_tx_info *info;
314 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
315 u32 status = le32_to_cpu(tx_resp->status);
319 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
320 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
321 "is out of range [0-%d] %d %d\n", txq_id,
322 index, txq->q.n_bd, txq->q.write_ptr,
327 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
328 ieee80211_tx_info_clear_status(info);
330 /* Fill the MRR chain with some info about on-chip retransmissions */
331 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
332 if (info->band == IEEE80211_BAND_5GHZ)
333 rate_idx -= IWL_FIRST_OFDM_RATE;
335 fail = tx_resp->failure_frame;
337 info->status.rates[0].idx = rate_idx;
338 info->status.rates[0].count = fail + 1; /* add final attempt */
340 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
341 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
342 IEEE80211_TX_STAT_ACK : 0;
344 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
345 txq_id, iwl3945_get_tx_fail_reason(status), status,
346 tx_resp->rate, tx_resp->failure_frame);
348 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
349 iwl3945_tx_queue_reclaim(priv, txq_id, index);
351 if (status & TX_ABORT_REQUIRED_MSK)
352 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
357 /*****************************************************************************
359 * Intel PRO/Wireless 3945ABG/BG Network Connection
361 * RX handler implementations
363 *****************************************************************************/
364 #ifdef CONFIG_IWLWIFI_DEBUGFS
366 * based on the assumption of all statistics counter are in DWORD
367 * FIXME: This function is for debugging, do not deal with
368 * the case of counters roll-over.
370 static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
376 u32 *delta, *max_delta;
378 prev_stats = (__le32 *)&priv->_3945.statistics;
379 accum_stats = (u32 *)&priv->_3945.accum_statistics;
380 delta = (u32 *)&priv->_3945.delta_statistics;
381 max_delta = (u32 *)&priv->_3945.max_delta;
383 for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
384 i += sizeof(__le32), stats++, prev_stats++, delta++,
385 max_delta++, accum_stats++) {
386 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
387 *delta = (le32_to_cpu(*stats) -
388 le32_to_cpu(*prev_stats));
389 *accum_stats += *delta;
390 if (*delta > *max_delta)
395 /* reset accumulative statistics for "no-counter" type statistics */
396 priv->_3945.accum_statistics.general.temperature =
397 priv->_3945.statistics.general.temperature;
398 priv->_3945.accum_statistics.general.ttl_timestamp =
399 priv->_3945.statistics.general.ttl_timestamp;
404 * iwl3945_good_plcp_health - checks for plcp error.
406 * When the plcp error is exceeding the thresholds, reset the radio
407 * to improve the throughput.
409 static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
410 struct iwl_rx_packet *pkt)
413 struct iwl3945_notif_statistics current_stat;
414 int combined_plcp_delta;
415 unsigned int plcp_msec;
416 unsigned long plcp_received_jiffies;
418 if (priv->cfg->base_params->plcp_delta_threshold ==
419 IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) {
420 IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n");
423 memcpy(¤t_stat, pkt->u.raw, sizeof(struct
424 iwl3945_notif_statistics));
426 * check for plcp_err and trigger radio reset if it exceeds
427 * the plcp error threshold plcp_delta.
429 plcp_received_jiffies = jiffies;
430 plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
431 (long) priv->plcp_jiffies);
432 priv->plcp_jiffies = plcp_received_jiffies;
434 * check to make sure plcp_msec is not 0 to prevent division
438 combined_plcp_delta =
439 (le32_to_cpu(current_stat.rx.ofdm.plcp_err) -
440 le32_to_cpu(priv->_3945.statistics.rx.ofdm.plcp_err));
442 if ((combined_plcp_delta > 0) &&
443 ((combined_plcp_delta * 100) / plcp_msec) >
444 priv->cfg->base_params->plcp_delta_threshold) {
446 * if plcp_err exceed the threshold, the following
447 * data is printed in csv format:
448 * Text: plcp_err exceeded %d,
449 * Received ofdm.plcp_err,
450 * Current ofdm.plcp_err,
451 * combined_plcp_delta,
454 IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
455 "%u, %d, %u mSecs\n",
456 priv->cfg->base_params->plcp_delta_threshold,
457 le32_to_cpu(current_stat.rx.ofdm.plcp_err),
458 combined_plcp_delta, plcp_msec);
460 * Reset the RF radio due to the high plcp
469 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
470 struct iwl_rx_mem_buffer *rxb)
472 struct iwl_rx_packet *pkt = rxb_addr(rxb);
474 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
475 (int)sizeof(struct iwl3945_notif_statistics),
476 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
477 #ifdef CONFIG_IWLWIFI_DEBUGFS
478 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
480 iwl_recover_from_statistics(priv, pkt);
482 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
485 void iwl3945_reply_statistics(struct iwl_priv *priv,
486 struct iwl_rx_mem_buffer *rxb)
488 struct iwl_rx_packet *pkt = rxb_addr(rxb);
489 __le32 *flag = (__le32 *)&pkt->u.raw;
491 if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
492 #ifdef CONFIG_IWLWIFI_DEBUGFS
493 memset(&priv->_3945.accum_statistics, 0,
494 sizeof(struct iwl3945_notif_statistics));
495 memset(&priv->_3945.delta_statistics, 0,
496 sizeof(struct iwl3945_notif_statistics));
497 memset(&priv->_3945.max_delta, 0,
498 sizeof(struct iwl3945_notif_statistics));
500 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
502 iwl3945_hw_rx_statistics(priv, rxb);
506 /******************************************************************************
508 * Misc. internal state and helper functions
510 ******************************************************************************/
512 /* This is necessary only for a number of statistics, see the caller. */
513 static int iwl3945_is_network_packet(struct iwl_priv *priv,
514 struct ieee80211_hdr *header)
516 /* Filter incoming packets to determine if they are targeted toward
517 * this network, discarding packets coming from ourselves */
518 switch (priv->iw_mode) {
519 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
520 /* packets to our IBSS update information */
521 return !compare_ether_addr(header->addr3, priv->bssid);
522 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
523 /* packets to our IBSS update information */
524 return !compare_ether_addr(header->addr2, priv->bssid);
530 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
531 struct iwl_rx_mem_buffer *rxb,
532 struct ieee80211_rx_status *stats)
534 struct iwl_rx_packet *pkt = rxb_addr(rxb);
535 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
536 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
537 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
538 u16 len = le16_to_cpu(rx_hdr->len);
540 __le16 fc = hdr->frame_control;
542 /* We received data from the HW, so stop the watchdog */
543 if (unlikely(len + IWL39_RX_FRAME_SIZE >
544 PAGE_SIZE << priv->hw_params.rx_page_order)) {
545 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
549 /* We only process data packets if the interface is open */
550 if (unlikely(!priv->is_open)) {
551 IWL_DEBUG_DROP_LIMIT(priv,
552 "Dropping packet while interface is not open.\n");
556 skb = dev_alloc_skb(128);
558 IWL_ERR(priv, "dev_alloc_skb failed\n");
562 if (!iwl3945_mod_params.sw_crypto)
563 iwl_set_decrypted_flag(priv,
564 (struct ieee80211_hdr *)rxb_addr(rxb),
565 le32_to_cpu(rx_end->status), stats);
567 skb_add_rx_frag(skb, 0, rxb->page,
568 (void *)rx_hdr->payload - (void *)pkt, len);
570 iwl_update_stats(priv, false, fc, len);
571 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
573 ieee80211_rx(priv->hw, skb);
574 priv->alloc_rxb_page--;
578 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
580 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
581 struct iwl_rx_mem_buffer *rxb)
583 struct ieee80211_hdr *header;
584 struct ieee80211_rx_status rx_status;
585 struct iwl_rx_packet *pkt = rxb_addr(rxb);
586 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
587 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
588 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
589 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
590 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
594 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
596 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
597 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
598 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
600 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
601 if (rx_status.band == IEEE80211_BAND_5GHZ)
602 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
604 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
605 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
607 /* set the preamble flag if appropriate */
608 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
609 rx_status.flag |= RX_FLAG_SHORTPRE;
611 if ((unlikely(rx_stats->phy_count > 20))) {
612 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
613 rx_stats->phy_count);
617 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
618 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
619 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
625 /* Convert 3945's rssi indicator to dBm */
626 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
628 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
629 rx_status.signal, rx_stats_sig_avg,
630 rx_stats_noise_diff);
632 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
634 network_packet = iwl3945_is_network_packet(priv, header);
636 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
637 network_packet ? '*' : ' ',
638 le16_to_cpu(rx_hdr->channel),
639 rx_status.signal, rx_status.signal,
642 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
644 if (network_packet) {
645 priv->_3945.last_beacon_time =
646 le32_to_cpu(rx_end->beacon_timestamp);
647 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
648 priv->_3945.last_rx_rssi = rx_status.signal;
651 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
654 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
655 struct iwl_tx_queue *txq,
656 dma_addr_t addr, u16 len, u8 reset, u8 pad)
660 struct iwl3945_tfd *tfd, *tfd_tmp;
663 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
664 tfd = &tfd_tmp[q->write_ptr];
667 memset(tfd, 0, sizeof(*tfd));
669 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
671 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
672 IWL_ERR(priv, "Error can not send more than %d chunks\n",
677 tfd->tbs[count].addr = cpu_to_le32(addr);
678 tfd->tbs[count].len = cpu_to_le32(len);
682 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
683 TFD_CTL_PAD_SET(pad));
689 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
691 * Does NOT advance any indexes
693 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
695 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
696 int index = txq->q.read_ptr;
697 struct iwl3945_tfd *tfd = &tfd_tmp[index];
698 struct pci_dev *dev = priv->pci_dev;
703 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
704 if (counter > NUM_TFD_CHUNKS) {
705 IWL_ERR(priv, "Too many chunks: %i\n", counter);
706 /* @todo issue fatal error, it is quite serious situation */
712 pci_unmap_single(dev,
713 dma_unmap_addr(&txq->meta[index], mapping),
714 dma_unmap_len(&txq->meta[index], len),
717 /* unmap chunks if any */
719 for (i = 1; i < counter; i++)
720 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
721 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
727 skb = txq->txb[txq->q.read_ptr].skb;
729 /* can be called from irqs-disabled context */
731 dev_kfree_skb_any(skb);
732 txq->txb[txq->q.read_ptr].skb = NULL;
738 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
741 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
742 struct iwl_device_cmd *cmd,
743 struct ieee80211_tx_info *info,
744 struct ieee80211_hdr *hdr,
745 int sta_id, int tx_id)
747 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
748 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
754 __le16 fc = hdr->frame_control;
755 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
757 rate = iwl3945_rates[rate_index].plcp;
758 tx_flags = tx_cmd->tx_flags;
760 /* We need to figure out how to get the sta->supp_rates while
761 * in this running context */
762 rate_mask = IWL_RATES_MASK;
765 /* Set retry limit on DATA packets and Probe Responses*/
766 if (ieee80211_is_probe_resp(fc))
767 data_retry_limit = 3;
769 data_retry_limit = IWL_DEFAULT_TX_RETRY;
770 tx_cmd->data_retry_limit = data_retry_limit;
772 if (tx_id >= IWL39_CMD_QUEUE_NUM)
777 if (data_retry_limit < rts_retry_limit)
778 rts_retry_limit = data_retry_limit;
779 tx_cmd->rts_retry_limit = rts_retry_limit;
782 tx_cmd->tx_flags = tx_flags;
785 tx_cmd->supp_rates[0] =
786 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
789 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
791 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
792 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
793 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
794 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
797 static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
799 unsigned long flags_spin;
800 struct iwl_station_entry *station;
802 if (sta_id == IWL_INVALID_STATION)
803 return IWL_INVALID_STATION;
805 spin_lock_irqsave(&priv->sta_lock, flags_spin);
806 station = &priv->stations[sta_id];
808 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
809 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
810 station->sta.mode = STA_CONTROL_MODIFY_MSK;
811 iwl_send_add_sta(priv, &station->sta, CMD_ASYNC);
812 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
814 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
819 static void iwl3945_set_pwr_vmain(struct iwl_priv *priv)
822 * (for documentation purposes)
823 * to set power to V_AUX, do
825 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
826 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
827 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
828 ~APMG_PS_CTRL_MSK_PWR_SRC);
830 iwl_poll_bit(priv, CSR_GPIO_IN,
831 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
832 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
836 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
837 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
838 ~APMG_PS_CTRL_MSK_PWR_SRC);
840 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
841 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
844 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
846 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
847 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
848 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
849 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
850 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
851 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
852 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
853 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
854 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
855 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
856 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
857 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
859 /* fake read to flush all prev I/O */
860 iwl_read_direct32(priv, FH39_RSSR_CTRL);
865 static int iwl3945_tx_reset(struct iwl_priv *priv)
869 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
872 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
874 /* all 6 fifo are active */
875 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
877 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
878 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
879 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
880 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
882 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
883 priv->_3945.shared_phys);
885 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
886 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
887 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
888 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
889 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
890 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
891 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
892 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
899 * iwl3945_txq_ctx_reset - Reset TX queue context
901 * Destroys all DMA structures and initialize them again
903 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
906 int txq_id, slots_num;
908 iwl3945_hw_txq_ctx_free(priv);
910 /* allocate tx queue structure */
911 rc = iwl_alloc_txq_mem(priv);
916 rc = iwl3945_tx_reset(priv);
921 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
922 slots_num = (txq_id == IWL39_CMD_QUEUE_NUM) ?
923 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
924 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
927 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
935 iwl3945_hw_txq_ctx_free(priv);
941 * Start up 3945's basic functionality after it has been reset
942 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
943 * NOTE: This does not load uCode nor start the embedded processor
945 static int iwl3945_apm_init(struct iwl_priv *priv)
947 int ret = iwl_apm_init(priv);
949 /* Clear APMG (NIC's internal power management) interrupts */
950 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
951 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
953 /* Reset radio chip */
954 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
956 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
961 static void iwl3945_nic_config(struct iwl_priv *priv)
963 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
967 spin_lock_irqsave(&priv->lock, flags);
969 /* Determine HW type */
970 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
972 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
974 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
975 IWL_DEBUG_INFO(priv, "RTP type\n");
976 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
977 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
978 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
979 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
981 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
982 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
983 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
986 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
987 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
988 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
989 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
991 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
993 if ((eeprom->board_revision & 0xF0) == 0xD0) {
994 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
995 eeprom->board_revision);
996 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
997 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
999 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1000 eeprom->board_revision);
1001 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1002 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1005 if (eeprom->almgor_m_version <= 1) {
1006 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1007 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1008 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1009 eeprom->almgor_m_version);
1011 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1012 eeprom->almgor_m_version);
1013 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1014 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1016 spin_unlock_irqrestore(&priv->lock, flags);
1018 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1019 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1021 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1022 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1025 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1028 unsigned long flags;
1029 struct iwl_rx_queue *rxq = &priv->rxq;
1031 spin_lock_irqsave(&priv->lock, flags);
1032 priv->cfg->ops->lib->apm_ops.init(priv);
1033 spin_unlock_irqrestore(&priv->lock, flags);
1035 iwl3945_set_pwr_vmain(priv);
1037 priv->cfg->ops->lib->apm_ops.config(priv);
1039 /* Allocate the RX queue, or reset if it is already allocated */
1041 rc = iwl_rx_queue_alloc(priv);
1043 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1047 iwl3945_rx_queue_reset(priv, rxq);
1049 iwl3945_rx_replenish(priv);
1051 iwl3945_rx_init(priv, rxq);
1054 /* Look at using this instead:
1055 rxq->need_update = 1;
1056 iwl_rx_queue_update_write_ptr(priv, rxq);
1059 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1061 rc = iwl3945_txq_ctx_reset(priv);
1065 set_bit(STATUS_INIT, &priv->status);
1071 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1073 * Destroy all TX DMA queues and structures
1075 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1081 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1083 if (txq_id == IWL39_CMD_QUEUE_NUM)
1084 iwl_cmd_queue_free(priv);
1086 iwl_tx_queue_free(priv, txq_id);
1088 /* free tx queue structure */
1089 iwl_free_txq_mem(priv);
1092 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1097 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1098 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1100 /* reset TFD queues */
1101 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1102 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1103 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1104 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1108 iwl3945_hw_txq_ctx_free(priv);
1112 * iwl3945_hw_reg_adjust_power_by_temp
1113 * return index delta into power gain settings table
1115 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1117 return (new_reading - old_reading) * (-11) / 100;
1121 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1123 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1125 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1128 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1130 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1134 * iwl3945_hw_reg_txpower_get_temperature
1135 * get the current temperature by reading from NIC
1137 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1139 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1142 temperature = iwl3945_hw_get_temperature(priv);
1144 /* driver's okay range is -260 to +25.
1145 * human readable okay range is 0 to +285 */
1146 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1148 /* handle insane temp reading */
1149 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1150 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1152 /* if really really hot(?),
1153 * substitute the 3rd band/group's temp measured at factory */
1154 if (priv->last_temperature > 100)
1155 temperature = eeprom->groups[2].temperature;
1156 else /* else use most recent "sane" value from driver */
1157 temperature = priv->last_temperature;
1160 return temperature; /* raw, not "human readable" */
1163 /* Adjust Txpower only if temperature variance is greater than threshold.
1165 * Both are lower than older versions' 9 degrees */
1166 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1169 * is_temp_calib_needed - determines if new calibration is needed
1171 * records new temperature in tx_mgr->temperature.
1172 * replaces tx_mgr->last_temperature *only* if calib needed
1173 * (assumes caller will actually do the calibration!). */
1174 static int is_temp_calib_needed(struct iwl_priv *priv)
1178 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1179 temp_diff = priv->temperature - priv->last_temperature;
1181 /* get absolute value */
1182 if (temp_diff < 0) {
1183 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1184 temp_diff = -temp_diff;
1185 } else if (temp_diff == 0)
1186 IWL_DEBUG_POWER(priv, "Same temp,\n");
1188 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1190 /* if we don't need calibration, *don't* update last_temperature */
1191 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1192 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1196 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1198 /* assume that caller will actually do calib ...
1199 * update the "last temperature" value */
1200 priv->last_temperature = priv->temperature;
1204 #define IWL_MAX_GAIN_ENTRIES 78
1205 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1206 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1208 /* radio and DSP power table, each step is 1/2 dB.
1209 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1210 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1212 {251, 127}, /* 2.4 GHz, highest power */
1289 {3, 95} }, /* 2.4 GHz, lowest power */
1291 {251, 127}, /* 5.x GHz, highest power */
1368 {3, 120} } /* 5.x GHz, lowest power */
1371 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1375 if (index >= IWL_MAX_GAIN_ENTRIES)
1376 return IWL_MAX_GAIN_ENTRIES - 1;
1380 /* Kick off thermal recalibration check every 60 seconds */
1381 #define REG_RECALIB_PERIOD (60)
1384 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1386 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1387 * or 6 Mbit (OFDM) rates.
1389 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1390 s32 rate_index, const s8 *clip_pwrs,
1391 struct iwl_channel_info *ch_info,
1394 struct iwl3945_scan_power_info *scan_power_info;
1398 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1400 /* use this channel group's 6Mbit clipping/saturation pwr,
1401 * but cap at regulatory scan power restriction (set during init
1402 * based on eeprom channel data) for this channel. */
1403 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1405 /* further limit to user's max power preference.
1406 * FIXME: Other spectrum management power limitations do not
1407 * seem to apply?? */
1408 power = min(power, priv->tx_power_user_lmt);
1409 scan_power_info->requested_power = power;
1411 /* find difference between new scan *power* and current "normal"
1412 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1413 * current "normal" temperature-compensated Tx power *index* for
1414 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1416 power_index = ch_info->power_info[rate_index].power_table_index
1417 - (power - ch_info->power_info
1418 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1420 /* store reference index that we use when adjusting *all* scan
1421 * powers. So we can accommodate user (all channel) or spectrum
1422 * management (single channel) power changes "between" temperature
1423 * feedback compensation procedures.
1424 * don't force fit this reference index into gain table; it may be a
1425 * negative number. This will help avoid errors when we're at
1426 * the lower bounds (highest gains, for warmest temperatures)
1429 /* don't exceed table bounds for "real" setting */
1430 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1432 scan_power_info->power_table_index = power_index;
1433 scan_power_info->tpc.tx_gain =
1434 power_gain_table[band_index][power_index].tx_gain;
1435 scan_power_info->tpc.dsp_atten =
1436 power_gain_table[band_index][power_index].dsp_atten;
1440 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1442 * Configures power settings for all rates for the current channel,
1443 * using values from channel info struct, and send to NIC
1445 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1448 const struct iwl_channel_info *ch_info = NULL;
1449 struct iwl3945_txpowertable_cmd txpower = {
1450 .channel = priv->contexts[IWL_RXON_CTX_BSS].active.channel,
1454 chan = le16_to_cpu(priv->contexts[IWL_RXON_CTX_BSS].active.channel);
1456 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1457 ch_info = iwl_get_channel_info(priv, priv->band, chan);
1460 "Failed to get channel info for channel %d [%d]\n",
1465 if (!is_channel_valid(ch_info)) {
1466 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1467 "non-Tx channel.\n");
1471 /* fill cmd with power settings for all rates for current channel */
1472 /* Fill OFDM rate */
1473 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1474 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1476 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1477 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1479 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1480 le16_to_cpu(txpower.channel),
1482 txpower.power[i].tpc.tx_gain,
1483 txpower.power[i].tpc.dsp_atten,
1484 txpower.power[i].rate);
1486 /* Fill CCK rates */
1487 for (rate_idx = IWL_FIRST_CCK_RATE;
1488 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1489 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1490 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1492 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1493 le16_to_cpu(txpower.channel),
1495 txpower.power[i].tpc.tx_gain,
1496 txpower.power[i].tpc.dsp_atten,
1497 txpower.power[i].rate);
1500 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1501 sizeof(struct iwl3945_txpowertable_cmd),
1507 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1508 * @ch_info: Channel to update. Uses power_info.requested_power.
1510 * Replace requested_power and base_power_index ch_info fields for
1513 * Called if user or spectrum management changes power preferences.
1514 * Takes into account h/w and modulation limitations (clip power).
1516 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1518 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1519 * properly fill out the scan powers, and actual h/w gain settings,
1520 * and send changes to NIC
1522 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1523 struct iwl_channel_info *ch_info)
1525 struct iwl3945_channel_power_info *power_info;
1526 int power_changed = 0;
1528 const s8 *clip_pwrs;
1531 /* Get this chnlgrp's rate-to-max/clip-powers table */
1532 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1534 /* Get this channel's rate-to-current-power settings table */
1535 power_info = ch_info->power_info;
1537 /* update OFDM Txpower settings */
1538 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1539 i++, ++power_info) {
1542 /* limit new power to be no more than h/w capability */
1543 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1544 if (power == power_info->requested_power)
1547 /* find difference between old and new requested powers,
1548 * update base (non-temp-compensated) power index */
1549 delta_idx = (power - power_info->requested_power) * 2;
1550 power_info->base_power_index -= delta_idx;
1552 /* save new requested power value */
1553 power_info->requested_power = power;
1558 /* update CCK Txpower settings, based on OFDM 12M setting ...
1559 * ... all CCK power settings for a given channel are the *same*. */
1560 if (power_changed) {
1562 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1563 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1565 /* do all CCK rates' iwl3945_channel_power_info structures */
1566 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1567 power_info->requested_power = power;
1568 power_info->base_power_index =
1569 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1570 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1579 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1581 * NOTE: Returned power limit may be less (but not more) than requested,
1582 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1583 * (no consideration for h/w clipping limitations).
1585 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1590 /* if we're using TGd limits, use lower of TGd or EEPROM */
1591 if (ch_info->tgd_data.max_power != 0)
1592 max_power = min(ch_info->tgd_data.max_power,
1593 ch_info->eeprom.max_power_avg);
1595 /* else just use EEPROM limits */
1598 max_power = ch_info->eeprom.max_power_avg;
1600 return min(max_power, ch_info->max_power_avg);
1604 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1606 * Compensate txpower settings of *all* channels for temperature.
1607 * This only accounts for the difference between current temperature
1608 * and the factory calibration temperatures, and bases the new settings
1609 * on the channel's base_power_index.
1611 * If RxOn is "associated", this sends the new Txpower to NIC!
1613 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1615 struct iwl_channel_info *ch_info = NULL;
1616 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1618 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1624 int temperature = priv->temperature;
1626 if (priv->disable_tx_power_cal ||
1627 test_bit(STATUS_SCANNING, &priv->status)) {
1628 /* do not perform tx power calibration */
1631 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1632 for (i = 0; i < priv->channel_count; i++) {
1633 ch_info = &priv->channel_info[i];
1634 a_band = is_channel_a_band(ch_info);
1636 /* Get this chnlgrp's factory calibration temperature */
1637 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1640 /* get power index adjustment based on current and factory
1642 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1645 /* set tx power value for all rates, OFDM and CCK */
1646 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1649 ch_info->power_info[rate_index].base_power_index;
1651 /* temperature compensate */
1652 power_idx += delta_index;
1654 /* stay within table range */
1655 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1656 ch_info->power_info[rate_index].
1657 power_table_index = (u8) power_idx;
1658 ch_info->power_info[rate_index].tpc =
1659 power_gain_table[a_band][power_idx];
1662 /* Get this chnlgrp's rate-to-max/clip-powers table */
1663 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1665 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1666 for (scan_tbl_index = 0;
1667 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1668 s32 actual_index = (scan_tbl_index == 0) ?
1669 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1670 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1671 actual_index, clip_pwrs,
1676 /* send Txpower command for current channel to ucode */
1677 return priv->cfg->ops->lib->send_tx_power(priv);
1680 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1682 struct iwl_channel_info *ch_info;
1687 if (priv->tx_power_user_lmt == power) {
1688 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1689 "limit: %ddBm.\n", power);
1693 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1694 priv->tx_power_user_lmt = power;
1696 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1698 for (i = 0; i < priv->channel_count; i++) {
1699 ch_info = &priv->channel_info[i];
1700 a_band = is_channel_a_band(ch_info);
1702 /* find minimum power of all user and regulatory constraints
1703 * (does not consider h/w clipping limitations) */
1704 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1705 max_power = min(power, max_power);
1706 if (max_power != ch_info->curr_txpow) {
1707 ch_info->curr_txpow = max_power;
1709 /* this considers the h/w clipping limitations */
1710 iwl3945_hw_reg_set_new_power(priv, ch_info);
1714 /* update txpower settings for all channels,
1715 * send to NIC if associated. */
1716 is_temp_calib_needed(priv);
1717 iwl3945_hw_reg_comp_txpower_temp(priv);
1722 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv,
1723 struct iwl_rxon_context *ctx)
1726 struct iwl_rx_packet *pkt;
1727 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1728 struct iwl_host_cmd cmd = {
1729 .id = REPLY_RXON_ASSOC,
1730 .len = sizeof(rxon_assoc),
1731 .flags = CMD_WANT_SKB,
1732 .data = &rxon_assoc,
1734 const struct iwl_rxon_cmd *rxon1 = &ctx->staging;
1735 const struct iwl_rxon_cmd *rxon2 = &ctx->active;
1737 if ((rxon1->flags == rxon2->flags) &&
1738 (rxon1->filter_flags == rxon2->filter_flags) &&
1739 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1740 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1741 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1745 rxon_assoc.flags = ctx->staging.flags;
1746 rxon_assoc.filter_flags = ctx->staging.filter_flags;
1747 rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates;
1748 rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates;
1749 rxon_assoc.reserved = 0;
1751 rc = iwl_send_cmd_sync(priv, &cmd);
1755 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1756 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1757 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1761 iwl_free_pages(priv, cmd.reply_page);
1767 * iwl3945_commit_rxon - commit staging_rxon to hardware
1769 * The RXON command in staging_rxon is committed to the hardware and
1770 * the active_rxon structure is updated with the new data. This
1771 * function correctly transitions out of the RXON_ASSOC_MSK state if
1772 * a HW tune is required based on the RXON structure changes.
1774 int iwl3945_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
1776 /* cast away the const for active_rxon in this function */
1777 struct iwl3945_rxon_cmd *active_rxon = (void *)&ctx->active;
1778 struct iwl3945_rxon_cmd *staging_rxon = (void *)&ctx->staging;
1780 bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1782 if (!iwl_is_alive(priv))
1785 /* always get timestamp with Rx frame */
1786 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1788 /* select antenna */
1789 staging_rxon->flags &=
1790 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1791 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1793 rc = iwl_check_rxon_cmd(priv, ctx);
1795 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1799 /* If we don't need to send a full RXON, we can use
1800 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1801 * and other flags for the current radio configuration. */
1802 if (!iwl_full_rxon_required(priv, &priv->contexts[IWL_RXON_CTX_BSS])) {
1803 rc = iwl_send_rxon_assoc(priv,
1804 &priv->contexts[IWL_RXON_CTX_BSS]);
1806 IWL_ERR(priv, "Error setting RXON_ASSOC "
1807 "configuration (%d).\n", rc);
1811 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1816 /* If we are currently associated and the new config requires
1817 * an RXON_ASSOC and the new config wants the associated mask enabled,
1818 * we must clear the associated from the active configuration
1819 * before we apply the new config */
1820 if (iwl_is_associated(priv, IWL_RXON_CTX_BSS) && new_assoc) {
1821 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1822 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1825 * reserved4 and 5 could have been filled by the iwlcore code.
1826 * Let's clear them before pushing to the 3945.
1828 active_rxon->reserved4 = 0;
1829 active_rxon->reserved5 = 0;
1830 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1831 sizeof(struct iwl3945_rxon_cmd),
1832 &priv->contexts[IWL_RXON_CTX_BSS].active);
1834 /* If the mask clearing failed then we set
1835 * active_rxon back to what it was previously */
1837 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1838 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1839 "configuration (%d).\n", rc);
1842 iwl_clear_ucode_stations(priv,
1843 &priv->contexts[IWL_RXON_CTX_BSS]);
1844 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1847 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1848 "* with%s RXON_FILTER_ASSOC_MSK\n"
1851 (new_assoc ? "" : "out"),
1852 le16_to_cpu(staging_rxon->channel),
1853 staging_rxon->bssid_addr);
1856 * reserved4 and 5 could have been filled by the iwlcore code.
1857 * Let's clear them before pushing to the 3945.
1859 staging_rxon->reserved4 = 0;
1860 staging_rxon->reserved5 = 0;
1862 iwl_set_rxon_hwcrypto(priv, ctx, !iwl3945_mod_params.sw_crypto);
1864 /* Apply the new configuration */
1865 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1866 sizeof(struct iwl3945_rxon_cmd),
1869 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1873 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1876 iwl_clear_ucode_stations(priv,
1877 &priv->contexts[IWL_RXON_CTX_BSS]);
1878 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1881 /* If we issue a new RXON command which required a tune then we must
1882 * send a new TXPOWER command or we won't be able to Tx any frames */
1883 rc = priv->cfg->ops->lib->send_tx_power(priv);
1885 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1889 /* Init the hardware's rate fallback order based on the band */
1890 rc = iwl3945_init_hw_rate_table(priv);
1892 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1900 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1902 * -- reset periodic timer
1903 * -- see if temp has changed enough to warrant re-calibration ... if so:
1904 * -- correct coeffs for temp (can reset temp timer)
1905 * -- save this temp as "last",
1906 * -- send new set of gain settings to NIC
1907 * NOTE: This should continue working, even when we're not associated,
1908 * so we can keep our internal table of scan powers current. */
1909 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1911 /* This will kick in the "brute force"
1912 * iwl3945_hw_reg_comp_txpower_temp() below */
1913 if (!is_temp_calib_needed(priv))
1916 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1917 * This is based *only* on current temperature,
1918 * ignoring any previous power measurements */
1919 iwl3945_hw_reg_comp_txpower_temp(priv);
1922 queue_delayed_work(priv->workqueue,
1923 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1926 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1928 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1929 _3945.thermal_periodic.work);
1931 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1934 mutex_lock(&priv->mutex);
1935 iwl3945_reg_txpower_periodic(priv);
1936 mutex_unlock(&priv->mutex);
1940 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1943 * This function is used when initializing channel-info structs.
1945 * NOTE: These channel groups do *NOT* match the bands above!
1946 * These channel groups are based on factory-tested channels;
1947 * on A-band, EEPROM's "group frequency" entries represent the top
1948 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1950 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1951 const struct iwl_channel_info *ch_info)
1953 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1954 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1956 u16 group_index = 0; /* based on factory calib frequencies */
1959 /* Find the group index for the channel ... don't use index 1(?) */
1960 if (is_channel_a_band(ch_info)) {
1961 for (group = 1; group < 5; group++) {
1962 grp_channel = ch_grp[group].group_channel;
1963 if (ch_info->channel <= grp_channel) {
1964 group_index = group;
1968 /* group 4 has a few channels *above* its factory cal freq */
1972 group_index = 0; /* 2.4 GHz, group 0 */
1974 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
1980 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
1982 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1983 * into radio/DSP gain settings table for requested power.
1985 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
1987 s32 setting_index, s32 *new_index)
1989 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
1990 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1992 s32 power = 2 * requested_power;
1994 const struct iwl3945_eeprom_txpower_sample *samples;
1999 chnl_grp = &eeprom->groups[setting_index];
2000 samples = chnl_grp->samples;
2001 for (i = 0; i < 5; i++) {
2002 if (power == samples[i].power) {
2003 *new_index = samples[i].gain_index;
2008 if (power > samples[1].power) {
2011 } else if (power > samples[2].power) {
2014 } else if (power > samples[3].power) {
2022 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2023 if (denominator == 0)
2025 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2026 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2027 res = gains0 + (gains1 - gains0) *
2028 ((s32) power - (s32) samples[index0].power) / denominator +
2030 *new_index = res >> 19;
2034 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2038 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2039 const struct iwl3945_eeprom_txpower_group *group;
2041 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2043 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2044 s8 *clip_pwrs; /* table of power levels for each rate */
2045 s8 satur_pwr; /* saturation power for each chnl group */
2046 group = &eeprom->groups[i];
2048 /* sanity check on factory saturation power value */
2049 if (group->saturation_power < 40) {
2050 IWL_WARN(priv, "Error: saturation power is %d, "
2051 "less than minimum expected 40\n",
2052 group->saturation_power);
2057 * Derive requested power levels for each rate, based on
2058 * hardware capabilities (saturation power for band).
2059 * Basic value is 3dB down from saturation, with further
2060 * power reductions for highest 3 data rates. These
2061 * backoffs provide headroom for high rate modulation
2062 * power peaks, without too much distortion (clipping).
2064 /* we'll fill in this array with h/w max power levels */
2065 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2067 /* divide factory saturation power by 2 to find -3dB level */
2068 satur_pwr = (s8) (group->saturation_power >> 1);
2070 /* fill in channel group's nominal powers for each rate */
2071 for (rate_index = 0;
2072 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2073 switch (rate_index) {
2074 case IWL_RATE_36M_INDEX_TABLE:
2075 if (i == 0) /* B/G */
2076 *clip_pwrs = satur_pwr;
2078 *clip_pwrs = satur_pwr - 5;
2080 case IWL_RATE_48M_INDEX_TABLE:
2082 *clip_pwrs = satur_pwr - 7;
2084 *clip_pwrs = satur_pwr - 10;
2086 case IWL_RATE_54M_INDEX_TABLE:
2088 *clip_pwrs = satur_pwr - 9;
2090 *clip_pwrs = satur_pwr - 12;
2093 *clip_pwrs = satur_pwr;
2101 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2103 * Second pass (during init) to set up priv->channel_info
2105 * Set up Tx-power settings in our channel info database for each VALID
2106 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2107 * and current temperature.
2109 * Since this is based on current temperature (at init time), these values may
2110 * not be valid for very long, but it gives us a starting/default point,
2111 * and allows us to active (i.e. using Tx) scan.
2113 * This does *not* write values to NIC, just sets up our internal table.
2115 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2117 struct iwl_channel_info *ch_info = NULL;
2118 struct iwl3945_channel_power_info *pwr_info;
2119 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2123 const s8 *clip_pwrs; /* array of power levels for each rate */
2126 u8 pwr_index, base_pwr_index, a_band;
2130 /* save temperature reference,
2131 * so we can determine next time to calibrate */
2132 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2133 priv->last_temperature = temperature;
2135 iwl3945_hw_reg_init_channel_groups(priv);
2137 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2138 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2140 a_band = is_channel_a_band(ch_info);
2141 if (!is_channel_valid(ch_info))
2144 /* find this channel's channel group (*not* "band") index */
2145 ch_info->group_index =
2146 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2148 /* Get this chnlgrp's rate->max/clip-powers table */
2149 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2151 /* calculate power index *adjustment* value according to
2152 * diff between current temperature and factory temperature */
2153 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2154 eeprom->groups[ch_info->group_index].
2157 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2158 ch_info->channel, delta_index, temperature +
2161 /* set tx power value for all OFDM rates */
2162 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2164 s32 uninitialized_var(power_idx);
2167 /* use channel group's clip-power table,
2168 * but don't exceed channel's max power */
2169 s8 pwr = min(ch_info->max_power_avg,
2170 clip_pwrs[rate_index]);
2172 pwr_info = &ch_info->power_info[rate_index];
2174 /* get base (i.e. at factory-measured temperature)
2175 * power table index for this rate's power */
2176 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2177 ch_info->group_index,
2180 IWL_ERR(priv, "Invalid power index\n");
2183 pwr_info->base_power_index = (u8) power_idx;
2185 /* temperature compensate */
2186 power_idx += delta_index;
2188 /* stay within range of gain table */
2189 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2191 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2192 pwr_info->requested_power = pwr;
2193 pwr_info->power_table_index = (u8) power_idx;
2194 pwr_info->tpc.tx_gain =
2195 power_gain_table[a_band][power_idx].tx_gain;
2196 pwr_info->tpc.dsp_atten =
2197 power_gain_table[a_band][power_idx].dsp_atten;
2200 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2201 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2202 power = pwr_info->requested_power +
2203 IWL_CCK_FROM_OFDM_POWER_DIFF;
2204 pwr_index = pwr_info->power_table_index +
2205 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2206 base_pwr_index = pwr_info->base_power_index +
2207 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2209 /* stay within table range */
2210 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2211 gain = power_gain_table[a_band][pwr_index].tx_gain;
2212 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2214 /* fill each CCK rate's iwl3945_channel_power_info structure
2215 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2216 * NOTE: CCK rates start at end of OFDM rates! */
2217 for (rate_index = 0;
2218 rate_index < IWL_CCK_RATES; rate_index++) {
2219 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2220 pwr_info->requested_power = power;
2221 pwr_info->power_table_index = pwr_index;
2222 pwr_info->base_power_index = base_pwr_index;
2223 pwr_info->tpc.tx_gain = gain;
2224 pwr_info->tpc.dsp_atten = dsp_atten;
2227 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2228 for (scan_tbl_index = 0;
2229 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2230 s32 actual_index = (scan_tbl_index == 0) ?
2231 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2232 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2233 actual_index, clip_pwrs, ch_info, a_band);
2240 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2244 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2245 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2246 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2248 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2253 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2255 int txq_id = txq->q.id;
2257 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2259 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2261 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2262 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2264 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2265 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2266 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2267 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2268 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2269 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2271 /* fake read to flush all prev. writes */
2272 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2280 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2284 return sizeof(struct iwl3945_rxon_cmd);
2285 case POWER_TABLE_CMD:
2286 return sizeof(struct iwl3945_powertable_cmd);
2293 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2295 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2296 addsta->mode = cmd->mode;
2297 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2298 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2299 addsta->station_flags = cmd->station_flags;
2300 addsta->station_flags_msk = cmd->station_flags_msk;
2301 addsta->tid_disable_tx = cpu_to_le16(0);
2302 addsta->rate_n_flags = cmd->rate_n_flags;
2303 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2304 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2305 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2307 return (u16)sizeof(struct iwl3945_addsta_cmd);
2310 static int iwl3945_add_bssid_station(struct iwl_priv *priv,
2311 const u8 *addr, u8 *sta_id_r)
2313 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2316 unsigned long flags;
2319 *sta_id_r = IWL_INVALID_STATION;
2321 ret = iwl_add_station_common(priv, ctx, addr, 0, NULL, &sta_id);
2323 IWL_ERR(priv, "Unable to add station %pM\n", addr);
2330 spin_lock_irqsave(&priv->sta_lock, flags);
2331 priv->stations[sta_id].used |= IWL_STA_LOCAL;
2332 spin_unlock_irqrestore(&priv->sta_lock, flags);
2336 static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2337 struct ieee80211_vif *vif, bool add)
2339 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2343 ret = iwl3945_add_bssid_station(priv, vif->bss_conf.bssid,
2344 &vif_priv->ibss_bssid_sta_id);
2348 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
2349 (priv->band == IEEE80211_BAND_5GHZ) ?
2350 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
2351 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
2356 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2357 vif->bss_conf.bssid);
2361 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2363 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2365 int rc, i, index, prev_index;
2366 struct iwl3945_rate_scaling_cmd rate_cmd = {
2367 .reserved = {0, 0, 0},
2369 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2371 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2372 index = iwl3945_rates[i].table_rs_index;
2374 table[index].rate_n_flags =
2375 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2376 table[index].try_cnt = priv->retry_rate;
2377 prev_index = iwl3945_get_prev_ieee_rate(i);
2378 table[index].next_rate_index =
2379 iwl3945_rates[prev_index].table_rs_index;
2382 switch (priv->band) {
2383 case IEEE80211_BAND_5GHZ:
2384 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2385 /* If one of the following CCK rates is used,
2386 * have it fall back to the 6M OFDM rate */
2387 for (i = IWL_RATE_1M_INDEX_TABLE;
2388 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2389 table[i].next_rate_index =
2390 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2392 /* Don't fall back to CCK rates */
2393 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2394 IWL_RATE_9M_INDEX_TABLE;
2396 /* Don't drop out of OFDM rates */
2397 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2398 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2401 case IEEE80211_BAND_2GHZ:
2402 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2403 /* If an OFDM rate is used, have it fall back to the
2406 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2407 iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
2409 index = IWL_FIRST_CCK_RATE;
2410 for (i = IWL_RATE_6M_INDEX_TABLE;
2411 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2412 table[i].next_rate_index =
2413 iwl3945_rates[index].table_rs_index;
2415 index = IWL_RATE_11M_INDEX_TABLE;
2416 /* CCK shouldn't fall back to OFDM... */
2417 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2426 /* Update the rate scaling for control frame Tx */
2427 rate_cmd.table_id = 0;
2428 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2433 /* Update the rate scaling for data frame Tx */
2434 rate_cmd.table_id = 1;
2435 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2439 /* Called when initializing driver */
2440 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2442 memset((void *)&priv->hw_params, 0,
2443 sizeof(struct iwl_hw_params));
2445 priv->_3945.shared_virt =
2446 dma_alloc_coherent(&priv->pci_dev->dev,
2447 sizeof(struct iwl3945_shared),
2448 &priv->_3945.shared_phys, GFP_KERNEL);
2449 if (!priv->_3945.shared_virt) {
2450 IWL_ERR(priv, "failed to allocate pci memory\n");
2454 /* Assign number of Usable TX queues */
2455 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
2457 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2458 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2459 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2460 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2461 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2462 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id = IWL3945_BROADCAST_ID;
2464 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2466 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2467 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2468 priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS;
2473 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2474 struct iwl3945_frame *frame, u8 rate)
2476 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2477 unsigned int frame_size;
2479 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2480 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2482 tx_beacon_cmd->tx.sta_id =
2483 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
2484 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2486 frame_size = iwl3945_fill_beacon_frame(priv,
2487 tx_beacon_cmd->frame,
2488 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2490 BUG_ON(frame_size > MAX_MPDU_SIZE);
2491 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2493 tx_beacon_cmd->tx.rate = rate;
2494 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2495 TX_CMD_FLG_TSF_MSK);
2497 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2498 tx_beacon_cmd->tx.supp_rates[0] =
2499 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2501 tx_beacon_cmd->tx.supp_rates[1] =
2502 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2504 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2507 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2509 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2510 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2513 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2515 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2516 iwl3945_bg_reg_txpower_periodic);
2519 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2521 cancel_delayed_work(&priv->_3945.thermal_periodic);
2524 /* check contents of special bootstrap uCode SRAM */
2525 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2527 __le32 *image = priv->ucode_boot.v_addr;
2528 u32 len = priv->ucode_boot.len;
2532 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2534 /* verify BSM SRAM contents */
2535 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2536 for (reg = BSM_SRAM_LOWER_BOUND;
2537 reg < BSM_SRAM_LOWER_BOUND + len;
2538 reg += sizeof(u32), image++) {
2539 val = iwl_read_prph(priv, reg);
2540 if (val != le32_to_cpu(*image)) {
2541 IWL_ERR(priv, "BSM uCode verification failed at "
2542 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2543 BSM_SRAM_LOWER_BOUND,
2544 reg - BSM_SRAM_LOWER_BOUND, len,
2545 val, le32_to_cpu(*image));
2550 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2556 /******************************************************************************
2558 * EEPROM related functions
2560 ******************************************************************************/
2563 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2564 * embedded controller) as EEPROM reader; each read is a series of pulses
2565 * to/from the EEPROM chip, not a single event, so even reads could conflict
2566 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2567 * simply claims ownership, which should be safe when this function is called
2568 * (i.e. before loading uCode!).
2570 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2572 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2577 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2583 * iwl3945_load_bsm - Load bootstrap instructions
2587 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2588 * in special SRAM that does not power down during RFKILL. When powering back
2589 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2590 * the bootstrap program into the on-board processor, and starts it.
2592 * The bootstrap program loads (via DMA) instructions and data for a new
2593 * program from host DRAM locations indicated by the host driver in the
2594 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2597 * When initializing the NIC, the host driver points the BSM to the
2598 * "initialize" uCode image. This uCode sets up some internal data, then
2599 * notifies host via "initialize alive" that it is complete.
2601 * The host then replaces the BSM_DRAM_* pointer values to point to the
2602 * normal runtime uCode instructions and a backup uCode data cache buffer
2603 * (filled initially with starting data values for the on-board processor),
2604 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2605 * which begins normal operation.
2607 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2608 * the backup data cache in DRAM before SRAM is powered down.
2610 * When powering back up, the BSM loads the bootstrap program. This reloads
2611 * the runtime uCode instructions and the backup data cache into SRAM,
2612 * and re-launches the runtime uCode from where it left off.
2614 static int iwl3945_load_bsm(struct iwl_priv *priv)
2616 __le32 *image = priv->ucode_boot.v_addr;
2617 u32 len = priv->ucode_boot.len;
2627 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2629 /* make sure bootstrap program is no larger than BSM's SRAM size */
2630 if (len > IWL39_MAX_BSM_SIZE)
2633 /* Tell bootstrap uCode where to find the "Initialize" uCode
2634 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2635 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2636 * after the "initialize" uCode has run, to point to
2637 * runtime/protocol instructions and backup data cache. */
2638 pinst = priv->ucode_init.p_addr;
2639 pdata = priv->ucode_init_data.p_addr;
2640 inst_len = priv->ucode_init.len;
2641 data_len = priv->ucode_init_data.len;
2643 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2644 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2645 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2646 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2648 /* Fill BSM memory with bootstrap instructions */
2649 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2650 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2651 reg_offset += sizeof(u32), image++)
2652 _iwl_write_prph(priv, reg_offset,
2653 le32_to_cpu(*image));
2655 rc = iwl3945_verify_bsm(priv);
2659 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2660 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2661 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2662 IWL39_RTC_INST_LOWER_BOUND);
2663 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2665 /* Load bootstrap code into instruction SRAM now,
2666 * to prepare to load "initialize" uCode */
2667 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2668 BSM_WR_CTRL_REG_BIT_START);
2670 /* Wait for load of bootstrap uCode to finish */
2671 for (i = 0; i < 100; i++) {
2672 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2673 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2678 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2680 IWL_ERR(priv, "BSM write did not complete!\n");
2684 /* Enable future boot loads whenever power management unit triggers it
2685 * (e.g. when powering back up after power-save shutdown) */
2686 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2687 BSM_WR_CTRL_REG_BIT_START_EN);
2692 static struct iwl_hcmd_ops iwl3945_hcmd = {
2693 .rxon_assoc = iwl3945_send_rxon_assoc,
2694 .commit_rxon = iwl3945_commit_rxon,
2695 .send_bt_config = iwl_send_bt_config,
2698 static struct iwl_lib_ops iwl3945_lib = {
2699 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2700 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2701 .txq_init = iwl3945_hw_tx_queue_init,
2702 .load_ucode = iwl3945_load_bsm,
2703 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2704 .dump_nic_error_log = iwl3945_dump_nic_error_log,
2706 .init = iwl3945_apm_init,
2707 .config = iwl3945_nic_config,
2710 .regulatory_bands = {
2711 EEPROM_REGULATORY_BAND_1_CHANNELS,
2712 EEPROM_REGULATORY_BAND_2_CHANNELS,
2713 EEPROM_REGULATORY_BAND_3_CHANNELS,
2714 EEPROM_REGULATORY_BAND_4_CHANNELS,
2715 EEPROM_REGULATORY_BAND_5_CHANNELS,
2716 EEPROM_REGULATORY_BAND_NO_HT40,
2717 EEPROM_REGULATORY_BAND_NO_HT40,
2719 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2720 .release_semaphore = iwl3945_eeprom_release_semaphore,
2721 .query_addr = iwlcore_eeprom_query_addr,
2723 .send_tx_power = iwl3945_send_tx_power,
2724 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2725 .post_associate = iwl3945_post_associate,
2726 .isr = iwl_isr_legacy,
2727 .config_ap = iwl3945_config_ap,
2728 .manage_ibss_station = iwl3945_manage_ibss_station,
2729 .recover_from_tx_stall = iwl_bg_monitor_recover,
2730 .check_plcp_health = iwl3945_good_plcp_health,
2733 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2734 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2735 .general_stats_read = iwl3945_ucode_general_stats_read,
2739 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2740 .get_hcmd_size = iwl3945_get_hcmd_size,
2741 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2742 .tx_cmd_protection = iwlcore_tx_cmd_protection,
2743 .request_scan = iwl3945_request_scan,
2744 .post_scan = iwl3945_post_scan,
2747 static const struct iwl_ops iwl3945_ops = {
2748 .lib = &iwl3945_lib,
2749 .hcmd = &iwl3945_hcmd,
2750 .utils = &iwl3945_hcmd_utils,
2751 .led = &iwl3945_led_ops,
2754 static struct iwl_base_params iwl3945_base_params = {
2755 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2756 .num_of_queues = IWL39_NUM_QUEUES,
2757 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2760 .use_isr_legacy = true,
2761 .led_compensation = 64,
2762 .broken_powersave = true,
2763 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2764 .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
2765 .max_event_log_size = 512,
2766 .tx_power_by_driver = true,
2769 static struct iwl_cfg iwl3945_bg_cfg = {
2771 .fw_name_pre = IWL3945_FW_PRE,
2772 .ucode_api_max = IWL3945_UCODE_API_MAX,
2773 .ucode_api_min = IWL3945_UCODE_API_MIN,
2775 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2776 .ops = &iwl3945_ops,
2777 .mod_params = &iwl3945_mod_params,
2778 .base_params = &iwl3945_base_params,
2781 static struct iwl_cfg iwl3945_abg_cfg = {
2783 .fw_name_pre = IWL3945_FW_PRE,
2784 .ucode_api_max = IWL3945_UCODE_API_MAX,
2785 .ucode_api_min = IWL3945_UCODE_API_MIN,
2786 .sku = IWL_SKU_A|IWL_SKU_G,
2787 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2788 .ops = &iwl3945_ops,
2789 .mod_params = &iwl3945_mod_params,
2790 .base_params = &iwl3945_base_params,
2793 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2794 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2795 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2796 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2797 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2798 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2799 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2803 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);