drivers/net/wireless/ath5k/base.c

   1 /*-
   2  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2004-2005 Atheros Communications, Inc.
   4  * Copyright (c) 2006 Devicescape Software, Inc.
   5  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
   6  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
   7  *
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18  *    redistribution must be conditioned upon including a substantially
  19  *    similar Disclaimer requirement for further binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39  * THE POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  */
  42
  43 #include <linux/module.h>
  44 #include <linux/delay.h>
  45 #include <linux/hardirq.h>
  46 #include <linux/if.h>
  47 #include <linux/io.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/cache.h>
  50 #include <linux/pci.h>
  51 #include <linux/ethtool.h>
  52 #include <linux/uaccess.h>
  53
  54 #include <net/ieee80211_radiotap.h>
  55
  56 #include <asm/unaligned.h>
  57
  58 #include "base.h"
  59 #include "reg.h"
  60 #include "debug.h"
  61
  62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
  63 static int modparam_nohwcrypt;
  64 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  66
  67
  68 /******************\
  69 * Internal defines *
  70 \******************/
  71
  72 /* Module info */
  73 MODULE_AUTHOR("Jiri Slaby");
  74 MODULE_AUTHOR("Nick Kossifidis");
  75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  77 MODULE_LICENSE("Dual BSD/GPL");
  78 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
  79
  80
  81 /* Known PCI ids */
  82 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
  83         { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
  84         { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
  85         { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
  86         { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
  87         { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
  88         { PCI_VDEVICE(3COM_2,  0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
  89         { PCI_VDEVICE(3COM,    0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
  90         { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
  91         { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  92         { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  93         { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  94         { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  95         { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  96         { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  97         { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
  98         { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
  99         { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
 100         { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
 101         { 0 }
 102 };
 103 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
 104
 105 /* Known SREVs */
 106 static struct ath5k_srev_name srev_names[] = {
 107         { "5210",       AR5K_VERSION_MAC,       AR5K_SREV_AR5210 },
 108         { "5311",       AR5K_VERSION_MAC,       AR5K_SREV_AR5311 },
 109         { "5311A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311A },
 110         { "5311B",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311B },
 111         { "5211",       AR5K_VERSION_MAC,       AR5K_SREV_AR5211 },
 112         { "5212",       AR5K_VERSION_MAC,       AR5K_SREV_AR5212 },
 113         { "5213",       AR5K_VERSION_MAC,       AR5K_SREV_AR5213 },
 114         { "5213A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5213A },
 115         { "2413",       AR5K_VERSION_MAC,       AR5K_SREV_AR2413 },
 116         { "2414",       AR5K_VERSION_MAC,       AR5K_SREV_AR2414 },
 117         { "5424",       AR5K_VERSION_MAC,       AR5K_SREV_AR5424 },
 118         { "5413",       AR5K_VERSION_MAC,       AR5K_SREV_AR5413 },
 119         { "5414",       AR5K_VERSION_MAC,       AR5K_SREV_AR5414 },
 120         { "2415",       AR5K_VERSION_MAC,       AR5K_SREV_AR2415 },
 121         { "5416",       AR5K_VERSION_MAC,       AR5K_SREV_AR5416 },
 122         { "5418",       AR5K_VERSION_MAC,       AR5K_SREV_AR5418 },
 123         { "2425",       AR5K_VERSION_MAC,       AR5K_SREV_AR2425 },
 124         { "2417",       AR5K_VERSION_MAC,       AR5K_SREV_AR2417 },
 125         { "xxxxx",      AR5K_VERSION_MAC,       AR5K_SREV_UNKNOWN },
 126         { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
 127         { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
 128         { "5111A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111A },
 129         { "2111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2111 },
 130         { "5112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112 },
 131         { "5112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112A },
 132         { "5112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112B },
 133         { "2112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112 },
 134         { "2112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112A },
 135         { "2112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112B },
 136         { "2413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2413 },
 137         { "5413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5413 },
 138         { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
 139         { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
 140         { "5424",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5424 },
 141         { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
 142         { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
 143 };
 144
 145 static struct ieee80211_rate ath5k_rates[] = {
 146         { .bitrate = 10,
 147           .hw_value = ATH5K_RATE_CODE_1M, },
 148         { .bitrate = 20,
 149           .hw_value = ATH5K_RATE_CODE_2M,
 150           .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
 151           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 152         { .bitrate = 55,
 153           .hw_value = ATH5K_RATE_CODE_5_5M,
 154           .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
 155           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 156         { .bitrate = 110,
 157           .hw_value = ATH5K_RATE_CODE_11M,
 158           .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
 159           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 160         { .bitrate = 60,
 161           .hw_value = ATH5K_RATE_CODE_6M,
 162           .flags = 0 },
 163         { .bitrate = 90,
 164           .hw_value = ATH5K_RATE_CODE_9M,
 165           .flags = 0 },
 166         { .bitrate = 120,
 167           .hw_value = ATH5K_RATE_CODE_12M,
 168           .flags = 0 },
 169         { .bitrate = 180,
 170           .hw_value = ATH5K_RATE_CODE_18M,
 171           .flags = 0 },
 172         { .bitrate = 240,
 173           .hw_value = ATH5K_RATE_CODE_24M,
 174           .flags = 0 },
 175         { .bitrate = 360,
 176           .hw_value = ATH5K_RATE_CODE_36M,
 177           .flags = 0 },
 178         { .bitrate = 480,
 179           .hw_value = ATH5K_RATE_CODE_48M,
 180           .flags = 0 },
 181         { .bitrate = 540,
 182           .hw_value = ATH5K_RATE_CODE_54M,
 183           .flags = 0 },
 184         /* XR missing */
 185 };
 186
 187 /*
 188  * Prototypes - PCI stack related functions
 189  */
 190 static int __devinit    ath5k_pci_probe(struct pci_dev *pdev,
 191                                 const struct pci_device_id *id);
 192 static void __devexit   ath5k_pci_remove(struct pci_dev *pdev);
 193 #ifdef CONFIG_PM
 194 static int              ath5k_pci_suspend(struct pci_dev *pdev,
 195                                         pm_message_t state);
 196 static int              ath5k_pci_resume(struct pci_dev *pdev);
 197 #else
 198 #define ath5k_pci_suspend NULL
 199 #define ath5k_pci_resume NULL
 200 #endif /* CONFIG_PM */
 201
 202 static struct pci_driver ath5k_pci_driver = {
 203         .name           = KBUILD_MODNAME,
 204         .id_table       = ath5k_pci_id_table,
 205         .probe          = ath5k_pci_probe,
 206         .remove         = __devexit_p(ath5k_pci_remove),
 207         .suspend        = ath5k_pci_suspend,
 208         .resume         = ath5k_pci_resume,
 209 };
 210
 211
 212
 213 /*
 214  * Prototypes - MAC 802.11 stack related functions
 215  */
 216 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
 217 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
 218 static int ath5k_reset_wake(struct ath5k_softc *sc);
 219 static int ath5k_start(struct ieee80211_hw *hw);
 220 static void ath5k_stop(struct ieee80211_hw *hw);
 221 static int ath5k_add_interface(struct ieee80211_hw *hw,
 222                 struct ieee80211_if_init_conf *conf);
 223 static void ath5k_remove_interface(struct ieee80211_hw *hw,
 224                 struct ieee80211_if_init_conf *conf);
 225 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
 226 static int ath5k_config_interface(struct ieee80211_hw *hw,
 227                 struct ieee80211_vif *vif,
 228                 struct ieee80211_if_conf *conf);
 229 static void ath5k_configure_filter(struct ieee80211_hw *hw,
 230                 unsigned int changed_flags,
 231                 unsigned int *new_flags,
 232                 int mc_count, struct dev_mc_list *mclist);
 233 static int ath5k_set_key(struct ieee80211_hw *hw,
 234                 enum set_key_cmd cmd,
 235                 const u8 *local_addr, const u8 *addr,
 236                 struct ieee80211_key_conf *key);
 237 static int ath5k_get_stats(struct ieee80211_hw *hw,
 238                 struct ieee80211_low_level_stats *stats);
 239 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
 240                 struct ieee80211_tx_queue_stats *stats);
 241 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
 242 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
 243 static int ath5k_beacon_update(struct ath5k_softc *sc,
 244                 struct sk_buff *skb);
 245 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
 246                 struct ieee80211_vif *vif,
 247                 struct ieee80211_bss_conf *bss_conf,
 248                 u32 changes);
 249
 250 static struct ieee80211_ops ath5k_hw_ops = {
 251         .tx             = ath5k_tx,
 252         .start          = ath5k_start,
 253         .stop           = ath5k_stop,
 254         .add_interface  = ath5k_add_interface,
 255         .remove_interface = ath5k_remove_interface,
 256         .config         = ath5k_config,
 257         .config_interface = ath5k_config_interface,
 258         .configure_filter = ath5k_configure_filter,
 259         .set_key        = ath5k_set_key,
 260         .get_stats      = ath5k_get_stats,
 261         .conf_tx        = NULL,
 262         .get_tx_stats   = ath5k_get_tx_stats,
 263         .get_tsf        = ath5k_get_tsf,
 264         .reset_tsf      = ath5k_reset_tsf,
 265         .bss_info_changed = ath5k_bss_info_changed,
 266 };
 267
 268 /*
 269  * Prototypes - Internal functions
 270  */
 271 /* Attach detach */
 272 static int      ath5k_attach(struct pci_dev *pdev,
 273                         struct ieee80211_hw *hw);
 274 static void     ath5k_detach(struct pci_dev *pdev,
 275                         struct ieee80211_hw *hw);
 276 /* Channel/mode setup */
 277 static inline short ath5k_ieee2mhz(short chan);
 278 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
 279                                 struct ieee80211_channel *channels,
 280                                 unsigned int mode,
 281                                 unsigned int max);
 282 static int      ath5k_setup_bands(struct ieee80211_hw *hw);
 283 static int      ath5k_chan_set(struct ath5k_softc *sc,
 284                                 struct ieee80211_channel *chan);
 285 static void     ath5k_setcurmode(struct ath5k_softc *sc,
 286                                 unsigned int mode);
 287 static void     ath5k_mode_setup(struct ath5k_softc *sc);
 288
 289 /* Descriptor setup */
 290 static int      ath5k_desc_alloc(struct ath5k_softc *sc,
 291                                 struct pci_dev *pdev);
 292 static void     ath5k_desc_free(struct ath5k_softc *sc,
 293                                 struct pci_dev *pdev);
 294 /* Buffers setup */
 295 static int      ath5k_rxbuf_setup(struct ath5k_softc *sc,
 296                                 struct ath5k_buf *bf);
 297 static int      ath5k_txbuf_setup(struct ath5k_softc *sc,
 298                                 struct ath5k_buf *bf);
 299 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
 300                                 struct ath5k_buf *bf)
 301 {
 302         BUG_ON(!bf);
 303         if (!bf->skb)
 304                 return;
 305         pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
 306                         PCI_DMA_TODEVICE);
 307         dev_kfree_skb_any(bf->skb);
 308         bf->skb = NULL;
 309 }
 310
 311 /* Queues setup */
 312 static struct   ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
 313                                 int qtype, int subtype);
 314 static int      ath5k_beaconq_setup(struct ath5k_hw *ah);
 315 static int      ath5k_beaconq_config(struct ath5k_softc *sc);
 316 static void     ath5k_txq_drainq(struct ath5k_softc *sc,
 317                                 struct ath5k_txq *txq);
 318 static void     ath5k_txq_cleanup(struct ath5k_softc *sc);
 319 static void     ath5k_txq_release(struct ath5k_softc *sc);
 320 /* Rx handling */
 321 static int      ath5k_rx_start(struct ath5k_softc *sc);
 322 static void     ath5k_rx_stop(struct ath5k_softc *sc);
 323 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
 324                                         struct ath5k_desc *ds,
 325                                         struct sk_buff *skb,
 326                                         struct ath5k_rx_status *rs);
 327 static void     ath5k_tasklet_rx(unsigned long data);
 328 /* Tx handling */
 329 static void     ath5k_tx_processq(struct ath5k_softc *sc,
 330                                 struct ath5k_txq *txq);
 331 static void     ath5k_tasklet_tx(unsigned long data);
 332 /* Beacon handling */
 333 static int      ath5k_beacon_setup(struct ath5k_softc *sc,
 334                                         struct ath5k_buf *bf);
 335 static void     ath5k_beacon_send(struct ath5k_softc *sc);
 336 static void     ath5k_beacon_config(struct ath5k_softc *sc);
 337 static void     ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
 338
 339 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
 340 {
 341         u64 tsf = ath5k_hw_get_tsf64(ah);
 342
 343         if ((tsf & 0x7fff) < rstamp)
 344                 tsf -= 0x8000;
 345
 346         return (tsf & ~0x7fff) | rstamp;
 347 }
 348
 349 /* Interrupt handling */
 350 static int      ath5k_init(struct ath5k_softc *sc, bool is_resume);
 351 static int      ath5k_stop_locked(struct ath5k_softc *sc);
 352 static int      ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend);
 353 static irqreturn_t ath5k_intr(int irq, void *dev_id);
 354 static void     ath5k_tasklet_reset(unsigned long data);
 355
 356 static void     ath5k_calibrate(unsigned long data);
 357 /* LED functions */
 358 static int      ath5k_init_leds(struct ath5k_softc *sc);
 359 static void     ath5k_led_enable(struct ath5k_softc *sc);
 360 static void     ath5k_led_off(struct ath5k_softc *sc);
 361 static void     ath5k_unregister_leds(struct ath5k_softc *sc);
 362
 363 /*
 364  * Module init/exit functions
 365  */
 366 static int __init
 367 init_ath5k_pci(void)
 368 {
 369         int ret;
 370
 371         ath5k_debug_init();
 372
 373         ret = pci_register_driver(&ath5k_pci_driver);
 374         if (ret) {
 375                 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
 376                 return ret;
 377         }
 378
 379         return 0;
 380 }
 381
 382 static void __exit
 383 exit_ath5k_pci(void)
 384 {
 385         pci_unregister_driver(&ath5k_pci_driver);
 386
 387         ath5k_debug_finish();
 388 }
 389
 390 module_init(init_ath5k_pci);
 391 module_exit(exit_ath5k_pci);
 392
 393
 394 /********************\
 395 * PCI Initialization *
 396 \********************/
 397
 398 static const char *
 399 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
 400 {
 401         const char *name = "xxxxx";
 402         unsigned int i;
 403
 404         for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
 405                 if (srev_names[i].sr_type != type)
 406                         continue;
 407
 408                 if ((val & 0xf0) == srev_names[i].sr_val)
 409                         name = srev_names[i].sr_name;
 410
 411                 if ((val & 0xff) == srev_names[i].sr_val) {
 412                         name = srev_names[i].sr_name;
 413                         break;
 414                 }
 415         }
 416
 417         return name;
 418 }
 419
 420 static int __devinit
 421 ath5k_pci_probe(struct pci_dev *pdev,
 422                 const struct pci_device_id *id)
 423 {
 424         void __iomem *mem;
 425         struct ath5k_softc *sc;
 426         struct ieee80211_hw *hw;
 427         int ret;
 428         u8 csz;
 429
 430         ret = pci_enable_device(pdev);
 431         if (ret) {
 432                 dev_err(&pdev->dev, "can't enable device\n");
 433                 goto err;
 434         }
 435
 436         /* XXX 32-bit addressing only */
 437         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 438         if (ret) {
 439                 dev_err(&pdev->dev, "32-bit DMA not available\n");
 440                 goto err_dis;
 441         }
 442
 443         /*
 444          * Cache line size is used to size and align various
 445          * structures used to communicate with the hardware.
 446          */
 447         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 448         if (csz == 0) {
 449                 /*
 450                  * Linux 2.4.18 (at least) writes the cache line size
 451                  * register as a 16-bit wide register which is wrong.
 452                  * We must have this setup properly for rx buffer
 453                  * DMA to work so force a reasonable value here if it
 454                  * comes up zero.
 455                  */
 456                 csz = L1_CACHE_BYTES / sizeof(u32);
 457                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 458         }
 459         /*
 460          * The default setting of latency timer yields poor results,
 461          * set it to the value used by other systems.  It may be worth
 462          * tweaking this setting more.
 463          */
 464         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 465
 466         /* Enable bus mastering */
 467         pci_set_master(pdev);
 468
 469         /*
 470          * Disable the RETRY_TIMEOUT register (0x41) to keep
 471          * PCI Tx retries from interfering with C3 CPU state.
 472          */
 473         pci_write_config_byte(pdev, 0x41, 0);
 474
 475         ret = pci_request_region(pdev, 0, "ath5k");
 476         if (ret) {
 477                 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
 478                 goto err_dis;
 479         }
 480
 481         mem = pci_iomap(pdev, 0, 0);
 482         if (!mem) {
 483                 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
 484                 ret = -EIO;
 485                 goto err_reg;
 486         }
 487
 488         /*
 489          * Allocate hw (mac80211 main struct)
 490          * and hw->priv (driver private data)
 491          */
 492         hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
 493         if (hw == NULL) {
 494                 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
 495                 ret = -ENOMEM;
 496                 goto err_map;
 497         }
 498
 499         dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
 500
 501         /* Initialize driver private data */
 502         SET_IEEE80211_DEV(hw, &pdev->dev);
 503         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
 504                     IEEE80211_HW_SIGNAL_DBM |
 505                     IEEE80211_HW_NOISE_DBM;
 506
 507         hw->wiphy->interface_modes =
 508                 BIT(NL80211_IFTYPE_STATION) |
 509                 BIT(NL80211_IFTYPE_ADHOC) |
 510                 BIT(NL80211_IFTYPE_MESH_POINT);
 511
 512         hw->extra_tx_headroom = 2;
 513         hw->channel_change_time = 5000;
 514         sc = hw->priv;
 515         sc->hw = hw;
 516         sc->pdev = pdev;
 517
 518         ath5k_debug_init_device(sc);
 519
 520         /*
 521          * Mark the device as detached to avoid processing
 522          * interrupts until setup is complete.
 523          */
 524         __set_bit(ATH_STAT_INVALID, sc->status);
 525
 526         sc->iobase = mem; /* So we can unmap it on detach */
 527         sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
 528         sc->opmode = NL80211_IFTYPE_STATION;
 529         mutex_init(&sc->lock);
 530         spin_lock_init(&sc->rxbuflock);
 531         spin_lock_init(&sc->txbuflock);
 532         spin_lock_init(&sc->block);
 533
 534         /* Set private data */
 535         pci_set_drvdata(pdev, hw);
 536
 537         /* Setup interrupt handler */
 538         ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 539         if (ret) {
 540                 ATH5K_ERR(sc, "request_irq failed\n");
 541                 goto err_free;
 542         }
 543
 544         /* Initialize device */
 545         sc->ah = ath5k_hw_attach(sc, id->driver_data);
 546         if (IS_ERR(sc->ah)) {
 547                 ret = PTR_ERR(sc->ah);
 548                 goto err_irq;
 549         }
 550
 551         /* set up multi-rate retry capabilities */
 552         if (sc->ah->ah_version == AR5K_AR5212) {
 553                 hw->max_rates = 4;
 554                 hw->max_rate_tries = 11;
 555         }
 556
 557         /* Finish private driver data initialization */
 558         ret = ath5k_attach(pdev, hw);
 559         if (ret)
 560                 goto err_ah;
 561
 562         ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
 563                         ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
 564                                         sc->ah->ah_mac_srev,
 565                                         sc->ah->ah_phy_revision);
 566
 567         if (!sc->ah->ah_single_chip) {
 568                 /* Single chip radio (!RF5111) */
 569                 if (sc->ah->ah_radio_5ghz_revision &&
 570                         !sc->ah->ah_radio_2ghz_revision) {
 571                         /* No 5GHz support -> report 2GHz radio */
 572                         if (!test_bit(AR5K_MODE_11A,
 573                                 sc->ah->ah_capabilities.cap_mode)) {
 574                                 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 575                                         ath5k_chip_name(AR5K_VERSION_RAD,
 576                                                 sc->ah->ah_radio_5ghz_revision),
 577                                                 sc->ah->ah_radio_5ghz_revision);
 578                         /* No 2GHz support (5110 and some
 579                          * 5Ghz only cards) -> report 5Ghz radio */
 580                         } else if (!test_bit(AR5K_MODE_11B,
 581                                 sc->ah->ah_capabilities.cap_mode)) {
 582                                 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 583                                         ath5k_chip_name(AR5K_VERSION_RAD,
 584                                                 sc->ah->ah_radio_5ghz_revision),
 585                                                 sc->ah->ah_radio_5ghz_revision);
 586                         /* Multiband radio */
 587                         } else {
 588                                 ATH5K_INFO(sc, "RF%s multiband radio found"
 589                                         " (0x%x)\n",
 590                                         ath5k_chip_name(AR5K_VERSION_RAD,
 591                                                 sc->ah->ah_radio_5ghz_revision),
 592                                                 sc->ah->ah_radio_5ghz_revision);
 593                         }
 594                 }
 595                 /* Multi chip radio (RF5111 - RF2111) ->
 596                  * report both 2GHz/5GHz radios */
 597                 else if (sc->ah->ah_radio_5ghz_revision &&
 598                                 sc->ah->ah_radio_2ghz_revision){
 599                         ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 600                                 ath5k_chip_name(AR5K_VERSION_RAD,
 601                                         sc->ah->ah_radio_5ghz_revision),
 602                                         sc->ah->ah_radio_5ghz_revision);
 603                         ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 604                                 ath5k_chip_name(AR5K_VERSION_RAD,
 605                                         sc->ah->ah_radio_2ghz_revision),
 606                                         sc->ah->ah_radio_2ghz_revision);
 607                 }
 608         }
 609
 610
 611         /* ready to process interrupts */
 612         __clear_bit(ATH_STAT_INVALID, sc->status);
 613
 614         return 0;
 615 err_ah:
 616         ath5k_hw_detach(sc->ah);
 617 err_irq:
 618         free_irq(pdev->irq, sc);
 619 err_free:
 620         ieee80211_free_hw(hw);
 621 err_map:
 622         pci_iounmap(pdev, mem);
 623 err_reg:
 624         pci_release_region(pdev, 0);
 625 err_dis:
 626         pci_disable_device(pdev);
 627 err:
 628         return ret;
 629 }
 630
 631 static void __devexit
 632 ath5k_pci_remove(struct pci_dev *pdev)
 633 {
 634         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 635         struct ath5k_softc *sc = hw->priv;
 636
 637         ath5k_debug_finish_device(sc);
 638         ath5k_detach(pdev, hw);
 639         ath5k_hw_detach(sc->ah);
 640         free_irq(pdev->irq, sc);
 641         pci_iounmap(pdev, sc->iobase);
 642         pci_release_region(pdev, 0);
 643         pci_disable_device(pdev);
 644         ieee80211_free_hw(hw);
 645 }
 646
 647 #ifdef CONFIG_PM
 648 static int
 649 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 650 {
 651         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 652         struct ath5k_softc *sc = hw->priv;
 653
 654         ath5k_led_off(sc);
 655
 656         ath5k_stop_hw(sc, true);
 657
 658         free_irq(pdev->irq, sc);
 659         pci_save_state(pdev);
 660         pci_disable_device(pdev);
 661         pci_set_power_state(pdev, PCI_D3hot);
 662
 663         return 0;
 664 }
 665
 666 static int
 667 ath5k_pci_resume(struct pci_dev *pdev)
 668 {
 669         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 670         struct ath5k_softc *sc = hw->priv;
 671         int err;
 672
 673         pci_restore_state(pdev);
 674
 675         err = pci_enable_device(pdev);
 676         if (err)
 677                 return err;
 678
 679         /*
 680          * Suspend/Resume resets the PCI configuration space, so we have to
 681          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 682          * PCI Tx retries from interfering with C3 CPU state
 683          */
 684         pci_write_config_byte(pdev, 0x41, 0);
 685
 686         err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 687         if (err) {
 688                 ATH5K_ERR(sc, "request_irq failed\n");
 689                 goto err_no_irq;
 690         }
 691
 692         err = ath5k_init(sc, true);
 693         if (err)
 694                 goto err_irq;
 695         ath5k_led_enable(sc);
 696
 697         return 0;
 698 err_irq:
 699         free_irq(pdev->irq, sc);
 700 err_no_irq:
 701         pci_disable_device(pdev);
 702         return err;
 703 }
 704 #endif /* CONFIG_PM */
 705
 706
 707 /***********************\
 708 * Driver Initialization *
 709 \***********************/
 710
 711 static int
 712 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 713 {
 714         struct ath5k_softc *sc = hw->priv;
 715         struct ath5k_hw *ah = sc->ah;
 716         u8 mac[ETH_ALEN] = {};
 717         int ret;
 718
 719         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
 720
 721         /*
 722          * Check if the MAC has multi-rate retry support.
 723          * We do this by trying to setup a fake extended
 724          * descriptor.  MAC's that don't have support will
 725          * return false w/o doing anything.  MAC's that do
 726          * support it will return true w/o doing anything.
 727          */
 728         ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
 729         if (ret < 0)
 730                 goto err;
 731         if (ret > 0)
 732                 __set_bit(ATH_STAT_MRRETRY, sc->status);
 733
 734         /*
 735          * Collect the channel list.  The 802.11 layer
 736          * is resposible for filtering this list based
 737          * on settings like the phy mode and regulatory
 738          * domain restrictions.
 739          */
 740         ret = ath5k_setup_bands(hw);
 741         if (ret) {
 742                 ATH5K_ERR(sc, "can't get channels\n");
 743                 goto err;
 744         }
 745
 746         /* NB: setup here so ath5k_rate_update is happy */
 747         if (test_bit(AR5K_MODE_11A, ah->ah_modes))
 748                 ath5k_setcurmode(sc, AR5K_MODE_11A);
 749         else
 750                 ath5k_setcurmode(sc, AR5K_MODE_11B);
 751
 752         /*
 753          * Allocate tx+rx descriptors and populate the lists.
 754          */
 755         ret = ath5k_desc_alloc(sc, pdev);
 756         if (ret) {
 757                 ATH5K_ERR(sc, "can't allocate descriptors\n");
 758                 goto err;
 759         }
 760
 761         /*
 762          * Allocate hardware transmit queues: one queue for
 763          * beacon frames and one data queue for each QoS
 764          * priority.  Note that hw functions handle reseting
 765          * these queues at the needed time.
 766          */
 767         ret = ath5k_beaconq_setup(ah);
 768         if (ret < 0) {
 769                 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
 770                 goto err_desc;
 771         }
 772         sc->bhalq = ret;
 773
 774         sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
 775         if (IS_ERR(sc->txq)) {
 776                 ATH5K_ERR(sc, "can't setup xmit queue\n");
 777                 ret = PTR_ERR(sc->txq);
 778                 goto err_bhal;
 779         }
 780
 781         tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
 782         tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
 783         tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
 784         setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
 785
 786         ret = ath5k_eeprom_read_mac(ah, mac);
 787         if (ret) {
 788                 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
 789                         sc->pdev->device);
 790                 goto err_queues;
 791         }
 792
 793         SET_IEEE80211_PERM_ADDR(hw, mac);
 794         /* All MAC address bits matter for ACKs */
 795         memset(sc->bssidmask, 0xff, ETH_ALEN);
 796         ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
 797
 798         ret = ieee80211_register_hw(hw);
 799         if (ret) {
 800                 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
 801                 goto err_queues;
 802         }
 803
 804         ath5k_init_leds(sc);
 805
 806         return 0;
 807 err_queues:
 808         ath5k_txq_release(sc);
 809 err_bhal:
 810         ath5k_hw_release_tx_queue(ah, sc->bhalq);
 811 err_desc:
 812         ath5k_desc_free(sc, pdev);
 813 err:
 814         return ret;
 815 }
 816
 817 static void
 818 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 819 {
 820         struct ath5k_softc *sc = hw->priv;
 821
 822         /*
 823          * NB: the order of these is important:
 824          * o call the 802.11 layer before detaching ath5k_hw to
 825          *   insure callbacks into the driver to delete global
 826          *   key cache entries can be handled
 827          * o reclaim the tx queue data structures after calling
 828          *   the 802.11 layer as we'll get called back to reclaim
 829          *   node state and potentially want to use them
 830          * o to cleanup the tx queues the hal is called, so detach
 831          *   it last
 832          * XXX: ??? detach ath5k_hw ???
 833          * Other than that, it's straightforward...
 834          */
 835         ieee80211_unregister_hw(hw);
 836         ath5k_desc_free(sc, pdev);
 837         ath5k_txq_release(sc);
 838         ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
 839         ath5k_unregister_leds(sc);
 840
 841         /*
 842          * NB: can't reclaim these until after ieee80211_ifdetach
 843          * returns because we'll get called back to reclaim node
 844          * state and potentially want to use them.
 845          */
 846 }
 847
 848
 849
 850
 851 /********************\
 852 * Channel/mode setup *
 853 \********************/
 854
 855 /*
 856  * Convert IEEE channel number to MHz frequency.
 857  */
 858 static inline short
 859 ath5k_ieee2mhz(short chan)
 860 {
 861         if (chan <= 14 || chan >= 27)
 862                 return ieee80211chan2mhz(chan);
 863         else
 864                 return 2212 + chan * 20;
 865 }
 866
 867 static unsigned int
 868 ath5k_copy_channels(struct ath5k_hw *ah,
 869                 struct ieee80211_channel *channels,
 870                 unsigned int mode,
 871                 unsigned int max)
 872 {
 873         unsigned int i, count, size, chfreq, freq, ch;
 874
 875         if (!test_bit(mode, ah->ah_modes))
 876                 return 0;
 877
 878         switch (mode) {
 879         case AR5K_MODE_11A:
 880         case AR5K_MODE_11A_TURBO:
 881                 /* 1..220, but 2GHz frequencies are filtered by check_channel */
 882                 size = 220 ;
 883                 chfreq = CHANNEL_5GHZ;
 884                 break;
 885         case AR5K_MODE_11B:
 886         case AR5K_MODE_11G:
 887         case AR5K_MODE_11G_TURBO:
 888                 size = 26;
 889                 chfreq = CHANNEL_2GHZ;
 890                 break;
 891         default:
 892                 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
 893                 return 0;
 894         }
 895
 896         for (i = 0, count = 0; i < size && max > 0; i++) {
 897                 ch = i + 1 ;
 898                 freq = ath5k_ieee2mhz(ch);
 899
 900                 /* Check if channel is supported by the chipset */
 901                 if (!ath5k_channel_ok(ah, freq, chfreq))
 902                         continue;
 903
 904                 /* Write channel info and increment counter */
 905                 channels[count].center_freq = freq;
 906                 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
 907                         IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 908                 switch (mode) {
 909                 case AR5K_MODE_11A:
 910                 case AR5K_MODE_11G:
 911                         channels[count].hw_value = chfreq | CHANNEL_OFDM;
 912                         break;
 913                 case AR5K_MODE_11A_TURBO:
 914                 case AR5K_MODE_11G_TURBO:
 915                         channels[count].hw_value = chfreq |
 916                                 CHANNEL_OFDM | CHANNEL_TURBO;
 917                         break;
 918                 case AR5K_MODE_11B:
 919                         channels[count].hw_value = CHANNEL_B;
 920                 }
 921
 922                 count++;
 923                 max--;
 924         }
 925
 926         return count;
 927 }
 928
 929 static void
 930 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
 931 {
 932         u8 i;
 933
 934         for (i = 0; i < AR5K_MAX_RATES; i++)
 935                 sc->rate_idx[b->band][i] = -1;
 936
 937         for (i = 0; i < b->n_bitrates; i++) {
 938                 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
 939                 if (b->bitrates[i].hw_value_short)
 940                         sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
 941         }
 942 }
 943
 944 static int
 945 ath5k_setup_bands(struct ieee80211_hw *hw)
 946 {
 947         struct ath5k_softc *sc = hw->priv;
 948         struct ath5k_hw *ah = sc->ah;
 949         struct ieee80211_supported_band *sband;
 950         int max_c, count_c = 0;
 951         int i;
 952
 953         BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
 954         max_c = ARRAY_SIZE(sc->channels);
 955
 956         /* 2GHz band */
 957         sband = &sc->sbands[IEEE80211_BAND_2GHZ];
 958         sband->band = IEEE80211_BAND_2GHZ;
 959         sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
 960
 961         if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
 962                 /* G mode */
 963                 memcpy(sband->bitrates, &ath5k_rates[0],
 964                        sizeof(struct ieee80211_rate) * 12);
 965                 sband->n_bitrates = 12;
 966
 967                 sband->channels = sc->channels;
 968                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 969                                         AR5K_MODE_11G, max_c);
 970
 971                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 972                 count_c = sband->n_channels;
 973                 max_c -= count_c;
 974         } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
 975                 /* B mode */
 976                 memcpy(sband->bitrates, &ath5k_rates[0],
 977                        sizeof(struct ieee80211_rate) * 4);
 978                 sband->n_bitrates = 4;
 979
 980                 /* 5211 only supports B rates and uses 4bit rate codes
 981                  * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
 982                  * fix them up here:
 983                  */
 984                 if (ah->ah_version == AR5K_AR5211) {
 985                         for (i = 0; i < 4; i++) {
 986                                 sband->bitrates[i].hw_value =
 987                                         sband->bitrates[i].hw_value & 0xF;
 988                                 sband->bitrates[i].hw_value_short =
 989                                         sband->bitrates[i].hw_value_short & 0xF;
 990                         }
 991                 }
 992
 993                 sband->channels = sc->channels;
 994                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 995                                         AR5K_MODE_11B, max_c);
 996
 997                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 998                 count_c = sband->n_channels;
 999                 max_c -= count_c;
1000         }
1001         ath5k_setup_rate_idx(sc, sband);
1002
1003         /* 5GHz band, A mode */
1004         if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1005                 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1006                 sband->band = IEEE80211_BAND_5GHZ;
1007                 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1008
1009                 memcpy(sband->bitrates, &ath5k_rates[4],
1010                        sizeof(struct ieee80211_rate) * 8);
1011                 sband->n_bitrates = 8;
1012
1013                 sband->channels = &sc->channels[count_c];
1014                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1015                                         AR5K_MODE_11A, max_c);
1016
1017                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1018         }
1019         ath5k_setup_rate_idx(sc, sband);
1020
1021         ath5k_debug_dump_bands(sc);
1022
1023         return 0;
1024 }
1025
1026 /*
1027  * Set/change channels.  If the channel is really being changed,
1028  * it's done by reseting the chip.  To accomplish this we must
1029  * first cleanup any pending DMA, then restart stuff after a la
1030  * ath5k_init.
1031  *
1032  * Called with sc->lock.
1033  */
1034 static int
1035 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1036 {
1037         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1038                 sc->curchan->center_freq, chan->center_freq);
1039
1040         if (chan->center_freq != sc->curchan->center_freq ||
1041                 chan->hw_value != sc->curchan->hw_value) {
1042
1043                 sc->curchan = chan;
1044                 sc->curband = &sc->sbands[chan->band];
1045
1046                 /*
1047                  * To switch channels clear any pending DMA operations;
1048                  * wait long enough for the RX fifo to drain, reset the
1049                  * hardware at the new frequency, and then re-enable
1050                  * the relevant bits of the h/w.
1051                  */
1052                 return ath5k_reset(sc, true, true);
1053         }
1054
1055         return 0;
1056 }
1057
1058 static void
1059 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1060 {
1061         sc->curmode = mode;
1062
1063         if (mode == AR5K_MODE_11A) {
1064                 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1065         } else {
1066                 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1067         }
1068 }
1069
1070 static void
1071 ath5k_mode_setup(struct ath5k_softc *sc)
1072 {
1073         struct ath5k_hw *ah = sc->ah;
1074         u32 rfilt;
1075
1076         /* configure rx filter */
1077         rfilt = sc->filter_flags;
1078         ath5k_hw_set_rx_filter(ah, rfilt);
1079
1080         if (ath5k_hw_hasbssidmask(ah))
1081                 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1082
1083         /* configure operational mode */
1084         ath5k_hw_set_opmode(ah);
1085
1086         ath5k_hw_set_mcast_filter(ah, 0, 0);
1087         ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1088 }
1089
1090 static inline int
1091 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1092 {
1093         WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1094         return sc->rate_idx[sc->curband->band][hw_rix];
1095 }
1096
1097 /***************\
1098 * Buffers setup *
1099 \***************/
1100
1101 static int
1102 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1103 {
1104         struct ath5k_hw *ah = sc->ah;
1105         struct sk_buff *skb = bf->skb;
1106         struct ath5k_desc *ds;
1107
1108         if (likely(skb == NULL)) {
1109                 unsigned int off;
1110
1111                 /*
1112                  * Allocate buffer with headroom_needed space for the
1113                  * fake physical layer header at the start.
1114                  */
1115                 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1116                 if (unlikely(skb == NULL)) {
1117                         ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1118                                         sc->rxbufsize + sc->cachelsz - 1);
1119                         return -ENOMEM;
1120                 }
1121                 /*
1122                  * Cache-line-align.  This is important (for the
1123                  * 5210 at least) as not doing so causes bogus data
1124                  * in rx'd frames.
1125                  */
1126                 off = ((unsigned long)skb->data) % sc->cachelsz;
1127                 if (off != 0)
1128                         skb_reserve(skb, sc->cachelsz - off);
1129
1130                 bf->skb = skb;
1131                 bf->skbaddr = pci_map_single(sc->pdev,
1132                         skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1133                 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1134                         ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1135                         dev_kfree_skb(skb);
1136                         bf->skb = NULL;
1137                         return -ENOMEM;
1138                 }
1139         }
1140
1141         /*
1142          * Setup descriptors.  For receive we always terminate
1143          * the descriptor list with a self-linked entry so we'll
1144          * not get overrun under high load (as can happen with a
1145          * 5212 when ANI processing enables PHY error frames).
1146          *
1147          * To insure the last descriptor is self-linked we create
1148          * each descriptor as self-linked and add it to the end.  As
1149          * each additional descriptor is added the previous self-linked
1150          * entry is ``fixed'' naturally.  This should be safe even
1151          * if DMA is happening.  When processing RX interrupts we
1152          * never remove/process the last, self-linked, entry on the
1153          * descriptor list.  This insures the hardware always has
1154          * someplace to write a new frame.
1155          */
1156         ds = bf->desc;
1157         ds->ds_link = bf->daddr;        /* link to self */
1158         ds->ds_data = bf->skbaddr;
1159         ah->ah_setup_rx_desc(ah, ds,
1160                 skb_tailroom(skb),      /* buffer size */
1161                 0);
1162
1163         if (sc->rxlink != NULL)
1164                 *sc->rxlink = bf->daddr;
1165         sc->rxlink = &ds->ds_link;
1166         return 0;
1167 }
1168
1169 static int
1170 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1171 {
1172         struct ath5k_hw *ah = sc->ah;
1173         struct ath5k_txq *txq = sc->txq;
1174         struct ath5k_desc *ds = bf->desc;
1175         struct sk_buff *skb = bf->skb;
1176         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1177         unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1178         struct ieee80211_rate *rate;
1179         unsigned int mrr_rate[3], mrr_tries[3];
1180         int i, ret;
1181
1182         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1183
1184         /* XXX endianness */
1185         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1186                         PCI_DMA_TODEVICE);
1187
1188         if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1189                 flags |= AR5K_TXDESC_NOACK;
1190
1191         pktlen = skb->len;
1192
1193         if (info->control.hw_key) {
1194                 keyidx = info->control.hw_key->hw_key_idx;
1195                 pktlen += info->control.hw_key->icv_len;
1196         }
1197         ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1198                 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1199                 (sc->power_level * 2),
1200                 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1201                 info->control.rates[0].count, keyidx, 0, flags, 0, 0);
1202         if (ret)
1203                 goto err_unmap;
1204
1205         memset(mrr_rate, 0, sizeof(mrr_rate));
1206         memset(mrr_tries, 0, sizeof(mrr_tries));
1207         for (i = 0; i < 3; i++) {
1208                 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1209                 if (!rate)
1210                         break;
1211
1212                 mrr_rate[i] = rate->hw_value;
1213                 mrr_tries[i] = info->control.rates[i + 1].count;
1214         }
1215
1216         ah->ah_setup_mrr_tx_desc(ah, ds,
1217                 mrr_rate[0], mrr_tries[0],
1218                 mrr_rate[1], mrr_tries[1],
1219                 mrr_rate[2], mrr_tries[2]);
1220
1221         ds->ds_link = 0;
1222         ds->ds_data = bf->skbaddr;
1223
1224         spin_lock_bh(&txq->lock);
1225         list_add_tail(&bf->list, &txq->q);
1226         sc->tx_stats[txq->qnum].len++;
1227         if (txq->link == NULL) /* is this first packet? */
1228                 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1229         else /* no, so only link it */
1230                 *txq->link = bf->daddr;
1231
1232         txq->link = &ds->ds_link;
1233         ath5k_hw_start_tx_dma(ah, txq->qnum);
1234         mmiowb();
1235         spin_unlock_bh(&txq->lock);
1236
1237         return 0;
1238 err_unmap:
1239         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1240         return ret;
1241 }
1242
1243 /*******************\
1244 * Descriptors setup *
1245 \*******************/
1246
1247 static int
1248 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1249 {
1250         struct ath5k_desc *ds;
1251         struct ath5k_buf *bf;
1252         dma_addr_t da;
1253         unsigned int i;
1254         int ret;
1255
1256         /* allocate descriptors */
1257         sc->desc_len = sizeof(struct ath5k_desc) *
1258                         (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1259         sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1260         if (sc->desc == NULL) {
1261                 ATH5K_ERR(sc, "can't allocate descriptors\n");
1262                 ret = -ENOMEM;
1263                 goto err;
1264         }
1265         ds = sc->desc;
1266         da = sc->desc_daddr;
1267         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1268                 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1269
1270         bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1271                         sizeof(struct ath5k_buf), GFP_KERNEL);
1272         if (bf == NULL) {
1273                 ATH5K_ERR(sc, "can't allocate bufptr\n");
1274                 ret = -ENOMEM;
1275                 goto err_free;
1276         }
1277         sc->bufptr = bf;
1278
1279         INIT_LIST_HEAD(&sc->rxbuf);
1280         for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1281                 bf->desc = ds;
1282                 bf->daddr = da;
1283                 list_add_tail(&bf->list, &sc->rxbuf);
1284         }
1285
1286         INIT_LIST_HEAD(&sc->txbuf);
1287         sc->txbuf_len = ATH_TXBUF;
1288         for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1289                         da += sizeof(*ds)) {
1290                 bf->desc = ds;
1291                 bf->daddr = da;
1292                 list_add_tail(&bf->list, &sc->txbuf);
1293         }
1294
1295         /* beacon buffer */
1296         bf->desc = ds;
1297         bf->daddr = da;
1298         sc->bbuf = bf;
1299
1300         return 0;
1301 err_free:
1302         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1303 err:
1304         sc->desc = NULL;
1305         return ret;
1306 }
1307
1308 static void
1309 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1310 {
1311         struct ath5k_buf *bf;
1312
1313         ath5k_txbuf_free(sc, sc->bbuf);
1314         list_for_each_entry(bf, &sc->txbuf, list)
1315                 ath5k_txbuf_free(sc, bf);
1316         list_for_each_entry(bf, &sc->rxbuf, list)
1317                 ath5k_txbuf_free(sc, bf);
1318
1319         /* Free memory associated with all descriptors */
1320         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1321
1322         kfree(sc->bufptr);
1323         sc->bufptr = NULL;
1324 }
1325
1326
1327
1328
1329
1330 /**************\
1331 * Queues setup *
1332 \**************/
1333
1334 static struct ath5k_txq *
1335 ath5k_txq_setup(struct ath5k_softc *sc,
1336                 int qtype, int subtype)
1337 {
1338         struct ath5k_hw *ah = sc->ah;
1339         struct ath5k_txq *txq;
1340         struct ath5k_txq_info qi = {
1341                 .tqi_subtype = subtype,
1342                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1343                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1344                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1345         };
1346         int qnum;
1347
1348         /*
1349          * Enable interrupts only for EOL and DESC conditions.
1350          * We mark tx descriptors to receive a DESC interrupt
1351          * when a tx queue gets deep; otherwise waiting for the
1352          * EOL to reap descriptors.  Note that this is done to
1353          * reduce interrupt load and this only defers reaping
1354          * descriptors, never transmitting frames.  Aside from
1355          * reducing interrupts this also permits more concurrency.
1356          * The only potential downside is if the tx queue backs
1357          * up in which case the top half of the kernel may backup
1358          * due to a lack of tx descriptors.
1359          */
1360         qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1361                                 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1362         qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1363         if (qnum < 0) {
1364                 /*
1365                  * NB: don't print a message, this happens
1366                  * normally on parts with too few tx queues
1367                  */
1368                 return ERR_PTR(qnum);
1369         }
1370         if (qnum >= ARRAY_SIZE(sc->txqs)) {
1371                 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1372                         qnum, ARRAY_SIZE(sc->txqs));
1373                 ath5k_hw_release_tx_queue(ah, qnum);
1374                 return ERR_PTR(-EINVAL);
1375         }
1376         txq = &sc->txqs[qnum];
1377         if (!txq->setup) {
1378                 txq->qnum = qnum;
1379                 txq->link = NULL;
1380                 INIT_LIST_HEAD(&txq->q);
1381                 spin_lock_init(&txq->lock);
1382                 txq->setup = true;
1383         }
1384         return &sc->txqs[qnum];
1385 }
1386
1387 static int
1388 ath5k_beaconq_setup(struct ath5k_hw *ah)
1389 {
1390         struct ath5k_txq_info qi = {
1391                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1392                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1393                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1394                 /* NB: for dynamic turbo, don't enable any other interrupts */
1395                 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1396         };
1397
1398         return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1399 }
1400
1401 static int
1402 ath5k_beaconq_config(struct ath5k_softc *sc)
1403 {
1404         struct ath5k_hw *ah = sc->ah;
1405         struct ath5k_txq_info qi;
1406         int ret;
1407
1408         ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1409         if (ret)
1410                 return ret;
1411         if (sc->opmode == NL80211_IFTYPE_AP ||
1412                 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1413                 /*
1414                  * Always burst out beacon and CAB traffic
1415                  * (aifs = cwmin = cwmax = 0)
1416                  */
1417                 qi.tqi_aifs = 0;
1418                 qi.tqi_cw_min = 0;
1419                 qi.tqi_cw_max = 0;
1420         } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1421                 /*
1422                  * Adhoc mode; backoff between 0 and (2 * cw_min).
1423                  */
1424                 qi.tqi_aifs = 0;
1425                 qi.tqi_cw_min = 0;
1426                 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1427         }
1428
1429         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1430                 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1431                 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1432
1433         ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1434         if (ret) {
1435                 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1436                         "hardware queue!\n", __func__);
1437                 return ret;
1438         }
1439
1440         return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1441 }
1442
1443 static void
1444 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1445 {
1446         struct ath5k_buf *bf, *bf0;
1447
1448         /*
1449          * NB: this assumes output has been stopped and
1450          *     we do not need to block ath5k_tx_tasklet
1451          */
1452         spin_lock_bh(&txq->lock);
1453         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1454                 ath5k_debug_printtxbuf(sc, bf);
1455
1456                 ath5k_txbuf_free(sc, bf);
1457
1458                 spin_lock_bh(&sc->txbuflock);
1459                 sc->tx_stats[txq->qnum].len--;
1460                 list_move_tail(&bf->list, &sc->txbuf);
1461                 sc->txbuf_len++;
1462                 spin_unlock_bh(&sc->txbuflock);
1463         }
1464         txq->link = NULL;
1465         spin_unlock_bh(&txq->lock);
1466 }
1467
1468 /*
1469  * Drain the transmit queues and reclaim resources.
1470  */
1471 static void
1472 ath5k_txq_cleanup(struct ath5k_softc *sc)
1473 {
1474         struct ath5k_hw *ah = sc->ah;
1475         unsigned int i;
1476
1477         /* XXX return value */
1478         if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1479                 /* don't touch the hardware if marked invalid */
1480                 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1481                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1482                         ath5k_hw_get_txdp(ah, sc->bhalq));
1483                 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1484                         if (sc->txqs[i].setup) {
1485                                 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1486                                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1487                                         "link %p\n",
1488                                         sc->txqs[i].qnum,
1489                                         ath5k_hw_get_txdp(ah,
1490                                                         sc->txqs[i].qnum),
1491                                         sc->txqs[i].link);
1492                         }
1493         }
1494         ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1495
1496         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1497                 if (sc->txqs[i].setup)
1498                         ath5k_txq_drainq(sc, &sc->txqs[i]);
1499 }
1500
1501 static void
1502 ath5k_txq_release(struct ath5k_softc *sc)
1503 {
1504         struct ath5k_txq *txq = sc->txqs;
1505         unsigned int i;
1506
1507         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1508                 if (txq->setup) {
1509                         ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1510                         txq->setup = false;
1511                 }
1512 }
1513
1514
1515
1516
1517 /*************\
1518 * RX Handling *
1519 \*************/
1520
1521 /*
1522  * Enable the receive h/w following a reset.
1523  */
1524 static int
1525 ath5k_rx_start(struct ath5k_softc *sc)
1526 {
1527         struct ath5k_hw *ah = sc->ah;
1528         struct ath5k_buf *bf;
1529         int ret;
1530
1531         sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1532
1533         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1534                 sc->cachelsz, sc->rxbufsize);
1535
1536         sc->rxlink = NULL;
1537
1538         spin_lock_bh(&sc->rxbuflock);
1539         list_for_each_entry(bf, &sc->rxbuf, list) {
1540                 ret = ath5k_rxbuf_setup(sc, bf);
1541                 if (ret != 0) {
1542                         spin_unlock_bh(&sc->rxbuflock);
1543                         goto err;
1544                 }
1545         }
1546         bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1547         spin_unlock_bh(&sc->rxbuflock);
1548
1549         ath5k_hw_set_rxdp(ah, bf->daddr);
1550         ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
1551         ath5k_mode_setup(sc);           /* set filters, etc. */
1552         ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
1553
1554         return 0;
1555 err:
1556         return ret;
1557 }
1558
1559 /*
1560  * Disable the receive h/w in preparation for a reset.
1561  */
1562 static void
1563 ath5k_rx_stop(struct ath5k_softc *sc)
1564 {
1565         struct ath5k_hw *ah = sc->ah;
1566
1567         ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
1568         ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
1569         ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
1570
1571         ath5k_debug_printrxbuffs(sc, ah);
1572
1573         sc->rxlink = NULL;              /* just in case */
1574 }
1575
1576 static unsigned int
1577 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1578                 struct sk_buff *skb, struct ath5k_rx_status *rs)
1579 {
1580         struct ieee80211_hdr *hdr = (void *)skb->data;
1581         unsigned int keyix, hlen;
1582
1583         if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1584                         rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1585                 return RX_FLAG_DECRYPTED;
1586
1587         /* Apparently when a default key is used to decrypt the packet
1588            the hw does not set the index used to decrypt.  In such cases
1589            get the index from the packet. */
1590         hlen = ieee80211_hdrlen(hdr->frame_control);
1591         if (ieee80211_has_protected(hdr->frame_control) &&
1592             !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1593             skb->len >= hlen + 4) {
1594                 keyix = skb->data[hlen + 3] >> 6;
1595
1596                 if (test_bit(keyix, sc->keymap))
1597                         return RX_FLAG_DECRYPTED;
1598         }
1599
1600         return 0;
1601 }
1602
1603
1604 static void
1605 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1606                      struct ieee80211_rx_status *rxs)
1607 {
1608         u64 tsf, bc_tstamp;
1609         u32 hw_tu;
1610         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1611
1612         if (ieee80211_is_beacon(mgmt->frame_control) &&
1613             le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1614             memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1615                 /*
1616                  * Received an IBSS beacon with the same BSSID. Hardware *must*
1617                  * have updated the local TSF. We have to work around various
1618                  * hardware bugs, though...
1619                  */
1620                 tsf = ath5k_hw_get_tsf64(sc->ah);
1621                 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1622                 hw_tu = TSF_TO_TU(tsf);
1623
1624                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1625                         "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1626                         (unsigned long long)bc_tstamp,
1627                         (unsigned long long)rxs->mactime,
1628                         (unsigned long long)(rxs->mactime - bc_tstamp),
1629                         (unsigned long long)tsf);
1630
1631                 /*
1632                  * Sometimes the HW will give us a wrong tstamp in the rx
1633                  * status, causing the timestamp extension to go wrong.
1634                  * (This seems to happen especially with beacon frames bigger
1635                  * than 78 byte (incl. FCS))
1636                  * But we know that the receive timestamp must be later than the
1637                  * timestamp of the beacon since HW must have synced to that.
1638                  *
1639                  * NOTE: here we assume mactime to be after the frame was
1640                  * received, not like mac80211 which defines it at the start.
1641                  */
1642                 if (bc_tstamp > rxs->mactime) {
1643                         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1644                                 "fixing mactime from %llx to %llx\n",
1645                                 (unsigned long long)rxs->mactime,
1646                                 (unsigned long long)tsf);
1647                         rxs->mactime = tsf;
1648                 }
1649
1650                 /*
1651                  * Local TSF might have moved higher than our beacon timers,
1652                  * in that case we have to update them to continue sending
1653                  * beacons. This also takes care of synchronizing beacon sending
1654                  * times with other stations.
1655                  */
1656                 if (hw_tu >= sc->nexttbtt)
1657                         ath5k_beacon_update_timers(sc, bc_tstamp);
1658         }
1659 }
1660
1661
1662 static void
1663 ath5k_tasklet_rx(unsigned long data)
1664 {
1665         struct ieee80211_rx_status rxs = {};
1666         struct ath5k_rx_status rs = {};
1667         struct sk_buff *skb;
1668         struct ath5k_softc *sc = (void *)data;
1669         struct ath5k_buf *bf, *bf_last;
1670         struct ath5k_desc *ds;
1671         int ret;
1672         int hdrlen;
1673         int padsize;
1674
1675         spin_lock(&sc->rxbuflock);
1676         if (list_empty(&sc->rxbuf)) {
1677                 ATH5K_WARN(sc, "empty rx buf pool\n");
1678                 goto unlock;
1679         }
1680         bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1681         do {
1682                 rxs.flag = 0;
1683
1684                 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1685                 BUG_ON(bf->skb == NULL);
1686                 skb = bf->skb;
1687                 ds = bf->desc;
1688
1689                 /*
1690                  * last buffer must not be freed to ensure proper hardware
1691                  * function. When the hardware finishes also a packet next to
1692                  * it, we are sure, it doesn't use it anymore and we can go on.
1693                  */
1694                 if (bf_last == bf)
1695                         bf->flags |= 1;
1696                 if (bf->flags) {
1697                         struct ath5k_buf *bf_next = list_entry(bf->list.next,
1698                                         struct ath5k_buf, list);
1699                         ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1700                                         &rs);
1701                         if (ret)
1702                                 break;
1703                         bf->flags &= ~1;
1704                         /* skip the overwritten one (even status is martian) */
1705                         goto next;
1706                 }
1707
1708                 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1709                 if (unlikely(ret == -EINPROGRESS))
1710                         break;
1711                 else if (unlikely(ret)) {
1712                         ATH5K_ERR(sc, "error in processing rx descriptor\n");
1713                         spin_unlock(&sc->rxbuflock);
1714                         return;
1715                 }
1716
1717                 if (unlikely(rs.rs_more)) {
1718                         ATH5K_WARN(sc, "unsupported jumbo\n");
1719                         goto next;
1720                 }
1721
1722                 if (unlikely(rs.rs_status)) {
1723                         if (rs.rs_status & AR5K_RXERR_PHY)
1724                                 goto next;
1725                         if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1726                                 /*
1727                                  * Decrypt error.  If the error occurred
1728                                  * because there was no hardware key, then
1729                                  * let the frame through so the upper layers
1730                                  * can process it.  This is necessary for 5210
1731                                  * parts which have no way to setup a ``clear''
1732                                  * key cache entry.
1733                                  *
1734                                  * XXX do key cache faulting
1735                                  */
1736                                 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1737                                     !(rs.rs_status & AR5K_RXERR_CRC))
1738                                         goto accept;
1739                         }
1740                         if (rs.rs_status & AR5K_RXERR_MIC) {
1741                                 rxs.flag |= RX_FLAG_MMIC_ERROR;
1742                                 goto accept;
1743                         }
1744
1745                         /* let crypto-error packets fall through in MNTR */
1746                         if ((rs.rs_status &
1747                                 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1748                                         sc->opmode != NL80211_IFTYPE_MONITOR)
1749                                 goto next;
1750                 }
1751 accept:
1752                 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1753                                 PCI_DMA_FROMDEVICE);
1754                 bf->skb = NULL;
1755
1756                 skb_put(skb, rs.rs_datalen);
1757
1758                 /* The MAC header is padded to have 32-bit boundary if the
1759                  * packet payload is non-zero. The general calculation for
1760                  * padsize would take into account odd header lengths:
1761                  * padsize = (4 - hdrlen % 4) % 4; However, since only
1762                  * even-length headers are used, padding can only be 0 or 2
1763                  * bytes and we can optimize this a bit. In addition, we must
1764                  * not try to remove padding from short control frames that do
1765                  * not have payload. */
1766                 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1767                 padsize = ath5k_pad_size(hdrlen);
1768                 if (padsize) {
1769                         memmove(skb->data + padsize, skb->data, hdrlen);
1770                         skb_pull(skb, padsize);
1771                 }
1772
1773                 /*
1774                  * always extend the mac timestamp, since this information is
1775                  * also needed for proper IBSS merging.
1776                  *
1777                  * XXX: it might be too late to do it here, since rs_tstamp is
1778                  * 15bit only. that means TSF extension has to be done within
1779                  * 32768usec (about 32ms). it might be necessary to move this to
1780                  * the interrupt handler, like it is done in madwifi.
1781                  *
1782                  * Unfortunately we don't know when the hardware takes the rx
1783                  * timestamp (beginning of phy frame, data frame, end of rx?).
1784                  * The only thing we know is that it is hardware specific...
1785                  * On AR5213 it seems the rx timestamp is at the end of the
1786                  * frame, but i'm not sure.
1787                  *
1788                  * NOTE: mac80211 defines mactime at the beginning of the first
1789                  * data symbol. Since we don't have any time references it's
1790                  * impossible to comply to that. This affects IBSS merge only
1791                  * right now, so it's not too bad...
1792                  */
1793                 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1794                 rxs.flag |= RX_FLAG_TSFT;
1795
1796                 rxs.freq = sc->curchan->center_freq;
1797                 rxs.band = sc->curband->band;
1798
1799                 rxs.noise = sc->ah->ah_noise_floor;
1800                 rxs.signal = rxs.noise + rs.rs_rssi;
1801
1802                 /* An rssi of 35 indicates you should be able use
1803                  * 54 Mbps reliably. A more elaborate scheme can be used
1804                  * here but it requires a map of SNR/throughput for each
1805                  * possible mode used */
1806                 rxs.qual = rs.rs_rssi * 100 / 35;
1807
1808                 /* rssi can be more than 35 though, anything above that
1809                  * should be considered at 100% */
1810                 if (rxs.qual > 100)
1811                         rxs.qual = 100;
1812
1813                 rxs.antenna = rs.rs_antenna;
1814                 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1815                 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1816
1817                 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1818                     sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1819                         rxs.flag |= RX_FLAG_SHORTPRE;
1820
1821                 ath5k_debug_dump_skb(sc, skb, "RX  ", 0);
1822
1823                 /* check beacons in IBSS mode */
1824                 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1825                         ath5k_check_ibss_tsf(sc, skb, &rxs);
1826
1827                 __ieee80211_rx(sc->hw, skb, &rxs);
1828 next:
1829                 list_move_tail(&bf->list, &sc->rxbuf);
1830         } while (ath5k_rxbuf_setup(sc, bf) == 0);
1831 unlock:
1832         spin_unlock(&sc->rxbuflock);
1833 }
1834
1835
1836
1837
1838 /*************\
1839 * TX Handling *
1840 \*************/
1841
1842 static void
1843 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1844 {
1845         struct ath5k_tx_status ts = {};
1846         struct ath5k_buf *bf, *bf0;
1847         struct ath5k_desc *ds;
1848         struct sk_buff *skb;
1849         struct ieee80211_tx_info *info;
1850         int i, ret;
1851
1852         spin_lock(&txq->lock);
1853         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1854                 ds = bf->desc;
1855
1856                 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1857                 if (unlikely(ret == -EINPROGRESS))
1858                         break;
1859                 else if (unlikely(ret)) {
1860                         ATH5K_ERR(sc, "error %d while processing queue %u\n",
1861                                 ret, txq->qnum);
1862                         break;
1863                 }
1864
1865                 skb = bf->skb;
1866                 info = IEEE80211_SKB_CB(skb);
1867                 bf->skb = NULL;
1868
1869                 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1870                                 PCI_DMA_TODEVICE);
1871
1872                 ieee80211_tx_info_clear_status(info);
1873                 for (i = 0; i < 4; i++) {
1874                         struct ieee80211_tx_rate *r =
1875                                 &info->status.rates[i];
1876
1877                         if (ts.ts_rate[i]) {
1878                                 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1879                                 r->count = ts.ts_retry[i];
1880                         } else {
1881                                 r->idx = -1;
1882                                 r->count = 0;
1883                         }
1884                 }
1885
1886                 /* count the successful attempt as well */
1887                 info->status.rates[ts.ts_final_idx].count++;
1888
1889                 if (unlikely(ts.ts_status)) {
1890                         sc->ll_stats.dot11ACKFailureCount++;
1891                         if (ts.ts_status & AR5K_TXERR_FILT)
1892                                 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1893                 } else {
1894                         info->flags |= IEEE80211_TX_STAT_ACK;
1895                         info->status.ack_signal = ts.ts_rssi;
1896                 }
1897
1898                 ieee80211_tx_status(sc->hw, skb);
1899                 sc->tx_stats[txq->qnum].count++;
1900
1901                 spin_lock(&sc->txbuflock);
1902                 sc->tx_stats[txq->qnum].len--;
1903                 list_move_tail(&bf->list, &sc->txbuf);
1904                 sc->txbuf_len++;
1905                 spin_unlock(&sc->txbuflock);
1906         }
1907         if (likely(list_empty(&txq->q)))
1908                 txq->link = NULL;
1909         spin_unlock(&txq->lock);
1910         if (sc->txbuf_len > ATH_TXBUF / 5)
1911                 ieee80211_wake_queues(sc->hw);
1912 }
1913
1914 static void
1915 ath5k_tasklet_tx(unsigned long data)
1916 {
1917         struct ath5k_softc *sc = (void *)data;
1918
1919         ath5k_tx_processq(sc, sc->txq);
1920 }
1921
1922
1923 /*****************\
1924 * Beacon handling *
1925 \*****************/
1926
1927 /*
1928  * Setup the beacon frame for transmit.
1929  */
1930 static int
1931 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1932 {
1933         struct sk_buff *skb = bf->skb;
1934         struct  ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1935         struct ath5k_hw *ah = sc->ah;
1936         struct ath5k_desc *ds;
1937         int ret, antenna = 0;
1938         u32 flags;
1939
1940         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1941                         PCI_DMA_TODEVICE);
1942         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1943                         "skbaddr %llx\n", skb, skb->data, skb->len,
1944                         (unsigned long long)bf->skbaddr);
1945         if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1946                 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1947                 return -EIO;
1948         }
1949
1950         ds = bf->desc;
1951
1952         flags = AR5K_TXDESC_NOACK;
1953         if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1954                 ds->ds_link = bf->daddr;        /* self-linked */
1955                 flags |= AR5K_TXDESC_VEOL;
1956                 /*
1957                  * Let hardware handle antenna switching if txantenna is not set
1958                  */
1959         } else {
1960                 ds->ds_link = 0;
1961                 /*
1962                  * Switch antenna every 4 beacons if txantenna is not set
1963                  * XXX assumes two antennas
1964                  */
1965                 if (antenna == 0)
1966                         antenna = sc->bsent & 4 ? 2 : 1;
1967         }
1968
1969         ds->ds_data = bf->skbaddr;
1970         ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1971                         ieee80211_get_hdrlen_from_skb(skb),
1972                         AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1973                         ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1974                         1, AR5K_TXKEYIX_INVALID,
1975                         antenna, flags, 0, 0);
1976         if (ret)
1977                 goto err_unmap;
1978
1979         return 0;
1980 err_unmap:
1981         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1982         return ret;
1983 }
1984
1985 /*
1986  * Transmit a beacon frame at SWBA.  Dynamic updates to the
1987  * frame contents are done as needed and the slot time is
1988  * also adjusted based on current state.
1989  *
1990  * this is usually called from interrupt context (ath5k_intr())
1991  * but also from ath5k_beacon_config() in IBSS mode which in turn
1992  * can be called from a tasklet and user context
1993  */
1994 static void
1995 ath5k_beacon_send(struct ath5k_softc *sc)
1996 {
1997         struct ath5k_buf *bf = sc->bbuf;
1998         struct ath5k_hw *ah = sc->ah;
1999
2000         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2001
2002         if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2003                         sc->opmode == NL80211_IFTYPE_MONITOR)) {
2004                 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2005                 return;
2006         }
2007         /*
2008          * Check if the previous beacon has gone out.  If
2009          * not don't don't try to post another, skip this
2010          * period and wait for the next.  Missed beacons
2011          * indicate a problem and should not occur.  If we
2012          * miss too many consecutive beacons reset the device.
2013          */
2014         if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2015                 sc->bmisscount++;
2016                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2017                         "missed %u consecutive beacons\n", sc->bmisscount);
2018                 if (sc->bmisscount > 3) {               /* NB: 3 is a guess */
2019                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2020                                 "stuck beacon time (%u missed)\n",
2021                                 sc->bmisscount);
2022                         tasklet_schedule(&sc->restq);
2023                 }
2024                 return;
2025         }
2026         if (unlikely(sc->bmisscount != 0)) {
2027                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2028                         "resume beacon xmit after %u misses\n",
2029                         sc->bmisscount);
2030                 sc->bmisscount = 0;
2031         }
2032
2033         /*
2034          * Stop any current dma and put the new frame on the queue.
2035          * This should never fail since we check above that no frames
2036          * are still pending on the queue.
2037          */
2038         if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2039                 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2040                 /* NB: hw still stops DMA, so proceed */
2041         }
2042
2043         ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2044         ath5k_hw_start_tx_dma(ah, sc->bhalq);
2045         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2046                 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2047
2048         sc->bsent++;
2049 }
2050
2051
2052 /**
2053  * ath5k_beacon_update_timers - update beacon timers
2054  *
2055  * @sc: struct ath5k_softc pointer we are operating on
2056  * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2057  *          beacon timer update based on the current HW TSF.
2058  *
2059  * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2060  * of a received beacon or the current local hardware TSF and write it to the
2061  * beacon timer registers.
2062  *
2063  * This is called in a variety of situations, e.g. when a beacon is received,
2064  * when a TSF update has been detected, but also when an new IBSS is created or
2065  * when we otherwise know we have to update the timers, but we keep it in this
2066  * function to have it all together in one place.
2067  */
2068 static void
2069 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2070 {
2071         struct ath5k_hw *ah = sc->ah;
2072         u32 nexttbtt, intval, hw_tu, bc_tu;
2073         u64 hw_tsf;
2074
2075         intval = sc->bintval & AR5K_BEACON_PERIOD;
2076         if (WARN_ON(!intval))
2077                 return;
2078
2079         /* beacon TSF converted to TU */
2080         bc_tu = TSF_TO_TU(bc_tsf);
2081
2082         /* current TSF converted to TU */
2083         hw_tsf = ath5k_hw_get_tsf64(ah);
2084         hw_tu = TSF_TO_TU(hw_tsf);
2085
2086 #define FUDGE 3
2087         /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2088         if (bc_tsf == -1) {
2089                 /*
2090                  * no beacons received, called internally.
2091                  * just need to refresh timers based on HW TSF.
2092                  */
2093                 nexttbtt = roundup(hw_tu + FUDGE, intval);
2094         } else if (bc_tsf == 0) {
2095                 /*
2096                  * no beacon received, probably called by ath5k_reset_tsf().
2097                  * reset TSF to start with 0.
2098                  */
2099                 nexttbtt = intval;
2100                 intval |= AR5K_BEACON_RESET_TSF;
2101         } else if (bc_tsf > hw_tsf) {
2102                 /*
2103                  * beacon received, SW merge happend but HW TSF not yet updated.
2104                  * not possible to reconfigure timers yet, but next time we
2105                  * receive a beacon with the same BSSID, the hardware will
2106                  * automatically update the TSF and then we need to reconfigure
2107                  * the timers.
2108                  */
2109                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2110                         "need to wait for HW TSF sync\n");
2111                 return;
2112         } else {
2113                 /*
2114                  * most important case for beacon synchronization between STA.
2115                  *
2116                  * beacon received and HW TSF has been already updated by HW.
2117                  * update next TBTT based on the TSF of the beacon, but make
2118                  * sure it is ahead of our local TSF timer.
2119                  */
2120                 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2121         }
2122 #undef FUDGE
2123
2124         sc->nexttbtt = nexttbtt;
2125
2126         intval |= AR5K_BEACON_ENA;
2127         ath5k_hw_init_beacon(ah, nexttbtt, intval);
2128
2129         /*
2130          * debugging output last in order to preserve the time critical aspect
2131          * of this function
2132          */
2133         if (bc_tsf == -1)
2134                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2135                         "reconfigured timers based on HW TSF\n");
2136         else if (bc_tsf == 0)
2137                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2138                         "reset HW TSF and timers\n");
2139         else
2140                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2141                         "updated timers based on beacon TSF\n");
2142
2143         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2144                           "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2145                           (unsigned long long) bc_tsf,
2146                           (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2147         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2148                 intval & AR5K_BEACON_PERIOD,
2149                 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2150                 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2151 }
2152
2153
2154 /**
2155  * ath5k_beacon_config - Configure the beacon queues and interrupts
2156  *
2157  * @sc: struct ath5k_softc pointer we are operating on
2158  *
2159  * When operating in station mode we want to receive a BMISS interrupt when we
2160  * stop seeing beacons from the AP we've associated with so we can look for
2161  * another AP to associate with.
2162  *
2163  * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2164  * interrupts to detect TSF updates only.
2165  */
2166 static void
2167 ath5k_beacon_config(struct ath5k_softc *sc)
2168 {
2169         struct ath5k_hw *ah = sc->ah;
2170
2171         ath5k_hw_set_imr(ah, 0);
2172         sc->bmisscount = 0;
2173         sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2174
2175         if (sc->opmode == NL80211_IFTYPE_STATION) {
2176                 sc->imask |= AR5K_INT_BMISS;
2177         } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2178                         sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2179                         sc->opmode == NL80211_IFTYPE_AP) {
2180                 /*
2181                  * In IBSS mode we use a self-linked tx descriptor and let the
2182                  * hardware send the beacons automatically. We have to load it
2183                  * only once here.
2184                  * We use the SWBA interrupt only to keep track of the beacon
2185                  * timers in order to detect automatic TSF updates.
2186                  */
2187                 ath5k_beaconq_config(sc);
2188
2189                 sc->imask |= AR5K_INT_SWBA;
2190
2191                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2192                         if (ath5k_hw_hasveol(ah)) {
2193                                 spin_lock(&sc->block);
2194                                 ath5k_beacon_send(sc);
2195                                 spin_unlock(&sc->block);
2196                         }
2197                 } else
2198                         ath5k_beacon_update_timers(sc, -1);
2199         }
2200
2201         ath5k_hw_set_imr(ah, sc->imask);
2202 }
2203
2204
2205 /********************\
2206 * Interrupt handling *
2207 \********************/
2208
2209 static int
2210 ath5k_init(struct ath5k_softc *sc, bool is_resume)
2211 {
2212         struct ath5k_hw *ah = sc->ah;
2213         int ret, i;
2214
2215         mutex_lock(&sc->lock);
2216
2217         if (is_resume && !test_bit(ATH_STAT_STARTED, sc->status))
2218                 goto out_ok;
2219
2220         __clear_bit(ATH_STAT_STARTED, sc->status);
2221
2222         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2223
2224         /*
2225          * Stop anything previously setup.  This is safe
2226          * no matter this is the first time through or not.
2227          */
2228         ath5k_stop_locked(sc);
2229
2230         /*
2231          * The basic interface to setting the hardware in a good
2232          * state is ``reset''.  On return the hardware is known to
2233          * be powered up and with interrupts disabled.  This must
2234          * be followed by initialization of the appropriate bits
2235          * and then setup of the interrupt mask.
2236          */
2237         sc->curchan = sc->hw->conf.channel;
2238         sc->curband = &sc->sbands[sc->curchan->band];
2239         sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2240                 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2241                 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2242         ret = ath5k_reset(sc, false, false);
2243         if (ret)
2244                 goto done;
2245
2246         /*
2247          * Reset the key cache since some parts do not reset the
2248          * contents on initial power up or resume from suspend.
2249          */
2250         for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2251                 ath5k_hw_reset_key(ah, i);
2252
2253         __set_bit(ATH_STAT_STARTED, sc->status);
2254
2255         /* Set ack to be sent at low bit-rates */
2256         ath5k_hw_set_ack_bitrate_high(ah, false);
2257
2258         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2259                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2260
2261 out_ok:
2262         ret = 0;
2263 done:
2264         mmiowb();
2265         mutex_unlock(&sc->lock);
2266         return ret;
2267 }
2268
2269 static int
2270 ath5k_stop_locked(struct ath5k_softc *sc)
2271 {
2272         struct ath5k_hw *ah = sc->ah;
2273
2274         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2275                         test_bit(ATH_STAT_INVALID, sc->status));
2276
2277         /*
2278          * Shutdown the hardware and driver:
2279          *    stop output from above
2280          *    disable interrupts
2281          *    turn off timers
2282          *    turn off the radio
2283          *    clear transmit machinery
2284          *    clear receive machinery
2285          *    drain and release tx queues
2286          *    reclaim beacon resources
2287          *    power down hardware
2288          *
2289          * Note that some of this work is not possible if the
2290          * hardware is gone (invalid).
2291          */
2292         ieee80211_stop_queues(sc->hw);
2293
2294         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2295                 ath5k_led_off(sc);
2296                 ath5k_hw_set_imr(ah, 0);
2297                 synchronize_irq(sc->pdev->irq);
2298         }
2299         ath5k_txq_cleanup(sc);
2300         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2301                 ath5k_rx_stop(sc);
2302                 ath5k_hw_phy_disable(ah);
2303         } else
2304                 sc->rxlink = NULL;
2305
2306         return 0;
2307 }
2308
2309 /*
2310  * Stop the device, grabbing the top-level lock to protect
2311  * against concurrent entry through ath5k_init (which can happen
2312  * if another thread does a system call and the thread doing the
2313  * stop is preempted).
2314  */
2315 static int
2316 ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend)
2317 {
2318         int ret;
2319
2320         mutex_lock(&sc->lock);
2321         ret = ath5k_stop_locked(sc);
2322         if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2323                 /*
2324                  * Set the chip in full sleep mode.  Note that we are
2325                  * careful to do this only when bringing the interface
2326                  * completely to a stop.  When the chip is in this state
2327                  * it must be carefully woken up or references to
2328                  * registers in the PCI clock domain may freeze the bus
2329                  * (and system).  This varies by chip and is mostly an
2330                  * issue with newer parts that go to sleep more quickly.
2331                  */
2332                 if (sc->ah->ah_mac_srev >= 0x78) {
2333                         /*
2334                          * XXX
2335                          * don't put newer MAC revisions > 7.8 to sleep because
2336                          * of the above mentioned problems
2337                          */
2338                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2339                                 "not putting device to sleep\n");
2340                 } else {
2341                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2342                                 "putting device to full sleep\n");
2343                         ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2344                 }
2345         }
2346         ath5k_txbuf_free(sc, sc->bbuf);
2347         if (!is_suspend)
2348                 __clear_bit(ATH_STAT_STARTED, sc->status);
2349
2350         mmiowb();
2351         mutex_unlock(&sc->lock);
2352
2353         del_timer_sync(&sc->calib_tim);
2354         tasklet_kill(&sc->rxtq);
2355         tasklet_kill(&sc->txtq);
2356         tasklet_kill(&sc->restq);
2357
2358         return ret;
2359 }
2360
2361 static irqreturn_t
2362 ath5k_intr(int irq, void *dev_id)
2363 {
2364         struct ath5k_softc *sc = dev_id;
2365         struct ath5k_hw *ah = sc->ah;
2366         enum ath5k_int status;
2367         unsigned int counter = 1000;
2368
2369         if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2370                                 !ath5k_hw_is_intr_pending(ah)))
2371                 return IRQ_NONE;
2372
2373         do {
2374                 /*
2375                  * Figure out the reason(s) for the interrupt.  Note
2376                  * that get_isr returns a pseudo-ISR that may include
2377                  * bits we haven't explicitly enabled so we mask the
2378                  * value to insure we only process bits we requested.
2379                  */
2380                 ath5k_hw_get_isr(ah, &status);          /* NB: clears IRQ too */
2381                 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2382                                 status, sc->imask);
2383                 status &= sc->imask; /* discard unasked for bits */
2384                 if (unlikely(status & AR5K_INT_FATAL)) {
2385                         /*
2386                          * Fatal errors are unrecoverable.
2387                          * Typically these are caused by DMA errors.
2388                          */
2389                         tasklet_schedule(&sc->restq);
2390                 } else if (unlikely(status & AR5K_INT_RXORN)) {
2391                         tasklet_schedule(&sc->restq);
2392                 } else {
2393                         if (status & AR5K_INT_SWBA) {
2394                                 /*
2395                                 * Software beacon alert--time to send a beacon.
2396                                 * Handle beacon transmission directly; deferring
2397                                 * this is too slow to meet timing constraints
2398                                 * under load.
2399                                 *
2400                                 * In IBSS mode we use this interrupt just to
2401                                 * keep track of the next TBTT (target beacon
2402                                 * transmission time) in order to detect wether
2403                                 * automatic TSF updates happened.
2404                                 */
2405                                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2406                                          /* XXX: only if VEOL suppported */
2407                                         u64 tsf = ath5k_hw_get_tsf64(ah);
2408                                         sc->nexttbtt += sc->bintval;
2409                                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2410                                                   "SWBA nexttbtt: %x hw_tu: %x "
2411                                                   "TSF: %llx\n",
2412                                                   sc->nexttbtt,
2413                                                   TSF_TO_TU(tsf),
2414                                                   (unsigned long long) tsf);
2415                                 } else {
2416                                         spin_lock(&sc->block);
2417                                         ath5k_beacon_send(sc);
2418                                         spin_unlock(&sc->block);
2419                                 }
2420                         }
2421                         if (status & AR5K_INT_RXEOL) {
2422                                 /*
2423                                 * NB: the hardware should re-read the link when
2424                                 *     RXE bit is written, but it doesn't work at
2425                                 *     least on older hardware revs.
2426                                 */
2427                                 sc->rxlink = NULL;
2428                         }
2429                         if (status & AR5K_INT_TXURN) {
2430                                 /* bump tx trigger level */
2431                                 ath5k_hw_update_tx_triglevel(ah, true);
2432                         }
2433                         if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2434                                 tasklet_schedule(&sc->rxtq);
2435                         if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2436                                         | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2437                                 tasklet_schedule(&sc->txtq);
2438                         if (status & AR5K_INT_BMISS) {
2439                         }
2440                         if (status & AR5K_INT_MIB) {
2441                                 /*
2442                                  * These stats are also used for ANI i think
2443                                  * so how about updating them more often ?
2444                                  */
2445                                 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2446                         }
2447                 }
2448         } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2449
2450         if (unlikely(!counter))
2451                 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2452
2453         return IRQ_HANDLED;
2454 }
2455
2456 static void
2457 ath5k_tasklet_reset(unsigned long data)
2458 {
2459         struct ath5k_softc *sc = (void *)data;
2460
2461         ath5k_reset_wake(sc);
2462 }
2463
2464 /*
2465  * Periodically recalibrate the PHY to account
2466  * for temperature/environment changes.
2467  */
2468 static void
2469 ath5k_calibrate(unsigned long data)
2470 {
2471         struct ath5k_softc *sc = (void *)data;
2472         struct ath5k_hw *ah = sc->ah;
2473
2474         ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2475                 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2476                 sc->curchan->hw_value);
2477
2478         if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2479                 /*
2480                  * Rfgain is out of bounds, reset the chip
2481                  * to load new gain values.
2482                  */
2483                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2484                 ath5k_reset_wake(sc);
2485         }
2486         if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2487                 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2488                         ieee80211_frequency_to_channel(
2489                                 sc->curchan->center_freq));
2490
2491         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2492                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2493 }
2494
2495
2496
2497 /***************\
2498 * LED functions *
2499 \***************/
2500
2501 static void
2502 ath5k_led_enable(struct ath5k_softc *sc)
2503 {
2504         if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2505                 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2506                 ath5k_led_off(sc);
2507         }
2508 }
2509
2510 static void
2511 ath5k_led_on(struct ath5k_softc *sc)
2512 {
2513         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2514                 return;
2515         ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2516 }
2517
2518 static void
2519 ath5k_led_off(struct ath5k_softc *sc)
2520 {
2521         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2522                 return;
2523         ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2524 }
2525
2526 static void
2527 ath5k_led_brightness_set(struct led_classdev *led_dev,
2528         enum led_brightness brightness)
2529 {
2530         struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2531                 led_dev);
2532
2533         if (brightness == LED_OFF)
2534                 ath5k_led_off(led->sc);
2535         else
2536                 ath5k_led_on(led->sc);
2537 }
2538
2539 static int
2540 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2541                    const char *name, char *trigger)
2542 {
2543         int err;
2544
2545         led->sc = sc;
2546         strncpy(led->name, name, sizeof(led->name));
2547         led->led_dev.name = led->name;
2548         led->led_dev.default_trigger = trigger;
2549         led->led_dev.brightness_set = ath5k_led_brightness_set;
2550
2551         err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2552         if (err) {
2553                 ATH5K_WARN(sc, "could not register LED %s\n", name);
2554                 led->sc = NULL;
2555         }
2556         return err;
2557 }
2558
2559 static void
2560 ath5k_unregister_led(struct ath5k_led *led)
2561 {
2562         if (!led->sc)
2563                 return;
2564         led_classdev_unregister(&led->led_dev);
2565         ath5k_led_off(led->sc);
2566         led->sc = NULL;
2567 }
2568
2569 static void
2570 ath5k_unregister_leds(struct ath5k_softc *sc)
2571 {
2572         ath5k_unregister_led(&sc->rx_led);
2573         ath5k_unregister_led(&sc->tx_led);
2574 }
2575
2576
2577 static int
2578 ath5k_init_leds(struct ath5k_softc *sc)
2579 {
2580         int ret = 0;
2581         struct ieee80211_hw *hw = sc->hw;
2582         struct pci_dev *pdev = sc->pdev;
2583         char name[ATH5K_LED_MAX_NAME_LEN + 1];
2584
2585         /*
2586          * Auto-enable soft led processing for IBM cards and for
2587          * 5211 minipci cards.
2588          */
2589         if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2590             pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2591                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2592                 sc->led_pin = 0;
2593                 sc->led_on = 0;  /* active low */
2594         }
2595         /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2596         if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2597                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2598                 sc->led_pin = 1;
2599                 sc->led_on = 1;  /* active high */
2600         }
2601         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2602                 goto out;
2603
2604         ath5k_led_enable(sc);
2605
2606         snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2607         ret = ath5k_register_led(sc, &sc->rx_led, name,
2608                 ieee80211_get_rx_led_name(hw));
2609         if (ret)
2610                 goto out;
2611
2612         snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2613         ret = ath5k_register_led(sc, &sc->tx_led, name,
2614                 ieee80211_get_tx_led_name(hw));
2615 out:
2616         return ret;
2617 }
2618
2619
2620 /********************\
2621 * Mac80211 functions *
2622 \********************/
2623
2624 static int
2625 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2626 {
2627         struct ath5k_softc *sc = hw->priv;
2628         struct ath5k_buf *bf;
2629         unsigned long flags;
2630         int hdrlen;
2631         int padsize;
2632
2633         ath5k_debug_dump_skb(sc, skb, "TX  ", 1);
2634
2635         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2636                 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2637
2638         /*
2639          * the hardware expects the header padded to 4 byte boundaries
2640          * if this is not the case we add the padding after the header
2641          */
2642         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2643         padsize = ath5k_pad_size(hdrlen);
2644         if (padsize) {
2645
2646                 if (skb_headroom(skb) < padsize) {
2647                         ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2648                                   " headroom to pad %d\n", hdrlen, padsize);
2649                         return NETDEV_TX_BUSY;
2650                 }
2651                 skb_push(skb, padsize);
2652                 memmove(skb->data, skb->data+padsize, hdrlen);
2653         }
2654
2655         spin_lock_irqsave(&sc->txbuflock, flags);
2656         if (list_empty(&sc->txbuf)) {
2657                 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2658                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2659                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2660                 return NETDEV_TX_BUSY;
2661         }
2662         bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2663         list_del(&bf->list);
2664         sc->txbuf_len--;
2665         if (list_empty(&sc->txbuf))
2666                 ieee80211_stop_queues(hw);
2667         spin_unlock_irqrestore(&sc->txbuflock, flags);
2668
2669         bf->skb = skb;
2670
2671         if (ath5k_txbuf_setup(sc, bf)) {
2672                 bf->skb = NULL;
2673                 spin_lock_irqsave(&sc->txbuflock, flags);
2674                 list_add_tail(&bf->list, &sc->txbuf);
2675                 sc->txbuf_len++;
2676                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2677                 dev_kfree_skb_any(skb);
2678                 return NETDEV_TX_OK;
2679         }
2680
2681         return NETDEV_TX_OK;
2682 }
2683
2684 static int
2685 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2686 {
2687         struct ath5k_hw *ah = sc->ah;
2688         int ret;
2689
2690         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2691
2692         if (stop) {
2693                 ath5k_hw_set_imr(ah, 0);
2694                 ath5k_txq_cleanup(sc);
2695                 ath5k_rx_stop(sc);
2696         }
2697         ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2698         if (ret) {
2699                 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2700                 goto err;
2701         }
2702
2703         /*
2704          * This is needed only to setup initial state
2705          * but it's best done after a reset.
2706          */
2707         ath5k_hw_set_txpower_limit(sc->ah, 0);
2708
2709         ret = ath5k_rx_start(sc);
2710         if (ret) {
2711                 ATH5K_ERR(sc, "can't start recv logic\n");
2712                 goto err;
2713         }
2714
2715         /*
2716          * Change channels and update the h/w rate map if we're switching;
2717          * e.g. 11a to 11b/g.
2718          *
2719          * We may be doing a reset in response to an ioctl that changes the
2720          * channel so update any state that might change as a result.
2721          *
2722          * XXX needed?
2723          */
2724 /*      ath5k_chan_change(sc, c); */
2725
2726         ath5k_beacon_config(sc);
2727         /* intrs are enabled by ath5k_beacon_config */
2728
2729         return 0;
2730 err:
2731         return ret;
2732 }
2733
2734 static int
2735 ath5k_reset_wake(struct ath5k_softc *sc)
2736 {
2737         int ret;
2738
2739         ret = ath5k_reset(sc, true, true);
2740         if (!ret)
2741                 ieee80211_wake_queues(sc->hw);
2742
2743         return ret;
2744 }
2745
2746 static int ath5k_start(struct ieee80211_hw *hw)
2747 {
2748         return ath5k_init(hw->priv, false);
2749 }
2750
2751 static void ath5k_stop(struct ieee80211_hw *hw)
2752 {
2753         ath5k_stop_hw(hw->priv, false);
2754 }
2755
2756 static int ath5k_add_interface(struct ieee80211_hw *hw,
2757                 struct ieee80211_if_init_conf *conf)
2758 {
2759         struct ath5k_softc *sc = hw->priv;
2760         int ret;
2761
2762         mutex_lock(&sc->lock);
2763         if (sc->vif) {
2764                 ret = 0;
2765                 goto end;
2766         }
2767
2768         sc->vif = conf->vif;
2769
2770         switch (conf->type) {
2771         case NL80211_IFTYPE_AP:
2772         case NL80211_IFTYPE_STATION:
2773         case NL80211_IFTYPE_ADHOC:
2774         case NL80211_IFTYPE_MESH_POINT:
2775         case NL80211_IFTYPE_MONITOR:
2776                 sc->opmode = conf->type;
2777                 break;
2778         default:
2779                 ret = -EOPNOTSUPP;
2780                 goto end;
2781         }
2782
2783         /* Set to a reasonable value. Note that this will
2784          * be set to mac80211's value at ath5k_config(). */
2785         sc->bintval = 1000;
2786         ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2787
2788         ret = 0;
2789 end:
2790         mutex_unlock(&sc->lock);
2791         return ret;
2792 }
2793
2794 static void
2795 ath5k_remove_interface(struct ieee80211_hw *hw,
2796                         struct ieee80211_if_init_conf *conf)
2797 {
2798         struct ath5k_softc *sc = hw->priv;
2799         u8 mac[ETH_ALEN] = {};
2800
2801         mutex_lock(&sc->lock);
2802         if (sc->vif != conf->vif)
2803                 goto end;
2804
2805         ath5k_hw_set_lladdr(sc->ah, mac);
2806         sc->vif = NULL;
2807 end:
2808         mutex_unlock(&sc->lock);
2809 }
2810
2811 /*
2812  * TODO: Phy disable/diversity etc
2813  */
2814 static int
2815 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2816 {
2817         struct ath5k_softc *sc = hw->priv;
2818         struct ieee80211_conf *conf = &hw->conf;
2819         int ret;
2820
2821         mutex_lock(&sc->lock);
2822
2823         sc->bintval = conf->beacon_int;
2824         sc->power_level = conf->power_level;
2825
2826         ret = ath5k_chan_set(sc, conf->channel);
2827
2828         mutex_unlock(&sc->lock);
2829         return ret;
2830 }
2831
2832 static int
2833 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2834                         struct ieee80211_if_conf *conf)
2835 {
2836         struct ath5k_softc *sc = hw->priv;
2837         struct ath5k_hw *ah = sc->ah;
2838         int ret;
2839
2840         mutex_lock(&sc->lock);
2841         if (sc->vif != vif) {
2842                 ret = -EIO;
2843                 goto unlock;
2844         }
2845         if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2846                 /* Cache for later use during resets */
2847                 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2848                 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2849                  * a clean way of letting us retrieve this yet. */
2850                 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2851                 mmiowb();
2852         }
2853         if (conf->changed & IEEE80211_IFCC_BEACON &&
2854                         (vif->type == NL80211_IFTYPE_ADHOC ||
2855                          vif->type == NL80211_IFTYPE_MESH_POINT ||
2856                          vif->type == NL80211_IFTYPE_AP)) {
2857                 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2858                 if (!beacon) {
2859                         ret = -ENOMEM;
2860                         goto unlock;
2861                 }
2862                 ath5k_beacon_update(sc, beacon);
2863         }
2864         mutex_unlock(&sc->lock);
2865
2866         return ath5k_reset_wake(sc);
2867 unlock:
2868         mutex_unlock(&sc->lock);
2869         return ret;
2870 }
2871
2872 #define SUPPORTED_FIF_FLAGS \
2873         FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
2874         FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2875         FIF_BCN_PRBRESP_PROMISC
2876 /*
2877  * o always accept unicast, broadcast, and multicast traffic
2878  * o multicast traffic for all BSSIDs will be enabled if mac80211
2879  *   says it should be
2880  * o maintain current state of phy ofdm or phy cck error reception.
2881  *   If the hardware detects any of these type of errors then
2882  *   ath5k_hw_get_rx_filter() will pass to us the respective
2883  *   hardware filters to be able to receive these type of frames.
2884  * o probe request frames are accepted only when operating in
2885  *   hostap, adhoc, or monitor modes
2886  * o enable promiscuous mode according to the interface state
2887  * o accept beacons:
2888  *   - when operating in adhoc mode so the 802.11 layer creates
2889  *     node table entries for peers,
2890  *   - when operating in station mode for collecting rssi data when
2891  *     the station is otherwise quiet, or
2892  *   - when scanning
2893  */
2894 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2895                 unsigned int changed_flags,
2896                 unsigned int *new_flags,
2897                 int mc_count, struct dev_mc_list *mclist)
2898 {
2899         struct ath5k_softc *sc = hw->priv;
2900         struct ath5k_hw *ah = sc->ah;
2901         u32 mfilt[2], val, rfilt;
2902         u8 pos;
2903         int i;
2904
2905         mfilt[0] = 0;
2906         mfilt[1] = 0;
2907
2908         /* Only deal with supported flags */
2909         changed_flags &= SUPPORTED_FIF_FLAGS;
2910         *new_flags &= SUPPORTED_FIF_FLAGS;
2911
2912         /* If HW detects any phy or radar errors, leave those filters on.
2913          * Also, always enable Unicast, Broadcasts and Multicast
2914          * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2915         rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2916                 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2917                 AR5K_RX_FILTER_MCAST);
2918
2919         if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2920                 if (*new_flags & FIF_PROMISC_IN_BSS) {
2921                         rfilt |= AR5K_RX_FILTER_PROM;
2922                         __set_bit(ATH_STAT_PROMISC, sc->status);
2923                 } else {
2924                         __clear_bit(ATH_STAT_PROMISC, sc->status);
2925                 }
2926         }
2927
2928         /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2929         if (*new_flags & FIF_ALLMULTI) {
2930                 mfilt[0] =  ~0;
2931                 mfilt[1] =  ~0;
2932         } else {
2933                 for (i = 0; i < mc_count; i++) {
2934                         if (!mclist)
2935                                 break;
2936                         /* calculate XOR of eight 6-bit values */
2937                         val = get_unaligned_le32(mclist->dmi_addr + 0);
2938                         pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2939                         val = get_unaligned_le32(mclist->dmi_addr + 3);
2940                         pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2941                         pos &= 0x3f;
2942                         mfilt[pos / 32] |= (1 << (pos % 32));
2943                         /* XXX: we might be able to just do this instead,
2944                         * but not sure, needs testing, if we do use this we'd
2945                         * neet to inform below to not reset the mcast */
2946                         /* ath5k_hw_set_mcast_filterindex(ah,
2947                          *      mclist->dmi_addr[5]); */
2948                         mclist = mclist->next;
2949                 }
2950         }
2951
2952         /* This is the best we can do */
2953         if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2954                 rfilt |= AR5K_RX_FILTER_PHYERR;
2955
2956         /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2957         * and probes for any BSSID, this needs testing */
2958         if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2959                 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2960
2961         /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2962          * set we should only pass on control frames for this
2963          * station. This needs testing. I believe right now this
2964          * enables *all* control frames, which is OK.. but
2965          * but we should see if we can improve on granularity */
2966         if (*new_flags & FIF_CONTROL)
2967                 rfilt |= AR5K_RX_FILTER_CONTROL;
2968
2969         /* Additional settings per mode -- this is per ath5k */
2970
2971         /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2972
2973         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2974                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2975                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2976         if (sc->opmode != NL80211_IFTYPE_STATION)
2977                 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2978         if (sc->opmode != NL80211_IFTYPE_AP &&
2979                 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2980                 test_bit(ATH_STAT_PROMISC, sc->status))
2981                 rfilt |= AR5K_RX_FILTER_PROM;
2982         if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
2983                 sc->opmode == NL80211_IFTYPE_ADHOC ||
2984                 sc->opmode == NL80211_IFTYPE_AP)
2985                 rfilt |= AR5K_RX_FILTER_BEACON;
2986         if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2987                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2988                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2989
2990         /* Set filters */
2991         ath5k_hw_set_rx_filter(ah, rfilt);
2992
2993         /* Set multicast bits */
2994         ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2995         /* Set the cached hw filter flags, this will alter actually
2996          * be set in HW */
2997         sc->filter_flags = rfilt;
2998 }
2999
3000 static int
3001 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3002                 const u8 *local_addr, const u8 *addr,
3003                 struct ieee80211_key_conf *key)
3004 {
3005         struct ath5k_softc *sc = hw->priv;
3006         int ret = 0;
3007
3008         if (modparam_nohwcrypt)
3009                 return -EOPNOTSUPP;
3010
3011         switch (key->alg) {
3012         case ALG_WEP:
3013         case ALG_TKIP:
3014                 break;
3015         case ALG_CCMP:
3016                 return -EOPNOTSUPP;
3017         default:
3018                 WARN_ON(1);
3019                 return -EINVAL;
3020         }
3021
3022         mutex_lock(&sc->lock);
3023
3024         switch (cmd) {
3025         case SET_KEY:
3026                 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
3027                 if (ret) {
3028                         ATH5K_ERR(sc, "can't set the key\n");
3029                         goto unlock;
3030                 }
3031                 __set_bit(key->keyidx, sc->keymap);
3032                 key->hw_key_idx = key->keyidx;
3033                 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3034                                IEEE80211_KEY_FLAG_GENERATE_MMIC);
3035                 break;
3036         case DISABLE_KEY:
3037                 ath5k_hw_reset_key(sc->ah, key->keyidx);
3038                 __clear_bit(key->keyidx, sc->keymap);
3039                 break;
3040         default:
3041                 ret = -EINVAL;
3042                 goto unlock;
3043         }
3044
3045 unlock:
3046         mmiowb();
3047         mutex_unlock(&sc->lock);
3048         return ret;
3049 }
3050
3051 static int
3052 ath5k_get_stats(struct ieee80211_hw *hw,
3053                 struct ieee80211_low_level_stats *stats)
3054 {
3055         struct ath5k_softc *sc = hw->priv;
3056         struct ath5k_hw *ah = sc->ah;
3057
3058         /* Force update */
3059         ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3060
3061         memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3062
3063         return 0;
3064 }
3065
3066 static int
3067 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3068                 struct ieee80211_tx_queue_stats *stats)
3069 {
3070         struct ath5k_softc *sc = hw->priv;
3071
3072         memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3073
3074         return 0;
3075 }
3076
3077 static u64
3078 ath5k_get_tsf(struct ieee80211_hw *hw)
3079 {
3080         struct ath5k_softc *sc = hw->priv;
3081
3082         return ath5k_hw_get_tsf64(sc->ah);
3083 }
3084
3085 static void
3086 ath5k_reset_tsf(struct ieee80211_hw *hw)
3087 {
3088         struct ath5k_softc *sc = hw->priv;
3089
3090         /*
3091          * in IBSS mode we need to update the beacon timers too.
3092          * this will also reset the TSF if we call it with 0
3093          */
3094         if (sc->opmode == NL80211_IFTYPE_ADHOC)
3095                 ath5k_beacon_update_timers(sc, 0);
3096         else
3097                 ath5k_hw_reset_tsf(sc->ah);
3098 }
3099
3100 static int
3101 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3102 {
3103         unsigned long flags;
3104         int ret;
3105
3106         ath5k_debug_dump_skb(sc, skb, "BC  ", 1);
3107
3108         spin_lock_irqsave(&sc->block, flags);
3109         ath5k_txbuf_free(sc, sc->bbuf);
3110         sc->bbuf->skb = skb;
3111         ret = ath5k_beacon_setup(sc, sc->bbuf);
3112         if (ret)
3113                 sc->bbuf->skb = NULL;
3114         spin_unlock_irqrestore(&sc->block, flags);
3115         if (!ret) {
3116                 ath5k_beacon_config(sc);
3117                 mmiowb();
3118         }
3119
3120         return ret;
3121 }
3122 static void
3123 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3124 {
3125         struct ath5k_softc *sc = hw->priv;
3126         struct ath5k_hw *ah = sc->ah;
3127         u32 rfilt;
3128         rfilt = ath5k_hw_get_rx_filter(ah);
3129         if (enable)
3130                 rfilt |= AR5K_RX_FILTER_BEACON;
3131         else
3132                 rfilt &= ~AR5K_RX_FILTER_BEACON;
3133         ath5k_hw_set_rx_filter(ah, rfilt);
3134         sc->filter_flags = rfilt;
3135 }
3136
3137 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3138                                     struct ieee80211_vif *vif,
3139                                     struct ieee80211_bss_conf *bss_conf,
3140                                     u32 changes)
3141 {
3142         struct ath5k_softc *sc = hw->priv;
3143         if (changes & BSS_CHANGED_ASSOC) {
3144                 mutex_lock(&sc->lock);
3145                 sc->assoc = bss_conf->assoc;
3146                 if (sc->opmode == NL80211_IFTYPE_STATION)
3147                         set_beacon_filter(hw, sc->assoc);
3148                 mutex_unlock(&sc->lock);
3149         }
3150 }