drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "initvals.h"
  23
  24 #define ATH9K_CLOCK_RATE_CCK            22
  25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  27
  28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  30
  31 MODULE_AUTHOR("Atheros Communications");
  32 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  33 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  34 MODULE_LICENSE("Dual BSD/GPL");
  35
  36 static int __init ath9k_init(void)
  37 {
  38         return 0;
  39 }
  40 module_init(ath9k_init);
  41
  42 static void __exit ath9k_exit(void)
  43 {
  44         return;
  45 }
  46 module_exit(ath9k_exit);
  47
  48 /********************/
  49 /* Helper Functions */
  50 /********************/
  51
  52 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  53 {
  54         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  55
  56         if (!ah->curchan) /* should really check for CCK instead */
  57                 return usecs *ATH9K_CLOCK_RATE_CCK;
  58         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  59                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  60         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  61 }
  62
  63 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  64 {
  65         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  66
  67         if (conf_is_ht40(conf))
  68                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  69         else
  70                 return ath9k_hw_mac_clks(ah, usecs);
  71 }
  72
  73 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  74 {
  75         int i;
  76
  77         BUG_ON(timeout < AH_TIME_QUANTUM);
  78
  79         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  80                 if ((REG_READ(ah, reg) & mask) == val)
  81                         return true;
  82
  83                 udelay(AH_TIME_QUANTUM);
  84         }
  85
  86         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
  87                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  88                   timeout, reg, REG_READ(ah, reg), mask, val);
  89
  90         return false;
  91 }
  92 EXPORT_SYMBOL(ath9k_hw_wait);
  93
  94 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
  95 {
  96         u32 retval;
  97         int i;
  98
  99         for (i = 0, retval = 0; i < n; i++) {
 100                 retval = (retval << 1) | (val & 1);
 101                 val >>= 1;
 102         }
 103         return retval;
 104 }
 105
 106 bool ath9k_get_channel_edges(struct ath_hw *ah,
 107                              u16 flags, u16 *low,
 108                              u16 *high)
 109 {
 110         struct ath9k_hw_capabilities *pCap = &ah->caps;
 111
 112         if (flags & CHANNEL_5GHZ) {
 113                 *low = pCap->low_5ghz_chan;
 114                 *high = pCap->high_5ghz_chan;
 115                 return true;
 116         }
 117         if ((flags & CHANNEL_2GHZ)) {
 118                 *low = pCap->low_2ghz_chan;
 119                 *high = pCap->high_2ghz_chan;
 120                 return true;
 121         }
 122         return false;
 123 }
 124
 125 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 126                            u8 phy, int kbps,
 127                            u32 frameLen, u16 rateix,
 128                            bool shortPreamble)
 129 {
 130         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 131
 132         if (kbps == 0)
 133                 return 0;
 134
 135         switch (phy) {
 136         case WLAN_RC_PHY_CCK:
 137                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 138                 if (shortPreamble)
 139                         phyTime >>= 1;
 140                 numBits = frameLen << 3;
 141                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 142                 break;
 143         case WLAN_RC_PHY_OFDM:
 144                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 145                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 146                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 147                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 148                         txTime = OFDM_SIFS_TIME_QUARTER
 149                                 + OFDM_PREAMBLE_TIME_QUARTER
 150                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 151                 } else if (ah->curchan &&
 152                            IS_CHAN_HALF_RATE(ah->curchan)) {
 153                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 154                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 155                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 156                         txTime = OFDM_SIFS_TIME_HALF +
 157                                 OFDM_PREAMBLE_TIME_HALF
 158                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 159                 } else {
 160                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 161                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 162                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 163                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 164                                 + (numSymbols * OFDM_SYMBOL_TIME);
 165                 }
 166                 break;
 167         default:
 168                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 169                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 170                 txTime = 0;
 171                 break;
 172         }
 173
 174         return txTime;
 175 }
 176 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 177
 178 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 179                                   struct ath9k_channel *chan,
 180                                   struct chan_centers *centers)
 181 {
 182         int8_t extoff;
 183
 184         if (!IS_CHAN_HT40(chan)) {
 185                 centers->ctl_center = centers->ext_center =
 186                         centers->synth_center = chan->channel;
 187                 return;
 188         }
 189
 190         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 191             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 192                 centers->synth_center =
 193                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 194                 extoff = 1;
 195         } else {
 196                 centers->synth_center =
 197                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 198                 extoff = -1;
 199         }
 200
 201         centers->ctl_center =
 202                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 203         /* 25 MHz spacing is supported by hw but not on upper layers */
 204         centers->ext_center =
 205                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 206 }
 207
 208 /******************/
 209 /* Chip Revisions */
 210 /******************/
 211
 212 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 213 {
 214         u32 val;
 215
 216         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 217
 218         if (val == 0xFF) {
 219                 val = REG_READ(ah, AR_SREV);
 220                 ah->hw_version.macVersion =
 221                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 222                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 223                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 224         } else {
 225                 if (!AR_SREV_9100(ah))
 226                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 227
 228                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 229
 230                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 231                         ah->is_pciexpress = true;
 232         }
 233 }
 234
 235 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 236 {
 237         u32 val;
 238         int i;
 239
 240         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 241
 242         for (i = 0; i < 8; i++)
 243                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 244         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 245         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 246
 247         return ath9k_hw_reverse_bits(val, 8);
 248 }
 249
 250 /************************************/
 251 /* HW Attach, Detach, Init Routines */
 252 /************************************/
 253
 254 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 255 {
 256         if (AR_SREV_9100(ah))
 257                 return;
 258
 259         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 260         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 261         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 262         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 263         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 264         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 265         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 266         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 267         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 268
 269         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 270 }
 271
 272 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 273 {
 274         struct ath_common *common = ath9k_hw_common(ah);
 275         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 276         u32 regHold[2];
 277         u32 patternData[4] = { 0x55555555,
 278                                0xaaaaaaaa,
 279                                0x66666666,
 280                                0x99999999 };
 281         int i, j;
 282
 283         for (i = 0; i < 2; i++) {
 284                 u32 addr = regAddr[i];
 285                 u32 wrData, rdData;
 286
 287                 regHold[i] = REG_READ(ah, addr);
 288                 for (j = 0; j < 0x100; j++) {
 289                         wrData = (j << 16) | j;
 290                         REG_WRITE(ah, addr, wrData);
 291                         rdData = REG_READ(ah, addr);
 292                         if (rdData != wrData) {
 293                                 ath_print(common, ATH_DBG_FATAL,
 294                                           "address test failed "
 295                                           "addr: 0x%08x - wr:0x%08x != "
 296                                           "rd:0x%08x\n",
 297                                           addr, wrData, rdData);
 298                                 return false;
 299                         }
 300                 }
 301                 for (j = 0; j < 4; j++) {
 302                         wrData = patternData[j];
 303                         REG_WRITE(ah, addr, wrData);
 304                         rdData = REG_READ(ah, addr);
 305                         if (wrData != rdData) {
 306                                 ath_print(common, ATH_DBG_FATAL,
 307                                           "address test failed "
 308                                           "addr: 0x%08x - wr:0x%08x != "
 309                                           "rd:0x%08x\n",
 310                                           addr, wrData, rdData);
 311                                 return false;
 312                         }
 313                 }
 314                 REG_WRITE(ah, regAddr[i], regHold[i]);
 315         }
 316         udelay(100);
 317
 318         return true;
 319 }
 320
 321 static void ath9k_hw_init_config(struct ath_hw *ah)
 322 {
 323         int i;
 324
 325         ah->config.dma_beacon_response_time = 2;
 326         ah->config.sw_beacon_response_time = 10;
 327         ah->config.additional_swba_backoff = 0;
 328         ah->config.ack_6mb = 0x0;
 329         ah->config.cwm_ignore_extcca = 0;
 330         ah->config.pcie_powersave_enable = 0;
 331         ah->config.pcie_clock_req = 0;
 332         ah->config.pcie_waen = 0;
 333         ah->config.analog_shiftreg = 1;
 334         ah->config.ofdm_trig_low = 200;
 335         ah->config.ofdm_trig_high = 500;
 336         ah->config.cck_trig_high = 200;
 337         ah->config.cck_trig_low = 100;
 338         ah->config.enable_ani = 1;
 339
 340         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 341                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 342                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 343         }
 344
 345         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 346                 ah->config.ht_enable = 1;
 347         else
 348                 ah->config.ht_enable = 0;
 349
 350         ah->config.rx_intr_mitigation = true;
 351
 352         /*
 353          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 354          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 355          * This means we use it for all AR5416 devices, and the few
 356          * minor PCI AR9280 devices out there.
 357          *
 358          * Serialization is required because these devices do not handle
 359          * well the case of two concurrent reads/writes due to the latency
 360          * involved. During one read/write another read/write can be issued
 361          * on another CPU while the previous read/write may still be working
 362          * on our hardware, if we hit this case the hardware poops in a loop.
 363          * We prevent this by serializing reads and writes.
 364          *
 365          * This issue is not present on PCI-Express devices or pre-AR5416
 366          * devices (legacy, 802.11abg).
 367          */
 368         if (num_possible_cpus() > 1)
 369                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 370 }
 371 EXPORT_SYMBOL(ath9k_hw_init);
 372
 373 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 374 {
 375         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 376
 377         regulatory->country_code = CTRY_DEFAULT;
 378         regulatory->power_limit = MAX_RATE_POWER;
 379         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 380
 381         ah->hw_version.magic = AR5416_MAGIC;
 382         ah->hw_version.subvendorid = 0;
 383
 384         ah->ah_flags = 0;
 385         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 386                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 387         if (!AR_SREV_9100(ah))
 388                 ah->ah_flags = AH_USE_EEPROM;
 389
 390         ah->atim_window = 0;
 391         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 392         ah->beacon_interval = 100;
 393         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 394         ah->slottime = (u32) -1;
 395         ah->globaltxtimeout = (u32) -1;
 396         ah->power_mode = ATH9K_PM_UNDEFINED;
 397 }
 398
 399 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 400 {
 401         u32 val;
 402
 403         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 404
 405         val = ath9k_hw_get_radiorev(ah);
 406         switch (val & AR_RADIO_SREV_MAJOR) {
 407         case 0:
 408                 val = AR_RAD5133_SREV_MAJOR;
 409                 break;
 410         case AR_RAD5133_SREV_MAJOR:
 411         case AR_RAD5122_SREV_MAJOR:
 412         case AR_RAD2133_SREV_MAJOR:
 413         case AR_RAD2122_SREV_MAJOR:
 414                 break;
 415         default:
 416                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 417                           "Radio Chip Rev 0x%02X not supported\n",
 418                           val & AR_RADIO_SREV_MAJOR);
 419                 return -EOPNOTSUPP;
 420         }
 421
 422         ah->hw_version.analog5GhzRev = val;
 423
 424         return 0;
 425 }
 426
 427 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 428 {
 429         struct ath_common *common = ath9k_hw_common(ah);
 430         u32 sum;
 431         int i;
 432         u16 eeval;
 433
 434         sum = 0;
 435         for (i = 0; i < 3; i++) {
 436                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 437                 sum += eeval;
 438                 common->macaddr[2 * i] = eeval >> 8;
 439                 common->macaddr[2 * i + 1] = eeval & 0xff;
 440         }
 441         if (sum == 0 || sum == 0xffff * 3)
 442                 return -EADDRNOTAVAIL;
 443
 444         return 0;
 445 }
 446
 447 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 448 {
 449         u32 rxgain_type;
 450
 451         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 452                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 453
 454                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 455                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 456                         ar9280Modes_backoff_13db_rxgain_9280_2,
 457                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 458                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 459                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 460                         ar9280Modes_backoff_23db_rxgain_9280_2,
 461                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 462                 else
 463                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 464                         ar9280Modes_original_rxgain_9280_2,
 465                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 466         } else {
 467                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 468                         ar9280Modes_original_rxgain_9280_2,
 469                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 470         }
 471 }
 472
 473 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 474 {
 475         u32 txgain_type;
 476
 477         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 478                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 479
 480                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 481                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 482                         ar9280Modes_high_power_tx_gain_9280_2,
 483                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 484                 else
 485                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 486                         ar9280Modes_original_tx_gain_9280_2,
 487                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 488         } else {
 489                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 490                 ar9280Modes_original_tx_gain_9280_2,
 491                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 492         }
 493 }
 494
 495 static int ath9k_hw_post_init(struct ath_hw *ah)
 496 {
 497         int ecode;
 498
 499         if (!AR_SREV_9271(ah)) {
 500                 if (!ath9k_hw_chip_test(ah))
 501                         return -ENODEV;
 502         }
 503
 504         ecode = ath9k_hw_rf_claim(ah);
 505         if (ecode != 0)
 506                 return ecode;
 507
 508         ecode = ath9k_hw_eeprom_init(ah);
 509         if (ecode != 0)
 510                 return ecode;
 511
 512         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 513                   "Eeprom VER: %d, REV: %d\n",
 514                   ah->eep_ops->get_eeprom_ver(ah),
 515                   ah->eep_ops->get_eeprom_rev(ah));
 516
 517         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 518                 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 519                 if (ecode) {
 520                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 521                                   "Failed allocating banks for "
 522                                   "external radio\n");
 523                         return ecode;
 524                 }
 525         }
 526
 527         if (!AR_SREV_9100(ah)) {
 528                 ath9k_hw_ani_setup(ah);
 529                 ath9k_hw_ani_init(ah);
 530         }
 531
 532         return 0;
 533 }
 534
 535 static bool ath9k_hw_devid_supported(u16 devid)
 536 {
 537         switch (devid) {
 538         case AR5416_DEVID_PCI:
 539         case AR5416_DEVID_PCIE:
 540         case AR5416_AR9100_DEVID:
 541         case AR9160_DEVID_PCI:
 542         case AR9280_DEVID_PCI:
 543         case AR9280_DEVID_PCIE:
 544         case AR9285_DEVID_PCIE:
 545         case AR5416_DEVID_AR9287_PCI:
 546         case AR5416_DEVID_AR9287_PCIE:
 547         case AR2427_DEVID_PCIE:
 548                 return true;
 549         default:
 550                 break;
 551         }
 552         return false;
 553 }
 554
 555 static bool ath9k_hw_macversion_supported(u32 macversion)
 556 {
 557         switch (macversion) {
 558         case AR_SREV_VERSION_5416_PCI:
 559         case AR_SREV_VERSION_5416_PCIE:
 560         case AR_SREV_VERSION_9160:
 561         case AR_SREV_VERSION_9100:
 562         case AR_SREV_VERSION_9280:
 563         case AR_SREV_VERSION_9285:
 564         case AR_SREV_VERSION_9287:
 565         case AR_SREV_VERSION_9271:
 566                 return true;
 567         default:
 568                 break;
 569         }
 570         return false;
 571 }
 572
 573 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 574 {
 575         if (AR_SREV_9160_10_OR_LATER(ah)) {
 576                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 577                         ah->iq_caldata.calData = &iq_cal_single_sample;
 578                         ah->adcgain_caldata.calData =
 579                                 &adc_gain_cal_single_sample;
 580                         ah->adcdc_caldata.calData =
 581                                 &adc_dc_cal_single_sample;
 582                         ah->adcdc_calinitdata.calData =
 583                                 &adc_init_dc_cal;
 584                 } else {
 585                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 586                         ah->adcgain_caldata.calData =
 587                                 &adc_gain_cal_multi_sample;
 588                         ah->adcdc_caldata.calData =
 589                                 &adc_dc_cal_multi_sample;
 590                         ah->adcdc_calinitdata.calData =
 591                                 &adc_init_dc_cal;
 592                 }
 593                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 594         }
 595 }
 596
 597 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 598 {
 599         if (AR_SREV_9271(ah)) {
 600                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
 601                                ARRAY_SIZE(ar9271Modes_9271), 6);
 602                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
 603                                ARRAY_SIZE(ar9271Common_9271), 2);
 604                 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
 605                                ar9271Common_normal_cck_fir_coeff_9271,
 606                                ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
 607                 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
 608                                ar9271Common_japan_2484_cck_fir_coeff_9271,
 609                                ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
 610                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
 611                                ar9271Modes_9271_1_0_only,
 612                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
 613                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
 614                                ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
 615                 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
 616                                ar9271Modes_high_power_tx_gain_9271,
 617                                ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
 618                 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
 619                                ar9271Modes_normal_power_tx_gain_9271,
 620                                ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
 621                 return;
 622         }
 623
 624         if (AR_SREV_9287_11_OR_LATER(ah)) {
 625                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 626                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 627                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 628                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 629                 if (ah->config.pcie_clock_req)
 630                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 631                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 632                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 633                 else
 634                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 635                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 636                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 637                                         2);
 638         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 639                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 640                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 641                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 642                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 643
 644                 if (ah->config.pcie_clock_req)
 645                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 646                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 647                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 648                 else
 649                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 650                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 651                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 652                                   2);
 653         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 654
 655
 656                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 657                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 658                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 659                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 660
 661                 if (ah->config.pcie_clock_req) {
 662                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 663                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 664                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 665                 } else {
 666                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 667                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 668                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 669                                   2);
 670                 }
 671         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 672                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 673                                ARRAY_SIZE(ar9285Modes_9285), 6);
 674                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 675                                ARRAY_SIZE(ar9285Common_9285), 2);
 676
 677                 if (ah->config.pcie_clock_req) {
 678                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 679                         ar9285PciePhy_clkreq_off_L1_9285,
 680                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 681                 } else {
 682                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 683                         ar9285PciePhy_clkreq_always_on_L1_9285,
 684                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 685                 }
 686         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 687                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 688                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 689                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 690                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 691
 692                 if (ah->config.pcie_clock_req) {
 693                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 694                                ar9280PciePhy_clkreq_off_L1_9280,
 695                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 696                 } else {
 697                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 698                                ar9280PciePhy_clkreq_always_on_L1_9280,
 699                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 700                 }
 701                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 702                                ar9280Modes_fast_clock_9280_2,
 703                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 704         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 705                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 706                                ARRAY_SIZE(ar9280Modes_9280), 6);
 707                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 708                                ARRAY_SIZE(ar9280Common_9280), 2);
 709         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 710                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 711                                ARRAY_SIZE(ar5416Modes_9160), 6);
 712                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 713                                ARRAY_SIZE(ar5416Common_9160), 2);
 714                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 715                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 716                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 717                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 718                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 719                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 720                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 721                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 722                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 723                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 724                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 725                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 726                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 727                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 728                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 729                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 730                 if (AR_SREV_9160_11(ah)) {
 731                         INIT_INI_ARRAY(&ah->iniAddac,
 732                                        ar5416Addac_91601_1,
 733                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 734                 } else {
 735                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 736                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 737                 }
 738         } else if (AR_SREV_9100_OR_LATER(ah)) {
 739                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 740                                ARRAY_SIZE(ar5416Modes_9100), 6);
 741                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 742                                ARRAY_SIZE(ar5416Common_9100), 2);
 743                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 744                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 745                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 746                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 747                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 748                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 749                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 750                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 751                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 752                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 753                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 754                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 755                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 756                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 757                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 758                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 759                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 760                                ARRAY_SIZE(ar5416Addac_9100), 2);
 761         } else {
 762                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 763                                ARRAY_SIZE(ar5416Modes), 6);
 764                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 765                                ARRAY_SIZE(ar5416Common), 2);
 766                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 767                                ARRAY_SIZE(ar5416Bank0), 2);
 768                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 769                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 770                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 771                                ARRAY_SIZE(ar5416Bank1), 2);
 772                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 773                                ARRAY_SIZE(ar5416Bank2), 2);
 774                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 775                                ARRAY_SIZE(ar5416Bank3), 3);
 776                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 777                                ARRAY_SIZE(ar5416Bank6), 3);
 778                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 779                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 780                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 781                                ARRAY_SIZE(ar5416Bank7), 2);
 782                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 783                                ARRAY_SIZE(ar5416Addac), 2);
 784         }
 785 }
 786
 787 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 788 {
 789         if (AR_SREV_9287_11_OR_LATER(ah))
 790                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 791                 ar9287Modes_rx_gain_9287_1_1,
 792                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 793         else if (AR_SREV_9287_10(ah))
 794                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 795                 ar9287Modes_rx_gain_9287_1_0,
 796                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 797         else if (AR_SREV_9280_20(ah))
 798                 ath9k_hw_init_rxgain_ini(ah);
 799
 800         if (AR_SREV_9287_11_OR_LATER(ah)) {
 801                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 802                 ar9287Modes_tx_gain_9287_1_1,
 803                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 804         } else if (AR_SREV_9287_10(ah)) {
 805                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 806                 ar9287Modes_tx_gain_9287_1_0,
 807                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 808         } else if (AR_SREV_9280_20(ah)) {
 809                 ath9k_hw_init_txgain_ini(ah);
 810         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 811                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 812
 813                 /* txgain table */
 814                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 815                         if (AR_SREV_9285E_20(ah)) {
 816                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 817                                 ar9285Modes_XE2_0_high_power,
 818                                 ARRAY_SIZE(
 819                                   ar9285Modes_XE2_0_high_power), 6);
 820                         } else {
 821                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 822                                 ar9285Modes_high_power_tx_gain_9285_1_2,
 823                                 ARRAY_SIZE(
 824                                   ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 825                         }
 826                 } else {
 827                         if (AR_SREV_9285E_20(ah)) {
 828                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 829                                 ar9285Modes_XE2_0_normal_power,
 830                                 ARRAY_SIZE(
 831                                   ar9285Modes_XE2_0_normal_power), 6);
 832                         } else {
 833                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 834                                 ar9285Modes_original_tx_gain_9285_1_2,
 835                                 ARRAY_SIZE(
 836                                   ar9285Modes_original_tx_gain_9285_1_2), 6);
 837                         }
 838                 }
 839         }
 840 }
 841
 842 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
 843 {
 844         struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
 845         struct ath_common *common = ath9k_hw_common(ah);
 846
 847         ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
 848                                  (ah->eep_map != EEP_MAP_4KBITS) &&
 849                                  ((pBase->version & 0xff) > 0x0a) &&
 850                                  (pBase->pwdclkind == 0);
 851
 852         if (ah->need_an_top2_fixup)
 853                 ath_print(common, ATH_DBG_EEPROM,
 854                           "needs fixup for AR_AN_TOP2 register\n");
 855 }
 856
 857 int ath9k_hw_init(struct ath_hw *ah)
 858 {
 859         struct ath_common *common = ath9k_hw_common(ah);
 860         int r = 0;
 861
 862         if (common->bus_ops->ath_bus_type != ATH_USB) {
 863                 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
 864                         ath_print(common, ATH_DBG_FATAL,
 865                                   "Unsupported device ID: 0x%0x\n",
 866                                   ah->hw_version.devid);
 867                         return -EOPNOTSUPP;
 868                 }
 869         }
 870
 871         ath9k_hw_init_defaults(ah);
 872         ath9k_hw_init_config(ah);
 873
 874         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 875                 ath_print(common, ATH_DBG_FATAL,
 876                           "Couldn't reset chip\n");
 877                 return -EIO;
 878         }
 879
 880         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 881                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 882                 return -EIO;
 883         }
 884
 885         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 886                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 887                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 888                         ah->config.serialize_regmode =
 889                                 SER_REG_MODE_ON;
 890                 } else {
 891                         ah->config.serialize_regmode =
 892                                 SER_REG_MODE_OFF;
 893                 }
 894         }
 895
 896         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 897                 ah->config.serialize_regmode);
 898
 899         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 900                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 901         else
 902                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 903
 904         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 905                 ath_print(common, ATH_DBG_FATAL,
 906                           "Mac Chip Rev 0x%02x.%x is not supported by "
 907                           "this driver\n", ah->hw_version.macVersion,
 908                           ah->hw_version.macRev);
 909                 return -EOPNOTSUPP;
 910         }
 911
 912         if (AR_SREV_9100(ah)) {
 913                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 914                 ah->supp_cals = IQ_MISMATCH_CAL;
 915                 ah->is_pciexpress = false;
 916         }
 917
 918         if (AR_SREV_9271(ah))
 919                 ah->is_pciexpress = false;
 920
 921         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 922
 923         ath9k_hw_init_cal_settings(ah);
 924
 925         ah->ani_function = ATH9K_ANI_ALL;
 926         if (AR_SREV_9280_10_OR_LATER(ah)) {
 927                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 928                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
 929                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
 930         } else {
 931                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
 932                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
 933         }
 934
 935         ath9k_hw_init_mode_regs(ah);
 936
 937         if (ah->is_pciexpress)
 938                 ath9k_hw_configpcipowersave(ah, 0, 0);
 939         else
 940                 ath9k_hw_disablepcie(ah);
 941
 942         /* Support for Japan ch.14 (2484) spread */
 943         if (AR_SREV_9287_11_OR_LATER(ah)) {
 944                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 945                        ar9287Common_normal_cck_fir_coeff_92871_1,
 946                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
 947                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 948                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 949                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
 950         }
 951
 952         r = ath9k_hw_post_init(ah);
 953         if (r)
 954                 return r;
 955
 956         ath9k_hw_init_mode_gain_regs(ah);
 957         r = ath9k_hw_fill_cap_info(ah);
 958         if (r)
 959                 return r;
 960
 961         ath9k_hw_init_eeprom_fix(ah);
 962
 963         r = ath9k_hw_init_macaddr(ah);
 964         if (r) {
 965                 ath_print(common, ATH_DBG_FATAL,
 966                           "Failed to initialize MAC address\n");
 967                 return r;
 968         }
 969
 970         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 971                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 972         else
 973                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 974
 975         ath9k_init_nfcal_hist_buffer(ah);
 976
 977         common->state = ATH_HW_INITIALIZED;
 978
 979         return 0;
 980 }
 981
 982 static void ath9k_hw_init_bb(struct ath_hw *ah,
 983                              struct ath9k_channel *chan)
 984 {
 985         u32 synthDelay;
 986
 987         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 988         if (IS_CHAN_B(chan))
 989                 synthDelay = (4 * synthDelay) / 22;
 990         else
 991                 synthDelay /= 10;
 992
 993         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 994
 995         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 996 }
 997
 998 static void ath9k_hw_init_qos(struct ath_hw *ah)
 999 {
1000         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1001         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1002
1003         REG_WRITE(ah, AR_QOS_NO_ACK,
1004                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1005                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1006                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1007
1008         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1009         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1010         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1011         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1012         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1013 }
1014
1015 static void ath9k_hw_init_pll(struct ath_hw *ah,
1016                               struct ath9k_channel *chan)
1017 {
1018         u32 pll;
1019
1020         if (AR_SREV_9100(ah)) {
1021                 if (chan && IS_CHAN_5GHZ(chan))
1022                         pll = 0x1450;
1023                 else
1024                         pll = 0x1458;
1025         } else {
1026                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1027                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1028
1029                         if (chan && IS_CHAN_HALF_RATE(chan))
1030                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1031                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1032                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1033
1034                         if (chan && IS_CHAN_5GHZ(chan)) {
1035                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1036
1037
1038                                 if (AR_SREV_9280_20(ah)) {
1039                                         if (((chan->channel % 20) == 0)
1040                                             || ((chan->channel % 10) == 0))
1041                                                 pll = 0x2850;
1042                                         else
1043                                                 pll = 0x142c;
1044                                 }
1045                         } else {
1046                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1047                         }
1048
1049                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1050
1051                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1052
1053                         if (chan && IS_CHAN_HALF_RATE(chan))
1054                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1055                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1056                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1057
1058                         if (chan && IS_CHAN_5GHZ(chan))
1059                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1060                         else
1061                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1062                 } else {
1063                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1064
1065                         if (chan && IS_CHAN_HALF_RATE(chan))
1066                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1067                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1068                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1069
1070                         if (chan && IS_CHAN_5GHZ(chan))
1071                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1072                         else
1073                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1074                 }
1075         }
1076         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1077
1078         /* Switch the core clock for ar9271 to 117Mhz */
1079         if (AR_SREV_9271(ah)) {
1080                 udelay(500);
1081                 REG_WRITE(ah, 0x50040, 0x304);
1082         }
1083
1084         udelay(RTC_PLL_SETTLE_DELAY);
1085
1086         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1087 }
1088
1089 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1090 {
1091         int rx_chainmask, tx_chainmask;
1092
1093         rx_chainmask = ah->rxchainmask;
1094         tx_chainmask = ah->txchainmask;
1095
1096         switch (rx_chainmask) {
1097         case 0x5:
1098                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1099                             AR_PHY_SWAP_ALT_CHAIN);
1100         case 0x3:
1101                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1102                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1103                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1104                         break;
1105                 }
1106         case 0x1:
1107         case 0x2:
1108         case 0x7:
1109                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1110                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1111                 break;
1112         default:
1113                 break;
1114         }
1115
1116         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1117         if (tx_chainmask == 0x5) {
1118                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1119                             AR_PHY_SWAP_ALT_CHAIN);
1120         }
1121         if (AR_SREV_9100(ah))
1122                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1123                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1124 }
1125
1126 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1127                                           enum nl80211_iftype opmode)
1128 {
1129         u32 imr_reg = AR_IMR_TXERR |
1130                 AR_IMR_TXURN |
1131                 AR_IMR_RXERR |
1132                 AR_IMR_RXORN |
1133                 AR_IMR_BCNMISC;
1134
1135         if (ah->config.rx_intr_mitigation)
1136                 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1137         else
1138                 imr_reg |= AR_IMR_RXOK;
1139
1140         imr_reg |= AR_IMR_TXOK;
1141
1142         if (opmode == NL80211_IFTYPE_AP)
1143                 imr_reg |= AR_IMR_MIB;
1144
1145         REG_WRITE(ah, AR_IMR, imr_reg);
1146         ah->imrs2_reg |= AR_IMR_S2_GTT;
1147         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1148
1149         if (!AR_SREV_9100(ah)) {
1150                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1151                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1152                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1153         }
1154 }
1155
1156 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1157 {
1158         u32 val = ath9k_hw_mac_to_clks(ah, us);
1159         val = min(val, (u32) 0xFFFF);
1160         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1161 }
1162
1163 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1164 {
1165         u32 val = ath9k_hw_mac_to_clks(ah, us);
1166         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1167         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1168 }
1169
1170 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1171 {
1172         u32 val = ath9k_hw_mac_to_clks(ah, us);
1173         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1174         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1175 }
1176
1177 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1178 {
1179         if (tu > 0xFFFF) {
1180                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1181                           "bad global tx timeout %u\n", tu);
1182                 ah->globaltxtimeout = (u32) -1;
1183                 return false;
1184         } else {
1185                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1186                 ah->globaltxtimeout = tu;
1187                 return true;
1188         }
1189 }
1190
1191 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1192 {
1193         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1194         int acktimeout;
1195         int slottime;
1196         int sifstime;
1197
1198         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1199                   ah->misc_mode);
1200
1201         if (ah->misc_mode != 0)
1202                 REG_WRITE(ah, AR_PCU_MISC,
1203                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1204
1205         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1206                 sifstime = 16;
1207         else
1208                 sifstime = 10;
1209
1210         /* As defined by IEEE 802.11-2007 17.3.8.6 */
1211         slottime = ah->slottime + 3 * ah->coverage_class;
1212         acktimeout = slottime + sifstime;
1213
1214         /*
1215          * Workaround for early ACK timeouts, add an offset to match the
1216          * initval's 64us ack timeout value.
1217          * This was initially only meant to work around an issue with delayed
1218          * BA frames in some implementations, but it has been found to fix ACK
1219          * timeout issues in other cases as well.
1220          */
1221         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1222                 acktimeout += 64 - sifstime - ah->slottime;
1223
1224         ath9k_hw_setslottime(ah, slottime);
1225         ath9k_hw_set_ack_timeout(ah, acktimeout);
1226         ath9k_hw_set_cts_timeout(ah, acktimeout);
1227         if (ah->globaltxtimeout != (u32) -1)
1228                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1229 }
1230 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1231
1232 void ath9k_hw_deinit(struct ath_hw *ah)
1233 {
1234         struct ath_common *common = ath9k_hw_common(ah);
1235
1236         if (common->state < ATH_HW_INITIALIZED)
1237                 goto free_hw;
1238
1239         if (!AR_SREV_9100(ah))
1240                 ath9k_hw_ani_disable(ah);
1241
1242         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1243
1244 free_hw:
1245         if (!AR_SREV_9280_10_OR_LATER(ah))
1246                 ath9k_hw_rf_free_ext_banks(ah);
1247 }
1248 EXPORT_SYMBOL(ath9k_hw_deinit);
1249
1250 /*******/
1251 /* INI */
1252 /*******/
1253
1254 static void ath9k_hw_override_ini(struct ath_hw *ah,
1255                                   struct ath9k_channel *chan)
1256 {
1257         u32 val;
1258
1259         /*
1260          * Set the RX_ABORT and RX_DIS and clear if off only after
1261          * RXE is set for MAC. This prevents frames with corrupted
1262          * descriptor status.
1263          */
1264         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1265
1266         if (AR_SREV_9280_10_OR_LATER(ah)) {
1267                 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1268
1269                 if (!AR_SREV_9271(ah))
1270                         val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1271
1272                 if (AR_SREV_9287_10_OR_LATER(ah))
1273                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1274
1275                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1276         }
1277
1278         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1279             AR_SREV_9280_10_OR_LATER(ah))
1280                 return;
1281         /*
1282          * Disable BB clock gating
1283          * Necessary to avoid issues on AR5416 2.0
1284          */
1285         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1286
1287         /*
1288          * Disable RIFS search on some chips to avoid baseband
1289          * hang issues.
1290          */
1291         if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1292                 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1293                 val &= ~AR_PHY_RIFS_INIT_DELAY;
1294                 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1295         }
1296 }
1297
1298 static void ath9k_olc_init(struct ath_hw *ah)
1299 {
1300         u32 i;
1301
1302         if (OLC_FOR_AR9287_10_LATER) {
1303                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1304                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1305                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1306                                 AR9287_AN_TXPC0_TXPCMODE,
1307                                 AR9287_AN_TXPC0_TXPCMODE_S,
1308                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1309                 udelay(100);
1310         } else {
1311                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1312                         ah->originalGain[i] =
1313                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1314                                                 AR_PHY_TX_GAIN);
1315                 ah->PDADCdelta = 0;
1316         }
1317 }
1318
1319 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1320                               struct ath9k_channel *chan)
1321 {
1322         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1323
1324         if (IS_CHAN_B(chan))
1325                 ctl |= CTL_11B;
1326         else if (IS_CHAN_G(chan))
1327                 ctl |= CTL_11G;
1328         else
1329                 ctl |= CTL_11A;
1330
1331         return ctl;
1332 }
1333
1334 static int ath9k_hw_process_ini(struct ath_hw *ah,
1335                                 struct ath9k_channel *chan)
1336 {
1337         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1338         int i, regWrites = 0;
1339         struct ieee80211_channel *channel = chan->chan;
1340         u32 modesIndex, freqIndex;
1341
1342         switch (chan->chanmode) {
1343         case CHANNEL_A:
1344         case CHANNEL_A_HT20:
1345                 modesIndex = 1;
1346                 freqIndex = 1;
1347                 break;
1348         case CHANNEL_A_HT40PLUS:
1349         case CHANNEL_A_HT40MINUS:
1350                 modesIndex = 2;
1351                 freqIndex = 1;
1352                 break;
1353         case CHANNEL_G:
1354         case CHANNEL_G_HT20:
1355         case CHANNEL_B:
1356                 modesIndex = 4;
1357                 freqIndex = 2;
1358                 break;
1359         case CHANNEL_G_HT40PLUS:
1360         case CHANNEL_G_HT40MINUS:
1361                 modesIndex = 3;
1362                 freqIndex = 2;
1363                 break;
1364
1365         default:
1366                 return -EINVAL;
1367         }
1368
1369         /* Set correct baseband to analog shift setting to access analog chips */
1370         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1371
1372         /* Write ADDAC shifts */
1373         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1374         ah->eep_ops->set_addac(ah, chan);
1375
1376         if (AR_SREV_5416_22_OR_LATER(ah)) {
1377                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1378         } else {
1379                 struct ar5416IniArray temp;
1380                 u32 addacSize =
1381                         sizeof(u32) * ah->iniAddac.ia_rows *
1382                         ah->iniAddac.ia_columns;
1383
1384                 /* For AR5416 2.0/2.1 */
1385                 memcpy(ah->addac5416_21,
1386                        ah->iniAddac.ia_array, addacSize);
1387
1388                 /* override CLKDRV value at [row, column] = [31, 1] */
1389                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1390
1391                 temp.ia_array = ah->addac5416_21;
1392                 temp.ia_columns = ah->iniAddac.ia_columns;
1393                 temp.ia_rows = ah->iniAddac.ia_rows;
1394                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1395         }
1396
1397         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1398
1399         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1400                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1401                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1402
1403                 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1404                         val &= ~AR_AN_TOP2_PWDCLKIND;
1405
1406                 REG_WRITE(ah, reg, val);
1407
1408                 if (reg >= 0x7800 && reg < 0x78a0
1409                     && ah->config.analog_shiftreg) {
1410                         udelay(100);
1411                 }
1412
1413                 DO_DELAY(regWrites);
1414         }
1415
1416         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1417                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1418
1419         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1420             AR_SREV_9287_10_OR_LATER(ah))
1421                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1422
1423         if (AR_SREV_9271_10(ah))
1424                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1425                                 modesIndex, regWrites);
1426
1427         /* Write common array parameters */
1428         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1429                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1430                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1431
1432                 REG_WRITE(ah, reg, val);
1433
1434                 if (reg >= 0x7800 && reg < 0x78a0
1435                     && ah->config.analog_shiftreg) {
1436                         udelay(100);
1437                 }
1438
1439                 DO_DELAY(regWrites);
1440         }
1441
1442         if (AR_SREV_9271(ah)) {
1443                 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1444                         REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1445                                         modesIndex, regWrites);
1446                 else
1447                         REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1448                                         modesIndex, regWrites);
1449         }
1450
1451         ath9k_hw_write_regs(ah, freqIndex, regWrites);
1452
1453         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1454                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1455                                 regWrites);
1456         }
1457
1458         ath9k_hw_override_ini(ah, chan);
1459         ath9k_hw_set_regs(ah, chan);
1460         ath9k_hw_init_chain_masks(ah);
1461
1462         if (OLC_FOR_AR9280_20_LATER)
1463                 ath9k_olc_init(ah);
1464
1465         /* Set TX power */
1466         ah->eep_ops->set_txpower(ah, chan,
1467                                  ath9k_regd_get_ctl(regulatory, chan),
1468                                  channel->max_antenna_gain * 2,
1469                                  channel->max_power * 2,
1470                                  min((u32) MAX_RATE_POWER,
1471                                  (u32) regulatory->power_limit));
1472
1473         /* Write analog registers */
1474         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1475                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1476                           "ar5416SetRfRegs failed\n");
1477                 return -EIO;
1478         }
1479
1480         return 0;
1481 }
1482
1483 /****************************************/
1484 /* Reset and Channel Switching Routines */
1485 /****************************************/
1486
1487 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1488 {
1489         u32 rfMode = 0;
1490
1491         if (chan == NULL)
1492                 return;
1493
1494         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1495                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1496
1497         if (!AR_SREV_9280_10_OR_LATER(ah))
1498                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1499                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1500
1501         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1502                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1503
1504         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1505 }
1506
1507 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1508 {
1509         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1510 }
1511
1512 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1513 {
1514         u32 regval;
1515
1516         /*
1517          * set AHB_MODE not to do cacheline prefetches
1518         */
1519         regval = REG_READ(ah, AR_AHB_MODE);
1520         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1521
1522         /*
1523          * let mac dma reads be in 128 byte chunks
1524          */
1525         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1526         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1527
1528         /*
1529          * Restore TX Trigger Level to its pre-reset value.
1530          * The initial value depends on whether aggregation is enabled, and is
1531          * adjusted whenever underruns are detected.
1532          */
1533         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1534
1535         /*
1536          * let mac dma writes be in 128 byte chunks
1537          */
1538         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1539         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1540
1541         /*
1542          * Setup receive FIFO threshold to hold off TX activities
1543          */
1544         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1545
1546         /*
1547          * reduce the number of usable entries in PCU TXBUF to avoid
1548          * wrap around issues.
1549          */
1550         if (AR_SREV_9285(ah)) {
1551                 /* For AR9285 the number of Fifos are reduced to half.
1552                  * So set the usable tx buf size also to half to
1553                  * avoid data/delimiter underruns
1554                  */
1555                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1556                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1557         } else if (!AR_SREV_9271(ah)) {
1558                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1559                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1560         }
1561 }
1562
1563 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1564 {
1565         u32 val;
1566
1567         val = REG_READ(ah, AR_STA_ID1);
1568         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1569         switch (opmode) {
1570         case NL80211_IFTYPE_AP:
1571                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1572                           | AR_STA_ID1_KSRCH_MODE);
1573                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1574                 break;
1575         case NL80211_IFTYPE_ADHOC:
1576         case NL80211_IFTYPE_MESH_POINT:
1577                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1578                           | AR_STA_ID1_KSRCH_MODE);
1579                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1580                 break;
1581         case NL80211_IFTYPE_STATION:
1582         case NL80211_IFTYPE_MONITOR:
1583                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1584                 break;
1585         }
1586 }
1587
1588 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1589                                                  u32 coef_scaled,
1590                                                  u32 *coef_mantissa,
1591                                                  u32 *coef_exponent)
1592 {
1593         u32 coef_exp, coef_man;
1594
1595         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1596                 if ((coef_scaled >> coef_exp) & 0x1)
1597                         break;
1598
1599         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1600
1601         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1602
1603         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1604         *coef_exponent = coef_exp - 16;
1605 }
1606
1607 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1608                                      struct ath9k_channel *chan)
1609 {
1610         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1611         u32 clockMhzScaled = 0x64000000;
1612         struct chan_centers centers;
1613
1614         if (IS_CHAN_HALF_RATE(chan))
1615                 clockMhzScaled = clockMhzScaled >> 1;
1616         else if (IS_CHAN_QUARTER_RATE(chan))
1617                 clockMhzScaled = clockMhzScaled >> 2;
1618
1619         ath9k_hw_get_channel_centers(ah, chan, &centers);
1620         coef_scaled = clockMhzScaled / centers.synth_center;
1621
1622         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1623                                       &ds_coef_exp);
1624
1625         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1626                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1627         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1628                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1629
1630         coef_scaled = (9 * coef_scaled) / 10;
1631
1632         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1633                                       &ds_coef_exp);
1634
1635         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1636                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1637         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1638                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1639 }
1640
1641 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1642 {
1643         u32 rst_flags;
1644         u32 tmpReg;
1645
1646         if (AR_SREV_9100(ah)) {
1647                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1648                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1649                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1650                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1651                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1652         }
1653
1654         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1655                   AR_RTC_FORCE_WAKE_ON_INT);
1656
1657         if (AR_SREV_9100(ah)) {
1658                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1659                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1660         } else {
1661                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1662                 if (tmpReg &
1663                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1664                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1665                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1666                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1667                 } else {
1668                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1669                 }
1670
1671                 rst_flags = AR_RTC_RC_MAC_WARM;
1672                 if (type == ATH9K_RESET_COLD)
1673                         rst_flags |= AR_RTC_RC_MAC_COLD;
1674         }
1675
1676         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1677         udelay(50);
1678
1679         REG_WRITE(ah, AR_RTC_RC, 0);
1680         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1681                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1682                           "RTC stuck in MAC reset\n");
1683                 return false;
1684         }
1685
1686         if (!AR_SREV_9100(ah))
1687                 REG_WRITE(ah, AR_RC, 0);
1688
1689         if (AR_SREV_9100(ah))
1690                 udelay(50);
1691
1692         return true;
1693 }
1694
1695 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1696 {
1697         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1698                   AR_RTC_FORCE_WAKE_ON_INT);
1699
1700         if (!AR_SREV_9100(ah))
1701                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1702
1703         REG_WRITE(ah, AR_RTC_RESET, 0);
1704         udelay(2);
1705
1706         if (!AR_SREV_9100(ah))
1707                 REG_WRITE(ah, AR_RC, 0);
1708
1709         REG_WRITE(ah, AR_RTC_RESET, 1);
1710
1711         if (!ath9k_hw_wait(ah,
1712                            AR_RTC_STATUS,
1713                            AR_RTC_STATUS_M,
1714                            AR_RTC_STATUS_ON,
1715                            AH_WAIT_TIMEOUT)) {
1716                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1717                           "RTC not waking up\n");
1718                 return false;
1719         }
1720
1721         ath9k_hw_read_revisions(ah);
1722
1723         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1724 }
1725
1726 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1727 {
1728         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1729                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1730
1731         switch (type) {
1732         case ATH9K_RESET_POWER_ON:
1733                 return ath9k_hw_set_reset_power_on(ah);
1734         case ATH9K_RESET_WARM:
1735         case ATH9K_RESET_COLD:
1736                 return ath9k_hw_set_reset(ah, type);
1737         default:
1738                 return false;
1739         }
1740 }
1741
1742 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1743 {
1744         u32 phymode;
1745         u32 enableDacFifo = 0;
1746
1747         if (AR_SREV_9285_10_OR_LATER(ah))
1748                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1749                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1750
1751         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1752                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1753
1754         if (IS_CHAN_HT40(chan)) {
1755                 phymode |= AR_PHY_FC_DYN2040_EN;
1756
1757                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1758                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1759                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1760
1761         }
1762         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1763
1764         ath9k_hw_set11nmac2040(ah);
1765
1766         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1767         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1768 }
1769
1770 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1771                                 struct ath9k_channel *chan)
1772 {
1773         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1774                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1775                         return false;
1776         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1777                 return false;
1778
1779         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1780                 return false;
1781
1782         ah->chip_fullsleep = false;
1783         ath9k_hw_init_pll(ah, chan);
1784         ath9k_hw_set_rfmode(ah, chan);
1785
1786         return true;
1787 }
1788
1789 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1790                                     struct ath9k_channel *chan)
1791 {
1792         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1793         struct ath_common *common = ath9k_hw_common(ah);
1794         struct ieee80211_channel *channel = chan->chan;
1795         u32 synthDelay, qnum;
1796         int r;
1797
1798         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1799                 if (ath9k_hw_numtxpending(ah, qnum)) {
1800                         ath_print(common, ATH_DBG_QUEUE,
1801                                   "Transmit frames pending on "
1802                                   "queue %d\n", qnum);
1803                         return false;
1804                 }
1805         }
1806
1807         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1808         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1809                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1810                 ath_print(common, ATH_DBG_FATAL,
1811                           "Could not kill baseband RX\n");
1812                 return false;
1813         }
1814
1815         ath9k_hw_set_regs(ah, chan);
1816
1817         r = ah->ath9k_hw_rf_set_freq(ah, chan);
1818         if (r) {
1819                 ath_print(common, ATH_DBG_FATAL,
1820                           "Failed to set channel\n");
1821                 return false;
1822         }
1823
1824         ah->eep_ops->set_txpower(ah, chan,
1825                              ath9k_regd_get_ctl(regulatory, chan),
1826                              channel->max_antenna_gain * 2,
1827                              channel->max_power * 2,
1828                              min((u32) MAX_RATE_POWER,
1829                              (u32) regulatory->power_limit));
1830
1831         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1832         if (IS_CHAN_B(chan))
1833                 synthDelay = (4 * synthDelay) / 22;
1834         else
1835                 synthDelay /= 10;
1836
1837         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1838
1839         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1840
1841         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1842                 ath9k_hw_set_delta_slope(ah, chan);
1843
1844         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1845
1846         if (!chan->oneTimeCalsDone)
1847                 chan->oneTimeCalsDone = true;
1848
1849         return true;
1850 }
1851
1852 static void ath9k_enable_rfkill(struct ath_hw *ah)
1853 {
1854         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1855                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1856
1857         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1858                     AR_GPIO_INPUT_MUX2_RFSILENT);
1859
1860         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1861         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1862 }
1863
1864 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1865                     bool bChannelChange)
1866 {
1867         struct ath_common *common = ath9k_hw_common(ah);
1868         u32 saveLedState;
1869         struct ath9k_channel *curchan = ah->curchan;
1870         u32 saveDefAntenna;
1871         u32 macStaId1;
1872         u64 tsf = 0;
1873         int i, rx_chainmask, r;
1874
1875         ah->txchainmask = common->tx_chainmask;
1876         ah->rxchainmask = common->rx_chainmask;
1877
1878         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1879                 return -EIO;
1880
1881         if (curchan && !ah->chip_fullsleep)
1882                 ath9k_hw_getnf(ah, curchan);
1883
1884         if (bChannelChange &&
1885             (ah->chip_fullsleep != true) &&
1886             (ah->curchan != NULL) &&
1887             (chan->channel != ah->curchan->channel) &&
1888             ((chan->channelFlags & CHANNEL_ALL) ==
1889              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1890              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1891              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1892
1893                 if (ath9k_hw_channel_change(ah, chan)) {
1894                         ath9k_hw_loadnf(ah, ah->curchan);
1895                         ath9k_hw_start_nfcal(ah);
1896                         return 0;
1897                 }
1898         }
1899
1900         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1901         if (saveDefAntenna == 0)
1902                 saveDefAntenna = 1;
1903
1904         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1905
1906         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1907         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1908                 tsf = ath9k_hw_gettsf64(ah);
1909
1910         saveLedState = REG_READ(ah, AR_CFG_LED) &
1911                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1912                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1913
1914         ath9k_hw_mark_phy_inactive(ah);
1915
1916         /* Only required on the first reset */
1917         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1918                 REG_WRITE(ah,
1919                           AR9271_RESET_POWER_DOWN_CONTROL,
1920                           AR9271_RADIO_RF_RST);
1921                 udelay(50);
1922         }
1923
1924         if (!ath9k_hw_chip_reset(ah, chan)) {
1925                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1926                 return -EINVAL;
1927         }
1928
1929         /* Only required on the first reset */
1930         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1931                 ah->htc_reset_init = false;
1932                 REG_WRITE(ah,
1933                           AR9271_RESET_POWER_DOWN_CONTROL,
1934                           AR9271_GATE_MAC_CTL);
1935                 udelay(50);
1936         }
1937
1938         /* Restore TSF */
1939         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1940                 ath9k_hw_settsf64(ah, tsf);
1941
1942         if (AR_SREV_9280_10_OR_LATER(ah))
1943                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1944
1945         if (AR_SREV_9287_12_OR_LATER(ah)) {
1946                 /* Enable ASYNC FIFO */
1947                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1948                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1949                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1950                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1951                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1952                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1953                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1954         }
1955         r = ath9k_hw_process_ini(ah, chan);
1956         if (r)
1957                 return r;
1958
1959         /* Setup MFP options for CCMP */
1960         if (AR_SREV_9280_20_OR_LATER(ah)) {
1961                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1962                  * frames when constructing CCMP AAD. */
1963                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1964                               0xc7ff);
1965                 ah->sw_mgmt_crypto = false;
1966         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1967                 /* Disable hardware crypto for management frames */
1968                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1969                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1970                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1971                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1972                 ah->sw_mgmt_crypto = true;
1973         } else
1974                 ah->sw_mgmt_crypto = true;
1975
1976         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1977                 ath9k_hw_set_delta_slope(ah, chan);
1978
1979         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1980         ah->eep_ops->set_board_values(ah, chan);
1981
1982         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1983         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1984                   | macStaId1
1985                   | AR_STA_ID1_RTS_USE_DEF
1986                   | (ah->config.
1987                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1988                   | ah->sta_id1_defaults);
1989         ath9k_hw_set_operating_mode(ah, ah->opmode);
1990
1991         ath_hw_setbssidmask(common);
1992
1993         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1994
1995         ath9k_hw_write_associd(ah);
1996
1997         REG_WRITE(ah, AR_ISR, ~0);
1998
1999         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2000
2001         r = ah->ath9k_hw_rf_set_freq(ah, chan);
2002         if (r)
2003                 return r;
2004
2005         for (i = 0; i < AR_NUM_DCU; i++)
2006                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2007
2008         ah->intr_txqs = 0;
2009         for (i = 0; i < ah->caps.total_queues; i++)
2010                 ath9k_hw_resettxqueue(ah, i);
2011
2012         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2013         ath9k_hw_init_qos(ah);
2014
2015         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2016                 ath9k_enable_rfkill(ah);
2017
2018         ath9k_hw_init_global_settings(ah);
2019
2020         if (AR_SREV_9287_12_OR_LATER(ah)) {
2021                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2022                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2023                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2024                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2025                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2026                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2027
2028                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2029                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2030
2031                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2032                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2033                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2034                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2035         }
2036         if (AR_SREV_9287_12_OR_LATER(ah)) {
2037                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2038                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2039         }
2040
2041         REG_WRITE(ah, AR_STA_ID1,
2042                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2043
2044         ath9k_hw_set_dma(ah);
2045
2046         REG_WRITE(ah, AR_OBS, 8);
2047
2048         if (ah->config.rx_intr_mitigation) {
2049                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2050                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2051         }
2052
2053         ath9k_hw_init_bb(ah, chan);
2054
2055         if (!ath9k_hw_init_cal(ah, chan))
2056                 return -EIO;
2057
2058         rx_chainmask = ah->rxchainmask;
2059         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2060                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2061                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2062         }
2063
2064         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2065
2066         /*
2067          * For big endian systems turn on swapping for descriptors
2068          */
2069         if (AR_SREV_9100(ah)) {
2070                 u32 mask;
2071                 mask = REG_READ(ah, AR_CFG);
2072                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2073                         ath_print(common, ATH_DBG_RESET,
2074                                 "CFG Byte Swap Set 0x%x\n", mask);
2075                 } else {
2076                         mask =
2077                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2078                         REG_WRITE(ah, AR_CFG, mask);
2079                         ath_print(common, ATH_DBG_RESET,
2080                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2081                 }
2082         } else {
2083                 /* Configure AR9271 target WLAN */
2084                 if (AR_SREV_9271(ah))
2085                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2086 #ifdef __BIG_ENDIAN
2087                 else
2088                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2089 #endif
2090         }
2091
2092         if (ah->btcoex_hw.enabled)
2093                 ath9k_hw_btcoex_enable(ah);
2094
2095         return 0;
2096 }
2097 EXPORT_SYMBOL(ath9k_hw_reset);
2098
2099 /************************/
2100 /* Key Cache Management */
2101 /************************/
2102
2103 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2104 {
2105         u32 keyType;
2106
2107         if (entry >= ah->caps.keycache_size) {
2108                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2109                           "keychache entry %u out of range\n", entry);
2110                 return false;
2111         }
2112
2113         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2114
2115         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2116         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2117         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2118         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2119         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2120         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2121         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2122         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2123
2124         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2125                 u16 micentry = entry + 64;
2126
2127                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2128                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2129                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2130                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2131
2132         }
2133
2134         return true;
2135 }
2136 EXPORT_SYMBOL(ath9k_hw_keyreset);
2137
2138 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2139 {
2140         u32 macHi, macLo;
2141
2142         if (entry >= ah->caps.keycache_size) {
2143                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2144                           "keychache entry %u out of range\n", entry);
2145                 return false;
2146         }
2147
2148         if (mac != NULL) {
2149                 macHi = (mac[5] << 8) | mac[4];
2150                 macLo = (mac[3] << 24) |
2151                         (mac[2] << 16) |
2152                         (mac[1] << 8) |
2153                         mac[0];
2154                 macLo >>= 1;
2155                 macLo |= (macHi & 1) << 31;
2156                 macHi >>= 1;
2157         } else {
2158                 macLo = macHi = 0;
2159         }
2160         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2161         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2162
2163         return true;
2164 }
2165 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2166
2167 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2168                                  const struct ath9k_keyval *k,
2169                                  const u8 *mac)
2170 {
2171         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2172         struct ath_common *common = ath9k_hw_common(ah);
2173         u32 key0, key1, key2, key3, key4;
2174         u32 keyType;
2175
2176         if (entry >= pCap->keycache_size) {
2177                 ath_print(common, ATH_DBG_FATAL,
2178                           "keycache entry %u out of range\n", entry);
2179                 return false;
2180         }
2181
2182         switch (k->kv_type) {
2183         case ATH9K_CIPHER_AES_OCB:
2184                 keyType = AR_KEYTABLE_TYPE_AES;
2185                 break;
2186         case ATH9K_CIPHER_AES_CCM:
2187                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2188                         ath_print(common, ATH_DBG_ANY,
2189                                   "AES-CCM not supported by mac rev 0x%x\n",
2190                                   ah->hw_version.macRev);
2191                         return false;
2192                 }
2193                 keyType = AR_KEYTABLE_TYPE_CCM;
2194                 break;
2195         case ATH9K_CIPHER_TKIP:
2196                 keyType = AR_KEYTABLE_TYPE_TKIP;
2197                 if (ATH9K_IS_MIC_ENABLED(ah)
2198                     && entry + 64 >= pCap->keycache_size) {
2199                         ath_print(common, ATH_DBG_ANY,
2200                                   "entry %u inappropriate for TKIP\n", entry);
2201                         return false;
2202                 }
2203                 break;
2204         case ATH9K_CIPHER_WEP:
2205                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2206                         ath_print(common, ATH_DBG_ANY,
2207                                   "WEP key length %u too small\n", k->kv_len);
2208                         return false;
2209                 }
2210                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2211                         keyType = AR_KEYTABLE_TYPE_40;
2212                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2213                         keyType = AR_KEYTABLE_TYPE_104;
2214                 else
2215                         keyType = AR_KEYTABLE_TYPE_128;
2216                 break;
2217         case ATH9K_CIPHER_CLR:
2218                 keyType = AR_KEYTABLE_TYPE_CLR;
2219                 break;
2220         default:
2221                 ath_print(common, ATH_DBG_FATAL,
2222                           "cipher %u not supported\n", k->kv_type);
2223                 return false;
2224         }
2225
2226         key0 = get_unaligned_le32(k->kv_val + 0);
2227         key1 = get_unaligned_le16(k->kv_val + 4);
2228         key2 = get_unaligned_le32(k->kv_val + 6);
2229         key3 = get_unaligned_le16(k->kv_val + 10);
2230         key4 = get_unaligned_le32(k->kv_val + 12);
2231         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2232                 key4 &= 0xff;
2233
2234         /*
2235          * Note: Key cache registers access special memory area that requires
2236          * two 32-bit writes to actually update the values in the internal
2237          * memory. Consequently, the exact order and pairs used here must be
2238          * maintained.
2239          */
2240
2241         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2242                 u16 micentry = entry + 64;
2243
2244                 /*
2245                  * Write inverted key[47:0] first to avoid Michael MIC errors
2246                  * on frames that could be sent or received at the same time.
2247                  * The correct key will be written in the end once everything
2248                  * else is ready.
2249                  */
2250                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2251                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2252
2253                 /* Write key[95:48] */
2254                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2255                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2256
2257                 /* Write key[127:96] and key type */
2258                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2259                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2260
2261                 /* Write MAC address for the entry */
2262                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2263
2264                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2265                         /*
2266                          * TKIP uses two key cache entries:
2267                          * Michael MIC TX/RX keys in the same key cache entry
2268                          * (idx = main index + 64):
2269                          * key0 [31:0] = RX key [31:0]
2270                          * key1 [15:0] = TX key [31:16]
2271                          * key1 [31:16] = reserved
2272                          * key2 [31:0] = RX key [63:32]
2273                          * key3 [15:0] = TX key [15:0]
2274                          * key3 [31:16] = reserved
2275                          * key4 [31:0] = TX key [63:32]
2276                          */
2277                         u32 mic0, mic1, mic2, mic3, mic4;
2278
2279                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2280                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2281                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2282                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2283                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2284
2285                         /* Write RX[31:0] and TX[31:16] */
2286                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2287                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2288
2289                         /* Write RX[63:32] and TX[15:0] */
2290                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2291                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2292
2293                         /* Write TX[63:32] and keyType(reserved) */
2294                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2295                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2296                                   AR_KEYTABLE_TYPE_CLR);
2297
2298                 } else {
2299                         /*
2300                          * TKIP uses four key cache entries (two for group
2301                          * keys):
2302                          * Michael MIC TX/RX keys are in different key cache
2303                          * entries (idx = main index + 64 for TX and
2304                          * main index + 32 + 96 for RX):
2305                          * key0 [31:0] = TX/RX MIC key [31:0]
2306                          * key1 [31:0] = reserved
2307                          * key2 [31:0] = TX/RX MIC key [63:32]
2308                          * key3 [31:0] = reserved
2309                          * key4 [31:0] = reserved
2310                          *
2311                          * Upper layer code will call this function separately
2312                          * for TX and RX keys when these registers offsets are
2313                          * used.
2314                          */
2315                         u32 mic0, mic2;
2316
2317                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2318                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2319
2320                         /* Write MIC key[31:0] */
2321                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2322                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2323
2324                         /* Write MIC key[63:32] */
2325                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2326                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2327
2328                         /* Write TX[63:32] and keyType(reserved) */
2329                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2330                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2331                                   AR_KEYTABLE_TYPE_CLR);
2332                 }
2333
2334                 /* MAC address registers are reserved for the MIC entry */
2335                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2336                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2337
2338                 /*
2339                  * Write the correct (un-inverted) key[47:0] last to enable
2340                  * TKIP now that all other registers are set with correct
2341                  * values.
2342                  */
2343                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2344                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2345         } else {
2346                 /* Write key[47:0] */
2347                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2348                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2349
2350                 /* Write key[95:48] */
2351                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2352                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2353
2354                 /* Write key[127:96] and key type */
2355                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2356                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2357
2358                 /* Write MAC address for the entry */
2359                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2360         }
2361
2362         return true;
2363 }
2364 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2365
2366 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2367 {
2368         if (entry < ah->caps.keycache_size) {
2369                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2370                 if (val & AR_KEYTABLE_VALID)
2371                         return true;
2372         }
2373         return false;
2374 }
2375 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2376
2377 /******************************/
2378 /* Power Management (Chipset) */
2379 /******************************/
2380
2381 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2382 {
2383         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2384         if (setChip) {
2385                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2386                             AR_RTC_FORCE_WAKE_EN);
2387                 if (!AR_SREV_9100(ah))
2388                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2389
2390                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2391                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2392                                     AR_RTC_RESET_EN);
2393         }
2394 }
2395
2396 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2397 {
2398         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2399         if (setChip) {
2400                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2401
2402                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2403                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2404                                   AR_RTC_FORCE_WAKE_ON_INT);
2405                 } else {
2406                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2407                                     AR_RTC_FORCE_WAKE_EN);
2408                 }
2409         }
2410 }
2411
2412 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2413 {
2414         u32 val;
2415         int i;
2416
2417         if (setChip) {
2418                 if ((REG_READ(ah, AR_RTC_STATUS) &
2419                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2420                         if (ath9k_hw_set_reset_reg(ah,
2421                                            ATH9K_RESET_POWER_ON) != true) {
2422                                 return false;
2423                         }
2424                         ath9k_hw_init_pll(ah, NULL);
2425                 }
2426                 if (AR_SREV_9100(ah))
2427                         REG_SET_BIT(ah, AR_RTC_RESET,
2428                                     AR_RTC_RESET_EN);
2429
2430                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2431                             AR_RTC_FORCE_WAKE_EN);
2432                 udelay(50);
2433
2434                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2435                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2436                         if (val == AR_RTC_STATUS_ON)
2437                                 break;
2438                         udelay(50);
2439                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2440                                     AR_RTC_FORCE_WAKE_EN);
2441                 }
2442                 if (i == 0) {
2443                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2444                                   "Failed to wakeup in %uus\n",
2445                                   POWER_UP_TIME / 20);
2446                         return false;
2447                 }
2448         }
2449
2450         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2451
2452         return true;
2453 }
2454
2455 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2456 {
2457         struct ath_common *common = ath9k_hw_common(ah);
2458         int status = true, setChip = true;
2459         static const char *modes[] = {
2460                 "AWAKE",
2461                 "FULL-SLEEP",
2462                 "NETWORK SLEEP",
2463                 "UNDEFINED"
2464         };
2465
2466         if (ah->power_mode == mode)
2467                 return status;
2468
2469         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2470                   modes[ah->power_mode], modes[mode]);
2471
2472         switch (mode) {
2473         case ATH9K_PM_AWAKE:
2474                 status = ath9k_hw_set_power_awake(ah, setChip);
2475                 break;
2476         case ATH9K_PM_FULL_SLEEP:
2477                 ath9k_set_power_sleep(ah, setChip);
2478                 ah->chip_fullsleep = true;
2479                 break;
2480         case ATH9K_PM_NETWORK_SLEEP:
2481                 ath9k_set_power_network_sleep(ah, setChip);
2482                 break;
2483         default:
2484                 ath_print(common, ATH_DBG_FATAL,
2485                           "Unknown power mode %u\n", mode);
2486                 return false;
2487         }
2488         ah->power_mode = mode;
2489
2490         return status;
2491 }
2492 EXPORT_SYMBOL(ath9k_hw_setpower);
2493
2494 /*
2495  * Helper for ASPM support.
2496  *
2497  * Disable PLL when in L0s as well as receiver clock when in L1.
2498  * This power saving option must be enabled through the SerDes.
2499  *
2500  * Programming the SerDes must go through the same 288 bit serial shift
2501  * register as the other analog registers.  Hence the 9 writes.
2502  */
2503 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2504 {
2505         u8 i;
2506         u32 val;
2507
2508         if (ah->is_pciexpress != true)
2509                 return;
2510
2511         /* Do not touch SerDes registers */
2512         if (ah->config.pcie_powersave_enable == 2)
2513                 return;
2514
2515         /* Nothing to do on restore for 11N */
2516         if (!restore) {
2517                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2518                         /*
2519                          * AR9280 2.0 or later chips use SerDes values from the
2520                          * initvals.h initialized depending on chipset during
2521                          * ath9k_hw_init()
2522                          */
2523                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2524                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2525                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2526                         }
2527                 } else if (AR_SREV_9280(ah) &&
2528                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2529                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2530                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2531
2532                         /* RX shut off when elecidle is asserted */
2533                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2534                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2535                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2536
2537                         /* Shut off CLKREQ active in L1 */
2538                         if (ah->config.pcie_clock_req)
2539                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2540                         else
2541                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2542
2543                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2544                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2545                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2546
2547                         /* Load the new settings */
2548                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2549
2550                 } else {
2551                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2552                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2553
2554                         /* RX shut off when elecidle is asserted */
2555                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2556                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2557                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2558
2559                         /*
2560                          * Ignore ah->ah_config.pcie_clock_req setting for
2561                          * pre-AR9280 11n
2562                          */
2563                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2564
2565                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2566                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2567                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2568
2569                         /* Load the new settings */
2570                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2571                 }
2572
2573                 udelay(1000);
2574
2575                 /* set bit 19 to allow forcing of pcie core into L1 state */
2576                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2577
2578                 /* Several PCIe massages to ensure proper behaviour */
2579                 if (ah->config.pcie_waen) {
2580                         val = ah->config.pcie_waen;
2581                         if (!power_off)
2582                                 val &= (~AR_WA_D3_L1_DISABLE);
2583                 } else {
2584                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2585                             AR_SREV_9287(ah)) {
2586                                 val = AR9285_WA_DEFAULT;
2587                                 if (!power_off)
2588                                         val &= (~AR_WA_D3_L1_DISABLE);
2589                         } else if (AR_SREV_9280(ah)) {
2590                                 /*
2591                                  * On AR9280 chips bit 22 of 0x4004 needs to be
2592                                  * set otherwise card may disappear.
2593                                  */
2594                                 val = AR9280_WA_DEFAULT;
2595                                 if (!power_off)
2596                                         val &= (~AR_WA_D3_L1_DISABLE);
2597                         } else
2598                                 val = AR_WA_DEFAULT;
2599                 }
2600
2601                 REG_WRITE(ah, AR_WA, val);
2602         }
2603
2604         if (power_off) {
2605                 /*
2606                  * Set PCIe workaround bits
2607                  * bit 14 in WA register (disable L1) should only
2608                  * be set when device enters D3 and be cleared
2609                  * when device comes back to D0.
2610                  */
2611                 if (ah->config.pcie_waen) {
2612                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2613                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2614                 } else {
2615                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2616                               AR_SREV_9287(ah)) &&
2617                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2618                             (AR_SREV_9280(ah) &&
2619                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2620                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2621                         }
2622                 }
2623         }
2624 }
2625 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2626
2627 /**********************/
2628 /* Interrupt Handling */
2629 /**********************/
2630
2631 bool ath9k_hw_intrpend(struct ath_hw *ah)
2632 {
2633         u32 host_isr;
2634
2635         if (AR_SREV_9100(ah))
2636                 return true;
2637
2638         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2639         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2640                 return true;
2641
2642         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2643         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2644             && (host_isr != AR_INTR_SPURIOUS))
2645                 return true;
2646
2647         return false;
2648 }
2649 EXPORT_SYMBOL(ath9k_hw_intrpend);
2650
2651 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2652 {
2653         u32 isr = 0;
2654         u32 mask2 = 0;
2655         struct ath9k_hw_capabilities *pCap = &ah->caps;
2656         u32 sync_cause = 0;
2657         bool fatal_int = false;
2658         struct ath_common *common = ath9k_hw_common(ah);
2659
2660         if (!AR_SREV_9100(ah)) {
2661                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2662                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2663                             == AR_RTC_STATUS_ON) {
2664                                 isr = REG_READ(ah, AR_ISR);
2665                         }
2666                 }
2667
2668                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2669                         AR_INTR_SYNC_DEFAULT;
2670
2671                 *masked = 0;
2672
2673                 if (!isr && !sync_cause)
2674                         return false;
2675         } else {
2676                 *masked = 0;
2677                 isr = REG_READ(ah, AR_ISR);
2678         }
2679
2680         if (isr) {
2681                 if (isr & AR_ISR_BCNMISC) {
2682                         u32 isr2;
2683                         isr2 = REG_READ(ah, AR_ISR_S2);
2684                         if (isr2 & AR_ISR_S2_TIM)
2685                                 mask2 |= ATH9K_INT_TIM;
2686                         if (isr2 & AR_ISR_S2_DTIM)
2687                                 mask2 |= ATH9K_INT_DTIM;
2688                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2689                                 mask2 |= ATH9K_INT_DTIMSYNC;
2690                         if (isr2 & (AR_ISR_S2_CABEND))
2691                                 mask2 |= ATH9K_INT_CABEND;
2692                         if (isr2 & AR_ISR_S2_GTT)
2693                                 mask2 |= ATH9K_INT_GTT;
2694                         if (isr2 & AR_ISR_S2_CST)
2695                                 mask2 |= ATH9K_INT_CST;
2696                         if (isr2 & AR_ISR_S2_TSFOOR)
2697                                 mask2 |= ATH9K_INT_TSFOOR;
2698                 }
2699
2700                 isr = REG_READ(ah, AR_ISR_RAC);
2701                 if (isr == 0xffffffff) {
2702                         *masked = 0;
2703                         return false;
2704                 }
2705
2706                 *masked = isr & ATH9K_INT_COMMON;
2707
2708                 if (ah->config.rx_intr_mitigation) {
2709                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2710                                 *masked |= ATH9K_INT_RX;
2711                 }
2712
2713                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2714                         *masked |= ATH9K_INT_RX;
2715                 if (isr &
2716                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2717                      AR_ISR_TXEOL)) {
2718                         u32 s0_s, s1_s;
2719
2720                         *masked |= ATH9K_INT_TX;
2721
2722                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2723                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2724                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2725
2726                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2727                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2728                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2729                 }
2730
2731                 if (isr & AR_ISR_RXORN) {
2732                         ath_print(common, ATH_DBG_INTERRUPT,
2733                                   "receive FIFO overrun interrupt\n");
2734                 }
2735
2736                 if (!AR_SREV_9100(ah)) {
2737                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2738                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2739                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2740                                         *masked |= ATH9K_INT_TIM_TIMER;
2741                         }
2742                 }
2743
2744                 *masked |= mask2;
2745         }
2746
2747         if (AR_SREV_9100(ah))
2748                 return true;
2749
2750         if (isr & AR_ISR_GENTMR) {
2751                 u32 s5_s;
2752
2753                 s5_s = REG_READ(ah, AR_ISR_S5_S);
2754                 if (isr & AR_ISR_GENTMR) {
2755                         ah->intr_gen_timer_trigger =
2756                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2757
2758                         ah->intr_gen_timer_thresh =
2759                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2760
2761                         if (ah->intr_gen_timer_trigger)
2762                                 *masked |= ATH9K_INT_GENTIMER;
2763
2764                 }
2765         }
2766
2767         if (sync_cause) {
2768                 fatal_int =
2769                         (sync_cause &
2770                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2771                         ? true : false;
2772
2773                 if (fatal_int) {
2774                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2775                                 ath_print(common, ATH_DBG_ANY,
2776                                           "received PCI FATAL interrupt\n");
2777                         }
2778                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2779                                 ath_print(common, ATH_DBG_ANY,
2780                                           "received PCI PERR interrupt\n");
2781                         }
2782                         *masked |= ATH9K_INT_FATAL;
2783                 }
2784                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2785                         ath_print(common, ATH_DBG_INTERRUPT,
2786                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2787                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2788                         REG_WRITE(ah, AR_RC, 0);
2789                         *masked |= ATH9K_INT_FATAL;
2790                 }
2791                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2792                         ath_print(common, ATH_DBG_INTERRUPT,
2793                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2794                 }
2795
2796                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2797                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2798         }
2799
2800         return true;
2801 }
2802 EXPORT_SYMBOL(ath9k_hw_getisr);
2803
2804 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2805 {
2806         enum ath9k_int omask = ah->imask;
2807         u32 mask, mask2;
2808         struct ath9k_hw_capabilities *pCap = &ah->caps;
2809         struct ath_common *common = ath9k_hw_common(ah);
2810
2811         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2812
2813         if (omask & ATH9K_INT_GLOBAL) {
2814                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2815                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2816                 (void) REG_READ(ah, AR_IER);
2817                 if (!AR_SREV_9100(ah)) {
2818                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2819                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2820
2821                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2822                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2823                 }
2824         }
2825
2826         mask = ints & ATH9K_INT_COMMON;
2827         mask2 = 0;
2828
2829         if (ints & ATH9K_INT_TX) {
2830                 if (ah->txok_interrupt_mask)
2831                         mask |= AR_IMR_TXOK;
2832                 if (ah->txdesc_interrupt_mask)
2833                         mask |= AR_IMR_TXDESC;
2834                 if (ah->txerr_interrupt_mask)
2835                         mask |= AR_IMR_TXERR;
2836                 if (ah->txeol_interrupt_mask)
2837                         mask |= AR_IMR_TXEOL;
2838         }
2839         if (ints & ATH9K_INT_RX) {
2840                 mask |= AR_IMR_RXERR;
2841                 if (ah->config.rx_intr_mitigation)
2842                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2843                 else
2844                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2845                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2846                         mask |= AR_IMR_GENTMR;
2847         }
2848
2849         if (ints & (ATH9K_INT_BMISC)) {
2850                 mask |= AR_IMR_BCNMISC;
2851                 if (ints & ATH9K_INT_TIM)
2852                         mask2 |= AR_IMR_S2_TIM;
2853                 if (ints & ATH9K_INT_DTIM)
2854                         mask2 |= AR_IMR_S2_DTIM;
2855                 if (ints & ATH9K_INT_DTIMSYNC)
2856                         mask2 |= AR_IMR_S2_DTIMSYNC;
2857                 if (ints & ATH9K_INT_CABEND)
2858                         mask2 |= AR_IMR_S2_CABEND;
2859                 if (ints & ATH9K_INT_TSFOOR)
2860                         mask2 |= AR_IMR_S2_TSFOOR;
2861         }
2862
2863         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2864                 mask |= AR_IMR_BCNMISC;
2865                 if (ints & ATH9K_INT_GTT)
2866                         mask2 |= AR_IMR_S2_GTT;
2867                 if (ints & ATH9K_INT_CST)
2868                         mask2 |= AR_IMR_S2_CST;
2869         }
2870
2871         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2872         REG_WRITE(ah, AR_IMR, mask);
2873         ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2874                            AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2875                            AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2876         ah->imrs2_reg |= mask2;
2877         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2878
2879         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2880                 if (ints & ATH9K_INT_TIM_TIMER)
2881                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2882                 else
2883                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2884         }
2885
2886         if (ints & ATH9K_INT_GLOBAL) {
2887                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2888                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2889                 if (!AR_SREV_9100(ah)) {
2890                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2891                                   AR_INTR_MAC_IRQ);
2892                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2893
2894
2895                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2896                                   AR_INTR_SYNC_DEFAULT);
2897                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2898                                   AR_INTR_SYNC_DEFAULT);
2899                 }
2900                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2901                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2902         }
2903
2904         return omask;
2905 }
2906 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2907
2908 /*******************/
2909 /* Beacon Handling */
2910 /*******************/
2911
2912 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2913 {
2914         int flags = 0;
2915
2916         ah->beacon_interval = beacon_period;
2917
2918         switch (ah->opmode) {
2919         case NL80211_IFTYPE_STATION:
2920         case NL80211_IFTYPE_MONITOR:
2921                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2922                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2923                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2924                 flags |= AR_TBTT_TIMER_EN;
2925                 break;
2926         case NL80211_IFTYPE_ADHOC:
2927         case NL80211_IFTYPE_MESH_POINT:
2928                 REG_SET_BIT(ah, AR_TXCFG,
2929                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2930                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2931                           TU_TO_USEC(next_beacon +
2932                                      (ah->atim_window ? ah->
2933                                       atim_window : 1)));
2934                 flags |= AR_NDP_TIMER_EN;
2935         case NL80211_IFTYPE_AP:
2936                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2937                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2938                           TU_TO_USEC(next_beacon -
2939                                      ah->config.
2940                                      dma_beacon_response_time));
2941                 REG_WRITE(ah, AR_NEXT_SWBA,
2942                           TU_TO_USEC(next_beacon -
2943                                      ah->config.
2944                                      sw_beacon_response_time));
2945                 flags |=
2946                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2947                 break;
2948         default:
2949                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2950                           "%s: unsupported opmode: %d\n",
2951                           __func__, ah->opmode);
2952                 return;
2953                 break;
2954         }
2955
2956         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2957         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2958         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2959         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2960
2961         beacon_period &= ~ATH9K_BEACON_ENA;
2962         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2963                 ath9k_hw_reset_tsf(ah);
2964         }
2965
2966         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2967 }
2968 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2969
2970 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2971                                     const struct ath9k_beacon_state *bs)
2972 {
2973         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2974         struct ath9k_hw_capabilities *pCap = &ah->caps;
2975         struct ath_common *common = ath9k_hw_common(ah);
2976
2977         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2978
2979         REG_WRITE(ah, AR_BEACON_PERIOD,
2980                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2981         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2982                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2983
2984         REG_RMW_FIELD(ah, AR_RSSI_THR,
2985                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2986
2987         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
2988
2989         if (bs->bs_sleepduration > beaconintval)
2990                 beaconintval = bs->bs_sleepduration;
2991
2992         dtimperiod = bs->bs_dtimperiod;
2993         if (bs->bs_sleepduration > dtimperiod)
2994                 dtimperiod = bs->bs_sleepduration;
2995
2996         if (beaconintval == dtimperiod)
2997                 nextTbtt = bs->bs_nextdtim;
2998         else
2999                 nextTbtt = bs->bs_nexttbtt;
3000
3001         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3002         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3003         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3004         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3005
3006         REG_WRITE(ah, AR_NEXT_DTIM,
3007                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3008         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3009
3010         REG_WRITE(ah, AR_SLEEP1,
3011                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3012                   | AR_SLEEP1_ASSUME_DTIM);
3013
3014         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3015                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3016         else
3017                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3018
3019         REG_WRITE(ah, AR_SLEEP2,
3020                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3021
3022         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3023         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3024
3025         REG_SET_BIT(ah, AR_TIMER_MODE,
3026                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3027                     AR_DTIM_TIMER_EN);
3028
3029         /* TSF Out of Range Threshold */
3030         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3031 }
3032 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3033
3034 /*******************/
3035 /* HW Capabilities */
3036 /*******************/
3037
3038 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3039 {
3040         struct ath9k_hw_capabilities *pCap = &ah->caps;
3041         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3042         struct ath_common *common = ath9k_hw_common(ah);
3043         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3044
3045         u16 capField = 0, eeval;
3046
3047         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3048         regulatory->current_rd = eeval;
3049
3050         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3051         if (AR_SREV_9285_10_OR_LATER(ah))
3052                 eeval |= AR9285_RDEXT_DEFAULT;
3053         regulatory->current_rd_ext = eeval;
3054
3055         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3056
3057         if (ah->opmode != NL80211_IFTYPE_AP &&
3058             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3059                 if (regulatory->current_rd == 0x64 ||
3060                     regulatory->current_rd == 0x65)
3061                         regulatory->current_rd += 5;
3062                 else if (regulatory->current_rd == 0x41)
3063                         regulatory->current_rd = 0x43;
3064                 ath_print(common, ATH_DBG_REGULATORY,
3065                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3066         }
3067
3068         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3069         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3070                 ath_print(common, ATH_DBG_FATAL,
3071                           "no band has been marked as supported in EEPROM.\n");
3072                 return -EINVAL;
3073         }
3074
3075         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3076
3077         if (eeval & AR5416_OPFLAGS_11A) {
3078                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3079                 if (ah->config.ht_enable) {
3080                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3081                                 set_bit(ATH9K_MODE_11NA_HT20,
3082                                         pCap->wireless_modes);
3083                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3084                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3085                                         pCap->wireless_modes);
3086                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3087                                         pCap->wireless_modes);
3088                         }
3089                 }
3090         }
3091
3092         if (eeval & AR5416_OPFLAGS_11G) {
3093                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3094                 if (ah->config.ht_enable) {
3095                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3096                                 set_bit(ATH9K_MODE_11NG_HT20,
3097                                         pCap->wireless_modes);
3098                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3099                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3100                                         pCap->wireless_modes);
3101                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3102                                         pCap->wireless_modes);
3103                         }
3104                 }
3105         }
3106
3107         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3108         /*
3109          * For AR9271 we will temporarilly uses the rx chainmax as read from
3110          * the EEPROM.
3111          */
3112         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3113             !(eeval & AR5416_OPFLAGS_11A) &&
3114             !(AR_SREV_9271(ah)))
3115                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3116                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3117         else
3118                 /* Use rx_chainmask from EEPROM. */
3119                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3120
3121         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3122                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3123
3124         pCap->low_2ghz_chan = 2312;
3125         pCap->high_2ghz_chan = 2732;
3126
3127         pCap->low_5ghz_chan = 4920;
3128         pCap->high_5ghz_chan = 6100;
3129
3130         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3131         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3132         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3133
3134         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3135         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3136         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3137
3138         if (ah->config.ht_enable)
3139                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3140         else
3141                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3142
3143         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3144         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3145         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3146         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3147
3148         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3149                 pCap->total_queues =
3150                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3151         else
3152                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3153
3154         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3155                 pCap->keycache_size =
3156                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3157         else
3158                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3159
3160         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3161
3162         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3163                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3164         else
3165                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3166
3167         if (AR_SREV_9271(ah))
3168                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
3169         else if (AR_SREV_9285_10_OR_LATER(ah))
3170                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3171         else if (AR_SREV_9280_10_OR_LATER(ah))
3172                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3173         else
3174                 pCap->num_gpio_pins = AR_NUM_GPIO;
3175
3176         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3177                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3178                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3179         } else {
3180                 pCap->rts_aggr_limit = (8 * 1024);
3181         }
3182
3183         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3184
3185 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3186         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3187         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3188                 ah->rfkill_gpio =
3189                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3190                 ah->rfkill_polarity =
3191                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3192
3193                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3194         }
3195 #endif
3196         if (AR_SREV_9271(ah))
3197                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3198         else
3199                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3200
3201         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3202                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3203         else
3204                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3205
3206         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3207                 pCap->reg_cap =
3208                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3209                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3210                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3211                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3212         } else {
3213                 pCap->reg_cap =
3214                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3215                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3216         }
3217
3218         /* Advertise midband for AR5416 with FCC midband set in eeprom */
3219         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3220             AR_SREV_5416(ah))
3221                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3222
3223         pCap->num_antcfg_5ghz =
3224                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3225         pCap->num_antcfg_2ghz =
3226                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3227
3228         if (AR_SREV_9280_10_OR_LATER(ah) &&
3229             ath9k_hw_btcoex_supported(ah)) {
3230                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3231                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3232
3233                 if (AR_SREV_9285(ah)) {
3234                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3235                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3236                 } else {
3237                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3238                 }
3239         } else {
3240                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3241         }
3242
3243         return 0;
3244 }
3245
3246 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3247                             u32 capability, u32 *result)
3248 {
3249         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3250         switch (type) {
3251         case ATH9K_CAP_CIPHER:
3252                 switch (capability) {
3253                 case ATH9K_CIPHER_AES_CCM:
3254                 case ATH9K_CIPHER_AES_OCB:
3255                 case ATH9K_CIPHER_TKIP:
3256                 case ATH9K_CIPHER_WEP:
3257                 case ATH9K_CIPHER_MIC:
3258                 case ATH9K_CIPHER_CLR:
3259                         return true;
3260                 default:
3261                         return false;
3262                 }
3263         case ATH9K_CAP_TKIP_MIC:
3264                 switch (capability) {
3265                 case 0:
3266                         return true;
3267                 case 1:
3268                         return (ah->sta_id1_defaults &
3269                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3270                         false;
3271                 }
3272         case ATH9K_CAP_TKIP_SPLIT:
3273                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3274                         false : true;
3275         case ATH9K_CAP_DIVERSITY:
3276                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3277                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3278                         true : false;
3279         case ATH9K_CAP_MCAST_KEYSRCH:
3280                 switch (capability) {
3281                 case 0:
3282                         return true;
3283                 case 1:
3284                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3285                                 return false;
3286                         } else {
3287                                 return (ah->sta_id1_defaults &
3288                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3289                                         false;
3290                         }
3291                 }
3292                 return false;
3293         case ATH9K_CAP_TXPOW:
3294                 switch (capability) {
3295                 case 0:
3296                         return 0;
3297                 case 1:
3298                         *result = regulatory->power_limit;
3299                         return 0;
3300                 case 2:
3301                         *result = regulatory->max_power_level;
3302                         return 0;
3303                 case 3:
3304                         *result = regulatory->tp_scale;
3305                         return 0;
3306                 }
3307                 return false;
3308         case ATH9K_CAP_DS:
3309                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3310                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3311                         ? false : true;
3312         default:
3313                 return false;
3314         }
3315 }
3316 EXPORT_SYMBOL(ath9k_hw_getcapability);
3317
3318 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3319                             u32 capability, u32 setting, int *status)
3320 {
3321         u32 v;
3322
3323         switch (type) {
3324         case ATH9K_CAP_TKIP_MIC:
3325                 if (setting)
3326                         ah->sta_id1_defaults |=
3327                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3328                 else
3329                         ah->sta_id1_defaults &=
3330                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3331                 return true;
3332         case ATH9K_CAP_DIVERSITY:
3333                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3334                 if (setting)
3335                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3336                 else
3337                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3338                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3339                 return true;
3340         case ATH9K_CAP_MCAST_KEYSRCH:
3341                 if (setting)
3342                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3343                 else
3344                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3345                 return true;
3346         default:
3347                 return false;
3348         }
3349 }
3350 EXPORT_SYMBOL(ath9k_hw_setcapability);
3351
3352 /****************************/
3353 /* GPIO / RFKILL / Antennae */
3354 /****************************/
3355
3356 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3357                                          u32 gpio, u32 type)
3358 {
3359         int addr;
3360         u32 gpio_shift, tmp;
3361
3362         if (gpio > 11)
3363                 addr = AR_GPIO_OUTPUT_MUX3;
3364         else if (gpio > 5)
3365                 addr = AR_GPIO_OUTPUT_MUX2;
3366         else
3367                 addr = AR_GPIO_OUTPUT_MUX1;
3368
3369         gpio_shift = (gpio % 6) * 5;
3370
3371         if (AR_SREV_9280_20_OR_LATER(ah)
3372             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3373                 REG_RMW(ah, addr, (type << gpio_shift),
3374                         (0x1f << gpio_shift));
3375         } else {
3376                 tmp = REG_READ(ah, addr);
3377                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3378                 tmp &= ~(0x1f << gpio_shift);
3379                 tmp |= (type << gpio_shift);
3380                 REG_WRITE(ah, addr, tmp);
3381         }
3382 }
3383
3384 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3385 {
3386         u32 gpio_shift;
3387
3388         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3389
3390         gpio_shift = gpio << 1;
3391
3392         REG_RMW(ah,
3393                 AR_GPIO_OE_OUT,
3394                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3395                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3396 }
3397 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3398
3399 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3400 {
3401 #define MS_REG_READ(x, y) \
3402         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3403
3404         if (gpio >= ah->caps.num_gpio_pins)
3405                 return 0xffffffff;
3406
3407         if (AR_SREV_9271(ah))
3408                 return MS_REG_READ(AR9271, gpio) != 0;
3409         else if (AR_SREV_9287_10_OR_LATER(ah))
3410                 return MS_REG_READ(AR9287, gpio) != 0;
3411         else if (AR_SREV_9285_10_OR_LATER(ah))
3412                 return MS_REG_READ(AR9285, gpio) != 0;
3413         else if (AR_SREV_9280_10_OR_LATER(ah))
3414                 return MS_REG_READ(AR928X, gpio) != 0;
3415         else
3416                 return MS_REG_READ(AR, gpio) != 0;
3417 }
3418 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3419
3420 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3421                          u32 ah_signal_type)
3422 {
3423         u32 gpio_shift;
3424
3425         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3426
3427         gpio_shift = 2 * gpio;
3428
3429         REG_RMW(ah,
3430                 AR_GPIO_OE_OUT,
3431                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3432                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3433 }
3434 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3435
3436 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3437 {
3438         if (AR_SREV_9271(ah))
3439                 val = ~val;
3440
3441         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3442                 AR_GPIO_BIT(gpio));
3443 }
3444 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3445
3446 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3447 {
3448         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3449 }
3450 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3451
3452 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3453 {
3454         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3455 }
3456 EXPORT_SYMBOL(ath9k_hw_setantenna);
3457
3458 /*********************/
3459 /* General Operation */
3460 /*********************/
3461
3462 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3463 {
3464         u32 bits = REG_READ(ah, AR_RX_FILTER);
3465         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3466
3467         if (phybits & AR_PHY_ERR_RADAR)
3468                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3469         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3470                 bits |= ATH9K_RX_FILTER_PHYERR;
3471
3472         return bits;
3473 }
3474 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3475
3476 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3477 {
3478         u32 phybits;
3479
3480         REG_WRITE(ah, AR_RX_FILTER, bits);
3481
3482         phybits = 0;
3483         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3484                 phybits |= AR_PHY_ERR_RADAR;
3485         if (bits & ATH9K_RX_FILTER_PHYERR)
3486                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3487         REG_WRITE(ah, AR_PHY_ERR, phybits);
3488
3489         if (phybits)
3490                 REG_WRITE(ah, AR_RXCFG,
3491                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3492         else
3493                 REG_WRITE(ah, AR_RXCFG,
3494                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3495 }
3496 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3497
3498 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3499 {
3500         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3501                 return false;
3502
3503         ath9k_hw_init_pll(ah, NULL);
3504         return true;
3505 }
3506 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3507
3508 bool ath9k_hw_disable(struct ath_hw *ah)
3509 {
3510         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3511                 return false;
3512
3513         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3514                 return false;
3515
3516         ath9k_hw_init_pll(ah, NULL);
3517         return true;
3518 }
3519 EXPORT_SYMBOL(ath9k_hw_disable);
3520
3521 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3522 {
3523         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3524         struct ath9k_channel *chan = ah->curchan;
3525         struct ieee80211_channel *channel = chan->chan;
3526
3527         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3528
3529         ah->eep_ops->set_txpower(ah, chan,
3530                                  ath9k_regd_get_ctl(regulatory, chan),
3531                                  channel->max_antenna_gain * 2,
3532                                  channel->max_power * 2,
3533                                  min((u32) MAX_RATE_POWER,
3534                                  (u32) regulatory->power_limit));
3535 }
3536 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3537
3538 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3539 {
3540         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3541 }
3542 EXPORT_SYMBOL(ath9k_hw_setmac);
3543
3544 void ath9k_hw_setopmode(struct ath_hw *ah)
3545 {
3546         ath9k_hw_set_operating_mode(ah, ah->opmode);
3547 }
3548 EXPORT_SYMBOL(ath9k_hw_setopmode);
3549
3550 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3551 {
3552         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3553         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3554 }
3555 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3556
3557 void ath9k_hw_write_associd(struct ath_hw *ah)
3558 {
3559         struct ath_common *common = ath9k_hw_common(ah);
3560
3561         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3562         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3563                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3564 }
3565 EXPORT_SYMBOL(ath9k_hw_write_associd);
3566
3567 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3568 {
3569         u64 tsf;
3570
3571         tsf = REG_READ(ah, AR_TSF_U32);
3572         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3573
3574         return tsf;
3575 }
3576 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3577
3578 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3579 {
3580         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3581         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3582 }
3583 EXPORT_SYMBOL(ath9k_hw_settsf64);
3584
3585 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3586 {
3587         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3588                            AH_TSF_WRITE_TIMEOUT))
3589                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3590                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3591
3592         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3593 }
3594 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3595
3596 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3597 {
3598         if (setting)
3599                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3600         else
3601                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3602 }
3603 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3604
3605 /*
3606  *  Extend 15-bit time stamp from rx descriptor to
3607  *  a full 64-bit TSF using the current h/w TSF.
3608 */
3609 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3610 {
3611         u64 tsf;
3612
3613         tsf = ath9k_hw_gettsf64(ah);
3614         if ((tsf & 0x7fff) < rstamp)
3615                 tsf -= 0x8000;
3616         return (tsf & ~0x7fff) | rstamp;
3617 }
3618 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3619
3620 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3621 {
3622         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3623         u32 macmode;
3624
3625         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3626                 macmode = AR_2040_JOINED_RX_CLEAR;
3627         else
3628                 macmode = 0;
3629
3630         REG_WRITE(ah, AR_2040_MODE, macmode);
3631 }
3632
3633 /* HW Generic timers configuration */
3634
3635 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3636 {
3637         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3638         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3639         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3640         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3641         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3642         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3643         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3644         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3645         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3646         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3647                                 AR_NDP2_TIMER_MODE, 0x0002},
3648         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3649                                 AR_NDP2_TIMER_MODE, 0x0004},
3650         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3651                                 AR_NDP2_TIMER_MODE, 0x0008},
3652         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3653                                 AR_NDP2_TIMER_MODE, 0x0010},
3654         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3655                                 AR_NDP2_TIMER_MODE, 0x0020},
3656         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3657                                 AR_NDP2_TIMER_MODE, 0x0040},
3658         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3659                                 AR_NDP2_TIMER_MODE, 0x0080}
3660 };
3661
3662 /* HW generic timer primitives */
3663
3664 /* compute and clear index of rightmost 1 */
3665 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3666 {
3667         u32 b;
3668
3669         b = *mask;
3670         b &= (0-b);
3671         *mask &= ~b;
3672         b *= debruijn32;
3673         b >>= 27;
3674
3675         return timer_table->gen_timer_index[b];
3676 }
3677
3678 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3679 {
3680         return REG_READ(ah, AR_TSF_L32);
3681 }
3682 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3683
3684 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3685                                           void (*trigger)(void *),
3686                                           void (*overflow)(void *),
3687                                           void *arg,
3688                                           u8 timer_index)
3689 {
3690         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3691         struct ath_gen_timer *timer;
3692
3693         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3694
3695         if (timer == NULL) {
3696                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3697                           "Failed to allocate memory"
3698                           "for hw timer[%d]\n", timer_index);
3699                 return NULL;
3700         }
3701
3702         /* allocate a hardware generic timer slot */
3703         timer_table->timers[timer_index] = timer;
3704         timer->index = timer_index;
3705         timer->trigger = trigger;
3706         timer->overflow = overflow;
3707         timer->arg = arg;
3708
3709         return timer;
3710 }
3711 EXPORT_SYMBOL(ath_gen_timer_alloc);
3712
3713 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3714                               struct ath_gen_timer *timer,
3715                               u32 timer_next,
3716                               u32 timer_period)
3717 {
3718         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3719         u32 tsf;
3720
3721         BUG_ON(!timer_period);
3722
3723         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3724
3725         tsf = ath9k_hw_gettsf32(ah);
3726
3727         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3728                   "curent tsf %x period %x"
3729                   "timer_next %x\n", tsf, timer_period, timer_next);
3730
3731         /*
3732          * Pull timer_next forward if the current TSF already passed it
3733          * because of software latency
3734          */
3735         if (timer_next < tsf)
3736                 timer_next = tsf + timer_period;
3737
3738         /*
3739          * Program generic timer registers
3740          */
3741         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3742                  timer_next);
3743         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3744                   timer_period);
3745         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3746                     gen_tmr_configuration[timer->index].mode_mask);
3747
3748         /* Enable both trigger and thresh interrupt masks */
3749         REG_SET_BIT(ah, AR_IMR_S5,
3750                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3751                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3752 }
3753 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3754
3755 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3756 {
3757         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3758
3759         if ((timer->index < AR_FIRST_NDP_TIMER) ||
3760                 (timer->index >= ATH_MAX_GEN_TIMER)) {
3761                 return;
3762         }
3763
3764         /* Clear generic timer enable bits. */
3765         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3766                         gen_tmr_configuration[timer->index].mode_mask);
3767
3768         /* Disable both trigger and thresh interrupt masks */
3769         REG_CLR_BIT(ah, AR_IMR_S5,
3770                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3771                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3772
3773         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3774 }
3775 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3776
3777 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3778 {
3779         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3780
3781         /* free the hardware generic timer slot */
3782         timer_table->timers[timer->index] = NULL;
3783         kfree(timer);
3784 }
3785 EXPORT_SYMBOL(ath_gen_timer_free);
3786
3787 /*
3788  * Generic Timer Interrupts handling
3789  */
3790 void ath_gen_timer_isr(struct ath_hw *ah)
3791 {
3792         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3793         struct ath_gen_timer *timer;
3794         struct ath_common *common = ath9k_hw_common(ah);
3795         u32 trigger_mask, thresh_mask, index;
3796
3797         /* get hardware generic timer interrupt status */
3798         trigger_mask = ah->intr_gen_timer_trigger;
3799         thresh_mask = ah->intr_gen_timer_thresh;
3800         trigger_mask &= timer_table->timer_mask.val;
3801         thresh_mask &= timer_table->timer_mask.val;
3802
3803         trigger_mask &= ~thresh_mask;
3804
3805         while (thresh_mask) {
3806                 index = rightmost_index(timer_table, &thresh_mask);
3807                 timer = timer_table->timers[index];
3808                 BUG_ON(!timer);
3809                 ath_print(common, ATH_DBG_HWTIMER,
3810                           "TSF overflow for Gen timer %d\n", index);
3811                 timer->overflow(timer->arg);
3812         }
3813
3814         while (trigger_mask) {
3815                 index = rightmost_index(timer_table, &trigger_mask);
3816                 timer = timer_table->timers[index];
3817                 BUG_ON(!timer);
3818                 ath_print(common, ATH_DBG_HWTIMER,
3819                           "Gen timer[%d] trigger\n", index);
3820                 timer->trigger(timer->arg);
3821         }
3822 }
3823 EXPORT_SYMBOL(ath_gen_timer_isr);
3824
3825 /********/
3826 /* HTC  */
3827 /********/
3828
3829 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3830 {
3831         ah->htc_reset_init = true;
3832 }
3833 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3834
3835 static struct {
3836         u32 version;
3837         const char * name;
3838 } ath_mac_bb_names[] = {
3839         /* Devices with external radios */
3840         { AR_SREV_VERSION_5416_PCI,     "5416" },
3841         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3842         { AR_SREV_VERSION_9100,         "9100" },
3843         { AR_SREV_VERSION_9160,         "9160" },
3844         /* Single-chip solutions */
3845         { AR_SREV_VERSION_9280,         "9280" },
3846         { AR_SREV_VERSION_9285,         "9285" },
3847         { AR_SREV_VERSION_9287,         "9287" },
3848         { AR_SREV_VERSION_9271,         "9271" },
3849 };
3850
3851 /* For devices with external radios */
3852 static struct {
3853         u16 version;
3854         const char * name;
3855 } ath_rf_names[] = {
3856         { 0,                            "5133" },
3857         { AR_RAD5133_SREV_MAJOR,        "5133" },
3858         { AR_RAD5122_SREV_MAJOR,        "5122" },
3859         { AR_RAD2133_SREV_MAJOR,        "2133" },
3860         { AR_RAD2122_SREV_MAJOR,        "2122" }
3861 };
3862
3863 /*
3864  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3865  */
3866 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3867 {
3868         int i;
3869
3870         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3871                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3872                         return ath_mac_bb_names[i].name;
3873                 }
3874         }
3875
3876         return "????";
3877 }
3878
3879 /*
3880  * Return the RF name. "????" is returned if the RF is unknown.
3881  * Used for devices with external radios.
3882  */
3883 static const char *ath9k_hw_rf_name(u16 rf_version)
3884 {
3885         int i;
3886
3887         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3888                 if (ath_rf_names[i].version == rf_version) {
3889                         return ath_rf_names[i].name;
3890                 }
3891         }
3892
3893         return "????";
3894 }
3895
3896 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3897 {
3898         int used;
3899
3900         /* chipsets >= AR9280 are single-chip */
3901         if (AR_SREV_9280_10_OR_LATER(ah)) {
3902                 used = snprintf(hw_name, len,
3903                                "Atheros AR%s Rev:%x",
3904                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3905                                ah->hw_version.macRev);
3906         }
3907         else {
3908                 used = snprintf(hw_name, len,
3909                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3910                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3911                                ah->hw_version.macRev,
3912                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3913                                                 AR_RADIO_SREV_MAJOR)),
3914                                ah->hw_version.phyRev);
3915         }
3916
3917         hw_name[used] = '\0';
3918 }
3919 EXPORT_SYMBOL(ath9k_hw_name);