drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <asm/unaligned.h>
  20
  21 #include "hw.h"
  22 #include "rc.h"
  23 #include "initvals.h"
  24
  25 #define ATH9K_CLOCK_RATE_CCK            22
  26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  28
  29 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  30 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  31
  32 MODULE_AUTHOR("Atheros Communications");
  33 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  34 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  35 MODULE_LICENSE("Dual BSD/GPL");
  36
  37 static int __init ath9k_init(void)
  38 {
  39         return 0;
  40 }
  41 module_init(ath9k_init);
  42
  43 static void __exit ath9k_exit(void)
  44 {
  45         return;
  46 }
  47 module_exit(ath9k_exit);
  48
  49 /********************/
  50 /* Helper Functions */
  51 /********************/
  52
  53 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  54 {
  55         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  56
  57         if (!ah->curchan) /* should really check for CCK instead */
  58                 return usecs *ATH9K_CLOCK_RATE_CCK;
  59         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  60                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  61         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  62 }
  63
  64 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  65 {
  66         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  67
  68         if (conf_is_ht40(conf))
  69                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  70         else
  71                 return ath9k_hw_mac_clks(ah, usecs);
  72 }
  73
  74 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  75 {
  76         int i;
  77
  78         BUG_ON(timeout < AH_TIME_QUANTUM);
  79
  80         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  81                 if ((REG_READ(ah, reg) & mask) == val)
  82                         return true;
  83
  84                 udelay(AH_TIME_QUANTUM);
  85         }
  86
  87         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
  88                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  89                   timeout, reg, REG_READ(ah, reg), mask, val);
  90
  91         return false;
  92 }
  93 EXPORT_SYMBOL(ath9k_hw_wait);
  94
  95 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
  96 {
  97         u32 retval;
  98         int i;
  99
 100         for (i = 0, retval = 0; i < n; i++) {
 101                 retval = (retval << 1) | (val & 1);
 102                 val >>= 1;
 103         }
 104         return retval;
 105 }
 106
 107 bool ath9k_get_channel_edges(struct ath_hw *ah,
 108                              u16 flags, u16 *low,
 109                              u16 *high)
 110 {
 111         struct ath9k_hw_capabilities *pCap = &ah->caps;
 112
 113         if (flags & CHANNEL_5GHZ) {
 114                 *low = pCap->low_5ghz_chan;
 115                 *high = pCap->high_5ghz_chan;
 116                 return true;
 117         }
 118         if ((flags & CHANNEL_2GHZ)) {
 119                 *low = pCap->low_2ghz_chan;
 120                 *high = pCap->high_2ghz_chan;
 121                 return true;
 122         }
 123         return false;
 124 }
 125
 126 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 127                            u8 phy, int kbps,
 128                            u32 frameLen, u16 rateix,
 129                            bool shortPreamble)
 130 {
 131         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 132
 133         if (kbps == 0)
 134                 return 0;
 135
 136         switch (phy) {
 137         case WLAN_RC_PHY_CCK:
 138                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 139                 if (shortPreamble)
 140                         phyTime >>= 1;
 141                 numBits = frameLen << 3;
 142                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 143                 break;
 144         case WLAN_RC_PHY_OFDM:
 145                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 146                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 147                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 148                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 149                         txTime = OFDM_SIFS_TIME_QUARTER
 150                                 + OFDM_PREAMBLE_TIME_QUARTER
 151                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 152                 } else if (ah->curchan &&
 153                            IS_CHAN_HALF_RATE(ah->curchan)) {
 154                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 155                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 156                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 157                         txTime = OFDM_SIFS_TIME_HALF +
 158                                 OFDM_PREAMBLE_TIME_HALF
 159                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 160                 } else {
 161                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 162                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 163                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 164                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 165                                 + (numSymbols * OFDM_SYMBOL_TIME);
 166                 }
 167                 break;
 168         default:
 169                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 170                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 171                 txTime = 0;
 172                 break;
 173         }
 174
 175         return txTime;
 176 }
 177 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 178
 179 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 180                                   struct ath9k_channel *chan,
 181                                   struct chan_centers *centers)
 182 {
 183         int8_t extoff;
 184
 185         if (!IS_CHAN_HT40(chan)) {
 186                 centers->ctl_center = centers->ext_center =
 187                         centers->synth_center = chan->channel;
 188                 return;
 189         }
 190
 191         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 192             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 193                 centers->synth_center =
 194                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 195                 extoff = 1;
 196         } else {
 197                 centers->synth_center =
 198                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 199                 extoff = -1;
 200         }
 201
 202         centers->ctl_center =
 203                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 204         /* 25 MHz spacing is supported by hw but not on upper layers */
 205         centers->ext_center =
 206                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 207 }
 208
 209 /******************/
 210 /* Chip Revisions */
 211 /******************/
 212
 213 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 214 {
 215         u32 val;
 216
 217         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 218
 219         if (val == 0xFF) {
 220                 val = REG_READ(ah, AR_SREV);
 221                 ah->hw_version.macVersion =
 222                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 223                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 224                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 225         } else {
 226                 if (!AR_SREV_9100(ah))
 227                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 228
 229                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 230
 231                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 232                         ah->is_pciexpress = true;
 233         }
 234 }
 235
 236 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 237 {
 238         u32 val;
 239         int i;
 240
 241         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 242
 243         for (i = 0; i < 8; i++)
 244                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 245         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 246         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 247
 248         return ath9k_hw_reverse_bits(val, 8);
 249 }
 250
 251 /************************************/
 252 /* HW Attach, Detach, Init Routines */
 253 /************************************/
 254
 255 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 256 {
 257         if (AR_SREV_9100(ah))
 258                 return;
 259
 260         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 261         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 262         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 263         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 264         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 265         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 266         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 267         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 268         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 269
 270         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 271 }
 272
 273 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 274 {
 275         struct ath_common *common = ath9k_hw_common(ah);
 276         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 277         u32 regHold[2];
 278         u32 patternData[4] = { 0x55555555,
 279                                0xaaaaaaaa,
 280                                0x66666666,
 281                                0x99999999 };
 282         int i, j;
 283
 284         for (i = 0; i < 2; i++) {
 285                 u32 addr = regAddr[i];
 286                 u32 wrData, rdData;
 287
 288                 regHold[i] = REG_READ(ah, addr);
 289                 for (j = 0; j < 0x100; j++) {
 290                         wrData = (j << 16) | j;
 291                         REG_WRITE(ah, addr, wrData);
 292                         rdData = REG_READ(ah, addr);
 293                         if (rdData != wrData) {
 294                                 ath_print(common, ATH_DBG_FATAL,
 295                                           "address test failed "
 296                                           "addr: 0x%08x - wr:0x%08x != "
 297                                           "rd:0x%08x\n",
 298                                           addr, wrData, rdData);
 299                                 return false;
 300                         }
 301                 }
 302                 for (j = 0; j < 4; j++) {
 303                         wrData = patternData[j];
 304                         REG_WRITE(ah, addr, wrData);
 305                         rdData = REG_READ(ah, addr);
 306                         if (wrData != rdData) {
 307                                 ath_print(common, ATH_DBG_FATAL,
 308                                           "address test failed "
 309                                           "addr: 0x%08x - wr:0x%08x != "
 310                                           "rd:0x%08x\n",
 311                                           addr, wrData, rdData);
 312                                 return false;
 313                         }
 314                 }
 315                 REG_WRITE(ah, regAddr[i], regHold[i]);
 316         }
 317         udelay(100);
 318
 319         return true;
 320 }
 321
 322 static void ath9k_hw_init_config(struct ath_hw *ah)
 323 {
 324         int i;
 325
 326         ah->config.dma_beacon_response_time = 2;
 327         ah->config.sw_beacon_response_time = 10;
 328         ah->config.additional_swba_backoff = 0;
 329         ah->config.ack_6mb = 0x0;
 330         ah->config.cwm_ignore_extcca = 0;
 331         ah->config.pcie_powersave_enable = 0;
 332         ah->config.pcie_clock_req = 0;
 333         ah->config.pcie_waen = 0;
 334         ah->config.analog_shiftreg = 1;
 335         ah->config.ofdm_trig_low = 200;
 336         ah->config.ofdm_trig_high = 500;
 337         ah->config.cck_trig_high = 200;
 338         ah->config.cck_trig_low = 100;
 339         ah->config.enable_ani = 1;
 340
 341         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 342                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 343                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 344         }
 345
 346         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 347                 ah->config.ht_enable = 1;
 348         else
 349                 ah->config.ht_enable = 0;
 350
 351         ah->config.rx_intr_mitigation = true;
 352
 353         /*
 354          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 355          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 356          * This means we use it for all AR5416 devices, and the few
 357          * minor PCI AR9280 devices out there.
 358          *
 359          * Serialization is required because these devices do not handle
 360          * well the case of two concurrent reads/writes due to the latency
 361          * involved. During one read/write another read/write can be issued
 362          * on another CPU while the previous read/write may still be working
 363          * on our hardware, if we hit this case the hardware poops in a loop.
 364          * We prevent this by serializing reads and writes.
 365          *
 366          * This issue is not present on PCI-Express devices or pre-AR5416
 367          * devices (legacy, 802.11abg).
 368          */
 369         if (num_possible_cpus() > 1)
 370                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 371 }
 372 EXPORT_SYMBOL(ath9k_hw_init);
 373
 374 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 375 {
 376         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 377
 378         regulatory->country_code = CTRY_DEFAULT;
 379         regulatory->power_limit = MAX_RATE_POWER;
 380         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 381
 382         ah->hw_version.magic = AR5416_MAGIC;
 383         ah->hw_version.subvendorid = 0;
 384
 385         ah->ah_flags = 0;
 386         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 387                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 388         if (!AR_SREV_9100(ah))
 389                 ah->ah_flags = AH_USE_EEPROM;
 390
 391         ah->atim_window = 0;
 392         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 393         ah->beacon_interval = 100;
 394         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 395         ah->slottime = (u32) -1;
 396         ah->globaltxtimeout = (u32) -1;
 397         ah->power_mode = ATH9K_PM_UNDEFINED;
 398 }
 399
 400 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 401 {
 402         u32 val;
 403
 404         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 405
 406         val = ath9k_hw_get_radiorev(ah);
 407         switch (val & AR_RADIO_SREV_MAJOR) {
 408         case 0:
 409                 val = AR_RAD5133_SREV_MAJOR;
 410                 break;
 411         case AR_RAD5133_SREV_MAJOR:
 412         case AR_RAD5122_SREV_MAJOR:
 413         case AR_RAD2133_SREV_MAJOR:
 414         case AR_RAD2122_SREV_MAJOR:
 415                 break;
 416         default:
 417                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 418                           "Radio Chip Rev 0x%02X not supported\n",
 419                           val & AR_RADIO_SREV_MAJOR);
 420                 return -EOPNOTSUPP;
 421         }
 422
 423         ah->hw_version.analog5GhzRev = val;
 424
 425         return 0;
 426 }
 427
 428 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 429 {
 430         struct ath_common *common = ath9k_hw_common(ah);
 431         u32 sum;
 432         int i;
 433         u16 eeval;
 434
 435         sum = 0;
 436         for (i = 0; i < 3; i++) {
 437                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 438                 sum += eeval;
 439                 common->macaddr[2 * i] = eeval >> 8;
 440                 common->macaddr[2 * i + 1] = eeval & 0xff;
 441         }
 442         if (sum == 0 || sum == 0xffff * 3)
 443                 return -EADDRNOTAVAIL;
 444
 445         return 0;
 446 }
 447
 448 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 449 {
 450         u32 rxgain_type;
 451
 452         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 453                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 454
 455                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 456                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 457                         ar9280Modes_backoff_13db_rxgain_9280_2,
 458                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 459                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 460                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 461                         ar9280Modes_backoff_23db_rxgain_9280_2,
 462                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 463                 else
 464                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 465                         ar9280Modes_original_rxgain_9280_2,
 466                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 467         } else {
 468                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 469                         ar9280Modes_original_rxgain_9280_2,
 470                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 471         }
 472 }
 473
 474 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 475 {
 476         u32 txgain_type;
 477
 478         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 479                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 480
 481                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 482                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 483                         ar9280Modes_high_power_tx_gain_9280_2,
 484                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 485                 else
 486                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 487                         ar9280Modes_original_tx_gain_9280_2,
 488                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 489         } else {
 490                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 491                 ar9280Modes_original_tx_gain_9280_2,
 492                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 493         }
 494 }
 495
 496 static int ath9k_hw_post_init(struct ath_hw *ah)
 497 {
 498         int ecode;
 499
 500         if (!AR_SREV_9271(ah)) {
 501                 if (!ath9k_hw_chip_test(ah))
 502                         return -ENODEV;
 503         }
 504
 505         ecode = ath9k_hw_rf_claim(ah);
 506         if (ecode != 0)
 507                 return ecode;
 508
 509         ecode = ath9k_hw_eeprom_init(ah);
 510         if (ecode != 0)
 511                 return ecode;
 512
 513         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 514                   "Eeprom VER: %d, REV: %d\n",
 515                   ah->eep_ops->get_eeprom_ver(ah),
 516                   ah->eep_ops->get_eeprom_rev(ah));
 517
 518         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 519                 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 520                 if (ecode) {
 521                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 522                                   "Failed allocating banks for "
 523                                   "external radio\n");
 524                         return ecode;
 525                 }
 526         }
 527
 528         if (!AR_SREV_9100(ah)) {
 529                 ath9k_hw_ani_setup(ah);
 530                 ath9k_hw_ani_init(ah);
 531         }
 532
 533         return 0;
 534 }
 535
 536 static bool ath9k_hw_devid_supported(u16 devid)
 537 {
 538         switch (devid) {
 539         case AR5416_DEVID_PCI:
 540         case AR5416_DEVID_PCIE:
 541         case AR5416_AR9100_DEVID:
 542         case AR9160_DEVID_PCI:
 543         case AR9280_DEVID_PCI:
 544         case AR9280_DEVID_PCIE:
 545         case AR9285_DEVID_PCIE:
 546         case AR5416_DEVID_AR9287_PCI:
 547         case AR5416_DEVID_AR9287_PCIE:
 548         case AR2427_DEVID_PCIE:
 549                 return true;
 550         default:
 551                 break;
 552         }
 553         return false;
 554 }
 555
 556 static bool ath9k_hw_macversion_supported(u32 macversion)
 557 {
 558         switch (macversion) {
 559         case AR_SREV_VERSION_5416_PCI:
 560         case AR_SREV_VERSION_5416_PCIE:
 561         case AR_SREV_VERSION_9160:
 562         case AR_SREV_VERSION_9100:
 563         case AR_SREV_VERSION_9280:
 564         case AR_SREV_VERSION_9285:
 565         case AR_SREV_VERSION_9287:
 566         case AR_SREV_VERSION_9271:
 567                 return true;
 568         default:
 569                 break;
 570         }
 571         return false;
 572 }
 573
 574 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 575 {
 576         if (AR_SREV_9160_10_OR_LATER(ah)) {
 577                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 578                         ah->iq_caldata.calData = &iq_cal_single_sample;
 579                         ah->adcgain_caldata.calData =
 580                                 &adc_gain_cal_single_sample;
 581                         ah->adcdc_caldata.calData =
 582                                 &adc_dc_cal_single_sample;
 583                         ah->adcdc_calinitdata.calData =
 584                                 &adc_init_dc_cal;
 585                 } else {
 586                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 587                         ah->adcgain_caldata.calData =
 588                                 &adc_gain_cal_multi_sample;
 589                         ah->adcdc_caldata.calData =
 590                                 &adc_dc_cal_multi_sample;
 591                         ah->adcdc_calinitdata.calData =
 592                                 &adc_init_dc_cal;
 593                 }
 594                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 595         }
 596 }
 597
 598 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 599 {
 600         if (AR_SREV_9271(ah)) {
 601                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
 602                                ARRAY_SIZE(ar9271Modes_9271), 6);
 603                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
 604                                ARRAY_SIZE(ar9271Common_9271), 2);
 605                 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
 606                                ar9271Common_normal_cck_fir_coeff_9271,
 607                                ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
 608                 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
 609                                ar9271Common_japan_2484_cck_fir_coeff_9271,
 610                                ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
 611                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
 612                                ar9271Modes_9271_1_0_only,
 613                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
 614                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
 615                                ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
 616                 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
 617                                ar9271Modes_high_power_tx_gain_9271,
 618                                ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
 619                 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
 620                                ar9271Modes_normal_power_tx_gain_9271,
 621                                ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
 622                 return;
 623         }
 624
 625         if (AR_SREV_9287_11_OR_LATER(ah)) {
 626                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 627                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 628                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 629                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 630                 if (ah->config.pcie_clock_req)
 631                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 632                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 633                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 634                 else
 635                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 636                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 637                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 638                                         2);
 639         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 640                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 641                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 642                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 643                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 644
 645                 if (ah->config.pcie_clock_req)
 646                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 647                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 648                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 649                 else
 650                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 651                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 652                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 653                                   2);
 654         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 655
 656
 657                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 658                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 659                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 660                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 661
 662                 if (ah->config.pcie_clock_req) {
 663                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 664                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 665                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 666                 } else {
 667                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 668                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 669                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 670                                   2);
 671                 }
 672         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 673                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 674                                ARRAY_SIZE(ar9285Modes_9285), 6);
 675                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 676                                ARRAY_SIZE(ar9285Common_9285), 2);
 677
 678                 if (ah->config.pcie_clock_req) {
 679                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 680                         ar9285PciePhy_clkreq_off_L1_9285,
 681                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 682                 } else {
 683                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 684                         ar9285PciePhy_clkreq_always_on_L1_9285,
 685                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 686                 }
 687         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 688                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 689                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 690                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 691                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 692
 693                 if (ah->config.pcie_clock_req) {
 694                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 695                                ar9280PciePhy_clkreq_off_L1_9280,
 696                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 697                 } else {
 698                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 699                                ar9280PciePhy_clkreq_always_on_L1_9280,
 700                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 701                 }
 702                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 703                                ar9280Modes_fast_clock_9280_2,
 704                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 705         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 706                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 707                                ARRAY_SIZE(ar9280Modes_9280), 6);
 708                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 709                                ARRAY_SIZE(ar9280Common_9280), 2);
 710         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 711                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 712                                ARRAY_SIZE(ar5416Modes_9160), 6);
 713                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 714                                ARRAY_SIZE(ar5416Common_9160), 2);
 715                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 716                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 717                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 718                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 719                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 720                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 721                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 722                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 723                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 724                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 725                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 726                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 727                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 728                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 729                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 730                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 731                 if (AR_SREV_9160_11(ah)) {
 732                         INIT_INI_ARRAY(&ah->iniAddac,
 733                                        ar5416Addac_91601_1,
 734                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 735                 } else {
 736                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 737                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 738                 }
 739         } else if (AR_SREV_9100_OR_LATER(ah)) {
 740                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 741                                ARRAY_SIZE(ar5416Modes_9100), 6);
 742                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 743                                ARRAY_SIZE(ar5416Common_9100), 2);
 744                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 745                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 746                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 747                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 748                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 749                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 750                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 751                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 752                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 753                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 754                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 755                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 756                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 757                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 758                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 759                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 760                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 761                                ARRAY_SIZE(ar5416Addac_9100), 2);
 762         } else {
 763                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 764                                ARRAY_SIZE(ar5416Modes), 6);
 765                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 766                                ARRAY_SIZE(ar5416Common), 2);
 767                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 768                                ARRAY_SIZE(ar5416Bank0), 2);
 769                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 770                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 771                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 772                                ARRAY_SIZE(ar5416Bank1), 2);
 773                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 774                                ARRAY_SIZE(ar5416Bank2), 2);
 775                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 776                                ARRAY_SIZE(ar5416Bank3), 3);
 777                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 778                                ARRAY_SIZE(ar5416Bank6), 3);
 779                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 780                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 781                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 782                                ARRAY_SIZE(ar5416Bank7), 2);
 783                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 784                                ARRAY_SIZE(ar5416Addac), 2);
 785         }
 786 }
 787
 788 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 789 {
 790         if (AR_SREV_9287_11_OR_LATER(ah))
 791                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 792                 ar9287Modes_rx_gain_9287_1_1,
 793                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 794         else if (AR_SREV_9287_10(ah))
 795                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 796                 ar9287Modes_rx_gain_9287_1_0,
 797                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 798         else if (AR_SREV_9280_20(ah))
 799                 ath9k_hw_init_rxgain_ini(ah);
 800
 801         if (AR_SREV_9287_11_OR_LATER(ah)) {
 802                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 803                 ar9287Modes_tx_gain_9287_1_1,
 804                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 805         } else if (AR_SREV_9287_10(ah)) {
 806                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 807                 ar9287Modes_tx_gain_9287_1_0,
 808                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 809         } else if (AR_SREV_9280_20(ah)) {
 810                 ath9k_hw_init_txgain_ini(ah);
 811         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 812                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 813
 814                 /* txgain table */
 815                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 816                         if (AR_SREV_9285E_20(ah)) {
 817                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 818                                 ar9285Modes_XE2_0_high_power,
 819                                 ARRAY_SIZE(
 820                                   ar9285Modes_XE2_0_high_power), 6);
 821                         } else {
 822                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 823                                 ar9285Modes_high_power_tx_gain_9285_1_2,
 824                                 ARRAY_SIZE(
 825                                   ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 826                         }
 827                 } else {
 828                         if (AR_SREV_9285E_20(ah)) {
 829                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 830                                 ar9285Modes_XE2_0_normal_power,
 831                                 ARRAY_SIZE(
 832                                   ar9285Modes_XE2_0_normal_power), 6);
 833                         } else {
 834                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 835                                 ar9285Modes_original_tx_gain_9285_1_2,
 836                                 ARRAY_SIZE(
 837                                   ar9285Modes_original_tx_gain_9285_1_2), 6);
 838                         }
 839                 }
 840         }
 841 }
 842
 843 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
 844 {
 845         struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
 846         struct ath_common *common = ath9k_hw_common(ah);
 847
 848         ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
 849                                  (ah->eep_map != EEP_MAP_4KBITS) &&
 850                                  ((pBase->version & 0xff) > 0x0a) &&
 851                                  (pBase->pwdclkind == 0);
 852
 853         if (ah->need_an_top2_fixup)
 854                 ath_print(common, ATH_DBG_EEPROM,
 855                           "needs fixup for AR_AN_TOP2 register\n");
 856 }
 857
 858 int ath9k_hw_init(struct ath_hw *ah)
 859 {
 860         struct ath_common *common = ath9k_hw_common(ah);
 861         int r = 0;
 862
 863         if (common->bus_ops->ath_bus_type != ATH_USB) {
 864                 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
 865                         ath_print(common, ATH_DBG_FATAL,
 866                                   "Unsupported device ID: 0x%0x\n",
 867                                   ah->hw_version.devid);
 868                         return -EOPNOTSUPP;
 869                 }
 870         }
 871
 872         ath9k_hw_init_defaults(ah);
 873         ath9k_hw_init_config(ah);
 874
 875         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 876                 ath_print(common, ATH_DBG_FATAL,
 877                           "Couldn't reset chip\n");
 878                 return -EIO;
 879         }
 880
 881         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 882                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 883                 return -EIO;
 884         }
 885
 886         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 887                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 888                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 889                         ah->config.serialize_regmode =
 890                                 SER_REG_MODE_ON;
 891                 } else {
 892                         ah->config.serialize_regmode =
 893                                 SER_REG_MODE_OFF;
 894                 }
 895         }
 896
 897         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 898                 ah->config.serialize_regmode);
 899
 900         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 901                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 902         else
 903                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 904
 905         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 906                 ath_print(common, ATH_DBG_FATAL,
 907                           "Mac Chip Rev 0x%02x.%x is not supported by "
 908                           "this driver\n", ah->hw_version.macVersion,
 909                           ah->hw_version.macRev);
 910                 return -EOPNOTSUPP;
 911         }
 912
 913         if (AR_SREV_9100(ah)) {
 914                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 915                 ah->supp_cals = IQ_MISMATCH_CAL;
 916                 ah->is_pciexpress = false;
 917         }
 918
 919         if (AR_SREV_9271(ah))
 920                 ah->is_pciexpress = false;
 921
 922         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 923
 924         ath9k_hw_init_cal_settings(ah);
 925
 926         ah->ani_function = ATH9K_ANI_ALL;
 927         if (AR_SREV_9280_10_OR_LATER(ah)) {
 928                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 929                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
 930                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
 931         } else {
 932                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
 933                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
 934         }
 935
 936         ath9k_hw_init_mode_regs(ah);
 937
 938         if (ah->is_pciexpress)
 939                 ath9k_hw_configpcipowersave(ah, 0, 0);
 940         else
 941                 ath9k_hw_disablepcie(ah);
 942
 943         /* Support for Japan ch.14 (2484) spread */
 944         if (AR_SREV_9287_11_OR_LATER(ah)) {
 945                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 946                        ar9287Common_normal_cck_fir_coeff_92871_1,
 947                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
 948                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 949                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 950                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
 951         }
 952
 953         r = ath9k_hw_post_init(ah);
 954         if (r)
 955                 return r;
 956
 957         ath9k_hw_init_mode_gain_regs(ah);
 958         r = ath9k_hw_fill_cap_info(ah);
 959         if (r)
 960                 return r;
 961
 962         ath9k_hw_init_eeprom_fix(ah);
 963
 964         r = ath9k_hw_init_macaddr(ah);
 965         if (r) {
 966                 ath_print(common, ATH_DBG_FATAL,
 967                           "Failed to initialize MAC address\n");
 968                 return r;
 969         }
 970
 971         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 972                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 973         else
 974                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 975
 976         ath9k_init_nfcal_hist_buffer(ah);
 977
 978         common->state = ATH_HW_INITIALIZED;
 979
 980         return 0;
 981 }
 982
 983 static void ath9k_hw_init_bb(struct ath_hw *ah,
 984                              struct ath9k_channel *chan)
 985 {
 986         u32 synthDelay;
 987
 988         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 989         if (IS_CHAN_B(chan))
 990                 synthDelay = (4 * synthDelay) / 22;
 991         else
 992                 synthDelay /= 10;
 993
 994         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 995
 996         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 997 }
 998
 999 static void ath9k_hw_init_qos(struct ath_hw *ah)
1000 {
1001         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1002         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1003
1004         REG_WRITE(ah, AR_QOS_NO_ACK,
1005                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1006                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1007                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1008
1009         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1010         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1011         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1012         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1013         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1014 }
1015
1016 static void ath9k_hw_init_pll(struct ath_hw *ah,
1017                               struct ath9k_channel *chan)
1018 {
1019         u32 pll;
1020
1021         if (AR_SREV_9100(ah)) {
1022                 if (chan && IS_CHAN_5GHZ(chan))
1023                         pll = 0x1450;
1024                 else
1025                         pll = 0x1458;
1026         } else {
1027                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1028                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1029
1030                         if (chan && IS_CHAN_HALF_RATE(chan))
1031                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1032                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1033                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1034
1035                         if (chan && IS_CHAN_5GHZ(chan)) {
1036                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1037
1038
1039                                 if (AR_SREV_9280_20(ah)) {
1040                                         if (((chan->channel % 20) == 0)
1041                                             || ((chan->channel % 10) == 0))
1042                                                 pll = 0x2850;
1043                                         else
1044                                                 pll = 0x142c;
1045                                 }
1046                         } else {
1047                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1048                         }
1049
1050                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1051
1052                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1053
1054                         if (chan && IS_CHAN_HALF_RATE(chan))
1055                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1056                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1057                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1058
1059                         if (chan && IS_CHAN_5GHZ(chan))
1060                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1061                         else
1062                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1063                 } else {
1064                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1065
1066                         if (chan && IS_CHAN_HALF_RATE(chan))
1067                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1068                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1069                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1070
1071                         if (chan && IS_CHAN_5GHZ(chan))
1072                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1073                         else
1074                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1075                 }
1076         }
1077         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1078
1079         /* Switch the core clock for ar9271 to 117Mhz */
1080         if (AR_SREV_9271(ah)) {
1081                 udelay(500);
1082                 REG_WRITE(ah, 0x50040, 0x304);
1083         }
1084
1085         udelay(RTC_PLL_SETTLE_DELAY);
1086
1087         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1088 }
1089
1090 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1091 {
1092         int rx_chainmask, tx_chainmask;
1093
1094         rx_chainmask = ah->rxchainmask;
1095         tx_chainmask = ah->txchainmask;
1096
1097         switch (rx_chainmask) {
1098         case 0x5:
1099                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1100                             AR_PHY_SWAP_ALT_CHAIN);
1101         case 0x3:
1102                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1103                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1104                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1105                         break;
1106                 }
1107         case 0x1:
1108         case 0x2:
1109         case 0x7:
1110                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1111                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1112                 break;
1113         default:
1114                 break;
1115         }
1116
1117         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1118         if (tx_chainmask == 0x5) {
1119                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1120                             AR_PHY_SWAP_ALT_CHAIN);
1121         }
1122         if (AR_SREV_9100(ah))
1123                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1124                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1125 }
1126
1127 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1128                                           enum nl80211_iftype opmode)
1129 {
1130         u32 imr_reg = AR_IMR_TXERR |
1131                 AR_IMR_TXURN |
1132                 AR_IMR_RXERR |
1133                 AR_IMR_RXORN |
1134                 AR_IMR_BCNMISC;
1135
1136         if (ah->config.rx_intr_mitigation)
1137                 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1138         else
1139                 imr_reg |= AR_IMR_RXOK;
1140
1141         imr_reg |= AR_IMR_TXOK;
1142
1143         if (opmode == NL80211_IFTYPE_AP)
1144                 imr_reg |= AR_IMR_MIB;
1145
1146         REG_WRITE(ah, AR_IMR, imr_reg);
1147         ah->imrs2_reg |= AR_IMR_S2_GTT;
1148         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1149
1150         if (!AR_SREV_9100(ah)) {
1151                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1152                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1153                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1154         }
1155 }
1156
1157 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1158 {
1159         u32 val = ath9k_hw_mac_to_clks(ah, us);
1160         val = min(val, (u32) 0xFFFF);
1161         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1162 }
1163
1164 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1165 {
1166         u32 val = ath9k_hw_mac_to_clks(ah, us);
1167         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1168         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1169 }
1170
1171 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1172 {
1173         u32 val = ath9k_hw_mac_to_clks(ah, us);
1174         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1175         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1176 }
1177
1178 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1179 {
1180         if (tu > 0xFFFF) {
1181                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1182                           "bad global tx timeout %u\n", tu);
1183                 ah->globaltxtimeout = (u32) -1;
1184                 return false;
1185         } else {
1186                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1187                 ah->globaltxtimeout = tu;
1188                 return true;
1189         }
1190 }
1191
1192 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1193 {
1194         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1195         int acktimeout;
1196         int slottime;
1197         int sifstime;
1198
1199         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1200                   ah->misc_mode);
1201
1202         if (ah->misc_mode != 0)
1203                 REG_WRITE(ah, AR_PCU_MISC,
1204                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1205
1206         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1207                 sifstime = 16;
1208         else
1209                 sifstime = 10;
1210
1211         /* As defined by IEEE 802.11-2007 17.3.8.6 */
1212         slottime = ah->slottime + 3 * ah->coverage_class;
1213         acktimeout = slottime + sifstime;
1214
1215         /*
1216          * Workaround for early ACK timeouts, add an offset to match the
1217          * initval's 64us ack timeout value.
1218          * This was initially only meant to work around an issue with delayed
1219          * BA frames in some implementations, but it has been found to fix ACK
1220          * timeout issues in other cases as well.
1221          */
1222         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1223                 acktimeout += 64 - sifstime - ah->slottime;
1224
1225         ath9k_hw_setslottime(ah, slottime);
1226         ath9k_hw_set_ack_timeout(ah, acktimeout);
1227         ath9k_hw_set_cts_timeout(ah, acktimeout);
1228         if (ah->globaltxtimeout != (u32) -1)
1229                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1230 }
1231 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1232
1233 void ath9k_hw_deinit(struct ath_hw *ah)
1234 {
1235         struct ath_common *common = ath9k_hw_common(ah);
1236
1237         if (common->state < ATH_HW_INITIALIZED)
1238                 goto free_hw;
1239
1240         if (!AR_SREV_9100(ah))
1241                 ath9k_hw_ani_disable(ah);
1242
1243         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1244
1245 free_hw:
1246         if (!AR_SREV_9280_10_OR_LATER(ah))
1247                 ath9k_hw_rf_free_ext_banks(ah);
1248 }
1249 EXPORT_SYMBOL(ath9k_hw_deinit);
1250
1251 /*******/
1252 /* INI */
1253 /*******/
1254
1255 static void ath9k_hw_override_ini(struct ath_hw *ah,
1256                                   struct ath9k_channel *chan)
1257 {
1258         u32 val;
1259
1260         /*
1261          * Set the RX_ABORT and RX_DIS and clear if off only after
1262          * RXE is set for MAC. This prevents frames with corrupted
1263          * descriptor status.
1264          */
1265         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1266
1267         if (AR_SREV_9280_10_OR_LATER(ah)) {
1268                 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1269
1270                 if (!AR_SREV_9271(ah))
1271                         val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1272
1273                 if (AR_SREV_9287_10_OR_LATER(ah))
1274                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1275
1276                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1277         }
1278
1279         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1280             AR_SREV_9280_10_OR_LATER(ah))
1281                 return;
1282         /*
1283          * Disable BB clock gating
1284          * Necessary to avoid issues on AR5416 2.0
1285          */
1286         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1287
1288         /*
1289          * Disable RIFS search on some chips to avoid baseband
1290          * hang issues.
1291          */
1292         if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1293                 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1294                 val &= ~AR_PHY_RIFS_INIT_DELAY;
1295                 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1296         }
1297 }
1298
1299 static void ath9k_olc_init(struct ath_hw *ah)
1300 {
1301         u32 i;
1302
1303         if (OLC_FOR_AR9287_10_LATER) {
1304                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1305                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1306                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1307                                 AR9287_AN_TXPC0_TXPCMODE,
1308                                 AR9287_AN_TXPC0_TXPCMODE_S,
1309                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1310                 udelay(100);
1311         } else {
1312                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1313                         ah->originalGain[i] =
1314                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1315                                                 AR_PHY_TX_GAIN);
1316                 ah->PDADCdelta = 0;
1317         }
1318 }
1319
1320 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1321                               struct ath9k_channel *chan)
1322 {
1323         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1324
1325         if (IS_CHAN_B(chan))
1326                 ctl |= CTL_11B;
1327         else if (IS_CHAN_G(chan))
1328                 ctl |= CTL_11G;
1329         else
1330                 ctl |= CTL_11A;
1331
1332         return ctl;
1333 }
1334
1335 static int ath9k_hw_process_ini(struct ath_hw *ah,
1336                                 struct ath9k_channel *chan)
1337 {
1338         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1339         int i, regWrites = 0;
1340         struct ieee80211_channel *channel = chan->chan;
1341         u32 modesIndex, freqIndex;
1342
1343         switch (chan->chanmode) {
1344         case CHANNEL_A:
1345         case CHANNEL_A_HT20:
1346                 modesIndex = 1;
1347                 freqIndex = 1;
1348                 break;
1349         case CHANNEL_A_HT40PLUS:
1350         case CHANNEL_A_HT40MINUS:
1351                 modesIndex = 2;
1352                 freqIndex = 1;
1353                 break;
1354         case CHANNEL_G:
1355         case CHANNEL_G_HT20:
1356         case CHANNEL_B:
1357                 modesIndex = 4;
1358                 freqIndex = 2;
1359                 break;
1360         case CHANNEL_G_HT40PLUS:
1361         case CHANNEL_G_HT40MINUS:
1362                 modesIndex = 3;
1363                 freqIndex = 2;
1364                 break;
1365
1366         default:
1367                 return -EINVAL;
1368         }
1369
1370         /* Set correct baseband to analog shift setting to access analog chips */
1371         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1372
1373         /* Write ADDAC shifts */
1374         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1375         ah->eep_ops->set_addac(ah, chan);
1376
1377         if (AR_SREV_5416_22_OR_LATER(ah)) {
1378                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1379         } else {
1380                 struct ar5416IniArray temp;
1381                 u32 addacSize =
1382                         sizeof(u32) * ah->iniAddac.ia_rows *
1383                         ah->iniAddac.ia_columns;
1384
1385                 /* For AR5416 2.0/2.1 */
1386                 memcpy(ah->addac5416_21,
1387                        ah->iniAddac.ia_array, addacSize);
1388
1389                 /* override CLKDRV value at [row, column] = [31, 1] */
1390                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1391
1392                 temp.ia_array = ah->addac5416_21;
1393                 temp.ia_columns = ah->iniAddac.ia_columns;
1394                 temp.ia_rows = ah->iniAddac.ia_rows;
1395                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1396         }
1397
1398         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1399
1400         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1401                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1402                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1403
1404                 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1405                         val &= ~AR_AN_TOP2_PWDCLKIND;
1406
1407                 REG_WRITE(ah, reg, val);
1408
1409                 if (reg >= 0x7800 && reg < 0x78a0
1410                     && ah->config.analog_shiftreg) {
1411                         udelay(100);
1412                 }
1413
1414                 DO_DELAY(regWrites);
1415         }
1416
1417         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1418                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1419
1420         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1421             AR_SREV_9287_10_OR_LATER(ah))
1422                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1423
1424         if (AR_SREV_9271_10(ah))
1425                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1426                                 modesIndex, regWrites);
1427
1428         /* Write common array parameters */
1429         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1430                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1431                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1432
1433                 REG_WRITE(ah, reg, val);
1434
1435                 if (reg >= 0x7800 && reg < 0x78a0
1436                     && ah->config.analog_shiftreg) {
1437                         udelay(100);
1438                 }
1439
1440                 DO_DELAY(regWrites);
1441         }
1442
1443         if (AR_SREV_9271(ah)) {
1444                 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1445                         REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1446                                         modesIndex, regWrites);
1447                 else
1448                         REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1449                                         modesIndex, regWrites);
1450         }
1451
1452         ath9k_hw_write_regs(ah, freqIndex, regWrites);
1453
1454         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1455                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1456                                 regWrites);
1457         }
1458
1459         ath9k_hw_override_ini(ah, chan);
1460         ath9k_hw_set_regs(ah, chan);
1461         ath9k_hw_init_chain_masks(ah);
1462
1463         if (OLC_FOR_AR9280_20_LATER)
1464                 ath9k_olc_init(ah);
1465
1466         /* Set TX power */
1467         ah->eep_ops->set_txpower(ah, chan,
1468                                  ath9k_regd_get_ctl(regulatory, chan),
1469                                  channel->max_antenna_gain * 2,
1470                                  channel->max_power * 2,
1471                                  min((u32) MAX_RATE_POWER,
1472                                  (u32) regulatory->power_limit));
1473
1474         /* Write analog registers */
1475         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1476                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1477                           "ar5416SetRfRegs failed\n");
1478                 return -EIO;
1479         }
1480
1481         return 0;
1482 }
1483
1484 /****************************************/
1485 /* Reset and Channel Switching Routines */
1486 /****************************************/
1487
1488 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1489 {
1490         u32 rfMode = 0;
1491
1492         if (chan == NULL)
1493                 return;
1494
1495         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1496                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1497
1498         if (!AR_SREV_9280_10_OR_LATER(ah))
1499                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1500                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1501
1502         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1503                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1504
1505         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1506 }
1507
1508 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1509 {
1510         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1511 }
1512
1513 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1514 {
1515         u32 regval;
1516
1517         /*
1518          * set AHB_MODE not to do cacheline prefetches
1519         */
1520         regval = REG_READ(ah, AR_AHB_MODE);
1521         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1522
1523         /*
1524          * let mac dma reads be in 128 byte chunks
1525          */
1526         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1527         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1528
1529         /*
1530          * Restore TX Trigger Level to its pre-reset value.
1531          * The initial value depends on whether aggregation is enabled, and is
1532          * adjusted whenever underruns are detected.
1533          */
1534         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1535
1536         /*
1537          * let mac dma writes be in 128 byte chunks
1538          */
1539         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1540         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1541
1542         /*
1543          * Setup receive FIFO threshold to hold off TX activities
1544          */
1545         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1546
1547         /*
1548          * reduce the number of usable entries in PCU TXBUF to avoid
1549          * wrap around issues.
1550          */
1551         if (AR_SREV_9285(ah)) {
1552                 /* For AR9285 the number of Fifos are reduced to half.
1553                  * So set the usable tx buf size also to half to
1554                  * avoid data/delimiter underruns
1555                  */
1556                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1557                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1558         } else if (!AR_SREV_9271(ah)) {
1559                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1560                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1561         }
1562 }
1563
1564 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1565 {
1566         u32 val;
1567
1568         val = REG_READ(ah, AR_STA_ID1);
1569         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1570         switch (opmode) {
1571         case NL80211_IFTYPE_AP:
1572                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1573                           | AR_STA_ID1_KSRCH_MODE);
1574                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1575                 break;
1576         case NL80211_IFTYPE_ADHOC:
1577         case NL80211_IFTYPE_MESH_POINT:
1578                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1579                           | AR_STA_ID1_KSRCH_MODE);
1580                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1581                 break;
1582         case NL80211_IFTYPE_STATION:
1583         case NL80211_IFTYPE_MONITOR:
1584                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1585                 break;
1586         }
1587 }
1588
1589 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1590                                                  u32 coef_scaled,
1591                                                  u32 *coef_mantissa,
1592                                                  u32 *coef_exponent)
1593 {
1594         u32 coef_exp, coef_man;
1595
1596         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1597                 if ((coef_scaled >> coef_exp) & 0x1)
1598                         break;
1599
1600         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1601
1602         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1603
1604         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1605         *coef_exponent = coef_exp - 16;
1606 }
1607
1608 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1609                                      struct ath9k_channel *chan)
1610 {
1611         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1612         u32 clockMhzScaled = 0x64000000;
1613         struct chan_centers centers;
1614
1615         if (IS_CHAN_HALF_RATE(chan))
1616                 clockMhzScaled = clockMhzScaled >> 1;
1617         else if (IS_CHAN_QUARTER_RATE(chan))
1618                 clockMhzScaled = clockMhzScaled >> 2;
1619
1620         ath9k_hw_get_channel_centers(ah, chan, &centers);
1621         coef_scaled = clockMhzScaled / centers.synth_center;
1622
1623         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1624                                       &ds_coef_exp);
1625
1626         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1627                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1628         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1629                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1630
1631         coef_scaled = (9 * coef_scaled) / 10;
1632
1633         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1634                                       &ds_coef_exp);
1635
1636         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1637                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1638         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1639                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1640 }
1641
1642 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1643 {
1644         u32 rst_flags;
1645         u32 tmpReg;
1646
1647         if (AR_SREV_9100(ah)) {
1648                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1649                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1650                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1651                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1652                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1653         }
1654
1655         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1656                   AR_RTC_FORCE_WAKE_ON_INT);
1657
1658         if (AR_SREV_9100(ah)) {
1659                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1660                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1661         } else {
1662                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1663                 if (tmpReg &
1664                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1665                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1666                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1667                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1668                 } else {
1669                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1670                 }
1671
1672                 rst_flags = AR_RTC_RC_MAC_WARM;
1673                 if (type == ATH9K_RESET_COLD)
1674                         rst_flags |= AR_RTC_RC_MAC_COLD;
1675         }
1676
1677         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1678         udelay(50);
1679
1680         REG_WRITE(ah, AR_RTC_RC, 0);
1681         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1682                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1683                           "RTC stuck in MAC reset\n");
1684                 return false;
1685         }
1686
1687         if (!AR_SREV_9100(ah))
1688                 REG_WRITE(ah, AR_RC, 0);
1689
1690         if (AR_SREV_9100(ah))
1691                 udelay(50);
1692
1693         return true;
1694 }
1695
1696 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1697 {
1698         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1699                   AR_RTC_FORCE_WAKE_ON_INT);
1700
1701         if (!AR_SREV_9100(ah))
1702                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1703
1704         REG_WRITE(ah, AR_RTC_RESET, 0);
1705         udelay(2);
1706
1707         if (!AR_SREV_9100(ah))
1708                 REG_WRITE(ah, AR_RC, 0);
1709
1710         REG_WRITE(ah, AR_RTC_RESET, 1);
1711
1712         if (!ath9k_hw_wait(ah,
1713                            AR_RTC_STATUS,
1714                            AR_RTC_STATUS_M,
1715                            AR_RTC_STATUS_ON,
1716                            AH_WAIT_TIMEOUT)) {
1717                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1718                           "RTC not waking up\n");
1719                 return false;
1720         }
1721
1722         ath9k_hw_read_revisions(ah);
1723
1724         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1725 }
1726
1727 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1728 {
1729         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1730                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1731
1732         switch (type) {
1733         case ATH9K_RESET_POWER_ON:
1734                 return ath9k_hw_set_reset_power_on(ah);
1735         case ATH9K_RESET_WARM:
1736         case ATH9K_RESET_COLD:
1737                 return ath9k_hw_set_reset(ah, type);
1738         default:
1739                 return false;
1740         }
1741 }
1742
1743 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1744 {
1745         u32 phymode;
1746         u32 enableDacFifo = 0;
1747
1748         if (AR_SREV_9285_10_OR_LATER(ah))
1749                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1750                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1751
1752         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1753                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1754
1755         if (IS_CHAN_HT40(chan)) {
1756                 phymode |= AR_PHY_FC_DYN2040_EN;
1757
1758                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1759                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1760                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1761
1762         }
1763         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1764
1765         ath9k_hw_set11nmac2040(ah);
1766
1767         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1768         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1769 }
1770
1771 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1772                                 struct ath9k_channel *chan)
1773 {
1774         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1775                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1776                         return false;
1777         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1778                 return false;
1779
1780         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1781                 return false;
1782
1783         ah->chip_fullsleep = false;
1784         ath9k_hw_init_pll(ah, chan);
1785         ath9k_hw_set_rfmode(ah, chan);
1786
1787         return true;
1788 }
1789
1790 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1791                                     struct ath9k_channel *chan)
1792 {
1793         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1794         struct ath_common *common = ath9k_hw_common(ah);
1795         struct ieee80211_channel *channel = chan->chan;
1796         u32 synthDelay, qnum;
1797         int r;
1798
1799         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1800                 if (ath9k_hw_numtxpending(ah, qnum)) {
1801                         ath_print(common, ATH_DBG_QUEUE,
1802                                   "Transmit frames pending on "
1803                                   "queue %d\n", qnum);
1804                         return false;
1805                 }
1806         }
1807
1808         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1809         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1810                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1811                 ath_print(common, ATH_DBG_FATAL,
1812                           "Could not kill baseband RX\n");
1813                 return false;
1814         }
1815
1816         ath9k_hw_set_regs(ah, chan);
1817
1818         r = ah->ath9k_hw_rf_set_freq(ah, chan);
1819         if (r) {
1820                 ath_print(common, ATH_DBG_FATAL,
1821                           "Failed to set channel\n");
1822                 return false;
1823         }
1824
1825         ah->eep_ops->set_txpower(ah, chan,
1826                              ath9k_regd_get_ctl(regulatory, chan),
1827                              channel->max_antenna_gain * 2,
1828                              channel->max_power * 2,
1829                              min((u32) MAX_RATE_POWER,
1830                              (u32) regulatory->power_limit));
1831
1832         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1833         if (IS_CHAN_B(chan))
1834                 synthDelay = (4 * synthDelay) / 22;
1835         else
1836                 synthDelay /= 10;
1837
1838         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1839
1840         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1841
1842         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1843                 ath9k_hw_set_delta_slope(ah, chan);
1844
1845         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1846
1847         if (!chan->oneTimeCalsDone)
1848                 chan->oneTimeCalsDone = true;
1849
1850         return true;
1851 }
1852
1853 static void ath9k_enable_rfkill(struct ath_hw *ah)
1854 {
1855         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1856                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1857
1858         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1859                     AR_GPIO_INPUT_MUX2_RFSILENT);
1860
1861         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1862         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1863 }
1864
1865 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1866                     bool bChannelChange)
1867 {
1868         struct ath_common *common = ath9k_hw_common(ah);
1869         u32 saveLedState;
1870         struct ath9k_channel *curchan = ah->curchan;
1871         u32 saveDefAntenna;
1872         u32 macStaId1;
1873         u64 tsf = 0;
1874         int i, rx_chainmask, r;
1875
1876         ah->txchainmask = common->tx_chainmask;
1877         ah->rxchainmask = common->rx_chainmask;
1878
1879         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1880                 return -EIO;
1881
1882         if (curchan && !ah->chip_fullsleep)
1883                 ath9k_hw_getnf(ah, curchan);
1884
1885         if (bChannelChange &&
1886             (ah->chip_fullsleep != true) &&
1887             (ah->curchan != NULL) &&
1888             (chan->channel != ah->curchan->channel) &&
1889             ((chan->channelFlags & CHANNEL_ALL) ==
1890              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1891              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1892              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1893
1894                 if (ath9k_hw_channel_change(ah, chan)) {
1895                         ath9k_hw_loadnf(ah, ah->curchan);
1896                         ath9k_hw_start_nfcal(ah);
1897                         return 0;
1898                 }
1899         }
1900
1901         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1902         if (saveDefAntenna == 0)
1903                 saveDefAntenna = 1;
1904
1905         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1906
1907         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1908         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1909                 tsf = ath9k_hw_gettsf64(ah);
1910
1911         saveLedState = REG_READ(ah, AR_CFG_LED) &
1912                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1913                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1914
1915         ath9k_hw_mark_phy_inactive(ah);
1916
1917         /* Only required on the first reset */
1918         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1919                 REG_WRITE(ah,
1920                           AR9271_RESET_POWER_DOWN_CONTROL,
1921                           AR9271_RADIO_RF_RST);
1922                 udelay(50);
1923         }
1924
1925         if (!ath9k_hw_chip_reset(ah, chan)) {
1926                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1927                 return -EINVAL;
1928         }
1929
1930         /* Only required on the first reset */
1931         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1932                 ah->htc_reset_init = false;
1933                 REG_WRITE(ah,
1934                           AR9271_RESET_POWER_DOWN_CONTROL,
1935                           AR9271_GATE_MAC_CTL);
1936                 udelay(50);
1937         }
1938
1939         /* Restore TSF */
1940         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1941                 ath9k_hw_settsf64(ah, tsf);
1942
1943         if (AR_SREV_9280_10_OR_LATER(ah))
1944                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1945
1946         if (AR_SREV_9287_12_OR_LATER(ah)) {
1947                 /* Enable ASYNC FIFO */
1948                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1949                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1950                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1951                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1952                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1953                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1954                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1955         }
1956         r = ath9k_hw_process_ini(ah, chan);
1957         if (r)
1958                 return r;
1959
1960         /* Setup MFP options for CCMP */
1961         if (AR_SREV_9280_20_OR_LATER(ah)) {
1962                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1963                  * frames when constructing CCMP AAD. */
1964                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1965                               0xc7ff);
1966                 ah->sw_mgmt_crypto = false;
1967         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1968                 /* Disable hardware crypto for management frames */
1969                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1970                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1971                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1972                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1973                 ah->sw_mgmt_crypto = true;
1974         } else
1975                 ah->sw_mgmt_crypto = true;
1976
1977         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1978                 ath9k_hw_set_delta_slope(ah, chan);
1979
1980         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1981         ah->eep_ops->set_board_values(ah, chan);
1982
1983         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1984         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1985                   | macStaId1
1986                   | AR_STA_ID1_RTS_USE_DEF
1987                   | (ah->config.
1988                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1989                   | ah->sta_id1_defaults);
1990         ath9k_hw_set_operating_mode(ah, ah->opmode);
1991
1992         ath_hw_setbssidmask(common);
1993
1994         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1995
1996         ath9k_hw_write_associd(ah);
1997
1998         REG_WRITE(ah, AR_ISR, ~0);
1999
2000         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2001
2002         r = ah->ath9k_hw_rf_set_freq(ah, chan);
2003         if (r)
2004                 return r;
2005
2006         for (i = 0; i < AR_NUM_DCU; i++)
2007                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2008
2009         ah->intr_txqs = 0;
2010         for (i = 0; i < ah->caps.total_queues; i++)
2011                 ath9k_hw_resettxqueue(ah, i);
2012
2013         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2014         ath9k_hw_init_qos(ah);
2015
2016         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2017                 ath9k_enable_rfkill(ah);
2018
2019         ath9k_hw_init_global_settings(ah);
2020
2021         if (AR_SREV_9287_12_OR_LATER(ah)) {
2022                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2023                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2024                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2025                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2026                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2027                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2028
2029                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2030                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2031
2032                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2033                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2034                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2035                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2036         }
2037         if (AR_SREV_9287_12_OR_LATER(ah)) {
2038                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2039                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2040         }
2041
2042         REG_WRITE(ah, AR_STA_ID1,
2043                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2044
2045         ath9k_hw_set_dma(ah);
2046
2047         REG_WRITE(ah, AR_OBS, 8);
2048
2049         if (ah->config.rx_intr_mitigation) {
2050                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2051                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2052         }
2053
2054         ath9k_hw_init_bb(ah, chan);
2055
2056         if (!ath9k_hw_init_cal(ah, chan))
2057                 return -EIO;
2058
2059         rx_chainmask = ah->rxchainmask;
2060         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2061                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2062                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2063         }
2064
2065         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2066
2067         /*
2068          * For big endian systems turn on swapping for descriptors
2069          */
2070         if (AR_SREV_9100(ah)) {
2071                 u32 mask;
2072                 mask = REG_READ(ah, AR_CFG);
2073                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2074                         ath_print(common, ATH_DBG_RESET,
2075                                 "CFG Byte Swap Set 0x%x\n", mask);
2076                 } else {
2077                         mask =
2078                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2079                         REG_WRITE(ah, AR_CFG, mask);
2080                         ath_print(common, ATH_DBG_RESET,
2081                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2082                 }
2083         } else {
2084                 /* Configure AR9271 target WLAN */
2085                 if (AR_SREV_9271(ah))
2086                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2087 #ifdef __BIG_ENDIAN
2088                 else
2089                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2090 #endif
2091         }
2092
2093         if (ah->btcoex_hw.enabled)
2094                 ath9k_hw_btcoex_enable(ah);
2095
2096         return 0;
2097 }
2098 EXPORT_SYMBOL(ath9k_hw_reset);
2099
2100 /************************/
2101 /* Key Cache Management */
2102 /************************/
2103
2104 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2105 {
2106         u32 keyType;
2107
2108         if (entry >= ah->caps.keycache_size) {
2109                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2110                           "keychache entry %u out of range\n", entry);
2111                 return false;
2112         }
2113
2114         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2115
2116         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2117         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2118         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2119         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2120         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2121         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2122         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2123         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2124
2125         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2126                 u16 micentry = entry + 64;
2127
2128                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2129                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2130                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2131                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2132
2133         }
2134
2135         return true;
2136 }
2137 EXPORT_SYMBOL(ath9k_hw_keyreset);
2138
2139 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2140 {
2141         u32 macHi, macLo;
2142
2143         if (entry >= ah->caps.keycache_size) {
2144                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2145                           "keychache entry %u out of range\n", entry);
2146                 return false;
2147         }
2148
2149         if (mac != NULL) {
2150                 macHi = (mac[5] << 8) | mac[4];
2151                 macLo = (mac[3] << 24) |
2152                         (mac[2] << 16) |
2153                         (mac[1] << 8) |
2154                         mac[0];
2155                 macLo >>= 1;
2156                 macLo |= (macHi & 1) << 31;
2157                 macHi >>= 1;
2158         } else {
2159                 macLo = macHi = 0;
2160         }
2161         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2162         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2163
2164         return true;
2165 }
2166 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2167
2168 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2169                                  const struct ath9k_keyval *k,
2170                                  const u8 *mac)
2171 {
2172         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2173         struct ath_common *common = ath9k_hw_common(ah);
2174         u32 key0, key1, key2, key3, key4;
2175         u32 keyType;
2176
2177         if (entry >= pCap->keycache_size) {
2178                 ath_print(common, ATH_DBG_FATAL,
2179                           "keycache entry %u out of range\n", entry);
2180                 return false;
2181         }
2182
2183         switch (k->kv_type) {
2184         case ATH9K_CIPHER_AES_OCB:
2185                 keyType = AR_KEYTABLE_TYPE_AES;
2186                 break;
2187         case ATH9K_CIPHER_AES_CCM:
2188                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2189                         ath_print(common, ATH_DBG_ANY,
2190                                   "AES-CCM not supported by mac rev 0x%x\n",
2191                                   ah->hw_version.macRev);
2192                         return false;
2193                 }
2194                 keyType = AR_KEYTABLE_TYPE_CCM;
2195                 break;
2196         case ATH9K_CIPHER_TKIP:
2197                 keyType = AR_KEYTABLE_TYPE_TKIP;
2198                 if (ATH9K_IS_MIC_ENABLED(ah)
2199                     && entry + 64 >= pCap->keycache_size) {
2200                         ath_print(common, ATH_DBG_ANY,
2201                                   "entry %u inappropriate for TKIP\n", entry);
2202                         return false;
2203                 }
2204                 break;
2205         case ATH9K_CIPHER_WEP:
2206                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2207                         ath_print(common, ATH_DBG_ANY,
2208                                   "WEP key length %u too small\n", k->kv_len);
2209                         return false;
2210                 }
2211                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2212                         keyType = AR_KEYTABLE_TYPE_40;
2213                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2214                         keyType = AR_KEYTABLE_TYPE_104;
2215                 else
2216                         keyType = AR_KEYTABLE_TYPE_128;
2217                 break;
2218         case ATH9K_CIPHER_CLR:
2219                 keyType = AR_KEYTABLE_TYPE_CLR;
2220                 break;
2221         default:
2222                 ath_print(common, ATH_DBG_FATAL,
2223                           "cipher %u not supported\n", k->kv_type);
2224                 return false;
2225         }
2226
2227         key0 = get_unaligned_le32(k->kv_val + 0);
2228         key1 = get_unaligned_le16(k->kv_val + 4);
2229         key2 = get_unaligned_le32(k->kv_val + 6);
2230         key3 = get_unaligned_le16(k->kv_val + 10);
2231         key4 = get_unaligned_le32(k->kv_val + 12);
2232         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2233                 key4 &= 0xff;
2234
2235         /*
2236          * Note: Key cache registers access special memory area that requires
2237          * two 32-bit writes to actually update the values in the internal
2238          * memory. Consequently, the exact order and pairs used here must be
2239          * maintained.
2240          */
2241
2242         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2243                 u16 micentry = entry + 64;
2244
2245                 /*
2246                  * Write inverted key[47:0] first to avoid Michael MIC errors
2247                  * on frames that could be sent or received at the same time.
2248                  * The correct key will be written in the end once everything
2249                  * else is ready.
2250                  */
2251                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2252                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2253
2254                 /* Write key[95:48] */
2255                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2256                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2257
2258                 /* Write key[127:96] and key type */
2259                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2260                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2261
2262                 /* Write MAC address for the entry */
2263                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2264
2265                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2266                         /*
2267                          * TKIP uses two key cache entries:
2268                          * Michael MIC TX/RX keys in the same key cache entry
2269                          * (idx = main index + 64):
2270                          * key0 [31:0] = RX key [31:0]
2271                          * key1 [15:0] = TX key [31:16]
2272                          * key1 [31:16] = reserved
2273                          * key2 [31:0] = RX key [63:32]
2274                          * key3 [15:0] = TX key [15:0]
2275                          * key3 [31:16] = reserved
2276                          * key4 [31:0] = TX key [63:32]
2277                          */
2278                         u32 mic0, mic1, mic2, mic3, mic4;
2279
2280                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2281                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2282                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2283                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2284                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2285
2286                         /* Write RX[31:0] and TX[31:16] */
2287                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2288                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2289
2290                         /* Write RX[63:32] and TX[15:0] */
2291                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2292                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2293
2294                         /* Write TX[63:32] and keyType(reserved) */
2295                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2296                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2297                                   AR_KEYTABLE_TYPE_CLR);
2298
2299                 } else {
2300                         /*
2301                          * TKIP uses four key cache entries (two for group
2302                          * keys):
2303                          * Michael MIC TX/RX keys are in different key cache
2304                          * entries (idx = main index + 64 for TX and
2305                          * main index + 32 + 96 for RX):
2306                          * key0 [31:0] = TX/RX MIC key [31:0]
2307                          * key1 [31:0] = reserved
2308                          * key2 [31:0] = TX/RX MIC key [63:32]
2309                          * key3 [31:0] = reserved
2310                          * key4 [31:0] = reserved
2311                          *
2312                          * Upper layer code will call this function separately
2313                          * for TX and RX keys when these registers offsets are
2314                          * used.
2315                          */
2316                         u32 mic0, mic2;
2317
2318                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2319                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2320
2321                         /* Write MIC key[31:0] */
2322                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2323                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2324
2325                         /* Write MIC key[63:32] */
2326                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2327                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2328
2329                         /* Write TX[63:32] and keyType(reserved) */
2330                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2331                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2332                                   AR_KEYTABLE_TYPE_CLR);
2333                 }
2334
2335                 /* MAC address registers are reserved for the MIC entry */
2336                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2337                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2338
2339                 /*
2340                  * Write the correct (un-inverted) key[47:0] last to enable
2341                  * TKIP now that all other registers are set with correct
2342                  * values.
2343                  */
2344                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2345                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2346         } else {
2347                 /* Write key[47:0] */
2348                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2349                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2350
2351                 /* Write key[95:48] */
2352                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2353                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2354
2355                 /* Write key[127:96] and key type */
2356                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2357                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2358
2359                 /* Write MAC address for the entry */
2360                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2361         }
2362
2363         return true;
2364 }
2365 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2366
2367 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2368 {
2369         if (entry < ah->caps.keycache_size) {
2370                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2371                 if (val & AR_KEYTABLE_VALID)
2372                         return true;
2373         }
2374         return false;
2375 }
2376 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2377
2378 /******************************/
2379 /* Power Management (Chipset) */
2380 /******************************/
2381
2382 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2383 {
2384         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2385         if (setChip) {
2386                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2387                             AR_RTC_FORCE_WAKE_EN);
2388                 if (!AR_SREV_9100(ah))
2389                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2390
2391                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2392                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2393                                     AR_RTC_RESET_EN);
2394         }
2395 }
2396
2397 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2398 {
2399         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2400         if (setChip) {
2401                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2402
2403                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2404                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2405                                   AR_RTC_FORCE_WAKE_ON_INT);
2406                 } else {
2407                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2408                                     AR_RTC_FORCE_WAKE_EN);
2409                 }
2410         }
2411 }
2412
2413 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2414 {
2415         u32 val;
2416         int i;
2417
2418         if (setChip) {
2419                 if ((REG_READ(ah, AR_RTC_STATUS) &
2420                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2421                         if (ath9k_hw_set_reset_reg(ah,
2422                                            ATH9K_RESET_POWER_ON) != true) {
2423                                 return false;
2424                         }
2425                         ath9k_hw_init_pll(ah, NULL);
2426                 }
2427                 if (AR_SREV_9100(ah))
2428                         REG_SET_BIT(ah, AR_RTC_RESET,
2429                                     AR_RTC_RESET_EN);
2430
2431                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2432                             AR_RTC_FORCE_WAKE_EN);
2433                 udelay(50);
2434
2435                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2436                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2437                         if (val == AR_RTC_STATUS_ON)
2438                                 break;
2439                         udelay(50);
2440                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2441                                     AR_RTC_FORCE_WAKE_EN);
2442                 }
2443                 if (i == 0) {
2444                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2445                                   "Failed to wakeup in %uus\n",
2446                                   POWER_UP_TIME / 20);
2447                         return false;
2448                 }
2449         }
2450
2451         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2452
2453         return true;
2454 }
2455
2456 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2457 {
2458         struct ath_common *common = ath9k_hw_common(ah);
2459         int status = true, setChip = true;
2460         static const char *modes[] = {
2461                 "AWAKE",
2462                 "FULL-SLEEP",
2463                 "NETWORK SLEEP",
2464                 "UNDEFINED"
2465         };
2466
2467         if (ah->power_mode == mode)
2468                 return status;
2469
2470         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2471                   modes[ah->power_mode], modes[mode]);
2472
2473         switch (mode) {
2474         case ATH9K_PM_AWAKE:
2475                 status = ath9k_hw_set_power_awake(ah, setChip);
2476                 break;
2477         case ATH9K_PM_FULL_SLEEP:
2478                 ath9k_set_power_sleep(ah, setChip);
2479                 ah->chip_fullsleep = true;
2480                 break;
2481         case ATH9K_PM_NETWORK_SLEEP:
2482                 ath9k_set_power_network_sleep(ah, setChip);
2483                 break;
2484         default:
2485                 ath_print(common, ATH_DBG_FATAL,
2486                           "Unknown power mode %u\n", mode);
2487                 return false;
2488         }
2489         ah->power_mode = mode;
2490
2491         return status;
2492 }
2493 EXPORT_SYMBOL(ath9k_hw_setpower);
2494
2495 /*
2496  * Helper for ASPM support.
2497  *
2498  * Disable PLL when in L0s as well as receiver clock when in L1.
2499  * This power saving option must be enabled through the SerDes.
2500  *
2501  * Programming the SerDes must go through the same 288 bit serial shift
2502  * register as the other analog registers.  Hence the 9 writes.
2503  */
2504 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2505 {
2506         u8 i;
2507         u32 val;
2508
2509         if (ah->is_pciexpress != true)
2510                 return;
2511
2512         /* Do not touch SerDes registers */
2513         if (ah->config.pcie_powersave_enable == 2)
2514                 return;
2515
2516         /* Nothing to do on restore for 11N */
2517         if (!restore) {
2518                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2519                         /*
2520                          * AR9280 2.0 or later chips use SerDes values from the
2521                          * initvals.h initialized depending on chipset during
2522                          * ath9k_hw_init()
2523                          */
2524                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2525                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2526                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2527                         }
2528                 } else if (AR_SREV_9280(ah) &&
2529                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2530                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2531                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2532
2533                         /* RX shut off when elecidle is asserted */
2534                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2535                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2536                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2537
2538                         /* Shut off CLKREQ active in L1 */
2539                         if (ah->config.pcie_clock_req)
2540                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2541                         else
2542                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2543
2544                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2545                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2546                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2547
2548                         /* Load the new settings */
2549                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2550
2551                 } else {
2552                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2553                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2554
2555                         /* RX shut off when elecidle is asserted */
2556                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2557                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2558                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2559
2560                         /*
2561                          * Ignore ah->ah_config.pcie_clock_req setting for
2562                          * pre-AR9280 11n
2563                          */
2564                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2565
2566                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2567                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2568                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2569
2570                         /* Load the new settings */
2571                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2572                 }
2573
2574                 udelay(1000);
2575
2576                 /* set bit 19 to allow forcing of pcie core into L1 state */
2577                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2578
2579                 /* Several PCIe massages to ensure proper behaviour */
2580                 if (ah->config.pcie_waen) {
2581                         val = ah->config.pcie_waen;
2582                         if (!power_off)
2583                                 val &= (~AR_WA_D3_L1_DISABLE);
2584                 } else {
2585                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2586                             AR_SREV_9287(ah)) {
2587                                 val = AR9285_WA_DEFAULT;
2588                                 if (!power_off)
2589                                         val &= (~AR_WA_D3_L1_DISABLE);
2590                         } else if (AR_SREV_9280(ah)) {
2591                                 /*
2592                                  * On AR9280 chips bit 22 of 0x4004 needs to be
2593                                  * set otherwise card may disappear.
2594                                  */
2595                                 val = AR9280_WA_DEFAULT;
2596                                 if (!power_off)
2597                                         val &= (~AR_WA_D3_L1_DISABLE);
2598                         } else
2599                                 val = AR_WA_DEFAULT;
2600                 }
2601
2602                 REG_WRITE(ah, AR_WA, val);
2603         }
2604
2605         if (power_off) {
2606                 /*
2607                  * Set PCIe workaround bits
2608                  * bit 14 in WA register (disable L1) should only
2609                  * be set when device enters D3 and be cleared
2610                  * when device comes back to D0.
2611                  */
2612                 if (ah->config.pcie_waen) {
2613                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2614                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2615                 } else {
2616                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2617                               AR_SREV_9287(ah)) &&
2618                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2619                             (AR_SREV_9280(ah) &&
2620                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2621                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2622                         }
2623                 }
2624         }
2625 }
2626 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2627
2628 /**********************/
2629 /* Interrupt Handling */
2630 /**********************/
2631
2632 bool ath9k_hw_intrpend(struct ath_hw *ah)
2633 {
2634         u32 host_isr;
2635
2636         if (AR_SREV_9100(ah))
2637                 return true;
2638
2639         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2640         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2641                 return true;
2642
2643         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2644         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2645             && (host_isr != AR_INTR_SPURIOUS))
2646                 return true;
2647
2648         return false;
2649 }
2650 EXPORT_SYMBOL(ath9k_hw_intrpend);
2651
2652 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2653 {
2654         u32 isr = 0;
2655         u32 mask2 = 0;
2656         struct ath9k_hw_capabilities *pCap = &ah->caps;
2657         u32 sync_cause = 0;
2658         bool fatal_int = false;
2659         struct ath_common *common = ath9k_hw_common(ah);
2660
2661         if (!AR_SREV_9100(ah)) {
2662                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2663                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2664                             == AR_RTC_STATUS_ON) {
2665                                 isr = REG_READ(ah, AR_ISR);
2666                         }
2667                 }
2668
2669                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2670                         AR_INTR_SYNC_DEFAULT;
2671
2672                 *masked = 0;
2673
2674                 if (!isr && !sync_cause)
2675                         return false;
2676         } else {
2677                 *masked = 0;
2678                 isr = REG_READ(ah, AR_ISR);
2679         }
2680
2681         if (isr) {
2682                 if (isr & AR_ISR_BCNMISC) {
2683                         u32 isr2;
2684                         isr2 = REG_READ(ah, AR_ISR_S2);
2685                         if (isr2 & AR_ISR_S2_TIM)
2686                                 mask2 |= ATH9K_INT_TIM;
2687                         if (isr2 & AR_ISR_S2_DTIM)
2688                                 mask2 |= ATH9K_INT_DTIM;
2689                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2690                                 mask2 |= ATH9K_INT_DTIMSYNC;
2691                         if (isr2 & (AR_ISR_S2_CABEND))
2692                                 mask2 |= ATH9K_INT_CABEND;
2693                         if (isr2 & AR_ISR_S2_GTT)
2694                                 mask2 |= ATH9K_INT_GTT;
2695                         if (isr2 & AR_ISR_S2_CST)
2696                                 mask2 |= ATH9K_INT_CST;
2697                         if (isr2 & AR_ISR_S2_TSFOOR)
2698                                 mask2 |= ATH9K_INT_TSFOOR;
2699                 }
2700
2701                 isr = REG_READ(ah, AR_ISR_RAC);
2702                 if (isr == 0xffffffff) {
2703                         *masked = 0;
2704                         return false;
2705                 }
2706
2707                 *masked = isr & ATH9K_INT_COMMON;
2708
2709                 if (ah->config.rx_intr_mitigation) {
2710                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2711                                 *masked |= ATH9K_INT_RX;
2712                 }
2713
2714                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2715                         *masked |= ATH9K_INT_RX;
2716                 if (isr &
2717                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2718                      AR_ISR_TXEOL)) {
2719                         u32 s0_s, s1_s;
2720
2721                         *masked |= ATH9K_INT_TX;
2722
2723                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2724                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2725                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2726
2727                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2728                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2729                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2730                 }
2731
2732                 if (isr & AR_ISR_RXORN) {
2733                         ath_print(common, ATH_DBG_INTERRUPT,
2734                                   "receive FIFO overrun interrupt\n");
2735                 }
2736
2737                 if (!AR_SREV_9100(ah)) {
2738                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2739                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2740                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2741                                         *masked |= ATH9K_INT_TIM_TIMER;
2742                         }
2743                 }
2744
2745                 *masked |= mask2;
2746         }
2747
2748         if (AR_SREV_9100(ah))
2749                 return true;
2750
2751         if (isr & AR_ISR_GENTMR) {
2752                 u32 s5_s;
2753
2754                 s5_s = REG_READ(ah, AR_ISR_S5_S);
2755                 if (isr & AR_ISR_GENTMR) {
2756                         ah->intr_gen_timer_trigger =
2757                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2758
2759                         ah->intr_gen_timer_thresh =
2760                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2761
2762                         if (ah->intr_gen_timer_trigger)
2763                                 *masked |= ATH9K_INT_GENTIMER;
2764
2765                 }
2766         }
2767
2768         if (sync_cause) {
2769                 fatal_int =
2770                         (sync_cause &
2771                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2772                         ? true : false;
2773
2774                 if (fatal_int) {
2775                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2776                                 ath_print(common, ATH_DBG_ANY,
2777                                           "received PCI FATAL interrupt\n");
2778                         }
2779                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2780                                 ath_print(common, ATH_DBG_ANY,
2781                                           "received PCI PERR interrupt\n");
2782                         }
2783                         *masked |= ATH9K_INT_FATAL;
2784                 }
2785                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2786                         ath_print(common, ATH_DBG_INTERRUPT,
2787                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2788                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2789                         REG_WRITE(ah, AR_RC, 0);
2790                         *masked |= ATH9K_INT_FATAL;
2791                 }
2792                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2793                         ath_print(common, ATH_DBG_INTERRUPT,
2794                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2795                 }
2796
2797                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2798                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2799         }
2800
2801         return true;
2802 }
2803 EXPORT_SYMBOL(ath9k_hw_getisr);
2804
2805 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2806 {
2807         enum ath9k_int omask = ah->imask;
2808         u32 mask, mask2;
2809         struct ath9k_hw_capabilities *pCap = &ah->caps;
2810         struct ath_common *common = ath9k_hw_common(ah);
2811
2812         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2813
2814         if (omask & ATH9K_INT_GLOBAL) {
2815                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2816                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2817                 (void) REG_READ(ah, AR_IER);
2818                 if (!AR_SREV_9100(ah)) {
2819                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2820                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2821
2822                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2823                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2824                 }
2825         }
2826
2827         mask = ints & ATH9K_INT_COMMON;
2828         mask2 = 0;
2829
2830         if (ints & ATH9K_INT_TX) {
2831                 if (ah->txok_interrupt_mask)
2832                         mask |= AR_IMR_TXOK;
2833                 if (ah->txdesc_interrupt_mask)
2834                         mask |= AR_IMR_TXDESC;
2835                 if (ah->txerr_interrupt_mask)
2836                         mask |= AR_IMR_TXERR;
2837                 if (ah->txeol_interrupt_mask)
2838                         mask |= AR_IMR_TXEOL;
2839         }
2840         if (ints & ATH9K_INT_RX) {
2841                 mask |= AR_IMR_RXERR;
2842                 if (ah->config.rx_intr_mitigation)
2843                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2844                 else
2845                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2846                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2847                         mask |= AR_IMR_GENTMR;
2848         }
2849
2850         if (ints & (ATH9K_INT_BMISC)) {
2851                 mask |= AR_IMR_BCNMISC;
2852                 if (ints & ATH9K_INT_TIM)
2853                         mask2 |= AR_IMR_S2_TIM;
2854                 if (ints & ATH9K_INT_DTIM)
2855                         mask2 |= AR_IMR_S2_DTIM;
2856                 if (ints & ATH9K_INT_DTIMSYNC)
2857                         mask2 |= AR_IMR_S2_DTIMSYNC;
2858                 if (ints & ATH9K_INT_CABEND)
2859                         mask2 |= AR_IMR_S2_CABEND;
2860                 if (ints & ATH9K_INT_TSFOOR)
2861                         mask2 |= AR_IMR_S2_TSFOOR;
2862         }
2863
2864         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2865                 mask |= AR_IMR_BCNMISC;
2866                 if (ints & ATH9K_INT_GTT)
2867                         mask2 |= AR_IMR_S2_GTT;
2868                 if (ints & ATH9K_INT_CST)
2869                         mask2 |= AR_IMR_S2_CST;
2870         }
2871
2872         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2873         REG_WRITE(ah, AR_IMR, mask);
2874         ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2875                            AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2876                            AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2877         ah->imrs2_reg |= mask2;
2878         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2879
2880         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2881                 if (ints & ATH9K_INT_TIM_TIMER)
2882                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2883                 else
2884                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2885         }
2886
2887         if (ints & ATH9K_INT_GLOBAL) {
2888                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2889                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2890                 if (!AR_SREV_9100(ah)) {
2891                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2892                                   AR_INTR_MAC_IRQ);
2893                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2894
2895
2896                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2897                                   AR_INTR_SYNC_DEFAULT);
2898                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2899                                   AR_INTR_SYNC_DEFAULT);
2900                 }
2901                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2902                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2903         }
2904
2905         return omask;
2906 }
2907 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2908
2909 /*******************/
2910 /* Beacon Handling */
2911 /*******************/
2912
2913 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2914 {
2915         int flags = 0;
2916
2917         ah->beacon_interval = beacon_period;
2918
2919         switch (ah->opmode) {
2920         case NL80211_IFTYPE_STATION:
2921         case NL80211_IFTYPE_MONITOR:
2922                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2923                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2924                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2925                 flags |= AR_TBTT_TIMER_EN;
2926                 break;
2927         case NL80211_IFTYPE_ADHOC:
2928         case NL80211_IFTYPE_MESH_POINT:
2929                 REG_SET_BIT(ah, AR_TXCFG,
2930                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2931                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2932                           TU_TO_USEC(next_beacon +
2933                                      (ah->atim_window ? ah->
2934                                       atim_window : 1)));
2935                 flags |= AR_NDP_TIMER_EN;
2936         case NL80211_IFTYPE_AP:
2937                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2938                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2939                           TU_TO_USEC(next_beacon -
2940                                      ah->config.
2941                                      dma_beacon_response_time));
2942                 REG_WRITE(ah, AR_NEXT_SWBA,
2943                           TU_TO_USEC(next_beacon -
2944                                      ah->config.
2945                                      sw_beacon_response_time));
2946                 flags |=
2947                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2948                 break;
2949         default:
2950                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2951                           "%s: unsupported opmode: %d\n",
2952                           __func__, ah->opmode);
2953                 return;
2954                 break;
2955         }
2956
2957         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2958         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2959         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2960         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2961
2962         beacon_period &= ~ATH9K_BEACON_ENA;
2963         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2964                 ath9k_hw_reset_tsf(ah);
2965         }
2966
2967         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2968 }
2969 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2970
2971 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2972                                     const struct ath9k_beacon_state *bs)
2973 {
2974         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2975         struct ath9k_hw_capabilities *pCap = &ah->caps;
2976         struct ath_common *common = ath9k_hw_common(ah);
2977
2978         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2979
2980         REG_WRITE(ah, AR_BEACON_PERIOD,
2981                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2982         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2983                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2984
2985         REG_RMW_FIELD(ah, AR_RSSI_THR,
2986                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2987
2988         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
2989
2990         if (bs->bs_sleepduration > beaconintval)
2991                 beaconintval = bs->bs_sleepduration;
2992
2993         dtimperiod = bs->bs_dtimperiod;
2994         if (bs->bs_sleepduration > dtimperiod)
2995                 dtimperiod = bs->bs_sleepduration;
2996
2997         if (beaconintval == dtimperiod)
2998                 nextTbtt = bs->bs_nextdtim;
2999         else
3000                 nextTbtt = bs->bs_nexttbtt;
3001
3002         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3003         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3004         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3005         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3006
3007         REG_WRITE(ah, AR_NEXT_DTIM,
3008                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3009         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3010
3011         REG_WRITE(ah, AR_SLEEP1,
3012                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3013                   | AR_SLEEP1_ASSUME_DTIM);
3014
3015         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3016                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3017         else
3018                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3019
3020         REG_WRITE(ah, AR_SLEEP2,
3021                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3022
3023         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3024         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3025
3026         REG_SET_BIT(ah, AR_TIMER_MODE,
3027                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3028                     AR_DTIM_TIMER_EN);
3029
3030         /* TSF Out of Range Threshold */
3031         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3032 }
3033 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3034
3035 /*******************/
3036 /* HW Capabilities */
3037 /*******************/
3038
3039 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3040 {
3041         struct ath9k_hw_capabilities *pCap = &ah->caps;
3042         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3043         struct ath_common *common = ath9k_hw_common(ah);
3044         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3045
3046         u16 capField = 0, eeval;
3047
3048         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3049         regulatory->current_rd = eeval;
3050
3051         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3052         if (AR_SREV_9285_10_OR_LATER(ah))
3053                 eeval |= AR9285_RDEXT_DEFAULT;
3054         regulatory->current_rd_ext = eeval;
3055
3056         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3057
3058         if (ah->opmode != NL80211_IFTYPE_AP &&
3059             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3060                 if (regulatory->current_rd == 0x64 ||
3061                     regulatory->current_rd == 0x65)
3062                         regulatory->current_rd += 5;
3063                 else if (regulatory->current_rd == 0x41)
3064                         regulatory->current_rd = 0x43;
3065                 ath_print(common, ATH_DBG_REGULATORY,
3066                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3067         }
3068
3069         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3070         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3071                 ath_print(common, ATH_DBG_FATAL,
3072                           "no band has been marked as supported in EEPROM.\n");
3073                 return -EINVAL;
3074         }
3075
3076         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3077
3078         if (eeval & AR5416_OPFLAGS_11A) {
3079                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3080                 if (ah->config.ht_enable) {
3081                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3082                                 set_bit(ATH9K_MODE_11NA_HT20,
3083                                         pCap->wireless_modes);
3084                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3085                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3086                                         pCap->wireless_modes);
3087                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3088                                         pCap->wireless_modes);
3089                         }
3090                 }
3091         }
3092
3093         if (eeval & AR5416_OPFLAGS_11G) {
3094                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3095                 if (ah->config.ht_enable) {
3096                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3097                                 set_bit(ATH9K_MODE_11NG_HT20,
3098                                         pCap->wireless_modes);
3099                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3100                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3101                                         pCap->wireless_modes);
3102                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3103                                         pCap->wireless_modes);
3104                         }
3105                 }
3106         }
3107
3108         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3109         /*
3110          * For AR9271 we will temporarilly uses the rx chainmax as read from
3111          * the EEPROM.
3112          */
3113         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3114             !(eeval & AR5416_OPFLAGS_11A) &&
3115             !(AR_SREV_9271(ah)))
3116                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3117                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3118         else
3119                 /* Use rx_chainmask from EEPROM. */
3120                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3121
3122         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3123                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3124
3125         pCap->low_2ghz_chan = 2312;
3126         pCap->high_2ghz_chan = 2732;
3127
3128         pCap->low_5ghz_chan = 4920;
3129         pCap->high_5ghz_chan = 6100;
3130
3131         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3132         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3133         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3134
3135         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3136         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3137         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3138
3139         if (ah->config.ht_enable)
3140                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3141         else
3142                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3143
3144         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3145         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3146         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3147         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3148
3149         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3150                 pCap->total_queues =
3151                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3152         else
3153                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3154
3155         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3156                 pCap->keycache_size =
3157                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3158         else
3159                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3160
3161         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3162
3163         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3164                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3165         else
3166                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3167
3168         if (AR_SREV_9271(ah))
3169                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
3170         else if (AR_SREV_9285_10_OR_LATER(ah))
3171                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3172         else if (AR_SREV_9280_10_OR_LATER(ah))
3173                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3174         else
3175                 pCap->num_gpio_pins = AR_NUM_GPIO;
3176
3177         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3178                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3179                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3180         } else {
3181                 pCap->rts_aggr_limit = (8 * 1024);
3182         }
3183
3184         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3185
3186 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3187         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3188         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3189                 ah->rfkill_gpio =
3190                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3191                 ah->rfkill_polarity =
3192                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3193
3194                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3195         }
3196 #endif
3197         if (AR_SREV_9271(ah))
3198                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3199         else
3200                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3201
3202         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3203                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3204         else
3205                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3206
3207         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3208                 pCap->reg_cap =
3209                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3210                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3211                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3212                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3213         } else {
3214                 pCap->reg_cap =
3215                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3216                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3217         }
3218
3219         /* Advertise midband for AR5416 with FCC midband set in eeprom */
3220         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3221             AR_SREV_5416(ah))
3222                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3223
3224         pCap->num_antcfg_5ghz =
3225                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3226         pCap->num_antcfg_2ghz =
3227                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3228
3229         if (AR_SREV_9280_10_OR_LATER(ah) &&
3230             ath9k_hw_btcoex_supported(ah)) {
3231                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3232                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3233
3234                 if (AR_SREV_9285(ah)) {
3235                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3236                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3237                 } else {
3238                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3239                 }
3240         } else {
3241                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3242         }
3243
3244         return 0;
3245 }
3246
3247 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3248                             u32 capability, u32 *result)
3249 {
3250         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3251         switch (type) {
3252         case ATH9K_CAP_CIPHER:
3253                 switch (capability) {
3254                 case ATH9K_CIPHER_AES_CCM:
3255                 case ATH9K_CIPHER_AES_OCB:
3256                 case ATH9K_CIPHER_TKIP:
3257                 case ATH9K_CIPHER_WEP:
3258                 case ATH9K_CIPHER_MIC:
3259                 case ATH9K_CIPHER_CLR:
3260                         return true;
3261                 default:
3262                         return false;
3263                 }
3264         case ATH9K_CAP_TKIP_MIC:
3265                 switch (capability) {
3266                 case 0:
3267                         return true;
3268                 case 1:
3269                         return (ah->sta_id1_defaults &
3270                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3271                         false;
3272                 }
3273         case ATH9K_CAP_TKIP_SPLIT:
3274                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3275                         false : true;
3276         case ATH9K_CAP_DIVERSITY:
3277                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3278                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3279                         true : false;
3280         case ATH9K_CAP_MCAST_KEYSRCH:
3281                 switch (capability) {
3282                 case 0:
3283                         return true;
3284                 case 1:
3285                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3286                                 return false;
3287                         } else {
3288                                 return (ah->sta_id1_defaults &
3289                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3290                                         false;
3291                         }
3292                 }
3293                 return false;
3294         case ATH9K_CAP_TXPOW:
3295                 switch (capability) {
3296                 case 0:
3297                         return 0;
3298                 case 1:
3299                         *result = regulatory->power_limit;
3300                         return 0;
3301                 case 2:
3302                         *result = regulatory->max_power_level;
3303                         return 0;
3304                 case 3:
3305                         *result = regulatory->tp_scale;
3306                         return 0;
3307                 }
3308                 return false;
3309         case ATH9K_CAP_DS:
3310                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3311                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3312                         ? false : true;
3313         default:
3314                 return false;
3315         }
3316 }
3317 EXPORT_SYMBOL(ath9k_hw_getcapability);
3318
3319 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3320                             u32 capability, u32 setting, int *status)
3321 {
3322         u32 v;
3323
3324         switch (type) {
3325         case ATH9K_CAP_TKIP_MIC:
3326                 if (setting)
3327                         ah->sta_id1_defaults |=
3328                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3329                 else
3330                         ah->sta_id1_defaults &=
3331                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3332                 return true;
3333         case ATH9K_CAP_DIVERSITY:
3334                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3335                 if (setting)
3336                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3337                 else
3338                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3339                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3340                 return true;
3341         case ATH9K_CAP_MCAST_KEYSRCH:
3342                 if (setting)
3343                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3344                 else
3345                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3346                 return true;
3347         default:
3348                 return false;
3349         }
3350 }
3351 EXPORT_SYMBOL(ath9k_hw_setcapability);
3352
3353 /****************************/
3354 /* GPIO / RFKILL / Antennae */
3355 /****************************/
3356
3357 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3358                                          u32 gpio, u32 type)
3359 {
3360         int addr;
3361         u32 gpio_shift, tmp;
3362
3363         if (gpio > 11)
3364                 addr = AR_GPIO_OUTPUT_MUX3;
3365         else if (gpio > 5)
3366                 addr = AR_GPIO_OUTPUT_MUX2;
3367         else
3368                 addr = AR_GPIO_OUTPUT_MUX1;
3369
3370         gpio_shift = (gpio % 6) * 5;
3371
3372         if (AR_SREV_9280_20_OR_LATER(ah)
3373             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3374                 REG_RMW(ah, addr, (type << gpio_shift),
3375                         (0x1f << gpio_shift));
3376         } else {
3377                 tmp = REG_READ(ah, addr);
3378                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3379                 tmp &= ~(0x1f << gpio_shift);
3380                 tmp |= (type << gpio_shift);
3381                 REG_WRITE(ah, addr, tmp);
3382         }
3383 }
3384
3385 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3386 {
3387         u32 gpio_shift;
3388
3389         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3390
3391         gpio_shift = gpio << 1;
3392
3393         REG_RMW(ah,
3394                 AR_GPIO_OE_OUT,
3395                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3396                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3397 }
3398 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3399
3400 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3401 {
3402 #define MS_REG_READ(x, y) \
3403         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3404
3405         if (gpio >= ah->caps.num_gpio_pins)
3406                 return 0xffffffff;
3407
3408         if (AR_SREV_9271(ah))
3409                 return MS_REG_READ(AR9271, gpio) != 0;
3410         else if (AR_SREV_9287_10_OR_LATER(ah))
3411                 return MS_REG_READ(AR9287, gpio) != 0;
3412         else if (AR_SREV_9285_10_OR_LATER(ah))
3413                 return MS_REG_READ(AR9285, gpio) != 0;
3414         else if (AR_SREV_9280_10_OR_LATER(ah))
3415                 return MS_REG_READ(AR928X, gpio) != 0;
3416         else
3417                 return MS_REG_READ(AR, gpio) != 0;
3418 }
3419 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3420
3421 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3422                          u32 ah_signal_type)
3423 {
3424         u32 gpio_shift;
3425
3426         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3427
3428         gpio_shift = 2 * gpio;
3429
3430         REG_RMW(ah,
3431                 AR_GPIO_OE_OUT,
3432                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3433                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3434 }
3435 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3436
3437 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3438 {
3439         if (AR_SREV_9271(ah))
3440                 val = ~val;
3441
3442         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3443                 AR_GPIO_BIT(gpio));
3444 }
3445 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3446
3447 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3448 {
3449         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3450 }
3451 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3452
3453 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3454 {
3455         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3456 }
3457 EXPORT_SYMBOL(ath9k_hw_setantenna);
3458
3459 /*********************/
3460 /* General Operation */
3461 /*********************/
3462
3463 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3464 {
3465         u32 bits = REG_READ(ah, AR_RX_FILTER);
3466         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3467
3468         if (phybits & AR_PHY_ERR_RADAR)
3469                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3470         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3471                 bits |= ATH9K_RX_FILTER_PHYERR;
3472
3473         return bits;
3474 }
3475 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3476
3477 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3478 {
3479         u32 phybits;
3480
3481         REG_WRITE(ah, AR_RX_FILTER, bits);
3482
3483         phybits = 0;
3484         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3485                 phybits |= AR_PHY_ERR_RADAR;
3486         if (bits & ATH9K_RX_FILTER_PHYERR)
3487                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3488         REG_WRITE(ah, AR_PHY_ERR, phybits);
3489
3490         if (phybits)
3491                 REG_WRITE(ah, AR_RXCFG,
3492                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3493         else
3494                 REG_WRITE(ah, AR_RXCFG,
3495                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3496 }
3497 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3498
3499 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3500 {
3501         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3502                 return false;
3503
3504         ath9k_hw_init_pll(ah, NULL);
3505         return true;
3506 }
3507 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3508
3509 bool ath9k_hw_disable(struct ath_hw *ah)
3510 {
3511         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3512                 return false;
3513
3514         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3515                 return false;
3516
3517         ath9k_hw_init_pll(ah, NULL);
3518         return true;
3519 }
3520 EXPORT_SYMBOL(ath9k_hw_disable);
3521
3522 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3523 {
3524         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3525         struct ath9k_channel *chan = ah->curchan;
3526         struct ieee80211_channel *channel = chan->chan;
3527
3528         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3529
3530         ah->eep_ops->set_txpower(ah, chan,
3531                                  ath9k_regd_get_ctl(regulatory, chan),
3532                                  channel->max_antenna_gain * 2,
3533                                  channel->max_power * 2,
3534                                  min((u32) MAX_RATE_POWER,
3535                                  (u32) regulatory->power_limit));
3536 }
3537 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3538
3539 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3540 {
3541         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3542 }
3543 EXPORT_SYMBOL(ath9k_hw_setmac);
3544
3545 void ath9k_hw_setopmode(struct ath_hw *ah)
3546 {
3547         ath9k_hw_set_operating_mode(ah, ah->opmode);
3548 }
3549 EXPORT_SYMBOL(ath9k_hw_setopmode);
3550
3551 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3552 {
3553         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3554         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3555 }
3556 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3557
3558 void ath9k_hw_write_associd(struct ath_hw *ah)
3559 {
3560         struct ath_common *common = ath9k_hw_common(ah);
3561
3562         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3563         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3564                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3565 }
3566 EXPORT_SYMBOL(ath9k_hw_write_associd);
3567
3568 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3569 {
3570         u64 tsf;
3571
3572         tsf = REG_READ(ah, AR_TSF_U32);
3573         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3574
3575         return tsf;
3576 }
3577 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3578
3579 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3580 {
3581         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3582         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3583 }
3584 EXPORT_SYMBOL(ath9k_hw_settsf64);
3585
3586 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3587 {
3588         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3589                            AH_TSF_WRITE_TIMEOUT))
3590                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3591                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3592
3593         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3594 }
3595 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3596
3597 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3598 {
3599         if (setting)
3600                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3601         else
3602                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3603 }
3604 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3605
3606 /*
3607  *  Extend 15-bit time stamp from rx descriptor to
3608  *  a full 64-bit TSF using the current h/w TSF.
3609 */
3610 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3611 {
3612         u64 tsf;
3613
3614         tsf = ath9k_hw_gettsf64(ah);
3615         if ((tsf & 0x7fff) < rstamp)
3616                 tsf -= 0x8000;
3617         return (tsf & ~0x7fff) | rstamp;
3618 }
3619 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3620
3621 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3622 {
3623         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3624         u32 macmode;
3625
3626         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3627                 macmode = AR_2040_JOINED_RX_CLEAR;
3628         else
3629                 macmode = 0;
3630
3631         REG_WRITE(ah, AR_2040_MODE, macmode);
3632 }
3633
3634 /* HW Generic timers configuration */
3635
3636 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3637 {
3638         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3639         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3640         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3641         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3642         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3643         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3644         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3645         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3646         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3647         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3648                                 AR_NDP2_TIMER_MODE, 0x0002},
3649         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3650                                 AR_NDP2_TIMER_MODE, 0x0004},
3651         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3652                                 AR_NDP2_TIMER_MODE, 0x0008},
3653         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3654                                 AR_NDP2_TIMER_MODE, 0x0010},
3655         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3656                                 AR_NDP2_TIMER_MODE, 0x0020},
3657         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3658                                 AR_NDP2_TIMER_MODE, 0x0040},
3659         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3660                                 AR_NDP2_TIMER_MODE, 0x0080}
3661 };
3662
3663 /* HW generic timer primitives */
3664
3665 /* compute and clear index of rightmost 1 */
3666 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3667 {
3668         u32 b;
3669
3670         b = *mask;
3671         b &= (0-b);
3672         *mask &= ~b;
3673         b *= debruijn32;
3674         b >>= 27;
3675
3676         return timer_table->gen_timer_index[b];
3677 }
3678
3679 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3680 {
3681         return REG_READ(ah, AR_TSF_L32);
3682 }
3683 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3684
3685 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3686                                           void (*trigger)(void *),
3687                                           void (*overflow)(void *),
3688                                           void *arg,
3689                                           u8 timer_index)
3690 {
3691         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3692         struct ath_gen_timer *timer;
3693
3694         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3695
3696         if (timer == NULL) {
3697                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3698                           "Failed to allocate memory"
3699                           "for hw timer[%d]\n", timer_index);
3700                 return NULL;
3701         }
3702
3703         /* allocate a hardware generic timer slot */
3704         timer_table->timers[timer_index] = timer;
3705         timer->index = timer_index;
3706         timer->trigger = trigger;
3707         timer->overflow = overflow;
3708         timer->arg = arg;
3709
3710         return timer;
3711 }
3712 EXPORT_SYMBOL(ath_gen_timer_alloc);
3713
3714 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3715                               struct ath_gen_timer *timer,
3716                               u32 timer_next,
3717                               u32 timer_period)
3718 {
3719         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3720         u32 tsf;
3721
3722         BUG_ON(!timer_period);
3723
3724         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3725
3726         tsf = ath9k_hw_gettsf32(ah);
3727
3728         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3729                   "curent tsf %x period %x"
3730                   "timer_next %x\n", tsf, timer_period, timer_next);
3731
3732         /*
3733          * Pull timer_next forward if the current TSF already passed it
3734          * because of software latency
3735          */
3736         if (timer_next < tsf)
3737                 timer_next = tsf + timer_period;
3738
3739         /*
3740          * Program generic timer registers
3741          */
3742         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3743                  timer_next);
3744         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3745                   timer_period);
3746         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3747                     gen_tmr_configuration[timer->index].mode_mask);
3748
3749         /* Enable both trigger and thresh interrupt masks */
3750         REG_SET_BIT(ah, AR_IMR_S5,
3751                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3752                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3753 }
3754 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3755
3756 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3757 {
3758         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3759
3760         if ((timer->index < AR_FIRST_NDP_TIMER) ||
3761                 (timer->index >= ATH_MAX_GEN_TIMER)) {
3762                 return;
3763         }
3764
3765         /* Clear generic timer enable bits. */
3766         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3767                         gen_tmr_configuration[timer->index].mode_mask);
3768
3769         /* Disable both trigger and thresh interrupt masks */
3770         REG_CLR_BIT(ah, AR_IMR_S5,
3771                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3772                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3773
3774         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3775 }
3776 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3777
3778 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3779 {
3780         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3781
3782         /* free the hardware generic timer slot */
3783         timer_table->timers[timer->index] = NULL;
3784         kfree(timer);
3785 }
3786 EXPORT_SYMBOL(ath_gen_timer_free);
3787
3788 /*
3789  * Generic Timer Interrupts handling
3790  */
3791 void ath_gen_timer_isr(struct ath_hw *ah)
3792 {
3793         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3794         struct ath_gen_timer *timer;
3795         struct ath_common *common = ath9k_hw_common(ah);
3796         u32 trigger_mask, thresh_mask, index;
3797
3798         /* get hardware generic timer interrupt status */
3799         trigger_mask = ah->intr_gen_timer_trigger;
3800         thresh_mask = ah->intr_gen_timer_thresh;
3801         trigger_mask &= timer_table->timer_mask.val;
3802         thresh_mask &= timer_table->timer_mask.val;
3803
3804         trigger_mask &= ~thresh_mask;
3805
3806         while (thresh_mask) {
3807                 index = rightmost_index(timer_table, &thresh_mask);
3808                 timer = timer_table->timers[index];
3809                 BUG_ON(!timer);
3810                 ath_print(common, ATH_DBG_HWTIMER,
3811                           "TSF overflow for Gen timer %d\n", index);
3812                 timer->overflow(timer->arg);
3813         }
3814
3815         while (trigger_mask) {
3816                 index = rightmost_index(timer_table, &trigger_mask);
3817                 timer = timer_table->timers[index];
3818                 BUG_ON(!timer);
3819                 ath_print(common, ATH_DBG_HWTIMER,
3820                           "Gen timer[%d] trigger\n", index);
3821                 timer->trigger(timer->arg);
3822         }
3823 }
3824 EXPORT_SYMBOL(ath_gen_timer_isr);
3825
3826 /********/
3827 /* HTC  */
3828 /********/
3829
3830 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3831 {
3832         ah->htc_reset_init = true;
3833 }
3834 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3835
3836 static struct {
3837         u32 version;
3838         const char * name;
3839 } ath_mac_bb_names[] = {
3840         /* Devices with external radios */
3841         { AR_SREV_VERSION_5416_PCI,     "5416" },
3842         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3843         { AR_SREV_VERSION_9100,         "9100" },
3844         { AR_SREV_VERSION_9160,         "9160" },
3845         /* Single-chip solutions */
3846         { AR_SREV_VERSION_9280,         "9280" },
3847         { AR_SREV_VERSION_9285,         "9285" },
3848         { AR_SREV_VERSION_9287,         "9287" },
3849         { AR_SREV_VERSION_9271,         "9271" },
3850 };
3851
3852 /* For devices with external radios */
3853 static struct {
3854         u16 version;
3855         const char * name;
3856 } ath_rf_names[] = {
3857         { 0,                            "5133" },
3858         { AR_RAD5133_SREV_MAJOR,        "5133" },
3859         { AR_RAD5122_SREV_MAJOR,        "5122" },
3860         { AR_RAD2133_SREV_MAJOR,        "2133" },
3861         { AR_RAD2122_SREV_MAJOR,        "2122" }
3862 };
3863
3864 /*
3865  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3866  */
3867 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3868 {
3869         int i;
3870
3871         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3872                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3873                         return ath_mac_bb_names[i].name;
3874                 }
3875         }
3876
3877         return "????";
3878 }
3879
3880 /*
3881  * Return the RF name. "????" is returned if the RF is unknown.
3882  * Used for devices with external radios.
3883  */
3884 static const char *ath9k_hw_rf_name(u16 rf_version)
3885 {
3886         int i;
3887
3888         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3889                 if (ath_rf_names[i].version == rf_version) {
3890                         return ath_rf_names[i].name;
3891                 }
3892         }
3893
3894         return "????";
3895 }
3896
3897 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3898 {
3899         int used;
3900
3901         /* chipsets >= AR9280 are single-chip */
3902         if (AR_SREV_9280_10_OR_LATER(ah)) {
3903                 used = snprintf(hw_name, len,
3904                                "Atheros AR%s Rev:%x",
3905                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3906                                ah->hw_version.macRev);
3907         }
3908         else {
3909                 used = snprintf(hw_name, len,
3910                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3911                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3912                                ah->hw_version.macRev,
3913                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3914                                                 AR_RADIO_SREV_MAJOR)),
3915                                ah->hw_version.phyRev);
3916         }
3917
3918         hw_name[used] = '\0';
3919 }
3920 EXPORT_SYMBOL(ath9k_hw_name);