drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <asm/unaligned.h>
  20
  21 #include "hw.h"
  22 #include "hw-ops.h"
  23 #include "rc.h"
  24 #include "ar9003_mac.h"
  25
  26 #define ATH9K_CLOCK_RATE_CCK            22
  27 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  28 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  29 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32
  33 MODULE_AUTHOR("Atheros Communications");
  34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  36 MODULE_LICENSE("Dual BSD/GPL");
  37
  38 static int __init ath9k_init(void)
  39 {
  40         return 0;
  41 }
  42 module_init(ath9k_init);
  43
  44 static void __exit ath9k_exit(void)
  45 {
  46         return;
  47 }
  48 module_exit(ath9k_exit);
  49
  50 /* Private hardware callbacks */
  51
  52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  53 {
  54         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  55 }
  56
  57 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  58 {
  59         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  60 }
  61
  62 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  63 {
  64         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  65
  66         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  67 }
  68
  69 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  70                                         struct ath9k_channel *chan)
  71 {
  72         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  73 }
  74
  75 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  76 {
  77         if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
  78                 return;
  79
  80         ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
  81 }
  82
  83 /********************/
  84 /* Helper Functions */
  85 /********************/
  86
  87 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  88 {
  89         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  90
  91         if (!ah->curchan) /* should really check for CCK instead */
  92                 return usecs *ATH9K_CLOCK_RATE_CCK;
  93         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  94                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  95
  96         if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
  97                 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
  98         else
  99                 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
 100 }
 101
 102 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
 103 {
 104         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 105
 106         if (conf_is_ht40(conf))
 107                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 108         else
 109                 return ath9k_hw_mac_clks(ah, usecs);
 110 }
 111
 112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 113 {
 114         int i;
 115
 116         BUG_ON(timeout < AH_TIME_QUANTUM);
 117
 118         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 119                 if ((REG_READ(ah, reg) & mask) == val)
 120                         return true;
 121
 122                 udelay(AH_TIME_QUANTUM);
 123         }
 124
 125         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 126                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 127                   timeout, reg, REG_READ(ah, reg), mask, val);
 128
 129         return false;
 130 }
 131 EXPORT_SYMBOL(ath9k_hw_wait);
 132
 133 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 134 {
 135         u32 retval;
 136         int i;
 137
 138         for (i = 0, retval = 0; i < n; i++) {
 139                 retval = (retval << 1) | (val & 1);
 140                 val >>= 1;
 141         }
 142         return retval;
 143 }
 144
 145 bool ath9k_get_channel_edges(struct ath_hw *ah,
 146                              u16 flags, u16 *low,
 147                              u16 *high)
 148 {
 149         struct ath9k_hw_capabilities *pCap = &ah->caps;
 150
 151         if (flags & CHANNEL_5GHZ) {
 152                 *low = pCap->low_5ghz_chan;
 153                 *high = pCap->high_5ghz_chan;
 154                 return true;
 155         }
 156         if ((flags & CHANNEL_2GHZ)) {
 157                 *low = pCap->low_2ghz_chan;
 158                 *high = pCap->high_2ghz_chan;
 159                 return true;
 160         }
 161         return false;
 162 }
 163
 164 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 165                            u8 phy, int kbps,
 166                            u32 frameLen, u16 rateix,
 167                            bool shortPreamble)
 168 {
 169         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 170
 171         if (kbps == 0)
 172                 return 0;
 173
 174         switch (phy) {
 175         case WLAN_RC_PHY_CCK:
 176                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 177                 if (shortPreamble)
 178                         phyTime >>= 1;
 179                 numBits = frameLen << 3;
 180                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 181                 break;
 182         case WLAN_RC_PHY_OFDM:
 183                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 184                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 185                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 186                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 187                         txTime = OFDM_SIFS_TIME_QUARTER
 188                                 + OFDM_PREAMBLE_TIME_QUARTER
 189                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 190                 } else if (ah->curchan &&
 191                            IS_CHAN_HALF_RATE(ah->curchan)) {
 192                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 193                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 194                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 195                         txTime = OFDM_SIFS_TIME_HALF +
 196                                 OFDM_PREAMBLE_TIME_HALF
 197                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 198                 } else {
 199                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 200                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 201                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 202                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 203                                 + (numSymbols * OFDM_SYMBOL_TIME);
 204                 }
 205                 break;
 206         default:
 207                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 208                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 209                 txTime = 0;
 210                 break;
 211         }
 212
 213         return txTime;
 214 }
 215 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 216
 217 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 218                                   struct ath9k_channel *chan,
 219                                   struct chan_centers *centers)
 220 {
 221         int8_t extoff;
 222
 223         if (!IS_CHAN_HT40(chan)) {
 224                 centers->ctl_center = centers->ext_center =
 225                         centers->synth_center = chan->channel;
 226                 return;
 227         }
 228
 229         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 230             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 231                 centers->synth_center =
 232                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 233                 extoff = 1;
 234         } else {
 235                 centers->synth_center =
 236                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 237                 extoff = -1;
 238         }
 239
 240         centers->ctl_center =
 241                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 242         /* 25 MHz spacing is supported by hw but not on upper layers */
 243         centers->ext_center =
 244                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 245 }
 246
 247 /******************/
 248 /* Chip Revisions */
 249 /******************/
 250
 251 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 252 {
 253         u32 val;
 254
 255         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 256
 257         if (val == 0xFF) {
 258                 val = REG_READ(ah, AR_SREV);
 259                 ah->hw_version.macVersion =
 260                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 261                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 262                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 263         } else {
 264                 if (!AR_SREV_9100(ah))
 265                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 266
 267                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 268
 269                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 270                         ah->is_pciexpress = true;
 271         }
 272 }
 273
 274 /************************************/
 275 /* HW Attach, Detach, Init Routines */
 276 /************************************/
 277
 278 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 279 {
 280         if (AR_SREV_9100(ah))
 281                 return;
 282
 283         ENABLE_REGWRITE_BUFFER(ah);
 284
 285         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 286         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 287         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 288         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 289         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 290         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 291         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 292         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 293         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 294
 295         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 296
 297         REGWRITE_BUFFER_FLUSH(ah);
 298         DISABLE_REGWRITE_BUFFER(ah);
 299 }
 300
 301 /* This should work for all families including legacy */
 302 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 303 {
 304         struct ath_common *common = ath9k_hw_common(ah);
 305         u32 regAddr[2] = { AR_STA_ID0 };
 306         u32 regHold[2];
 307         u32 patternData[4] = { 0x55555555,
 308                                0xaaaaaaaa,
 309                                0x66666666,
 310                                0x99999999 };
 311         int i, j, loop_max;
 312
 313         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 314                 loop_max = 2;
 315                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 316         } else
 317                 loop_max = 1;
 318
 319         for (i = 0; i < loop_max; i++) {
 320                 u32 addr = regAddr[i];
 321                 u32 wrData, rdData;
 322
 323                 regHold[i] = REG_READ(ah, addr);
 324                 for (j = 0; j < 0x100; j++) {
 325                         wrData = (j << 16) | j;
 326                         REG_WRITE(ah, addr, wrData);
 327                         rdData = REG_READ(ah, addr);
 328                         if (rdData != wrData) {
 329                                 ath_print(common, ATH_DBG_FATAL,
 330                                           "address test failed "
 331                                           "addr: 0x%08x - wr:0x%08x != "
 332                                           "rd:0x%08x\n",
 333                                           addr, wrData, rdData);
 334                                 return false;
 335                         }
 336                 }
 337                 for (j = 0; j < 4; j++) {
 338                         wrData = patternData[j];
 339                         REG_WRITE(ah, addr, wrData);
 340                         rdData = REG_READ(ah, addr);
 341                         if (wrData != rdData) {
 342                                 ath_print(common, ATH_DBG_FATAL,
 343                                           "address test failed "
 344                                           "addr: 0x%08x - wr:0x%08x != "
 345                                           "rd:0x%08x\n",
 346                                           addr, wrData, rdData);
 347                                 return false;
 348                         }
 349                 }
 350                 REG_WRITE(ah, regAddr[i], regHold[i]);
 351         }
 352         udelay(100);
 353
 354         return true;
 355 }
 356
 357 static void ath9k_hw_init_config(struct ath_hw *ah)
 358 {
 359         int i;
 360
 361         ah->config.dma_beacon_response_time = 2;
 362         ah->config.sw_beacon_response_time = 10;
 363         ah->config.additional_swba_backoff = 0;
 364         ah->config.ack_6mb = 0x0;
 365         ah->config.cwm_ignore_extcca = 0;
 366         ah->config.pcie_powersave_enable = 0;
 367         ah->config.pcie_clock_req = 0;
 368         ah->config.pcie_waen = 0;
 369         ah->config.analog_shiftreg = 1;
 370         ah->config.ofdm_trig_low = 200;
 371         ah->config.ofdm_trig_high = 500;
 372         ah->config.cck_trig_high = 200;
 373         ah->config.cck_trig_low = 100;
 374
 375         /*
 376          * For now ANI is disabled for AR9003, it is still
 377          * being tested.
 378          */
 379         if (!AR_SREV_9300_20_OR_LATER(ah))
 380                 ah->config.enable_ani = 1;
 381
 382         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 383                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 384                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 385         }
 386
 387         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 388                 ah->config.ht_enable = 1;
 389         else
 390                 ah->config.ht_enable = 0;
 391
 392         ah->config.rx_intr_mitigation = true;
 393
 394         /*
 395          * Tx IQ Calibration (ah->config.tx_iq_calibration) is only
 396          * used by AR9003, but it is showing reliability issues.
 397          * It will take a while to fix so this is currently disabled.
 398          */
 399
 400         /*
 401          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 402          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 403          * This means we use it for all AR5416 devices, and the few
 404          * minor PCI AR9280 devices out there.
 405          *
 406          * Serialization is required because these devices do not handle
 407          * well the case of two concurrent reads/writes due to the latency
 408          * involved. During one read/write another read/write can be issued
 409          * on another CPU while the previous read/write may still be working
 410          * on our hardware, if we hit this case the hardware poops in a loop.
 411          * We prevent this by serializing reads and writes.
 412          *
 413          * This issue is not present on PCI-Express devices or pre-AR5416
 414          * devices (legacy, 802.11abg).
 415          */
 416         if (num_possible_cpus() > 1)
 417                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 418 }
 419
 420 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 421 {
 422         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 423
 424         regulatory->country_code = CTRY_DEFAULT;
 425         regulatory->power_limit = MAX_RATE_POWER;
 426         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 427
 428         ah->hw_version.magic = AR5416_MAGIC;
 429         ah->hw_version.subvendorid = 0;
 430
 431         ah->ah_flags = 0;
 432         if (!AR_SREV_9100(ah))
 433                 ah->ah_flags = AH_USE_EEPROM;
 434
 435         ah->atim_window = 0;
 436         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 437         ah->beacon_interval = 100;
 438         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 439         ah->slottime = (u32) -1;
 440         ah->globaltxtimeout = (u32) -1;
 441         ah->power_mode = ATH9K_PM_UNDEFINED;
 442 }
 443
 444 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 445 {
 446         struct ath_common *common = ath9k_hw_common(ah);
 447         u32 sum;
 448         int i;
 449         u16 eeval;
 450         u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 451
 452         sum = 0;
 453         for (i = 0; i < 3; i++) {
 454                 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
 455                 sum += eeval;
 456                 common->macaddr[2 * i] = eeval >> 8;
 457                 common->macaddr[2 * i + 1] = eeval & 0xff;
 458         }
 459         if (sum == 0 || sum == 0xffff * 3)
 460                 return -EADDRNOTAVAIL;
 461
 462         return 0;
 463 }
 464
 465 static int ath9k_hw_post_init(struct ath_hw *ah)
 466 {
 467         int ecode;
 468
 469         if (!AR_SREV_9271(ah)) {
 470                 if (!ath9k_hw_chip_test(ah))
 471                         return -ENODEV;
 472         }
 473
 474         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 475                 ecode = ar9002_hw_rf_claim(ah);
 476                 if (ecode != 0)
 477                         return ecode;
 478         }
 479
 480         ecode = ath9k_hw_eeprom_init(ah);
 481         if (ecode != 0)
 482                 return ecode;
 483
 484         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 485                   "Eeprom VER: %d, REV: %d\n",
 486                   ah->eep_ops->get_eeprom_ver(ah),
 487                   ah->eep_ops->get_eeprom_rev(ah));
 488
 489         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 490         if (ecode) {
 491                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 492                           "Failed allocating banks for "
 493                           "external radio\n");
 494                 return ecode;
 495         }
 496
 497         if (!AR_SREV_9100(ah)) {
 498                 ath9k_hw_ani_setup(ah);
 499                 ath9k_hw_ani_init(ah);
 500         }
 501
 502         return 0;
 503 }
 504
 505 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 506 {
 507         if (AR_SREV_9300_20_OR_LATER(ah))
 508                 ar9003_hw_attach_ops(ah);
 509         else
 510                 ar9002_hw_attach_ops(ah);
 511 }
 512
 513 /* Called for all hardware families */
 514 static int __ath9k_hw_init(struct ath_hw *ah)
 515 {
 516         struct ath_common *common = ath9k_hw_common(ah);
 517         int r = 0;
 518
 519         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 520                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 521
 522         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 523                 ath_print(common, ATH_DBG_FATAL,
 524                           "Couldn't reset chip\n");
 525                 return -EIO;
 526         }
 527
 528         ath9k_hw_init_defaults(ah);
 529         ath9k_hw_init_config(ah);
 530
 531         ath9k_hw_attach_ops(ah);
 532
 533         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 534                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 535                 return -EIO;
 536         }
 537
 538         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 539                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 540                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 541                         ah->config.serialize_regmode =
 542                                 SER_REG_MODE_ON;
 543                 } else {
 544                         ah->config.serialize_regmode =
 545                                 SER_REG_MODE_OFF;
 546                 }
 547         }
 548
 549         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 550                 ah->config.serialize_regmode);
 551
 552         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 553                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 554         else
 555                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 556
 557         if (!ath9k_hw_macversion_supported(ah)) {
 558                 ath_print(common, ATH_DBG_FATAL,
 559                           "Mac Chip Rev 0x%02x.%x is not supported by "
 560                           "this driver\n", ah->hw_version.macVersion,
 561                           ah->hw_version.macRev);
 562                 return -EOPNOTSUPP;
 563         }
 564
 565         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
 566                 ah->is_pciexpress = false;
 567
 568         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 569         ath9k_hw_init_cal_settings(ah);
 570
 571         ah->ani_function = ATH9K_ANI_ALL;
 572         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
 573                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 574
 575         ath9k_hw_init_mode_regs(ah);
 576
 577         if (ah->is_pciexpress)
 578                 ath9k_hw_configpcipowersave(ah, 0, 0);
 579         else
 580                 ath9k_hw_disablepcie(ah);
 581
 582         if (!AR_SREV_9300_20_OR_LATER(ah))
 583                 ar9002_hw_cck_chan14_spread(ah);
 584
 585         r = ath9k_hw_post_init(ah);
 586         if (r)
 587                 return r;
 588
 589         ath9k_hw_init_mode_gain_regs(ah);
 590         r = ath9k_hw_fill_cap_info(ah);
 591         if (r)
 592                 return r;
 593
 594         r = ath9k_hw_init_macaddr(ah);
 595         if (r) {
 596                 ath_print(common, ATH_DBG_FATAL,
 597                           "Failed to initialize MAC address\n");
 598                 return r;
 599         }
 600
 601         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 602                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 603         else
 604                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 605
 606         if (AR_SREV_9300_20_OR_LATER(ah))
 607                 ar9003_hw_set_nf_limits(ah);
 608
 609         ath9k_init_nfcal_hist_buffer(ah);
 610
 611         common->state = ATH_HW_INITIALIZED;
 612
 613         return 0;
 614 }
 615
 616 int ath9k_hw_init(struct ath_hw *ah)
 617 {
 618         int ret;
 619         struct ath_common *common = ath9k_hw_common(ah);
 620
 621         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
 622         switch (ah->hw_version.devid) {
 623         case AR5416_DEVID_PCI:
 624         case AR5416_DEVID_PCIE:
 625         case AR5416_AR9100_DEVID:
 626         case AR9160_DEVID_PCI:
 627         case AR9280_DEVID_PCI:
 628         case AR9280_DEVID_PCIE:
 629         case AR9285_DEVID_PCIE:
 630         case AR9287_DEVID_PCI:
 631         case AR9287_DEVID_PCIE:
 632         case AR2427_DEVID_PCIE:
 633         case AR9300_DEVID_PCIE:
 634                 break;
 635         default:
 636                 if (common->bus_ops->ath_bus_type == ATH_USB)
 637                         break;
 638                 ath_print(common, ATH_DBG_FATAL,
 639                           "Hardware device ID 0x%04x not supported\n",
 640                           ah->hw_version.devid);
 641                 return -EOPNOTSUPP;
 642         }
 643
 644         ret = __ath9k_hw_init(ah);
 645         if (ret) {
 646                 ath_print(common, ATH_DBG_FATAL,
 647                           "Unable to initialize hardware; "
 648                           "initialization status: %d\n", ret);
 649                 return ret;
 650         }
 651
 652         return 0;
 653 }
 654 EXPORT_SYMBOL(ath9k_hw_init);
 655
 656 static void ath9k_hw_init_qos(struct ath_hw *ah)
 657 {
 658         ENABLE_REGWRITE_BUFFER(ah);
 659
 660         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 661         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 662
 663         REG_WRITE(ah, AR_QOS_NO_ACK,
 664                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 665                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 666                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 667
 668         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 669         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 670         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 671         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 672         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 673
 674         REGWRITE_BUFFER_FLUSH(ah);
 675         DISABLE_REGWRITE_BUFFER(ah);
 676 }
 677
 678 static void ath9k_hw_init_pll(struct ath_hw *ah,
 679                               struct ath9k_channel *chan)
 680 {
 681         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
 682
 683         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 684
 685         /* Switch the core clock for ar9271 to 117Mhz */
 686         if (AR_SREV_9271(ah)) {
 687                 udelay(500);
 688                 REG_WRITE(ah, 0x50040, 0x304);
 689         }
 690
 691         udelay(RTC_PLL_SETTLE_DELAY);
 692
 693         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 694 }
 695
 696 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 697                                           enum nl80211_iftype opmode)
 698 {
 699         u32 imr_reg = AR_IMR_TXERR |
 700                 AR_IMR_TXURN |
 701                 AR_IMR_RXERR |
 702                 AR_IMR_RXORN |
 703                 AR_IMR_BCNMISC;
 704
 705         if (AR_SREV_9300_20_OR_LATER(ah)) {
 706                 imr_reg |= AR_IMR_RXOK_HP;
 707                 if (ah->config.rx_intr_mitigation)
 708                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 709                 else
 710                         imr_reg |= AR_IMR_RXOK_LP;
 711
 712         } else {
 713                 if (ah->config.rx_intr_mitigation)
 714                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 715                 else
 716                         imr_reg |= AR_IMR_RXOK;
 717         }
 718
 719         if (ah->config.tx_intr_mitigation)
 720                 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
 721         else
 722                 imr_reg |= AR_IMR_TXOK;
 723
 724         if (opmode == NL80211_IFTYPE_AP)
 725                 imr_reg |= AR_IMR_MIB;
 726
 727         ENABLE_REGWRITE_BUFFER(ah);
 728
 729         REG_WRITE(ah, AR_IMR, imr_reg);
 730         ah->imrs2_reg |= AR_IMR_S2_GTT;
 731         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 732
 733         if (!AR_SREV_9100(ah)) {
 734                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 735                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 736                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 737         }
 738
 739         REGWRITE_BUFFER_FLUSH(ah);
 740         DISABLE_REGWRITE_BUFFER(ah);
 741
 742         if (AR_SREV_9300_20_OR_LATER(ah)) {
 743                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
 744                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
 745                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
 746                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
 747         }
 748 }
 749
 750 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
 751 {
 752         u32 val = ath9k_hw_mac_to_clks(ah, us);
 753         val = min(val, (u32) 0xFFFF);
 754         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
 755 }
 756
 757 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
 758 {
 759         u32 val = ath9k_hw_mac_to_clks(ah, us);
 760         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
 761         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
 762 }
 763
 764 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 765 {
 766         u32 val = ath9k_hw_mac_to_clks(ah, us);
 767         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
 768         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
 769 }
 770
 771 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 772 {
 773         if (tu > 0xFFFF) {
 774                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
 775                           "bad global tx timeout %u\n", tu);
 776                 ah->globaltxtimeout = (u32) -1;
 777                 return false;
 778         } else {
 779                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
 780                 ah->globaltxtimeout = tu;
 781                 return true;
 782         }
 783 }
 784
 785 void ath9k_hw_init_global_settings(struct ath_hw *ah)
 786 {
 787         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 788         int acktimeout;
 789         int slottime;
 790         int sifstime;
 791
 792         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
 793                   ah->misc_mode);
 794
 795         if (ah->misc_mode != 0)
 796                 REG_WRITE(ah, AR_PCU_MISC,
 797                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
 798
 799         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
 800                 sifstime = 16;
 801         else
 802                 sifstime = 10;
 803
 804         /* As defined by IEEE 802.11-2007 17.3.8.6 */
 805         slottime = ah->slottime + 3 * ah->coverage_class;
 806         acktimeout = slottime + sifstime;
 807
 808         /*
 809          * Workaround for early ACK timeouts, add an offset to match the
 810          * initval's 64us ack timeout value.
 811          * This was initially only meant to work around an issue with delayed
 812          * BA frames in some implementations, but it has been found to fix ACK
 813          * timeout issues in other cases as well.
 814          */
 815         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
 816                 acktimeout += 64 - sifstime - ah->slottime;
 817
 818         ath9k_hw_setslottime(ah, slottime);
 819         ath9k_hw_set_ack_timeout(ah, acktimeout);
 820         ath9k_hw_set_cts_timeout(ah, acktimeout);
 821         if (ah->globaltxtimeout != (u32) -1)
 822                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
 823 }
 824 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
 825
 826 void ath9k_hw_deinit(struct ath_hw *ah)
 827 {
 828         struct ath_common *common = ath9k_hw_common(ah);
 829
 830         if (common->state < ATH_HW_INITIALIZED)
 831                 goto free_hw;
 832
 833         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
 834
 835 free_hw:
 836         ath9k_hw_rf_free_ext_banks(ah);
 837 }
 838 EXPORT_SYMBOL(ath9k_hw_deinit);
 839
 840 /*******/
 841 /* INI */
 842 /*******/
 843
 844 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 845 {
 846         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
 847
 848         if (IS_CHAN_B(chan))
 849                 ctl |= CTL_11B;
 850         else if (IS_CHAN_G(chan))
 851                 ctl |= CTL_11G;
 852         else
 853                 ctl |= CTL_11A;
 854
 855         return ctl;
 856 }
 857
 858 /****************************************/
 859 /* Reset and Channel Switching Routines */
 860 /****************************************/
 861
 862 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 863 {
 864         struct ath_common *common = ath9k_hw_common(ah);
 865         u32 regval;
 866
 867         ENABLE_REGWRITE_BUFFER(ah);
 868
 869         /*
 870          * set AHB_MODE not to do cacheline prefetches
 871         */
 872         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 873                 regval = REG_READ(ah, AR_AHB_MODE);
 874                 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
 875         }
 876
 877         /*
 878          * let mac dma reads be in 128 byte chunks
 879          */
 880         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
 881         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 882
 883         REGWRITE_BUFFER_FLUSH(ah);
 884         DISABLE_REGWRITE_BUFFER(ah);
 885
 886         /*
 887          * Restore TX Trigger Level to its pre-reset value.
 888          * The initial value depends on whether aggregation is enabled, and is
 889          * adjusted whenever underruns are detected.
 890          */
 891         if (!AR_SREV_9300_20_OR_LATER(ah))
 892                 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
 893
 894         ENABLE_REGWRITE_BUFFER(ah);
 895
 896         /*
 897          * let mac dma writes be in 128 byte chunks
 898          */
 899         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
 900         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
 901
 902         /*
 903          * Setup receive FIFO threshold to hold off TX activities
 904          */
 905         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
 906
 907         if (AR_SREV_9300_20_OR_LATER(ah)) {
 908                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
 909                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
 910
 911                 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 912                         ah->caps.rx_status_len);
 913         }
 914
 915         /*
 916          * reduce the number of usable entries in PCU TXBUF to avoid
 917          * wrap around issues.
 918          */
 919         if (AR_SREV_9285(ah)) {
 920                 /* For AR9285 the number of Fifos are reduced to half.
 921                  * So set the usable tx buf size also to half to
 922                  * avoid data/delimiter underruns
 923                  */
 924                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 925                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
 926         } else if (!AR_SREV_9271(ah)) {
 927                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 928                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
 929         }
 930
 931         REGWRITE_BUFFER_FLUSH(ah);
 932         DISABLE_REGWRITE_BUFFER(ah);
 933
 934         if (AR_SREV_9300_20_OR_LATER(ah))
 935                 ath9k_hw_reset_txstatus_ring(ah);
 936 }
 937
 938 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 939 {
 940         u32 val;
 941
 942         val = REG_READ(ah, AR_STA_ID1);
 943         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
 944         switch (opmode) {
 945         case NL80211_IFTYPE_AP:
 946                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 947                           | AR_STA_ID1_KSRCH_MODE);
 948                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 949                 break;
 950         case NL80211_IFTYPE_ADHOC:
 951         case NL80211_IFTYPE_MESH_POINT:
 952                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 953                           | AR_STA_ID1_KSRCH_MODE);
 954                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 955                 break;
 956         case NL80211_IFTYPE_STATION:
 957         case NL80211_IFTYPE_MONITOR:
 958                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 959                 break;
 960         }
 961 }
 962
 963 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 964                                    u32 *coef_mantissa, u32 *coef_exponent)
 965 {
 966         u32 coef_exp, coef_man;
 967
 968         for (coef_exp = 31; coef_exp > 0; coef_exp--)
 969                 if ((coef_scaled >> coef_exp) & 0x1)
 970                         break;
 971
 972         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
 973
 974         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
 975
 976         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
 977         *coef_exponent = coef_exp - 16;
 978 }
 979
 980 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
 981 {
 982         u32 rst_flags;
 983         u32 tmpReg;
 984
 985         if (AR_SREV_9100(ah)) {
 986                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
 987                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
 988                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
 989                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
 990                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
 991         }
 992
 993         ENABLE_REGWRITE_BUFFER(ah);
 994
 995         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
 996                   AR_RTC_FORCE_WAKE_ON_INT);
 997
 998         if (AR_SREV_9100(ah)) {
 999                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1000                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1001         } else {
1002                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1003                 if (tmpReg &
1004                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1005                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1006                         u32 val;
1007                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1008
1009                         val = AR_RC_HOSTIF;
1010                         if (!AR_SREV_9300_20_OR_LATER(ah))
1011                                 val |= AR_RC_AHB;
1012                         REG_WRITE(ah, AR_RC, val);
1013
1014                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1015                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1016
1017                 rst_flags = AR_RTC_RC_MAC_WARM;
1018                 if (type == ATH9K_RESET_COLD)
1019                         rst_flags |= AR_RTC_RC_MAC_COLD;
1020         }
1021
1022         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1023
1024         REGWRITE_BUFFER_FLUSH(ah);
1025         DISABLE_REGWRITE_BUFFER(ah);
1026
1027         udelay(50);
1028
1029         REG_WRITE(ah, AR_RTC_RC, 0);
1030         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1031                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1032                           "RTC stuck in MAC reset\n");
1033                 return false;
1034         }
1035
1036         if (!AR_SREV_9100(ah))
1037                 REG_WRITE(ah, AR_RC, 0);
1038
1039         if (AR_SREV_9100(ah))
1040                 udelay(50);
1041
1042         return true;
1043 }
1044
1045 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1046 {
1047         ENABLE_REGWRITE_BUFFER(ah);
1048
1049         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1050                   AR_RTC_FORCE_WAKE_ON_INT);
1051
1052         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1053                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1054
1055         REG_WRITE(ah, AR_RTC_RESET, 0);
1056
1057         REGWRITE_BUFFER_FLUSH(ah);
1058         DISABLE_REGWRITE_BUFFER(ah);
1059
1060         if (!AR_SREV_9300_20_OR_LATER(ah))
1061                 udelay(2);
1062
1063         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1064                 REG_WRITE(ah, AR_RC, 0);
1065
1066         REG_WRITE(ah, AR_RTC_RESET, 1);
1067
1068         if (!ath9k_hw_wait(ah,
1069                            AR_RTC_STATUS,
1070                            AR_RTC_STATUS_M,
1071                            AR_RTC_STATUS_ON,
1072                            AH_WAIT_TIMEOUT)) {
1073                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1074                           "RTC not waking up\n");
1075                 return false;
1076         }
1077
1078         ath9k_hw_read_revisions(ah);
1079
1080         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1081 }
1082
1083 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1084 {
1085         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1086                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1087
1088         switch (type) {
1089         case ATH9K_RESET_POWER_ON:
1090                 return ath9k_hw_set_reset_power_on(ah);
1091         case ATH9K_RESET_WARM:
1092         case ATH9K_RESET_COLD:
1093                 return ath9k_hw_set_reset(ah, type);
1094         default:
1095                 return false;
1096         }
1097 }
1098
1099 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1100                                 struct ath9k_channel *chan)
1101 {
1102         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1103                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1104                         return false;
1105         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1106                 return false;
1107
1108         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1109                 return false;
1110
1111         ah->chip_fullsleep = false;
1112         ath9k_hw_init_pll(ah, chan);
1113         ath9k_hw_set_rfmode(ah, chan);
1114
1115         return true;
1116 }
1117
1118 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1119                                     struct ath9k_channel *chan)
1120 {
1121         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1122         struct ath_common *common = ath9k_hw_common(ah);
1123         struct ieee80211_channel *channel = chan->chan;
1124         u32 qnum;
1125         int r;
1126
1127         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1128                 if (ath9k_hw_numtxpending(ah, qnum)) {
1129                         ath_print(common, ATH_DBG_QUEUE,
1130                                   "Transmit frames pending on "
1131                                   "queue %d\n", qnum);
1132                         return false;
1133                 }
1134         }
1135
1136         if (!ath9k_hw_rfbus_req(ah)) {
1137                 ath_print(common, ATH_DBG_FATAL,
1138                           "Could not kill baseband RX\n");
1139                 return false;
1140         }
1141
1142         ath9k_hw_set_channel_regs(ah, chan);
1143
1144         r = ath9k_hw_rf_set_freq(ah, chan);
1145         if (r) {
1146                 ath_print(common, ATH_DBG_FATAL,
1147                           "Failed to set channel\n");
1148                 return false;
1149         }
1150
1151         ah->eep_ops->set_txpower(ah, chan,
1152                              ath9k_regd_get_ctl(regulatory, chan),
1153                              channel->max_antenna_gain * 2,
1154                              channel->max_power * 2,
1155                              min((u32) MAX_RATE_POWER,
1156                              (u32) regulatory->power_limit));
1157
1158         ath9k_hw_rfbus_done(ah);
1159
1160         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1161                 ath9k_hw_set_delta_slope(ah, chan);
1162
1163         ath9k_hw_spur_mitigate_freq(ah, chan);
1164
1165         if (!chan->oneTimeCalsDone)
1166                 chan->oneTimeCalsDone = true;
1167
1168         return true;
1169 }
1170
1171 bool ath9k_hw_check_alive(struct ath_hw *ah)
1172 {
1173         int count = 50;
1174         u32 reg;
1175
1176         if (AR_SREV_9285_10_OR_LATER(ah))
1177                 return true;
1178
1179         do {
1180                 reg = REG_READ(ah, AR_OBS_BUS_1);
1181
1182                 if ((reg & 0x7E7FFFEF) == 0x00702400)
1183                         continue;
1184
1185                 switch (reg & 0x7E000B00) {
1186                 case 0x1E000000:
1187                 case 0x52000B00:
1188                 case 0x18000B00:
1189                         continue;
1190                 default:
1191                         return true;
1192                 }
1193         } while (count-- > 0);
1194
1195         return false;
1196 }
1197 EXPORT_SYMBOL(ath9k_hw_check_alive);
1198
1199 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1200                     bool bChannelChange)
1201 {
1202         struct ath_common *common = ath9k_hw_common(ah);
1203         u32 saveLedState;
1204         struct ath9k_channel *curchan = ah->curchan;
1205         u32 saveDefAntenna;
1206         u32 macStaId1;
1207         u64 tsf = 0;
1208         int i, r;
1209
1210         ah->txchainmask = common->tx_chainmask;
1211         ah->rxchainmask = common->rx_chainmask;
1212
1213         if (!ah->chip_fullsleep) {
1214                 ath9k_hw_abortpcurecv(ah);
1215                 if (!ath9k_hw_stopdmarecv(ah))
1216                         ath_print(common, ATH_DBG_XMIT,
1217                                 "Failed to stop receive dma\n");
1218         }
1219
1220         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1221                 return -EIO;
1222
1223         if (curchan && !ah->chip_fullsleep)
1224                 ath9k_hw_getnf(ah, curchan);
1225
1226         if (bChannelChange &&
1227             (ah->chip_fullsleep != true) &&
1228             (ah->curchan != NULL) &&
1229             (chan->channel != ah->curchan->channel) &&
1230             ((chan->channelFlags & CHANNEL_ALL) ==
1231              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1232             !AR_SREV_9280(ah)) {
1233
1234                 if (ath9k_hw_channel_change(ah, chan)) {
1235                         ath9k_hw_loadnf(ah, ah->curchan);
1236                         ath9k_hw_start_nfcal(ah);
1237                         return 0;
1238                 }
1239         }
1240
1241         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1242         if (saveDefAntenna == 0)
1243                 saveDefAntenna = 1;
1244
1245         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1246
1247         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1248         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1249                 tsf = ath9k_hw_gettsf64(ah);
1250
1251         saveLedState = REG_READ(ah, AR_CFG_LED) &
1252                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1253                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1254
1255         ath9k_hw_mark_phy_inactive(ah);
1256
1257         /* Only required on the first reset */
1258         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1259                 REG_WRITE(ah,
1260                           AR9271_RESET_POWER_DOWN_CONTROL,
1261                           AR9271_RADIO_RF_RST);
1262                 udelay(50);
1263         }
1264
1265         if (!ath9k_hw_chip_reset(ah, chan)) {
1266                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1267                 return -EINVAL;
1268         }
1269
1270         /* Only required on the first reset */
1271         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1272                 ah->htc_reset_init = false;
1273                 REG_WRITE(ah,
1274                           AR9271_RESET_POWER_DOWN_CONTROL,
1275                           AR9271_GATE_MAC_CTL);
1276                 udelay(50);
1277         }
1278
1279         /* Restore TSF */
1280         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1281                 ath9k_hw_settsf64(ah, tsf);
1282
1283         if (AR_SREV_9280_10_OR_LATER(ah))
1284                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1285
1286         r = ath9k_hw_process_ini(ah, chan);
1287         if (r)
1288                 return r;
1289
1290         /* Setup MFP options for CCMP */
1291         if (AR_SREV_9280_20_OR_LATER(ah)) {
1292                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1293                  * frames when constructing CCMP AAD. */
1294                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1295                               0xc7ff);
1296                 ah->sw_mgmt_crypto = false;
1297         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1298                 /* Disable hardware crypto for management frames */
1299                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1300                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1301                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1302                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1303                 ah->sw_mgmt_crypto = true;
1304         } else
1305                 ah->sw_mgmt_crypto = true;
1306
1307         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1308                 ath9k_hw_set_delta_slope(ah, chan);
1309
1310         ath9k_hw_spur_mitigate_freq(ah, chan);
1311         ah->eep_ops->set_board_values(ah, chan);
1312
1313         ath9k_hw_set_operating_mode(ah, ah->opmode);
1314
1315         ENABLE_REGWRITE_BUFFER(ah);
1316
1317         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1318         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1319                   | macStaId1
1320                   | AR_STA_ID1_RTS_USE_DEF
1321                   | (ah->config.
1322                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1323                   | ah->sta_id1_defaults);
1324         ath_hw_setbssidmask(common);
1325         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1326         ath9k_hw_write_associd(ah);
1327         REG_WRITE(ah, AR_ISR, ~0);
1328         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1329
1330         REGWRITE_BUFFER_FLUSH(ah);
1331         DISABLE_REGWRITE_BUFFER(ah);
1332
1333         r = ath9k_hw_rf_set_freq(ah, chan);
1334         if (r)
1335                 return r;
1336
1337         ENABLE_REGWRITE_BUFFER(ah);
1338
1339         for (i = 0; i < AR_NUM_DCU; i++)
1340                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1341
1342         REGWRITE_BUFFER_FLUSH(ah);
1343         DISABLE_REGWRITE_BUFFER(ah);
1344
1345         ah->intr_txqs = 0;
1346         for (i = 0; i < ah->caps.total_queues; i++)
1347                 ath9k_hw_resettxqueue(ah, i);
1348
1349         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1350         ath9k_hw_init_qos(ah);
1351
1352         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1353                 ath9k_enable_rfkill(ah);
1354
1355         ath9k_hw_init_global_settings(ah);
1356
1357         if (!AR_SREV_9300_20_OR_LATER(ah)) {
1358                 ar9002_hw_enable_async_fifo(ah);
1359                 ar9002_hw_enable_wep_aggregation(ah);
1360         }
1361
1362         REG_WRITE(ah, AR_STA_ID1,
1363                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1364
1365         ath9k_hw_set_dma(ah);
1366
1367         REG_WRITE(ah, AR_OBS, 8);
1368
1369         if (ah->config.rx_intr_mitigation) {
1370                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1371                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1372         }
1373
1374         if (ah->config.tx_intr_mitigation) {
1375                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1376                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1377         }
1378
1379         ath9k_hw_init_bb(ah, chan);
1380
1381         if (!ath9k_hw_init_cal(ah, chan))
1382                 return -EIO;
1383
1384         ENABLE_REGWRITE_BUFFER(ah);
1385
1386         ath9k_hw_restore_chainmask(ah);
1387         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1388
1389         REGWRITE_BUFFER_FLUSH(ah);
1390         DISABLE_REGWRITE_BUFFER(ah);
1391
1392         /*
1393          * For big endian systems turn on swapping for descriptors
1394          */
1395         if (AR_SREV_9100(ah)) {
1396                 u32 mask;
1397                 mask = REG_READ(ah, AR_CFG);
1398                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1399                         ath_print(common, ATH_DBG_RESET,
1400                                 "CFG Byte Swap Set 0x%x\n", mask);
1401                 } else {
1402                         mask =
1403                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1404                         REG_WRITE(ah, AR_CFG, mask);
1405                         ath_print(common, ATH_DBG_RESET,
1406                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1407                 }
1408         } else {
1409                 /* Configure AR9271 target WLAN */
1410                 if (AR_SREV_9271(ah))
1411                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1412 #ifdef __BIG_ENDIAN
1413                 else
1414                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1415 #endif
1416         }
1417
1418         if (ah->btcoex_hw.enabled)
1419                 ath9k_hw_btcoex_enable(ah);
1420
1421         if (AR_SREV_9300_20_OR_LATER(ah)) {
1422                 ath9k_hw_loadnf(ah, curchan);
1423                 ath9k_hw_start_nfcal(ah);
1424         }
1425
1426         return 0;
1427 }
1428 EXPORT_SYMBOL(ath9k_hw_reset);
1429
1430 /************************/
1431 /* Key Cache Management */
1432 /************************/
1433
1434 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1435 {
1436         u32 keyType;
1437
1438         if (entry >= ah->caps.keycache_size) {
1439                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1440                           "keychache entry %u out of range\n", entry);
1441                 return false;
1442         }
1443
1444         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1445
1446         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1447         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1448         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1449         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1450         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1451         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1452         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1453         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1454
1455         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1456                 u16 micentry = entry + 64;
1457
1458                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1459                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1460                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1461                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1462
1463         }
1464
1465         return true;
1466 }
1467 EXPORT_SYMBOL(ath9k_hw_keyreset);
1468
1469 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1470 {
1471         u32 macHi, macLo;
1472
1473         if (entry >= ah->caps.keycache_size) {
1474                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1475                           "keychache entry %u out of range\n", entry);
1476                 return false;
1477         }
1478
1479         if (mac != NULL) {
1480                 macHi = (mac[5] << 8) | mac[4];
1481                 macLo = (mac[3] << 24) |
1482                         (mac[2] << 16) |
1483                         (mac[1] << 8) |
1484                         mac[0];
1485                 macLo >>= 1;
1486                 macLo |= (macHi & 1) << 31;
1487                 macHi >>= 1;
1488         } else {
1489                 macLo = macHi = 0;
1490         }
1491         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1492         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1493
1494         return true;
1495 }
1496 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1497
1498 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1499                                  const struct ath9k_keyval *k,
1500                                  const u8 *mac)
1501 {
1502         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1503         struct ath_common *common = ath9k_hw_common(ah);
1504         u32 key0, key1, key2, key3, key4;
1505         u32 keyType;
1506
1507         if (entry >= pCap->keycache_size) {
1508                 ath_print(common, ATH_DBG_FATAL,
1509                           "keycache entry %u out of range\n", entry);
1510                 return false;
1511         }
1512
1513         switch (k->kv_type) {
1514         case ATH9K_CIPHER_AES_OCB:
1515                 keyType = AR_KEYTABLE_TYPE_AES;
1516                 break;
1517         case ATH9K_CIPHER_AES_CCM:
1518                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1519                         ath_print(common, ATH_DBG_ANY,
1520                                   "AES-CCM not supported by mac rev 0x%x\n",
1521                                   ah->hw_version.macRev);
1522                         return false;
1523                 }
1524                 keyType = AR_KEYTABLE_TYPE_CCM;
1525                 break;
1526         case ATH9K_CIPHER_TKIP:
1527                 keyType = AR_KEYTABLE_TYPE_TKIP;
1528                 if (ATH9K_IS_MIC_ENABLED(ah)
1529                     && entry + 64 >= pCap->keycache_size) {
1530                         ath_print(common, ATH_DBG_ANY,
1531                                   "entry %u inappropriate for TKIP\n", entry);
1532                         return false;
1533                 }
1534                 break;
1535         case ATH9K_CIPHER_WEP:
1536                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1537                         ath_print(common, ATH_DBG_ANY,
1538                                   "WEP key length %u too small\n", k->kv_len);
1539                         return false;
1540                 }
1541                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1542                         keyType = AR_KEYTABLE_TYPE_40;
1543                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1544                         keyType = AR_KEYTABLE_TYPE_104;
1545                 else
1546                         keyType = AR_KEYTABLE_TYPE_128;
1547                 break;
1548         case ATH9K_CIPHER_CLR:
1549                 keyType = AR_KEYTABLE_TYPE_CLR;
1550                 break;
1551         default:
1552                 ath_print(common, ATH_DBG_FATAL,
1553                           "cipher %u not supported\n", k->kv_type);
1554                 return false;
1555         }
1556
1557         key0 = get_unaligned_le32(k->kv_val + 0);
1558         key1 = get_unaligned_le16(k->kv_val + 4);
1559         key2 = get_unaligned_le32(k->kv_val + 6);
1560         key3 = get_unaligned_le16(k->kv_val + 10);
1561         key4 = get_unaligned_le32(k->kv_val + 12);
1562         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1563                 key4 &= 0xff;
1564
1565         /*
1566          * Note: Key cache registers access special memory area that requires
1567          * two 32-bit writes to actually update the values in the internal
1568          * memory. Consequently, the exact order and pairs used here must be
1569          * maintained.
1570          */
1571
1572         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1573                 u16 micentry = entry + 64;
1574
1575                 /*
1576                  * Write inverted key[47:0] first to avoid Michael MIC errors
1577                  * on frames that could be sent or received at the same time.
1578                  * The correct key will be written in the end once everything
1579                  * else is ready.
1580                  */
1581                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1582                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1583
1584                 /* Write key[95:48] */
1585                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1586                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1587
1588                 /* Write key[127:96] and key type */
1589                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1590                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1591
1592                 /* Write MAC address for the entry */
1593                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1594
1595                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1596                         /*
1597                          * TKIP uses two key cache entries:
1598                          * Michael MIC TX/RX keys in the same key cache entry
1599                          * (idx = main index + 64):
1600                          * key0 [31:0] = RX key [31:0]
1601                          * key1 [15:0] = TX key [31:16]
1602                          * key1 [31:16] = reserved
1603                          * key2 [31:0] = RX key [63:32]
1604                          * key3 [15:0] = TX key [15:0]
1605                          * key3 [31:16] = reserved
1606                          * key4 [31:0] = TX key [63:32]
1607                          */
1608                         u32 mic0, mic1, mic2, mic3, mic4;
1609
1610                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1611                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1612                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1613                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1614                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1615
1616                         /* Write RX[31:0] and TX[31:16] */
1617                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1618                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1619
1620                         /* Write RX[63:32] and TX[15:0] */
1621                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1622                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1623
1624                         /* Write TX[63:32] and keyType(reserved) */
1625                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1626                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1627                                   AR_KEYTABLE_TYPE_CLR);
1628
1629                 } else {
1630                         /*
1631                          * TKIP uses four key cache entries (two for group
1632                          * keys):
1633                          * Michael MIC TX/RX keys are in different key cache
1634                          * entries (idx = main index + 64 for TX and
1635                          * main index + 32 + 96 for RX):
1636                          * key0 [31:0] = TX/RX MIC key [31:0]
1637                          * key1 [31:0] = reserved
1638                          * key2 [31:0] = TX/RX MIC key [63:32]
1639                          * key3 [31:0] = reserved
1640                          * key4 [31:0] = reserved
1641                          *
1642                          * Upper layer code will call this function separately
1643                          * for TX and RX keys when these registers offsets are
1644                          * used.
1645                          */
1646                         u32 mic0, mic2;
1647
1648                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1649                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1650
1651                         /* Write MIC key[31:0] */
1652                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1653                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1654
1655                         /* Write MIC key[63:32] */
1656                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1657                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1658
1659                         /* Write TX[63:32] and keyType(reserved) */
1660                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1661                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1662                                   AR_KEYTABLE_TYPE_CLR);
1663                 }
1664
1665                 /* MAC address registers are reserved for the MIC entry */
1666                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1667                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1668
1669                 /*
1670                  * Write the correct (un-inverted) key[47:0] last to enable
1671                  * TKIP now that all other registers are set with correct
1672                  * values.
1673                  */
1674                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1675                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1676         } else {
1677                 /* Write key[47:0] */
1678                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1679                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1680
1681                 /* Write key[95:48] */
1682                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1683                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1684
1685                 /* Write key[127:96] and key type */
1686                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1687                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1688
1689                 /* Write MAC address for the entry */
1690                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1691         }
1692
1693         return true;
1694 }
1695 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1696
1697 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1698 {
1699         if (entry < ah->caps.keycache_size) {
1700                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1701                 if (val & AR_KEYTABLE_VALID)
1702                         return true;
1703         }
1704         return false;
1705 }
1706 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1707
1708 /******************************/
1709 /* Power Management (Chipset) */
1710 /******************************/
1711
1712 /*
1713  * Notify Power Mgt is disabled in self-generated frames.
1714  * If requested, force chip to sleep.
1715  */
1716 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1717 {
1718         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1719         if (setChip) {
1720                 /*
1721                  * Clear the RTC force wake bit to allow the
1722                  * mac to go to sleep.
1723                  */
1724                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1725                             AR_RTC_FORCE_WAKE_EN);
1726                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1727                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1728
1729                 /* Shutdown chip. Active low */
1730                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1731                         REG_CLR_BIT(ah, (AR_RTC_RESET),
1732                                     AR_RTC_RESET_EN);
1733         }
1734 }
1735
1736 /*
1737  * Notify Power Management is enabled in self-generating
1738  * frames. If request, set power mode of chip to
1739  * auto/normal.  Duration in units of 128us (1/8 TU).
1740  */
1741 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1742 {
1743         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1744         if (setChip) {
1745                 struct ath9k_hw_capabilities *pCap = &ah->caps;
1746
1747                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1748                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
1749                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1750                                   AR_RTC_FORCE_WAKE_ON_INT);
1751                 } else {
1752                         /*
1753                          * Clear the RTC force wake bit to allow the
1754                          * mac to go to sleep.
1755                          */
1756                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1757                                     AR_RTC_FORCE_WAKE_EN);
1758                 }
1759         }
1760 }
1761
1762 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1763 {
1764         u32 val;
1765         int i;
1766
1767         if (setChip) {
1768                 if ((REG_READ(ah, AR_RTC_STATUS) &
1769                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1770                         if (ath9k_hw_set_reset_reg(ah,
1771                                            ATH9K_RESET_POWER_ON) != true) {
1772                                 return false;
1773                         }
1774                         if (!AR_SREV_9300_20_OR_LATER(ah))
1775                                 ath9k_hw_init_pll(ah, NULL);
1776                 }
1777                 if (AR_SREV_9100(ah))
1778                         REG_SET_BIT(ah, AR_RTC_RESET,
1779                                     AR_RTC_RESET_EN);
1780
1781                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1782                             AR_RTC_FORCE_WAKE_EN);
1783                 udelay(50);
1784
1785                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1786                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1787                         if (val == AR_RTC_STATUS_ON)
1788                                 break;
1789                         udelay(50);
1790                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1791                                     AR_RTC_FORCE_WAKE_EN);
1792                 }
1793                 if (i == 0) {
1794                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1795                                   "Failed to wakeup in %uus\n",
1796                                   POWER_UP_TIME / 20);
1797                         return false;
1798                 }
1799         }
1800
1801         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1802
1803         return true;
1804 }
1805
1806 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1807 {
1808         struct ath_common *common = ath9k_hw_common(ah);
1809         int status = true, setChip = true;
1810         static const char *modes[] = {
1811                 "AWAKE",
1812                 "FULL-SLEEP",
1813                 "NETWORK SLEEP",
1814                 "UNDEFINED"
1815         };
1816
1817         if (ah->power_mode == mode)
1818                 return status;
1819
1820         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1821                   modes[ah->power_mode], modes[mode]);
1822
1823         switch (mode) {
1824         case ATH9K_PM_AWAKE:
1825                 status = ath9k_hw_set_power_awake(ah, setChip);
1826                 break;
1827         case ATH9K_PM_FULL_SLEEP:
1828                 ath9k_set_power_sleep(ah, setChip);
1829                 ah->chip_fullsleep = true;
1830                 break;
1831         case ATH9K_PM_NETWORK_SLEEP:
1832                 ath9k_set_power_network_sleep(ah, setChip);
1833                 break;
1834         default:
1835                 ath_print(common, ATH_DBG_FATAL,
1836                           "Unknown power mode %u\n", mode);
1837                 return false;
1838         }
1839         ah->power_mode = mode;
1840
1841         return status;
1842 }
1843 EXPORT_SYMBOL(ath9k_hw_setpower);
1844
1845 /*******************/
1846 /* Beacon Handling */
1847 /*******************/
1848
1849 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1850 {
1851         int flags = 0;
1852
1853         ah->beacon_interval = beacon_period;
1854
1855         ENABLE_REGWRITE_BUFFER(ah);
1856
1857         switch (ah->opmode) {
1858         case NL80211_IFTYPE_STATION:
1859         case NL80211_IFTYPE_MONITOR:
1860                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1861                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1862                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1863                 flags |= AR_TBTT_TIMER_EN;
1864                 break;
1865         case NL80211_IFTYPE_ADHOC:
1866         case NL80211_IFTYPE_MESH_POINT:
1867                 REG_SET_BIT(ah, AR_TXCFG,
1868                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1869                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1870                           TU_TO_USEC(next_beacon +
1871                                      (ah->atim_window ? ah->
1872                                       atim_window : 1)));
1873                 flags |= AR_NDP_TIMER_EN;
1874         case NL80211_IFTYPE_AP:
1875                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1876                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1877                           TU_TO_USEC(next_beacon -
1878                                      ah->config.
1879                                      dma_beacon_response_time));
1880                 REG_WRITE(ah, AR_NEXT_SWBA,
1881                           TU_TO_USEC(next_beacon -
1882                                      ah->config.
1883                                      sw_beacon_response_time));
1884                 flags |=
1885                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1886                 break;
1887         default:
1888                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1889                           "%s: unsupported opmode: %d\n",
1890                           __func__, ah->opmode);
1891                 return;
1892                 break;
1893         }
1894
1895         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1896         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1897         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1898         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1899
1900         REGWRITE_BUFFER_FLUSH(ah);
1901         DISABLE_REGWRITE_BUFFER(ah);
1902
1903         beacon_period &= ~ATH9K_BEACON_ENA;
1904         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1905                 ath9k_hw_reset_tsf(ah);
1906         }
1907
1908         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1909 }
1910 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1911
1912 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1913                                     const struct ath9k_beacon_state *bs)
1914 {
1915         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1916         struct ath9k_hw_capabilities *pCap = &ah->caps;
1917         struct ath_common *common = ath9k_hw_common(ah);
1918
1919         ENABLE_REGWRITE_BUFFER(ah);
1920
1921         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1922
1923         REG_WRITE(ah, AR_BEACON_PERIOD,
1924                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1925         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1926                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1927
1928         REGWRITE_BUFFER_FLUSH(ah);
1929         DISABLE_REGWRITE_BUFFER(ah);
1930
1931         REG_RMW_FIELD(ah, AR_RSSI_THR,
1932                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1933
1934         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1935
1936         if (bs->bs_sleepduration > beaconintval)
1937                 beaconintval = bs->bs_sleepduration;
1938
1939         dtimperiod = bs->bs_dtimperiod;
1940         if (bs->bs_sleepduration > dtimperiod)
1941                 dtimperiod = bs->bs_sleepduration;
1942
1943         if (beaconintval == dtimperiod)
1944                 nextTbtt = bs->bs_nextdtim;
1945         else
1946                 nextTbtt = bs->bs_nexttbtt;
1947
1948         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1949         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1950         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1951         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1952
1953         ENABLE_REGWRITE_BUFFER(ah);
1954
1955         REG_WRITE(ah, AR_NEXT_DTIM,
1956                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1957         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1958
1959         REG_WRITE(ah, AR_SLEEP1,
1960                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1961                   | AR_SLEEP1_ASSUME_DTIM);
1962
1963         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1964                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1965         else
1966                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1967
1968         REG_WRITE(ah, AR_SLEEP2,
1969                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1970
1971         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1972         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1973
1974         REGWRITE_BUFFER_FLUSH(ah);
1975         DISABLE_REGWRITE_BUFFER(ah);
1976
1977         REG_SET_BIT(ah, AR_TIMER_MODE,
1978                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1979                     AR_DTIM_TIMER_EN);
1980
1981         /* TSF Out of Range Threshold */
1982         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1983 }
1984 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1985
1986 /*******************/
1987 /* HW Capabilities */
1988 /*******************/
1989
1990 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1991 {
1992         struct ath9k_hw_capabilities *pCap = &ah->caps;
1993         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1994         struct ath_common *common = ath9k_hw_common(ah);
1995         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1996
1997         u16 capField = 0, eeval;
1998
1999         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2000         regulatory->current_rd = eeval;
2001
2002         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2003         if (AR_SREV_9285_10_OR_LATER(ah))
2004                 eeval |= AR9285_RDEXT_DEFAULT;
2005         regulatory->current_rd_ext = eeval;
2006
2007         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2008
2009         if (ah->opmode != NL80211_IFTYPE_AP &&
2010             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2011                 if (regulatory->current_rd == 0x64 ||
2012                     regulatory->current_rd == 0x65)
2013                         regulatory->current_rd += 5;
2014                 else if (regulatory->current_rd == 0x41)
2015                         regulatory->current_rd = 0x43;
2016                 ath_print(common, ATH_DBG_REGULATORY,
2017                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
2018         }
2019
2020         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2021         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2022                 ath_print(common, ATH_DBG_FATAL,
2023                           "no band has been marked as supported in EEPROM.\n");
2024                 return -EINVAL;
2025         }
2026
2027         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2028
2029         if (eeval & AR5416_OPFLAGS_11A) {
2030                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2031                 if (ah->config.ht_enable) {
2032                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2033                                 set_bit(ATH9K_MODE_11NA_HT20,
2034                                         pCap->wireless_modes);
2035                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2036                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2037                                         pCap->wireless_modes);
2038                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2039                                         pCap->wireless_modes);
2040                         }
2041                 }
2042         }
2043
2044         if (eeval & AR5416_OPFLAGS_11G) {
2045                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2046                 if (ah->config.ht_enable) {
2047                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2048                                 set_bit(ATH9K_MODE_11NG_HT20,
2049                                         pCap->wireless_modes);
2050                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2051                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2052                                         pCap->wireless_modes);
2053                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2054                                         pCap->wireless_modes);
2055                         }
2056                 }
2057         }
2058
2059         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2060         /*
2061          * For AR9271 we will temporarilly uses the rx chainmax as read from
2062          * the EEPROM.
2063          */
2064         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2065             !(eeval & AR5416_OPFLAGS_11A) &&
2066             !(AR_SREV_9271(ah)))
2067                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2068                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2069         else
2070                 /* Use rx_chainmask from EEPROM. */
2071                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2072
2073         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2074                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2075
2076         pCap->low_2ghz_chan = 2312;
2077         pCap->high_2ghz_chan = 2732;
2078
2079         pCap->low_5ghz_chan = 4920;
2080         pCap->high_5ghz_chan = 6100;
2081
2082         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2083         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2084         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2085
2086         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2087         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2088         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2089
2090         if (ah->config.ht_enable)
2091                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2092         else
2093                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2094
2095         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2096         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2097         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2098         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2099
2100         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2101                 pCap->total_queues =
2102                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2103         else
2104                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2105
2106         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2107                 pCap->keycache_size =
2108                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2109         else
2110                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2111
2112         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2113
2114         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2115                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2116         else
2117                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2118
2119         if (AR_SREV_9271(ah))
2120                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2121         else if (AR_SREV_9285_10_OR_LATER(ah))
2122                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2123         else if (AR_SREV_9280_10_OR_LATER(ah))
2124                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2125         else
2126                 pCap->num_gpio_pins = AR_NUM_GPIO;
2127
2128         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2129                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2130                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2131         } else {
2132                 pCap->rts_aggr_limit = (8 * 1024);
2133         }
2134
2135         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2136
2137 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2138         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2139         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2140                 ah->rfkill_gpio =
2141                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2142                 ah->rfkill_polarity =
2143                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2144
2145                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2146         }
2147 #endif
2148         if (AR_SREV_9271(ah))
2149                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2150         else
2151                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2152
2153         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2154                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2155         else
2156                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2157
2158         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2159                 pCap->reg_cap =
2160                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2161                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2162                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2163                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2164         } else {
2165                 pCap->reg_cap =
2166                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2167                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2168         }
2169
2170         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2171         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2172             AR_SREV_5416(ah))
2173                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2174
2175         pCap->num_antcfg_5ghz =
2176                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2177         pCap->num_antcfg_2ghz =
2178                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2179
2180         if (AR_SREV_9280_10_OR_LATER(ah) &&
2181             ath9k_hw_btcoex_supported(ah)) {
2182                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2183                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2184
2185                 if (AR_SREV_9285(ah)) {
2186                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2187                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2188                 } else {
2189                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2190                 }
2191         } else {
2192                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2193         }
2194
2195         if (AR_SREV_9300_20_OR_LATER(ah)) {
2196                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2197                                  ATH9K_HW_CAP_FASTCLOCK;
2198                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2199                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2200                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2201                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2202                 pCap->txs_len = sizeof(struct ar9003_txs);
2203         } else {
2204                 pCap->tx_desc_len = sizeof(struct ath_desc);
2205                 if (AR_SREV_9280_20(ah) &&
2206                     ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2207                       AR5416_EEP_MINOR_VER_16) ||
2208                      ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2209                         pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2210         }
2211
2212         if (AR_SREV_9300_20_OR_LATER(ah))
2213                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2214
2215         return 0;
2216 }
2217
2218 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2219                             u32 capability, u32 *result)
2220 {
2221         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2222         switch (type) {
2223         case ATH9K_CAP_CIPHER:
2224                 switch (capability) {
2225                 case ATH9K_CIPHER_AES_CCM:
2226                 case ATH9K_CIPHER_AES_OCB:
2227                 case ATH9K_CIPHER_TKIP:
2228                 case ATH9K_CIPHER_WEP:
2229                 case ATH9K_CIPHER_MIC:
2230                 case ATH9K_CIPHER_CLR:
2231                         return true;
2232                 default:
2233                         return false;
2234                 }
2235         case ATH9K_CAP_TKIP_MIC:
2236                 switch (capability) {
2237                 case 0:
2238                         return true;
2239                 case 1:
2240                         return (ah->sta_id1_defaults &
2241                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2242                         false;
2243                 }
2244         case ATH9K_CAP_TKIP_SPLIT:
2245                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2246                         false : true;
2247         case ATH9K_CAP_MCAST_KEYSRCH:
2248                 switch (capability) {
2249                 case 0:
2250                         return true;
2251                 case 1:
2252                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2253                                 return false;
2254                         } else {
2255                                 return (ah->sta_id1_defaults &
2256                                         AR_STA_ID1_MCAST_KSRCH) ? true :
2257                                         false;
2258                         }
2259                 }
2260                 return false;
2261         case ATH9K_CAP_TXPOW:
2262                 switch (capability) {
2263                 case 0:
2264                         return 0;
2265                 case 1:
2266                         *result = regulatory->power_limit;
2267                         return 0;
2268                 case 2:
2269                         *result = regulatory->max_power_level;
2270                         return 0;
2271                 case 3:
2272                         *result = regulatory->tp_scale;
2273                         return 0;
2274                 }
2275                 return false;
2276         case ATH9K_CAP_DS:
2277                 return (AR_SREV_9280_20_OR_LATER(ah) &&
2278                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2279                         ? false : true;
2280         default:
2281                 return false;
2282         }
2283 }
2284 EXPORT_SYMBOL(ath9k_hw_getcapability);
2285
2286 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2287                             u32 capability, u32 setting, int *status)
2288 {
2289         switch (type) {
2290         case ATH9K_CAP_TKIP_MIC:
2291                 if (setting)
2292                         ah->sta_id1_defaults |=
2293                                 AR_STA_ID1_CRPT_MIC_ENABLE;
2294                 else
2295                         ah->sta_id1_defaults &=
2296                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2297                 return true;
2298         case ATH9K_CAP_MCAST_KEYSRCH:
2299                 if (setting)
2300                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2301                 else
2302                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2303                 return true;
2304         default:
2305                 return false;
2306         }
2307 }
2308 EXPORT_SYMBOL(ath9k_hw_setcapability);
2309
2310 /****************************/
2311 /* GPIO / RFKILL / Antennae */
2312 /****************************/
2313
2314 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2315                                          u32 gpio, u32 type)
2316 {
2317         int addr;
2318         u32 gpio_shift, tmp;
2319
2320         if (gpio > 11)
2321                 addr = AR_GPIO_OUTPUT_MUX3;
2322         else if (gpio > 5)
2323                 addr = AR_GPIO_OUTPUT_MUX2;
2324         else
2325                 addr = AR_GPIO_OUTPUT_MUX1;
2326
2327         gpio_shift = (gpio % 6) * 5;
2328
2329         if (AR_SREV_9280_20_OR_LATER(ah)
2330             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2331                 REG_RMW(ah, addr, (type << gpio_shift),
2332                         (0x1f << gpio_shift));
2333         } else {
2334                 tmp = REG_READ(ah, addr);
2335                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2336                 tmp &= ~(0x1f << gpio_shift);
2337                 tmp |= (type << gpio_shift);
2338                 REG_WRITE(ah, addr, tmp);
2339         }
2340 }
2341
2342 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2343 {
2344         u32 gpio_shift;
2345
2346         BUG_ON(gpio >= ah->caps.num_gpio_pins);
2347
2348         gpio_shift = gpio << 1;
2349
2350         REG_RMW(ah,
2351                 AR_GPIO_OE_OUT,
2352                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2353                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2354 }
2355 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2356
2357 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2358 {
2359 #define MS_REG_READ(x, y) \
2360         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2361
2362         if (gpio >= ah->caps.num_gpio_pins)
2363                 return 0xffffffff;
2364
2365         if (AR_SREV_9300_20_OR_LATER(ah))
2366                 return MS_REG_READ(AR9300, gpio) != 0;
2367         else if (AR_SREV_9271(ah))
2368                 return MS_REG_READ(AR9271, gpio) != 0;
2369         else if (AR_SREV_9287_10_OR_LATER(ah))
2370                 return MS_REG_READ(AR9287, gpio) != 0;
2371         else if (AR_SREV_9285_10_OR_LATER(ah))
2372                 return MS_REG_READ(AR9285, gpio) != 0;
2373         else if (AR_SREV_9280_10_OR_LATER(ah))
2374                 return MS_REG_READ(AR928X, gpio) != 0;
2375         else
2376                 return MS_REG_READ(AR, gpio) != 0;
2377 }
2378 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2379
2380 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2381                          u32 ah_signal_type)
2382 {
2383         u32 gpio_shift;
2384
2385         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2386
2387         gpio_shift = 2 * gpio;
2388
2389         REG_RMW(ah,
2390                 AR_GPIO_OE_OUT,
2391                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2392                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2393 }
2394 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2395
2396 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2397 {
2398         if (AR_SREV_9271(ah))
2399                 val = ~val;
2400
2401         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2402                 AR_GPIO_BIT(gpio));
2403 }
2404 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2405
2406 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2407 {
2408         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2409 }
2410 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2411
2412 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2413 {
2414         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2415 }
2416 EXPORT_SYMBOL(ath9k_hw_setantenna);
2417
2418 /*********************/
2419 /* General Operation */
2420 /*********************/
2421
2422 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2423 {
2424         u32 bits = REG_READ(ah, AR_RX_FILTER);
2425         u32 phybits = REG_READ(ah, AR_PHY_ERR);
2426
2427         if (phybits & AR_PHY_ERR_RADAR)
2428                 bits |= ATH9K_RX_FILTER_PHYRADAR;
2429         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2430                 bits |= ATH9K_RX_FILTER_PHYERR;
2431
2432         return bits;
2433 }
2434 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2435
2436 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2437 {
2438         u32 phybits;
2439
2440         ENABLE_REGWRITE_BUFFER(ah);
2441
2442         REG_WRITE(ah, AR_RX_FILTER, bits);
2443
2444         phybits = 0;
2445         if (bits & ATH9K_RX_FILTER_PHYRADAR)
2446                 phybits |= AR_PHY_ERR_RADAR;
2447         if (bits & ATH9K_RX_FILTER_PHYERR)
2448                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2449         REG_WRITE(ah, AR_PHY_ERR, phybits);
2450
2451         if (phybits)
2452                 REG_WRITE(ah, AR_RXCFG,
2453                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2454         else
2455                 REG_WRITE(ah, AR_RXCFG,
2456                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2457
2458         REGWRITE_BUFFER_FLUSH(ah);
2459         DISABLE_REGWRITE_BUFFER(ah);
2460 }
2461 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2462
2463 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2464 {
2465         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2466                 return false;
2467
2468         ath9k_hw_init_pll(ah, NULL);
2469         return true;
2470 }
2471 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2472
2473 bool ath9k_hw_disable(struct ath_hw *ah)
2474 {
2475         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2476                 return false;
2477
2478         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2479                 return false;
2480
2481         ath9k_hw_init_pll(ah, NULL);
2482         return true;
2483 }
2484 EXPORT_SYMBOL(ath9k_hw_disable);
2485
2486 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2487 {
2488         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2489         struct ath9k_channel *chan = ah->curchan;
2490         struct ieee80211_channel *channel = chan->chan;
2491
2492         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2493
2494         ah->eep_ops->set_txpower(ah, chan,
2495                                  ath9k_regd_get_ctl(regulatory, chan),
2496                                  channel->max_antenna_gain * 2,
2497                                  channel->max_power * 2,
2498                                  min((u32) MAX_RATE_POWER,
2499                                  (u32) regulatory->power_limit));
2500 }
2501 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2502
2503 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2504 {
2505         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2506 }
2507 EXPORT_SYMBOL(ath9k_hw_setmac);
2508
2509 void ath9k_hw_setopmode(struct ath_hw *ah)
2510 {
2511         ath9k_hw_set_operating_mode(ah, ah->opmode);
2512 }
2513 EXPORT_SYMBOL(ath9k_hw_setopmode);
2514
2515 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2516 {
2517         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2518         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2519 }
2520 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2521
2522 void ath9k_hw_write_associd(struct ath_hw *ah)
2523 {
2524         struct ath_common *common = ath9k_hw_common(ah);
2525
2526         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2527         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2528                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2529 }
2530 EXPORT_SYMBOL(ath9k_hw_write_associd);
2531
2532 #define ATH9K_MAX_TSF_READ 10
2533
2534 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2535 {
2536         u32 tsf_lower, tsf_upper1, tsf_upper2;
2537         int i;
2538
2539         tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2540         for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2541                 tsf_lower = REG_READ(ah, AR_TSF_L32);
2542                 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2543                 if (tsf_upper2 == tsf_upper1)
2544                         break;
2545                 tsf_upper1 = tsf_upper2;
2546         }
2547
2548         WARN_ON( i == ATH9K_MAX_TSF_READ );
2549
2550         return (((u64)tsf_upper1 << 32) | tsf_lower);
2551 }
2552 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2553
2554 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2555 {
2556         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2557         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2558 }
2559 EXPORT_SYMBOL(ath9k_hw_settsf64);
2560
2561 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2562 {
2563         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2564                            AH_TSF_WRITE_TIMEOUT))
2565                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2566                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2567
2568         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2569 }
2570 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2571
2572 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2573 {
2574         if (setting)
2575                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2576         else
2577                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2578 }
2579 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2580
2581 /*
2582  *  Extend 15-bit time stamp from rx descriptor to
2583  *  a full 64-bit TSF using the current h/w TSF.
2584 */
2585 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2586 {
2587         u64 tsf;
2588
2589         tsf = ath9k_hw_gettsf64(ah);
2590         if ((tsf & 0x7fff) < rstamp)
2591                 tsf -= 0x8000;
2592         return (tsf & ~0x7fff) | rstamp;
2593 }
2594 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2595
2596 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2597 {
2598         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2599         u32 macmode;
2600
2601         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2602                 macmode = AR_2040_JOINED_RX_CLEAR;
2603         else
2604                 macmode = 0;
2605
2606         REG_WRITE(ah, AR_2040_MODE, macmode);
2607 }
2608
2609 /* HW Generic timers configuration */
2610
2611 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2612 {
2613         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2614         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2615         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2616         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2617         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2618         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2619         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2620         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2621         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2622         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2623                                 AR_NDP2_TIMER_MODE, 0x0002},
2624         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2625                                 AR_NDP2_TIMER_MODE, 0x0004},
2626         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2627                                 AR_NDP2_TIMER_MODE, 0x0008},
2628         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2629                                 AR_NDP2_TIMER_MODE, 0x0010},
2630         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2631                                 AR_NDP2_TIMER_MODE, 0x0020},
2632         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2633                                 AR_NDP2_TIMER_MODE, 0x0040},
2634         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2635                                 AR_NDP2_TIMER_MODE, 0x0080}
2636 };
2637
2638 /* HW generic timer primitives */
2639
2640 /* compute and clear index of rightmost 1 */
2641 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2642 {
2643         u32 b;
2644
2645         b = *mask;
2646         b &= (0-b);
2647         *mask &= ~b;
2648         b *= debruijn32;
2649         b >>= 27;
2650
2651         return timer_table->gen_timer_index[b];
2652 }
2653
2654 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2655 {
2656         return REG_READ(ah, AR_TSF_L32);
2657 }
2658 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2659
2660 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2661                                           void (*trigger)(void *),
2662                                           void (*overflow)(void *),
2663                                           void *arg,
2664                                           u8 timer_index)
2665 {
2666         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2667         struct ath_gen_timer *timer;
2668
2669         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2670
2671         if (timer == NULL) {
2672                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2673                           "Failed to allocate memory"
2674                           "for hw timer[%d]\n", timer_index);
2675                 return NULL;
2676         }
2677
2678         /* allocate a hardware generic timer slot */
2679         timer_table->timers[timer_index] = timer;
2680         timer->index = timer_index;
2681         timer->trigger = trigger;
2682         timer->overflow = overflow;
2683         timer->arg = arg;
2684
2685         return timer;
2686 }
2687 EXPORT_SYMBOL(ath_gen_timer_alloc);
2688
2689 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2690                               struct ath_gen_timer *timer,
2691                               u32 timer_next,
2692                               u32 timer_period)
2693 {
2694         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2695         u32 tsf;
2696
2697         BUG_ON(!timer_period);
2698
2699         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2700
2701         tsf = ath9k_hw_gettsf32(ah);
2702
2703         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2704                   "curent tsf %x period %x"
2705                   "timer_next %x\n", tsf, timer_period, timer_next);
2706
2707         /*
2708          * Pull timer_next forward if the current TSF already passed it
2709          * because of software latency
2710          */
2711         if (timer_next < tsf)
2712                 timer_next = tsf + timer_period;
2713
2714         /*
2715          * Program generic timer registers
2716          */
2717         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2718                  timer_next);
2719         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2720                   timer_period);
2721         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2722                     gen_tmr_configuration[timer->index].mode_mask);
2723
2724         /* Enable both trigger and thresh interrupt masks */
2725         REG_SET_BIT(ah, AR_IMR_S5,
2726                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2727                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2728 }
2729 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2730
2731 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2732 {
2733         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2734
2735         if ((timer->index < AR_FIRST_NDP_TIMER) ||
2736                 (timer->index >= ATH_MAX_GEN_TIMER)) {
2737                 return;
2738         }
2739
2740         /* Clear generic timer enable bits. */
2741         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2742                         gen_tmr_configuration[timer->index].mode_mask);
2743
2744         /* Disable both trigger and thresh interrupt masks */
2745         REG_CLR_BIT(ah, AR_IMR_S5,
2746                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2747                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2748
2749         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2750 }
2751 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2752
2753 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2754 {
2755         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2756
2757         /* free the hardware generic timer slot */
2758         timer_table->timers[timer->index] = NULL;
2759         kfree(timer);
2760 }
2761 EXPORT_SYMBOL(ath_gen_timer_free);
2762
2763 /*
2764  * Generic Timer Interrupts handling
2765  */
2766 void ath_gen_timer_isr(struct ath_hw *ah)
2767 {
2768         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2769         struct ath_gen_timer *timer;
2770         struct ath_common *common = ath9k_hw_common(ah);
2771         u32 trigger_mask, thresh_mask, index;
2772
2773         /* get hardware generic timer interrupt status */
2774         trigger_mask = ah->intr_gen_timer_trigger;
2775         thresh_mask = ah->intr_gen_timer_thresh;
2776         trigger_mask &= timer_table->timer_mask.val;
2777         thresh_mask &= timer_table->timer_mask.val;
2778
2779         trigger_mask &= ~thresh_mask;
2780
2781         while (thresh_mask) {
2782                 index = rightmost_index(timer_table, &thresh_mask);
2783                 timer = timer_table->timers[index];
2784                 BUG_ON(!timer);
2785                 ath_print(common, ATH_DBG_HWTIMER,
2786                           "TSF overflow for Gen timer %d\n", index);
2787                 timer->overflow(timer->arg);
2788         }
2789
2790         while (trigger_mask) {
2791                 index = rightmost_index(timer_table, &trigger_mask);
2792                 timer = timer_table->timers[index];
2793                 BUG_ON(!timer);
2794                 ath_print(common, ATH_DBG_HWTIMER,
2795                           "Gen timer[%d] trigger\n", index);
2796                 timer->trigger(timer->arg);
2797         }
2798 }
2799 EXPORT_SYMBOL(ath_gen_timer_isr);
2800
2801 /********/
2802 /* HTC  */
2803 /********/
2804
2805 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2806 {
2807         ah->htc_reset_init = true;
2808 }
2809 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2810
2811 static struct {
2812         u32 version;
2813         const char * name;
2814 } ath_mac_bb_names[] = {
2815         /* Devices with external radios */
2816         { AR_SREV_VERSION_5416_PCI,     "5416" },
2817         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2818         { AR_SREV_VERSION_9100,         "9100" },
2819         { AR_SREV_VERSION_9160,         "9160" },
2820         /* Single-chip solutions */
2821         { AR_SREV_VERSION_9280,         "9280" },
2822         { AR_SREV_VERSION_9285,         "9285" },
2823         { AR_SREV_VERSION_9287,         "9287" },
2824         { AR_SREV_VERSION_9271,         "9271" },
2825         { AR_SREV_VERSION_9300,         "9300" },
2826 };
2827
2828 /* For devices with external radios */
2829 static struct {
2830         u16 version;
2831         const char * name;
2832 } ath_rf_names[] = {
2833         { 0,                            "5133" },
2834         { AR_RAD5133_SREV_MAJOR,        "5133" },
2835         { AR_RAD5122_SREV_MAJOR,        "5122" },
2836         { AR_RAD2133_SREV_MAJOR,        "2133" },
2837         { AR_RAD2122_SREV_MAJOR,        "2122" }
2838 };
2839
2840 /*
2841  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2842  */
2843 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2844 {
2845         int i;
2846
2847         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2848                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2849                         return ath_mac_bb_names[i].name;
2850                 }
2851         }
2852
2853         return "????";
2854 }
2855
2856 /*
2857  * Return the RF name. "????" is returned if the RF is unknown.
2858  * Used for devices with external radios.
2859  */
2860 static const char *ath9k_hw_rf_name(u16 rf_version)
2861 {
2862         int i;
2863
2864         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2865                 if (ath_rf_names[i].version == rf_version) {
2866                         return ath_rf_names[i].name;
2867                 }
2868         }
2869
2870         return "????";
2871 }
2872
2873 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2874 {
2875         int used;
2876
2877         /* chipsets >= AR9280 are single-chip */
2878         if (AR_SREV_9280_10_OR_LATER(ah)) {
2879                 used = snprintf(hw_name, len,
2880                                "Atheros AR%s Rev:%x",
2881                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2882                                ah->hw_version.macRev);
2883         }
2884         else {
2885                 used = snprintf(hw_name, len,
2886                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2887                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2888                                ah->hw_version.macRev,
2889                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2890                                                 AR_RADIO_SREV_MAJOR)),
2891                                ah->hw_version.phyRev);
2892         }
2893
2894         hw_name[used] = '\0';
2895 }
2896 EXPORT_SYMBOL(ath9k_hw_name);