2 * Copyright (c) 2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 MODULE_AUTHOR("Atheros Communications");
20 MODULE_LICENSE("Dual BSD/GPL");
21 MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
23 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
24 module_param_named(debug, ath9k_debug, uint, 0);
25 MODULE_PARM_DESC(debug, "Debugging mask");
27 int htc_modparam_nohwcrypt;
28 module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31 #define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
37 #define CHAN5G(_freq, _idx) { \
38 .band = IEEE80211_BAND_5GHZ, \
39 .center_freq = (_freq), \
44 #define ATH_HTC_BTCOEX_PRODUCT_ID "wb193"
46 static struct ieee80211_channel ath9k_2ghz_channels[] = {
47 CHAN2G(2412, 0), /* Channel 1 */
48 CHAN2G(2417, 1), /* Channel 2 */
49 CHAN2G(2422, 2), /* Channel 3 */
50 CHAN2G(2427, 3), /* Channel 4 */
51 CHAN2G(2432, 4), /* Channel 5 */
52 CHAN2G(2437, 5), /* Channel 6 */
53 CHAN2G(2442, 6), /* Channel 7 */
54 CHAN2G(2447, 7), /* Channel 8 */
55 CHAN2G(2452, 8), /* Channel 9 */
56 CHAN2G(2457, 9), /* Channel 10 */
57 CHAN2G(2462, 10), /* Channel 11 */
58 CHAN2G(2467, 11), /* Channel 12 */
59 CHAN2G(2472, 12), /* Channel 13 */
60 CHAN2G(2484, 13), /* Channel 14 */
63 static struct ieee80211_channel ath9k_5ghz_channels[] = {
64 /* _We_ call this UNII 1 */
65 CHAN5G(5180, 14), /* Channel 36 */
66 CHAN5G(5200, 15), /* Channel 40 */
67 CHAN5G(5220, 16), /* Channel 44 */
68 CHAN5G(5240, 17), /* Channel 48 */
69 /* _We_ call this UNII 2 */
70 CHAN5G(5260, 18), /* Channel 52 */
71 CHAN5G(5280, 19), /* Channel 56 */
72 CHAN5G(5300, 20), /* Channel 60 */
73 CHAN5G(5320, 21), /* Channel 64 */
74 /* _We_ call this "Middle band" */
75 CHAN5G(5500, 22), /* Channel 100 */
76 CHAN5G(5520, 23), /* Channel 104 */
77 CHAN5G(5540, 24), /* Channel 108 */
78 CHAN5G(5560, 25), /* Channel 112 */
79 CHAN5G(5580, 26), /* Channel 116 */
80 CHAN5G(5600, 27), /* Channel 120 */
81 CHAN5G(5620, 28), /* Channel 124 */
82 CHAN5G(5640, 29), /* Channel 128 */
83 CHAN5G(5660, 30), /* Channel 132 */
84 CHAN5G(5680, 31), /* Channel 136 */
85 CHAN5G(5700, 32), /* Channel 140 */
86 /* _We_ call this UNII 3 */
87 CHAN5G(5745, 33), /* Channel 149 */
88 CHAN5G(5765, 34), /* Channel 153 */
89 CHAN5G(5785, 35), /* Channel 157 */
90 CHAN5G(5805, 36), /* Channel 161 */
91 CHAN5G(5825, 37), /* Channel 165 */
94 /* Atheros hardware rate code addition for short premble */
95 #define SHPCHECK(__hw_rate, __flags) \
96 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
98 #define RATE(_bitrate, _hw_rate, _flags) { \
99 .bitrate = (_bitrate), \
101 .hw_value = (_hw_rate), \
102 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
105 static struct ieee80211_rate ath9k_legacy_rates[] = {
107 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
108 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
109 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
120 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
124 if (atomic_read(&priv->htc->tgt_ready) > 0) {
125 atomic_dec(&priv->htc->tgt_ready);
129 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
130 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
132 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
136 atomic_dec(&priv->htc->tgt_ready);
141 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
143 ath9k_htc_exit_debug(priv->ah);
144 ath9k_hw_deinit(priv->ah);
145 tasklet_kill(&priv->wmi_tasklet);
146 tasklet_kill(&priv->rx_tasklet);
147 tasklet_kill(&priv->tx_tasklet);
152 static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
154 struct ieee80211_hw *hw = priv->hw;
156 wiphy_rfkill_stop_polling(hw->wiphy);
157 ath9k_deinit_leds(priv);
158 ieee80211_unregister_hw(hw);
159 ath9k_rx_cleanup(priv);
160 ath9k_tx_cleanup(priv);
161 ath9k_deinit_priv(priv);
164 static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
168 enum htc_endpoint_id,
170 enum htc_endpoint_id *ep_id)
172 struct htc_service_connreq req;
174 memset(&req, 0, sizeof(struct htc_service_connreq));
176 req.service_id = service_id;
177 req.ep_callbacks.priv = priv;
178 req.ep_callbacks.rx = ath9k_htc_rxep;
179 req.ep_callbacks.tx = tx;
181 return htc_connect_service(priv->htc, &req, ep_id);
184 static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid)
189 ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
194 ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
200 ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
207 ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
213 ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
219 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
225 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
231 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
237 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
243 * Setup required credits before initializing HTC.
244 * This is a bit hacky, but, since queuing is done in
245 * the HIF layer, shouldn't matter much.
252 priv->htc->credits = 45;
255 priv->htc->credits = 33;
258 ret = htc_init(priv->htc);
262 dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
268 dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
272 static int ath9k_reg_notifier(struct wiphy *wiphy,
273 struct regulatory_request *request)
275 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
276 struct ath9k_htc_priv *priv = hw->priv;
278 return ath_reg_notifier_apply(wiphy, request,
279 ath9k_hw_regulatory(priv->ah));
282 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
284 struct ath_hw *ah = (struct ath_hw *) hw_priv;
285 struct ath_common *common = ath9k_hw_common(ah);
286 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
287 __be32 val, reg = cpu_to_be32(reg_offset);
290 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
291 (u8 *) ®, sizeof(reg),
292 (u8 *) &val, sizeof(val),
295 ath_print(common, ATH_DBG_WMI,
296 "REGISTER READ FAILED: (0x%04x, %d)\n",
301 return be32_to_cpu(val);
304 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
306 struct ath_hw *ah = (struct ath_hw *) hw_priv;
307 struct ath_common *common = ath9k_hw_common(ah);
308 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
310 cpu_to_be32(reg_offset),
315 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
316 (u8 *) &buf, sizeof(buf),
317 (u8 *) &val, sizeof(val),
320 ath_print(common, ATH_DBG_WMI,
321 "REGISTER WRITE FAILED:(0x%04x, %d)\n",
326 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
328 struct ath_hw *ah = (struct ath_hw *) hw_priv;
329 struct ath_common *common = ath9k_hw_common(ah);
330 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
334 mutex_lock(&priv->wmi->multi_write_mutex);
336 /* Store the register/value */
337 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
338 cpu_to_be32(reg_offset);
339 priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
342 priv->wmi->multi_write_idx++;
344 /* If the buffer is full, send it out. */
345 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
346 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
347 (u8 *) &priv->wmi->multi_write,
348 sizeof(struct register_write) * priv->wmi->multi_write_idx,
349 (u8 *) &rsp_status, sizeof(rsp_status),
352 ath_print(common, ATH_DBG_WMI,
353 "REGISTER WRITE FAILED, multi len: %d\n",
354 priv->wmi->multi_write_idx);
356 priv->wmi->multi_write_idx = 0;
359 mutex_unlock(&priv->wmi->multi_write_mutex);
362 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
364 struct ath_hw *ah = (struct ath_hw *) hw_priv;
365 struct ath_common *common = ath9k_hw_common(ah);
366 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
368 if (atomic_read(&priv->wmi->mwrite_cnt))
369 ath9k_regwrite_buffer(hw_priv, val, reg_offset);
371 ath9k_regwrite_single(hw_priv, val, reg_offset);
374 static void ath9k_enable_regwrite_buffer(void *hw_priv)
376 struct ath_hw *ah = (struct ath_hw *) hw_priv;
377 struct ath_common *common = ath9k_hw_common(ah);
378 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
380 atomic_inc(&priv->wmi->mwrite_cnt);
383 static void ath9k_disable_regwrite_buffer(void *hw_priv)
385 struct ath_hw *ah = (struct ath_hw *) hw_priv;
386 struct ath_common *common = ath9k_hw_common(ah);
387 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
389 atomic_dec(&priv->wmi->mwrite_cnt);
392 static void ath9k_regwrite_flush(void *hw_priv)
394 struct ath_hw *ah = (struct ath_hw *) hw_priv;
395 struct ath_common *common = ath9k_hw_common(ah);
396 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
400 mutex_lock(&priv->wmi->multi_write_mutex);
402 if (priv->wmi->multi_write_idx) {
403 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
404 (u8 *) &priv->wmi->multi_write,
405 sizeof(struct register_write) * priv->wmi->multi_write_idx,
406 (u8 *) &rsp_status, sizeof(rsp_status),
409 ath_print(common, ATH_DBG_WMI,
410 "REGISTER WRITE FAILED, multi len: %d\n",
411 priv->wmi->multi_write_idx);
413 priv->wmi->multi_write_idx = 0;
416 mutex_unlock(&priv->wmi->multi_write_mutex);
419 static const struct ath_ops ath9k_common_ops = {
420 .read = ath9k_regread,
421 .write = ath9k_regwrite,
422 .enable_write_buffer = ath9k_enable_regwrite_buffer,
423 .disable_write_buffer = ath9k_disable_regwrite_buffer,
424 .write_flush = ath9k_regwrite_flush,
427 static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
429 *csz = L1_CACHE_BYTES >> 2;
432 static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
434 struct ath_hw *ah = (struct ath_hw *) common->ah;
436 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
438 if (!ath9k_hw_wait(ah,
439 AR_EEPROM_STATUS_DATA,
440 AR_EEPROM_STATUS_DATA_BUSY |
441 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
445 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
446 AR_EEPROM_STATUS_DATA_VAL);
451 static const struct ath_bus_ops ath9k_usb_bus_ops = {
452 .ath_bus_type = ATH_USB,
453 .read_cachesize = ath_usb_read_cachesize,
454 .eeprom_read = ath_usb_eeprom_read,
457 static void setup_ht_cap(struct ath9k_htc_priv *priv,
458 struct ieee80211_sta_ht_cap *ht_info)
460 struct ath_common *common = ath9k_hw_common(priv->ah);
461 u8 tx_streams, rx_streams;
464 ht_info->ht_supported = true;
465 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
466 IEEE80211_HT_CAP_SM_PS |
467 IEEE80211_HT_CAP_SGI_40 |
468 IEEE80211_HT_CAP_DSSSCCK40;
470 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
471 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
473 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
475 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
476 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
478 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
480 /* ath9k_htc supports only 1 or 2 stream devices */
481 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2);
482 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2);
484 ath_print(common, ATH_DBG_CONFIG,
485 "TX streams %d, RX streams: %d\n",
486 tx_streams, rx_streams);
488 if (tx_streams != rx_streams) {
489 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
490 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
491 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
494 for (i = 0; i < rx_streams; i++)
495 ht_info->mcs.rx_mask[i] = 0xff;
497 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
500 static int ath9k_init_queues(struct ath9k_htc_priv *priv)
502 struct ath_common *common = ath9k_hw_common(priv->ah);
505 for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
506 priv->hwq_map[i] = -1;
508 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
509 if (priv->beaconq == -1) {
510 ath_print(common, ATH_DBG_FATAL,
511 "Unable to setup BEACON xmit queue\n");
515 priv->cabq = ath9k_htc_cabq_setup(priv);
516 if (priv->cabq == -1) {
517 ath_print(common, ATH_DBG_FATAL,
518 "Unable to setup CAB xmit queue\n");
522 if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
523 ath_print(common, ATH_DBG_FATAL,
524 "Unable to setup xmit queue for BE traffic\n");
528 if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
529 ath_print(common, ATH_DBG_FATAL,
530 "Unable to setup xmit queue for BK traffic\n");
533 if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
534 ath_print(common, ATH_DBG_FATAL,
535 "Unable to setup xmit queue for VI traffic\n");
538 if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
539 ath_print(common, ATH_DBG_FATAL,
540 "Unable to setup xmit queue for VO traffic\n");
550 static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
552 struct ath_common *common = ath9k_hw_common(priv->ah);
555 /* Get the hardware key cache size. */
556 common->keymax = priv->ah->caps.keycache_size;
557 if (common->keymax > ATH_KEYMAX) {
558 ath_print(common, ATH_DBG_ANY,
559 "Warning, using only %u entries in %u key cache\n",
560 ATH_KEYMAX, common->keymax);
561 common->keymax = ATH_KEYMAX;
564 if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
565 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
568 * Reset the key cache since some parts do not
569 * reset the contents on initial power up.
571 for (i = 0; i < common->keymax; i++)
572 ath_hw_keyreset(common, (u16) i);
575 static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
577 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) {
578 priv->sbands[IEEE80211_BAND_2GHZ].channels =
580 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
581 priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
582 ARRAY_SIZE(ath9k_2ghz_channels);
583 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
584 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
585 ARRAY_SIZE(ath9k_legacy_rates);
588 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes)) {
589 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
590 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
591 priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
592 ARRAY_SIZE(ath9k_5ghz_channels);
593 priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
594 ath9k_legacy_rates + 4;
595 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
596 ARRAY_SIZE(ath9k_legacy_rates) - 4;
600 static void ath9k_init_misc(struct ath9k_htc_priv *priv)
602 struct ath_common *common = ath9k_hw_common(priv->ah);
604 common->tx_chainmask = priv->ah->caps.tx_chainmask;
605 common->rx_chainmask = priv->ah->caps.rx_chainmask;
607 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
609 priv->ah->opmode = NL80211_IFTYPE_STATION;
612 static void ath9k_init_btcoex(struct ath9k_htc_priv *priv)
616 switch (priv->ah->btcoex_hw.scheme) {
617 case ATH_BTCOEX_CFG_NONE:
619 case ATH_BTCOEX_CFG_3WIRE:
620 priv->ah->btcoex_hw.btactive_gpio = 7;
621 priv->ah->btcoex_hw.btpriority_gpio = 6;
622 priv->ah->btcoex_hw.wlanactive_gpio = 8;
623 priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
624 ath9k_hw_btcoex_init_3wire(priv->ah);
625 ath_htc_init_btcoex_work(priv);
626 qnum = priv->hwq_map[WME_AC_BE];
627 ath9k_hw_init_btcoex_hw(priv->ah, qnum);
635 static int ath9k_init_priv(struct ath9k_htc_priv *priv,
636 u16 devid, char *product)
638 struct ath_hw *ah = NULL;
639 struct ath_common *common;
640 int ret = 0, csz = 0;
642 priv->op_flags |= OP_INVALID;
644 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
648 ah->hw_version.devid = devid;
649 ah->hw_version.subsysid = 0; /* FIXME */
652 common = ath9k_hw_common(ah);
653 common->ops = &ath9k_common_ops;
654 common->bus_ops = &ath9k_usb_bus_ops;
656 common->hw = priv->hw;
658 common->debug_mask = ath9k_debug;
660 spin_lock_init(&priv->wmi->wmi_lock);
661 spin_lock_init(&priv->beacon_lock);
662 spin_lock_init(&priv->tx_lock);
663 mutex_init(&priv->mutex);
664 mutex_init(&priv->htc_pm_lock);
665 tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet,
666 (unsigned long)priv);
667 tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
668 (unsigned long)priv);
669 tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv);
670 INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work);
671 INIT_WORK(&priv->ps_work, ath9k_ps_work);
674 * Cache line size is used to size and align various
675 * structures used to communicate with the hardware.
677 ath_read_cachesize(common, &csz);
678 common->cachelsz = csz << 2; /* convert to bytes */
680 ret = ath9k_hw_init(ah);
682 ath_print(common, ATH_DBG_FATAL,
683 "Unable to initialize hardware; "
684 "initialization status: %d\n", ret);
688 ret = ath9k_htc_init_debug(ah);
690 ath_print(common, ATH_DBG_FATAL,
691 "Unable to create debugfs files\n");
695 ret = ath9k_init_queues(priv);
699 ath9k_init_crypto(priv);
700 ath9k_init_channels_rates(priv);
701 ath9k_init_misc(priv);
703 if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) {
704 ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE;
705 ath9k_init_btcoex(priv);
711 ath9k_htc_exit_debug(ah);
722 static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
723 struct ieee80211_hw *hw)
725 struct ath_common *common = ath9k_hw_common(priv->ah);
727 hw->flags = IEEE80211_HW_SIGNAL_DBM |
728 IEEE80211_HW_AMPDU_AGGREGATION |
729 IEEE80211_HW_SPECTRUM_MGMT |
730 IEEE80211_HW_HAS_RATE_CONTROL |
731 IEEE80211_HW_RX_INCLUDES_FCS |
732 IEEE80211_HW_SUPPORTS_PS |
733 IEEE80211_HW_PS_NULLFUNC_STACK;
735 hw->wiphy->interface_modes =
736 BIT(NL80211_IFTYPE_STATION) |
737 BIT(NL80211_IFTYPE_ADHOC);
739 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
742 hw->channel_change_time = 5000;
743 hw->max_listen_interval = 10;
744 hw->vif_data_size = sizeof(struct ath9k_htc_vif);
745 hw->sta_data_size = sizeof(struct ath9k_htc_sta);
747 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
748 hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
749 sizeof(struct htc_frame_hdr) + 4;
751 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
752 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
753 &priv->sbands[IEEE80211_BAND_2GHZ];
754 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes))
755 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
756 &priv->sbands[IEEE80211_BAND_5GHZ];
758 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
759 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
761 &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
762 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes))
764 &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
767 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
770 static int ath9k_init_device(struct ath9k_htc_priv *priv,
771 u16 devid, char *product)
773 struct ieee80211_hw *hw = priv->hw;
774 struct ath_common *common;
777 struct ath_regulatory *reg;
779 /* Bring up device */
780 error = ath9k_init_priv(priv, devid, product);
785 common = ath9k_hw_common(ah);
786 ath9k_set_hw_capab(priv, hw);
788 /* Initialize regulatory */
789 error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
794 reg = &common->regulatory;
797 error = ath9k_tx_init(priv);
802 error = ath9k_rx_init(priv);
806 /* Register with mac80211 */
807 error = ieee80211_register_hw(hw);
811 /* Handle world regulatory */
812 if (!ath_is_world_regd(reg)) {
813 error = regulatory_hint(hw->wiphy, reg->alpha2);
818 ath9k_init_leds(priv);
819 ath9k_start_rfkill_poll(priv);
824 ieee80211_unregister_hw(hw);
826 ath9k_rx_cleanup(priv);
828 ath9k_tx_cleanup(priv);
832 ath9k_deinit_priv(priv);
837 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
838 u16 devid, char *product)
840 struct ieee80211_hw *hw;
841 struct ath9k_htc_priv *priv;
844 hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
850 priv->htc = htc_handle;
852 htc_handle->drv_priv = priv;
853 SET_IEEE80211_DEV(hw, priv->dev);
855 ret = ath9k_htc_wait_for_target(priv);
859 priv->wmi = ath9k_init_wmi(priv);
865 ret = ath9k_init_htc_services(priv, devid);
869 /* The device may have been unplugged earlier. */
870 priv->op_flags &= ~OP_UNPLUGGED;
872 ret = ath9k_init_device(priv, devid, product);
879 ath9k_deinit_wmi(priv);
881 ieee80211_free_hw(hw);
885 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
887 if (htc_handle->drv_priv) {
889 /* Check if the device has been yanked out. */
891 htc_handle->drv_priv->op_flags |= OP_UNPLUGGED;
893 ath9k_deinit_device(htc_handle->drv_priv);
894 ath9k_deinit_wmi(htc_handle->drv_priv);
895 ieee80211_free_hw(htc_handle->drv_priv->hw);
900 int ath9k_htc_resume(struct htc_target *htc_handle)
904 ret = ath9k_htc_wait_for_target(htc_handle->drv_priv);
908 ret = ath9k_init_htc_services(htc_handle->drv_priv,
909 htc_handle->drv_priv->ah->hw_version.devid);
914 static int __init ath9k_htc_init(void)
918 error = ath9k_htc_debug_create_root();
921 "ath9k_htc: Unable to create debugfs root: %d\n",
926 error = ath9k_hif_usb_init();
929 "ath9k_htc: No USB devices found,"
930 " driver not installed.\n");
938 ath9k_htc_debug_remove_root();
942 module_init(ath9k_htc_init);
944 static void __exit ath9k_htc_exit(void)
946 ath9k_hif_usb_exit();
947 ath9k_htc_debug_remove_root();
948 printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
950 module_exit(ath9k_htc_exit);