2 * Copyright (c) 2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 MODULE_AUTHOR("Atheros Communications");
20 MODULE_LICENSE("Dual BSD/GPL");
21 MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
23 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
24 module_param_named(debug, ath9k_debug, uint, 0);
25 MODULE_PARM_DESC(debug, "Debugging mask");
27 int htc_modparam_nohwcrypt;
28 module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31 #define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
37 #define CHAN5G(_freq, _idx) { \
38 .band = IEEE80211_BAND_5GHZ, \
39 .center_freq = (_freq), \
44 static struct ieee80211_channel ath9k_2ghz_channels[] = {
45 CHAN2G(2412, 0), /* Channel 1 */
46 CHAN2G(2417, 1), /* Channel 2 */
47 CHAN2G(2422, 2), /* Channel 3 */
48 CHAN2G(2427, 3), /* Channel 4 */
49 CHAN2G(2432, 4), /* Channel 5 */
50 CHAN2G(2437, 5), /* Channel 6 */
51 CHAN2G(2442, 6), /* Channel 7 */
52 CHAN2G(2447, 7), /* Channel 8 */
53 CHAN2G(2452, 8), /* Channel 9 */
54 CHAN2G(2457, 9), /* Channel 10 */
55 CHAN2G(2462, 10), /* Channel 11 */
56 CHAN2G(2467, 11), /* Channel 12 */
57 CHAN2G(2472, 12), /* Channel 13 */
58 CHAN2G(2484, 13), /* Channel 14 */
61 static struct ieee80211_channel ath9k_5ghz_channels[] = {
62 /* _We_ call this UNII 1 */
63 CHAN5G(5180, 14), /* Channel 36 */
64 CHAN5G(5200, 15), /* Channel 40 */
65 CHAN5G(5220, 16), /* Channel 44 */
66 CHAN5G(5240, 17), /* Channel 48 */
67 /* _We_ call this UNII 2 */
68 CHAN5G(5260, 18), /* Channel 52 */
69 CHAN5G(5280, 19), /* Channel 56 */
70 CHAN5G(5300, 20), /* Channel 60 */
71 CHAN5G(5320, 21), /* Channel 64 */
72 /* _We_ call this "Middle band" */
73 CHAN5G(5500, 22), /* Channel 100 */
74 CHAN5G(5520, 23), /* Channel 104 */
75 CHAN5G(5540, 24), /* Channel 108 */
76 CHAN5G(5560, 25), /* Channel 112 */
77 CHAN5G(5580, 26), /* Channel 116 */
78 CHAN5G(5600, 27), /* Channel 120 */
79 CHAN5G(5620, 28), /* Channel 124 */
80 CHAN5G(5640, 29), /* Channel 128 */
81 CHAN5G(5660, 30), /* Channel 132 */
82 CHAN5G(5680, 31), /* Channel 136 */
83 CHAN5G(5700, 32), /* Channel 140 */
84 /* _We_ call this UNII 3 */
85 CHAN5G(5745, 33), /* Channel 149 */
86 CHAN5G(5765, 34), /* Channel 153 */
87 CHAN5G(5785, 35), /* Channel 157 */
88 CHAN5G(5805, 36), /* Channel 161 */
89 CHAN5G(5825, 37), /* Channel 165 */
92 /* Atheros hardware rate code addition for short premble */
93 #define SHPCHECK(__hw_rate, __flags) \
94 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
96 #define RATE(_bitrate, _hw_rate, _flags) { \
97 .bitrate = (_bitrate), \
99 .hw_value = (_hw_rate), \
100 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
103 static struct ieee80211_rate ath9k_legacy_rates[] = {
105 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
106 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
107 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
118 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
122 if (atomic_read(&priv->htc->tgt_ready) > 0) {
123 atomic_dec(&priv->htc->tgt_ready);
127 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
128 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
130 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
134 atomic_dec(&priv->htc->tgt_ready);
139 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
141 ath9k_htc_exit_debug(priv->ah);
142 ath9k_hw_deinit(priv->ah);
143 tasklet_kill(&priv->wmi_tasklet);
144 tasklet_kill(&priv->rx_tasklet);
145 tasklet_kill(&priv->tx_tasklet);
150 static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
152 struct ieee80211_hw *hw = priv->hw;
154 wiphy_rfkill_stop_polling(hw->wiphy);
155 ath9k_deinit_leds(priv);
156 ieee80211_unregister_hw(hw);
157 ath9k_rx_cleanup(priv);
158 ath9k_tx_cleanup(priv);
159 ath9k_deinit_priv(priv);
162 static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
166 enum htc_endpoint_id,
168 enum htc_endpoint_id *ep_id)
170 struct htc_service_connreq req;
172 memset(&req, 0, sizeof(struct htc_service_connreq));
174 req.service_id = service_id;
175 req.ep_callbacks.priv = priv;
176 req.ep_callbacks.rx = ath9k_htc_rxep;
177 req.ep_callbacks.tx = tx;
179 return htc_connect_service(priv->htc, &req, ep_id);
182 static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid)
187 ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
192 ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
198 ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
205 ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
211 ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
217 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
223 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
229 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
235 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
241 * Setup required credits before initializing HTC.
242 * This is a bit hacky, but, since queuing is done in
243 * the HIF layer, shouldn't matter much.
249 priv->htc->credits = 45;
252 priv->htc->credits = 33;
255 ret = htc_init(priv->htc);
259 dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
265 dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
269 static int ath9k_reg_notifier(struct wiphy *wiphy,
270 struct regulatory_request *request)
272 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
273 struct ath9k_htc_priv *priv = hw->priv;
275 return ath_reg_notifier_apply(wiphy, request,
276 ath9k_hw_regulatory(priv->ah));
279 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
281 struct ath_hw *ah = (struct ath_hw *) hw_priv;
282 struct ath_common *common = ath9k_hw_common(ah);
283 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
284 __be32 val, reg = cpu_to_be32(reg_offset);
287 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
288 (u8 *) ®, sizeof(reg),
289 (u8 *) &val, sizeof(val),
292 ath_print(common, ATH_DBG_WMI,
293 "REGISTER READ FAILED: (0x%04x, %d)\n",
298 return be32_to_cpu(val);
301 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
303 struct ath_hw *ah = (struct ath_hw *) hw_priv;
304 struct ath_common *common = ath9k_hw_common(ah);
305 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
307 cpu_to_be32(reg_offset),
312 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
313 (u8 *) &buf, sizeof(buf),
314 (u8 *) &val, sizeof(val),
317 ath_print(common, ATH_DBG_WMI,
318 "REGISTER WRITE FAILED:(0x%04x, %d)\n",
323 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
325 struct ath_hw *ah = (struct ath_hw *) hw_priv;
326 struct ath_common *common = ath9k_hw_common(ah);
327 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
331 mutex_lock(&priv->wmi->multi_write_mutex);
333 /* Store the register/value */
334 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
335 cpu_to_be32(reg_offset);
336 priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
339 priv->wmi->multi_write_idx++;
341 /* If the buffer is full, send it out. */
342 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
343 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
344 (u8 *) &priv->wmi->multi_write,
345 sizeof(struct register_write) * priv->wmi->multi_write_idx,
346 (u8 *) &rsp_status, sizeof(rsp_status),
349 ath_print(common, ATH_DBG_WMI,
350 "REGISTER WRITE FAILED, multi len: %d\n",
351 priv->wmi->multi_write_idx);
353 priv->wmi->multi_write_idx = 0;
356 mutex_unlock(&priv->wmi->multi_write_mutex);
359 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
361 struct ath_hw *ah = (struct ath_hw *) hw_priv;
362 struct ath_common *common = ath9k_hw_common(ah);
363 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
365 if (atomic_read(&priv->wmi->mwrite_cnt))
366 ath9k_regwrite_buffer(hw_priv, val, reg_offset);
368 ath9k_regwrite_single(hw_priv, val, reg_offset);
371 static void ath9k_enable_regwrite_buffer(void *hw_priv)
373 struct ath_hw *ah = (struct ath_hw *) hw_priv;
374 struct ath_common *common = ath9k_hw_common(ah);
375 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
377 atomic_inc(&priv->wmi->mwrite_cnt);
380 static void ath9k_disable_regwrite_buffer(void *hw_priv)
382 struct ath_hw *ah = (struct ath_hw *) hw_priv;
383 struct ath_common *common = ath9k_hw_common(ah);
384 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
386 atomic_dec(&priv->wmi->mwrite_cnt);
389 static void ath9k_regwrite_flush(void *hw_priv)
391 struct ath_hw *ah = (struct ath_hw *) hw_priv;
392 struct ath_common *common = ath9k_hw_common(ah);
393 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
397 mutex_lock(&priv->wmi->multi_write_mutex);
399 if (priv->wmi->multi_write_idx) {
400 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
401 (u8 *) &priv->wmi->multi_write,
402 sizeof(struct register_write) * priv->wmi->multi_write_idx,
403 (u8 *) &rsp_status, sizeof(rsp_status),
406 ath_print(common, ATH_DBG_WMI,
407 "REGISTER WRITE FAILED, multi len: %d\n",
408 priv->wmi->multi_write_idx);
410 priv->wmi->multi_write_idx = 0;
413 mutex_unlock(&priv->wmi->multi_write_mutex);
416 static const struct ath_ops ath9k_common_ops = {
417 .read = ath9k_regread,
418 .write = ath9k_regwrite,
419 .enable_write_buffer = ath9k_enable_regwrite_buffer,
420 .disable_write_buffer = ath9k_disable_regwrite_buffer,
421 .write_flush = ath9k_regwrite_flush,
424 static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
426 *csz = L1_CACHE_BYTES >> 2;
429 static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
431 struct ath_hw *ah = (struct ath_hw *) common->ah;
433 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
435 if (!ath9k_hw_wait(ah,
436 AR_EEPROM_STATUS_DATA,
437 AR_EEPROM_STATUS_DATA_BUSY |
438 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
442 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
443 AR_EEPROM_STATUS_DATA_VAL);
448 static const struct ath_bus_ops ath9k_usb_bus_ops = {
449 .ath_bus_type = ATH_USB,
450 .read_cachesize = ath_usb_read_cachesize,
451 .eeprom_read = ath_usb_eeprom_read,
454 static void setup_ht_cap(struct ath9k_htc_priv *priv,
455 struct ieee80211_sta_ht_cap *ht_info)
457 struct ath_common *common = ath9k_hw_common(priv->ah);
458 u8 tx_streams, rx_streams;
461 ht_info->ht_supported = true;
462 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
463 IEEE80211_HT_CAP_SM_PS |
464 IEEE80211_HT_CAP_SGI_40 |
465 IEEE80211_HT_CAP_DSSSCCK40;
467 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
468 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
470 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
472 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
473 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
475 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
477 /* ath9k_htc supports only 1 or 2 stream devices */
478 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2);
479 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2);
481 ath_print(common, ATH_DBG_CONFIG,
482 "TX streams %d, RX streams: %d\n",
483 tx_streams, rx_streams);
485 if (tx_streams != rx_streams) {
486 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
487 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
488 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
491 for (i = 0; i < rx_streams; i++)
492 ht_info->mcs.rx_mask[i] = 0xff;
494 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
497 static int ath9k_init_queues(struct ath9k_htc_priv *priv)
499 struct ath_common *common = ath9k_hw_common(priv->ah);
502 for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
503 priv->hwq_map[i] = -1;
505 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
506 if (priv->beaconq == -1) {
507 ath_print(common, ATH_DBG_FATAL,
508 "Unable to setup BEACON xmit queue\n");
512 priv->cabq = ath9k_htc_cabq_setup(priv);
513 if (priv->cabq == -1) {
514 ath_print(common, ATH_DBG_FATAL,
515 "Unable to setup CAB xmit queue\n");
519 if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
520 ath_print(common, ATH_DBG_FATAL,
521 "Unable to setup xmit queue for BE traffic\n");
525 if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
526 ath_print(common, ATH_DBG_FATAL,
527 "Unable to setup xmit queue for BK traffic\n");
530 if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
531 ath_print(common, ATH_DBG_FATAL,
532 "Unable to setup xmit queue for VI traffic\n");
535 if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
536 ath_print(common, ATH_DBG_FATAL,
537 "Unable to setup xmit queue for VO traffic\n");
547 static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
549 struct ath_common *common = ath9k_hw_common(priv->ah);
552 /* Get the hardware key cache size. */
553 common->keymax = priv->ah->caps.keycache_size;
554 if (common->keymax > ATH_KEYMAX) {
555 ath_print(common, ATH_DBG_ANY,
556 "Warning, using only %u entries in %u key cache\n",
557 ATH_KEYMAX, common->keymax);
558 common->keymax = ATH_KEYMAX;
562 * Reset the key cache since some parts do not
563 * reset the contents on initial power up.
565 for (i = 0; i < common->keymax; i++)
566 ath9k_hw_keyreset(priv->ah, (u16) i);
569 static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
571 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) {
572 priv->sbands[IEEE80211_BAND_2GHZ].channels =
574 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
575 priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
576 ARRAY_SIZE(ath9k_2ghz_channels);
577 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
578 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
579 ARRAY_SIZE(ath9k_legacy_rates);
582 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes)) {
583 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
584 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
585 priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
586 ARRAY_SIZE(ath9k_5ghz_channels);
587 priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
588 ath9k_legacy_rates + 4;
589 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
590 ARRAY_SIZE(ath9k_legacy_rates) - 4;
594 static void ath9k_init_misc(struct ath9k_htc_priv *priv)
596 struct ath_common *common = ath9k_hw_common(priv->ah);
598 common->tx_chainmask = priv->ah->caps.tx_chainmask;
599 common->rx_chainmask = priv->ah->caps.rx_chainmask;
601 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
602 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
604 priv->ah->opmode = NL80211_IFTYPE_STATION;
607 static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid)
609 struct ath_hw *ah = NULL;
610 struct ath_common *common;
611 int ret = 0, csz = 0;
613 priv->op_flags |= OP_INVALID;
615 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
619 ah->hw_version.devid = devid;
620 ah->hw_version.subsysid = 0; /* FIXME */
623 common = ath9k_hw_common(ah);
624 common->ops = &ath9k_common_ops;
625 common->bus_ops = &ath9k_usb_bus_ops;
627 common->hw = priv->hw;
629 common->debug_mask = ath9k_debug;
631 spin_lock_init(&priv->wmi->wmi_lock);
632 spin_lock_init(&priv->beacon_lock);
633 spin_lock_init(&priv->tx_lock);
634 mutex_init(&priv->mutex);
635 mutex_init(&priv->htc_pm_lock);
636 tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet,
637 (unsigned long)priv);
638 tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
639 (unsigned long)priv);
640 tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv);
641 INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work);
642 INIT_WORK(&priv->ps_work, ath9k_ps_work);
645 * Cache line size is used to size and align various
646 * structures used to communicate with the hardware.
648 ath_read_cachesize(common, &csz);
649 common->cachelsz = csz << 2; /* convert to bytes */
651 ret = ath9k_hw_init(ah);
653 ath_print(common, ATH_DBG_FATAL,
654 "Unable to initialize hardware; "
655 "initialization status: %d\n", ret);
659 ret = ath9k_htc_init_debug(ah);
661 ath_print(common, ATH_DBG_FATAL,
662 "Unable to create debugfs files\n");
666 ret = ath9k_init_queues(priv);
670 ath9k_init_crypto(priv);
671 ath9k_init_channels_rates(priv);
672 ath9k_init_misc(priv);
677 ath9k_htc_exit_debug(ah);
688 static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
689 struct ieee80211_hw *hw)
691 struct ath_common *common = ath9k_hw_common(priv->ah);
693 hw->flags = IEEE80211_HW_SIGNAL_DBM |
694 IEEE80211_HW_AMPDU_AGGREGATION |
695 IEEE80211_HW_SPECTRUM_MGMT |
696 IEEE80211_HW_HAS_RATE_CONTROL |
697 IEEE80211_HW_RX_INCLUDES_FCS |
698 IEEE80211_HW_SUPPORTS_PS |
699 IEEE80211_HW_PS_NULLFUNC_STACK;
701 hw->wiphy->interface_modes =
702 BIT(NL80211_IFTYPE_STATION) |
703 BIT(NL80211_IFTYPE_ADHOC);
705 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
708 hw->channel_change_time = 5000;
709 hw->max_listen_interval = 10;
710 hw->vif_data_size = sizeof(struct ath9k_htc_vif);
711 hw->sta_data_size = sizeof(struct ath9k_htc_sta);
713 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
714 hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
715 sizeof(struct htc_frame_hdr) + 4;
717 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
718 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
719 &priv->sbands[IEEE80211_BAND_2GHZ];
720 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes))
721 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
722 &priv->sbands[IEEE80211_BAND_5GHZ];
724 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
725 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
727 &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
728 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes))
730 &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
733 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
736 static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
738 struct ieee80211_hw *hw = priv->hw;
739 struct ath_common *common;
742 struct ath_regulatory *reg;
744 /* Bring up device */
745 error = ath9k_init_priv(priv, devid);
750 common = ath9k_hw_common(ah);
751 ath9k_set_hw_capab(priv, hw);
753 /* Initialize regulatory */
754 error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
759 reg = &common->regulatory;
762 error = ath9k_tx_init(priv);
767 error = ath9k_rx_init(priv);
771 /* Register with mac80211 */
772 error = ieee80211_register_hw(hw);
776 /* Handle world regulatory */
777 if (!ath_is_world_regd(reg)) {
778 error = regulatory_hint(hw->wiphy, reg->alpha2);
783 ath9k_init_leds(priv);
784 ath9k_start_rfkill_poll(priv);
789 ieee80211_unregister_hw(hw);
791 ath9k_rx_cleanup(priv);
793 ath9k_tx_cleanup(priv);
797 ath9k_deinit_priv(priv);
802 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
805 struct ieee80211_hw *hw;
806 struct ath9k_htc_priv *priv;
809 hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
815 priv->htc = htc_handle;
817 htc_handle->drv_priv = priv;
818 SET_IEEE80211_DEV(hw, priv->dev);
820 ret = ath9k_htc_wait_for_target(priv);
824 priv->wmi = ath9k_init_wmi(priv);
830 ret = ath9k_init_htc_services(priv, devid);
834 /* The device may have been unplugged earlier. */
835 priv->op_flags &= ~OP_UNPLUGGED;
837 ret = ath9k_init_device(priv, devid);
844 ath9k_deinit_wmi(priv);
846 ieee80211_free_hw(hw);
850 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
852 if (htc_handle->drv_priv) {
854 /* Check if the device has been yanked out. */
856 htc_handle->drv_priv->op_flags |= OP_UNPLUGGED;
858 ath9k_deinit_device(htc_handle->drv_priv);
859 ath9k_deinit_wmi(htc_handle->drv_priv);
860 ieee80211_free_hw(htc_handle->drv_priv->hw);
865 int ath9k_htc_resume(struct htc_target *htc_handle)
869 ret = ath9k_htc_wait_for_target(htc_handle->drv_priv);
873 ret = ath9k_init_htc_services(htc_handle->drv_priv,
874 htc_handle->drv_priv->ah->hw_version.devid);
879 static int __init ath9k_htc_init(void)
883 error = ath9k_htc_debug_create_root();
886 "ath9k_htc: Unable to create debugfs root: %d\n",
891 error = ath9k_hif_usb_init();
894 "ath9k_htc: No USB devices found,"
895 " driver not installed.\n");
903 ath9k_htc_debug_remove_root();
907 module_init(ath9k_htc_init);
909 static void __exit ath9k_htc_exit(void)
911 ath9k_hif_usb_exit();
912 ath9k_htc_debug_remove_root();
913 printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
915 module_exit(ath9k_htc_exit);