drivers/net/wireless/ath/ath9k/calib.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "hw-ops.h"
  19 #include "ar9002_phy.h"
  20
  21 /* We can tune this as we go by monitoring really low values */
  22 #define ATH9K_NF_TOO_LOW        -60
  23 #define AR9285_CLCAL_REDO_THRESH    1
  24
  25 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
  26  * is incorrect and we should use the static NF value. Later we can try to
  27  * find out why they are reporting these values */
  28
  29 static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
  30 {
  31         if (nf > ATH9K_NF_TOO_LOW) {
  32                 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
  33                           "noise floor value detected (%d) is "
  34                           "lower than what we think is a "
  35                           "reasonable value (%d)\n",
  36                           nf, ATH9K_NF_TOO_LOW);
  37                 return false;
  38         }
  39         return true;
  40 }
  41
  42 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
  43 {
  44         int16_t nfval;
  45         int16_t sort[ATH9K_NF_CAL_HIST_MAX];
  46         int i, j;
  47
  48         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
  49                 sort[i] = nfCalBuffer[i];
  50
  51         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
  52                 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
  53                         if (sort[j] > sort[j - 1]) {
  54                                 nfval = sort[j];
  55                                 sort[j] = sort[j - 1];
  56                                 sort[j - 1] = nfval;
  57                         }
  58                 }
  59         }
  60         nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
  61
  62         return nfval;
  63 }
  64
  65 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
  66                                               int16_t *nfarray)
  67 {
  68         int i;
  69
  70         for (i = 0; i < NUM_NF_READINGS; i++) {
  71                 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
  72
  73                 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
  74                         h[i].currIndex = 0;
  75
  76                 if (h[i].invalidNFcount > 0) {
  77                         if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE ||
  78                             nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
  79                                 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
  80                         } else {
  81                                 h[i].invalidNFcount--;
  82                                 h[i].privNF = nfarray[i];
  83                         }
  84                 } else {
  85                         h[i].privNF =
  86                                 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
  87                 }
  88         }
  89         return;
  90 }
  91
  92 static bool getNoiseFloorThresh(struct ath_hw *ah,
  93                                 enum ieee80211_band band,
  94                                 int16_t *nft)
  95 {
  96         switch (band) {
  97         case IEEE80211_BAND_5GHZ:
  98                 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
  99                 break;
 100         case IEEE80211_BAND_2GHZ:
 101                 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
 102                 break;
 103         default:
 104                 BUG_ON(1);
 105                 return false;
 106         }
 107
 108         return true;
 109 }
 110
 111 static void ath9k_hw_setup_calibration(struct ath_hw *ah,
 112                                        struct ath9k_cal_list *currCal)
 113 {
 114         struct ath_common *common = ath9k_hw_common(ah);
 115
 116         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
 117                       AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
 118                       currCal->calData->calCountMax);
 119
 120         switch (currCal->calData->calType) {
 121         case IQ_MISMATCH_CAL:
 122                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
 123                 ath_print(common, ATH_DBG_CALIBRATE,
 124                           "starting IQ Mismatch Calibration\n");
 125                 break;
 126         case ADC_GAIN_CAL:
 127                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
 128                 ath_print(common, ATH_DBG_CALIBRATE,
 129                           "starting ADC Gain Calibration\n");
 130                 break;
 131         case ADC_DC_CAL:
 132                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
 133                 ath_print(common, ATH_DBG_CALIBRATE,
 134                           "starting ADC DC Calibration\n");
 135                 break;
 136         case ADC_DC_INIT_CAL:
 137                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
 138                 ath_print(common, ATH_DBG_CALIBRATE,
 139                           "starting Init ADC DC Calibration\n");
 140                 break;
 141         }
 142
 143         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
 144                     AR_PHY_TIMING_CTRL4_DO_CAL);
 145 }
 146
 147 static void ath9k_hw_reset_calibration(struct ath_hw *ah,
 148                                        struct ath9k_cal_list *currCal)
 149 {
 150         int i;
 151
 152         ath9k_hw_setup_calibration(ah, currCal);
 153
 154         currCal->calState = CAL_RUNNING;
 155
 156         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 157                 ah->meas0.sign[i] = 0;
 158                 ah->meas1.sign[i] = 0;
 159                 ah->meas2.sign[i] = 0;
 160                 ah->meas3.sign[i] = 0;
 161         }
 162
 163         ah->cal_samples = 0;
 164 }
 165
 166 static bool ath9k_hw_per_calibration(struct ath_hw *ah,
 167                                      struct ath9k_channel *ichan,
 168                                      u8 rxchainmask,
 169                                      struct ath9k_cal_list *currCal)
 170 {
 171         bool iscaldone = false;
 172
 173         if (currCal->calState == CAL_RUNNING) {
 174                 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
 175                       AR_PHY_TIMING_CTRL4_DO_CAL)) {
 176
 177                         currCal->calData->calCollect(ah);
 178                         ah->cal_samples++;
 179
 180                         if (ah->cal_samples >= currCal->calData->calNumSamples) {
 181                                 int i, numChains = 0;
 182                                 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 183                                         if (rxchainmask & (1 << i))
 184                                                 numChains++;
 185                                 }
 186
 187                                 currCal->calData->calPostProc(ah, numChains);
 188                                 ichan->CalValid |= currCal->calData->calType;
 189                                 currCal->calState = CAL_DONE;
 190                                 iscaldone = true;
 191                         } else {
 192                                 ath9k_hw_setup_calibration(ah, currCal);
 193                         }
 194                 }
 195         } else if (!(ichan->CalValid & currCal->calData->calType)) {
 196                 ath9k_hw_reset_calibration(ah, currCal);
 197         }
 198
 199         return iscaldone;
 200 }
 201
 202 /* Assumes you are talking about the currently configured channel */
 203 static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
 204                                      enum ath9k_cal_types calType)
 205 {
 206         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 207
 208         switch (calType & ah->supp_cals) {
 209         case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
 210                 return true;
 211         case ADC_GAIN_CAL:
 212         case ADC_DC_CAL:
 213                 if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
 214                       conf_is_ht20(conf)))
 215                         return true;
 216                 break;
 217         }
 218         return false;
 219 }
 220
 221 static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
 222 {
 223         int i;
 224
 225         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 226                 ah->totalPowerMeasI[i] +=
 227                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 228                 ah->totalPowerMeasQ[i] +=
 229                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 230                 ah->totalIqCorrMeas[i] +=
 231                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 232                 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
 233                           "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
 234                           ah->cal_samples, i, ah->totalPowerMeasI[i],
 235                           ah->totalPowerMeasQ[i],
 236                           ah->totalIqCorrMeas[i]);
 237         }
 238 }
 239
 240 static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
 241 {
 242         int i;
 243
 244         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 245                 ah->totalAdcIOddPhase[i] +=
 246                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 247                 ah->totalAdcIEvenPhase[i] +=
 248                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 249                 ah->totalAdcQOddPhase[i] +=
 250                         REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 251                 ah->totalAdcQEvenPhase[i] +=
 252                         REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 253
 254                 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
 255                           "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
 256                           "oddq=0x%08x; evenq=0x%08x;\n",
 257                           ah->cal_samples, i,
 258                           ah->totalAdcIOddPhase[i],
 259                           ah->totalAdcIEvenPhase[i],
 260                           ah->totalAdcQOddPhase[i],
 261                           ah->totalAdcQEvenPhase[i]);
 262         }
 263 }
 264
 265 static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
 266 {
 267         int i;
 268
 269         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 270                 ah->totalAdcDcOffsetIOddPhase[i] +=
 271                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 272                 ah->totalAdcDcOffsetIEvenPhase[i] +=
 273                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 274                 ah->totalAdcDcOffsetQOddPhase[i] +=
 275                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 276                 ah->totalAdcDcOffsetQEvenPhase[i] +=
 277                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 278
 279                 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
 280                           "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
 281                           "oddq=0x%08x; evenq=0x%08x;\n",
 282                           ah->cal_samples, i,
 283                           ah->totalAdcDcOffsetIOddPhase[i],
 284                           ah->totalAdcDcOffsetIEvenPhase[i],
 285                           ah->totalAdcDcOffsetQOddPhase[i],
 286                           ah->totalAdcDcOffsetQEvenPhase[i]);
 287         }
 288 }
 289
 290 static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
 291 {
 292         struct ath_common *common = ath9k_hw_common(ah);
 293         u32 powerMeasQ, powerMeasI, iqCorrMeas;
 294         u32 qCoffDenom, iCoffDenom;
 295         int32_t qCoff, iCoff;
 296         int iqCorrNeg, i;
 297
 298         for (i = 0; i < numChains; i++) {
 299                 powerMeasI = ah->totalPowerMeasI[i];
 300                 powerMeasQ = ah->totalPowerMeasQ[i];
 301                 iqCorrMeas = ah->totalIqCorrMeas[i];
 302
 303                 ath_print(common, ATH_DBG_CALIBRATE,
 304                           "Starting IQ Cal and Correction for Chain %d\n",
 305                           i);
 306
 307                 ath_print(common, ATH_DBG_CALIBRATE,
 308                           "Orignal: Chn %diq_corr_meas = 0x%08x\n",
 309                           i, ah->totalIqCorrMeas[i]);
 310
 311                 iqCorrNeg = 0;
 312
 313                 if (iqCorrMeas > 0x80000000) {
 314                         iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
 315                         iqCorrNeg = 1;
 316                 }
 317
 318                 ath_print(common, ATH_DBG_CALIBRATE,
 319                           "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
 320                 ath_print(common, ATH_DBG_CALIBRATE,
 321                           "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
 322                 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
 323                           iqCorrNeg);
 324
 325                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
 326                 qCoffDenom = powerMeasQ / 64;
 327
 328                 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
 329                     (qCoffDenom != 0)) {
 330                         iCoff = iqCorrMeas / iCoffDenom;
 331                         qCoff = powerMeasI / qCoffDenom - 64;
 332                         ath_print(common, ATH_DBG_CALIBRATE,
 333                                   "Chn %d iCoff = 0x%08x\n", i, iCoff);
 334                         ath_print(common, ATH_DBG_CALIBRATE,
 335                                   "Chn %d qCoff = 0x%08x\n", i, qCoff);
 336
 337                         iCoff = iCoff & 0x3f;
 338                         ath_print(common, ATH_DBG_CALIBRATE,
 339                                   "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
 340                         if (iqCorrNeg == 0x0)
 341                                 iCoff = 0x40 - iCoff;
 342
 343                         if (qCoff > 15)
 344                                 qCoff = 15;
 345                         else if (qCoff <= -16)
 346                                 qCoff = 16;
 347
 348                         ath_print(common, ATH_DBG_CALIBRATE,
 349                                   "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
 350                                   i, iCoff, qCoff);
 351
 352                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
 353                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
 354                                       iCoff);
 355                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
 356                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
 357                                       qCoff);
 358                         ath_print(common, ATH_DBG_CALIBRATE,
 359                                   "IQ Cal and Correction done for Chain %d\n",
 360                                   i);
 361                 }
 362         }
 363
 364         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
 365                     AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
 366 }
 367
 368 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
 369 {
 370         struct ath_common *common = ath9k_hw_common(ah);
 371         u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
 372         u32 qGainMismatch, iGainMismatch, val, i;
 373
 374         for (i = 0; i < numChains; i++) {
 375                 iOddMeasOffset = ah->totalAdcIOddPhase[i];
 376                 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
 377                 qOddMeasOffset = ah->totalAdcQOddPhase[i];
 378                 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
 379
 380                 ath_print(common, ATH_DBG_CALIBRATE,
 381                           "Starting ADC Gain Cal for Chain %d\n", i);
 382
 383                 ath_print(common, ATH_DBG_CALIBRATE,
 384                           "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
 385                           iOddMeasOffset);
 386                 ath_print(common, ATH_DBG_CALIBRATE,
 387                           "Chn %d pwr_meas_even_i = 0x%08x\n", i,
 388                           iEvenMeasOffset);
 389                 ath_print(common, ATH_DBG_CALIBRATE,
 390                           "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
 391                           qOddMeasOffset);
 392                 ath_print(common, ATH_DBG_CALIBRATE,
 393                           "Chn %d pwr_meas_even_q = 0x%08x\n", i,
 394                           qEvenMeasOffset);
 395
 396                 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
 397                         iGainMismatch =
 398                                 ((iEvenMeasOffset * 32) /
 399                                  iOddMeasOffset) & 0x3f;
 400                         qGainMismatch =
 401                                 ((qOddMeasOffset * 32) /
 402                                  qEvenMeasOffset) & 0x3f;
 403
 404                         ath_print(common, ATH_DBG_CALIBRATE,
 405                                   "Chn %d gain_mismatch_i = 0x%08x\n", i,
 406                                   iGainMismatch);
 407                         ath_print(common, ATH_DBG_CALIBRATE,
 408                                   "Chn %d gain_mismatch_q = 0x%08x\n", i,
 409                                   qGainMismatch);
 410
 411                         val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
 412                         val &= 0xfffff000;
 413                         val |= (qGainMismatch) | (iGainMismatch << 6);
 414                         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 415
 416                         ath_print(common, ATH_DBG_CALIBRATE,
 417                                   "ADC Gain Cal done for Chain %d\n", i);
 418                 }
 419         }
 420
 421         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
 422                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
 423                   AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
 424 }
 425
 426 static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
 427 {
 428         struct ath_common *common = ath9k_hw_common(ah);
 429         u32 iOddMeasOffset, iEvenMeasOffset, val, i;
 430         int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
 431         const struct ath9k_percal_data *calData =
 432                 ah->cal_list_curr->calData;
 433         u32 numSamples =
 434                 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
 435
 436         for (i = 0; i < numChains; i++) {
 437                 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
 438                 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
 439                 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
 440                 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
 441
 442                 ath_print(common, ATH_DBG_CALIBRATE,
 443                            "Starting ADC DC Offset Cal for Chain %d\n", i);
 444
 445                 ath_print(common, ATH_DBG_CALIBRATE,
 446                           "Chn %d pwr_meas_odd_i = %d\n", i,
 447                           iOddMeasOffset);
 448                 ath_print(common, ATH_DBG_CALIBRATE,
 449                           "Chn %d pwr_meas_even_i = %d\n", i,
 450                           iEvenMeasOffset);
 451                 ath_print(common, ATH_DBG_CALIBRATE,
 452                           "Chn %d pwr_meas_odd_q = %d\n", i,
 453                           qOddMeasOffset);
 454                 ath_print(common, ATH_DBG_CALIBRATE,
 455                           "Chn %d pwr_meas_even_q = %d\n", i,
 456                           qEvenMeasOffset);
 457
 458                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
 459                                numSamples) & 0x1ff;
 460                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
 461                                numSamples) & 0x1ff;
 462
 463                 ath_print(common, ATH_DBG_CALIBRATE,
 464                           "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
 465                           iDcMismatch);
 466                 ath_print(common, ATH_DBG_CALIBRATE,
 467                           "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
 468                           qDcMismatch);
 469
 470                 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
 471                 val &= 0xc0000fff;
 472                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
 473                 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 474
 475                 ath_print(common, ATH_DBG_CALIBRATE,
 476                           "ADC DC Offset Cal done for Chain %d\n", i);
 477         }
 478
 479         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
 480                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
 481                   AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
 482 }
 483
 484 /* This is done for the currently configured channel */
 485 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
 486 {
 487         struct ath_common *common = ath9k_hw_common(ah);
 488         struct ieee80211_conf *conf = &common->hw->conf;
 489         struct ath9k_cal_list *currCal = ah->cal_list_curr;
 490
 491         if (!ah->curchan)
 492                 return true;
 493
 494         if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
 495                 return true;
 496
 497         if (currCal == NULL)
 498                 return true;
 499
 500         if (currCal->calState != CAL_DONE) {
 501                 ath_print(common, ATH_DBG_CALIBRATE,
 502                           "Calibration state incorrect, %d\n",
 503                           currCal->calState);
 504                 return true;
 505         }
 506
 507         if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
 508                 return true;
 509
 510         ath_print(common, ATH_DBG_CALIBRATE,
 511                   "Resetting Cal %d state for channel %u\n",
 512                   currCal->calData->calType, conf->channel->center_freq);
 513
 514         ah->curchan->CalValid &= ~currCal->calData->calType;
 515         currCal->calState = CAL_WAITING;
 516
 517         return false;
 518 }
 519 EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
 520
 521 void ath9k_hw_start_nfcal(struct ath_hw *ah)
 522 {
 523         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
 524                     AR_PHY_AGC_CONTROL_ENABLE_NF);
 525         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
 526                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
 527         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
 528 }
 529
 530 void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
 531 {
 532         struct ath9k_nfcal_hist *h;
 533         int i, j;
 534         int32_t val;
 535         const u32 ar5416_cca_regs[6] = {
 536                 AR_PHY_CCA,
 537                 AR_PHY_CH1_CCA,
 538                 AR_PHY_CH2_CCA,
 539                 AR_PHY_EXT_CCA,
 540                 AR_PHY_CH1_EXT_CCA,
 541                 AR_PHY_CH2_EXT_CCA
 542         };
 543         u8 chainmask, rx_chain_status;
 544
 545         rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
 546         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 547                 chainmask = 0x9;
 548         else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
 549                 if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
 550                         chainmask = 0x1B;
 551                 else
 552                         chainmask = 0x09;
 553         } else {
 554                 if (rx_chain_status & 0x4)
 555                         chainmask = 0x3F;
 556                 else if (rx_chain_status & 0x2)
 557                         chainmask = 0x1B;
 558                 else
 559                         chainmask = 0x09;
 560         }
 561
 562         h = ah->nfCalHist;
 563
 564         for (i = 0; i < NUM_NF_READINGS; i++) {
 565                 if (chainmask & (1 << i)) {
 566                         val = REG_READ(ah, ar5416_cca_regs[i]);
 567                         val &= 0xFFFFFE00;
 568                         val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
 569                         REG_WRITE(ah, ar5416_cca_regs[i], val);
 570                 }
 571         }
 572
 573         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
 574                     AR_PHY_AGC_CONTROL_ENABLE_NF);
 575         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
 576                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
 577         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
 578
 579         for (j = 0; j < 5; j++) {
 580                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
 581                      AR_PHY_AGC_CONTROL_NF) == 0)
 582                         break;
 583                 udelay(50);
 584         }
 585
 586         for (i = 0; i < NUM_NF_READINGS; i++) {
 587                 if (chainmask & (1 << i)) {
 588                         val = REG_READ(ah, ar5416_cca_regs[i]);
 589                         val &= 0xFFFFFE00;
 590                         val |= (((u32) (-50) << 1) & 0x1ff);
 591                         REG_WRITE(ah, ar5416_cca_regs[i], val);
 592                 }
 593         }
 594 }
 595
 596 int16_t ath9k_hw_getnf(struct ath_hw *ah,
 597                        struct ath9k_channel *chan)
 598 {
 599         struct ath_common *common = ath9k_hw_common(ah);
 600         int16_t nf, nfThresh;
 601         int16_t nfarray[NUM_NF_READINGS] = { 0 };
 602         struct ath9k_nfcal_hist *h;
 603         struct ieee80211_channel *c = chan->chan;
 604
 605         chan->channelFlags &= (~CHANNEL_CW_INT);
 606         if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
 607                 ath_print(common, ATH_DBG_CALIBRATE,
 608                           "NF did not complete in calibration window\n");
 609                 nf = 0;
 610                 chan->rawNoiseFloor = nf;
 611                 return chan->rawNoiseFloor;
 612         } else {
 613                 ath9k_hw_do_getnf(ah, nfarray);
 614                 nf = nfarray[0];
 615                 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
 616                     && nf > nfThresh) {
 617                         ath_print(common, ATH_DBG_CALIBRATE,
 618                                   "noise floor failed detected; "
 619                                   "detected %d, threshold %d\n",
 620                                   nf, nfThresh);
 621                         chan->channelFlags |= CHANNEL_CW_INT;
 622                 }
 623         }
 624
 625         h = ah->nfCalHist;
 626
 627         ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
 628         chan->rawNoiseFloor = h[0].privNF;
 629
 630         return chan->rawNoiseFloor;
 631 }
 632
 633 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah)
 634 {
 635         int i, j;
 636         s16 noise_floor;
 637
 638         if (AR_SREV_9280(ah))
 639                 noise_floor = AR_PHY_CCA_MAX_AR9280_GOOD_VALUE;
 640         else if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 641                 noise_floor = AR_PHY_CCA_MAX_AR9285_GOOD_VALUE;
 642         else if (AR_SREV_9287(ah))
 643                 noise_floor = AR_PHY_CCA_MAX_AR9287_GOOD_VALUE;
 644         else
 645                 noise_floor = AR_PHY_CCA_MAX_AR5416_GOOD_VALUE;
 646
 647         for (i = 0; i < NUM_NF_READINGS; i++) {
 648                 ah->nfCalHist[i].currIndex = 0;
 649                 ah->nfCalHist[i].privNF = noise_floor;
 650                 ah->nfCalHist[i].invalidNFcount =
 651                         AR_PHY_CCA_FILTERWINDOW_LENGTH;
 652                 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
 653                         ah->nfCalHist[i].nfCalBuffer[j] = noise_floor;
 654                 }
 655         }
 656 }
 657
 658 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
 659 {
 660         s16 nf;
 661
 662         if (chan->rawNoiseFloor == 0)
 663                 nf = -96;
 664         else
 665                 nf = chan->rawNoiseFloor;
 666
 667         if (!ath9k_hw_nf_in_range(ah, nf))
 668                 nf = ATH_DEFAULT_NOISE_FLOOR;
 669
 670         return nf;
 671 }
 672 EXPORT_SYMBOL(ath9k_hw_getchan_noise);
 673
 674 static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
 675 {
 676         u32 rddata;
 677         int32_t delta, currPDADC, slope;
 678
 679         rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
 680         currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
 681
 682         if (ah->initPDADC == 0 || currPDADC == 0) {
 683                 /*
 684                  * Zero value indicates that no frames have been transmitted yet,
 685                  * can't do temperature compensation until frames are transmitted.
 686                  */
 687                 return;
 688         } else {
 689                 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
 690
 691                 if (slope == 0) { /* to avoid divide by zero case */
 692                         delta = 0;
 693                 } else {
 694                         delta = ((currPDADC - ah->initPDADC)*4) / slope;
 695                 }
 696                 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
 697                               AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
 698                 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
 699                               AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
 700         }
 701 }
 702
 703 static void ath9k_olc_temp_compensation(struct ath_hw *ah)
 704 {
 705         u32 rddata, i;
 706         int delta, currPDADC, regval;
 707
 708         if (OLC_FOR_AR9287_10_LATER) {
 709                 ar9287_hw_olc_temp_compensation(ah);
 710         } else {
 711                 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
 712                 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
 713
 714                 if (ah->initPDADC == 0 || currPDADC == 0)
 715                         return;
 716
 717                 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
 718                         delta = (currPDADC - ah->initPDADC + 4) / 8;
 719                 else
 720                         delta = (currPDADC - ah->initPDADC + 5) / 10;
 721
 722                 if (delta != ah->PDADCdelta) {
 723                         ah->PDADCdelta = delta;
 724                         for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
 725                                 regval = ah->originalGain[i] - delta;
 726                                 if (regval < 0)
 727                                         regval = 0;
 728
 729                                 REG_RMW_FIELD(ah,
 730                                               AR_PHY_TX_GAIN_TBL1 + i * 4,
 731                                               AR_PHY_TX_GAIN, regval);
 732                         }
 733                 }
 734         }
 735 }
 736
 737 static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
 738 {
 739         u32 regVal;
 740         unsigned int i;
 741         u32 regList [][2] = {
 742                 { 0x786c, 0 },
 743                 { 0x7854, 0 },
 744                 { 0x7820, 0 },
 745                 { 0x7824, 0 },
 746                 { 0x7868, 0 },
 747                 { 0x783c, 0 },
 748                 { 0x7838, 0 } ,
 749                 { 0x7828, 0 } ,
 750         };
 751
 752         for (i = 0; i < ARRAY_SIZE(regList); i++)
 753                 regList[i][1] = REG_READ(ah, regList[i][0]);
 754
 755         regVal = REG_READ(ah, 0x7834);
 756         regVal &= (~(0x1));
 757         REG_WRITE(ah, 0x7834, regVal);
 758         regVal = REG_READ(ah, 0x9808);
 759         regVal |= (0x1 << 27);
 760         REG_WRITE(ah, 0x9808, regVal);
 761
 762         /* 786c,b23,1, pwddac=1 */
 763         REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
 764         /* 7854, b5,1, pdrxtxbb=1 */
 765         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
 766         /* 7854, b7,1, pdv2i=1 */
 767         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
 768         /* 7854, b8,1, pddacinterface=1 */
 769         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
 770         /* 7824,b12,0, offcal=0 */
 771         REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
 772         /* 7838, b1,0, pwddb=0 */
 773         REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
 774         /* 7820,b11,0, enpacal=0 */
 775         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
 776         /* 7820,b25,1, pdpadrv1=0 */
 777         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
 778         /* 7820,b24,0, pdpadrv2=0 */
 779         REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
 780         /* 7820,b23,0, pdpaout=0 */
 781         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
 782         /* 783c,b14-16,7, padrvgn2tab_0=7 */
 783         REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
 784         /*
 785          * 7838,b29-31,0, padrvgn1tab_0=0
 786          * does not matter since we turn it off
 787          */
 788         REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
 789
 790         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
 791
 792         /* Set:
 793          * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
 794          * txon=1,paon=1,oscon=1,synthon_force=1
 795          */
 796         REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
 797         udelay(30);
 798         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
 799
 800         /* find off_6_1; */
 801         for (i = 6; i > 0; i--) {
 802                 regVal = REG_READ(ah, 0x7834);
 803                 regVal |= (1 << (20 + i));
 804                 REG_WRITE(ah, 0x7834, regVal);
 805                 udelay(1);
 806                 //regVal = REG_READ(ah, 0x7834);
 807                 regVal &= (~(0x1 << (20 + i)));
 808                 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
 809                             << (20 + i));
 810                 REG_WRITE(ah, 0x7834, regVal);
 811         }
 812
 813         regVal = (regVal >>20) & 0x7f;
 814
 815         /* Update PA cal info */
 816         if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
 817                 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
 818                         ah->pacal_info.max_skipcount =
 819                                 2 * ah->pacal_info.max_skipcount;
 820                 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
 821         } else {
 822                 ah->pacal_info.max_skipcount = 1;
 823                 ah->pacal_info.skipcount = 0;
 824                 ah->pacal_info.prev_offset = regVal;
 825         }
 826
 827         regVal = REG_READ(ah, 0x7834);
 828         regVal |= 0x1;
 829         REG_WRITE(ah, 0x7834, regVal);
 830         regVal = REG_READ(ah, 0x9808);
 831         regVal &= (~(0x1 << 27));
 832         REG_WRITE(ah, 0x9808, regVal);
 833
 834         for (i = 0; i < ARRAY_SIZE(regList); i++)
 835                 REG_WRITE(ah, regList[i][0], regList[i][1]);
 836 }
 837
 838 static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
 839 {
 840         struct ath_common *common = ath9k_hw_common(ah);
 841         u32 regVal;
 842         int i, offset, offs_6_1, offs_0;
 843         u32 ccomp_org, reg_field;
 844         u32 regList[][2] = {
 845                 { 0x786c, 0 },
 846                 { 0x7854, 0 },
 847                 { 0x7820, 0 },
 848                 { 0x7824, 0 },
 849                 { 0x7868, 0 },
 850                 { 0x783c, 0 },
 851                 { 0x7838, 0 },
 852         };
 853
 854         ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
 855
 856         /* PA CAL is not needed for high power solution */
 857         if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
 858             AR5416_EEP_TXGAIN_HIGH_POWER)
 859                 return;
 860
 861         if (AR_SREV_9285_11(ah)) {
 862                 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
 863                 udelay(10);
 864         }
 865
 866         for (i = 0; i < ARRAY_SIZE(regList); i++)
 867                 regList[i][1] = REG_READ(ah, regList[i][0]);
 868
 869         regVal = REG_READ(ah, 0x7834);
 870         regVal &= (~(0x1));
 871         REG_WRITE(ah, 0x7834, regVal);
 872         regVal = REG_READ(ah, 0x9808);
 873         regVal |= (0x1 << 27);
 874         REG_WRITE(ah, 0x9808, regVal);
 875
 876         REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
 877         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
 878         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
 879         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
 880         REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
 881         REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
 882         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
 883         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
 884         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
 885         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
 886         REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
 887         REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
 888         ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
 889         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
 890
 891         REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
 892         udelay(30);
 893         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
 894         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
 895
 896         for (i = 6; i > 0; i--) {
 897                 regVal = REG_READ(ah, 0x7834);
 898                 regVal |= (1 << (19 + i));
 899                 REG_WRITE(ah, 0x7834, regVal);
 900                 udelay(1);
 901                 regVal = REG_READ(ah, 0x7834);
 902                 regVal &= (~(0x1 << (19 + i)));
 903                 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
 904                 regVal |= (reg_field << (19 + i));
 905                 REG_WRITE(ah, 0x7834, regVal);
 906         }
 907
 908         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
 909         udelay(1);
 910         reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
 911         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
 912         offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
 913         offs_0   = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
 914
 915         offset = (offs_6_1<<1) | offs_0;
 916         offset = offset - 0;
 917         offs_6_1 = offset>>1;
 918         offs_0 = offset & 1;
 919
 920         if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
 921                 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
 922                         ah->pacal_info.max_skipcount =
 923                                 2 * ah->pacal_info.max_skipcount;
 924                 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
 925         } else {
 926                 ah->pacal_info.max_skipcount = 1;
 927                 ah->pacal_info.skipcount = 0;
 928                 ah->pacal_info.prev_offset = offset;
 929         }
 930
 931         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
 932         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
 933
 934         regVal = REG_READ(ah, 0x7834);
 935         regVal |= 0x1;
 936         REG_WRITE(ah, 0x7834, regVal);
 937         regVal = REG_READ(ah, 0x9808);
 938         regVal &= (~(0x1 << 27));
 939         REG_WRITE(ah, 0x9808, regVal);
 940
 941         for (i = 0; i < ARRAY_SIZE(regList); i++)
 942                 REG_WRITE(ah, regList[i][0], regList[i][1]);
 943
 944         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
 945
 946         if (AR_SREV_9285_11(ah))
 947                 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
 948
 949 }
 950
 951 static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
 952 {
 953         if (AR_SREV_9271(ah)) {
 954                 if (is_reset || !ah->pacal_info.skipcount)
 955                         ath9k_hw_9271_pa_cal(ah, is_reset);
 956                 else
 957                         ah->pacal_info.skipcount--;
 958         } else if (AR_SREV_9285_11_OR_LATER(ah)) {
 959                 if (is_reset || !ah->pacal_info.skipcount)
 960                         ath9k_hw_9285_pa_cal(ah, is_reset);
 961                 else
 962                         ah->pacal_info.skipcount--;
 963         }
 964 }
 965
 966 static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
 967 {
 968         if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
 969                 ath9k_olc_temp_compensation(ah);
 970 }
 971
 972 bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
 973                         u8 rxchainmask, bool longcal)
 974 {
 975         bool iscaldone = true;
 976         struct ath9k_cal_list *currCal = ah->cal_list_curr;
 977
 978         if (currCal &&
 979             (currCal->calState == CAL_RUNNING ||
 980              currCal->calState == CAL_WAITING)) {
 981                 iscaldone = ath9k_hw_per_calibration(ah, chan,
 982                                                      rxchainmask, currCal);
 983                 if (iscaldone) {
 984                         ah->cal_list_curr = currCal = currCal->calNext;
 985
 986                         if (currCal->calState == CAL_WAITING) {
 987                                 iscaldone = false;
 988                                 ath9k_hw_reset_calibration(ah, currCal);
 989                         }
 990                 }
 991         }
 992
 993         /* Do NF cal only at longer intervals */
 994         if (longcal) {
 995                 /* Do periodic PAOffset Cal */
 996                 ar9002_hw_pa_cal(ah, false);
 997                 ar9002_hw_olc_temp_compensation(ah);
 998
 999                 /* Get the value from the previous NF cal and update history buffer */
1000                 ath9k_hw_getnf(ah, chan);
1001
1002                 /*
1003                  * Load the NF from history buffer of the current channel.
1004                  * NF is slow time-variant, so it is OK to use a historical value.
1005                  */
1006                 ath9k_hw_loadnf(ah, ah->curchan);
1007
1008                 ath9k_hw_start_nfcal(ah);
1009         }
1010
1011         return iscaldone;
1012 }
1013 EXPORT_SYMBOL(ath9k_hw_calibrate);
1014
1015 /* Carrier leakage Calibration fix */
1016 static bool ar9285_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1017 {
1018         struct ath_common *common = ath9k_hw_common(ah);
1019
1020         REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1021         if (IS_CHAN_HT20(chan)) {
1022                 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1023                 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1024                 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1025                             AR_PHY_AGC_CONTROL_FLTR_CAL);
1026                 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1027                 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1028                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1029                                   AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
1030                         ath_print(common, ATH_DBG_CALIBRATE, "offset "
1031                                   "calibration failed to complete in "
1032                                   "1ms; noisy ??\n");
1033                         return false;
1034                 }
1035                 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1036                 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1037                 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1038         }
1039         REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1040         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1041         REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1042         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1043         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1044                           0, AH_WAIT_TIMEOUT)) {
1045                 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
1046                           "failed to complete in 1ms; noisy ??\n");
1047                 return false;
1048         }
1049
1050         REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1051         REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1052         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1053
1054         return true;
1055 }
1056
1057 static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1058 {
1059         int i;
1060         u_int32_t txgain_max;
1061         u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
1062         u_int32_t reg_clc_I0, reg_clc_Q0;
1063         u_int32_t i0_num = 0;
1064         u_int32_t q0_num = 0;
1065         u_int32_t total_num = 0;
1066         u_int32_t reg_rf2g5_org;
1067         bool retv = true;
1068
1069         if (!(ar9285_cl_cal(ah, chan)))
1070                 return false;
1071
1072         txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
1073                         AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
1074
1075         for (i = 0; i < (txgain_max+1); i++) {
1076                 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
1077                            AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
1078                 if (!(gain_mask & (1 << clc_gain))) {
1079                         gain_mask |= (1 << clc_gain);
1080                         clc_num++;
1081                 }
1082         }
1083
1084         for (i = 0; i < clc_num; i++) {
1085                 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
1086                               & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
1087                 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
1088                               & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
1089                 if (reg_clc_I0 == 0)
1090                         i0_num++;
1091
1092                 if (reg_clc_Q0 == 0)
1093                         q0_num++;
1094         }
1095         total_num = i0_num + q0_num;
1096         if (total_num > AR9285_CLCAL_REDO_THRESH) {
1097                 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
1098                 if (AR_SREV_9285E_20(ah)) {
1099                         REG_WRITE(ah, AR9285_RF2G5,
1100                                   (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
1101                                   AR9285_RF2G5_IC50TX_XE_SET);
1102                 } else {
1103                         REG_WRITE(ah, AR9285_RF2G5,
1104                                   (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
1105                                   AR9285_RF2G5_IC50TX_SET);
1106                 }
1107                 retv = ar9285_cl_cal(ah, chan);
1108                 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
1109         }
1110         return retv;
1111 }
1112
1113 bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1114 {
1115         struct ath_common *common = ath9k_hw_common(ah);
1116
1117         if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
1118                 if (!ar9285_clc(ah, chan))
1119                         return false;
1120         } else {
1121                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1122                         if (!AR_SREV_9287_10_OR_LATER(ah))
1123                                 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
1124                                             AR_PHY_ADC_CTL_OFF_PWDADC);
1125                         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1126                                     AR_PHY_AGC_CONTROL_FLTR_CAL);
1127                 }
1128
1129                 /* Calibrate the AGC */
1130                 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1131                           REG_READ(ah, AR_PHY_AGC_CONTROL) |
1132                           AR_PHY_AGC_CONTROL_CAL);
1133
1134                 /* Poll for offset calibration complete */
1135                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1136                                    0, AH_WAIT_TIMEOUT)) {
1137                         ath_print(common, ATH_DBG_CALIBRATE,
1138                                   "offset calibration failed to "
1139                                   "complete in 1ms; noisy environment?\n");
1140                         return false;
1141                 }
1142
1143                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1144                         if (!AR_SREV_9287_10_OR_LATER(ah))
1145                                 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
1146                                             AR_PHY_ADC_CTL_OFF_PWDADC);
1147                         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1148                                     AR_PHY_AGC_CONTROL_FLTR_CAL);
1149                 }
1150         }
1151
1152         /* Do PA Calibration */
1153         ar9002_hw_pa_cal(ah, true);
1154
1155         /* Do NF Calibration after DC offset and other calibrations */
1156         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1157                   REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
1158
1159         ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
1160
1161         /* Enable IQ, ADC Gain and ADC DC offset CALs */
1162         if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
1163                 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
1164                         INIT_CAL(&ah->adcgain_caldata);
1165                         INSERT_CAL(ah, &ah->adcgain_caldata);
1166                         ath_print(common, ATH_DBG_CALIBRATE,
1167                                   "enabling ADC Gain Calibration.\n");
1168                 }
1169                 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
1170                         INIT_CAL(&ah->adcdc_caldata);
1171                         INSERT_CAL(ah, &ah->adcdc_caldata);
1172                         ath_print(common, ATH_DBG_CALIBRATE,
1173                                   "enabling ADC DC Calibration.\n");
1174                 }
1175                 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
1176                         INIT_CAL(&ah->iq_caldata);
1177                         INSERT_CAL(ah, &ah->iq_caldata);
1178                         ath_print(common, ATH_DBG_CALIBRATE,
1179                                   "enabling IQ Calibration.\n");
1180                 }
1181
1182                 ah->cal_list_curr = ah->cal_list;
1183
1184                 if (ah->cal_list_curr)
1185                         ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1186         }
1187
1188         chan->CalValid = 0;
1189
1190         return true;
1191 }
1192
1193 const struct ath9k_percal_data iq_cal_multi_sample = {
1194         IQ_MISMATCH_CAL,
1195         MAX_CAL_SAMPLES,
1196         PER_MIN_LOG_COUNT,
1197         ath9k_hw_iqcal_collect,
1198         ath9k_hw_iqcalibrate
1199 };
1200 const struct ath9k_percal_data iq_cal_single_sample = {
1201         IQ_MISMATCH_CAL,
1202         MIN_CAL_SAMPLES,
1203         PER_MAX_LOG_COUNT,
1204         ath9k_hw_iqcal_collect,
1205         ath9k_hw_iqcalibrate
1206 };
1207 const struct ath9k_percal_data adc_gain_cal_multi_sample = {
1208         ADC_GAIN_CAL,
1209         MAX_CAL_SAMPLES,
1210         PER_MIN_LOG_COUNT,
1211         ath9k_hw_adc_gaincal_collect,
1212         ath9k_hw_adc_gaincal_calibrate
1213 };
1214 const struct ath9k_percal_data adc_gain_cal_single_sample = {
1215         ADC_GAIN_CAL,
1216         MIN_CAL_SAMPLES,
1217         PER_MAX_LOG_COUNT,
1218         ath9k_hw_adc_gaincal_collect,
1219         ath9k_hw_adc_gaincal_calibrate
1220 };
1221 const struct ath9k_percal_data adc_dc_cal_multi_sample = {
1222         ADC_DC_CAL,
1223         MAX_CAL_SAMPLES,
1224         PER_MIN_LOG_COUNT,
1225         ath9k_hw_adc_dccal_collect,
1226         ath9k_hw_adc_dccal_calibrate
1227 };
1228 const struct ath9k_percal_data adc_dc_cal_single_sample = {
1229         ADC_DC_CAL,
1230         MIN_CAL_SAMPLES,
1231         PER_MAX_LOG_COUNT,
1232         ath9k_hw_adc_dccal_collect,
1233         ath9k_hw_adc_dccal_calibrate
1234 };
1235 const struct ath9k_percal_data adc_init_dc_cal = {
1236         ADC_DC_INIT_CAL,
1237         MIN_CAL_SAMPLES,
1238         INIT_LOG_COUNT,
1239         ath9k_hw_adc_dccal_collect,
1240         ath9k_hw_adc_dccal_calibrate
1241 };