drivers/net/wireless/ath/ath9k/ar9002_hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar5008_initvals.h"
  19 #include "ar9001_initvals.h"
  20 #include "ar9002_initvals.h"
  21 #include "ar9002_phy.h"
  22
  23 int modparam_force_new_ani;
  24 module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
  25 MODULE_PARM_DESC(nohwcrypt, "Force new ANI for AR5008, AR9001, AR9002");
  26
  27 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
  28
  29 static bool ar9002_hw_macversion_supported(u32 macversion)
  30 {
  31         switch (macversion) {
  32         case AR_SREV_VERSION_5416_PCI:
  33         case AR_SREV_VERSION_5416_PCIE:
  34         case AR_SREV_VERSION_9160:
  35         case AR_SREV_VERSION_9100:
  36         case AR_SREV_VERSION_9280:
  37         case AR_SREV_VERSION_9285:
  38         case AR_SREV_VERSION_9287:
  39         case AR_SREV_VERSION_9271:
  40                 return true;
  41         default:
  42                 break;
  43         }
  44         return false;
  45 }
  46
  47 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
  48 {
  49         if (AR_SREV_9271(ah)) {
  50                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
  51                                ARRAY_SIZE(ar9271Modes_9271), 6);
  52                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
  53                                ARRAY_SIZE(ar9271Common_9271), 2);
  54                 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
  55                                ar9271Common_normal_cck_fir_coeff_9271,
  56                                ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
  57                 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
  58                                ar9271Common_japan_2484_cck_fir_coeff_9271,
  59                                ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
  60                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
  61                                ar9271Modes_9271_1_0_only,
  62                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
  63                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
  64                                ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
  65                 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
  66                                ar9271Modes_high_power_tx_gain_9271,
  67                                ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
  68                 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
  69                                ar9271Modes_normal_power_tx_gain_9271,
  70                                ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
  71                 return;
  72         }
  73
  74         if (AR_SREV_9287_11_OR_LATER(ah)) {
  75                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
  76                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
  77                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
  78                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
  79                 if (ah->config.pcie_clock_req)
  80                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  81                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
  82                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
  83                 else
  84                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  85                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
  86                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
  87                                         2);
  88         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
  89
  90
  91                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
  92                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
  93                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
  94                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
  95
  96                 if (ah->config.pcie_clock_req) {
  97                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  98                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
  99                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 100                 } else {
 101                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 102                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 103                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 104                                   2);
 105                 }
 106         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 107                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 108                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 109                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 110                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 111
 112                 if (ah->config.pcie_clock_req) {
 113                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 114                                ar9280PciePhy_clkreq_off_L1_9280,
 115                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
 116                 } else {
 117                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 118                                ar9280PciePhy_clkreq_always_on_L1_9280,
 119                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 120                 }
 121                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 122                                ar9280Modes_fast_clock_9280_2,
 123                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 124         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 125                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 126                                ARRAY_SIZE(ar5416Modes_9160), 6);
 127                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 128                                ARRAY_SIZE(ar5416Common_9160), 2);
 129                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 130                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 131                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 132                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 133                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 134                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 135                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 136                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 137                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 138                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 139                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 140                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 141                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 142                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 143                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 144                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 145                 if (AR_SREV_9160_11(ah)) {
 146                         INIT_INI_ARRAY(&ah->iniAddac,
 147                                        ar5416Addac_9160_1_1,
 148                                        ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
 149                 } else {
 150                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 151                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 152                 }
 153         } else if (AR_SREV_9100_OR_LATER(ah)) {
 154                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 155                                ARRAY_SIZE(ar5416Modes_9100), 6);
 156                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 157                                ARRAY_SIZE(ar5416Common_9100), 2);
 158                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 159                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 160                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 161                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 162                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 163                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 164                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 165                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 166                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 167                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 168                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 169                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 170                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 171                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 172                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 173                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 174                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 175                                ARRAY_SIZE(ar5416Addac_9100), 2);
 176         } else {
 177                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 178                                ARRAY_SIZE(ar5416Modes), 6);
 179                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 180                                ARRAY_SIZE(ar5416Common), 2);
 181                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 182                                ARRAY_SIZE(ar5416Bank0), 2);
 183                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 184                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 185                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 186                                ARRAY_SIZE(ar5416Bank1), 2);
 187                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 188                                ARRAY_SIZE(ar5416Bank2), 2);
 189                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 190                                ARRAY_SIZE(ar5416Bank3), 3);
 191                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 192                                ARRAY_SIZE(ar5416Bank6), 3);
 193                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 194                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 195                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 196                                ARRAY_SIZE(ar5416Bank7), 2);
 197                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 198                                ARRAY_SIZE(ar5416Addac), 2);
 199         }
 200 }
 201
 202 /* Support for Japan ch.14 (2484) spread */
 203 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
 204 {
 205         if (AR_SREV_9287_11_OR_LATER(ah)) {
 206                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 207                        ar9287Common_normal_cck_fir_coeff_9287_1_1,
 208                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
 209                        2);
 210                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 211                        ar9287Common_japan_2484_cck_fir_coeff_9287_1_1,
 212                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
 213                        2);
 214         }
 215 }
 216
 217 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
 218 {
 219         u32 rxgain_type;
 220
 221         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 222             AR5416_EEP_MINOR_VER_17) {
 223                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 224
 225                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 226                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 227                         ar9280Modes_backoff_13db_rxgain_9280_2,
 228                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 229                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 230                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 231                         ar9280Modes_backoff_23db_rxgain_9280_2,
 232                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 233                 else
 234                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 235                         ar9280Modes_original_rxgain_9280_2,
 236                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 237         } else {
 238                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 239                         ar9280Modes_original_rxgain_9280_2,
 240                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 241         }
 242 }
 243
 244 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
 245 {
 246         u32 txgain_type;
 247
 248         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 249             AR5416_EEP_MINOR_VER_19) {
 250                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 251
 252                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 253                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 254                         ar9280Modes_high_power_tx_gain_9280_2,
 255                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 256                 else
 257                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 258                         ar9280Modes_original_tx_gain_9280_2,
 259                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 260         } else {
 261                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 262                 ar9280Modes_original_tx_gain_9280_2,
 263                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 264         }
 265 }
 266
 267 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
 268 {
 269         if (AR_SREV_9287_11_OR_LATER(ah))
 270                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 271                 ar9287Modes_rx_gain_9287_1_1,
 272                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 273         else if (AR_SREV_9280_20(ah))
 274                 ar9280_20_hw_init_rxgain_ini(ah);
 275
 276         if (AR_SREV_9287_11_OR_LATER(ah)) {
 277                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 278                 ar9287Modes_tx_gain_9287_1_1,
 279                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 280         } else if (AR_SREV_9280_20(ah)) {
 281                 ar9280_20_hw_init_txgain_ini(ah);
 282         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 283                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 284
 285                 /* txgain table */
 286                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 287                         if (AR_SREV_9285E_20(ah)) {
 288                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 289                                 ar9285Modes_XE2_0_high_power,
 290                                 ARRAY_SIZE(
 291                                   ar9285Modes_XE2_0_high_power), 6);
 292                         } else {
 293                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 294                                 ar9285Modes_high_power_tx_gain_9285_1_2,
 295                                 ARRAY_SIZE(
 296                                   ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 297                         }
 298                 } else {
 299                         if (AR_SREV_9285E_20(ah)) {
 300                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 301                                 ar9285Modes_XE2_0_normal_power,
 302                                 ARRAY_SIZE(
 303                                   ar9285Modes_XE2_0_normal_power), 6);
 304                         } else {
 305                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 306                                 ar9285Modes_original_tx_gain_9285_1_2,
 307                                 ARRAY_SIZE(
 308                                   ar9285Modes_original_tx_gain_9285_1_2), 6);
 309                         }
 310                 }
 311         }
 312 }
 313
 314 /*
 315  * Helper for ASPM support.
 316  *
 317  * Disable PLL when in L0s as well as receiver clock when in L1.
 318  * This power saving option must be enabled through the SerDes.
 319  *
 320  * Programming the SerDes must go through the same 288 bit serial shift
 321  * register as the other analog registers.  Hence the 9 writes.
 322  */
 323 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
 324                                          int restore,
 325                                          int power_off)
 326 {
 327         u8 i;
 328         u32 val;
 329
 330         if (ah->is_pciexpress != true)
 331                 return;
 332
 333         /* Do not touch SerDes registers */
 334         if (ah->config.pcie_powersave_enable == 2)
 335                 return;
 336
 337         /* Nothing to do on restore for 11N */
 338         if (!restore) {
 339                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 340                         /*
 341                          * AR9280 2.0 or later chips use SerDes values from the
 342                          * initvals.h initialized depending on chipset during
 343                          * __ath9k_hw_init()
 344                          */
 345                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
 346                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
 347                                           INI_RA(&ah->iniPcieSerdes, i, 1));
 348                         }
 349                 } else {
 350                         ENABLE_REGWRITE_BUFFER(ah);
 351
 352                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 353                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 354
 355                         /* RX shut off when elecidle is asserted */
 356                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
 357                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
 358                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
 359
 360                         /*
 361                          * Ignore ah->ah_config.pcie_clock_req setting for
 362                          * pre-AR9280 11n
 363                          */
 364                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
 365
 366                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 367                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 368                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
 369
 370                         /* Load the new settings */
 371                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 372
 373                         REGWRITE_BUFFER_FLUSH(ah);
 374                         DISABLE_REGWRITE_BUFFER(ah);
 375                 }
 376
 377                 udelay(1000);
 378         }
 379
 380         if (power_off) {
 381                 /* clear bit 19 to disable L1 */
 382                 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 383
 384                 val = REG_READ(ah, AR_WA);
 385
 386                 /*
 387                  * Set PCIe workaround bits
 388                  * In AR9280 and AR9285, bit 14 in WA register (disable L1)
 389                  * should only  be set when device enters D3 and be
 390                  * cleared when device comes back to D0.
 391                  */
 392                 if (ah->config.pcie_waen) {
 393                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
 394                                 val |= AR_WA_D3_L1_DISABLE;
 395                 } else {
 396                         if (((AR_SREV_9285(ah) ||
 397                               AR_SREV_9271(ah) ||
 398                               AR_SREV_9287(ah)) &&
 399                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
 400                             (AR_SREV_9280(ah) &&
 401                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
 402                                 val |= AR_WA_D3_L1_DISABLE;
 403                         }
 404                 }
 405
 406                 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
 407                         /*
 408                          * Disable bit 6 and 7 before entering D3 to
 409                          * prevent system hang.
 410                          */
 411                         val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
 412                 }
 413
 414                 if (AR_SREV_9285E_20(ah))
 415                         val |= AR_WA_BIT23;
 416
 417                 REG_WRITE(ah, AR_WA, val);
 418         } else {
 419                 if (ah->config.pcie_waen) {
 420                         val = ah->config.pcie_waen;
 421                         if (!power_off)
 422                                 val &= (~AR_WA_D3_L1_DISABLE);
 423                 } else {
 424                         if (AR_SREV_9285(ah) ||
 425                             AR_SREV_9271(ah) ||
 426                             AR_SREV_9287(ah)) {
 427                                 val = AR9285_WA_DEFAULT;
 428                                 if (!power_off)
 429                                         val &= (~AR_WA_D3_L1_DISABLE);
 430                         }
 431                         else if (AR_SREV_9280(ah)) {
 432                                 /*
 433                                  * For AR9280 chips, bit 22 of 0x4004
 434                                  * needs to be set.
 435                                  */
 436                                 val = AR9280_WA_DEFAULT;
 437                                 if (!power_off)
 438                                         val &= (~AR_WA_D3_L1_DISABLE);
 439                         } else {
 440                                 val = AR_WA_DEFAULT;
 441                         }
 442                 }
 443
 444                 /* WAR for ASPM system hang */
 445                 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
 446                         val |= (AR_WA_BIT6 | AR_WA_BIT7);
 447                 }
 448
 449                 if (AR_SREV_9285E_20(ah))
 450                         val |= AR_WA_BIT23;
 451
 452                 REG_WRITE(ah, AR_WA, val);
 453
 454                 /* set bit 19 to allow forcing of pcie core into L1 state */
 455                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 456         }
 457 }
 458
 459 static int ar9002_hw_get_radiorev(struct ath_hw *ah)
 460 {
 461         u32 val;
 462         int i;
 463
 464         ENABLE_REGWRITE_BUFFER(ah);
 465
 466         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 467         for (i = 0; i < 8; i++)
 468                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 469
 470         REGWRITE_BUFFER_FLUSH(ah);
 471         DISABLE_REGWRITE_BUFFER(ah);
 472
 473         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 474         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 475
 476         return ath9k_hw_reverse_bits(val, 8);
 477 }
 478
 479 int ar9002_hw_rf_claim(struct ath_hw *ah)
 480 {
 481         u32 val;
 482
 483         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 484
 485         val = ar9002_hw_get_radiorev(ah);
 486         switch (val & AR_RADIO_SREV_MAJOR) {
 487         case 0:
 488                 val = AR_RAD5133_SREV_MAJOR;
 489                 break;
 490         case AR_RAD5133_SREV_MAJOR:
 491         case AR_RAD5122_SREV_MAJOR:
 492         case AR_RAD2133_SREV_MAJOR:
 493         case AR_RAD2122_SREV_MAJOR:
 494                 break;
 495         default:
 496                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 497                           "Radio Chip Rev 0x%02X not supported\n",
 498                           val & AR_RADIO_SREV_MAJOR);
 499                 return -EOPNOTSUPP;
 500         }
 501
 502         ah->hw_version.analog5GhzRev = val;
 503
 504         return 0;
 505 }
 506
 507 void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
 508 {
 509         if (AR_SREV_9287_13_OR_LATER(ah)) {
 510                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 511                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
 512                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
 513                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 514                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 515                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 516                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 517         }
 518 }
 519
 520 /*
 521  * If Async FIFO is enabled, the following counters change as MAC now runs
 522  * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
 523  *
 524  * The values below tested for ht40 2 chain.
 525  * Overwrite the delay/timeouts initialized in process ini.
 526  */
 527 void ar9002_hw_update_async_fifo(struct ath_hw *ah)
 528 {
 529         if (AR_SREV_9287_13_OR_LATER(ah)) {
 530                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
 531                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
 532                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
 533                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
 534                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
 535                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
 536
 537                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
 538                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
 539
 540                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
 541                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
 542                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
 543                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
 544         }
 545 }
 546
 547 /*
 548  * We don't enable WEP aggregation on mac80211 but we keep this
 549  * around for HAL unification purposes.
 550  */
 551 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
 552 {
 553         if (AR_SREV_9287_13_OR_LATER(ah)) {
 554                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
 555                             AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
 556         }
 557 }
 558
 559 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
 560 void ar9002_hw_attach_ops(struct ath_hw *ah)
 561 {
 562         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 563         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 564
 565         priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
 566         priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
 567         priv_ops->macversion_supported = ar9002_hw_macversion_supported;
 568
 569         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
 570
 571         ar5008_hw_attach_phy_ops(ah);
 572         if (AR_SREV_9280_20_OR_LATER(ah))
 573                 ar9002_hw_attach_phy_ops(ah);
 574
 575         ar9002_hw_attach_calib_ops(ah);
 576         ar9002_hw_attach_mac_ops(ah);
 577
 578         if (modparam_force_new_ani)
 579                 ath9k_hw_attach_ani_ops_new(ah);
 580         else
 581                 ath9k_hw_attach_ani_ops_old(ah);
 582 }
 583
 584 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
 585 {
 586         u32 modesIndex;
 587         int i;
 588
 589         switch (chan->chanmode) {
 590         case CHANNEL_A:
 591         case CHANNEL_A_HT20:
 592                 modesIndex = 1;
 593                 break;
 594         case CHANNEL_A_HT40PLUS:
 595         case CHANNEL_A_HT40MINUS:
 596                 modesIndex = 2;
 597                 break;
 598         case CHANNEL_G:
 599         case CHANNEL_G_HT20:
 600         case CHANNEL_B:
 601                 modesIndex = 4;
 602                 break;
 603         case CHANNEL_G_HT40PLUS:
 604         case CHANNEL_G_HT40MINUS:
 605                 modesIndex = 3;
 606                 break;
 607
 608         default:
 609                 return;
 610         }
 611
 612         ENABLE_REGWRITE_BUFFER(ah);
 613
 614         for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
 615                 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
 616                 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
 617                 u32 val_orig;
 618
 619                 if (reg == AR_PHY_CCK_DETECT) {
 620                         val_orig = REG_READ(ah, reg);
 621                         val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
 622                         val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
 623
 624                         REG_WRITE(ah, reg, val|val_orig);
 625                 } else
 626                         REG_WRITE(ah, reg, val);
 627         }
 628
 629         REGWRITE_BUFFER_FLUSH(ah);
 630         DISABLE_REGWRITE_BUFFER(ah);
 631
 632 }