drivers/net/wireless/ath/ath9k/ar5008_phy.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "hw-ops.h"
  19 #include "../regd.h"
  20 #include "ar9002_phy.h"
  21
  22 /* All code below is for AR5008, AR9001, AR9002 */
  23
  24 static const int firstep_table[] =
  25 /* level:  0   1   2   3   4   5   6   7   8  */
  26         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  27
  28 static const int cycpwrThr1_table[] =
  29 /* level:  0   1   2   3   4   5   6   7   8  */
  30         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  31
  32 /*
  33  * register values to turn OFDM weak signal detection OFF
  34  */
  35 static const int m1ThreshLow_off = 127;
  36 static const int m2ThreshLow_off = 127;
  37 static const int m1Thresh_off = 127;
  38 static const int m2Thresh_off = 127;
  39 static const int m2CountThr_off =  31;
  40 static const int m2CountThrLow_off =  63;
  41 static const int m1ThreshLowExt_off = 127;
  42 static const int m2ThreshLowExt_off = 127;
  43 static const int m1ThreshExt_off = 127;
  44 static const int m2ThreshExt_off = 127;
  45
  46
  47 /**
  48  * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
  49  * @rfbuf:
  50  * @reg32:
  51  * @numBits:
  52  * @firstBit:
  53  * @column:
  54  *
  55  * Performs analog "swizzling" of parameters into their location.
  56  * Used on external AR2133/AR5133 radios.
  57  */
  58 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
  59                                            u32 numBits, u32 firstBit,
  60                                            u32 column)
  61 {
  62         u32 tmp32, mask, arrayEntry, lastBit;
  63         int32_t bitPosition, bitsLeft;
  64
  65         tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
  66         arrayEntry = (firstBit - 1) / 8;
  67         bitPosition = (firstBit - 1) % 8;
  68         bitsLeft = numBits;
  69         while (bitsLeft > 0) {
  70                 lastBit = (bitPosition + bitsLeft > 8) ?
  71                     8 : bitPosition + bitsLeft;
  72                 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
  73                     (column * 8);
  74                 rfBuf[arrayEntry] &= ~mask;
  75                 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
  76                                       (column * 8)) & mask;
  77                 bitsLeft -= 8 - bitPosition;
  78                 tmp32 = tmp32 >> (8 - bitPosition);
  79                 bitPosition = 0;
  80                 arrayEntry++;
  81         }
  82 }
  83
  84 /*
  85  * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
  86  * rf_pwd_icsyndiv.
  87  *
  88  * Theoretical Rules:
  89  *   if 2 GHz band
  90  *      if forceBiasAuto
  91  *         if synth_freq < 2412
  92  *            bias = 0
  93  *         else if 2412 <= synth_freq <= 2422
  94  *            bias = 1
  95  *         else // synth_freq > 2422
  96  *            bias = 2
  97  *      else if forceBias > 0
  98  *         bias = forceBias & 7
  99  *      else
 100  *         no change, use value from ini file
 101  *   else
 102  *      no change, invalid band
 103  *
 104  *  1st Mod:
 105  *    2422 also uses value of 2
 106  *    <approved>
 107  *
 108  *  2nd Mod:
 109  *    Less than 2412 uses value of 0, 2412 and above uses value of 2
 110  */
 111 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
 112 {
 113         struct ath_common *common = ath9k_hw_common(ah);
 114         u32 tmp_reg;
 115         int reg_writes = 0;
 116         u32 new_bias = 0;
 117
 118         if (!AR_SREV_5416(ah) || synth_freq >= 3000)
 119                 return;
 120
 121         BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 122
 123         if (synth_freq < 2412)
 124                 new_bias = 0;
 125         else if (synth_freq < 2422)
 126                 new_bias = 1;
 127         else
 128                 new_bias = 2;
 129
 130         /* pre-reverse this field */
 131         tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
 132
 133         ath_print(common, ATH_DBG_CONFIG,
 134                   "Force rf_pwd_icsyndiv to %1d on %4d\n",
 135                   new_bias, synth_freq);
 136
 137         /* swizzle rf_pwd_icsyndiv */
 138         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
 139
 140         /* write Bank 6 with new params */
 141         REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
 142 }
 143
 144 /**
 145  * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
 146  * @ah: atheros hardware stucture
 147  * @chan:
 148  *
 149  * For the external AR2133/AR5133 radios, takes the MHz channel value and set
 150  * the channel value. Assumes writes enabled to analog bus and bank6 register
 151  * cache in ah->analogBank6Data.
 152  */
 153 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
 154 {
 155         struct ath_common *common = ath9k_hw_common(ah);
 156         u32 channelSel = 0;
 157         u32 bModeSynth = 0;
 158         u32 aModeRefSel = 0;
 159         u32 reg32 = 0;
 160         u16 freq;
 161         struct chan_centers centers;
 162
 163         ath9k_hw_get_channel_centers(ah, chan, &centers);
 164         freq = centers.synth_center;
 165
 166         if (freq < 4800) {
 167                 u32 txctl;
 168
 169                 if (((freq - 2192) % 5) == 0) {
 170                         channelSel = ((freq - 672) * 2 - 3040) / 10;
 171                         bModeSynth = 0;
 172                 } else if (((freq - 2224) % 5) == 0) {
 173                         channelSel = ((freq - 704) * 2 - 3040) / 10;
 174                         bModeSynth = 1;
 175                 } else {
 176                         ath_print(common, ATH_DBG_FATAL,
 177                                   "Invalid channel %u MHz\n", freq);
 178                         return -EINVAL;
 179                 }
 180
 181                 channelSel = (channelSel << 2) & 0xff;
 182                 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
 183
 184                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
 185                 if (freq == 2484) {
 186
 187                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 188                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
 189                 } else {
 190                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 191                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
 192                 }
 193
 194         } else if ((freq % 20) == 0 && freq >= 5120) {
 195                 channelSel =
 196                     ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
 197                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
 198         } else if ((freq % 10) == 0) {
 199                 channelSel =
 200                     ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
 201                 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
 202                         aModeRefSel = ath9k_hw_reverse_bits(2, 2);
 203                 else
 204                         aModeRefSel = ath9k_hw_reverse_bits(1, 2);
 205         } else if ((freq % 5) == 0) {
 206                 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
 207                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
 208         } else {
 209                 ath_print(common, ATH_DBG_FATAL,
 210                           "Invalid channel %u MHz\n", freq);
 211                 return -EINVAL;
 212         }
 213
 214         ar5008_hw_force_bias(ah, freq);
 215
 216         reg32 =
 217             (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
 218             (1 << 5) | 0x1;
 219
 220         REG_WRITE(ah, AR_PHY(0x37), reg32);
 221
 222         ah->curchan = chan;
 223         ah->curchan_rad_index = -1;
 224
 225         return 0;
 226 }
 227
 228 /**
 229  * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
 230  * @ah: atheros hardware structure
 231  * @chan:
 232  *
 233  * For non single-chip solutions. Converts to baseband spur frequency given the
 234  * input channel frequency and compute register settings below.
 235  */
 236 static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
 237                                     struct ath9k_channel *chan)
 238 {
 239         int bb_spur = AR_NO_SPUR;
 240         int bin, cur_bin;
 241         int spur_freq_sd;
 242         int spur_delta_phase;
 243         int denominator;
 244         int upper, lower, cur_vit_mask;
 245         int tmp, new;
 246         int i;
 247         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
 248                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
 249         };
 250         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
 251                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
 252         };
 253         int inc[4] = { 0, 100, 0, 0 };
 254
 255         int8_t mask_m[123];
 256         int8_t mask_p[123];
 257         int8_t mask_amt;
 258         int tmp_mask;
 259         int cur_bb_spur;
 260         bool is2GHz = IS_CHAN_2GHZ(chan);
 261
 262         memset(&mask_m, 0, sizeof(int8_t) * 123);
 263         memset(&mask_p, 0, sizeof(int8_t) * 123);
 264
 265         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 266                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
 267                 if (AR_NO_SPUR == cur_bb_spur)
 268                         break;
 269                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
 270                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
 271                         bb_spur = cur_bb_spur;
 272                         break;
 273                 }
 274         }
 275
 276         if (AR_NO_SPUR == bb_spur)
 277                 return;
 278
 279         bin = bb_spur * 32;
 280
 281         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
 282         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
 283                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
 284                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
 285                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
 286
 287         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
 288
 289         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
 290                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
 291                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
 292                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
 293                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
 294         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
 295
 296         spur_delta_phase = ((bb_spur * 524288) / 100) &
 297                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
 298
 299         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
 300         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
 301
 302         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
 303                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
 304                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
 305         REG_WRITE(ah, AR_PHY_TIMING11, new);
 306
 307         cur_bin = -6000;
 308         upper = bin + 100;
 309         lower = bin - 100;
 310
 311         for (i = 0; i < 4; i++) {
 312                 int pilot_mask = 0;
 313                 int chan_mask = 0;
 314                 int bp = 0;
 315                 for (bp = 0; bp < 30; bp++) {
 316                         if ((cur_bin > lower) && (cur_bin < upper)) {
 317                                 pilot_mask = pilot_mask | 0x1 << bp;
 318                                 chan_mask = chan_mask | 0x1 << bp;
 319                         }
 320                         cur_bin += 100;
 321                 }
 322                 cur_bin += inc[i];
 323                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
 324                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
 325         }
 326
 327         cur_vit_mask = 6100;
 328         upper = bin + 120;
 329         lower = bin - 120;
 330
 331         for (i = 0; i < 123; i++) {
 332                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
 333
 334                         /* workaround for gcc bug #37014 */
 335                         volatile int tmp_v = abs(cur_vit_mask - bin);
 336
 337                         if (tmp_v < 75)
 338                                 mask_amt = 1;
 339                         else
 340                                 mask_amt = 0;
 341                         if (cur_vit_mask < 0)
 342                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
 343                         else
 344                                 mask_p[cur_vit_mask / 100] = mask_amt;
 345                 }
 346                 cur_vit_mask -= 100;
 347         }
 348
 349         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
 350                 | (mask_m[48] << 26) | (mask_m[49] << 24)
 351                 | (mask_m[50] << 22) | (mask_m[51] << 20)
 352                 | (mask_m[52] << 18) | (mask_m[53] << 16)
 353                 | (mask_m[54] << 14) | (mask_m[55] << 12)
 354                 | (mask_m[56] << 10) | (mask_m[57] << 8)
 355                 | (mask_m[58] << 6) | (mask_m[59] << 4)
 356                 | (mask_m[60] << 2) | (mask_m[61] << 0);
 357         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
 358         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
 359
 360         tmp_mask = (mask_m[31] << 28)
 361                 | (mask_m[32] << 26) | (mask_m[33] << 24)
 362                 | (mask_m[34] << 22) | (mask_m[35] << 20)
 363                 | (mask_m[36] << 18) | (mask_m[37] << 16)
 364                 | (mask_m[48] << 14) | (mask_m[39] << 12)
 365                 | (mask_m[40] << 10) | (mask_m[41] << 8)
 366                 | (mask_m[42] << 6) | (mask_m[43] << 4)
 367                 | (mask_m[44] << 2) | (mask_m[45] << 0);
 368         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
 369         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
 370
 371         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
 372                 | (mask_m[18] << 26) | (mask_m[18] << 24)
 373                 | (mask_m[20] << 22) | (mask_m[20] << 20)
 374                 | (mask_m[22] << 18) | (mask_m[22] << 16)
 375                 | (mask_m[24] << 14) | (mask_m[24] << 12)
 376                 | (mask_m[25] << 10) | (mask_m[26] << 8)
 377                 | (mask_m[27] << 6) | (mask_m[28] << 4)
 378                 | (mask_m[29] << 2) | (mask_m[30] << 0);
 379         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
 380         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
 381
 382         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
 383                 | (mask_m[2] << 26) | (mask_m[3] << 24)
 384                 | (mask_m[4] << 22) | (mask_m[5] << 20)
 385                 | (mask_m[6] << 18) | (mask_m[7] << 16)
 386                 | (mask_m[8] << 14) | (mask_m[9] << 12)
 387                 | (mask_m[10] << 10) | (mask_m[11] << 8)
 388                 | (mask_m[12] << 6) | (mask_m[13] << 4)
 389                 | (mask_m[14] << 2) | (mask_m[15] << 0);
 390         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
 391         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
 392
 393         tmp_mask = (mask_p[15] << 28)
 394                 | (mask_p[14] << 26) | (mask_p[13] << 24)
 395                 | (mask_p[12] << 22) | (mask_p[11] << 20)
 396                 | (mask_p[10] << 18) | (mask_p[9] << 16)
 397                 | (mask_p[8] << 14) | (mask_p[7] << 12)
 398                 | (mask_p[6] << 10) | (mask_p[5] << 8)
 399                 | (mask_p[4] << 6) | (mask_p[3] << 4)
 400                 | (mask_p[2] << 2) | (mask_p[1] << 0);
 401         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
 402         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
 403
 404         tmp_mask = (mask_p[30] << 28)
 405                 | (mask_p[29] << 26) | (mask_p[28] << 24)
 406                 | (mask_p[27] << 22) | (mask_p[26] << 20)
 407                 | (mask_p[25] << 18) | (mask_p[24] << 16)
 408                 | (mask_p[23] << 14) | (mask_p[22] << 12)
 409                 | (mask_p[21] << 10) | (mask_p[20] << 8)
 410                 | (mask_p[19] << 6) | (mask_p[18] << 4)
 411                 | (mask_p[17] << 2) | (mask_p[16] << 0);
 412         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
 413         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
 414
 415         tmp_mask = (mask_p[45] << 28)
 416                 | (mask_p[44] << 26) | (mask_p[43] << 24)
 417                 | (mask_p[42] << 22) | (mask_p[41] << 20)
 418                 | (mask_p[40] << 18) | (mask_p[39] << 16)
 419                 | (mask_p[38] << 14) | (mask_p[37] << 12)
 420                 | (mask_p[36] << 10) | (mask_p[35] << 8)
 421                 | (mask_p[34] << 6) | (mask_p[33] << 4)
 422                 | (mask_p[32] << 2) | (mask_p[31] << 0);
 423         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
 424         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
 425
 426         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
 427                 | (mask_p[59] << 26) | (mask_p[58] << 24)
 428                 | (mask_p[57] << 22) | (mask_p[56] << 20)
 429                 | (mask_p[55] << 18) | (mask_p[54] << 16)
 430                 | (mask_p[53] << 14) | (mask_p[52] << 12)
 431                 | (mask_p[51] << 10) | (mask_p[50] << 8)
 432                 | (mask_p[49] << 6) | (mask_p[48] << 4)
 433                 | (mask_p[47] << 2) | (mask_p[46] << 0);
 434         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
 435         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
 436 }
 437
 438 /**
 439  * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
 440  * @ah: atheros hardware structure
 441  *
 442  * Only required for older devices with external AR2133/AR5133 radios.
 443  */
 444 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
 445 {
 446 #define ATH_ALLOC_BANK(bank, size) do { \
 447                 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
 448                 if (!bank) { \
 449                         ath_print(common, ATH_DBG_FATAL, \
 450                                   "Cannot allocate RF banks\n"); \
 451                         return -ENOMEM; \
 452                 } \
 453         } while (0);
 454
 455         struct ath_common *common = ath9k_hw_common(ah);
 456
 457         BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 458
 459         ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
 460         ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
 461         ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
 462         ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
 463         ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
 464         ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
 465         ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
 466         ATH_ALLOC_BANK(ah->addac5416_21,
 467                        ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
 468         ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
 469
 470         return 0;
 471 #undef ATH_ALLOC_BANK
 472 }
 473
 474
 475 /**
 476  * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
 477  * @ah: atheros hardware struture
 478  * For the external AR2133/AR5133 radios banks.
 479  */
 480 static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
 481 {
 482 #define ATH_FREE_BANK(bank) do { \
 483                 kfree(bank); \
 484                 bank = NULL; \
 485         } while (0);
 486
 487         BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 488
 489         ATH_FREE_BANK(ah->analogBank0Data);
 490         ATH_FREE_BANK(ah->analogBank1Data);
 491         ATH_FREE_BANK(ah->analogBank2Data);
 492         ATH_FREE_BANK(ah->analogBank3Data);
 493         ATH_FREE_BANK(ah->analogBank6Data);
 494         ATH_FREE_BANK(ah->analogBank6TPCData);
 495         ATH_FREE_BANK(ah->analogBank7Data);
 496         ATH_FREE_BANK(ah->addac5416_21);
 497         ATH_FREE_BANK(ah->bank6Temp);
 498
 499 #undef ATH_FREE_BANK
 500 }
 501
 502 /* *
 503  * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
 504  * @ah: atheros hardware structure
 505  * @chan:
 506  * @modesIndex:
 507  *
 508  * Used for the external AR2133/AR5133 radios.
 509  *
 510  * Reads the EEPROM header info from the device structure and programs
 511  * all rf registers. This routine requires access to the analog
 512  * rf device. This is not required for single-chip devices.
 513  */
 514 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
 515                                   struct ath9k_channel *chan,
 516                                   u16 modesIndex)
 517 {
 518         u32 eepMinorRev;
 519         u32 ob5GHz = 0, db5GHz = 0;
 520         u32 ob2GHz = 0, db2GHz = 0;
 521         int regWrites = 0;
 522
 523         /*
 524          * Software does not need to program bank data
 525          * for single chip devices, that is AR9280 or anything
 526          * after that.
 527          */
 528         if (AR_SREV_9280_20_OR_LATER(ah))
 529                 return true;
 530
 531         /* Setup rf parameters */
 532         eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
 533
 534         /* Setup Bank 0 Write */
 535         RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
 536
 537         /* Setup Bank 1 Write */
 538         RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
 539
 540         /* Setup Bank 2 Write */
 541         RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
 542
 543         /* Setup Bank 6 Write */
 544         RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
 545                       modesIndex);
 546         {
 547                 int i;
 548                 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
 549                         ah->analogBank6Data[i] =
 550                             INI_RA(&ah->iniBank6TPC, i, modesIndex);
 551                 }
 552         }
 553
 554         /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
 555         if (eepMinorRev >= 2) {
 556                 if (IS_CHAN_2GHZ(chan)) {
 557                         ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
 558                         db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
 559                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
 560                                                        ob2GHz, 3, 197, 0);
 561                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
 562                                                        db2GHz, 3, 194, 0);
 563                 } else {
 564                         ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
 565                         db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
 566                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
 567                                                        ob5GHz, 3, 203, 0);
 568                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
 569                                                        db5GHz, 3, 200, 0);
 570                 }
 571         }
 572
 573         /* Setup Bank 7 Setup */
 574         RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
 575
 576         /* Write Analog registers */
 577         REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
 578                            regWrites);
 579         REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
 580                            regWrites);
 581         REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
 582                            regWrites);
 583         REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
 584                            regWrites);
 585         REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
 586                            regWrites);
 587         REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
 588                            regWrites);
 589
 590         return true;
 591 }
 592
 593 static void ar5008_hw_init_bb(struct ath_hw *ah,
 594                               struct ath9k_channel *chan)
 595 {
 596         u32 synthDelay;
 597
 598         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 599         if (IS_CHAN_B(chan))
 600                 synthDelay = (4 * synthDelay) / 22;
 601         else
 602                 synthDelay /= 10;
 603
 604         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 605
 606         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 607 }
 608
 609 static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
 610 {
 611         int rx_chainmask, tx_chainmask;
 612
 613         rx_chainmask = ah->rxchainmask;
 614         tx_chainmask = ah->txchainmask;
 615
 616         ENABLE_REGWRITE_BUFFER(ah);
 617
 618         switch (rx_chainmask) {
 619         case 0x5:
 620                 DISABLE_REGWRITE_BUFFER(ah);
 621                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 622                             AR_PHY_SWAP_ALT_CHAIN);
 623                 ENABLE_REGWRITE_BUFFER(ah);
 624         case 0x3:
 625                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
 626                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
 627                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
 628                         break;
 629                 }
 630         case 0x1:
 631         case 0x2:
 632         case 0x7:
 633                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
 634                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
 635                 break;
 636         default:
 637                 break;
 638         }
 639
 640         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
 641
 642         REGWRITE_BUFFER_FLUSH(ah);
 643         DISABLE_REGWRITE_BUFFER(ah);
 644
 645         if (tx_chainmask == 0x5) {
 646                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 647                             AR_PHY_SWAP_ALT_CHAIN);
 648         }
 649         if (AR_SREV_9100(ah))
 650                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
 651                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
 652 }
 653
 654 static void ar5008_hw_override_ini(struct ath_hw *ah,
 655                                    struct ath9k_channel *chan)
 656 {
 657         u32 val;
 658
 659         /*
 660          * Set the RX_ABORT and RX_DIS and clear if off only after
 661          * RXE is set for MAC. This prevents frames with corrupted
 662          * descriptor status.
 663          */
 664         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 665
 666         if (AR_SREV_9280_20_OR_LATER(ah)) {
 667                 val = REG_READ(ah, AR_PCU_MISC_MODE2);
 668
 669                 if (!AR_SREV_9271(ah))
 670                         val &= ~AR_PCU_MISC_MODE2_HWWAR1;
 671
 672                 if (AR_SREV_9287_11_OR_LATER(ah))
 673                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
 674
 675                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
 676         }
 677
 678         if (!AR_SREV_5416_20_OR_LATER(ah) ||
 679             AR_SREV_9280_20_OR_LATER(ah))
 680                 return;
 681         /*
 682          * Disable BB clock gating
 683          * Necessary to avoid issues on AR5416 2.0
 684          */
 685         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
 686
 687         /*
 688          * Disable RIFS search on some chips to avoid baseband
 689          * hang issues.
 690          */
 691         if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
 692                 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
 693                 val &= ~AR_PHY_RIFS_INIT_DELAY;
 694                 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
 695         }
 696 }
 697
 698 static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
 699                                        struct ath9k_channel *chan)
 700 {
 701         u32 phymode;
 702         u32 enableDacFifo = 0;
 703
 704         if (AR_SREV_9285_12_OR_LATER(ah))
 705                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
 706                                          AR_PHY_FC_ENABLE_DAC_FIFO);
 707
 708         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
 709                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
 710
 711         if (IS_CHAN_HT40(chan)) {
 712                 phymode |= AR_PHY_FC_DYN2040_EN;
 713
 714                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 715                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 716                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
 717
 718         }
 719         REG_WRITE(ah, AR_PHY_TURBO, phymode);
 720
 721         ath9k_hw_set11nmac2040(ah);
 722
 723         ENABLE_REGWRITE_BUFFER(ah);
 724
 725         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 726         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 727
 728         REGWRITE_BUFFER_FLUSH(ah);
 729         DISABLE_REGWRITE_BUFFER(ah);
 730 }
 731
 732
 733 static int ar5008_hw_process_ini(struct ath_hw *ah,
 734                                  struct ath9k_channel *chan)
 735 {
 736         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 737         int i, regWrites = 0;
 738         struct ieee80211_channel *channel = chan->chan;
 739         u32 modesIndex, freqIndex;
 740
 741         switch (chan->chanmode) {
 742         case CHANNEL_A:
 743         case CHANNEL_A_HT20:
 744                 modesIndex = 1;
 745                 freqIndex = 1;
 746                 break;
 747         case CHANNEL_A_HT40PLUS:
 748         case CHANNEL_A_HT40MINUS:
 749                 modesIndex = 2;
 750                 freqIndex = 1;
 751                 break;
 752         case CHANNEL_G:
 753         case CHANNEL_G_HT20:
 754         case CHANNEL_B:
 755                 modesIndex = 4;
 756                 freqIndex = 2;
 757                 break;
 758         case CHANNEL_G_HT40PLUS:
 759         case CHANNEL_G_HT40MINUS:
 760                 modesIndex = 3;
 761                 freqIndex = 2;
 762                 break;
 763
 764         default:
 765                 return -EINVAL;
 766         }
 767
 768         /*
 769          * Set correct baseband to analog shift setting to
 770          * access analog chips.
 771          */
 772         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 773
 774         /* Write ADDAC shifts */
 775         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
 776         ah->eep_ops->set_addac(ah, chan);
 777
 778         if (AR_SREV_5416_22_OR_LATER(ah)) {
 779                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
 780         } else {
 781                 struct ar5416IniArray temp;
 782                 u32 addacSize =
 783                         sizeof(u32) * ah->iniAddac.ia_rows *
 784                         ah->iniAddac.ia_columns;
 785
 786                 /* For AR5416 2.0/2.1 */
 787                 memcpy(ah->addac5416_21,
 788                        ah->iniAddac.ia_array, addacSize);
 789
 790                 /* override CLKDRV value at [row, column] = [31, 1] */
 791                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
 792
 793                 temp.ia_array = ah->addac5416_21;
 794                 temp.ia_columns = ah->iniAddac.ia_columns;
 795                 temp.ia_rows = ah->iniAddac.ia_rows;
 796                 REG_WRITE_ARRAY(&temp, 1, regWrites);
 797         }
 798
 799         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
 800
 801         ENABLE_REGWRITE_BUFFER(ah);
 802
 803         for (i = 0; i < ah->iniModes.ia_rows; i++) {
 804                 u32 reg = INI_RA(&ah->iniModes, i, 0);
 805                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
 806
 807                 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
 808                         val &= ~AR_AN_TOP2_PWDCLKIND;
 809
 810                 REG_WRITE(ah, reg, val);
 811
 812                 if (reg >= 0x7800 && reg < 0x78a0
 813                     && ah->config.analog_shiftreg) {
 814                         udelay(100);
 815                 }
 816
 817                 DO_DELAY(regWrites);
 818         }
 819
 820         REGWRITE_BUFFER_FLUSH(ah);
 821         DISABLE_REGWRITE_BUFFER(ah);
 822
 823         if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
 824                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
 825
 826         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
 827             AR_SREV_9287_11_OR_LATER(ah))
 828                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 829
 830         if (AR_SREV_9271_10(ah))
 831                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
 832                                 modesIndex, regWrites);
 833
 834         ENABLE_REGWRITE_BUFFER(ah);
 835
 836         /* Write common array parameters */
 837         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
 838                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
 839                 u32 val = INI_RA(&ah->iniCommon, i, 1);
 840
 841                 REG_WRITE(ah, reg, val);
 842
 843                 if (reg >= 0x7800 && reg < 0x78a0
 844                     && ah->config.analog_shiftreg) {
 845                         udelay(100);
 846                 }
 847
 848                 DO_DELAY(regWrites);
 849         }
 850
 851         REGWRITE_BUFFER_FLUSH(ah);
 852         DISABLE_REGWRITE_BUFFER(ah);
 853
 854         if (AR_SREV_9271(ah)) {
 855                 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
 856                         REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
 857                                         modesIndex, regWrites);
 858                 else
 859                         REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
 860                                         modesIndex, regWrites);
 861         }
 862
 863         REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
 864
 865         if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
 866                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
 867                                 regWrites);
 868         }
 869
 870         ar5008_hw_override_ini(ah, chan);
 871         ar5008_hw_set_channel_regs(ah, chan);
 872         ar5008_hw_init_chain_masks(ah);
 873         ath9k_olc_init(ah);
 874
 875         /* Set TX power */
 876         ah->eep_ops->set_txpower(ah, chan,
 877                                  ath9k_regd_get_ctl(regulatory, chan),
 878                                  channel->max_antenna_gain * 2,
 879                                  channel->max_power * 2,
 880                                  min((u32) MAX_RATE_POWER,
 881                                  (u32) regulatory->power_limit));
 882
 883         /* Write analog registers */
 884         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
 885                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 886                           "ar5416SetRfRegs failed\n");
 887                 return -EIO;
 888         }
 889
 890         return 0;
 891 }
 892
 893 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
 894 {
 895         u32 rfMode = 0;
 896
 897         if (chan == NULL)
 898                 return;
 899
 900         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 901                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 902
 903         if (!AR_SREV_9280_20_OR_LATER(ah))
 904                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
 905                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
 906
 907         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 908                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 909
 910         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 911 }
 912
 913 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
 914 {
 915         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 916 }
 917
 918 static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
 919                                       struct ath9k_channel *chan)
 920 {
 921         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 922         u32 clockMhzScaled = 0x64000000;
 923         struct chan_centers centers;
 924
 925         if (IS_CHAN_HALF_RATE(chan))
 926                 clockMhzScaled = clockMhzScaled >> 1;
 927         else if (IS_CHAN_QUARTER_RATE(chan))
 928                 clockMhzScaled = clockMhzScaled >> 2;
 929
 930         ath9k_hw_get_channel_centers(ah, chan, &centers);
 931         coef_scaled = clockMhzScaled / centers.synth_center;
 932
 933         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 934                                       &ds_coef_exp);
 935
 936         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 937                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 938         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 939                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 940
 941         coef_scaled = (9 * coef_scaled) / 10;
 942
 943         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 944                                       &ds_coef_exp);
 945
 946         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
 947                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
 948         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
 949                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
 950 }
 951
 952 static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
 953 {
 954         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 955         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 956                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 957 }
 958
 959 static void ar5008_hw_rfbus_done(struct ath_hw *ah)
 960 {
 961         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 962         if (IS_CHAN_B(ah->curchan))
 963                 synthDelay = (4 * synthDelay) / 22;
 964         else
 965                 synthDelay /= 10;
 966
 967         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 968
 969         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 970 }
 971
 972 static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
 973 {
 974         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
 975                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
 976
 977         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
 978                     AR_GPIO_INPUT_MUX2_RFSILENT);
 979
 980         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
 981         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
 982 }
 983
 984 static void ar5008_restore_chainmask(struct ath_hw *ah)
 985 {
 986         int rx_chainmask = ah->rxchainmask;
 987
 988         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
 989                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
 990                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
 991         }
 992 }
 993
 994 static void ar5008_set_diversity(struct ath_hw *ah, bool value)
 995 {
 996         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
 997         if (value)
 998                 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 999         else
1000                 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1001         REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1002 }
1003
1004 static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
1005                                          struct ath9k_channel *chan)
1006 {
1007         if (chan && IS_CHAN_5GHZ(chan))
1008                 return 0x1450;
1009         return 0x1458;
1010 }
1011
1012 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
1013                                          struct ath9k_channel *chan)
1014 {
1015         u32 pll;
1016
1017         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1018
1019         if (chan && IS_CHAN_HALF_RATE(chan))
1020                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1021         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1022                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1023
1024         if (chan && IS_CHAN_5GHZ(chan))
1025                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1026         else
1027                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1028
1029         return pll;
1030 }
1031
1032 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
1033                                          struct ath9k_channel *chan)
1034 {
1035         u32 pll;
1036
1037         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1038
1039         if (chan && IS_CHAN_HALF_RATE(chan))
1040                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1041         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1042                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1043
1044         if (chan && IS_CHAN_5GHZ(chan))
1045                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1046         else
1047                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1048
1049         return pll;
1050 }
1051
1052 static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1053                                       enum ath9k_ani_cmd cmd,
1054                                       int param)
1055 {
1056         struct ar5416AniState *aniState = ah->curani;
1057         struct ath_common *common = ath9k_hw_common(ah);
1058
1059         switch (cmd & ah->ani_function) {
1060         case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1061                 u32 level = param;
1062
1063                 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1064                         ath_print(common, ATH_DBG_ANI,
1065                                   "level out of range (%u > %u)\n",
1066                                   level,
1067                                   (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
1068                         return false;
1069                 }
1070
1071                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1072                               AR_PHY_DESIRED_SZ_TOT_DES,
1073                               ah->totalSizeDesired[level]);
1074                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1075                               AR_PHY_AGC_CTL1_COARSE_LOW,
1076                               ah->coarse_low[level]);
1077                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1078                               AR_PHY_AGC_CTL1_COARSE_HIGH,
1079                               ah->coarse_high[level]);
1080                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1081                               AR_PHY_FIND_SIG_FIRPWR,
1082                               ah->firpwr[level]);
1083
1084                 if (level > aniState->noiseImmunityLevel)
1085                         ah->stats.ast_ani_niup++;
1086                 else if (level < aniState->noiseImmunityLevel)
1087                         ah->stats.ast_ani_nidown++;
1088                 aniState->noiseImmunityLevel = level;
1089                 break;
1090         }
1091         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1092                 const int m1ThreshLow[] = { 127, 50 };
1093                 const int m2ThreshLow[] = { 127, 40 };
1094                 const int m1Thresh[] = { 127, 0x4d };
1095                 const int m2Thresh[] = { 127, 0x40 };
1096                 const int m2CountThr[] = { 31, 16 };
1097                 const int m2CountThrLow[] = { 63, 48 };
1098                 u32 on = param ? 1 : 0;
1099
1100                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1101                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1102                               m1ThreshLow[on]);
1103                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1104                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1105                               m2ThreshLow[on]);
1106                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1107                               AR_PHY_SFCORR_M1_THRESH,
1108                               m1Thresh[on]);
1109                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1110                               AR_PHY_SFCORR_M2_THRESH,
1111                               m2Thresh[on]);
1112                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1113                               AR_PHY_SFCORR_M2COUNT_THR,
1114                               m2CountThr[on]);
1115                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1116                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1117                               m2CountThrLow[on]);
1118
1119                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1120                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1121                               m1ThreshLow[on]);
1122                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1123                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1124                               m2ThreshLow[on]);
1125                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1126                               AR_PHY_SFCORR_EXT_M1_THRESH,
1127                               m1Thresh[on]);
1128                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1129                               AR_PHY_SFCORR_EXT_M2_THRESH,
1130                               m2Thresh[on]);
1131
1132                 if (on)
1133                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1134                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1135                 else
1136                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1137                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1138
1139                 if (!on != aniState->ofdmWeakSigDetectOff) {
1140                         if (on)
1141                                 ah->stats.ast_ani_ofdmon++;
1142                         else
1143                                 ah->stats.ast_ani_ofdmoff++;
1144                         aniState->ofdmWeakSigDetectOff = !on;
1145                 }
1146                 break;
1147         }
1148         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1149                 const int weakSigThrCck[] = { 8, 6 };
1150                 u32 high = param ? 1 : 0;
1151
1152                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1153                               AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1154                               weakSigThrCck[high]);
1155                 if (high != aniState->cckWeakSigThreshold) {
1156                         if (high)
1157                                 ah->stats.ast_ani_cckhigh++;
1158                         else
1159                                 ah->stats.ast_ani_ccklow++;
1160                         aniState->cckWeakSigThreshold = high;
1161                 }
1162                 break;
1163         }
1164         case ATH9K_ANI_FIRSTEP_LEVEL:{
1165                 const int firstep[] = { 0, 4, 8 };
1166                 u32 level = param;
1167
1168                 if (level >= ARRAY_SIZE(firstep)) {
1169                         ath_print(common, ATH_DBG_ANI,
1170                                   "level out of range (%u > %u)\n",
1171                                   level,
1172                                   (unsigned) ARRAY_SIZE(firstep));
1173                         return false;
1174                 }
1175                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1176                               AR_PHY_FIND_SIG_FIRSTEP,
1177                               firstep[level]);
1178                 if (level > aniState->firstepLevel)
1179                         ah->stats.ast_ani_stepup++;
1180                 else if (level < aniState->firstepLevel)
1181                         ah->stats.ast_ani_stepdown++;
1182                 aniState->firstepLevel = level;
1183                 break;
1184         }
1185         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1186                 const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1187                 u32 level = param;
1188
1189                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1190                         ath_print(common, ATH_DBG_ANI,
1191                                   "level out of range (%u > %u)\n",
1192                                   level,
1193                                   (unsigned) ARRAY_SIZE(cycpwrThr1));
1194                         return false;
1195                 }
1196                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1197                               AR_PHY_TIMING5_CYCPWR_THR1,
1198                               cycpwrThr1[level]);
1199                 if (level > aniState->spurImmunityLevel)
1200                         ah->stats.ast_ani_spurup++;
1201                 else if (level < aniState->spurImmunityLevel)
1202                         ah->stats.ast_ani_spurdown++;
1203                 aniState->spurImmunityLevel = level;
1204                 break;
1205         }
1206         case ATH9K_ANI_PRESENT:
1207                 break;
1208         default:
1209                 ath_print(common, ATH_DBG_ANI,
1210                           "invalid cmd %u\n", cmd);
1211                 return false;
1212         }
1213
1214         ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
1215         ath_print(common, ATH_DBG_ANI,
1216                   "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
1217                   "ofdmWeakSigDetectOff=%d\n",
1218                   aniState->noiseImmunityLevel,
1219                   aniState->spurImmunityLevel,
1220                   !aniState->ofdmWeakSigDetectOff);
1221         ath_print(common, ATH_DBG_ANI,
1222                   "cckWeakSigThreshold=%d, "
1223                   "firstepLevel=%d, listenTime=%d\n",
1224                   aniState->cckWeakSigThreshold,
1225                   aniState->firstepLevel,
1226                   aniState->listenTime);
1227         ath_print(common, ATH_DBG_ANI,
1228                 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1229                 aniState->cycleCount,
1230                 aniState->ofdmPhyErrCount,
1231                 aniState->cckPhyErrCount);
1232
1233         return true;
1234 }
1235
1236 static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1237                                       enum ath9k_ani_cmd cmd,
1238                                       int param)
1239 {
1240         struct ar5416AniState *aniState = ah->curani;
1241         struct ath_common *common = ath9k_hw_common(ah);
1242         struct ath9k_channel *chan = ah->curchan;
1243         s32 value, value2;
1244
1245         switch (cmd & ah->ani_function) {
1246         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1247                 /*
1248                  * on == 1 means ofdm weak signal detection is ON
1249                  * on == 1 is the default, for less noise immunity
1250                  *
1251                  * on == 0 means ofdm weak signal detection is OFF
1252                  * on == 0 means more noise imm
1253                  */
1254                 u32 on = param ? 1 : 0;
1255                 /*
1256                  * make register setting for default
1257                  * (weak sig detect ON) come from INI file
1258                  */
1259                 int m1ThreshLow = on ?
1260                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1261                 int m2ThreshLow = on ?
1262                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1263                 int m1Thresh = on ?
1264                         aniState->iniDef.m1Thresh : m1Thresh_off;
1265                 int m2Thresh = on ?
1266                         aniState->iniDef.m2Thresh : m2Thresh_off;
1267                 int m2CountThr = on ?
1268                         aniState->iniDef.m2CountThr : m2CountThr_off;
1269                 int m2CountThrLow = on ?
1270                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1271                 int m1ThreshLowExt = on ?
1272                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1273                 int m2ThreshLowExt = on ?
1274                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1275                 int m1ThreshExt = on ?
1276                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1277                 int m2ThreshExt = on ?
1278                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1279
1280                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1281                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1282                               m1ThreshLow);
1283                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1284                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1285                               m2ThreshLow);
1286                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1287                               AR_PHY_SFCORR_M1_THRESH, m1Thresh);
1288                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1289                               AR_PHY_SFCORR_M2_THRESH, m2Thresh);
1290                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1291                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
1292                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1293                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1294                               m2CountThrLow);
1295
1296                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1297                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
1298                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1299                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1300                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1301                               AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1302                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1303                               AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1304
1305                 if (on)
1306                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1307                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1308                 else
1309                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1310                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1311
1312                 if (!on != aniState->ofdmWeakSigDetectOff) {
1313                         ath_print(common, ATH_DBG_ANI,
1314                                   "** ch %d: ofdm weak signal: %s=>%s\n",
1315                                   chan->channel,
1316                                   !aniState->ofdmWeakSigDetectOff ?
1317                                         "on" : "off",
1318                                   on ? "on" : "off");
1319                         if (on)
1320                                 ah->stats.ast_ani_ofdmon++;
1321                         else
1322                                 ah->stats.ast_ani_ofdmoff++;
1323                         aniState->ofdmWeakSigDetectOff = !on;
1324                 }
1325                 break;
1326         }
1327         case ATH9K_ANI_FIRSTEP_LEVEL:{
1328                 u32 level = param;
1329
1330                 if (level >= ARRAY_SIZE(firstep_table)) {
1331                         ath_print(common, ATH_DBG_ANI,
1332                                   "ATH9K_ANI_FIRSTEP_LEVEL: level "
1333                                   "out of range (%u > %u)\n",
1334                                   level,
1335                                   (unsigned) ARRAY_SIZE(firstep_table));
1336                         return false;
1337                 }
1338
1339                 /*
1340                  * make register setting relative to default
1341                  * from INI file & cap value
1342                  */
1343                 value = firstep_table[level] -
1344                         firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1345                         aniState->iniDef.firstep;
1346                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1347                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1348                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1349                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1350                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1351                               AR_PHY_FIND_SIG_FIRSTEP,
1352                               value);
1353                 /*
1354                  * we need to set first step low register too
1355                  * make register setting relative to default
1356                  * from INI file & cap value
1357                  */
1358                 value2 = firstep_table[level] -
1359                          firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1360                          aniState->iniDef.firstepLow;
1361                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1362                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1363                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1364                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1365
1366                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1367                               AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1368
1369                 if (level != aniState->firstepLevel) {
1370                         ath_print(common, ATH_DBG_ANI,
1371                                   "** ch %d: level %d=>%d[def:%d] "
1372                                   "firstep[level]=%d ini=%d\n",
1373                                   chan->channel,
1374                                   aniState->firstepLevel,
1375                                   level,
1376                                   ATH9K_ANI_FIRSTEP_LVL_NEW,
1377                                   value,
1378                                   aniState->iniDef.firstep);
1379                         ath_print(common, ATH_DBG_ANI,
1380                                   "** ch %d: level %d=>%d[def:%d] "
1381                                   "firstep_low[level]=%d ini=%d\n",
1382                                   chan->channel,
1383                                   aniState->firstepLevel,
1384                                   level,
1385                                   ATH9K_ANI_FIRSTEP_LVL_NEW,
1386                                   value2,
1387                                   aniState->iniDef.firstepLow);
1388                         if (level > aniState->firstepLevel)
1389                                 ah->stats.ast_ani_stepup++;
1390                         else if (level < aniState->firstepLevel)
1391                                 ah->stats.ast_ani_stepdown++;
1392                         aniState->firstepLevel = level;
1393                 }
1394                 break;
1395         }
1396         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1397                 u32 level = param;
1398
1399                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1400                         ath_print(common, ATH_DBG_ANI,
1401                                   "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
1402                                   "out of range (%u > %u)\n",
1403                                   level,
1404                                   (unsigned) ARRAY_SIZE(cycpwrThr1_table));
1405                         return false;
1406                 }
1407                 /*
1408                  * make register setting relative to default
1409                  * from INI file & cap value
1410                  */
1411                 value = cycpwrThr1_table[level] -
1412                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1413                         aniState->iniDef.cycpwrThr1;
1414                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1415                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1416                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1417                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1418                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1419                               AR_PHY_TIMING5_CYCPWR_THR1,
1420                               value);
1421
1422                 /*
1423                  * set AR_PHY_EXT_CCA for extension channel
1424                  * make register setting relative to default
1425                  * from INI file & cap value
1426                  */
1427                 value2 = cycpwrThr1_table[level] -
1428                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1429                          aniState->iniDef.cycpwrThr1Ext;
1430                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1431                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1432                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1433                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1434                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1435                               AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
1436
1437                 if (level != aniState->spurImmunityLevel) {
1438                         ath_print(common, ATH_DBG_ANI,
1439                                   "** ch %d: level %d=>%d[def:%d] "
1440                                   "cycpwrThr1[level]=%d ini=%d\n",
1441                                   chan->channel,
1442                                   aniState->spurImmunityLevel,
1443                                   level,
1444                                   ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1445                                   value,
1446                                   aniState->iniDef.cycpwrThr1);
1447                         ath_print(common, ATH_DBG_ANI,
1448                                   "** ch %d: level %d=>%d[def:%d] "
1449                                   "cycpwrThr1Ext[level]=%d ini=%d\n",
1450                                   chan->channel,
1451                                   aniState->spurImmunityLevel,
1452                                   level,
1453                                   ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1454                                   value2,
1455                                   aniState->iniDef.cycpwrThr1Ext);
1456                         if (level > aniState->spurImmunityLevel)
1457                                 ah->stats.ast_ani_spurup++;
1458                         else if (level < aniState->spurImmunityLevel)
1459                                 ah->stats.ast_ani_spurdown++;
1460                         aniState->spurImmunityLevel = level;
1461                 }
1462                 break;
1463         }
1464         case ATH9K_ANI_MRC_CCK:
1465                 /*
1466                  * You should not see this as AR5008, AR9001, AR9002
1467                  * does not have hardware support for MRC CCK.
1468                  */
1469                 WARN_ON(1);
1470                 break;
1471         case ATH9K_ANI_PRESENT:
1472                 break;
1473         default:
1474                 ath_print(common, ATH_DBG_ANI,
1475                           "invalid cmd %u\n", cmd);
1476                 return false;
1477         }
1478
1479         ath_print(common, ATH_DBG_ANI,
1480                   "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
1481                   "MRCcck=%s listenTime=%d CC=%d listen=%d "
1482                   "ofdmErrs=%d cckErrs=%d\n",
1483                   aniState->spurImmunityLevel,
1484                   !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1485                   aniState->firstepLevel,
1486                   !aniState->mrcCCKOff ? "on" : "off",
1487                   aniState->listenTime,
1488                   aniState->cycleCount,
1489                   aniState->listenTime,
1490                   aniState->ofdmPhyErrCount,
1491                   aniState->cckPhyErrCount);
1492         return true;
1493 }
1494
1495 static void ar5008_hw_do_getnf(struct ath_hw *ah,
1496                               int16_t nfarray[NUM_NF_READINGS])
1497 {
1498         int16_t nf;
1499
1500         nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1501         nfarray[0] = sign_extend(nf, 9);
1502
1503         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1504         nfarray[1] = sign_extend(nf, 9);
1505
1506         nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1507         nfarray[2] = sign_extend(nf, 9);
1508
1509         if (!IS_CHAN_HT40(ah->curchan))
1510                 return;
1511
1512         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1513         nfarray[3] = sign_extend(nf, 9);
1514
1515         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1516         nfarray[4] = sign_extend(nf, 9);
1517
1518         nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1519         nfarray[5] = sign_extend(nf, 9);
1520 }
1521
1522 /*
1523  * Initialize the ANI register values with default (ini) values.
1524  * This routine is called during a (full) hardware reset after
1525  * all the registers are initialised from the INI.
1526  */
1527 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1528 {
1529         struct ar5416AniState *aniState;
1530         struct ath_common *common = ath9k_hw_common(ah);
1531         struct ath9k_channel *chan = ah->curchan;
1532         struct ath9k_ani_default *iniDef;
1533         int index;
1534         u32 val;
1535
1536         index = ath9k_hw_get_ani_channel_idx(ah, chan);
1537         aniState = &ah->ani[index];
1538         ah->curani = aniState;
1539         iniDef = &aniState->iniDef;
1540
1541         ath_print(common, ATH_DBG_ANI,
1542                   "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1543                   ah->hw_version.macVersion,
1544                   ah->hw_version.macRev,
1545                   ah->opmode,
1546                   chan->channel,
1547                   chan->channelFlags);
1548
1549         val = REG_READ(ah, AR_PHY_SFCORR);
1550         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1551         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1552         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1553
1554         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1555         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1556         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1557         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1558
1559         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1560         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1561         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1562         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1563         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1564         iniDef->firstep = REG_READ_FIELD(ah,
1565                                          AR_PHY_FIND_SIG,
1566                                          AR_PHY_FIND_SIG_FIRSTEP);
1567         iniDef->firstepLow = REG_READ_FIELD(ah,
1568                                             AR_PHY_FIND_SIG_LOW,
1569                                             AR_PHY_FIND_SIG_FIRSTEP_LOW);
1570         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1571                                             AR_PHY_TIMING5,
1572                                             AR_PHY_TIMING5_CYCPWR_THR1);
1573         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1574                                                AR_PHY_EXT_CCA,
1575                                                AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1576
1577         /* these levels just got reset to defaults by the INI */
1578         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1579         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1580         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1581         aniState->mrcCCKOff = true; /* not available on pre AR9003 */
1582
1583         aniState->cycleCount = 0;
1584 }
1585
1586 static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1587 {
1588         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1589         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1590         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1591         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1592         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1593         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1594 }
1595
1596 void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1597 {
1598         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1599         const u32 ar5416_cca_regs[6] = {
1600                 AR_PHY_CCA,
1601                 AR_PHY_CH1_CCA,
1602                 AR_PHY_CH2_CCA,
1603                 AR_PHY_EXT_CCA,
1604                 AR_PHY_CH1_EXT_CCA,
1605                 AR_PHY_CH2_EXT_CCA
1606         };
1607
1608         priv_ops->rf_set_freq = ar5008_hw_set_channel;
1609         priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1610
1611         priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
1612         priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
1613         priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1614         priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1615         priv_ops->init_bb = ar5008_hw_init_bb;
1616         priv_ops->process_ini = ar5008_hw_process_ini;
1617         priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1618         priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1619         priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1620         priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1621         priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1622         priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
1623         priv_ops->restore_chainmask = ar5008_restore_chainmask;
1624         priv_ops->set_diversity = ar5008_set_diversity;
1625         priv_ops->do_getnf = ar5008_hw_do_getnf;
1626
1627         if (modparam_force_new_ani) {
1628                 priv_ops->ani_control = ar5008_hw_ani_control_new;
1629                 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1630         } else
1631                 priv_ops->ani_control = ar5008_hw_ani_control_old;
1632
1633         if (AR_SREV_9100(ah))
1634                 priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
1635         else if (AR_SREV_9160_10_OR_LATER(ah))
1636                 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1637         else
1638                 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1639
1640         ar5008_hw_set_nf_limits(ah);
1641         memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
1642 }