1 /* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
3 Copyright 2000,2001 The Linux Kernel Team
4 Written/copyright 1994-2001 by Donald Becker.
6 This software may be used and distributed according to the terms
7 of the GNU General Public License, incorporated herein by reference.
9 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
10 for more information on this driver.
12 Please submit bugs to http://bugzilla.kernel.org/ .
16 #define DRV_NAME "tulip"
17 #ifdef CONFIG_TULIP_NAPI
18 #define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
20 #define DRV_VERSION "1.1.15"
22 #define DRV_RELDATE "Feb 27, 2007"
25 #include <linux/module.h>
26 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/etherdevice.h>
30 #include <linux/delay.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/crc32.h>
34 #include <asm/unaligned.h>
35 #include <asm/uaccess.h>
41 static char version[] __devinitdata =
42 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
44 /* A few user-configurable values. */
46 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
47 static unsigned int max_interrupt_work = 25;
50 /* Used to pass the full-duplex flag, etc. */
51 static int full_duplex[MAX_UNITS];
52 static int options[MAX_UNITS];
53 static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
55 /* The possible media types that can be set in options[] are: */
56 const char * const medianame[32] = {
57 "10baseT", "10base2", "AUI", "100baseTx",
58 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
59 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
60 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
61 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
62 "","","","", "","","","", "","","","Transceiver reset",
65 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
66 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
67 defined(CONFIG_SPARC) || defined(__ia64__) || \
68 defined(__sh__) || defined(__mips__)
69 static int rx_copybreak = 1518;
71 static int rx_copybreak = 100;
75 Set the bus performance register.
76 Typical: Set 16 longword cache alignment, no burst limit.
77 Cache alignment bits 15:14 Burst length 13:8
78 0000 No alignment 0x00000000 unlimited 0800 8 longwords
79 4000 8 longwords 0100 1 longword 1000 16 longwords
80 8000 16 longwords 0200 2 longwords 2000 32 longwords
81 C000 32 longwords 0400 4 longwords
82 Warning: many older 486 systems are broken and require setting 0x00A04800
83 8 longword cache alignment, 8 longword burst.
84 ToDo: Non-Intel setting could be better.
87 #if defined(__alpha__) || defined(__ia64__)
88 static int csr0 = 0x01A00000 | 0xE000;
89 #elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
90 static int csr0 = 0x01A00000 | 0x8000;
91 #elif defined(CONFIG_SPARC) || defined(__hppa__)
92 /* The UltraSparc PCI controllers will disconnect at every 64-byte
93 * crossing anyways so it makes no sense to tell Tulip to burst
96 static int csr0 = 0x01A00000 | 0x9000;
97 #elif defined(__arm__) || defined(__sh__)
98 static int csr0 = 0x01A00000 | 0x4800;
99 #elif defined(__mips__)
100 static int csr0 = 0x00200000 | 0x4000;
102 #warning Processor architecture undefined!
103 static int csr0 = 0x00A00000 | 0x4800;
106 /* Operational parameters that usually are not changed. */
107 /* Time in jiffies before concluding the transmitter is hung. */
108 #define TX_TIMEOUT (4*HZ)
111 MODULE_AUTHOR("The Linux Kernel Team");
112 MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
113 MODULE_LICENSE("GPL");
114 MODULE_VERSION(DRV_VERSION);
115 module_param(tulip_debug, int, 0);
116 module_param(max_interrupt_work, int, 0);
117 module_param(rx_copybreak, int, 0);
118 module_param(csr0, int, 0);
119 module_param_array(options, int, NULL, 0);
120 module_param_array(full_duplex, int, NULL, 0);
122 #define PFX DRV_NAME ": "
125 int tulip_debug = TULIP_DEBUG;
130 static void tulip_timer(unsigned long data)
132 struct net_device *dev = (struct net_device *)data;
133 struct tulip_private *tp = netdev_priv(dev);
135 if (netif_running(dev))
136 schedule_work(&tp->media_work);
140 * This table use during operation for capabilities and media timer.
142 * It is indexed via the values in 'enum chips'
145 struct tulip_chip_table tulip_tbl[] = {
146 { }, /* placeholder for array, slot unused currently */
147 { }, /* placeholder for array, slot unused currently */
150 { "Digital DS21140 Tulip", 128, 0x0001ebef,
151 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
154 /* DC21142, DC21143 */
155 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
156 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
157 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
160 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
161 HAS_MII | HAS_PNICNWAY, pnic_timer, },
164 { "Macronix 98713 PMAC", 128, 0x0001ebef,
165 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
168 { "Macronix 98715 PMAC", 256, 0x0001ebef,
169 HAS_MEDIA_TABLE, mxic_timer, },
172 { "Macronix 98725 PMAC", 256, 0x0001ebef,
173 HAS_MEDIA_TABLE, mxic_timer, },
176 { "ASIX AX88140", 128, 0x0001fbff,
177 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
178 | IS_ASIX, tulip_timer, tulip_media_task },
181 { "Lite-On PNIC-II", 256, 0x0801fbff,
182 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
185 { "ADMtek Comet", 256, 0x0001abef,
186 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
189 { "Compex 9881 PMAC", 128, 0x0001ebef,
190 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
193 { "Intel DS21145 Tulip", 128, 0x0801fbff,
194 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
195 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
198 #ifdef CONFIG_TULIP_DM910X
199 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
200 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
201 tulip_timer, tulip_media_task },
207 { "Conexant LANfinity", 256, 0x0001ebef,
208 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
213 static DEFINE_PCI_DEVICE_TABLE(tulip_pci_tbl) = {
214 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
215 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
216 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
217 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
218 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
219 /* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
220 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
221 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
222 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
232 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
233 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
234 #ifdef CONFIG_TULIP_DM910X
235 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
236 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
238 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
240 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
245 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
246 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
247 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
248 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
249 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
250 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
251 { 0x1414, 0x0001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Microsoft MN-120 */
252 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
253 { } /* terminate list */
255 MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
258 /* A full-duplex map for media types. */
259 const char tulip_media_cap[32] =
260 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
262 static void tulip_tx_timeout(struct net_device *dev);
263 static void tulip_init_ring(struct net_device *dev);
264 static void tulip_free_ring(struct net_device *dev);
265 static netdev_tx_t tulip_start_xmit(struct sk_buff *skb,
266 struct net_device *dev);
267 static int tulip_open(struct net_device *dev);
268 static int tulip_close(struct net_device *dev);
269 static void tulip_up(struct net_device *dev);
270 static void tulip_down(struct net_device *dev);
271 static struct net_device_stats *tulip_get_stats(struct net_device *dev);
272 static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
273 static void set_rx_mode(struct net_device *dev);
274 #ifdef CONFIG_NET_POLL_CONTROLLER
275 static void poll_tulip(struct net_device *dev);
278 static void tulip_set_power_state (struct tulip_private *tp,
279 int sleep, int snooze)
281 if (tp->flags & HAS_ACPI) {
283 pci_read_config_dword (tp->pdev, CFDD, &tmp);
284 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
286 newtmp |= CFDD_Sleep;
288 newtmp |= CFDD_Snooze;
290 pci_write_config_dword (tp->pdev, CFDD, newtmp);
296 static void tulip_up(struct net_device *dev)
298 struct tulip_private *tp = netdev_priv(dev);
299 void __iomem *ioaddr = tp->base_addr;
300 int next_tick = 3*HZ;
304 #ifdef CONFIG_TULIP_NAPI
305 napi_enable(&tp->napi);
308 /* Wake the chip from sleep/snooze mode. */
309 tulip_set_power_state (tp, 0, 0);
311 /* On some chip revs we must set the MII/SYM port before the reset!? */
312 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
313 iowrite32(0x00040000, ioaddr + CSR6);
315 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
316 iowrite32(0x00000001, ioaddr + CSR0);
317 pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */
321 Wait the specified 50 PCI cycles after a reset by initializing
322 Tx and Rx queues and the address filter list. */
323 iowrite32(tp->csr0, ioaddr + CSR0);
324 pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */
328 printk(KERN_DEBUG "%s: tulip_up(), irq==%d\n",
329 dev->name, dev->irq);
331 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
332 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
333 tp->cur_rx = tp->cur_tx = 0;
334 tp->dirty_rx = tp->dirty_tx = 0;
336 if (tp->flags & MC_HASH_ONLY) {
337 u32 addr_low = get_unaligned_le32(dev->dev_addr);
338 u32 addr_high = get_unaligned_le16(dev->dev_addr + 4);
339 if (tp->chip_id == AX88140) {
340 iowrite32(0, ioaddr + CSR13);
341 iowrite32(addr_low, ioaddr + CSR14);
342 iowrite32(1, ioaddr + CSR13);
343 iowrite32(addr_high, ioaddr + CSR14);
344 } else if (tp->flags & COMET_MAC_ADDR) {
345 iowrite32(addr_low, ioaddr + 0xA4);
346 iowrite32(addr_high, ioaddr + 0xA8);
347 iowrite32(0, ioaddr + 0xAC);
348 iowrite32(0, ioaddr + 0xB0);
351 /* This is set_rx_mode(), but without starting the transmitter. */
352 u16 *eaddrs = (u16 *)dev->dev_addr;
353 u16 *setup_frm = &tp->setup_frame[15*6];
356 /* 21140 bug: you must add the broadcast address. */
357 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
358 /* Fill the final entry of the table with our physical address. */
359 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
360 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
361 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
363 mapping = pci_map_single(tp->pdev, tp->setup_frame,
364 sizeof(tp->setup_frame),
366 tp->tx_buffers[tp->cur_tx].skb = NULL;
367 tp->tx_buffers[tp->cur_tx].mapping = mapping;
369 /* Put the setup frame on the Tx list. */
370 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
371 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
372 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
377 tp->saved_if_port = dev->if_port;
378 if (dev->if_port == 0)
379 dev->if_port = tp->default_port;
381 /* Allow selecting a default media. */
383 if (tp->mtable == NULL)
386 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
387 (dev->if_port == 12 ? 0 : dev->if_port);
388 for (i = 0; i < tp->mtable->leafcount; i++)
389 if (tp->mtable->mleaf[i].media == looking_for) {
391 "Using user-specified media %s\n",
392 medianame[dev->if_port]);
396 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
397 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
398 for (i = 0; i < tp->mtable->leafcount; i++)
399 if (tp->mtable->mleaf[i].media == looking_for) {
401 "Using EEPROM-set media %s\n",
402 medianame[looking_for]);
406 /* Start sensing first non-full-duplex media. */
407 for (i = tp->mtable->leafcount - 1;
408 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
417 if (tp->chip_id == DC21143 &&
418 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
419 /* We must reset the media CSRs when we force-select MII mode. */
420 iowrite32(0x0000, ioaddr + CSR13);
421 iowrite32(0x0000, ioaddr + CSR14);
422 iowrite32(0x0008, ioaddr + CSR15);
424 tulip_select_media(dev, 1);
425 } else if (tp->chip_id == DC21142) {
427 tulip_select_media(dev, 1);
430 "Using MII transceiver %d, status %04x\n",
432 tulip_mdio_read(dev, tp->phys[0], 1));
433 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
434 tp->csr6 = csr6_mask_hdcap;
436 iowrite32(0x0000, ioaddr + CSR13);
437 iowrite32(0x0000, ioaddr + CSR14);
439 t21142_start_nway(dev);
440 } else if (tp->chip_id == PNIC2) {
441 /* for initial startup advertise 10/100 Full and Half */
442 tp->sym_advertise = 0x01E0;
443 /* enable autonegotiate end interrupt */
444 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
445 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
446 pnic2_start_nway(dev);
447 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
450 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
451 iowrite32(0x0001, ioaddr + CSR15);
452 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
455 /* Start with 10mbps to do autonegotiation. */
456 iowrite32(0x32, ioaddr + CSR12);
457 tp->csr6 = 0x00420000;
458 iowrite32(0x0001B078, ioaddr + 0xB8);
459 iowrite32(0x0201B078, ioaddr + 0xB8);
462 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881) &&
465 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
466 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
467 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
468 /* Provided by BOLO, Macronix - 12/10/1998. */
470 tp->csr6 = 0x01a80200;
471 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
472 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
473 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
474 /* Enable automatic Tx underrun recovery. */
475 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
476 dev->if_port = tp->mii_cnt ? 11 : 0;
477 tp->csr6 = 0x00040000;
478 } else if (tp->chip_id == AX88140) {
479 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
481 tulip_select_media(dev, 1);
483 /* Start the chip's Tx to process setup frame. */
487 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
489 /* Enable interrupts by setting the interrupt mask. */
490 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
491 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
492 tulip_start_rxtx(tp);
493 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
495 if (tulip_debug > 2) {
496 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n",
497 dev->name, ioread32(ioaddr + CSR0),
498 ioread32(ioaddr + CSR5),
499 ioread32(ioaddr + CSR6));
502 /* Set the timer to switch to check for link beat and perhaps switch
503 to an alternate media type. */
504 tp->timer.expires = RUN_AT(next_tick);
505 add_timer(&tp->timer);
506 #ifdef CONFIG_TULIP_NAPI
507 init_timer(&tp->oom_timer);
508 tp->oom_timer.data = (unsigned long)dev;
509 tp->oom_timer.function = oom_timer;
514 tulip_open(struct net_device *dev)
518 tulip_init_ring (dev);
520 retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev);
526 netif_start_queue (dev);
531 tulip_free_ring (dev);
536 static void tulip_tx_timeout(struct net_device *dev)
538 struct tulip_private *tp = netdev_priv(dev);
539 void __iomem *ioaddr = tp->base_addr;
542 spin_lock_irqsave (&tp->lock, flags);
544 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
545 /* Do nothing -- the media monitor should handle this. */
548 "Transmit timeout using MII device\n");
549 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142 ||
550 tp->chip_id == MX98713 || tp->chip_id == COMPEX9881 ||
551 tp->chip_id == DM910X) {
553 "21140 transmit timed out, status %08x, SIA %08x %08x %08x %08x, resetting...\n",
554 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
555 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14),
556 ioread32(ioaddr + CSR15));
557 tp->timeout_recovery = 1;
558 schedule_work(&tp->media_work);
560 } else if (tp->chip_id == PNIC2) {
562 "PNIC2 transmit timed out, status %08x, CSR6/7 %08x / %08x CSR12 %08x, resetting...\n",
563 (int)ioread32(ioaddr + CSR5),
564 (int)ioread32(ioaddr + CSR6),
565 (int)ioread32(ioaddr + CSR7),
566 (int)ioread32(ioaddr + CSR12));
569 "Transmit timed out, status %08x, CSR12 %08x, resetting...\n",
570 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
574 #if defined(way_too_many_messages)
575 if (tulip_debug > 3) {
577 for (i = 0; i < RX_RING_SIZE; i++) {
578 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
581 "%2d: %08x %08x %08x %08x %02x %02x %02x\n",
583 (unsigned int)tp->rx_ring[i].status,
584 (unsigned int)tp->rx_ring[i].length,
585 (unsigned int)tp->rx_ring[i].buffer1,
586 (unsigned int)tp->rx_ring[i].buffer2,
587 buf[0], buf[1], buf[2]);
588 for (j = 0; buf[j] != 0xee && j < 1600; j++)
590 pr_cont(" %02x", buf[j]);
591 pr_cont(" j=%d\n", j);
593 printk(KERN_DEBUG " Rx ring %08x: ", (int)tp->rx_ring);
594 for (i = 0; i < RX_RING_SIZE; i++)
595 pr_cont(" %08x", (unsigned int)tp->rx_ring[i].status);
596 printk(KERN_DEBUG " Tx ring %08x: ", (int)tp->tx_ring);
597 for (i = 0; i < TX_RING_SIZE; i++)
598 pr_cont(" %08x", (unsigned int)tp->tx_ring[i].status);
603 tulip_tx_timeout_complete(tp, ioaddr);
606 spin_unlock_irqrestore (&tp->lock, flags);
607 dev->trans_start = jiffies;
608 netif_wake_queue (dev);
612 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
613 static void tulip_init_ring(struct net_device *dev)
615 struct tulip_private *tp = netdev_priv(dev);
622 for (i = 0; i < RX_RING_SIZE; i++) {
623 tp->rx_ring[i].status = 0x00000000;
624 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
625 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
626 tp->rx_buffers[i].skb = NULL;
627 tp->rx_buffers[i].mapping = 0;
629 /* Mark the last entry as wrapping the ring. */
630 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
631 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
633 for (i = 0; i < RX_RING_SIZE; i++) {
636 /* Note the receive buffer must be longword aligned.
637 dev_alloc_skb() provides 16 byte alignment. But do *not*
638 use skb_reserve() to align the IP header! */
639 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
640 tp->rx_buffers[i].skb = skb;
643 mapping = pci_map_single(tp->pdev, skb->data,
644 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
645 tp->rx_buffers[i].mapping = mapping;
646 skb->dev = dev; /* Mark as being used by this device. */
647 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
648 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
650 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
652 /* The Tx buffer descriptor is filled in as needed, but we
653 do need to clear the ownership bit. */
654 for (i = 0; i < TX_RING_SIZE; i++) {
655 tp->tx_buffers[i].skb = NULL;
656 tp->tx_buffers[i].mapping = 0;
657 tp->tx_ring[i].status = 0x00000000;
658 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
660 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
664 tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
666 struct tulip_private *tp = netdev_priv(dev);
672 spin_lock_irqsave(&tp->lock, flags);
674 /* Calculate the next Tx descriptor entry. */
675 entry = tp->cur_tx % TX_RING_SIZE;
677 tp->tx_buffers[entry].skb = skb;
678 mapping = pci_map_single(tp->pdev, skb->data,
679 skb->len, PCI_DMA_TODEVICE);
680 tp->tx_buffers[entry].mapping = mapping;
681 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
683 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
684 flag = 0x60000000; /* No interrupt */
685 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
686 flag = 0xe0000000; /* Tx-done intr. */
687 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
688 flag = 0x60000000; /* No Tx-done intr. */
689 } else { /* Leave room for set_rx_mode() to fill entries. */
690 flag = 0xe0000000; /* Tx-done intr. */
691 netif_stop_queue(dev);
693 if (entry == TX_RING_SIZE-1)
694 flag = 0xe0000000 | DESC_RING_WRAP;
696 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
697 /* if we were using Transmit Automatic Polling, we would need a
699 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
704 /* Trigger an immediate transmit demand. */
705 iowrite32(0, tp->base_addr + CSR1);
707 spin_unlock_irqrestore(&tp->lock, flags);
709 dev->trans_start = jiffies;
714 static void tulip_clean_tx_ring(struct tulip_private *tp)
716 unsigned int dirty_tx;
718 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
720 int entry = dirty_tx % TX_RING_SIZE;
721 int status = le32_to_cpu(tp->tx_ring[entry].status);
724 tp->stats.tx_errors++; /* It wasn't Txed */
725 tp->tx_ring[entry].status = 0;
728 /* Check for Tx filter setup frames. */
729 if (tp->tx_buffers[entry].skb == NULL) {
730 /* test because dummy frames not mapped */
731 if (tp->tx_buffers[entry].mapping)
732 pci_unmap_single(tp->pdev,
733 tp->tx_buffers[entry].mapping,
734 sizeof(tp->setup_frame),
739 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
740 tp->tx_buffers[entry].skb->len,
743 /* Free the original skb. */
744 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
745 tp->tx_buffers[entry].skb = NULL;
746 tp->tx_buffers[entry].mapping = 0;
750 static void tulip_down (struct net_device *dev)
752 struct tulip_private *tp = netdev_priv(dev);
753 void __iomem *ioaddr = tp->base_addr;
756 cancel_work_sync(&tp->media_work);
758 #ifdef CONFIG_TULIP_NAPI
759 napi_disable(&tp->napi);
762 del_timer_sync (&tp->timer);
763 #ifdef CONFIG_TULIP_NAPI
764 del_timer_sync (&tp->oom_timer);
766 spin_lock_irqsave (&tp->lock, flags);
768 /* Disable interrupts by clearing the interrupt mask. */
769 iowrite32 (0x00000000, ioaddr + CSR7);
771 /* Stop the Tx and Rx processes. */
774 /* prepare receive buffers */
775 tulip_refill_rx(dev);
777 /* release any unconsumed transmit buffers */
778 tulip_clean_tx_ring(tp);
780 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
781 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
783 spin_unlock_irqrestore (&tp->lock, flags);
785 init_timer(&tp->timer);
786 tp->timer.data = (unsigned long)dev;
787 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
789 dev->if_port = tp->saved_if_port;
791 /* Leave the driver in snooze, not sleep, mode. */
792 tulip_set_power_state (tp, 0, 1);
795 static void tulip_free_ring (struct net_device *dev)
797 struct tulip_private *tp = netdev_priv(dev);
800 /* Free all the skbuffs in the Rx queue. */
801 for (i = 0; i < RX_RING_SIZE; i++) {
802 struct sk_buff *skb = tp->rx_buffers[i].skb;
803 dma_addr_t mapping = tp->rx_buffers[i].mapping;
805 tp->rx_buffers[i].skb = NULL;
806 tp->rx_buffers[i].mapping = 0;
808 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
809 tp->rx_ring[i].length = 0;
810 /* An invalid address. */
811 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
813 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
819 for (i = 0; i < TX_RING_SIZE; i++) {
820 struct sk_buff *skb = tp->tx_buffers[i].skb;
823 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
824 skb->len, PCI_DMA_TODEVICE);
827 tp->tx_buffers[i].skb = NULL;
828 tp->tx_buffers[i].mapping = 0;
832 static int tulip_close (struct net_device *dev)
834 struct tulip_private *tp = netdev_priv(dev);
835 void __iomem *ioaddr = tp->base_addr;
837 netif_stop_queue (dev);
842 dev_printk(KERN_DEBUG, &dev->dev,
843 "Shutting down ethercard, status was %02x\n",
844 ioread32 (ioaddr + CSR5));
846 free_irq (dev->irq, dev);
848 tulip_free_ring (dev);
853 static struct net_device_stats *tulip_get_stats(struct net_device *dev)
855 struct tulip_private *tp = netdev_priv(dev);
856 void __iomem *ioaddr = tp->base_addr;
858 if (netif_running(dev)) {
861 spin_lock_irqsave (&tp->lock, flags);
863 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
865 spin_unlock_irqrestore(&tp->lock, flags);
872 static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
874 struct tulip_private *np = netdev_priv(dev);
875 strcpy(info->driver, DRV_NAME);
876 strcpy(info->version, DRV_VERSION);
877 strcpy(info->bus_info, pci_name(np->pdev));
880 static const struct ethtool_ops ops = {
881 .get_drvinfo = tulip_get_drvinfo
884 /* Provide ioctl() calls to examine the MII xcvr state. */
885 static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
887 struct tulip_private *tp = netdev_priv(dev);
888 void __iomem *ioaddr = tp->base_addr;
889 struct mii_ioctl_data *data = if_mii(rq);
890 const unsigned int phy_idx = 0;
891 int phy = tp->phys[phy_idx] & 0x1f;
892 unsigned int regnum = data->reg_num;
895 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
898 else if (tp->flags & HAS_NWAY)
900 else if (tp->chip_id == COMET)
905 case SIOCGMIIREG: /* Read MII PHY register. */
906 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
907 int csr12 = ioread32 (ioaddr + CSR12);
908 int csr14 = ioread32 (ioaddr + CSR14);
911 if (((csr14<<5) & 0x1000) ||
912 (dev->if_port == 5 && tp->nwayset))
913 data->val_out = 0x1000;
915 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
916 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
921 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
922 ((csr12&0x06) == 6 ? 0 : 4);
923 data->val_out |= 0x6048;
926 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
928 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
929 ((csr14 >> 1) & 0x20) + 1;
930 data->val_out |= ((csr14 >> 9) & 0x03C0);
932 case 5: data->val_out = tp->lpar; break;
933 default: data->val_out = 0; break;
936 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
940 case SIOCSMIIREG: /* Write MII PHY register. */
943 if (data->phy_id == phy) {
944 u16 value = data->val_in;
946 case 0: /* Check for autonegotiation on or reset. */
947 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
948 if (tp->full_duplex_lock)
949 tp->full_duplex = (value & 0x0100) ? 1 : 0;
952 tp->advertising[phy_idx] =
953 tp->mii_advertise = data->val_in;
957 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
958 u16 value = data->val_in;
960 if ((value & 0x1200) == 0x1200) {
961 if (tp->chip_id == PNIC2) {
962 pnic2_start_nway (dev);
964 t21142_start_nway (dev);
967 } else if (regnum == 4)
968 tp->sym_advertise = value;
970 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
981 /* Set or clear the multicast filter for this adaptor.
982 Note that we only use exclusion around actually queueing the
983 new frame, not around filling tp->setup_frame. This is non-deterministic
984 when re-entered but still correct. */
987 #define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
989 static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
991 struct tulip_private *tp = netdev_priv(dev);
993 struct dev_mc_list *mclist;
997 memset(hash_table, 0, sizeof(hash_table));
998 set_bit_le(255, hash_table); /* Broadcast entry */
999 /* This should work on big-endian machines as well. */
1000 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1001 i++, mclist = mclist->next) {
1002 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
1004 set_bit_le(index, hash_table);
1007 for (i = 0; i < 32; i++) {
1008 *setup_frm++ = hash_table[i];
1009 *setup_frm++ = hash_table[i];
1011 setup_frm = &tp->setup_frame[13*6];
1013 /* Fill the final entry with our physical address. */
1014 eaddrs = (u16 *)dev->dev_addr;
1015 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1016 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1017 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1020 static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
1022 struct tulip_private *tp = netdev_priv(dev);
1023 struct dev_mc_list *mclist;
1027 /* We have <= 14 addresses so we can use the wonderful
1028 16 address perfect filtering of the Tulip. */
1029 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
1030 i++, mclist = mclist->next) {
1031 eaddrs = (u16 *)mclist->dmi_addr;
1032 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1033 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1034 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1036 /* Fill the unused entries with the broadcast address. */
1037 memset(setup_frm, 0xff, (15-i)*12);
1038 setup_frm = &tp->setup_frame[15*6];
1040 /* Fill the final entry with our physical address. */
1041 eaddrs = (u16 *)dev->dev_addr;
1042 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1043 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1044 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1048 static void set_rx_mode(struct net_device *dev)
1050 struct tulip_private *tp = netdev_priv(dev);
1051 void __iomem *ioaddr = tp->base_addr;
1054 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1056 tp->csr6 &= ~0x00D5;
1057 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1058 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1059 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1060 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1061 /* Too many to filter well -- accept all multicasts. */
1062 tp->csr6 |= AcceptAllMulticast;
1063 csr6 |= AcceptAllMulticast;
1064 } else if (tp->flags & MC_HASH_ONLY) {
1065 /* Some work-alikes have only a 64-entry hash filter table. */
1066 /* Should verify correctness on big-endian/__powerpc__ */
1067 struct dev_mc_list *mclist;
1069 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1070 tp->csr6 |= AcceptAllMulticast;
1071 csr6 |= AcceptAllMulticast;
1073 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1075 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1076 i++, mclist = mclist->next) {
1077 if (tp->flags & COMET_MAC_ADDR)
1078 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1080 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1082 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1083 if (tulip_debug > 2)
1085 "Added filter for %pM %08x bit %d\n",
1087 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1089 if (mc_filter[0] == tp->mc_filter[0] &&
1090 mc_filter[1] == tp->mc_filter[1])
1092 else if (tp->flags & IS_ASIX) {
1093 iowrite32(2, ioaddr + CSR13);
1094 iowrite32(mc_filter[0], ioaddr + CSR14);
1095 iowrite32(3, ioaddr + CSR13);
1096 iowrite32(mc_filter[1], ioaddr + CSR14);
1097 } else if (tp->flags & COMET_MAC_ADDR) {
1098 iowrite32(mc_filter[0], ioaddr + 0xAC);
1099 iowrite32(mc_filter[1], ioaddr + 0xB0);
1101 tp->mc_filter[0] = mc_filter[0];
1102 tp->mc_filter[1] = mc_filter[1];
1105 unsigned long flags;
1106 u32 tx_flags = 0x08000000 | 192;
1108 /* Note that only the low-address shortword of setup_frame is valid!
1109 The values are doubled for big-endian architectures. */
1110 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1111 build_setup_frame_hash(tp->setup_frame, dev);
1112 tx_flags = 0x08400000 | 192;
1114 build_setup_frame_perfect(tp->setup_frame, dev);
1117 spin_lock_irqsave(&tp->lock, flags);
1119 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1120 /* Same setup recently queued, we need not add it. */
1125 /* Now add this frame to the Tx list. */
1127 entry = tp->cur_tx++ % TX_RING_SIZE;
1130 /* Avoid a chip errata by prefixing a dummy entry. */
1131 tp->tx_buffers[entry].skb = NULL;
1132 tp->tx_buffers[entry].mapping = 0;
1133 tp->tx_ring[entry].length =
1134 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1135 tp->tx_ring[entry].buffer1 = 0;
1136 /* Must set DescOwned later to avoid race with chip */
1138 entry = tp->cur_tx++ % TX_RING_SIZE;
1142 tp->tx_buffers[entry].skb = NULL;
1143 tp->tx_buffers[entry].mapping =
1144 pci_map_single(tp->pdev, tp->setup_frame,
1145 sizeof(tp->setup_frame),
1147 /* Put the setup frame on the Tx list. */
1148 if (entry == TX_RING_SIZE-1)
1149 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1150 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1151 tp->tx_ring[entry].buffer1 =
1152 cpu_to_le32(tp->tx_buffers[entry].mapping);
1153 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1155 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1156 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1157 netif_stop_queue(dev);
1159 /* Trigger an immediate transmit demand. */
1160 iowrite32(0, ioaddr + CSR1);
1163 spin_unlock_irqrestore(&tp->lock, flags);
1166 iowrite32(csr6, ioaddr + CSR6);
1169 #ifdef CONFIG_TULIP_MWI
1170 static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1171 struct net_device *dev)
1173 struct tulip_private *tp = netdev_priv(dev);
1178 if (tulip_debug > 3)
1179 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1181 tp->csr0 = csr0 = 0;
1183 /* if we have any cache line size at all, we can do MRM and MWI */
1186 /* Enable MWI in the standard PCI command bit.
1187 * Check for the case where MWI is desired but not available
1189 pci_try_set_mwi(pdev);
1191 /* read result from hardware (in case bit refused to enable) */
1192 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1193 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1196 /* if cache line size hardwired to zero, no MWI */
1197 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1198 if ((csr0 & MWI) && (cache == 0)) {
1200 pci_clear_mwi(pdev);
1203 /* assign per-cacheline-size cache alignment and
1204 * burst length values
1208 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1211 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1214 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1221 /* if we have a good cache line size, we by now have a good
1222 * csr0, so save it and exit
1227 /* we don't have a good csr0 or cache line size, disable MWI */
1229 pci_clear_mwi(pdev);
1233 /* sane defaults for burst length and cache alignment
1234 * originally from de4x5 driver
1236 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1240 if (tulip_debug > 2)
1241 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1242 pci_name(pdev), cache, csr0);
1247 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1248 * is the DM910X and the on chip ULi devices
1251 static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1253 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1258 static const struct net_device_ops tulip_netdev_ops = {
1259 .ndo_open = tulip_open,
1260 .ndo_start_xmit = tulip_start_xmit,
1261 .ndo_tx_timeout = tulip_tx_timeout,
1262 .ndo_stop = tulip_close,
1263 .ndo_get_stats = tulip_get_stats,
1264 .ndo_do_ioctl = private_ioctl,
1265 .ndo_set_multicast_list = set_rx_mode,
1266 .ndo_change_mtu = eth_change_mtu,
1267 .ndo_set_mac_address = eth_mac_addr,
1268 .ndo_validate_addr = eth_validate_addr,
1269 #ifdef CONFIG_NET_POLL_CONTROLLER
1270 .ndo_poll_controller = poll_tulip,
1274 static int __devinit tulip_init_one (struct pci_dev *pdev,
1275 const struct pci_device_id *ent)
1277 struct tulip_private *tp;
1278 /* See note below on the multiport cards. */
1279 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1280 static struct pci_device_id early_486_chipsets[] = {
1281 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1282 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1285 static int last_irq;
1286 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1289 unsigned char *ee_data;
1290 struct net_device *dev;
1291 void __iomem *ioaddr;
1292 static int board_idx = -1;
1293 int chip_idx = ent->driver_data;
1294 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1295 unsigned int eeprom_missing = 0;
1296 unsigned int force_csr0 = 0;
1299 if (tulip_debug > 0)
1300 printk_once(KERN_INFO "%s", version);
1306 * Lan media wire a tulip chip to a wan interface. Needs a very
1307 * different driver (lmc driver)
1310 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1311 pr_err(PFX "skipping LMC card\n");
1316 * DM910x chips should be handled by the dmfe driver, except
1317 * on-board chips on SPARC systems. Also, early DM9100s need
1318 * software CRC which only the dmfe driver supports.
1321 #ifdef CONFIG_TULIP_DM910X
1322 if (chip_idx == DM910X) {
1323 struct device_node *dp;
1325 if (pdev->vendor == 0x1282 && pdev->device == 0x9100 &&
1326 pdev->revision < 0x30) {
1327 pr_info(PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1331 dp = pci_device_to_OF_node(pdev);
1332 if (!(dp && of_get_property(dp, "local-mac-address", NULL))) {
1333 pr_info(PFX "skipping DM910x expansion card (use dmfe)\n");
1340 * Looks for early PCI chipsets where people report hangs
1341 * without the workarounds being on.
1344 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
1345 aligned. Aries might need this too. The Saturn errata are not
1346 pretty reading but thankfully it's an old 486 chipset.
1348 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1352 if (pci_dev_present(early_486_chipsets)) {
1353 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1357 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1358 if (chip_idx == AX88140) {
1359 if ((csr0 & 0x3f00) == 0)
1363 /* PNIC doesn't have MWI/MRL/MRM... */
1364 if (chip_idx == LC82C168)
1365 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1367 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1368 if (tulip_uli_dm_quirk(pdev)) {
1369 csr0 &= ~0x01f100ff;
1370 #if defined(CONFIG_SPARC)
1371 csr0 = (csr0 & ~0xff00) | 0xe000;
1375 * And back to business
1378 i = pci_enable_device(pdev);
1380 pr_err(PFX "Cannot enable tulip board #%d, aborting\n",
1387 /* alloc_etherdev ensures aligned and zeroed private structures */
1388 dev = alloc_etherdev (sizeof (*tp));
1390 pr_err(PFX "ether device alloc failed, aborting\n");
1394 SET_NETDEV_DEV(dev, &pdev->dev);
1395 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1396 pr_err(PFX "%s: I/O region (0x%llx@0x%llx) too small, aborting\n",
1398 (unsigned long long)pci_resource_len (pdev, 0),
1399 (unsigned long long)pci_resource_start (pdev, 0));
1400 goto err_out_free_netdev;
1403 /* grab all resources from both PIO and MMIO regions, as we
1404 * don't want anyone else messing around with our hardware */
1405 if (pci_request_regions (pdev, DRV_NAME))
1406 goto err_out_free_netdev;
1408 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1411 goto err_out_free_res;
1414 * initialize private data structure 'tp'
1415 * it is zeroed and aligned in alloc_etherdev
1417 tp = netdev_priv(dev);
1420 tp->rx_ring = pci_alloc_consistent(pdev,
1421 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1422 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1425 goto err_out_mtable;
1426 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1427 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1429 tp->chip_id = chip_idx;
1430 tp->flags = tulip_tbl[chip_idx].flags;
1432 tp->base_addr = ioaddr;
1433 tp->revision = pdev->revision;
1435 spin_lock_init(&tp->lock);
1436 spin_lock_init(&tp->mii_lock);
1437 init_timer(&tp->timer);
1438 tp->timer.data = (unsigned long)dev;
1439 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1441 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
1443 dev->base_addr = (unsigned long)ioaddr;
1445 #ifdef CONFIG_TULIP_MWI
1446 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1447 tulip_mwi_config (pdev, dev);
1450 /* Stop the chip's Tx and Rx processes. */
1451 tulip_stop_rxtx(tp);
1453 pci_set_master(pdev);
1456 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1457 switch (pdev->subsystem_device) {
1466 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1467 chip_name = "GSC DS21140 Tulip";
1472 /* Clear the missed-packet counter. */
1473 ioread32(ioaddr + CSR8);
1475 /* The station address ROM is read byte serially. The register must
1476 be polled, waiting for the value to be read bit serially from the
1479 ee_data = tp->eeprom;
1480 memset(ee_data, 0, sizeof(tp->eeprom));
1482 if (chip_idx == LC82C168) {
1483 for (i = 0; i < 3; i++) {
1484 int value, boguscnt = 100000;
1485 iowrite32(0x600 | i, ioaddr + 0x98);
1487 value = ioread32(ioaddr + CSR9);
1488 } while (value < 0 && --boguscnt > 0);
1489 put_unaligned_le16(value, ((__le16 *)dev->dev_addr) + i);
1490 sum += value & 0xffff;
1492 } else if (chip_idx == COMET) {
1493 /* No need to read the EEPROM. */
1494 put_unaligned_le32(ioread32(ioaddr + 0xA4), dev->dev_addr);
1495 put_unaligned_le16(ioread32(ioaddr + 0xA8), dev->dev_addr + 4);
1496 for (i = 0; i < 6; i ++)
1497 sum += dev->dev_addr[i];
1499 /* A serial EEPROM interface, we read now and sort it out later. */
1501 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1502 int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16);
1504 if (ee_max_addr > sizeof(tp->eeprom))
1505 ee_max_addr = sizeof(tp->eeprom);
1507 for (i = 0; i < ee_max_addr ; i += sizeof(u16)) {
1508 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1509 ee_data[i] = data & 0xff;
1510 ee_data[i + 1] = data >> 8;
1513 /* DEC now has a specification (see Notes) but early board makers
1514 just put the address in the first EEPROM locations. */
1515 /* This does memcmp(ee_data, ee_data+16, 8) */
1516 for (i = 0; i < 8; i ++)
1517 if (ee_data[i] != ee_data[16+i])
1519 if (chip_idx == CONEXANT) {
1520 /* Check that the tuple type and length is correct. */
1521 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1523 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1525 sa_offset = 2; /* Grrr, damn Matrox boards. */
1528 #ifdef CONFIG_MIPS_COBALT
1529 if ((pdev->bus->number == 0) &&
1530 ((PCI_SLOT(pdev->devfn) == 7) ||
1531 (PCI_SLOT(pdev->devfn) == 12))) {
1532 /* Cobalt MAC address in first EEPROM locations. */
1534 /* Ensure our media table fixup get's applied */
1535 memcpy(ee_data + 16, ee_data, 8);
1539 /* Check to see if we have a broken srom */
1540 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1541 /* pci_vendor_id and subsystem_id are swapped */
1542 ee_data[0] = ee_data[2];
1543 ee_data[1] = ee_data[3];
1547 /* HSC-PCI boards need to be byte-swaped and shifted
1548 * up 1 word. This shift needs to happen at the end
1549 * of the MAC first because of the 2 byte overlap.
1551 for (i = 4; i >= 0; i -= 2) {
1552 ee_data[17 + i + 3] = ee_data[17 + i];
1553 ee_data[16 + i + 5] = ee_data[16 + i];
1558 for (i = 0; i < 6; i ++) {
1559 dev->dev_addr[i] = ee_data[i + sa_offset];
1560 sum += ee_data[i + sa_offset];
1563 /* Lite-On boards have the address byte-swapped. */
1564 if ((dev->dev_addr[0] == 0xA0 ||
1565 dev->dev_addr[0] == 0xC0 ||
1566 dev->dev_addr[0] == 0x02) &&
1567 dev->dev_addr[1] == 0x00)
1568 for (i = 0; i < 6; i+=2) {
1569 char tmp = dev->dev_addr[i];
1570 dev->dev_addr[i] = dev->dev_addr[i+1];
1571 dev->dev_addr[i+1] = tmp;
1573 /* On the Zynx 315 Etherarray and other multiport boards only the
1574 first Tulip has an EEPROM.
1575 On Sparc systems the mac address is held in the OBP property
1576 "local-mac-address".
1577 The addresses of the subsequent ports are derived from the first.
1578 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1579 that here as well. */
1580 if (sum == 0 || sum == 6*0xff) {
1581 #if defined(CONFIG_SPARC)
1582 struct device_node *dp = pci_device_to_OF_node(pdev);
1583 const unsigned char *addr;
1587 for (i = 0; i < 5; i++)
1588 dev->dev_addr[i] = last_phys_addr[i];
1589 dev->dev_addr[i] = last_phys_addr[i] + 1;
1590 #if defined(CONFIG_SPARC)
1591 addr = of_get_property(dp, "local-mac-address", &len);
1592 if (addr && len == 6)
1593 memcpy(dev->dev_addr, addr, 6);
1595 #if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1601 for (i = 0; i < 6; i++)
1602 last_phys_addr[i] = dev->dev_addr[i];
1606 /* The lower four bits are the media type. */
1607 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1608 if (options[board_idx] & MEDIA_MASK)
1609 tp->default_port = options[board_idx] & MEDIA_MASK;
1610 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1611 tp->full_duplex = 1;
1612 if (mtu[board_idx] > 0)
1613 dev->mtu = mtu[board_idx];
1615 if (dev->mem_start & MEDIA_MASK)
1616 tp->default_port = dev->mem_start & MEDIA_MASK;
1617 if (tp->default_port) {
1618 pr_info(DRV_NAME "%d: Transceiver selection forced to %s\n",
1619 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1621 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1622 tp->full_duplex = 1;
1624 if (tp->full_duplex)
1625 tp->full_duplex_lock = 1;
1627 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1628 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1629 tp->mii_advertise = media2advert[tp->default_port - 9];
1630 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1633 if (tp->flags & HAS_MEDIA_TABLE) {
1634 sprintf(dev->name, DRV_NAME "%d", board_idx); /* hack */
1635 tulip_parse_eeprom(dev);
1636 strcpy(dev->name, "eth%d"); /* un-hack */
1639 if ((tp->flags & ALWAYS_CHECK_MII) ||
1640 (tp->mtable && tp->mtable->has_mii) ||
1641 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1642 if (tp->mtable && tp->mtable->has_mii) {
1643 for (i = 0; i < tp->mtable->leafcount; i++)
1644 if (tp->mtable->mleaf[i].media == 11) {
1646 tp->saved_if_port = dev->if_port;
1647 tulip_select_media(dev, 2);
1648 dev->if_port = tp->saved_if_port;
1653 /* Find the connected MII xcvrs.
1654 Doing this in open() would allow detecting external xcvrs
1655 later, but takes much time. */
1656 tulip_find_mii (dev, board_idx);
1659 /* The Tulip-specific entries in the device structure. */
1660 dev->netdev_ops = &tulip_netdev_ops;
1661 dev->watchdog_timeo = TX_TIMEOUT;
1662 #ifdef CONFIG_TULIP_NAPI
1663 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1665 SET_ETHTOOL_OPS(dev, &ops);
1667 if (register_netdev(dev))
1668 goto err_out_free_ring;
1670 pci_set_drvdata(pdev, dev);
1673 #ifdef CONFIG_TULIP_MMIO
1674 "%s rev %d at MMIO %#llx,%s %pM, IRQ %d\n",
1676 "%s rev %d at Port %#llx,%s %pM, IRQ %d\n",
1678 chip_name, pdev->revision,
1679 (unsigned long long)pci_resource_start(pdev, TULIP_BAR),
1680 eeprom_missing ? " EEPROM not present," : "",
1681 dev->dev_addr, irq);
1683 if (tp->chip_id == PNIC2)
1684 tp->link_change = pnic2_lnk_change;
1685 else if (tp->flags & HAS_NWAY)
1686 tp->link_change = t21142_lnk_change;
1687 else if (tp->flags & HAS_PNICNWAY)
1688 tp->link_change = pnic_lnk_change;
1690 /* Reset the xcvr interface and turn on heartbeat. */
1696 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1699 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1700 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1701 iowrite32(0x0000, ioaddr + CSR13);
1702 iowrite32(0x0000, ioaddr + CSR14);
1703 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1705 t21142_start_nway(dev);
1708 /* just do a reset for sanity sake */
1709 iowrite32(0x0000, ioaddr + CSR13);
1710 iowrite32(0x0000, ioaddr + CSR14);
1713 if ( ! tp->mii_cnt) {
1716 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1717 iowrite32(0x30, ioaddr + CSR12);
1718 iowrite32(0x0001F078, ioaddr + CSR6);
1719 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1724 iowrite32(0x00000000, ioaddr + CSR6);
1725 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1726 iowrite32(0x00000001, ioaddr + CSR13);
1730 iowrite32(0x01a80000, ioaddr + CSR6);
1731 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1732 iowrite32(0x00001000, ioaddr + CSR12);
1735 /* No initialization necessary. */
1739 /* put the chip in snooze mode until opened */
1740 tulip_set_power_state (tp, 0, 1);
1745 pci_free_consistent (pdev,
1746 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1747 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1748 tp->rx_ring, tp->rx_ring_dma);
1752 pci_iounmap(pdev, ioaddr);
1755 pci_release_regions (pdev);
1757 err_out_free_netdev:
1765 static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1767 struct net_device *dev = pci_get_drvdata(pdev);
1772 if (!netif_running(dev))
1777 netif_device_detach(dev);
1778 free_irq(dev->irq, dev);
1781 pci_save_state(pdev);
1782 pci_disable_device(pdev);
1783 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1789 static int tulip_resume(struct pci_dev *pdev)
1791 struct net_device *dev = pci_get_drvdata(pdev);
1797 pci_set_power_state(pdev, PCI_D0);
1798 pci_restore_state(pdev);
1800 if (!netif_running(dev))
1803 if ((retval = pci_enable_device(pdev))) {
1804 pr_err(PFX "pci_enable_device failed in resume\n");
1808 if ((retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1809 pr_err(PFX "request_irq failed in resume\n");
1813 netif_device_attach(dev);
1815 if (netif_running(dev))
1821 #endif /* CONFIG_PM */
1824 static void __devexit tulip_remove_one (struct pci_dev *pdev)
1826 struct net_device *dev = pci_get_drvdata (pdev);
1827 struct tulip_private *tp;
1832 tp = netdev_priv(dev);
1833 unregister_netdev(dev);
1834 pci_free_consistent (pdev,
1835 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1836 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1837 tp->rx_ring, tp->rx_ring_dma);
1839 pci_iounmap(pdev, tp->base_addr);
1841 pci_release_regions (pdev);
1842 pci_set_drvdata (pdev, NULL);
1844 /* pci_power_off (pdev, -1); */
1847 #ifdef CONFIG_NET_POLL_CONTROLLER
1849 * Polling 'interrupt' - used by things like netconsole to send skbs
1850 * without having to re-enable interrupts. It's not called while
1851 * the interrupt routine is executing.
1854 static void poll_tulip (struct net_device *dev)
1856 /* disable_irq here is not very nice, but with the lockless
1857 interrupt handler we have no other choice. */
1858 disable_irq(dev->irq);
1859 tulip_interrupt (dev->irq, dev);
1860 enable_irq(dev->irq);
1864 static struct pci_driver tulip_driver = {
1866 .id_table = tulip_pci_tbl,
1867 .probe = tulip_init_one,
1868 .remove = __devexit_p(tulip_remove_one),
1870 .suspend = tulip_suspend,
1871 .resume = tulip_resume,
1872 #endif /* CONFIG_PM */
1876 static int __init tulip_init (void)
1879 pr_info("%s", version);
1882 /* copy module parms into globals */
1883 tulip_rx_copybreak = rx_copybreak;
1884 tulip_max_interrupt_work = max_interrupt_work;
1886 /* probe for and init boards */
1887 return pci_register_driver(&tulip_driver);
1891 static void __exit tulip_cleanup (void)
1893 pci_unregister_driver (&tulip_driver);
1897 module_init(tulip_init);
1898 module_exit(tulip_cleanup);