drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.106"
  72 #define DRV_MODULE_RELDATE      "January 12, 2010"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 #define TG3_RX_STD_BUFF_RING_SIZE \
 141         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 142
 143 #define TG3_RX_JMB_BUFF_RING_SIZE \
 144         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 145
 146 /* minimum number of free TX descriptors required to wake up TX process */
 147 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 148
 149 #define TG3_RAW_IP_ALIGN 2
 150
 151 /* number of ETHTOOL_GSTATS u64's */
 152 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 153
 154 #define TG3_NUM_TEST            6
 155
 156 #define FIRMWARE_TG3            "tigon/tg3.bin"
 157 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 158 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 159
 160 static char version[] __devinitdata =
 161         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 162
 163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 165 MODULE_LICENSE("GPL");
 166 MODULE_VERSION(DRV_MODULE_VERSION);
 167 MODULE_FIRMWARE(FIRMWARE_TG3);
 168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 170
 171 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 172
 173 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 174 module_param(tg3_debug, int, 0);
 175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 176
 177 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 260         {}
 261 };
 262
 263 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 264
 265 static const struct {
 266         const char string[ETH_GSTRING_LEN];
 267 } ethtool_stats_keys[TG3_NUM_STATS] = {
 268         { "rx_octets" },
 269         { "rx_fragments" },
 270         { "rx_ucast_packets" },
 271         { "rx_mcast_packets" },
 272         { "rx_bcast_packets" },
 273         { "rx_fcs_errors" },
 274         { "rx_align_errors" },
 275         { "rx_xon_pause_rcvd" },
 276         { "rx_xoff_pause_rcvd" },
 277         { "rx_mac_ctrl_rcvd" },
 278         { "rx_xoff_entered" },
 279         { "rx_frame_too_long_errors" },
 280         { "rx_jabbers" },
 281         { "rx_undersize_packets" },
 282         { "rx_in_length_errors" },
 283         { "rx_out_length_errors" },
 284         { "rx_64_or_less_octet_packets" },
 285         { "rx_65_to_127_octet_packets" },
 286         { "rx_128_to_255_octet_packets" },
 287         { "rx_256_to_511_octet_packets" },
 288         { "rx_512_to_1023_octet_packets" },
 289         { "rx_1024_to_1522_octet_packets" },
 290         { "rx_1523_to_2047_octet_packets" },
 291         { "rx_2048_to_4095_octet_packets" },
 292         { "rx_4096_to_8191_octet_packets" },
 293         { "rx_8192_to_9022_octet_packets" },
 294
 295         { "tx_octets" },
 296         { "tx_collisions" },
 297
 298         { "tx_xon_sent" },
 299         { "tx_xoff_sent" },
 300         { "tx_flow_control" },
 301         { "tx_mac_errors" },
 302         { "tx_single_collisions" },
 303         { "tx_mult_collisions" },
 304         { "tx_deferred" },
 305         { "tx_excessive_collisions" },
 306         { "tx_late_collisions" },
 307         { "tx_collide_2times" },
 308         { "tx_collide_3times" },
 309         { "tx_collide_4times" },
 310         { "tx_collide_5times" },
 311         { "tx_collide_6times" },
 312         { "tx_collide_7times" },
 313         { "tx_collide_8times" },
 314         { "tx_collide_9times" },
 315         { "tx_collide_10times" },
 316         { "tx_collide_11times" },
 317         { "tx_collide_12times" },
 318         { "tx_collide_13times" },
 319         { "tx_collide_14times" },
 320         { "tx_collide_15times" },
 321         { "tx_ucast_packets" },
 322         { "tx_mcast_packets" },
 323         { "tx_bcast_packets" },
 324         { "tx_carrier_sense_errors" },
 325         { "tx_discards" },
 326         { "tx_errors" },
 327
 328         { "dma_writeq_full" },
 329         { "dma_write_prioq_full" },
 330         { "rxbds_empty" },
 331         { "rx_discards" },
 332         { "rx_errors" },
 333         { "rx_threshold_hit" },
 334
 335         { "dma_readq_full" },
 336         { "dma_read_prioq_full" },
 337         { "tx_comp_queue_full" },
 338
 339         { "ring_set_send_prod_index" },
 340         { "ring_status_update" },
 341         { "nic_irqs" },
 342         { "nic_avoided_irqs" },
 343         { "nic_tx_threshold_hit" }
 344 };
 345
 346 static const struct {
 347         const char string[ETH_GSTRING_LEN];
 348 } ethtool_test_keys[TG3_NUM_TEST] = {
 349         { "nvram test     (online) " },
 350         { "link test      (online) " },
 351         { "register test  (offline)" },
 352         { "memory test    (offline)" },
 353         { "loopback test  (offline)" },
 354         { "interrupt test (offline)" },
 355 };
 356
 357 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 358 {
 359         writel(val, tp->regs + off);
 360 }
 361
 362 static u32 tg3_read32(struct tg3 *tp, u32 off)
 363 {
 364         return (readl(tp->regs + off));
 365 }
 366
 367 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 368 {
 369         writel(val, tp->aperegs + off);
 370 }
 371
 372 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 373 {
 374         return (readl(tp->aperegs + off));
 375 }
 376
 377 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 378 {
 379         unsigned long flags;
 380
 381         spin_lock_irqsave(&tp->indirect_lock, flags);
 382         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 383         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 384         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 385 }
 386
 387 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 388 {
 389         writel(val, tp->regs + off);
 390         readl(tp->regs + off);
 391 }
 392
 393 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 394 {
 395         unsigned long flags;
 396         u32 val;
 397
 398         spin_lock_irqsave(&tp->indirect_lock, flags);
 399         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 400         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 401         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 402         return val;
 403 }
 404
 405 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 406 {
 407         unsigned long flags;
 408
 409         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 410                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 411                                        TG3_64BIT_REG_LOW, val);
 412                 return;
 413         }
 414         if (off == TG3_RX_STD_PROD_IDX_REG) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 416                                        TG3_64BIT_REG_LOW, val);
 417                 return;
 418         }
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 422         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424
 425         /* In indirect mode when disabling interrupts, we also need
 426          * to clear the interrupt bit in the GRC local ctrl register.
 427          */
 428         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 429             (val == 0x1)) {
 430                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 431                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 432         }
 433 }
 434
 435 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 436 {
 437         unsigned long flags;
 438         u32 val;
 439
 440         spin_lock_irqsave(&tp->indirect_lock, flags);
 441         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 442         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 443         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 444         return val;
 445 }
 446
 447 /* usec_wait specifies the wait time in usec when writing to certain registers
 448  * where it is unsafe to read back the register without some delay.
 449  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 450  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 451  */
 452 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 453 {
 454         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 455             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 456                 /* Non-posted methods */
 457                 tp->write32(tp, off, val);
 458         else {
 459                 /* Posted method */
 460                 tg3_write32(tp, off, val);
 461                 if (usec_wait)
 462                         udelay(usec_wait);
 463                 tp->read32(tp, off);
 464         }
 465         /* Wait again after the read for the posted method to guarantee that
 466          * the wait time is met.
 467          */
 468         if (usec_wait)
 469                 udelay(usec_wait);
 470 }
 471
 472 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 473 {
 474         tp->write32_mbox(tp, off, val);
 475         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 476             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 477                 tp->read32_mbox(tp, off);
 478 }
 479
 480 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         void __iomem *mbox = tp->regs + off;
 483         writel(val, mbox);
 484         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 485                 writel(val, mbox);
 486         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 487                 readl(mbox);
 488 }
 489
 490 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 491 {
 492         return (readl(tp->regs + off + GRCMBOX_BASE));
 493 }
 494
 495 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 496 {
 497         writel(val, tp->regs + off + GRCMBOX_BASE);
 498 }
 499
 500 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 501 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 502 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 503 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 504 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 505
 506 #define tw32(reg,val)           tp->write32(tp, reg, val)
 507 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 508 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 509 #define tr32(reg)               tp->read32(tp, reg)
 510
 511 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 512 {
 513         unsigned long flags;
 514
 515         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 516             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 517                 return;
 518
 519         spin_lock_irqsave(&tp->indirect_lock, flags);
 520         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 521                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 523
 524                 /* Always leave this as zero. */
 525                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 526         } else {
 527                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 528                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 529
 530                 /* Always leave this as zero. */
 531                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 532         }
 533         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 534 }
 535
 536 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 537 {
 538         unsigned long flags;
 539
 540         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 541             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 542                 *val = 0;
 543                 return;
 544         }
 545
 546         spin_lock_irqsave(&tp->indirect_lock, flags);
 547         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 548                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 549                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 550
 551                 /* Always leave this as zero. */
 552                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 553         } else {
 554                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 555                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 556
 557                 /* Always leave this as zero. */
 558                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 559         }
 560         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 561 }
 562
 563 static void tg3_ape_lock_init(struct tg3 *tp)
 564 {
 565         int i;
 566
 567         /* Make sure the driver hasn't any stale locks. */
 568         for (i = 0; i < 8; i++)
 569                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 570                                 APE_LOCK_GRANT_DRIVER);
 571 }
 572
 573 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 574 {
 575         int i, off;
 576         int ret = 0;
 577         u32 status;
 578
 579         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 580                 return 0;
 581
 582         switch (locknum) {
 583                 case TG3_APE_LOCK_GRC:
 584                 case TG3_APE_LOCK_MEM:
 585                         break;
 586                 default:
 587                         return -EINVAL;
 588         }
 589
 590         off = 4 * locknum;
 591
 592         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 593
 594         /* Wait for up to 1 millisecond to acquire lock. */
 595         for (i = 0; i < 100; i++) {
 596                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 597                 if (status == APE_LOCK_GRANT_DRIVER)
 598                         break;
 599                 udelay(10);
 600         }
 601
 602         if (status != APE_LOCK_GRANT_DRIVER) {
 603                 /* Revoke the lock request. */
 604                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 605                                 APE_LOCK_GRANT_DRIVER);
 606
 607                 ret = -EBUSY;
 608         }
 609
 610         return ret;
 611 }
 612
 613 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 614 {
 615         int off;
 616
 617         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 618                 return;
 619
 620         switch (locknum) {
 621                 case TG3_APE_LOCK_GRC:
 622                 case TG3_APE_LOCK_MEM:
 623                         break;
 624                 default:
 625                         return;
 626         }
 627
 628         off = 4 * locknum;
 629         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 630 }
 631
 632 static void tg3_disable_ints(struct tg3 *tp)
 633 {
 634         int i;
 635
 636         tw32(TG3PCI_MISC_HOST_CTRL,
 637              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 638         for (i = 0; i < tp->irq_max; i++)
 639                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 640 }
 641
 642 static void tg3_enable_ints(struct tg3 *tp)
 643 {
 644         int i;
 645
 646         tp->irq_sync = 0;
 647         wmb();
 648
 649         tw32(TG3PCI_MISC_HOST_CTRL,
 650              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 651
 652         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 653         for (i = 0; i < tp->irq_cnt; i++) {
 654                 struct tg3_napi *tnapi = &tp->napi[i];
 655                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 656                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 657                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 658
 659                 tp->coal_now |= tnapi->coal_now;
 660         }
 661
 662         /* Force an initial interrupt */
 663         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 664             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 665                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 666         else
 667                 tw32(HOSTCC_MODE, tp->coal_now);
 668
 669         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 670 }
 671
 672 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 673 {
 674         struct tg3 *tp = tnapi->tp;
 675         struct tg3_hw_status *sblk = tnapi->hw_status;
 676         unsigned int work_exists = 0;
 677
 678         /* check for phy events */
 679         if (!(tp->tg3_flags &
 680               (TG3_FLAG_USE_LINKCHG_REG |
 681                TG3_FLAG_POLL_SERDES))) {
 682                 if (sblk->status & SD_STATUS_LINK_CHG)
 683                         work_exists = 1;
 684         }
 685         /* check for RX/TX work to do */
 686         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 687             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 688                 work_exists = 1;
 689
 690         return work_exists;
 691 }
 692
 693 /* tg3_int_reenable
 694  *  similar to tg3_enable_ints, but it accurately determines whether there
 695  *  is new work pending and can return without flushing the PIO write
 696  *  which reenables interrupts
 697  */
 698 static void tg3_int_reenable(struct tg3_napi *tnapi)
 699 {
 700         struct tg3 *tp = tnapi->tp;
 701
 702         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 703         mmiowb();
 704
 705         /* When doing tagged status, this work check is unnecessary.
 706          * The last_tag we write above tells the chip which piece of
 707          * work we've completed.
 708          */
 709         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 710             tg3_has_work(tnapi))
 711                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 712                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 713 }
 714
 715 static void tg3_napi_disable(struct tg3 *tp)
 716 {
 717         int i;
 718
 719         for (i = tp->irq_cnt - 1; i >= 0; i--)
 720                 napi_disable(&tp->napi[i].napi);
 721 }
 722
 723 static void tg3_napi_enable(struct tg3 *tp)
 724 {
 725         int i;
 726
 727         for (i = 0; i < tp->irq_cnt; i++)
 728                 napi_enable(&tp->napi[i].napi);
 729 }
 730
 731 static inline void tg3_netif_stop(struct tg3 *tp)
 732 {
 733         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 734         tg3_napi_disable(tp);
 735         netif_tx_disable(tp->dev);
 736 }
 737
 738 static inline void tg3_netif_start(struct tg3 *tp)
 739 {
 740         /* NOTE: unconditional netif_tx_wake_all_queues is only
 741          * appropriate so long as all callers are assured to
 742          * have free tx slots (such as after tg3_init_hw)
 743          */
 744         netif_tx_wake_all_queues(tp->dev);
 745
 746         tg3_napi_enable(tp);
 747         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 748         tg3_enable_ints(tp);
 749 }
 750
 751 static void tg3_switch_clocks(struct tg3 *tp)
 752 {
 753         u32 clock_ctrl;
 754         u32 orig_clock_ctrl;
 755
 756         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 757             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 758                 return;
 759
 760         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 761
 762         orig_clock_ctrl = clock_ctrl;
 763         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 764                        CLOCK_CTRL_CLKRUN_OENABLE |
 765                        0x1f);
 766         tp->pci_clock_ctrl = clock_ctrl;
 767
 768         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 769                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 770                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 771                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 772                 }
 773         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 774                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 775                             clock_ctrl |
 776                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 777                             40);
 778                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 779                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 780                             40);
 781         }
 782         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 783 }
 784
 785 #define PHY_BUSY_LOOPS  5000
 786
 787 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 788 {
 789         u32 frame_val;
 790         unsigned int loops;
 791         int ret;
 792
 793         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 794                 tw32_f(MAC_MI_MODE,
 795                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 796                 udelay(80);
 797         }
 798
 799         *val = 0x0;
 800
 801         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 802                       MI_COM_PHY_ADDR_MASK);
 803         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 804                       MI_COM_REG_ADDR_MASK);
 805         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 806
 807         tw32_f(MAC_MI_COM, frame_val);
 808
 809         loops = PHY_BUSY_LOOPS;
 810         while (loops != 0) {
 811                 udelay(10);
 812                 frame_val = tr32(MAC_MI_COM);
 813
 814                 if ((frame_val & MI_COM_BUSY) == 0) {
 815                         udelay(5);
 816                         frame_val = tr32(MAC_MI_COM);
 817                         break;
 818                 }
 819                 loops -= 1;
 820         }
 821
 822         ret = -EBUSY;
 823         if (loops != 0) {
 824                 *val = frame_val & MI_COM_DATA_MASK;
 825                 ret = 0;
 826         }
 827
 828         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 829                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 830                 udelay(80);
 831         }
 832
 833         return ret;
 834 }
 835
 836 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 837 {
 838         u32 frame_val;
 839         unsigned int loops;
 840         int ret;
 841
 842         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 843             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 844                 return 0;
 845
 846         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 847                 tw32_f(MAC_MI_MODE,
 848                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 849                 udelay(80);
 850         }
 851
 852         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 853                       MI_COM_PHY_ADDR_MASK);
 854         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 855                       MI_COM_REG_ADDR_MASK);
 856         frame_val |= (val & MI_COM_DATA_MASK);
 857         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 858
 859         tw32_f(MAC_MI_COM, frame_val);
 860
 861         loops = PHY_BUSY_LOOPS;
 862         while (loops != 0) {
 863                 udelay(10);
 864                 frame_val = tr32(MAC_MI_COM);
 865                 if ((frame_val & MI_COM_BUSY) == 0) {
 866                         udelay(5);
 867                         frame_val = tr32(MAC_MI_COM);
 868                         break;
 869                 }
 870                 loops -= 1;
 871         }
 872
 873         ret = -EBUSY;
 874         if (loops != 0)
 875                 ret = 0;
 876
 877         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 878                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 879                 udelay(80);
 880         }
 881
 882         return ret;
 883 }
 884
 885 static int tg3_bmcr_reset(struct tg3 *tp)
 886 {
 887         u32 phy_control;
 888         int limit, err;
 889
 890         /* OK, reset it, and poll the BMCR_RESET bit until it
 891          * clears or we time out.
 892          */
 893         phy_control = BMCR_RESET;
 894         err = tg3_writephy(tp, MII_BMCR, phy_control);
 895         if (err != 0)
 896                 return -EBUSY;
 897
 898         limit = 5000;
 899         while (limit--) {
 900                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 901                 if (err != 0)
 902                         return -EBUSY;
 903
 904                 if ((phy_control & BMCR_RESET) == 0) {
 905                         udelay(40);
 906                         break;
 907                 }
 908                 udelay(10);
 909         }
 910         if (limit < 0)
 911                 return -EBUSY;
 912
 913         return 0;
 914 }
 915
 916 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 917 {
 918         struct tg3 *tp = bp->priv;
 919         u32 val;
 920
 921         spin_lock_bh(&tp->lock);
 922
 923         if (tg3_readphy(tp, reg, &val))
 924                 val = -EIO;
 925
 926         spin_unlock_bh(&tp->lock);
 927
 928         return val;
 929 }
 930
 931 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 932 {
 933         struct tg3 *tp = bp->priv;
 934         u32 ret = 0;
 935
 936         spin_lock_bh(&tp->lock);
 937
 938         if (tg3_writephy(tp, reg, val))
 939                 ret = -EIO;
 940
 941         spin_unlock_bh(&tp->lock);
 942
 943         return ret;
 944 }
 945
 946 static int tg3_mdio_reset(struct mii_bus *bp)
 947 {
 948         return 0;
 949 }
 950
 951 static void tg3_mdio_config_5785(struct tg3 *tp)
 952 {
 953         u32 val;
 954         struct phy_device *phydev;
 955
 956         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 957         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 958         case TG3_PHY_ID_BCM50610:
 959         case TG3_PHY_ID_BCM50610M:
 960                 val = MAC_PHYCFG2_50610_LED_MODES;
 961                 break;
 962         case TG3_PHY_ID_BCMAC131:
 963                 val = MAC_PHYCFG2_AC131_LED_MODES;
 964                 break;
 965         case TG3_PHY_ID_RTL8211C:
 966                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 967                 break;
 968         case TG3_PHY_ID_RTL8201E:
 969                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 970                 break;
 971         default:
 972                 return;
 973         }
 974
 975         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 976                 tw32(MAC_PHYCFG2, val);
 977
 978                 val = tr32(MAC_PHYCFG1);
 979                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 980                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 981                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 982                 tw32(MAC_PHYCFG1, val);
 983
 984                 return;
 985         }
 986
 987         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 988                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 989                        MAC_PHYCFG2_FMODE_MASK_MASK |
 990                        MAC_PHYCFG2_GMODE_MASK_MASK |
 991                        MAC_PHYCFG2_ACT_MASK_MASK   |
 992                        MAC_PHYCFG2_QUAL_MASK_MASK |
 993                        MAC_PHYCFG2_INBAND_ENABLE;
 994
 995         tw32(MAC_PHYCFG2, val);
 996
 997         val = tr32(MAC_PHYCFG1);
 998         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 999                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1000         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1001                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1002                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1003                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1004                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1005         }
1006         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1007                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1008         tw32(MAC_PHYCFG1, val);
1009
1010         val = tr32(MAC_EXT_RGMII_MODE);
1011         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1012                  MAC_RGMII_MODE_RX_QUALITY |
1013                  MAC_RGMII_MODE_RX_ACTIVITY |
1014                  MAC_RGMII_MODE_RX_ENG_DET |
1015                  MAC_RGMII_MODE_TX_ENABLE |
1016                  MAC_RGMII_MODE_TX_LOWPWR |
1017                  MAC_RGMII_MODE_TX_RESET);
1018         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1019                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1020                         val |= MAC_RGMII_MODE_RX_INT_B |
1021                                MAC_RGMII_MODE_RX_QUALITY |
1022                                MAC_RGMII_MODE_RX_ACTIVITY |
1023                                MAC_RGMII_MODE_RX_ENG_DET;
1024                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1025                         val |= MAC_RGMII_MODE_TX_ENABLE |
1026                                MAC_RGMII_MODE_TX_LOWPWR |
1027                                MAC_RGMII_MODE_TX_RESET;
1028         }
1029         tw32(MAC_EXT_RGMII_MODE, val);
1030 }
1031
1032 static void tg3_mdio_start(struct tg3 *tp)
1033 {
1034         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1035         tw32_f(MAC_MI_MODE, tp->mi_mode);
1036         udelay(80);
1037
1038         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1039                 u32 funcnum, is_serdes;
1040
1041                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1042                 if (funcnum)
1043                         tp->phy_addr = 2;
1044                 else
1045                         tp->phy_addr = 1;
1046
1047                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1048                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1049                 else
1050                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1051                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1052                 if (is_serdes)
1053                         tp->phy_addr += 7;
1054         } else
1055                 tp->phy_addr = TG3_PHY_MII_ADDR;
1056
1057         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1058             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1059                 tg3_mdio_config_5785(tp);
1060 }
1061
1062 static int tg3_mdio_init(struct tg3 *tp)
1063 {
1064         int i;
1065         u32 reg;
1066         struct phy_device *phydev;
1067
1068         tg3_mdio_start(tp);
1069
1070         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1071             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1072                 return 0;
1073
1074         tp->mdio_bus = mdiobus_alloc();
1075         if (tp->mdio_bus == NULL)
1076                 return -ENOMEM;
1077
1078         tp->mdio_bus->name     = "tg3 mdio bus";
1079         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1080                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1081         tp->mdio_bus->priv     = tp;
1082         tp->mdio_bus->parent   = &tp->pdev->dev;
1083         tp->mdio_bus->read     = &tg3_mdio_read;
1084         tp->mdio_bus->write    = &tg3_mdio_write;
1085         tp->mdio_bus->reset    = &tg3_mdio_reset;
1086         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1087         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1088
1089         for (i = 0; i < PHY_MAX_ADDR; i++)
1090                 tp->mdio_bus->irq[i] = PHY_POLL;
1091
1092         /* The bus registration will look for all the PHYs on the mdio bus.
1093          * Unfortunately, it does not ensure the PHY is powered up before
1094          * accessing the PHY ID registers.  A chip reset is the
1095          * quickest way to bring the device back to an operational state..
1096          */
1097         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1098                 tg3_bmcr_reset(tp);
1099
1100         i = mdiobus_register(tp->mdio_bus);
1101         if (i) {
1102                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1103                         tp->dev->name, i);
1104                 mdiobus_free(tp->mdio_bus);
1105                 return i;
1106         }
1107
1108         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1109
1110         if (!phydev || !phydev->drv) {
1111                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1112                 mdiobus_unregister(tp->mdio_bus);
1113                 mdiobus_free(tp->mdio_bus);
1114                 return -ENODEV;
1115         }
1116
1117         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1118         case TG3_PHY_ID_BCM57780:
1119                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1120                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1121                 break;
1122         case TG3_PHY_ID_BCM50610:
1123         case TG3_PHY_ID_BCM50610M:
1124                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1125                                      PHY_BRCM_RX_REFCLK_UNUSED |
1126                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1127                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1128                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1129                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1131                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1134                 /* fallthru */
1135         case TG3_PHY_ID_RTL8211C:
1136                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1137                 break;
1138         case TG3_PHY_ID_RTL8201E:
1139         case TG3_PHY_ID_BCMAC131:
1140                 phydev->interface = PHY_INTERFACE_MODE_MII;
1141                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1142                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1143                 break;
1144         }
1145
1146         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1147
1148         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1149                 tg3_mdio_config_5785(tp);
1150
1151         return 0;
1152 }
1153
1154 static void tg3_mdio_fini(struct tg3 *tp)
1155 {
1156         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1157                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1158                 mdiobus_unregister(tp->mdio_bus);
1159                 mdiobus_free(tp->mdio_bus);
1160         }
1161 }
1162
1163 /* tp->lock is held. */
1164 static inline void tg3_generate_fw_event(struct tg3 *tp)
1165 {
1166         u32 val;
1167
1168         val = tr32(GRC_RX_CPU_EVENT);
1169         val |= GRC_RX_CPU_DRIVER_EVENT;
1170         tw32_f(GRC_RX_CPU_EVENT, val);
1171
1172         tp->last_event_jiffies = jiffies;
1173 }
1174
1175 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1176
1177 /* tp->lock is held. */
1178 static void tg3_wait_for_event_ack(struct tg3 *tp)
1179 {
1180         int i;
1181         unsigned int delay_cnt;
1182         long time_remain;
1183
1184         /* If enough time has passed, no wait is necessary. */
1185         time_remain = (long)(tp->last_event_jiffies + 1 +
1186                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1187                       (long)jiffies;
1188         if (time_remain < 0)
1189                 return;
1190
1191         /* Check if we can shorten the wait time. */
1192         delay_cnt = jiffies_to_usecs(time_remain);
1193         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1194                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1195         delay_cnt = (delay_cnt >> 3) + 1;
1196
1197         for (i = 0; i < delay_cnt; i++) {
1198                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1199                         break;
1200                 udelay(8);
1201         }
1202 }
1203
1204 /* tp->lock is held. */
1205 static void tg3_ump_link_report(struct tg3 *tp)
1206 {
1207         u32 reg;
1208         u32 val;
1209
1210         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1211             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1212                 return;
1213
1214         tg3_wait_for_event_ack(tp);
1215
1216         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1217
1218         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1219
1220         val = 0;
1221         if (!tg3_readphy(tp, MII_BMCR, &reg))
1222                 val = reg << 16;
1223         if (!tg3_readphy(tp, MII_BMSR, &reg))
1224                 val |= (reg & 0xffff);
1225         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1226
1227         val = 0;
1228         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1229                 val = reg << 16;
1230         if (!tg3_readphy(tp, MII_LPA, &reg))
1231                 val |= (reg & 0xffff);
1232         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1233
1234         val = 0;
1235         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1236                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1237                         val = reg << 16;
1238                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1239                         val |= (reg & 0xffff);
1240         }
1241         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1242
1243         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1244                 val = reg << 16;
1245         else
1246                 val = 0;
1247         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1248
1249         tg3_generate_fw_event(tp);
1250 }
1251
1252 static void tg3_link_report(struct tg3 *tp)
1253 {
1254         if (!netif_carrier_ok(tp->dev)) {
1255                 if (netif_msg_link(tp))
1256                         printk(KERN_INFO PFX "%s: Link is down.\n",
1257                                tp->dev->name);
1258                 tg3_ump_link_report(tp);
1259         } else if (netif_msg_link(tp)) {
1260                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1261                        tp->dev->name,
1262                        (tp->link_config.active_speed == SPEED_1000 ?
1263                         1000 :
1264                         (tp->link_config.active_speed == SPEED_100 ?
1265                          100 : 10)),
1266                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1267                         "full" : "half"));
1268
1269                 printk(KERN_INFO PFX
1270                        "%s: Flow control is %s for TX and %s for RX.\n",
1271                        tp->dev->name,
1272                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1273                        "on" : "off",
1274                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1275                        "on" : "off");
1276                 tg3_ump_link_report(tp);
1277         }
1278 }
1279
1280 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1281 {
1282         u16 miireg;
1283
1284         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1285                 miireg = ADVERTISE_PAUSE_CAP;
1286         else if (flow_ctrl & FLOW_CTRL_TX)
1287                 miireg = ADVERTISE_PAUSE_ASYM;
1288         else if (flow_ctrl & FLOW_CTRL_RX)
1289                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1290         else
1291                 miireg = 0;
1292
1293         return miireg;
1294 }
1295
1296 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1297 {
1298         u16 miireg;
1299
1300         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1301                 miireg = ADVERTISE_1000XPAUSE;
1302         else if (flow_ctrl & FLOW_CTRL_TX)
1303                 miireg = ADVERTISE_1000XPSE_ASYM;
1304         else if (flow_ctrl & FLOW_CTRL_RX)
1305                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1306         else
1307                 miireg = 0;
1308
1309         return miireg;
1310 }
1311
1312 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1313 {
1314         u8 cap = 0;
1315
1316         if (lcladv & ADVERTISE_1000XPAUSE) {
1317                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1318                         if (rmtadv & LPA_1000XPAUSE)
1319                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1320                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1321                                 cap = FLOW_CTRL_RX;
1322                 } else {
1323                         if (rmtadv & LPA_1000XPAUSE)
1324                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1325                 }
1326         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1327                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1328                         cap = FLOW_CTRL_TX;
1329         }
1330
1331         return cap;
1332 }
1333
1334 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1335 {
1336         u8 autoneg;
1337         u8 flowctrl = 0;
1338         u32 old_rx_mode = tp->rx_mode;
1339         u32 old_tx_mode = tp->tx_mode;
1340
1341         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1342                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1343         else
1344                 autoneg = tp->link_config.autoneg;
1345
1346         if (autoneg == AUTONEG_ENABLE &&
1347             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1348                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1349                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1350                 else
1351                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1352         } else
1353                 flowctrl = tp->link_config.flowctrl;
1354
1355         tp->link_config.active_flowctrl = flowctrl;
1356
1357         if (flowctrl & FLOW_CTRL_RX)
1358                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1359         else
1360                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1361
1362         if (old_rx_mode != tp->rx_mode)
1363                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1364
1365         if (flowctrl & FLOW_CTRL_TX)
1366                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1367         else
1368                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1369
1370         if (old_tx_mode != tp->tx_mode)
1371                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1372 }
1373
1374 static void tg3_adjust_link(struct net_device *dev)
1375 {
1376         u8 oldflowctrl, linkmesg = 0;
1377         u32 mac_mode, lcl_adv, rmt_adv;
1378         struct tg3 *tp = netdev_priv(dev);
1379         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1380
1381         spin_lock_bh(&tp->lock);
1382
1383         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1384                                     MAC_MODE_HALF_DUPLEX);
1385
1386         oldflowctrl = tp->link_config.active_flowctrl;
1387
1388         if (phydev->link) {
1389                 lcl_adv = 0;
1390                 rmt_adv = 0;
1391
1392                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1393                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1394                 else if (phydev->speed == SPEED_1000 ||
1395                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1396                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1397                 else
1398                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1399
1400                 if (phydev->duplex == DUPLEX_HALF)
1401                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1402                 else {
1403                         lcl_adv = tg3_advert_flowctrl_1000T(
1404                                   tp->link_config.flowctrl);
1405
1406                         if (phydev->pause)
1407                                 rmt_adv = LPA_PAUSE_CAP;
1408                         if (phydev->asym_pause)
1409                                 rmt_adv |= LPA_PAUSE_ASYM;
1410                 }
1411
1412                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1413         } else
1414                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1415
1416         if (mac_mode != tp->mac_mode) {
1417                 tp->mac_mode = mac_mode;
1418                 tw32_f(MAC_MODE, tp->mac_mode);
1419                 udelay(40);
1420         }
1421
1422         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1423                 if (phydev->speed == SPEED_10)
1424                         tw32(MAC_MI_STAT,
1425                              MAC_MI_STAT_10MBPS_MODE |
1426                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1427                 else
1428                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1429         }
1430
1431         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1432                 tw32(MAC_TX_LENGTHS,
1433                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1434                       (6 << TX_LENGTHS_IPG_SHIFT) |
1435                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1436         else
1437                 tw32(MAC_TX_LENGTHS,
1438                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1439                       (6 << TX_LENGTHS_IPG_SHIFT) |
1440                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1441
1442         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1443             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1444             phydev->speed != tp->link_config.active_speed ||
1445             phydev->duplex != tp->link_config.active_duplex ||
1446             oldflowctrl != tp->link_config.active_flowctrl)
1447             linkmesg = 1;
1448
1449         tp->link_config.active_speed = phydev->speed;
1450         tp->link_config.active_duplex = phydev->duplex;
1451
1452         spin_unlock_bh(&tp->lock);
1453
1454         if (linkmesg)
1455                 tg3_link_report(tp);
1456 }
1457
1458 static int tg3_phy_init(struct tg3 *tp)
1459 {
1460         struct phy_device *phydev;
1461
1462         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1463                 return 0;
1464
1465         /* Bring the PHY back to a known state. */
1466         tg3_bmcr_reset(tp);
1467
1468         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1469
1470         /* Attach the MAC to the PHY. */
1471         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1472                              phydev->dev_flags, phydev->interface);
1473         if (IS_ERR(phydev)) {
1474                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1475                 return PTR_ERR(phydev);
1476         }
1477
1478         /* Mask with MAC supported features. */
1479         switch (phydev->interface) {
1480         case PHY_INTERFACE_MODE_GMII:
1481         case PHY_INTERFACE_MODE_RGMII:
1482                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1483                         phydev->supported &= (PHY_GBIT_FEATURES |
1484                                               SUPPORTED_Pause |
1485                                               SUPPORTED_Asym_Pause);
1486                         break;
1487                 }
1488                 /* fallthru */
1489         case PHY_INTERFACE_MODE_MII:
1490                 phydev->supported &= (PHY_BASIC_FEATURES |
1491                                       SUPPORTED_Pause |
1492                                       SUPPORTED_Asym_Pause);
1493                 break;
1494         default:
1495                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1496                 return -EINVAL;
1497         }
1498
1499         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1500
1501         phydev->advertising = phydev->supported;
1502
1503         return 0;
1504 }
1505
1506 static void tg3_phy_start(struct tg3 *tp)
1507 {
1508         struct phy_device *phydev;
1509
1510         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511                 return;
1512
1513         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1514
1515         if (tp->link_config.phy_is_low_power) {
1516                 tp->link_config.phy_is_low_power = 0;
1517                 phydev->speed = tp->link_config.orig_speed;
1518                 phydev->duplex = tp->link_config.orig_duplex;
1519                 phydev->autoneg = tp->link_config.orig_autoneg;
1520                 phydev->advertising = tp->link_config.orig_advertising;
1521         }
1522
1523         phy_start(phydev);
1524
1525         phy_start_aneg(phydev);
1526 }
1527
1528 static void tg3_phy_stop(struct tg3 *tp)
1529 {
1530         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1531                 return;
1532
1533         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1534 }
1535
1536 static void tg3_phy_fini(struct tg3 *tp)
1537 {
1538         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1539                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1540                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1541         }
1542 }
1543
1544 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1545 {
1546         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1547         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1548 }
1549
1550 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1551 {
1552         u32 phytest;
1553
1554         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1555                 u32 phy;
1556
1557                 tg3_writephy(tp, MII_TG3_FET_TEST,
1558                              phytest | MII_TG3_FET_SHADOW_EN);
1559                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1560                         if (enable)
1561                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1562                         else
1563                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1564                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1565                 }
1566                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1567         }
1568 }
1569
1570 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1571 {
1572         u32 reg;
1573
1574         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1575                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1576              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1577                 return;
1578
1579         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1580                 tg3_phy_fet_toggle_apd(tp, enable);
1581                 return;
1582         }
1583
1584         reg = MII_TG3_MISC_SHDW_WREN |
1585               MII_TG3_MISC_SHDW_SCR5_SEL |
1586               MII_TG3_MISC_SHDW_SCR5_LPED |
1587               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1588               MII_TG3_MISC_SHDW_SCR5_SDTL |
1589               MII_TG3_MISC_SHDW_SCR5_C125OE;
1590         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1591                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1592
1593         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1594
1595
1596         reg = MII_TG3_MISC_SHDW_WREN |
1597               MII_TG3_MISC_SHDW_APD_SEL |
1598               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1599         if (enable)
1600                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1601
1602         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1603 }
1604
1605 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1606 {
1607         u32 phy;
1608
1609         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1610             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1611                 return;
1612
1613         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1614                 u32 ephy;
1615
1616                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1617                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1618
1619                         tg3_writephy(tp, MII_TG3_FET_TEST,
1620                                      ephy | MII_TG3_FET_SHADOW_EN);
1621                         if (!tg3_readphy(tp, reg, &phy)) {
1622                                 if (enable)
1623                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1624                                 else
1625                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1626                                 tg3_writephy(tp, reg, phy);
1627                         }
1628                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1629                 }
1630         } else {
1631                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1632                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1633                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1634                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1635                         if (enable)
1636                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1637                         else
1638                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1639                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1640                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1641                 }
1642         }
1643 }
1644
1645 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1646 {
1647         u32 val;
1648
1649         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1650                 return;
1651
1652         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1653             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1654                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1655                              (val | (1 << 15) | (1 << 4)));
1656 }
1657
1658 static void tg3_phy_apply_otp(struct tg3 *tp)
1659 {
1660         u32 otp, phy;
1661
1662         if (!tp->phy_otp)
1663                 return;
1664
1665         otp = tp->phy_otp;
1666
1667         /* Enable SM_DSP clock and tx 6dB coding. */
1668         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1669               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1670               MII_TG3_AUXCTL_ACTL_TX_6DB;
1671         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1672
1673         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1674         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1675         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1676
1677         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1678               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1679         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1680
1681         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1682         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1683         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1684
1685         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1686         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1687
1688         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1689         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1690
1691         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1692               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1693         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1694
1695         /* Turn off SM_DSP clock. */
1696         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1697               MII_TG3_AUXCTL_ACTL_TX_6DB;
1698         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1699 }
1700
1701 static int tg3_wait_macro_done(struct tg3 *tp)
1702 {
1703         int limit = 100;
1704
1705         while (limit--) {
1706                 u32 tmp32;
1707
1708                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1709                         if ((tmp32 & 0x1000) == 0)
1710                                 break;
1711                 }
1712         }
1713         if (limit < 0)
1714                 return -EBUSY;
1715
1716         return 0;
1717 }
1718
1719 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1720 {
1721         static const u32 test_pat[4][6] = {
1722         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1723         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1724         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1725         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1726         };
1727         int chan;
1728
1729         for (chan = 0; chan < 4; chan++) {
1730                 int i;
1731
1732                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1733                              (chan * 0x2000) | 0x0200);
1734                 tg3_writephy(tp, 0x16, 0x0002);
1735
1736                 for (i = 0; i < 6; i++)
1737                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1738                                      test_pat[chan][i]);
1739
1740                 tg3_writephy(tp, 0x16, 0x0202);
1741                 if (tg3_wait_macro_done(tp)) {
1742                         *resetp = 1;
1743                         return -EBUSY;
1744                 }
1745
1746                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1747                              (chan * 0x2000) | 0x0200);
1748                 tg3_writephy(tp, 0x16, 0x0082);
1749                 if (tg3_wait_macro_done(tp)) {
1750                         *resetp = 1;
1751                         return -EBUSY;
1752                 }
1753
1754                 tg3_writephy(tp, 0x16, 0x0802);
1755                 if (tg3_wait_macro_done(tp)) {
1756                         *resetp = 1;
1757                         return -EBUSY;
1758                 }
1759
1760                 for (i = 0; i < 6; i += 2) {
1761                         u32 low, high;
1762
1763                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1764                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1765                             tg3_wait_macro_done(tp)) {
1766                                 *resetp = 1;
1767                                 return -EBUSY;
1768                         }
1769                         low &= 0x7fff;
1770                         high &= 0x000f;
1771                         if (low != test_pat[chan][i] ||
1772                             high != test_pat[chan][i+1]) {
1773                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1774                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1775                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1776
1777                                 return -EBUSY;
1778                         }
1779                 }
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1786 {
1787         int chan;
1788
1789         for (chan = 0; chan < 4; chan++) {
1790                 int i;
1791
1792                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1793                              (chan * 0x2000) | 0x0200);
1794                 tg3_writephy(tp, 0x16, 0x0002);
1795                 for (i = 0; i < 6; i++)
1796                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1797                 tg3_writephy(tp, 0x16, 0x0202);
1798                 if (tg3_wait_macro_done(tp))
1799                         return -EBUSY;
1800         }
1801
1802         return 0;
1803 }
1804
1805 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1806 {
1807         u32 reg32, phy9_orig;
1808         int retries, do_phy_reset, err;
1809
1810         retries = 10;
1811         do_phy_reset = 1;
1812         do {
1813                 if (do_phy_reset) {
1814                         err = tg3_bmcr_reset(tp);
1815                         if (err)
1816                                 return err;
1817                         do_phy_reset = 0;
1818                 }
1819
1820                 /* Disable transmitter and interrupt.  */
1821                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1822                         continue;
1823
1824                 reg32 |= 0x3000;
1825                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1826
1827                 /* Set full-duplex, 1000 mbps.  */
1828                 tg3_writephy(tp, MII_BMCR,
1829                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1830
1831                 /* Set to master mode.  */
1832                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1833                         continue;
1834
1835                 tg3_writephy(tp, MII_TG3_CTRL,
1836                              (MII_TG3_CTRL_AS_MASTER |
1837                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1838
1839                 /* Enable SM_DSP_CLOCK and 6dB.  */
1840                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1841
1842                 /* Block the PHY control access.  */
1843                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1844                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1845
1846                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1847                 if (!err)
1848                         break;
1849         } while (--retries);
1850
1851         err = tg3_phy_reset_chanpat(tp);
1852         if (err)
1853                 return err;
1854
1855         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1856         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1857
1858         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1859         tg3_writephy(tp, 0x16, 0x0000);
1860
1861         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1862             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1863                 /* Set Extended packet length bit for jumbo frames */
1864                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1865         }
1866         else {
1867                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1868         }
1869
1870         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1871
1872         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1873                 reg32 &= ~0x3000;
1874                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1875         } else if (!err)
1876                 err = -EBUSY;
1877
1878         return err;
1879 }
1880
1881 /* This will reset the tigon3 PHY if there is no valid
1882  * link unless the FORCE argument is non-zero.
1883  */
1884 static int tg3_phy_reset(struct tg3 *tp)
1885 {
1886         u32 cpmuctrl;
1887         u32 phy_status;
1888         int err;
1889
1890         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1891                 u32 val;
1892
1893                 val = tr32(GRC_MISC_CFG);
1894                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1895                 udelay(40);
1896         }
1897         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1898         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1899         if (err != 0)
1900                 return -EBUSY;
1901
1902         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1903                 netif_carrier_off(tp->dev);
1904                 tg3_link_report(tp);
1905         }
1906
1907         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1908             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1909             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1910                 err = tg3_phy_reset_5703_4_5(tp);
1911                 if (err)
1912                         return err;
1913                 goto out;
1914         }
1915
1916         cpmuctrl = 0;
1917         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1918             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1919                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1920                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1921                         tw32(TG3_CPMU_CTRL,
1922                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1923         }
1924
1925         err = tg3_bmcr_reset(tp);
1926         if (err)
1927                 return err;
1928
1929         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1930                 u32 phy;
1931
1932                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1933                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1934
1935                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1936         }
1937
1938         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1939             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1940                 u32 val;
1941
1942                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1943                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1944                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1945                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1946                         udelay(40);
1947                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1948                 }
1949         }
1950
1951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1952             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1953                 return 0;
1954
1955         tg3_phy_apply_otp(tp);
1956
1957         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1958                 tg3_phy_toggle_apd(tp, true);
1959         else
1960                 tg3_phy_toggle_apd(tp, false);
1961
1962 out:
1963         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1964                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1965                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1966                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1967                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1968                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1970         }
1971         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1972                 tg3_writephy(tp, 0x1c, 0x8d68);
1973                 tg3_writephy(tp, 0x1c, 0x8d68);
1974         }
1975         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1976                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1977                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1978                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1979                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1980                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1981                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1982                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1983                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1984         }
1985         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1986                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1987                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1988                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1989                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1990                         tg3_writephy(tp, MII_TG3_TEST1,
1991                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1992                 } else
1993                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1994                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1995         }
1996         /* Set Extended packet length bit (bit 14) on all chips that */
1997         /* support jumbo frames */
1998         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1999                 /* Cannot do read-modify-write on 5401 */
2000                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2001         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2002                 u32 phy_reg;
2003
2004                 /* Set bit 14 with read-modify-write to preserve other bits */
2005                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2006                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2007                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2008         }
2009
2010         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2011          * jumbo frames transmission.
2012          */
2013         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2014                 u32 phy_reg;
2015
2016                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2017                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
2018                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2019         }
2020
2021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2022                 /* adjust output voltage */
2023                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2024         }
2025
2026         tg3_phy_toggle_automdix(tp, 1);
2027         tg3_phy_set_wirespeed(tp);
2028         return 0;
2029 }
2030
2031 static void tg3_frob_aux_power(struct tg3 *tp)
2032 {
2033         struct tg3 *tp_peer = tp;
2034
2035         /* The GPIOs do something completely different on 57765. */
2036         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2038                 return;
2039
2040         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2041             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2042             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2043                 struct net_device *dev_peer;
2044
2045                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2046                 /* remove_one() may have been run on the peer. */
2047                 if (!dev_peer)
2048                         tp_peer = tp;
2049                 else
2050                         tp_peer = netdev_priv(dev_peer);
2051         }
2052
2053         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2054             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2055             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2056             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2057                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2058                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2059                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2060                                     (GRC_LCLCTRL_GPIO_OE0 |
2061                                      GRC_LCLCTRL_GPIO_OE1 |
2062                                      GRC_LCLCTRL_GPIO_OE2 |
2063                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2064                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2065                                     100);
2066                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2067                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2068                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2069                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2070                                              GRC_LCLCTRL_GPIO_OE1 |
2071                                              GRC_LCLCTRL_GPIO_OE2 |
2072                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2073                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2074                                              tp->grc_local_ctrl;
2075                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2076
2077                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2078                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2079
2080                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2081                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2082                 } else {
2083                         u32 no_gpio2;
2084                         u32 grc_local_ctrl = 0;
2085
2086                         if (tp_peer != tp &&
2087                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2088                                 return;
2089
2090                         /* Workaround to prevent overdrawing Amps. */
2091                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2092                             ASIC_REV_5714) {
2093                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2094                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095                                             grc_local_ctrl, 100);
2096                         }
2097
2098                         /* On 5753 and variants, GPIO2 cannot be used. */
2099                         no_gpio2 = tp->nic_sram_data_cfg &
2100                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2101
2102                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2103                                          GRC_LCLCTRL_GPIO_OE1 |
2104                                          GRC_LCLCTRL_GPIO_OE2 |
2105                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2106                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2107                         if (no_gpio2) {
2108                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2109                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2110                         }
2111                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112                                                     grc_local_ctrl, 100);
2113
2114                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2115
2116                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2117                                                     grc_local_ctrl, 100);
2118
2119                         if (!no_gpio2) {
2120                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2121                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122                                             grc_local_ctrl, 100);
2123                         }
2124                 }
2125         } else {
2126                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2127                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2128                         if (tp_peer != tp &&
2129                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2130                                 return;
2131
2132                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2133                                     (GRC_LCLCTRL_GPIO_OE1 |
2134                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2135
2136                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2137                                     GRC_LCLCTRL_GPIO_OE1, 100);
2138
2139                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2140                                     (GRC_LCLCTRL_GPIO_OE1 |
2141                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2142                 }
2143         }
2144 }
2145
2146 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2147 {
2148         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2149                 return 1;
2150         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2151                 if (speed != SPEED_10)
2152                         return 1;
2153         } else if (speed == SPEED_10)
2154                 return 1;
2155
2156         return 0;
2157 }
2158
2159 static int tg3_setup_phy(struct tg3 *, int);
2160
2161 #define RESET_KIND_SHUTDOWN     0
2162 #define RESET_KIND_INIT         1
2163 #define RESET_KIND_SUSPEND      2
2164
2165 static void tg3_write_sig_post_reset(struct tg3 *, int);
2166 static int tg3_halt_cpu(struct tg3 *, u32);
2167
2168 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2169 {
2170         u32 val;
2171
2172         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2173                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2174                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2175                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2176
2177                         sg_dig_ctrl |=
2178                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2179                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2180                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2181                 }
2182                 return;
2183         }
2184
2185         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2186                 tg3_bmcr_reset(tp);
2187                 val = tr32(GRC_MISC_CFG);
2188                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2189                 udelay(40);
2190                 return;
2191         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2192                 u32 phytest;
2193                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2194                         u32 phy;
2195
2196                         tg3_writephy(tp, MII_ADVERTISE, 0);
2197                         tg3_writephy(tp, MII_BMCR,
2198                                      BMCR_ANENABLE | BMCR_ANRESTART);
2199
2200                         tg3_writephy(tp, MII_TG3_FET_TEST,
2201                                      phytest | MII_TG3_FET_SHADOW_EN);
2202                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2203                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2204                                 tg3_writephy(tp,
2205                                              MII_TG3_FET_SHDW_AUXMODE4,
2206                                              phy);
2207                         }
2208                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2209                 }
2210                 return;
2211         } else if (do_low_power) {
2212                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2213                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2214
2215                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2216                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2217                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2218                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2219                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2220         }
2221
2222         /* The PHY should not be powered down on some chips because
2223          * of bugs.
2224          */
2225         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2226             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2227             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2228              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2229                 return;
2230
2231         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2232             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2233                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2234                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2235                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2236                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2237         }
2238
2239         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2240 }
2241
2242 /* tp->lock is held. */
2243 static int tg3_nvram_lock(struct tg3 *tp)
2244 {
2245         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2246                 int i;
2247
2248                 if (tp->nvram_lock_cnt == 0) {
2249                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2250                         for (i = 0; i < 8000; i++) {
2251                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2252                                         break;
2253                                 udelay(20);
2254                         }
2255                         if (i == 8000) {
2256                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2257                                 return -ENODEV;
2258                         }
2259                 }
2260                 tp->nvram_lock_cnt++;
2261         }
2262         return 0;
2263 }
2264
2265 /* tp->lock is held. */
2266 static void tg3_nvram_unlock(struct tg3 *tp)
2267 {
2268         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2269                 if (tp->nvram_lock_cnt > 0)
2270                         tp->nvram_lock_cnt--;
2271                 if (tp->nvram_lock_cnt == 0)
2272                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2273         }
2274 }
2275
2276 /* tp->lock is held. */
2277 static void tg3_enable_nvram_access(struct tg3 *tp)
2278 {
2279         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2280             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2281                 u32 nvaccess = tr32(NVRAM_ACCESS);
2282
2283                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2284         }
2285 }
2286
2287 /* tp->lock is held. */
2288 static void tg3_disable_nvram_access(struct tg3 *tp)
2289 {
2290         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2291             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2292                 u32 nvaccess = tr32(NVRAM_ACCESS);
2293
2294                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2295         }
2296 }
2297
2298 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2299                                         u32 offset, u32 *val)
2300 {
2301         u32 tmp;
2302         int i;
2303
2304         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2305                 return -EINVAL;
2306
2307         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2308                                         EEPROM_ADDR_DEVID_MASK |
2309                                         EEPROM_ADDR_READ);
2310         tw32(GRC_EEPROM_ADDR,
2311              tmp |
2312              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2313              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2314               EEPROM_ADDR_ADDR_MASK) |
2315              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2316
2317         for (i = 0; i < 1000; i++) {
2318                 tmp = tr32(GRC_EEPROM_ADDR);
2319
2320                 if (tmp & EEPROM_ADDR_COMPLETE)
2321                         break;
2322                 msleep(1);
2323         }
2324         if (!(tmp & EEPROM_ADDR_COMPLETE))
2325                 return -EBUSY;
2326
2327         tmp = tr32(GRC_EEPROM_DATA);
2328
2329         /*
2330          * The data will always be opposite the native endian
2331          * format.  Perform a blind byteswap to compensate.
2332          */
2333         *val = swab32(tmp);
2334
2335         return 0;
2336 }
2337
2338 #define NVRAM_CMD_TIMEOUT 10000
2339
2340 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2341 {
2342         int i;
2343
2344         tw32(NVRAM_CMD, nvram_cmd);
2345         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2346                 udelay(10);
2347                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2348                         udelay(10);
2349                         break;
2350                 }
2351         }
2352
2353         if (i == NVRAM_CMD_TIMEOUT)
2354                 return -EBUSY;
2355
2356         return 0;
2357 }
2358
2359 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2360 {
2361         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2362             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2363             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2364            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2365             (tp->nvram_jedecnum == JEDEC_ATMEL))
2366
2367                 addr = ((addr / tp->nvram_pagesize) <<
2368                         ATMEL_AT45DB0X1B_PAGE_POS) +
2369                        (addr % tp->nvram_pagesize);
2370
2371         return addr;
2372 }
2373
2374 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2375 {
2376         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2377             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2378             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2379            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2380             (tp->nvram_jedecnum == JEDEC_ATMEL))
2381
2382                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2383                         tp->nvram_pagesize) +
2384                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2385
2386         return addr;
2387 }
2388
2389 /* NOTE: Data read in from NVRAM is byteswapped according to
2390  * the byteswapping settings for all other register accesses.
2391  * tg3 devices are BE devices, so on a BE machine, the data
2392  * returned will be exactly as it is seen in NVRAM.  On a LE
2393  * machine, the 32-bit value will be byteswapped.
2394  */
2395 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2396 {
2397         int ret;
2398
2399         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2400                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2401
2402         offset = tg3_nvram_phys_addr(tp, offset);
2403
2404         if (offset > NVRAM_ADDR_MSK)
2405                 return -EINVAL;
2406
2407         ret = tg3_nvram_lock(tp);
2408         if (ret)
2409                 return ret;
2410
2411         tg3_enable_nvram_access(tp);
2412
2413         tw32(NVRAM_ADDR, offset);
2414         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2415                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2416
2417         if (ret == 0)
2418                 *val = tr32(NVRAM_RDDATA);
2419
2420         tg3_disable_nvram_access(tp);
2421
2422         tg3_nvram_unlock(tp);
2423
2424         return ret;
2425 }
2426
2427 /* Ensures NVRAM data is in bytestream format. */
2428 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2429 {
2430         u32 v;
2431         int res = tg3_nvram_read(tp, offset, &v);
2432         if (!res)
2433                 *val = cpu_to_be32(v);
2434         return res;
2435 }
2436
2437 /* tp->lock is held. */
2438 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2439 {
2440         u32 addr_high, addr_low;
2441         int i;
2442
2443         addr_high = ((tp->dev->dev_addr[0] << 8) |
2444                      tp->dev->dev_addr[1]);
2445         addr_low = ((tp->dev->dev_addr[2] << 24) |
2446                     (tp->dev->dev_addr[3] << 16) |
2447                     (tp->dev->dev_addr[4] <<  8) |
2448                     (tp->dev->dev_addr[5] <<  0));
2449         for (i = 0; i < 4; i++) {
2450                 if (i == 1 && skip_mac_1)
2451                         continue;
2452                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2453                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2454         }
2455
2456         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2457             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2458                 for (i = 0; i < 12; i++) {
2459                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2460                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2461                 }
2462         }
2463
2464         addr_high = (tp->dev->dev_addr[0] +
2465                      tp->dev->dev_addr[1] +
2466                      tp->dev->dev_addr[2] +
2467                      tp->dev->dev_addr[3] +
2468                      tp->dev->dev_addr[4] +
2469                      tp->dev->dev_addr[5]) &
2470                 TX_BACKOFF_SEED_MASK;
2471         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2472 }
2473
2474 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2475 {
2476         u32 misc_host_ctrl;
2477         bool device_should_wake, do_low_power;
2478
2479         /* Make sure register accesses (indirect or otherwise)
2480          * will function correctly.
2481          */
2482         pci_write_config_dword(tp->pdev,
2483                                TG3PCI_MISC_HOST_CTRL,
2484                                tp->misc_host_ctrl);
2485
2486         switch (state) {
2487         case PCI_D0:
2488                 pci_enable_wake(tp->pdev, state, false);
2489                 pci_set_power_state(tp->pdev, PCI_D0);
2490
2491                 /* Switch out of Vaux if it is a NIC */
2492                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2493                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2494
2495                 return 0;
2496
2497         case PCI_D1:
2498         case PCI_D2:
2499         case PCI_D3hot:
2500                 break;
2501
2502         default:
2503                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2504                         tp->dev->name, state);
2505                 return -EINVAL;
2506         }
2507
2508         /* Restore the CLKREQ setting. */
2509         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2510                 u16 lnkctl;
2511
2512                 pci_read_config_word(tp->pdev,
2513                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2514                                      &lnkctl);
2515                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2516                 pci_write_config_word(tp->pdev,
2517                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2518                                       lnkctl);
2519         }
2520
2521         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2522         tw32(TG3PCI_MISC_HOST_CTRL,
2523              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2524
2525         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2526                              device_may_wakeup(&tp->pdev->dev) &&
2527                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2528
2529         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2530                 do_low_power = false;
2531                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2532                     !tp->link_config.phy_is_low_power) {
2533                         struct phy_device *phydev;
2534                         u32 phyid, advertising;
2535
2536                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2537
2538                         tp->link_config.phy_is_low_power = 1;
2539
2540                         tp->link_config.orig_speed = phydev->speed;
2541                         tp->link_config.orig_duplex = phydev->duplex;
2542                         tp->link_config.orig_autoneg = phydev->autoneg;
2543                         tp->link_config.orig_advertising = phydev->advertising;
2544
2545                         advertising = ADVERTISED_TP |
2546                                       ADVERTISED_Pause |
2547                                       ADVERTISED_Autoneg |
2548                                       ADVERTISED_10baseT_Half;
2549
2550                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2551                             device_should_wake) {
2552                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2553                                         advertising |=
2554                                                 ADVERTISED_100baseT_Half |
2555                                                 ADVERTISED_100baseT_Full |
2556                                                 ADVERTISED_10baseT_Full;
2557                                 else
2558                                         advertising |= ADVERTISED_10baseT_Full;
2559                         }
2560
2561                         phydev->advertising = advertising;
2562
2563                         phy_start_aneg(phydev);
2564
2565                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2566                         if (phyid != TG3_PHY_ID_BCMAC131) {
2567                                 phyid &= TG3_PHY_OUI_MASK;
2568                                 if (phyid == TG3_PHY_OUI_1 ||
2569                                     phyid == TG3_PHY_OUI_2 ||
2570                                     phyid == TG3_PHY_OUI_3)
2571                                         do_low_power = true;
2572                         }
2573                 }
2574         } else {
2575                 do_low_power = true;
2576
2577                 if (tp->link_config.phy_is_low_power == 0) {
2578                         tp->link_config.phy_is_low_power = 1;
2579                         tp->link_config.orig_speed = tp->link_config.speed;
2580                         tp->link_config.orig_duplex = tp->link_config.duplex;
2581                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2582                 }
2583
2584                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2585                         tp->link_config.speed = SPEED_10;
2586                         tp->link_config.duplex = DUPLEX_HALF;
2587                         tp->link_config.autoneg = AUTONEG_ENABLE;
2588                         tg3_setup_phy(tp, 0);
2589                 }
2590         }
2591
2592         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2593                 u32 val;
2594
2595                 val = tr32(GRC_VCPU_EXT_CTRL);
2596                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2597         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2598                 int i;
2599                 u32 val;
2600
2601                 for (i = 0; i < 200; i++) {
2602                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2603                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2604                                 break;
2605                         msleep(1);
2606                 }
2607         }
2608         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2609                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2610                                                      WOL_DRV_STATE_SHUTDOWN |
2611                                                      WOL_DRV_WOL |
2612                                                      WOL_SET_MAGIC_PKT);
2613
2614         if (device_should_wake) {
2615                 u32 mac_mode;
2616
2617                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2618                         if (do_low_power) {
2619                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2620                                 udelay(40);
2621                         }
2622
2623                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2624                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2625                         else
2626                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2627
2628                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2629                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2630                             ASIC_REV_5700) {
2631                                 u32 speed = (tp->tg3_flags &
2632                                              TG3_FLAG_WOL_SPEED_100MB) ?
2633                                              SPEED_100 : SPEED_10;
2634                                 if (tg3_5700_link_polarity(tp, speed))
2635                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2636                                 else
2637                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2638                         }
2639                 } else {
2640                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2641                 }
2642
2643                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2644                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2645
2646                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2647                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2648                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2649                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2650                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2651                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2652
2653                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2654                         mac_mode |= tp->mac_mode &
2655                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2656                         if (mac_mode & MAC_MODE_APE_TX_EN)
2657                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2658                 }
2659
2660                 tw32_f(MAC_MODE, mac_mode);
2661                 udelay(100);
2662
2663                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2664                 udelay(10);
2665         }
2666
2667         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2668             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2669              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2670                 u32 base_val;
2671
2672                 base_val = tp->pci_clock_ctrl;
2673                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2674                              CLOCK_CTRL_TXCLK_DISABLE);
2675
2676                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2677                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2678         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2679                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2680                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2681                 /* do nothing */
2682         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2683                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2684                 u32 newbits1, newbits2;
2685
2686                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2687                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2688                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2689                                     CLOCK_CTRL_TXCLK_DISABLE |
2690                                     CLOCK_CTRL_ALTCLK);
2691                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2692                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2693                         newbits1 = CLOCK_CTRL_625_CORE;
2694                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2695                 } else {
2696                         newbits1 = CLOCK_CTRL_ALTCLK;
2697                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2698                 }
2699
2700                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2701                             40);
2702
2703                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2704                             40);
2705
2706                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2707                         u32 newbits3;
2708
2709                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2710                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2711                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2712                                             CLOCK_CTRL_TXCLK_DISABLE |
2713                                             CLOCK_CTRL_44MHZ_CORE);
2714                         } else {
2715                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2716                         }
2717
2718                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2719                                     tp->pci_clock_ctrl | newbits3, 40);
2720                 }
2721         }
2722
2723         if (!(device_should_wake) &&
2724             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2725                 tg3_power_down_phy(tp, do_low_power);
2726
2727         tg3_frob_aux_power(tp);
2728
2729         /* Workaround for unstable PLL clock */
2730         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2731             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2732                 u32 val = tr32(0x7d00);
2733
2734                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2735                 tw32(0x7d00, val);
2736                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2737                         int err;
2738
2739                         err = tg3_nvram_lock(tp);
2740                         tg3_halt_cpu(tp, RX_CPU_BASE);
2741                         if (!err)
2742                                 tg3_nvram_unlock(tp);
2743                 }
2744         }
2745
2746         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2747
2748         if (device_should_wake)
2749                 pci_enable_wake(tp->pdev, state, true);
2750
2751         /* Finally, set the new power state. */
2752         pci_set_power_state(tp->pdev, state);
2753
2754         return 0;
2755 }
2756
2757 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2758 {
2759         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2760         case MII_TG3_AUX_STAT_10HALF:
2761                 *speed = SPEED_10;
2762                 *duplex = DUPLEX_HALF;
2763                 break;
2764
2765         case MII_TG3_AUX_STAT_10FULL:
2766                 *speed = SPEED_10;
2767                 *duplex = DUPLEX_FULL;
2768                 break;
2769
2770         case MII_TG3_AUX_STAT_100HALF:
2771                 *speed = SPEED_100;
2772                 *duplex = DUPLEX_HALF;
2773                 break;
2774
2775         case MII_TG3_AUX_STAT_100FULL:
2776                 *speed = SPEED_100;
2777                 *duplex = DUPLEX_FULL;
2778                 break;
2779
2780         case MII_TG3_AUX_STAT_1000HALF:
2781                 *speed = SPEED_1000;
2782                 *duplex = DUPLEX_HALF;
2783                 break;
2784
2785         case MII_TG3_AUX_STAT_1000FULL:
2786                 *speed = SPEED_1000;
2787                 *duplex = DUPLEX_FULL;
2788                 break;
2789
2790         default:
2791                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2792                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2793                                  SPEED_10;
2794                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2795                                   DUPLEX_HALF;
2796                         break;
2797                 }
2798                 *speed = SPEED_INVALID;
2799                 *duplex = DUPLEX_INVALID;
2800                 break;
2801         }
2802 }
2803
2804 static void tg3_phy_copper_begin(struct tg3 *tp)
2805 {
2806         u32 new_adv;
2807         int i;
2808
2809         if (tp->link_config.phy_is_low_power) {
2810                 /* Entering low power mode.  Disable gigabit and
2811                  * 100baseT advertisements.
2812                  */
2813                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2814
2815                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2816                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2817                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2818                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2819
2820                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821         } else if (tp->link_config.speed == SPEED_INVALID) {
2822                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2823                         tp->link_config.advertising &=
2824                                 ~(ADVERTISED_1000baseT_Half |
2825                                   ADVERTISED_1000baseT_Full);
2826
2827                 new_adv = ADVERTISE_CSMA;
2828                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2829                         new_adv |= ADVERTISE_10HALF;
2830                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2831                         new_adv |= ADVERTISE_10FULL;
2832                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2833                         new_adv |= ADVERTISE_100HALF;
2834                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2835                         new_adv |= ADVERTISE_100FULL;
2836
2837                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2838
2839                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2840
2841                 if (tp->link_config.advertising &
2842                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2843                         new_adv = 0;
2844                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2845                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2846                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2847                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2848                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2849                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2850                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2851                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2852                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2853                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2854                 } else {
2855                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2856                 }
2857         } else {
2858                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2859                 new_adv |= ADVERTISE_CSMA;
2860
2861                 /* Asking for a specific link mode. */
2862                 if (tp->link_config.speed == SPEED_1000) {
2863                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2864
2865                         if (tp->link_config.duplex == DUPLEX_FULL)
2866                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2867                         else
2868                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2869                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2870                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2871                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2872                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2873                 } else {
2874                         if (tp->link_config.speed == SPEED_100) {
2875                                 if (tp->link_config.duplex == DUPLEX_FULL)
2876                                         new_adv |= ADVERTISE_100FULL;
2877                                 else
2878                                         new_adv |= ADVERTISE_100HALF;
2879                         } else {
2880                                 if (tp->link_config.duplex == DUPLEX_FULL)
2881                                         new_adv |= ADVERTISE_10FULL;
2882                                 else
2883                                         new_adv |= ADVERTISE_10HALF;
2884                         }
2885                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2886
2887                         new_adv = 0;
2888                 }
2889
2890                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2891         }
2892
2893         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2894             tp->link_config.speed != SPEED_INVALID) {
2895                 u32 bmcr, orig_bmcr;
2896
2897                 tp->link_config.active_speed = tp->link_config.speed;
2898                 tp->link_config.active_duplex = tp->link_config.duplex;
2899
2900                 bmcr = 0;
2901                 switch (tp->link_config.speed) {
2902                 default:
2903                 case SPEED_10:
2904                         break;
2905
2906                 case SPEED_100:
2907                         bmcr |= BMCR_SPEED100;
2908                         break;
2909
2910                 case SPEED_1000:
2911                         bmcr |= TG3_BMCR_SPEED1000;
2912                         break;
2913                 }
2914
2915                 if (tp->link_config.duplex == DUPLEX_FULL)
2916                         bmcr |= BMCR_FULLDPLX;
2917
2918                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2919                     (bmcr != orig_bmcr)) {
2920                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2921                         for (i = 0; i < 1500; i++) {
2922                                 u32 tmp;
2923
2924                                 udelay(10);
2925                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2926                                     tg3_readphy(tp, MII_BMSR, &tmp))
2927                                         continue;
2928                                 if (!(tmp & BMSR_LSTATUS)) {
2929                                         udelay(40);
2930                                         break;
2931                                 }
2932                         }
2933                         tg3_writephy(tp, MII_BMCR, bmcr);
2934                         udelay(40);
2935                 }
2936         } else {
2937                 tg3_writephy(tp, MII_BMCR,
2938                              BMCR_ANENABLE | BMCR_ANRESTART);
2939         }
2940 }
2941
2942 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2943 {
2944         int err;
2945
2946         /* Turn off tap power management. */
2947         /* Set Extended packet length bit */
2948         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2949
2950         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2951         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2952
2953         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2954         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2955
2956         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2957         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2958
2959         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2960         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2961
2962         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2963         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2964
2965         udelay(40);
2966
2967         return err;
2968 }
2969
2970 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2971 {
2972         u32 adv_reg, all_mask = 0;
2973
2974         if (mask & ADVERTISED_10baseT_Half)
2975                 all_mask |= ADVERTISE_10HALF;
2976         if (mask & ADVERTISED_10baseT_Full)
2977                 all_mask |= ADVERTISE_10FULL;
2978         if (mask & ADVERTISED_100baseT_Half)
2979                 all_mask |= ADVERTISE_100HALF;
2980         if (mask & ADVERTISED_100baseT_Full)
2981                 all_mask |= ADVERTISE_100FULL;
2982
2983         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2984                 return 0;
2985
2986         if ((adv_reg & all_mask) != all_mask)
2987                 return 0;
2988         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2989                 u32 tg3_ctrl;
2990
2991                 all_mask = 0;
2992                 if (mask & ADVERTISED_1000baseT_Half)
2993                         all_mask |= ADVERTISE_1000HALF;
2994                 if (mask & ADVERTISED_1000baseT_Full)
2995                         all_mask |= ADVERTISE_1000FULL;
2996
2997                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2998                         return 0;
2999
3000                 if ((tg3_ctrl & all_mask) != all_mask)
3001                         return 0;
3002         }
3003         return 1;
3004 }
3005
3006 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3007 {
3008         u32 curadv, reqadv;
3009
3010         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3011                 return 1;
3012
3013         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3014         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3015
3016         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3017                 if (curadv != reqadv)
3018                         return 0;
3019
3020                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3021                         tg3_readphy(tp, MII_LPA, rmtadv);
3022         } else {
3023                 /* Reprogram the advertisement register, even if it
3024                  * does not affect the current link.  If the link
3025                  * gets renegotiated in the future, we can save an
3026                  * additional renegotiation cycle by advertising
3027                  * it correctly in the first place.
3028                  */
3029                 if (curadv != reqadv) {
3030                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3031                                      ADVERTISE_PAUSE_ASYM);
3032                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3033                 }
3034         }
3035
3036         return 1;
3037 }
3038
3039 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3040 {
3041         int current_link_up;
3042         u32 bmsr, dummy;
3043         u32 lcl_adv, rmt_adv;
3044         u16 current_speed;
3045         u8 current_duplex;
3046         int i, err;
3047
3048         tw32(MAC_EVENT, 0);
3049
3050         tw32_f(MAC_STATUS,
3051              (MAC_STATUS_SYNC_CHANGED |
3052               MAC_STATUS_CFG_CHANGED |
3053               MAC_STATUS_MI_COMPLETION |
3054               MAC_STATUS_LNKSTATE_CHANGED));
3055         udelay(40);
3056
3057         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3058                 tw32_f(MAC_MI_MODE,
3059                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3060                 udelay(80);
3061         }
3062
3063         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3064
3065         /* Some third-party PHYs need to be reset on link going
3066          * down.
3067          */
3068         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3069              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3070              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3071             netif_carrier_ok(tp->dev)) {
3072                 tg3_readphy(tp, MII_BMSR, &bmsr);
3073                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3074                     !(bmsr & BMSR_LSTATUS))
3075                         force_reset = 1;
3076         }
3077         if (force_reset)
3078                 tg3_phy_reset(tp);
3079
3080         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3081                 tg3_readphy(tp, MII_BMSR, &bmsr);
3082                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3083                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3084                         bmsr = 0;
3085
3086                 if (!(bmsr & BMSR_LSTATUS)) {
3087                         err = tg3_init_5401phy_dsp(tp);
3088                         if (err)
3089                                 return err;
3090
3091                         tg3_readphy(tp, MII_BMSR, &bmsr);
3092                         for (i = 0; i < 1000; i++) {
3093                                 udelay(10);
3094                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3095                                     (bmsr & BMSR_LSTATUS)) {
3096                                         udelay(40);
3097                                         break;
3098                                 }
3099                         }
3100
3101                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3102                             !(bmsr & BMSR_LSTATUS) &&
3103                             tp->link_config.active_speed == SPEED_1000) {
3104                                 err = tg3_phy_reset(tp);
3105                                 if (!err)
3106                                         err = tg3_init_5401phy_dsp(tp);
3107                                 if (err)
3108                                         return err;
3109                         }
3110                 }
3111         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3112                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3113                 /* 5701 {A0,B0} CRC bug workaround */
3114                 tg3_writephy(tp, 0x15, 0x0a75);
3115                 tg3_writephy(tp, 0x1c, 0x8c68);
3116                 tg3_writephy(tp, 0x1c, 0x8d68);
3117                 tg3_writephy(tp, 0x1c, 0x8c68);
3118         }
3119
3120         /* Clear pending interrupts... */
3121         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3122         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3123
3124         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3125                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3126         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3127                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3128
3129         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3130             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3131                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3132                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3133                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3134                 else
3135                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3136         }
3137
3138         current_link_up = 0;
3139         current_speed = SPEED_INVALID;
3140         current_duplex = DUPLEX_INVALID;
3141
3142         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3143                 u32 val;
3144
3145                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3146                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3147                 if (!(val & (1 << 10))) {
3148                         val |= (1 << 10);
3149                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3150                         goto relink;
3151                 }
3152         }
3153
3154         bmsr = 0;
3155         for (i = 0; i < 100; i++) {
3156                 tg3_readphy(tp, MII_BMSR, &bmsr);
3157                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3158                     (bmsr & BMSR_LSTATUS))
3159                         break;
3160                 udelay(40);
3161         }
3162
3163         if (bmsr & BMSR_LSTATUS) {
3164                 u32 aux_stat, bmcr;
3165
3166                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3167                 for (i = 0; i < 2000; i++) {
3168                         udelay(10);
3169                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3170                             aux_stat)
3171                                 break;
3172                 }
3173
3174                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3175                                              &current_speed,
3176                                              &current_duplex);
3177
3178                 bmcr = 0;
3179                 for (i = 0; i < 200; i++) {
3180                         tg3_readphy(tp, MII_BMCR, &bmcr);
3181                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3182                                 continue;
3183                         if (bmcr && bmcr != 0x7fff)
3184                                 break;
3185                         udelay(10);
3186                 }
3187
3188                 lcl_adv = 0;
3189                 rmt_adv = 0;
3190
3191                 tp->link_config.active_speed = current_speed;
3192                 tp->link_config.active_duplex = current_duplex;
3193
3194                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3195                         if ((bmcr & BMCR_ANENABLE) &&
3196                             tg3_copper_is_advertising_all(tp,
3197                                                 tp->link_config.advertising)) {
3198                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3199                                                                   &rmt_adv))
3200                                         current_link_up = 1;
3201                         }
3202                 } else {
3203                         if (!(bmcr & BMCR_ANENABLE) &&
3204                             tp->link_config.speed == current_speed &&
3205                             tp->link_config.duplex == current_duplex &&
3206                             tp->link_config.flowctrl ==
3207                             tp->link_config.active_flowctrl) {
3208                                 current_link_up = 1;
3209                         }
3210                 }
3211
3212                 if (current_link_up == 1 &&
3213                     tp->link_config.active_duplex == DUPLEX_FULL)
3214                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3215         }
3216
3217 relink:
3218         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3219                 u32 tmp;
3220
3221                 tg3_phy_copper_begin(tp);
3222
3223                 tg3_readphy(tp, MII_BMSR, &tmp);
3224                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3225                     (tmp & BMSR_LSTATUS))
3226                         current_link_up = 1;
3227         }
3228
3229         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3230         if (current_link_up == 1) {
3231                 if (tp->link_config.active_speed == SPEED_100 ||
3232                     tp->link_config.active_speed == SPEED_10)
3233                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3234                 else
3235                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3236         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3237                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3238         else
3239                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3240
3241         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3242         if (tp->link_config.active_duplex == DUPLEX_HALF)
3243                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3244
3245         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3246                 if (current_link_up == 1 &&
3247                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3248                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3249                 else
3250                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3251         }
3252
3253         /* ??? Without this setting Netgear GA302T PHY does not
3254          * ??? send/receive packets...
3255          */
3256         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3257             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3258                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3259                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3260                 udelay(80);
3261         }
3262
3263         tw32_f(MAC_MODE, tp->mac_mode);
3264         udelay(40);
3265
3266         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3267                 /* Polled via timer. */
3268                 tw32_f(MAC_EVENT, 0);
3269         } else {
3270                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3271         }
3272         udelay(40);
3273
3274         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3275             current_link_up == 1 &&
3276             tp->link_config.active_speed == SPEED_1000 &&
3277             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3278              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3279                 udelay(120);
3280                 tw32_f(MAC_STATUS,
3281                      (MAC_STATUS_SYNC_CHANGED |
3282                       MAC_STATUS_CFG_CHANGED));
3283                 udelay(40);
3284                 tg3_write_mem(tp,
3285                               NIC_SRAM_FIRMWARE_MBOX,
3286                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3287         }
3288
3289         /* Prevent send BD corruption. */
3290         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3291                 u16 oldlnkctl, newlnkctl;
3292
3293                 pci_read_config_word(tp->pdev,
3294                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3295                                      &oldlnkctl);
3296                 if (tp->link_config.active_speed == SPEED_100 ||
3297                     tp->link_config.active_speed == SPEED_10)
3298                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3299                 else
3300                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3301                 if (newlnkctl != oldlnkctl)
3302                         pci_write_config_word(tp->pdev,
3303                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3304                                               newlnkctl);
3305         }
3306
3307         if (current_link_up != netif_carrier_ok(tp->dev)) {
3308                 if (current_link_up)
3309                         netif_carrier_on(tp->dev);
3310                 else
3311                         netif_carrier_off(tp->dev);
3312                 tg3_link_report(tp);
3313         }
3314
3315         return 0;
3316 }
3317
3318 struct tg3_fiber_aneginfo {
3319         int state;
3320 #define ANEG_STATE_UNKNOWN              0
3321 #define ANEG_STATE_AN_ENABLE            1
3322 #define ANEG_STATE_RESTART_INIT         2
3323 #define ANEG_STATE_RESTART              3
3324 #define ANEG_STATE_DISABLE_LINK_OK      4
3325 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3326 #define ANEG_STATE_ABILITY_DETECT       6
3327 #define ANEG_STATE_ACK_DETECT_INIT      7
3328 #define ANEG_STATE_ACK_DETECT           8
3329 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3330 #define ANEG_STATE_COMPLETE_ACK         10
3331 #define ANEG_STATE_IDLE_DETECT_INIT     11
3332 #define ANEG_STATE_IDLE_DETECT          12
3333 #define ANEG_STATE_LINK_OK              13
3334 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3335 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3336
3337         u32 flags;
3338 #define MR_AN_ENABLE            0x00000001
3339 #define MR_RESTART_AN           0x00000002
3340 #define MR_AN_COMPLETE          0x00000004
3341 #define MR_PAGE_RX              0x00000008
3342 #define MR_NP_LOADED            0x00000010
3343 #define MR_TOGGLE_TX            0x00000020
3344 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3345 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3346 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3347 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3348 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3349 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3350 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3351 #define MR_TOGGLE_RX            0x00002000
3352 #define MR_NP_RX                0x00004000
3353
3354 #define MR_LINK_OK              0x80000000
3355
3356         unsigned long link_time, cur_time;
3357
3358         u32 ability_match_cfg;
3359         int ability_match_count;
3360
3361         char ability_match, idle_match, ack_match;
3362
3363         u32 txconfig, rxconfig;
3364 #define ANEG_CFG_NP             0x00000080
3365 #define ANEG_CFG_ACK            0x00000040
3366 #define ANEG_CFG_RF2            0x00000020
3367 #define ANEG_CFG_RF1            0x00000010
3368 #define ANEG_CFG_PS2            0x00000001
3369 #define ANEG_CFG_PS1            0x00008000
3370 #define ANEG_CFG_HD             0x00004000
3371 #define ANEG_CFG_FD             0x00002000
3372 #define ANEG_CFG_INVAL          0x00001f06
3373
3374 };
3375 #define ANEG_OK         0
3376 #define ANEG_DONE       1
3377 #define ANEG_TIMER_ENAB 2
3378 #define ANEG_FAILED     -1
3379
3380 #define ANEG_STATE_SETTLE_TIME  10000
3381
3382 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3383                                    struct tg3_fiber_aneginfo *ap)
3384 {
3385         u16 flowctrl;
3386         unsigned long delta;
3387         u32 rx_cfg_reg;
3388         int ret;
3389
3390         if (ap->state == ANEG_STATE_UNKNOWN) {
3391                 ap->rxconfig = 0;
3392                 ap->link_time = 0;
3393                 ap->cur_time = 0;
3394                 ap->ability_match_cfg = 0;
3395                 ap->ability_match_count = 0;
3396                 ap->ability_match = 0;
3397                 ap->idle_match = 0;
3398                 ap->ack_match = 0;
3399         }
3400         ap->cur_time++;
3401
3402         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3403                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3404
3405                 if (rx_cfg_reg != ap->ability_match_cfg) {
3406                         ap->ability_match_cfg = rx_cfg_reg;
3407                         ap->ability_match = 0;
3408                         ap->ability_match_count = 0;
3409                 } else {
3410                         if (++ap->ability_match_count > 1) {
3411                                 ap->ability_match = 1;
3412                                 ap->ability_match_cfg = rx_cfg_reg;
3413                         }
3414                 }
3415                 if (rx_cfg_reg & ANEG_CFG_ACK)
3416                         ap->ack_match = 1;
3417                 else
3418                         ap->ack_match = 0;
3419
3420                 ap->idle_match = 0;
3421         } else {
3422                 ap->idle_match = 1;
3423                 ap->ability_match_cfg = 0;
3424                 ap->ability_match_count = 0;
3425                 ap->ability_match = 0;
3426                 ap->ack_match = 0;
3427
3428                 rx_cfg_reg = 0;
3429         }
3430
3431         ap->rxconfig = rx_cfg_reg;
3432         ret = ANEG_OK;
3433
3434         switch(ap->state) {
3435         case ANEG_STATE_UNKNOWN:
3436                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3437                         ap->state = ANEG_STATE_AN_ENABLE;
3438
3439                 /* fallthru */
3440         case ANEG_STATE_AN_ENABLE:
3441                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3442                 if (ap->flags & MR_AN_ENABLE) {
3443                         ap->link_time = 0;
3444                         ap->cur_time = 0;
3445                         ap->ability_match_cfg = 0;
3446                         ap->ability_match_count = 0;
3447                         ap->ability_match = 0;
3448                         ap->idle_match = 0;
3449                         ap->ack_match = 0;
3450
3451                         ap->state = ANEG_STATE_RESTART_INIT;
3452                 } else {
3453                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3454                 }
3455                 break;
3456
3457         case ANEG_STATE_RESTART_INIT:
3458                 ap->link_time = ap->cur_time;
3459                 ap->flags &= ~(MR_NP_LOADED);
3460                 ap->txconfig = 0;
3461                 tw32(MAC_TX_AUTO_NEG, 0);
3462                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3463                 tw32_f(MAC_MODE, tp->mac_mode);
3464                 udelay(40);
3465
3466                 ret = ANEG_TIMER_ENAB;
3467                 ap->state = ANEG_STATE_RESTART;
3468
3469                 /* fallthru */
3470         case ANEG_STATE_RESTART:
3471                 delta = ap->cur_time - ap->link_time;
3472                 if (delta > ANEG_STATE_SETTLE_TIME) {
3473                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3474                 } else {
3475                         ret = ANEG_TIMER_ENAB;
3476                 }
3477                 break;
3478
3479         case ANEG_STATE_DISABLE_LINK_OK:
3480                 ret = ANEG_DONE;
3481                 break;
3482
3483         case ANEG_STATE_ABILITY_DETECT_INIT:
3484                 ap->flags &= ~(MR_TOGGLE_TX);
3485                 ap->txconfig = ANEG_CFG_FD;
3486                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3487                 if (flowctrl & ADVERTISE_1000XPAUSE)
3488                         ap->txconfig |= ANEG_CFG_PS1;
3489                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3490                         ap->txconfig |= ANEG_CFG_PS2;
3491                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3492                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3493                 tw32_f(MAC_MODE, tp->mac_mode);
3494                 udelay(40);
3495
3496                 ap->state = ANEG_STATE_ABILITY_DETECT;
3497                 break;
3498
3499         case ANEG_STATE_ABILITY_DETECT:
3500                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3501                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3502                 }
3503                 break;
3504
3505         case ANEG_STATE_ACK_DETECT_INIT:
3506                 ap->txconfig |= ANEG_CFG_ACK;
3507                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3508                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3509                 tw32_f(MAC_MODE, tp->mac_mode);
3510                 udelay(40);
3511
3512                 ap->state = ANEG_STATE_ACK_DETECT;
3513
3514                 /* fallthru */
3515         case ANEG_STATE_ACK_DETECT:
3516                 if (ap->ack_match != 0) {
3517                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3518                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3519                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3520                         } else {
3521                                 ap->state = ANEG_STATE_AN_ENABLE;
3522                         }
3523                 } else if (ap->ability_match != 0 &&
3524                            ap->rxconfig == 0) {
3525                         ap->state = ANEG_STATE_AN_ENABLE;
3526                 }
3527                 break;
3528
3529         case ANEG_STATE_COMPLETE_ACK_INIT:
3530                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3531                         ret = ANEG_FAILED;
3532                         break;
3533                 }
3534                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3535                                MR_LP_ADV_HALF_DUPLEX |
3536                                MR_LP_ADV_SYM_PAUSE |
3537                                MR_LP_ADV_ASYM_PAUSE |
3538                                MR_LP_ADV_REMOTE_FAULT1 |
3539                                MR_LP_ADV_REMOTE_FAULT2 |
3540                                MR_LP_ADV_NEXT_PAGE |
3541                                MR_TOGGLE_RX |
3542                                MR_NP_RX);
3543                 if (ap->rxconfig & ANEG_CFG_FD)
3544                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3545                 if (ap->rxconfig & ANEG_CFG_HD)
3546                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3547                 if (ap->rxconfig & ANEG_CFG_PS1)
3548                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3549                 if (ap->rxconfig & ANEG_CFG_PS2)
3550                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3551                 if (ap->rxconfig & ANEG_CFG_RF1)
3552                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3553                 if (ap->rxconfig & ANEG_CFG_RF2)
3554                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3555                 if (ap->rxconfig & ANEG_CFG_NP)
3556                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3557
3558                 ap->link_time = ap->cur_time;
3559
3560                 ap->flags ^= (MR_TOGGLE_TX);
3561                 if (ap->rxconfig & 0x0008)
3562                         ap->flags |= MR_TOGGLE_RX;
3563                 if (ap->rxconfig & ANEG_CFG_NP)
3564                         ap->flags |= MR_NP_RX;
3565                 ap->flags |= MR_PAGE_RX;
3566
3567                 ap->state = ANEG_STATE_COMPLETE_ACK;
3568                 ret = ANEG_TIMER_ENAB;
3569                 break;
3570
3571         case ANEG_STATE_COMPLETE_ACK:
3572                 if (ap->ability_match != 0 &&
3573                     ap->rxconfig == 0) {
3574                         ap->state = ANEG_STATE_AN_ENABLE;
3575                         break;
3576                 }
3577                 delta = ap->cur_time - ap->link_time;
3578                 if (delta > ANEG_STATE_SETTLE_TIME) {
3579                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3580                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3581                         } else {
3582                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3583                                     !(ap->flags & MR_NP_RX)) {
3584                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3585                                 } else {
3586                                         ret = ANEG_FAILED;
3587                                 }
3588                         }
3589                 }
3590                 break;
3591
3592         case ANEG_STATE_IDLE_DETECT_INIT:
3593                 ap->link_time = ap->cur_time;
3594                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3595                 tw32_f(MAC_MODE, tp->mac_mode);
3596                 udelay(40);
3597
3598                 ap->state = ANEG_STATE_IDLE_DETECT;
3599                 ret = ANEG_TIMER_ENAB;
3600                 break;
3601
3602         case ANEG_STATE_IDLE_DETECT:
3603                 if (ap->ability_match != 0 &&
3604                     ap->rxconfig == 0) {
3605                         ap->state = ANEG_STATE_AN_ENABLE;
3606                         break;
3607                 }
3608                 delta = ap->cur_time - ap->link_time;
3609                 if (delta > ANEG_STATE_SETTLE_TIME) {
3610                         /* XXX another gem from the Broadcom driver :( */
3611                         ap->state = ANEG_STATE_LINK_OK;
3612                 }
3613                 break;
3614
3615         case ANEG_STATE_LINK_OK:
3616                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3617                 ret = ANEG_DONE;
3618                 break;
3619
3620         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3621                 /* ??? unimplemented */
3622                 break;
3623
3624         case ANEG_STATE_NEXT_PAGE_WAIT:
3625                 /* ??? unimplemented */
3626                 break;
3627
3628         default:
3629                 ret = ANEG_FAILED;
3630                 break;
3631         }
3632
3633         return ret;
3634 }
3635
3636 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3637 {
3638         int res = 0;
3639         struct tg3_fiber_aneginfo aninfo;
3640         int status = ANEG_FAILED;
3641         unsigned int tick;
3642         u32 tmp;
3643
3644         tw32_f(MAC_TX_AUTO_NEG, 0);
3645
3646         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3647         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3648         udelay(40);
3649
3650         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3651         udelay(40);
3652
3653         memset(&aninfo, 0, sizeof(aninfo));
3654         aninfo.flags |= MR_AN_ENABLE;
3655         aninfo.state = ANEG_STATE_UNKNOWN;
3656         aninfo.cur_time = 0;
3657         tick = 0;
3658         while (++tick < 195000) {
3659                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3660                 if (status == ANEG_DONE || status == ANEG_FAILED)
3661                         break;
3662
3663                 udelay(1);
3664         }
3665
3666         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3667         tw32_f(MAC_MODE, tp->mac_mode);
3668         udelay(40);
3669
3670         *txflags = aninfo.txconfig;
3671         *rxflags = aninfo.flags;
3672
3673         if (status == ANEG_DONE &&
3674             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3675                              MR_LP_ADV_FULL_DUPLEX)))
3676                 res = 1;
3677
3678         return res;
3679 }
3680
3681 static void tg3_init_bcm8002(struct tg3 *tp)
3682 {
3683         u32 mac_status = tr32(MAC_STATUS);
3684         int i;
3685
3686         /* Reset when initting first time or we have a link. */
3687         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3688             !(mac_status & MAC_STATUS_PCS_SYNCED))
3689                 return;
3690
3691         /* Set PLL lock range. */
3692         tg3_writephy(tp, 0x16, 0x8007);
3693
3694         /* SW reset */
3695         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3696
3697         /* Wait for reset to complete. */
3698         /* XXX schedule_timeout() ... */
3699         for (i = 0; i < 500; i++)
3700                 udelay(10);
3701
3702         /* Config mode; select PMA/Ch 1 regs. */
3703         tg3_writephy(tp, 0x10, 0x8411);
3704
3705         /* Enable auto-lock and comdet, select txclk for tx. */
3706         tg3_writephy(tp, 0x11, 0x0a10);
3707
3708         tg3_writephy(tp, 0x18, 0x00a0);
3709         tg3_writephy(tp, 0x16, 0x41ff);
3710
3711         /* Assert and deassert POR. */
3712         tg3_writephy(tp, 0x13, 0x0400);
3713         udelay(40);
3714         tg3_writephy(tp, 0x13, 0x0000);
3715
3716         tg3_writephy(tp, 0x11, 0x0a50);
3717         udelay(40);
3718         tg3_writephy(tp, 0x11, 0x0a10);
3719
3720         /* Wait for signal to stabilize */
3721         /* XXX schedule_timeout() ... */
3722         for (i = 0; i < 15000; i++)
3723                 udelay(10);
3724
3725         /* Deselect the channel register so we can read the PHYID
3726          * later.
3727          */
3728         tg3_writephy(tp, 0x10, 0x8011);
3729 }
3730
3731 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3732 {
3733         u16 flowctrl;
3734         u32 sg_dig_ctrl, sg_dig_status;
3735         u32 serdes_cfg, expected_sg_dig_ctrl;
3736         int workaround, port_a;
3737         int current_link_up;
3738
3739         serdes_cfg = 0;
3740         expected_sg_dig_ctrl = 0;
3741         workaround = 0;
3742         port_a = 1;
3743         current_link_up = 0;
3744
3745         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3746             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3747                 workaround = 1;
3748                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3749                         port_a = 0;
3750
3751                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3752                 /* preserve bits 20-23 for voltage regulator */
3753                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3754         }
3755
3756         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3757
3758         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3759                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3760                         if (workaround) {
3761                                 u32 val = serdes_cfg;
3762
3763                                 if (port_a)
3764                                         val |= 0xc010000;
3765                                 else
3766                                         val |= 0x4010000;
3767                                 tw32_f(MAC_SERDES_CFG, val);
3768                         }
3769
3770                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3771                 }
3772                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3773                         tg3_setup_flow_control(tp, 0, 0);
3774                         current_link_up = 1;
3775                 }
3776                 goto out;
3777         }
3778
3779         /* Want auto-negotiation.  */
3780         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3781
3782         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3783         if (flowctrl & ADVERTISE_1000XPAUSE)
3784                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3785         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3786                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3787
3788         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3789                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3790                     tp->serdes_counter &&
3791                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3792                                     MAC_STATUS_RCVD_CFG)) ==
3793                      MAC_STATUS_PCS_SYNCED)) {
3794                         tp->serdes_counter--;
3795                         current_link_up = 1;
3796                         goto out;
3797                 }
3798 restart_autoneg:
3799                 if (workaround)
3800                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3801                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3802                 udelay(5);
3803                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3804
3805                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3806                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3807         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3808                                  MAC_STATUS_SIGNAL_DET)) {
3809                 sg_dig_status = tr32(SG_DIG_STATUS);
3810                 mac_status = tr32(MAC_STATUS);
3811
3812                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3813                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3814                         u32 local_adv = 0, remote_adv = 0;
3815
3816                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3817                                 local_adv |= ADVERTISE_1000XPAUSE;
3818                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3819                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3820
3821                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3822                                 remote_adv |= LPA_1000XPAUSE;
3823                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3824                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3825
3826                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3827                         current_link_up = 1;
3828                         tp->serdes_counter = 0;
3829                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3830                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3831                         if (tp->serdes_counter)
3832                                 tp->serdes_counter--;
3833                         else {
3834                                 if (workaround) {
3835                                         u32 val = serdes_cfg;
3836
3837                                         if (port_a)
3838                                                 val |= 0xc010000;
3839                                         else
3840                                                 val |= 0x4010000;
3841
3842                                         tw32_f(MAC_SERDES_CFG, val);
3843                                 }
3844
3845                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3846                                 udelay(40);
3847
3848                                 /* Link parallel detection - link is up */
3849                                 /* only if we have PCS_SYNC and not */
3850                                 /* receiving config code words */
3851                                 mac_status = tr32(MAC_STATUS);
3852                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3853                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3854                                         tg3_setup_flow_control(tp, 0, 0);
3855                                         current_link_up = 1;
3856                                         tp->tg3_flags2 |=
3857                                                 TG3_FLG2_PARALLEL_DETECT;
3858                                         tp->serdes_counter =
3859                                                 SERDES_PARALLEL_DET_TIMEOUT;
3860                                 } else
3861                                         goto restart_autoneg;
3862                         }
3863                 }
3864         } else {
3865                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3866                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3867         }
3868
3869 out:
3870         return current_link_up;
3871 }
3872
3873 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3874 {
3875         int current_link_up = 0;
3876
3877         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3878                 goto out;
3879
3880         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3881                 u32 txflags, rxflags;
3882                 int i;
3883
3884                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3885                         u32 local_adv = 0, remote_adv = 0;
3886
3887                         if (txflags & ANEG_CFG_PS1)
3888                                 local_adv |= ADVERTISE_1000XPAUSE;
3889                         if (txflags & ANEG_CFG_PS2)
3890                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3891
3892                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3893                                 remote_adv |= LPA_1000XPAUSE;
3894                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3895                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3896
3897                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3898
3899                         current_link_up = 1;
3900                 }
3901                 for (i = 0; i < 30; i++) {
3902                         udelay(20);
3903                         tw32_f(MAC_STATUS,
3904                                (MAC_STATUS_SYNC_CHANGED |
3905                                 MAC_STATUS_CFG_CHANGED));
3906                         udelay(40);
3907                         if ((tr32(MAC_STATUS) &
3908                              (MAC_STATUS_SYNC_CHANGED |
3909                               MAC_STATUS_CFG_CHANGED)) == 0)
3910                                 break;
3911                 }
3912
3913                 mac_status = tr32(MAC_STATUS);
3914                 if (current_link_up == 0 &&
3915                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3916                     !(mac_status & MAC_STATUS_RCVD_CFG))
3917                         current_link_up = 1;
3918         } else {
3919                 tg3_setup_flow_control(tp, 0, 0);
3920
3921                 /* Forcing 1000FD link up. */
3922                 current_link_up = 1;
3923
3924                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3925                 udelay(40);
3926
3927                 tw32_f(MAC_MODE, tp->mac_mode);
3928                 udelay(40);
3929         }
3930
3931 out:
3932         return current_link_up;
3933 }
3934
3935 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3936 {
3937         u32 orig_pause_cfg;
3938         u16 orig_active_speed;
3939         u8 orig_active_duplex;
3940         u32 mac_status;
3941         int current_link_up;
3942         int i;
3943
3944         orig_pause_cfg = tp->link_config.active_flowctrl;
3945         orig_active_speed = tp->link_config.active_speed;
3946         orig_active_duplex = tp->link_config.active_duplex;
3947
3948         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3949             netif_carrier_ok(tp->dev) &&
3950             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3951                 mac_status = tr32(MAC_STATUS);
3952                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3953                                MAC_STATUS_SIGNAL_DET |
3954                                MAC_STATUS_CFG_CHANGED |
3955                                MAC_STATUS_RCVD_CFG);
3956                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3957                                    MAC_STATUS_SIGNAL_DET)) {
3958                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3959                                             MAC_STATUS_CFG_CHANGED));
3960                         return 0;
3961                 }
3962         }
3963
3964         tw32_f(MAC_TX_AUTO_NEG, 0);
3965
3966         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3967         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3968         tw32_f(MAC_MODE, tp->mac_mode);
3969         udelay(40);
3970
3971         if (tp->phy_id == PHY_ID_BCM8002)
3972                 tg3_init_bcm8002(tp);
3973
3974         /* Enable link change event even when serdes polling.  */
3975         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3976         udelay(40);
3977
3978         current_link_up = 0;
3979         mac_status = tr32(MAC_STATUS);
3980
3981         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3982                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3983         else
3984                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3985
3986         tp->napi[0].hw_status->status =
3987                 (SD_STATUS_UPDATED |
3988                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3989
3990         for (i = 0; i < 100; i++) {
3991                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3992                                     MAC_STATUS_CFG_CHANGED));
3993                 udelay(5);
3994                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3995                                          MAC_STATUS_CFG_CHANGED |
3996                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3997                         break;
3998         }
3999
4000         mac_status = tr32(MAC_STATUS);
4001         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4002                 current_link_up = 0;
4003                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4004                     tp->serdes_counter == 0) {
4005                         tw32_f(MAC_MODE, (tp->mac_mode |
4006                                           MAC_MODE_SEND_CONFIGS));
4007                         udelay(1);
4008                         tw32_f(MAC_MODE, tp->mac_mode);
4009                 }
4010         }
4011
4012         if (current_link_up == 1) {
4013                 tp->link_config.active_speed = SPEED_1000;
4014                 tp->link_config.active_duplex = DUPLEX_FULL;
4015                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4016                                     LED_CTRL_LNKLED_OVERRIDE |
4017                                     LED_CTRL_1000MBPS_ON));
4018         } else {
4019                 tp->link_config.active_speed = SPEED_INVALID;
4020                 tp->link_config.active_duplex = DUPLEX_INVALID;
4021                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4022                                     LED_CTRL_LNKLED_OVERRIDE |
4023                                     LED_CTRL_TRAFFIC_OVERRIDE));
4024         }
4025
4026         if (current_link_up != netif_carrier_ok(tp->dev)) {
4027                 if (current_link_up)
4028                         netif_carrier_on(tp->dev);
4029                 else
4030                         netif_carrier_off(tp->dev);
4031                 tg3_link_report(tp);
4032         } else {
4033                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4034                 if (orig_pause_cfg != now_pause_cfg ||
4035                     orig_active_speed != tp->link_config.active_speed ||
4036                     orig_active_duplex != tp->link_config.active_duplex)
4037                         tg3_link_report(tp);
4038         }
4039
4040         return 0;
4041 }
4042
4043 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4044 {
4045         int current_link_up, err = 0;
4046         u32 bmsr, bmcr;
4047         u16 current_speed;
4048         u8 current_duplex;
4049         u32 local_adv, remote_adv;
4050
4051         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4052         tw32_f(MAC_MODE, tp->mac_mode);
4053         udelay(40);
4054
4055         tw32(MAC_EVENT, 0);
4056
4057         tw32_f(MAC_STATUS,
4058              (MAC_STATUS_SYNC_CHANGED |
4059               MAC_STATUS_CFG_CHANGED |
4060               MAC_STATUS_MI_COMPLETION |
4061               MAC_STATUS_LNKSTATE_CHANGED));
4062         udelay(40);
4063
4064         if (force_reset)
4065                 tg3_phy_reset(tp);
4066
4067         current_link_up = 0;
4068         current_speed = SPEED_INVALID;
4069         current_duplex = DUPLEX_INVALID;
4070
4071         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4072         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4073         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4074                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4075                         bmsr |= BMSR_LSTATUS;
4076                 else
4077                         bmsr &= ~BMSR_LSTATUS;
4078         }
4079
4080         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4081
4082         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4083             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4084                 /* do nothing, just check for link up at the end */
4085         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4086                 u32 adv, new_adv;
4087
4088                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4089                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4090                                   ADVERTISE_1000XPAUSE |
4091                                   ADVERTISE_1000XPSE_ASYM |
4092                                   ADVERTISE_SLCT);
4093
4094                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4095
4096                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4097                         new_adv |= ADVERTISE_1000XHALF;
4098                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4099                         new_adv |= ADVERTISE_1000XFULL;
4100
4101                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4102                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4103                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4104                         tg3_writephy(tp, MII_BMCR, bmcr);
4105
4106                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4107                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4108                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4109
4110                         return err;
4111                 }
4112         } else {
4113                 u32 new_bmcr;
4114
4115                 bmcr &= ~BMCR_SPEED1000;
4116                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4117
4118                 if (tp->link_config.duplex == DUPLEX_FULL)
4119                         new_bmcr |= BMCR_FULLDPLX;
4120
4121                 if (new_bmcr != bmcr) {
4122                         /* BMCR_SPEED1000 is a reserved bit that needs
4123                          * to be set on write.
4124                          */
4125                         new_bmcr |= BMCR_SPEED1000;
4126
4127                         /* Force a linkdown */
4128                         if (netif_carrier_ok(tp->dev)) {
4129                                 u32 adv;
4130
4131                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4132                                 adv &= ~(ADVERTISE_1000XFULL |
4133                                          ADVERTISE_1000XHALF |
4134                                          ADVERTISE_SLCT);
4135                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4136                                 tg3_writephy(tp, MII_BMCR, bmcr |
4137                                                            BMCR_ANRESTART |
4138                                                            BMCR_ANENABLE);
4139                                 udelay(10);
4140                                 netif_carrier_off(tp->dev);
4141                         }
4142                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4143                         bmcr = new_bmcr;
4144                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4145                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4146                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4147                             ASIC_REV_5714) {
4148                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4149                                         bmsr |= BMSR_LSTATUS;
4150                                 else
4151                                         bmsr &= ~BMSR_LSTATUS;
4152                         }
4153                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4154                 }
4155         }
4156
4157         if (bmsr & BMSR_LSTATUS) {
4158                 current_speed = SPEED_1000;
4159                 current_link_up = 1;
4160                 if (bmcr & BMCR_FULLDPLX)
4161                         current_duplex = DUPLEX_FULL;
4162                 else
4163                         current_duplex = DUPLEX_HALF;
4164
4165                 local_adv = 0;
4166                 remote_adv = 0;
4167
4168                 if (bmcr & BMCR_ANENABLE) {
4169                         u32 common;
4170
4171                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4172                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4173                         common = local_adv & remote_adv;
4174                         if (common & (ADVERTISE_1000XHALF |
4175                                       ADVERTISE_1000XFULL)) {
4176                                 if (common & ADVERTISE_1000XFULL)
4177                                         current_duplex = DUPLEX_FULL;
4178                                 else
4179                                         current_duplex = DUPLEX_HALF;
4180                         }
4181                         else
4182                                 current_link_up = 0;
4183                 }
4184         }
4185
4186         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4187                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4188
4189         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4190         if (tp->link_config.active_duplex == DUPLEX_HALF)
4191                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4192
4193         tw32_f(MAC_MODE, tp->mac_mode);
4194         udelay(40);
4195
4196         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4197
4198         tp->link_config.active_speed = current_speed;
4199         tp->link_config.active_duplex = current_duplex;
4200
4201         if (current_link_up != netif_carrier_ok(tp->dev)) {
4202                 if (current_link_up)
4203                         netif_carrier_on(tp->dev);
4204                 else {
4205                         netif_carrier_off(tp->dev);
4206                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4207                 }
4208                 tg3_link_report(tp);
4209         }
4210         return err;
4211 }
4212
4213 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4214 {
4215         if (tp->serdes_counter) {
4216                 /* Give autoneg time to complete. */
4217                 tp->serdes_counter--;
4218                 return;
4219         }
4220         if (!netif_carrier_ok(tp->dev) &&
4221             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4222                 u32 bmcr;
4223
4224                 tg3_readphy(tp, MII_BMCR, &bmcr);
4225                 if (bmcr & BMCR_ANENABLE) {
4226                         u32 phy1, phy2;
4227
4228                         /* Select shadow register 0x1f */
4229                         tg3_writephy(tp, 0x1c, 0x7c00);
4230                         tg3_readphy(tp, 0x1c, &phy1);
4231
4232                         /* Select expansion interrupt status register */
4233                         tg3_writephy(tp, 0x17, 0x0f01);
4234                         tg3_readphy(tp, 0x15, &phy2);
4235                         tg3_readphy(tp, 0x15, &phy2);
4236
4237                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4238                                 /* We have signal detect and not receiving
4239                                  * config code words, link is up by parallel
4240                                  * detection.
4241                                  */
4242
4243                                 bmcr &= ~BMCR_ANENABLE;
4244                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4245                                 tg3_writephy(tp, MII_BMCR, bmcr);
4246                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4247                         }
4248                 }
4249         }
4250         else if (netif_carrier_ok(tp->dev) &&
4251                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4252                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4253                 u32 phy2;
4254
4255                 /* Select expansion interrupt status register */
4256                 tg3_writephy(tp, 0x17, 0x0f01);
4257                 tg3_readphy(tp, 0x15, &phy2);
4258                 if (phy2 & 0x20) {
4259                         u32 bmcr;
4260
4261                         /* Config code words received, turn on autoneg. */
4262                         tg3_readphy(tp, MII_BMCR, &bmcr);
4263                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4264
4265                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4266
4267                 }
4268         }
4269 }
4270
4271 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4272 {
4273         int err;
4274
4275         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4276                 err = tg3_setup_fiber_phy(tp, force_reset);
4277         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4278                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4279         } else {
4280                 err = tg3_setup_copper_phy(tp, force_reset);
4281         }
4282
4283         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4284                 u32 val, scale;
4285
4286                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4287                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4288                         scale = 65;
4289                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4290                         scale = 6;
4291                 else
4292                         scale = 12;
4293
4294                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4295                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4296                 tw32(GRC_MISC_CFG, val);
4297         }
4298
4299         if (tp->link_config.active_speed == SPEED_1000 &&
4300             tp->link_config.active_duplex == DUPLEX_HALF)
4301                 tw32(MAC_TX_LENGTHS,
4302                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4303                       (6 << TX_LENGTHS_IPG_SHIFT) |
4304                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4305         else
4306                 tw32(MAC_TX_LENGTHS,
4307                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4308                       (6 << TX_LENGTHS_IPG_SHIFT) |
4309                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4310
4311         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4312                 if (netif_carrier_ok(tp->dev)) {
4313                         tw32(HOSTCC_STAT_COAL_TICKS,
4314                              tp->coal.stats_block_coalesce_usecs);
4315                 } else {
4316                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4317                 }
4318         }
4319
4320         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4321                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4322                 if (!netif_carrier_ok(tp->dev))
4323                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4324                               tp->pwrmgmt_thresh;
4325                 else
4326                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4327                 tw32(PCIE_PWR_MGMT_THRESH, val);
4328         }
4329
4330         return err;
4331 }
4332
4333 /* This is called whenever we suspect that the system chipset is re-
4334  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4335  * is bogus tx completions. We try to recover by setting the
4336  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4337  * in the workqueue.
4338  */
4339 static void tg3_tx_recover(struct tg3 *tp)
4340 {
4341         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4342                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4343
4344         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4345                "mapped I/O cycles to the network device, attempting to "
4346                "recover. Please report the problem to the driver maintainer "
4347                "and include system chipset information.\n", tp->dev->name);
4348
4349         spin_lock(&tp->lock);
4350         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4351         spin_unlock(&tp->lock);
4352 }
4353
4354 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4355 {
4356         smp_mb();
4357         return tnapi->tx_pending -
4358                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4359 }
4360
4361 /* Tigon3 never reports partial packet sends.  So we do not
4362  * need special logic to handle SKBs that have not had all
4363  * of their frags sent yet, like SunGEM does.
4364  */
4365 static void tg3_tx(struct tg3_napi *tnapi)
4366 {
4367         struct tg3 *tp = tnapi->tp;
4368         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4369         u32 sw_idx = tnapi->tx_cons;
4370         struct netdev_queue *txq;
4371         int index = tnapi - tp->napi;
4372
4373         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4374                 index--;
4375
4376         txq = netdev_get_tx_queue(tp->dev, index);
4377
4378         while (sw_idx != hw_idx) {
4379                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4380                 struct sk_buff *skb = ri->skb;
4381                 int i, tx_bug = 0;
4382
4383                 if (unlikely(skb == NULL)) {
4384                         tg3_tx_recover(tp);
4385                         return;
4386                 }
4387
4388                 pci_unmap_single(tp->pdev,
4389                                  pci_unmap_addr(ri, mapping),
4390                                  skb_headlen(skb),
4391                                  PCI_DMA_TODEVICE);
4392
4393                 ri->skb = NULL;
4394
4395                 sw_idx = NEXT_TX(sw_idx);
4396
4397                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4398                         ri = &tnapi->tx_buffers[sw_idx];
4399                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4400                                 tx_bug = 1;
4401
4402                         pci_unmap_page(tp->pdev,
4403                                        pci_unmap_addr(ri, mapping),
4404                                        skb_shinfo(skb)->frags[i].size,
4405                                        PCI_DMA_TODEVICE);
4406                         sw_idx = NEXT_TX(sw_idx);
4407                 }
4408
4409                 dev_kfree_skb(skb);
4410
4411                 if (unlikely(tx_bug)) {
4412                         tg3_tx_recover(tp);
4413                         return;
4414                 }
4415         }
4416
4417         tnapi->tx_cons = sw_idx;
4418
4419         /* Need to make the tx_cons update visible to tg3_start_xmit()
4420          * before checking for netif_queue_stopped().  Without the
4421          * memory barrier, there is a small possibility that tg3_start_xmit()
4422          * will miss it and cause the queue to be stopped forever.
4423          */
4424         smp_mb();
4425
4426         if (unlikely(netif_tx_queue_stopped(txq) &&
4427                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4428                 __netif_tx_lock(txq, smp_processor_id());
4429                 if (netif_tx_queue_stopped(txq) &&
4430                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4431                         netif_tx_wake_queue(txq);
4432                 __netif_tx_unlock(txq);
4433         }
4434 }
4435
4436 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4437 {
4438         if (!ri->skb)
4439                 return;
4440
4441         pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4442                          map_sz, PCI_DMA_FROMDEVICE);
4443         dev_kfree_skb_any(ri->skb);
4444         ri->skb = NULL;
4445 }
4446
4447 /* Returns size of skb allocated or < 0 on error.
4448  *
4449  * We only need to fill in the address because the other members
4450  * of the RX descriptor are invariant, see tg3_init_rings.
4451  *
4452  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4453  * posting buffers we only dirty the first cache line of the RX
4454  * descriptor (containing the address).  Whereas for the RX status
4455  * buffers the cpu only reads the last cacheline of the RX descriptor
4456  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4457  */
4458 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4459                             u32 opaque_key, u32 dest_idx_unmasked)
4460 {
4461         struct tg3_rx_buffer_desc *desc;
4462         struct ring_info *map, *src_map;
4463         struct sk_buff *skb;
4464         dma_addr_t mapping;
4465         int skb_size, dest_idx;
4466
4467         src_map = NULL;
4468         switch (opaque_key) {
4469         case RXD_OPAQUE_RING_STD:
4470                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4471                 desc = &tpr->rx_std[dest_idx];
4472                 map = &tpr->rx_std_buffers[dest_idx];
4473                 skb_size = tp->rx_pkt_map_sz;
4474                 break;
4475
4476         case RXD_OPAQUE_RING_JUMBO:
4477                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4478                 desc = &tpr->rx_jmb[dest_idx].std;
4479                 map = &tpr->rx_jmb_buffers[dest_idx];
4480                 skb_size = TG3_RX_JMB_MAP_SZ;
4481                 break;
4482
4483         default:
4484                 return -EINVAL;
4485         }
4486
4487         /* Do not overwrite any of the map or rp information
4488          * until we are sure we can commit to a new buffer.
4489          *
4490          * Callers depend upon this behavior and assume that
4491          * we leave everything unchanged if we fail.
4492          */
4493         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4494         if (skb == NULL)
4495                 return -ENOMEM;
4496
4497         skb_reserve(skb, tp->rx_offset);
4498
4499         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4500                                  PCI_DMA_FROMDEVICE);
4501         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4502                 dev_kfree_skb(skb);
4503                 return -EIO;
4504         }
4505
4506         map->skb = skb;
4507         pci_unmap_addr_set(map, mapping, mapping);
4508
4509         desc->addr_hi = ((u64)mapping >> 32);
4510         desc->addr_lo = ((u64)mapping & 0xffffffff);
4511
4512         return skb_size;
4513 }
4514
4515 /* We only need to move over in the address because the other
4516  * members of the RX descriptor are invariant.  See notes above
4517  * tg3_alloc_rx_skb for full details.
4518  */
4519 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4520                            struct tg3_rx_prodring_set *dpr,
4521                            u32 opaque_key, int src_idx,
4522                            u32 dest_idx_unmasked)
4523 {
4524         struct tg3 *tp = tnapi->tp;
4525         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4526         struct ring_info *src_map, *dest_map;
4527         int dest_idx;
4528         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4529
4530         switch (opaque_key) {
4531         case RXD_OPAQUE_RING_STD:
4532                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4533                 dest_desc = &dpr->rx_std[dest_idx];
4534                 dest_map = &dpr->rx_std_buffers[dest_idx];
4535                 src_desc = &spr->rx_std[src_idx];
4536                 src_map = &spr->rx_std_buffers[src_idx];
4537                 break;
4538
4539         case RXD_OPAQUE_RING_JUMBO:
4540                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4541                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4542                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4543                 src_desc = &spr->rx_jmb[src_idx].std;
4544                 src_map = &spr->rx_jmb_buffers[src_idx];
4545                 break;
4546
4547         default:
4548                 return;
4549         }
4550
4551         dest_map->skb = src_map->skb;
4552         pci_unmap_addr_set(dest_map, mapping,
4553                            pci_unmap_addr(src_map, mapping));
4554         dest_desc->addr_hi = src_desc->addr_hi;
4555         dest_desc->addr_lo = src_desc->addr_lo;
4556
4557         /* Ensure that the update to the skb happens after the physical
4558          * addresses have been transferred to the new BD location.
4559          */
4560         smp_wmb();
4561
4562         src_map->skb = NULL;
4563 }
4564
4565 /* The RX ring scheme is composed of multiple rings which post fresh
4566  * buffers to the chip, and one special ring the chip uses to report
4567  * status back to the host.
4568  *
4569  * The special ring reports the status of received packets to the
4570  * host.  The chip does not write into the original descriptor the
4571  * RX buffer was obtained from.  The chip simply takes the original
4572  * descriptor as provided by the host, updates the status and length
4573  * field, then writes this into the next status ring entry.
4574  *
4575  * Each ring the host uses to post buffers to the chip is described
4576  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4577  * it is first placed into the on-chip ram.  When the packet's length
4578  * is known, it walks down the TG3_BDINFO entries to select the ring.
4579  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4580  * which is within the range of the new packet's length is chosen.
4581  *
4582  * The "separate ring for rx status" scheme may sound queer, but it makes
4583  * sense from a cache coherency perspective.  If only the host writes
4584  * to the buffer post rings, and only the chip writes to the rx status
4585  * rings, then cache lines never move beyond shared-modified state.
4586  * If both the host and chip were to write into the same ring, cache line
4587  * eviction could occur since both entities want it in an exclusive state.
4588  */
4589 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4590 {
4591         struct tg3 *tp = tnapi->tp;
4592         u32 work_mask, rx_std_posted = 0;
4593         u32 std_prod_idx, jmb_prod_idx;
4594         u32 sw_idx = tnapi->rx_rcb_ptr;
4595         u16 hw_idx;
4596         int received;
4597         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4598
4599         hw_idx = *(tnapi->rx_rcb_prod_idx);
4600         /*
4601          * We need to order the read of hw_idx and the read of
4602          * the opaque cookie.
4603          */
4604         rmb();
4605         work_mask = 0;
4606         received = 0;
4607         std_prod_idx = tpr->rx_std_prod_idx;
4608         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4609         while (sw_idx != hw_idx && budget > 0) {
4610                 struct ring_info *ri;
4611                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4612                 unsigned int len;
4613                 struct sk_buff *skb;
4614                 dma_addr_t dma_addr;
4615                 u32 opaque_key, desc_idx, *post_ptr;
4616
4617                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4618                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4619                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4620                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4621                         dma_addr = pci_unmap_addr(ri, mapping);
4622                         skb = ri->skb;
4623                         post_ptr = &std_prod_idx;
4624                         rx_std_posted++;
4625                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4626                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4627                         dma_addr = pci_unmap_addr(ri, mapping);
4628                         skb = ri->skb;
4629                         post_ptr = &jmb_prod_idx;
4630                 } else
4631                         goto next_pkt_nopost;
4632
4633                 work_mask |= opaque_key;
4634
4635                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4636                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4637                 drop_it:
4638                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4639                                        desc_idx, *post_ptr);
4640                 drop_it_no_recycle:
4641                         /* Other statistics kept track of by card. */
4642                         tp->net_stats.rx_dropped++;
4643                         goto next_pkt;
4644                 }
4645
4646                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4647                       ETH_FCS_LEN;
4648
4649                 if (len > RX_COPY_THRESHOLD &&
4650                     tp->rx_offset == NET_IP_ALIGN) {
4651                     /* rx_offset will likely not equal NET_IP_ALIGN
4652                      * if this is a 5701 card running in PCI-X mode
4653                      * [see tg3_get_invariants()]
4654                      */
4655                         int skb_size;
4656
4657                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4658                                                     *post_ptr);
4659                         if (skb_size < 0)
4660                                 goto drop_it;
4661
4662                         ri->skb = NULL;
4663
4664                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4665                                          PCI_DMA_FROMDEVICE);
4666
4667                         skb_put(skb, len);
4668                 } else {
4669                         struct sk_buff *copy_skb;
4670
4671                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4672                                        desc_idx, *post_ptr);
4673
4674                         copy_skb = netdev_alloc_skb(tp->dev,
4675                                                     len + TG3_RAW_IP_ALIGN);
4676                         if (copy_skb == NULL)
4677                                 goto drop_it_no_recycle;
4678
4679                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4680                         skb_put(copy_skb, len);
4681                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4682                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4683                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4684
4685                         /* We'll reuse the original ring buffer. */
4686                         skb = copy_skb;
4687                 }
4688
4689                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4690                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4691                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4692                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4693                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4694                 else
4695                         skb->ip_summed = CHECKSUM_NONE;
4696
4697                 skb->protocol = eth_type_trans(skb, tp->dev);
4698
4699                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4700                     skb->protocol != htons(ETH_P_8021Q)) {
4701                         dev_kfree_skb(skb);
4702                         goto next_pkt;
4703                 }
4704
4705 #if TG3_VLAN_TAG_USED
4706                 if (tp->vlgrp != NULL &&
4707                     desc->type_flags & RXD_FLAG_VLAN) {
4708                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4709                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4710                 } else
4711 #endif
4712                         napi_gro_receive(&tnapi->napi, skb);
4713
4714                 received++;
4715                 budget--;
4716
4717 next_pkt:
4718                 (*post_ptr)++;
4719
4720                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4721                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4722                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4723                                      tpr->rx_std_prod_idx);
4724                         work_mask &= ~RXD_OPAQUE_RING_STD;
4725                         rx_std_posted = 0;
4726                 }
4727 next_pkt_nopost:
4728                 sw_idx++;
4729                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4730
4731                 /* Refresh hw_idx to see if there is new work */
4732                 if (sw_idx == hw_idx) {
4733                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4734                         rmb();
4735                 }
4736         }
4737
4738         /* ACK the status ring. */
4739         tnapi->rx_rcb_ptr = sw_idx;
4740         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4741
4742         /* Refill RX ring(s). */
4743         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4744                 if (work_mask & RXD_OPAQUE_RING_STD) {
4745                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4746                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4747                                      tpr->rx_std_prod_idx);
4748                 }
4749                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4750                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4751                                                TG3_RX_JUMBO_RING_SIZE;
4752                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4753                                      tpr->rx_jmb_prod_idx);
4754                 }
4755                 mmiowb();
4756         } else if (work_mask) {
4757                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4758                  * updated before the producer indices can be updated.
4759                  */
4760                 smp_wmb();
4761
4762                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4763                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4764
4765                 if (tnapi != &tp->napi[1])
4766                         napi_schedule(&tp->napi[1].napi);
4767         }
4768
4769         return received;
4770 }
4771
4772 static void tg3_poll_link(struct tg3 *tp)
4773 {
4774         /* handle link change and other phy events */
4775         if (!(tp->tg3_flags &
4776               (TG3_FLAG_USE_LINKCHG_REG |
4777                TG3_FLAG_POLL_SERDES))) {
4778                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4779
4780                 if (sblk->status & SD_STATUS_LINK_CHG) {
4781                         sblk->status = SD_STATUS_UPDATED |
4782                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4783                         spin_lock(&tp->lock);
4784                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4785                                 tw32_f(MAC_STATUS,
4786                                      (MAC_STATUS_SYNC_CHANGED |
4787                                       MAC_STATUS_CFG_CHANGED |
4788                                       MAC_STATUS_MI_COMPLETION |
4789                                       MAC_STATUS_LNKSTATE_CHANGED));
4790                                 udelay(40);
4791                         } else
4792                                 tg3_setup_phy(tp, 0);
4793                         spin_unlock(&tp->lock);
4794                 }
4795         }
4796 }
4797
4798 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4799                                 struct tg3_rx_prodring_set *dpr,
4800                                 struct tg3_rx_prodring_set *spr)
4801 {
4802         u32 si, di, cpycnt, src_prod_idx;
4803         int i, err = 0;
4804
4805         while (1) {
4806                 src_prod_idx = spr->rx_std_prod_idx;
4807
4808                 /* Make sure updates to the rx_std_buffers[] entries and the
4809                  * standard producer index are seen in the correct order.
4810                  */
4811                 smp_rmb();
4812
4813                 if (spr->rx_std_cons_idx == src_prod_idx)
4814                         break;
4815
4816                 if (spr->rx_std_cons_idx < src_prod_idx)
4817                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4818                 else
4819                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4820
4821                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4822
4823                 si = spr->rx_std_cons_idx;
4824                 di = dpr->rx_std_prod_idx;
4825
4826                 for (i = di; i < di + cpycnt; i++) {
4827                         if (dpr->rx_std_buffers[i].skb) {
4828                                 cpycnt = i - di;
4829                                 err = -ENOSPC;
4830                                 break;
4831                         }
4832                 }
4833
4834                 if (!cpycnt)
4835                         break;
4836
4837                 /* Ensure that updates to the rx_std_buffers ring and the
4838                  * shadowed hardware producer ring from tg3_recycle_skb() are
4839                  * ordered correctly WRT the skb check above.
4840                  */
4841                 smp_rmb();
4842
4843                 memcpy(&dpr->rx_std_buffers[di],
4844                        &spr->rx_std_buffers[si],
4845                        cpycnt * sizeof(struct ring_info));
4846
4847                 for (i = 0; i < cpycnt; i++, di++, si++) {
4848                         struct tg3_rx_buffer_desc *sbd, *dbd;
4849                         sbd = &spr->rx_std[si];
4850                         dbd = &dpr->rx_std[di];
4851                         dbd->addr_hi = sbd->addr_hi;
4852                         dbd->addr_lo = sbd->addr_lo;
4853                 }
4854
4855                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4856                                        TG3_RX_RING_SIZE;
4857                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4858                                        TG3_RX_RING_SIZE;
4859         }
4860
4861         while (1) {
4862                 src_prod_idx = spr->rx_jmb_prod_idx;
4863
4864                 /* Make sure updates to the rx_jmb_buffers[] entries and
4865                  * the jumbo producer index are seen in the correct order.
4866                  */
4867                 smp_rmb();
4868
4869                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4870                         break;
4871
4872                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4873                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4874                 else
4875                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4876
4877                 cpycnt = min(cpycnt,
4878                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4879
4880                 si = spr->rx_jmb_cons_idx;
4881                 di = dpr->rx_jmb_prod_idx;
4882
4883                 for (i = di; i < di + cpycnt; i++) {
4884                         if (dpr->rx_jmb_buffers[i].skb) {
4885                                 cpycnt = i - di;
4886                                 err = -ENOSPC;
4887                                 break;
4888                         }
4889                 }
4890
4891                 if (!cpycnt)
4892                         break;
4893
4894                 /* Ensure that updates to the rx_jmb_buffers ring and the
4895                  * shadowed hardware producer ring from tg3_recycle_skb() are
4896                  * ordered correctly WRT the skb check above.
4897                  */
4898                 smp_rmb();
4899
4900                 memcpy(&dpr->rx_jmb_buffers[di],
4901                        &spr->rx_jmb_buffers[si],
4902                        cpycnt * sizeof(struct ring_info));
4903
4904                 for (i = 0; i < cpycnt; i++, di++, si++) {
4905                         struct tg3_rx_buffer_desc *sbd, *dbd;
4906                         sbd = &spr->rx_jmb[si].std;
4907                         dbd = &dpr->rx_jmb[di].std;
4908                         dbd->addr_hi = sbd->addr_hi;
4909                         dbd->addr_lo = sbd->addr_lo;
4910                 }
4911
4912                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4913                                        TG3_RX_JUMBO_RING_SIZE;
4914                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4915                                        TG3_RX_JUMBO_RING_SIZE;
4916         }
4917
4918         return err;
4919 }
4920
4921 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4922 {
4923         struct tg3 *tp = tnapi->tp;
4924
4925         /* run TX completion thread */
4926         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4927                 tg3_tx(tnapi);
4928                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4929                         return work_done;
4930         }
4931
4932         /* run RX thread, within the bounds set by NAPI.
4933          * All RX "locking" is done by ensuring outside
4934          * code synchronizes with tg3->napi.poll()
4935          */
4936         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4937                 work_done += tg3_rx(tnapi, budget - work_done);
4938
4939         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4940                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4941                 int i, err = 0;
4942                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4943                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4944
4945                 for (i = 1; i < tp->irq_cnt; i++)
4946                         err |= tg3_rx_prodring_xfer(tp, dpr,
4947                                                     tp->napi[i].prodring);
4948
4949                 wmb();
4950
4951                 if (std_prod_idx != dpr->rx_std_prod_idx)
4952                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4953                                      dpr->rx_std_prod_idx);
4954
4955                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4956                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4957                                      dpr->rx_jmb_prod_idx);
4958
4959                 mmiowb();
4960
4961                 if (err)
4962                         tw32_f(HOSTCC_MODE, tp->coal_now);
4963         }
4964
4965         return work_done;
4966 }
4967
4968 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4969 {
4970         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4971         struct tg3 *tp = tnapi->tp;
4972         int work_done = 0;
4973         struct tg3_hw_status *sblk = tnapi->hw_status;
4974
4975         while (1) {
4976                 work_done = tg3_poll_work(tnapi, work_done, budget);
4977
4978                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4979                         goto tx_recovery;
4980
4981                 if (unlikely(work_done >= budget))
4982                         break;
4983
4984                 /* tp->last_tag is used in tg3_restart_ints() below
4985                  * to tell the hw how much work has been processed,
4986                  * so we must read it before checking for more work.
4987                  */
4988                 tnapi->last_tag = sblk->status_tag;
4989                 tnapi->last_irq_tag = tnapi->last_tag;
4990                 rmb();
4991
4992                 /* check for RX/TX work to do */
4993                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4994                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4995                         napi_complete(napi);
4996                         /* Reenable interrupts. */
4997                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4998                         mmiowb();
4999                         break;
5000                 }
5001         }
5002
5003         return work_done;
5004
5005 tx_recovery:
5006         /* work_done is guaranteed to be less than budget. */
5007         napi_complete(napi);
5008         schedule_work(&tp->reset_task);
5009         return work_done;
5010 }
5011
5012 static int tg3_poll(struct napi_struct *napi, int budget)
5013 {
5014         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5015         struct tg3 *tp = tnapi->tp;
5016         int work_done = 0;
5017         struct tg3_hw_status *sblk = tnapi->hw_status;
5018
5019         while (1) {
5020                 tg3_poll_link(tp);
5021
5022                 work_done = tg3_poll_work(tnapi, work_done, budget);
5023
5024                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5025                         goto tx_recovery;
5026
5027                 if (unlikely(work_done >= budget))
5028                         break;
5029
5030                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5031                         /* tp->last_tag is used in tg3_int_reenable() below
5032                          * to tell the hw how much work has been processed,
5033                          * so we must read it before checking for more work.
5034                          */
5035                         tnapi->last_tag = sblk->status_tag;
5036                         tnapi->last_irq_tag = tnapi->last_tag;
5037                         rmb();
5038                 } else
5039                         sblk->status &= ~SD_STATUS_UPDATED;
5040
5041                 if (likely(!tg3_has_work(tnapi))) {
5042                         napi_complete(napi);
5043                         tg3_int_reenable(tnapi);
5044                         break;
5045                 }
5046         }
5047
5048         return work_done;
5049
5050 tx_recovery:
5051         /* work_done is guaranteed to be less than budget. */
5052         napi_complete(napi);
5053         schedule_work(&tp->reset_task);
5054         return work_done;
5055 }
5056
5057 static void tg3_irq_quiesce(struct tg3 *tp)
5058 {
5059         int i;
5060
5061         BUG_ON(tp->irq_sync);
5062
5063         tp->irq_sync = 1;
5064         smp_mb();
5065
5066         for (i = 0; i < tp->irq_cnt; i++)
5067                 synchronize_irq(tp->napi[i].irq_vec);
5068 }
5069
5070 static inline int tg3_irq_sync(struct tg3 *tp)
5071 {
5072         return tp->irq_sync;
5073 }
5074
5075 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5076  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5077  * with as well.  Most of the time, this is not necessary except when
5078  * shutting down the device.
5079  */
5080 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5081 {
5082         spin_lock_bh(&tp->lock);
5083         if (irq_sync)
5084                 tg3_irq_quiesce(tp);
5085 }
5086
5087 static inline void tg3_full_unlock(struct tg3 *tp)
5088 {
5089         spin_unlock_bh(&tp->lock);
5090 }
5091
5092 /* One-shot MSI handler - Chip automatically disables interrupt
5093  * after sending MSI so driver doesn't have to do it.
5094  */
5095 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5096 {
5097         struct tg3_napi *tnapi = dev_id;
5098         struct tg3 *tp = tnapi->tp;
5099
5100         prefetch(tnapi->hw_status);
5101         if (tnapi->rx_rcb)
5102                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5103
5104         if (likely(!tg3_irq_sync(tp)))
5105                 napi_schedule(&tnapi->napi);
5106
5107         return IRQ_HANDLED;
5108 }
5109
5110 /* MSI ISR - No need to check for interrupt sharing and no need to
5111  * flush status block and interrupt mailbox. PCI ordering rules
5112  * guarantee that MSI will arrive after the status block.
5113  */
5114 static irqreturn_t tg3_msi(int irq, void *dev_id)
5115 {
5116         struct tg3_napi *tnapi = dev_id;
5117         struct tg3 *tp = tnapi->tp;
5118
5119         prefetch(tnapi->hw_status);
5120         if (tnapi->rx_rcb)
5121                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5122         /*
5123          * Writing any value to intr-mbox-0 clears PCI INTA# and
5124          * chip-internal interrupt pending events.
5125          * Writing non-zero to intr-mbox-0 additional tells the
5126          * NIC to stop sending us irqs, engaging "in-intr-handler"
5127          * event coalescing.
5128          */
5129         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5130         if (likely(!tg3_irq_sync(tp)))
5131                 napi_schedule(&tnapi->napi);
5132
5133         return IRQ_RETVAL(1);
5134 }
5135
5136 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5137 {
5138         struct tg3_napi *tnapi = dev_id;
5139         struct tg3 *tp = tnapi->tp;
5140         struct tg3_hw_status *sblk = tnapi->hw_status;
5141         unsigned int handled = 1;
5142
5143         /* In INTx mode, it is possible for the interrupt to arrive at
5144          * the CPU before the status block posted prior to the interrupt.
5145          * Reading the PCI State register will confirm whether the
5146          * interrupt is ours and will flush the status block.
5147          */
5148         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5149                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5150                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5151                         handled = 0;
5152                         goto out;
5153                 }
5154         }
5155
5156         /*
5157          * Writing any value to intr-mbox-0 clears PCI INTA# and
5158          * chip-internal interrupt pending events.
5159          * Writing non-zero to intr-mbox-0 additional tells the
5160          * NIC to stop sending us irqs, engaging "in-intr-handler"
5161          * event coalescing.
5162          *
5163          * Flush the mailbox to de-assert the IRQ immediately to prevent
5164          * spurious interrupts.  The flush impacts performance but
5165          * excessive spurious interrupts can be worse in some cases.
5166          */
5167         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5168         if (tg3_irq_sync(tp))
5169                 goto out;
5170         sblk->status &= ~SD_STATUS_UPDATED;
5171         if (likely(tg3_has_work(tnapi))) {
5172                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5173                 napi_schedule(&tnapi->napi);
5174         } else {
5175                 /* No work, shared interrupt perhaps?  re-enable
5176                  * interrupts, and flush that PCI write
5177                  */
5178                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5179                                0x00000000);
5180         }
5181 out:
5182         return IRQ_RETVAL(handled);
5183 }
5184
5185 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5186 {
5187         struct tg3_napi *tnapi = dev_id;
5188         struct tg3 *tp = tnapi->tp;
5189         struct tg3_hw_status *sblk = tnapi->hw_status;
5190         unsigned int handled = 1;
5191
5192         /* In INTx mode, it is possible for the interrupt to arrive at
5193          * the CPU before the status block posted prior to the interrupt.
5194          * Reading the PCI State register will confirm whether the
5195          * interrupt is ours and will flush the status block.
5196          */
5197         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5198                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5199                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5200                         handled = 0;
5201                         goto out;
5202                 }
5203         }
5204
5205         /*
5206          * writing any value to intr-mbox-0 clears PCI INTA# and
5207          * chip-internal interrupt pending events.
5208          * writing non-zero to intr-mbox-0 additional tells the
5209          * NIC to stop sending us irqs, engaging "in-intr-handler"
5210          * event coalescing.
5211          *
5212          * Flush the mailbox to de-assert the IRQ immediately to prevent
5213          * spurious interrupts.  The flush impacts performance but
5214          * excessive spurious interrupts can be worse in some cases.
5215          */
5216         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5217
5218         /*
5219          * In a shared interrupt configuration, sometimes other devices'
5220          * interrupts will scream.  We record the current status tag here
5221          * so that the above check can report that the screaming interrupts
5222          * are unhandled.  Eventually they will be silenced.
5223          */
5224         tnapi->last_irq_tag = sblk->status_tag;
5225
5226         if (tg3_irq_sync(tp))
5227                 goto out;
5228
5229         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5230
5231         napi_schedule(&tnapi->napi);
5232
5233 out:
5234         return IRQ_RETVAL(handled);
5235 }
5236
5237 /* ISR for interrupt test */
5238 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5239 {
5240         struct tg3_napi *tnapi = dev_id;
5241         struct tg3 *tp = tnapi->tp;
5242         struct tg3_hw_status *sblk = tnapi->hw_status;
5243
5244         if ((sblk->status & SD_STATUS_UPDATED) ||
5245             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5246                 tg3_disable_ints(tp);
5247                 return IRQ_RETVAL(1);
5248         }
5249         return IRQ_RETVAL(0);
5250 }
5251
5252 static int tg3_init_hw(struct tg3 *, int);
5253 static int tg3_halt(struct tg3 *, int, int);
5254
5255 /* Restart hardware after configuration changes, self-test, etc.
5256  * Invoked with tp->lock held.
5257  */
5258 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5259         __releases(tp->lock)
5260         __acquires(tp->lock)
5261 {
5262         int err;
5263
5264         err = tg3_init_hw(tp, reset_phy);
5265         if (err) {
5266                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5267                        "aborting.\n", tp->dev->name);
5268                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5269                 tg3_full_unlock(tp);
5270                 del_timer_sync(&tp->timer);
5271                 tp->irq_sync = 0;
5272                 tg3_napi_enable(tp);
5273                 dev_close(tp->dev);
5274                 tg3_full_lock(tp, 0);
5275         }
5276         return err;
5277 }
5278
5279 #ifdef CONFIG_NET_POLL_CONTROLLER
5280 static void tg3_poll_controller(struct net_device *dev)
5281 {
5282         int i;
5283         struct tg3 *tp = netdev_priv(dev);
5284
5285         for (i = 0; i < tp->irq_cnt; i++)
5286                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5287 }
5288 #endif
5289
5290 static void tg3_reset_task(struct work_struct *work)
5291 {
5292         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5293         int err;
5294         unsigned int restart_timer;
5295
5296         tg3_full_lock(tp, 0);
5297
5298         if (!netif_running(tp->dev)) {
5299                 tg3_full_unlock(tp);
5300                 return;
5301         }
5302
5303         tg3_full_unlock(tp);
5304
5305         tg3_phy_stop(tp);
5306
5307         tg3_netif_stop(tp);
5308
5309         tg3_full_lock(tp, 1);
5310
5311         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5312         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5313
5314         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5315                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5316                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5317                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5318                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5319         }
5320
5321         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5322         err = tg3_init_hw(tp, 1);
5323         if (err)
5324                 goto out;
5325
5326         tg3_netif_start(tp);
5327
5328         if (restart_timer)
5329                 mod_timer(&tp->timer, jiffies + 1);
5330
5331 out:
5332         tg3_full_unlock(tp);
5333
5334         if (!err)
5335                 tg3_phy_start(tp);
5336 }
5337
5338 static void tg3_dump_short_state(struct tg3 *tp)
5339 {
5340         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5341                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5342         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5343                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5344 }
5345
5346 static void tg3_tx_timeout(struct net_device *dev)
5347 {
5348         struct tg3 *tp = netdev_priv(dev);
5349
5350         if (netif_msg_tx_err(tp)) {
5351                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5352                        dev->name);
5353                 tg3_dump_short_state(tp);
5354         }
5355
5356         schedule_work(&tp->reset_task);
5357 }
5358
5359 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5360 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5361 {
5362         u32 base = (u32) mapping & 0xffffffff;
5363
5364         return ((base > 0xffffdcc0) &&
5365                 (base + len + 8 < base));
5366 }
5367
5368 /* Test for DMA addresses > 40-bit */
5369 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5370                                           int len)
5371 {
5372 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5373         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5374                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5375         return 0;
5376 #else
5377         return 0;
5378 #endif
5379 }
5380
5381 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5382
5383 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5384 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5385                                        struct sk_buff *skb, u32 last_plus_one,
5386                                        u32 *start, u32 base_flags, u32 mss)
5387 {
5388         struct tg3 *tp = tnapi->tp;
5389         struct sk_buff *new_skb;
5390         dma_addr_t new_addr = 0;
5391         u32 entry = *start;
5392         int i, ret = 0;
5393
5394         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5395                 new_skb = skb_copy(skb, GFP_ATOMIC);
5396         else {
5397                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5398
5399                 new_skb = skb_copy_expand(skb,
5400                                           skb_headroom(skb) + more_headroom,
5401                                           skb_tailroom(skb), GFP_ATOMIC);
5402         }
5403
5404         if (!new_skb) {
5405                 ret = -1;
5406         } else {
5407                 /* New SKB is guaranteed to be linear. */
5408                 entry = *start;
5409                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5410                                           PCI_DMA_TODEVICE);
5411                 /* Make sure the mapping succeeded */
5412                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5413                         ret = -1;
5414                         dev_kfree_skb(new_skb);
5415                         new_skb = NULL;
5416
5417                 /* Make sure new skb does not cross any 4G boundaries.
5418                  * Drop the packet if it does.
5419                  */
5420                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5421                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5422                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5423                                          PCI_DMA_TODEVICE);
5424                         ret = -1;
5425                         dev_kfree_skb(new_skb);
5426                         new_skb = NULL;
5427                 } else {
5428                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5429                                     base_flags, 1 | (mss << 1));
5430                         *start = NEXT_TX(entry);
5431                 }
5432         }
5433
5434         /* Now clean up the sw ring entries. */
5435         i = 0;
5436         while (entry != last_plus_one) {
5437                 int len;
5438
5439                 if (i == 0)
5440                         len = skb_headlen(skb);
5441                 else
5442                         len = skb_shinfo(skb)->frags[i-1].size;
5443
5444                 pci_unmap_single(tp->pdev,
5445                                  pci_unmap_addr(&tnapi->tx_buffers[entry],
5446                                                 mapping),
5447                                  len, PCI_DMA_TODEVICE);
5448                 if (i == 0) {
5449                         tnapi->tx_buffers[entry].skb = new_skb;
5450                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5451                                            new_addr);
5452                 } else {
5453                         tnapi->tx_buffers[entry].skb = NULL;
5454                 }
5455                 entry = NEXT_TX(entry);
5456                 i++;
5457         }
5458
5459         dev_kfree_skb(skb);
5460
5461         return ret;
5462 }
5463
5464 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5465                         dma_addr_t mapping, int len, u32 flags,
5466                         u32 mss_and_is_end)
5467 {
5468         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5469         int is_end = (mss_and_is_end & 0x1);
5470         u32 mss = (mss_and_is_end >> 1);
5471         u32 vlan_tag = 0;
5472
5473         if (is_end)
5474                 flags |= TXD_FLAG_END;
5475         if (flags & TXD_FLAG_VLAN) {
5476                 vlan_tag = flags >> 16;
5477                 flags &= 0xffff;
5478         }
5479         vlan_tag |= (mss << TXD_MSS_SHIFT);
5480
5481         txd->addr_hi = ((u64) mapping >> 32);
5482         txd->addr_lo = ((u64) mapping & 0xffffffff);
5483         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5484         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5485 }
5486
5487 /* hard_start_xmit for devices that don't have any bugs and
5488  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5489  */
5490 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5491                                   struct net_device *dev)
5492 {
5493         struct tg3 *tp = netdev_priv(dev);
5494         u32 len, entry, base_flags, mss;
5495         dma_addr_t mapping;
5496         struct tg3_napi *tnapi;
5497         struct netdev_queue *txq;
5498         unsigned int i, last;
5499
5500
5501         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5502         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5503         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5504                 tnapi++;
5505
5506         /* We are running in BH disabled context with netif_tx_lock
5507          * and TX reclaim runs via tp->napi.poll inside of a software
5508          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5509          * no IRQ context deadlocks to worry about either.  Rejoice!
5510          */
5511         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5512                 if (!netif_tx_queue_stopped(txq)) {
5513                         netif_tx_stop_queue(txq);
5514
5515                         /* This is a hard error, log it. */
5516                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5517                                "queue awake!\n", dev->name);
5518                 }
5519                 return NETDEV_TX_BUSY;
5520         }
5521
5522         entry = tnapi->tx_prod;
5523         base_flags = 0;
5524         mss = 0;
5525         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5526                 int tcp_opt_len, ip_tcp_len;
5527                 u32 hdrlen;
5528
5529                 if (skb_header_cloned(skb) &&
5530                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5531                         dev_kfree_skb(skb);
5532                         goto out_unlock;
5533                 }
5534
5535                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5536                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5537                 else {
5538                         struct iphdr *iph = ip_hdr(skb);
5539
5540                         tcp_opt_len = tcp_optlen(skb);
5541                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5542
5543                         iph->check = 0;
5544                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5545                         hdrlen = ip_tcp_len + tcp_opt_len;
5546                 }
5547
5548                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5549                         mss |= (hdrlen & 0xc) << 12;
5550                         if (hdrlen & 0x10)
5551                                 base_flags |= 0x00000010;
5552                         base_flags |= (hdrlen & 0x3e0) << 5;
5553                 } else
5554                         mss |= hdrlen << 9;
5555
5556                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5557                                TXD_FLAG_CPU_POST_DMA);
5558
5559                 tcp_hdr(skb)->check = 0;
5560
5561         }
5562         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5563                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5564 #if TG3_VLAN_TAG_USED
5565         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5566                 base_flags |= (TXD_FLAG_VLAN |
5567                                (vlan_tx_tag_get(skb) << 16));
5568 #endif
5569
5570         len = skb_headlen(skb);
5571
5572         /* Queue skb data, a.k.a. the main skb fragment. */
5573         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5574         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5575                 dev_kfree_skb(skb);
5576                 goto out_unlock;
5577         }
5578
5579         tnapi->tx_buffers[entry].skb = skb;
5580         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5581
5582         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5583             !mss && skb->len > ETH_DATA_LEN)
5584                 base_flags |= TXD_FLAG_JMB_PKT;
5585
5586         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5587                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5588
5589         entry = NEXT_TX(entry);
5590
5591         /* Now loop through additional data fragments, and queue them. */
5592         if (skb_shinfo(skb)->nr_frags > 0) {
5593                 last = skb_shinfo(skb)->nr_frags - 1;
5594                 for (i = 0; i <= last; i++) {
5595                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5596
5597                         len = frag->size;
5598                         mapping = pci_map_page(tp->pdev,
5599                                                frag->page,
5600                                                frag->page_offset,
5601                                                len, PCI_DMA_TODEVICE);
5602                         if (pci_dma_mapping_error(tp->pdev, mapping))
5603                                 goto dma_error;
5604
5605                         tnapi->tx_buffers[entry].skb = NULL;
5606                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5607                                            mapping);
5608
5609                         tg3_set_txd(tnapi, entry, mapping, len,
5610                                     base_flags, (i == last) | (mss << 1));
5611
5612                         entry = NEXT_TX(entry);
5613                 }
5614         }
5615
5616         /* Packets are ready, update Tx producer idx local and on card. */
5617         tw32_tx_mbox(tnapi->prodmbox, entry);
5618
5619         tnapi->tx_prod = entry;
5620         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5621                 netif_tx_stop_queue(txq);
5622                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5623                         netif_tx_wake_queue(txq);
5624         }
5625
5626 out_unlock:
5627         mmiowb();
5628
5629         return NETDEV_TX_OK;
5630
5631 dma_error:
5632         last = i;
5633         entry = tnapi->tx_prod;
5634         tnapi->tx_buffers[entry].skb = NULL;
5635         pci_unmap_single(tp->pdev,
5636                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5637                          skb_headlen(skb),
5638                          PCI_DMA_TODEVICE);
5639         for (i = 0; i <= last; i++) {
5640                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5641                 entry = NEXT_TX(entry);
5642
5643                 pci_unmap_page(tp->pdev,
5644                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5645                                               mapping),
5646                                frag->size, PCI_DMA_TODEVICE);
5647         }
5648
5649         dev_kfree_skb(skb);
5650         return NETDEV_TX_OK;
5651 }
5652
5653 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5654                                           struct net_device *);
5655
5656 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5657  * TSO header is greater than 80 bytes.
5658  */
5659 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5660 {
5661         struct sk_buff *segs, *nskb;
5662         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5663
5664         /* Estimate the number of fragments in the worst case */
5665         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5666                 netif_stop_queue(tp->dev);
5667                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5668                         return NETDEV_TX_BUSY;
5669
5670                 netif_wake_queue(tp->dev);
5671         }
5672
5673         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5674         if (IS_ERR(segs))
5675                 goto tg3_tso_bug_end;
5676
5677         do {
5678                 nskb = segs;
5679                 segs = segs->next;
5680                 nskb->next = NULL;
5681                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5682         } while (segs);
5683
5684 tg3_tso_bug_end:
5685         dev_kfree_skb(skb);
5686
5687         return NETDEV_TX_OK;
5688 }
5689
5690 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5691  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5692  */
5693 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5694                                           struct net_device *dev)
5695 {
5696         struct tg3 *tp = netdev_priv(dev);
5697         u32 len, entry, base_flags, mss;
5698         int would_hit_hwbug;
5699         dma_addr_t mapping;
5700         struct tg3_napi *tnapi;
5701         struct netdev_queue *txq;
5702         unsigned int i, last;
5703
5704
5705         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5706         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5707         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5708                 tnapi++;
5709
5710         /* We are running in BH disabled context with netif_tx_lock
5711          * and TX reclaim runs via tp->napi.poll inside of a software
5712          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5713          * no IRQ context deadlocks to worry about either.  Rejoice!
5714          */
5715         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5716                 if (!netif_tx_queue_stopped(txq)) {
5717                         netif_tx_stop_queue(txq);
5718
5719                         /* This is a hard error, log it. */
5720                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5721                                "queue awake!\n", dev->name);
5722                 }
5723                 return NETDEV_TX_BUSY;
5724         }
5725
5726         entry = tnapi->tx_prod;
5727         base_flags = 0;
5728         if (skb->ip_summed == CHECKSUM_PARTIAL)
5729                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5730
5731         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5732                 struct iphdr *iph;
5733                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5734
5735                 if (skb_header_cloned(skb) &&
5736                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5737                         dev_kfree_skb(skb);
5738                         goto out_unlock;
5739                 }
5740
5741                 tcp_opt_len = tcp_optlen(skb);
5742                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5743
5744                 hdr_len = ip_tcp_len + tcp_opt_len;
5745                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5746                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5747                         return (tg3_tso_bug(tp, skb));
5748
5749                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5750                                TXD_FLAG_CPU_POST_DMA);
5751
5752                 iph = ip_hdr(skb);
5753                 iph->check = 0;
5754                 iph->tot_len = htons(mss + hdr_len);
5755                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5756                         tcp_hdr(skb)->check = 0;
5757                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5758                 } else
5759                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5760                                                                  iph->daddr, 0,
5761                                                                  IPPROTO_TCP,
5762                                                                  0);
5763
5764                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5765                         mss |= (hdr_len & 0xc) << 12;
5766                         if (hdr_len & 0x10)
5767                                 base_flags |= 0x00000010;
5768                         base_flags |= (hdr_len & 0x3e0) << 5;
5769                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5770                         mss |= hdr_len << 9;
5771                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5772                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5773                         if (tcp_opt_len || iph->ihl > 5) {
5774                                 int tsflags;
5775
5776                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5777                                 mss |= (tsflags << 11);
5778                         }
5779                 } else {
5780                         if (tcp_opt_len || iph->ihl > 5) {
5781                                 int tsflags;
5782
5783                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5784                                 base_flags |= tsflags << 12;
5785                         }
5786                 }
5787         }
5788 #if TG3_VLAN_TAG_USED
5789         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5790                 base_flags |= (TXD_FLAG_VLAN |
5791                                (vlan_tx_tag_get(skb) << 16));
5792 #endif
5793
5794         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5795             !mss && skb->len > ETH_DATA_LEN)
5796                 base_flags |= TXD_FLAG_JMB_PKT;
5797
5798         len = skb_headlen(skb);
5799
5800         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5801         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5802                 dev_kfree_skb(skb);
5803                 goto out_unlock;
5804         }
5805
5806         tnapi->tx_buffers[entry].skb = skb;
5807         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5808
5809         would_hit_hwbug = 0;
5810
5811         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5812                 would_hit_hwbug = 1;
5813
5814         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5815             tg3_4g_overflow_test(mapping, len))
5816                 would_hit_hwbug = 1;
5817
5818         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5819             tg3_40bit_overflow_test(tp, mapping, len))
5820                 would_hit_hwbug = 1;
5821
5822         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5823                 would_hit_hwbug = 1;
5824
5825         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5826                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5827
5828         entry = NEXT_TX(entry);
5829
5830         /* Now loop through additional data fragments, and queue them. */
5831         if (skb_shinfo(skb)->nr_frags > 0) {
5832                 last = skb_shinfo(skb)->nr_frags - 1;
5833                 for (i = 0; i <= last; i++) {
5834                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5835
5836                         len = frag->size;
5837                         mapping = pci_map_page(tp->pdev,
5838                                                frag->page,
5839                                                frag->page_offset,
5840                                                len, PCI_DMA_TODEVICE);
5841
5842                         tnapi->tx_buffers[entry].skb = NULL;
5843                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5844                                            mapping);
5845                         if (pci_dma_mapping_error(tp->pdev, mapping))
5846                                 goto dma_error;
5847
5848                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5849                             len <= 8)
5850                                 would_hit_hwbug = 1;
5851
5852                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5853                             tg3_4g_overflow_test(mapping, len))
5854                                 would_hit_hwbug = 1;
5855
5856                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5857                             tg3_40bit_overflow_test(tp, mapping, len))
5858                                 would_hit_hwbug = 1;
5859
5860                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5861                                 tg3_set_txd(tnapi, entry, mapping, len,
5862                                             base_flags, (i == last)|(mss << 1));
5863                         else
5864                                 tg3_set_txd(tnapi, entry, mapping, len,
5865                                             base_flags, (i == last));
5866
5867                         entry = NEXT_TX(entry);
5868                 }
5869         }
5870
5871         if (would_hit_hwbug) {
5872                 u32 last_plus_one = entry;
5873                 u32 start;
5874
5875                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5876                 start &= (TG3_TX_RING_SIZE - 1);
5877
5878                 /* If the workaround fails due to memory/mapping
5879                  * failure, silently drop this packet.
5880                  */
5881                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5882                                                 &start, base_flags, mss))
5883                         goto out_unlock;
5884
5885                 entry = start;
5886         }
5887
5888         /* Packets are ready, update Tx producer idx local and on card. */
5889         tw32_tx_mbox(tnapi->prodmbox, entry);
5890
5891         tnapi->tx_prod = entry;
5892         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5893                 netif_tx_stop_queue(txq);
5894                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5895                         netif_tx_wake_queue(txq);
5896         }
5897
5898 out_unlock:
5899         mmiowb();
5900
5901         return NETDEV_TX_OK;
5902
5903 dma_error:
5904         last = i;
5905         entry = tnapi->tx_prod;
5906         tnapi->tx_buffers[entry].skb = NULL;
5907         pci_unmap_single(tp->pdev,
5908                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5909                          skb_headlen(skb),
5910                          PCI_DMA_TODEVICE);
5911         for (i = 0; i <= last; i++) {
5912                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5913                 entry = NEXT_TX(entry);
5914
5915                 pci_unmap_page(tp->pdev,
5916                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5917                                               mapping),
5918                                frag->size, PCI_DMA_TODEVICE);
5919         }
5920
5921         dev_kfree_skb(skb);
5922         return NETDEV_TX_OK;
5923 }
5924
5925 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5926                                int new_mtu)
5927 {
5928         dev->mtu = new_mtu;
5929
5930         if (new_mtu > ETH_DATA_LEN) {
5931                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5932                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5933                         ethtool_op_set_tso(dev, 0);
5934                 }
5935                 else
5936                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5937         } else {
5938                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5939                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5940                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5941         }
5942 }
5943
5944 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5945 {
5946         struct tg3 *tp = netdev_priv(dev);
5947         int err;
5948
5949         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5950                 return -EINVAL;
5951
5952         if (!netif_running(dev)) {
5953                 /* We'll just catch it later when the
5954                  * device is up'd.
5955                  */
5956                 tg3_set_mtu(dev, tp, new_mtu);
5957                 return 0;
5958         }
5959
5960         tg3_phy_stop(tp);
5961
5962         tg3_netif_stop(tp);
5963
5964         tg3_full_lock(tp, 1);
5965
5966         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5967
5968         tg3_set_mtu(dev, tp, new_mtu);
5969
5970         err = tg3_restart_hw(tp, 0);
5971
5972         if (!err)
5973                 tg3_netif_start(tp);
5974
5975         tg3_full_unlock(tp);
5976
5977         if (!err)
5978                 tg3_phy_start(tp);
5979
5980         return err;
5981 }
5982
5983 static void tg3_rx_prodring_free(struct tg3 *tp,
5984                                  struct tg3_rx_prodring_set *tpr)
5985 {
5986         int i;
5987
5988         if (tpr != &tp->prodring[0]) {
5989                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5990                      i = (i + 1) % TG3_RX_RING_SIZE)
5991                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5992                                         tp->rx_pkt_map_sz);
5993
5994                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5995                         for (i = tpr->rx_jmb_cons_idx;
5996                              i != tpr->rx_jmb_prod_idx;
5997                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5998                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5999                                                 TG3_RX_JMB_MAP_SZ);
6000                         }
6001                 }
6002
6003                 return;
6004         }
6005
6006         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6007                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6008                                 tp->rx_pkt_map_sz);
6009
6010         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6011                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6012                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6013                                         TG3_RX_JMB_MAP_SZ);
6014         }
6015 }
6016
6017 /* Initialize tx/rx rings for packet processing.
6018  *
6019  * The chip has been shut down and the driver detached from
6020  * the networking, so no interrupts or new tx packets will
6021  * end up in the driver.  tp->{tx,}lock are held and thus
6022  * we may not sleep.
6023  */
6024 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6025                                  struct tg3_rx_prodring_set *tpr)
6026 {
6027         u32 i, rx_pkt_dma_sz;
6028
6029         tpr->rx_std_cons_idx = 0;
6030         tpr->rx_std_prod_idx = 0;
6031         tpr->rx_jmb_cons_idx = 0;
6032         tpr->rx_jmb_prod_idx = 0;
6033
6034         if (tpr != &tp->prodring[0]) {
6035                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6036                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6037                         memset(&tpr->rx_jmb_buffers[0], 0,
6038                                TG3_RX_JMB_BUFF_RING_SIZE);
6039                 goto done;
6040         }
6041
6042         /* Zero out all descriptors. */
6043         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6044
6045         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6046         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6047             tp->dev->mtu > ETH_DATA_LEN)
6048                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6049         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6050
6051         /* Initialize invariants of the rings, we only set this
6052          * stuff once.  This works because the card does not
6053          * write into the rx buffer posting rings.
6054          */
6055         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6056                 struct tg3_rx_buffer_desc *rxd;
6057
6058                 rxd = &tpr->rx_std[i];
6059                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6060                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6061                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6062                                (i << RXD_OPAQUE_INDEX_SHIFT));
6063         }
6064
6065         /* Now allocate fresh SKBs for each rx ring. */
6066         for (i = 0; i < tp->rx_pending; i++) {
6067                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6068                         printk(KERN_WARNING PFX
6069                                "%s: Using a smaller RX standard ring, "
6070                                "only %d out of %d buffers were allocated "
6071                                "successfully.\n",
6072                                tp->dev->name, i, tp->rx_pending);
6073                         if (i == 0)
6074                                 goto initfail;
6075                         tp->rx_pending = i;
6076                         break;
6077                 }
6078         }
6079
6080         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6081                 goto done;
6082
6083         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6084
6085         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6086                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6087                         struct tg3_rx_buffer_desc *rxd;
6088
6089                         rxd = &tpr->rx_jmb[i].std;
6090                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6091                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6092                                 RXD_FLAG_JUMBO;
6093                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6094                                (i << RXD_OPAQUE_INDEX_SHIFT));
6095                 }
6096
6097                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6098                         if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6099                                              i) < 0) {
6100                                 printk(KERN_WARNING PFX
6101                                        "%s: Using a smaller RX jumbo ring, "
6102                                        "only %d out of %d buffers were "
6103                                        "allocated successfully.\n",
6104                                        tp->dev->name, i, tp->rx_jumbo_pending);
6105                                 if (i == 0)
6106                                         goto initfail;
6107                                 tp->rx_jumbo_pending = i;
6108                                 break;
6109                         }
6110                 }
6111         }
6112
6113 done:
6114         return 0;
6115
6116 initfail:
6117         tg3_rx_prodring_free(tp, tpr);
6118         return -ENOMEM;
6119 }
6120
6121 static void tg3_rx_prodring_fini(struct tg3 *tp,
6122                                  struct tg3_rx_prodring_set *tpr)
6123 {
6124         kfree(tpr->rx_std_buffers);
6125         tpr->rx_std_buffers = NULL;
6126         kfree(tpr->rx_jmb_buffers);
6127         tpr->rx_jmb_buffers = NULL;
6128         if (tpr->rx_std) {
6129                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6130                                     tpr->rx_std, tpr->rx_std_mapping);
6131                 tpr->rx_std = NULL;
6132         }
6133         if (tpr->rx_jmb) {
6134                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6135                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6136                 tpr->rx_jmb = NULL;
6137         }
6138 }
6139
6140 static int tg3_rx_prodring_init(struct tg3 *tp,
6141                                 struct tg3_rx_prodring_set *tpr)
6142 {
6143         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6144         if (!tpr->rx_std_buffers)
6145                 return -ENOMEM;
6146
6147         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6148                                            &tpr->rx_std_mapping);
6149         if (!tpr->rx_std)
6150                 goto err_out;
6151
6152         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6153                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6154                                               GFP_KERNEL);
6155                 if (!tpr->rx_jmb_buffers)
6156                         goto err_out;
6157
6158                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6159                                                    TG3_RX_JUMBO_RING_BYTES,
6160                                                    &tpr->rx_jmb_mapping);
6161                 if (!tpr->rx_jmb)
6162                         goto err_out;
6163         }
6164
6165         return 0;
6166
6167 err_out:
6168         tg3_rx_prodring_fini(tp, tpr);
6169         return -ENOMEM;
6170 }
6171
6172 /* Free up pending packets in all rx/tx rings.
6173  *
6174  * The chip has been shut down and the driver detached from
6175  * the networking, so no interrupts or new tx packets will
6176  * end up in the driver.  tp->{tx,}lock is not held and we are not
6177  * in an interrupt context and thus may sleep.
6178  */
6179 static void tg3_free_rings(struct tg3 *tp)
6180 {
6181         int i, j;
6182
6183         for (j = 0; j < tp->irq_cnt; j++) {
6184                 struct tg3_napi *tnapi = &tp->napi[j];
6185
6186                 if (!tnapi->tx_buffers)
6187                         continue;
6188
6189                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6190                         struct ring_info *txp;
6191                         struct sk_buff *skb;
6192                         unsigned int k;
6193
6194                         txp = &tnapi->tx_buffers[i];
6195                         skb = txp->skb;
6196
6197                         if (skb == NULL) {
6198                                 i++;
6199                                 continue;
6200                         }
6201
6202                         pci_unmap_single(tp->pdev,
6203                                          pci_unmap_addr(txp, mapping),
6204                                          skb_headlen(skb),
6205                                          PCI_DMA_TODEVICE);
6206                         txp->skb = NULL;
6207
6208                         i++;
6209
6210                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6211                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6212                                 pci_unmap_page(tp->pdev,
6213                                                pci_unmap_addr(txp, mapping),
6214                                                skb_shinfo(skb)->frags[k].size,
6215                                                PCI_DMA_TODEVICE);
6216                                 i++;
6217                         }
6218
6219                         dev_kfree_skb_any(skb);
6220                 }
6221
6222                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6223         }
6224 }
6225
6226 /* Initialize tx/rx rings for packet processing.
6227  *
6228  * The chip has been shut down and the driver detached from
6229  * the networking, so no interrupts or new tx packets will
6230  * end up in the driver.  tp->{tx,}lock are held and thus
6231  * we may not sleep.
6232  */
6233 static int tg3_init_rings(struct tg3 *tp)
6234 {
6235         int i;
6236
6237         /* Free up all the SKBs. */
6238         tg3_free_rings(tp);
6239
6240         for (i = 0; i < tp->irq_cnt; i++) {
6241                 struct tg3_napi *tnapi = &tp->napi[i];
6242
6243                 tnapi->last_tag = 0;
6244                 tnapi->last_irq_tag = 0;
6245                 tnapi->hw_status->status = 0;
6246                 tnapi->hw_status->status_tag = 0;
6247                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6248
6249                 tnapi->tx_prod = 0;
6250                 tnapi->tx_cons = 0;
6251                 if (tnapi->tx_ring)
6252                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6253
6254                 tnapi->rx_rcb_ptr = 0;
6255                 if (tnapi->rx_rcb)
6256                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6257
6258                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6259                         tg3_free_rings(tp);
6260                         return -ENOMEM;
6261                 }
6262         }
6263
6264         return 0;
6265 }
6266
6267 /*
6268  * Must not be invoked with interrupt sources disabled and
6269  * the hardware shutdown down.
6270  */
6271 static void tg3_free_consistent(struct tg3 *tp)
6272 {
6273         int i;
6274
6275         for (i = 0; i < tp->irq_cnt; i++) {
6276                 struct tg3_napi *tnapi = &tp->napi[i];
6277
6278                 if (tnapi->tx_ring) {
6279                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6280                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6281                         tnapi->tx_ring = NULL;
6282                 }
6283
6284                 kfree(tnapi->tx_buffers);
6285                 tnapi->tx_buffers = NULL;
6286
6287                 if (tnapi->rx_rcb) {
6288                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6289                                             tnapi->rx_rcb,
6290                                             tnapi->rx_rcb_mapping);
6291                         tnapi->rx_rcb = NULL;
6292                 }
6293
6294                 if (tnapi->hw_status) {
6295                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6296                                             tnapi->hw_status,
6297                                             tnapi->status_mapping);
6298                         tnapi->hw_status = NULL;
6299                 }
6300         }
6301
6302         if (tp->hw_stats) {
6303                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6304                                     tp->hw_stats, tp->stats_mapping);
6305                 tp->hw_stats = NULL;
6306         }
6307
6308         for (i = 0; i < tp->irq_cnt; i++)
6309                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6310 }
6311
6312 /*
6313  * Must not be invoked with interrupt sources disabled and
6314  * the hardware shutdown down.  Can sleep.
6315  */
6316 static int tg3_alloc_consistent(struct tg3 *tp)
6317 {
6318         int i;
6319
6320         for (i = 0; i < tp->irq_cnt; i++) {
6321                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6322                         goto err_out;
6323         }
6324
6325         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6326                                             sizeof(struct tg3_hw_stats),
6327                                             &tp->stats_mapping);
6328         if (!tp->hw_stats)
6329                 goto err_out;
6330
6331         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6332
6333         for (i = 0; i < tp->irq_cnt; i++) {
6334                 struct tg3_napi *tnapi = &tp->napi[i];
6335                 struct tg3_hw_status *sblk;
6336
6337                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6338                                                         TG3_HW_STATUS_SIZE,
6339                                                         &tnapi->status_mapping);
6340                 if (!tnapi->hw_status)
6341                         goto err_out;
6342
6343                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6344                 sblk = tnapi->hw_status;
6345
6346                 /* If multivector TSS is enabled, vector 0 does not handle
6347                  * tx interrupts.  Don't allocate any resources for it.
6348                  */
6349                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6350                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6351                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6352                                                     TG3_TX_RING_SIZE,
6353                                                     GFP_KERNEL);
6354                         if (!tnapi->tx_buffers)
6355                                 goto err_out;
6356
6357                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6358                                                               TG3_TX_RING_BYTES,
6359                                                        &tnapi->tx_desc_mapping);
6360                         if (!tnapi->tx_ring)
6361                                 goto err_out;
6362                 }
6363
6364                 /*
6365                  * When RSS is enabled, the status block format changes
6366                  * slightly.  The "rx_jumbo_consumer", "reserved",
6367                  * and "rx_mini_consumer" members get mapped to the
6368                  * other three rx return ring producer indexes.
6369                  */
6370                 switch (i) {
6371                 default:
6372                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6373                         break;
6374                 case 2:
6375                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6376                         break;
6377                 case 3:
6378                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6379                         break;
6380                 case 4:
6381                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6382                         break;
6383                 }
6384
6385                 tnapi->prodring = &tp->prodring[i];
6386
6387                 /*
6388                  * If multivector RSS is enabled, vector 0 does not handle
6389                  * rx or tx interrupts.  Don't allocate any resources for it.
6390                  */
6391                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6392                         continue;
6393
6394                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6395                                                      TG3_RX_RCB_RING_BYTES(tp),
6396                                                      &tnapi->rx_rcb_mapping);
6397                 if (!tnapi->rx_rcb)
6398                         goto err_out;
6399
6400                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6401         }
6402
6403         return 0;
6404
6405 err_out:
6406         tg3_free_consistent(tp);
6407         return -ENOMEM;
6408 }
6409
6410 #define MAX_WAIT_CNT 1000
6411
6412 /* To stop a block, clear the enable bit and poll till it
6413  * clears.  tp->lock is held.
6414  */
6415 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6416 {
6417         unsigned int i;
6418         u32 val;
6419
6420         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6421                 switch (ofs) {
6422                 case RCVLSC_MODE:
6423                 case DMAC_MODE:
6424                 case MBFREE_MODE:
6425                 case BUFMGR_MODE:
6426                 case MEMARB_MODE:
6427                         /* We can't enable/disable these bits of the
6428                          * 5705/5750, just say success.
6429                          */
6430                         return 0;
6431
6432                 default:
6433                         break;
6434                 }
6435         }
6436
6437         val = tr32(ofs);
6438         val &= ~enable_bit;
6439         tw32_f(ofs, val);
6440
6441         for (i = 0; i < MAX_WAIT_CNT; i++) {
6442                 udelay(100);
6443                 val = tr32(ofs);
6444                 if ((val & enable_bit) == 0)
6445                         break;
6446         }
6447
6448         if (i == MAX_WAIT_CNT && !silent) {
6449                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6450                        "ofs=%lx enable_bit=%x\n",
6451                        ofs, enable_bit);
6452                 return -ENODEV;
6453         }
6454
6455         return 0;
6456 }
6457
6458 /* tp->lock is held. */
6459 static int tg3_abort_hw(struct tg3 *tp, int silent)
6460 {
6461         int i, err;
6462
6463         tg3_disable_ints(tp);
6464
6465         tp->rx_mode &= ~RX_MODE_ENABLE;
6466         tw32_f(MAC_RX_MODE, tp->rx_mode);
6467         udelay(10);
6468
6469         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6470         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6471         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6472         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6473         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6474         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6475
6476         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6477         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6478         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6479         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6480         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6481         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6482         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6483
6484         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6485         tw32_f(MAC_MODE, tp->mac_mode);
6486         udelay(40);
6487
6488         tp->tx_mode &= ~TX_MODE_ENABLE;
6489         tw32_f(MAC_TX_MODE, tp->tx_mode);
6490
6491         for (i = 0; i < MAX_WAIT_CNT; i++) {
6492                 udelay(100);
6493                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6494                         break;
6495         }
6496         if (i >= MAX_WAIT_CNT) {
6497                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6498                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6499                        tp->dev->name, tr32(MAC_TX_MODE));
6500                 err |= -ENODEV;
6501         }
6502
6503         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6504         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6505         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6506
6507         tw32(FTQ_RESET, 0xffffffff);
6508         tw32(FTQ_RESET, 0x00000000);
6509
6510         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6511         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6512
6513         for (i = 0; i < tp->irq_cnt; i++) {
6514                 struct tg3_napi *tnapi = &tp->napi[i];
6515                 if (tnapi->hw_status)
6516                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6517         }
6518         if (tp->hw_stats)
6519                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6520
6521         return err;
6522 }
6523
6524 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6525 {
6526         int i;
6527         u32 apedata;
6528
6529         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6530         if (apedata != APE_SEG_SIG_MAGIC)
6531                 return;
6532
6533         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6534         if (!(apedata & APE_FW_STATUS_READY))
6535                 return;
6536
6537         /* Wait for up to 1 millisecond for APE to service previous event. */
6538         for (i = 0; i < 10; i++) {
6539                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6540                         return;
6541
6542                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6543
6544                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6545                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6546                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6547
6548                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6549
6550                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6551                         break;
6552
6553                 udelay(100);
6554         }
6555
6556         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6557                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6558 }
6559
6560 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6561 {
6562         u32 event;
6563         u32 apedata;
6564
6565         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6566                 return;
6567
6568         switch (kind) {
6569                 case RESET_KIND_INIT:
6570                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6571                                         APE_HOST_SEG_SIG_MAGIC);
6572                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6573                                         APE_HOST_SEG_LEN_MAGIC);
6574                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6575                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6576                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6577                                         APE_HOST_DRIVER_ID_MAGIC);
6578                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6579                                         APE_HOST_BEHAV_NO_PHYLOCK);
6580
6581                         event = APE_EVENT_STATUS_STATE_START;
6582                         break;
6583                 case RESET_KIND_SHUTDOWN:
6584                         /* With the interface we are currently using,
6585                          * APE does not track driver state.  Wiping
6586                          * out the HOST SEGMENT SIGNATURE forces
6587                          * the APE to assume OS absent status.
6588                          */
6589                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6590
6591                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6592                         break;
6593                 case RESET_KIND_SUSPEND:
6594                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6595                         break;
6596                 default:
6597                         return;
6598         }
6599
6600         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6601
6602         tg3_ape_send_event(tp, event);
6603 }
6604
6605 /* tp->lock is held. */
6606 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6607 {
6608         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6609                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6610
6611         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6612                 switch (kind) {
6613                 case RESET_KIND_INIT:
6614                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6615                                       DRV_STATE_START);
6616                         break;
6617
6618                 case RESET_KIND_SHUTDOWN:
6619                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6620                                       DRV_STATE_UNLOAD);
6621                         break;
6622
6623                 case RESET_KIND_SUSPEND:
6624                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6625                                       DRV_STATE_SUSPEND);
6626                         break;
6627
6628                 default:
6629                         break;
6630                 }
6631         }
6632
6633         if (kind == RESET_KIND_INIT ||
6634             kind == RESET_KIND_SUSPEND)
6635                 tg3_ape_driver_state_change(tp, kind);
6636 }
6637
6638 /* tp->lock is held. */
6639 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6640 {
6641         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6642                 switch (kind) {
6643                 case RESET_KIND_INIT:
6644                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6645                                       DRV_STATE_START_DONE);
6646                         break;
6647
6648                 case RESET_KIND_SHUTDOWN:
6649                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6650                                       DRV_STATE_UNLOAD_DONE);
6651                         break;
6652
6653                 default:
6654                         break;
6655                 }
6656         }
6657
6658         if (kind == RESET_KIND_SHUTDOWN)
6659                 tg3_ape_driver_state_change(tp, kind);
6660 }
6661
6662 /* tp->lock is held. */
6663 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6664 {
6665         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6666                 switch (kind) {
6667                 case RESET_KIND_INIT:
6668                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6669                                       DRV_STATE_START);
6670                         break;
6671
6672                 case RESET_KIND_SHUTDOWN:
6673                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6674                                       DRV_STATE_UNLOAD);
6675                         break;
6676
6677                 case RESET_KIND_SUSPEND:
6678                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6679                                       DRV_STATE_SUSPEND);
6680                         break;
6681
6682                 default:
6683                         break;
6684                 }
6685         }
6686 }
6687
6688 static int tg3_poll_fw(struct tg3 *tp)
6689 {
6690         int i;
6691         u32 val;
6692
6693         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6694                 /* Wait up to 20ms for init done. */
6695                 for (i = 0; i < 200; i++) {
6696                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6697                                 return 0;
6698                         udelay(100);
6699                 }
6700                 return -ENODEV;
6701         }
6702
6703         /* Wait for firmware initialization to complete. */
6704         for (i = 0; i < 100000; i++) {
6705                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6706                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6707                         break;
6708                 udelay(10);
6709         }
6710
6711         /* Chip might not be fitted with firmware.  Some Sun onboard
6712          * parts are configured like that.  So don't signal the timeout
6713          * of the above loop as an error, but do report the lack of
6714          * running firmware once.
6715          */
6716         if (i >= 100000 &&
6717             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6718                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6719
6720                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6721                        tp->dev->name);
6722         }
6723
6724         return 0;
6725 }
6726
6727 /* Save PCI command register before chip reset */
6728 static void tg3_save_pci_state(struct tg3 *tp)
6729 {
6730         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6731 }
6732
6733 /* Restore PCI state after chip reset */
6734 static void tg3_restore_pci_state(struct tg3 *tp)
6735 {
6736         u32 val;
6737
6738         /* Re-enable indirect register accesses. */
6739         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6740                                tp->misc_host_ctrl);
6741
6742         /* Set MAX PCI retry to zero. */
6743         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6744         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6745             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6746                 val |= PCISTATE_RETRY_SAME_DMA;
6747         /* Allow reads and writes to the APE register and memory space. */
6748         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6749                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6750                        PCISTATE_ALLOW_APE_SHMEM_WR;
6751         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6752
6753         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6754
6755         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6756                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6757                         pcie_set_readrq(tp->pdev, 4096);
6758                 else {
6759                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6760                                               tp->pci_cacheline_sz);
6761                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6762                                               tp->pci_lat_timer);
6763                 }
6764         }
6765
6766         /* Make sure PCI-X relaxed ordering bit is clear. */
6767         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6768                 u16 pcix_cmd;
6769
6770                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6771                                      &pcix_cmd);
6772                 pcix_cmd &= ~PCI_X_CMD_ERO;
6773                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6774                                       pcix_cmd);
6775         }
6776
6777         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6778
6779                 /* Chip reset on 5780 will reset MSI enable bit,
6780                  * so need to restore it.
6781                  */
6782                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6783                         u16 ctrl;
6784
6785                         pci_read_config_word(tp->pdev,
6786                                              tp->msi_cap + PCI_MSI_FLAGS,
6787                                              &ctrl);
6788                         pci_write_config_word(tp->pdev,
6789                                               tp->msi_cap + PCI_MSI_FLAGS,
6790                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6791                         val = tr32(MSGINT_MODE);
6792                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6793                 }
6794         }
6795 }
6796
6797 static void tg3_stop_fw(struct tg3 *);
6798
6799 /* tp->lock is held. */
6800 static int tg3_chip_reset(struct tg3 *tp)
6801 {
6802         u32 val;
6803         void (*write_op)(struct tg3 *, u32, u32);
6804         int i, err;
6805
6806         tg3_nvram_lock(tp);
6807
6808         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6809
6810         /* No matching tg3_nvram_unlock() after this because
6811          * chip reset below will undo the nvram lock.
6812          */
6813         tp->nvram_lock_cnt = 0;
6814
6815         /* GRC_MISC_CFG core clock reset will clear the memory
6816          * enable bit in PCI register 4 and the MSI enable bit
6817          * on some chips, so we save relevant registers here.
6818          */
6819         tg3_save_pci_state(tp);
6820
6821         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6822             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6823                 tw32(GRC_FASTBOOT_PC, 0);
6824
6825         /*
6826          * We must avoid the readl() that normally takes place.
6827          * It locks machines, causes machine checks, and other
6828          * fun things.  So, temporarily disable the 5701
6829          * hardware workaround, while we do the reset.
6830          */
6831         write_op = tp->write32;
6832         if (write_op == tg3_write_flush_reg32)
6833                 tp->write32 = tg3_write32;
6834
6835         /* Prevent the irq handler from reading or writing PCI registers
6836          * during chip reset when the memory enable bit in the PCI command
6837          * register may be cleared.  The chip does not generate interrupt
6838          * at this time, but the irq handler may still be called due to irq
6839          * sharing or irqpoll.
6840          */
6841         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6842         for (i = 0; i < tp->irq_cnt; i++) {
6843                 struct tg3_napi *tnapi = &tp->napi[i];
6844                 if (tnapi->hw_status) {
6845                         tnapi->hw_status->status = 0;
6846                         tnapi->hw_status->status_tag = 0;
6847                 }
6848                 tnapi->last_tag = 0;
6849                 tnapi->last_irq_tag = 0;
6850         }
6851         smp_mb();
6852
6853         for (i = 0; i < tp->irq_cnt; i++)
6854                 synchronize_irq(tp->napi[i].irq_vec);
6855
6856         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6857                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6858                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6859         }
6860
6861         /* do the reset */
6862         val = GRC_MISC_CFG_CORECLK_RESET;
6863
6864         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6865                 if (tr32(0x7e2c) == 0x60) {
6866                         tw32(0x7e2c, 0x20);
6867                 }
6868                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6869                         tw32(GRC_MISC_CFG, (1 << 29));
6870                         val |= (1 << 29);
6871                 }
6872         }
6873
6874         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6875                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6876                 tw32(GRC_VCPU_EXT_CTRL,
6877                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6878         }
6879
6880         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6881                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6882         tw32(GRC_MISC_CFG, val);
6883
6884         /* restore 5701 hardware bug workaround write method */
6885         tp->write32 = write_op;
6886
6887         /* Unfortunately, we have to delay before the PCI read back.
6888          * Some 575X chips even will not respond to a PCI cfg access
6889          * when the reset command is given to the chip.
6890          *
6891          * How do these hardware designers expect things to work
6892          * properly if the PCI write is posted for a long period
6893          * of time?  It is always necessary to have some method by
6894          * which a register read back can occur to push the write
6895          * out which does the reset.
6896          *
6897          * For most tg3 variants the trick below was working.
6898          * Ho hum...
6899          */
6900         udelay(120);
6901
6902         /* Flush PCI posted writes.  The normal MMIO registers
6903          * are inaccessible at this time so this is the only
6904          * way to make this reliably (actually, this is no longer
6905          * the case, see above).  I tried to use indirect
6906          * register read/write but this upset some 5701 variants.
6907          */
6908         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6909
6910         udelay(120);
6911
6912         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6913                 u16 val16;
6914
6915                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6916                         int i;
6917                         u32 cfg_val;
6918
6919                         /* Wait for link training to complete.  */
6920                         for (i = 0; i < 5000; i++)
6921                                 udelay(100);
6922
6923                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6924                         pci_write_config_dword(tp->pdev, 0xc4,
6925                                                cfg_val | (1 << 15));
6926                 }
6927
6928                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6929                 pci_read_config_word(tp->pdev,
6930                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6931                                      &val16);
6932                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6933                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6934                 /*
6935                  * Older PCIe devices only support the 128 byte
6936                  * MPS setting.  Enforce the restriction.
6937                  */
6938                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6939                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6940                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6941                 pci_write_config_word(tp->pdev,
6942                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6943                                       val16);
6944
6945                 pcie_set_readrq(tp->pdev, 4096);
6946
6947                 /* Clear error status */
6948                 pci_write_config_word(tp->pdev,
6949                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6950                                       PCI_EXP_DEVSTA_CED |
6951                                       PCI_EXP_DEVSTA_NFED |
6952                                       PCI_EXP_DEVSTA_FED |
6953                                       PCI_EXP_DEVSTA_URD);
6954         }
6955
6956         tg3_restore_pci_state(tp);
6957
6958         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6959
6960         val = 0;
6961         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6962                 val = tr32(MEMARB_MODE);
6963         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6964
6965         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6966                 tg3_stop_fw(tp);
6967                 tw32(0x5000, 0x400);
6968         }
6969
6970         tw32(GRC_MODE, tp->grc_mode);
6971
6972         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6973                 val = tr32(0xc4);
6974
6975                 tw32(0xc4, val | (1 << 15));
6976         }
6977
6978         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6979             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6980                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6981                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6982                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6983                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6984         }
6985
6986         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6987                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6988                 tw32_f(MAC_MODE, tp->mac_mode);
6989         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6990                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6991                 tw32_f(MAC_MODE, tp->mac_mode);
6992         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6993                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6994                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6995                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6996                 tw32_f(MAC_MODE, tp->mac_mode);
6997         } else
6998                 tw32_f(MAC_MODE, 0);
6999         udelay(40);
7000
7001         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7002
7003         err = tg3_poll_fw(tp);
7004         if (err)
7005                 return err;
7006
7007         tg3_mdio_start(tp);
7008
7009         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7010                 u8 phy_addr;
7011
7012                 phy_addr = tp->phy_addr;
7013                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7014
7015                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7016                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7017                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7018                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7019                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
7020                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7021                 udelay(10);
7022
7023                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7024                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7025                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7026                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7027                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7028                 udelay(10);
7029
7030                 tp->phy_addr = phy_addr;
7031         }
7032
7033         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7034             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7035             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7036             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7037             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7038                 val = tr32(0x7c00);
7039
7040                 tw32(0x7c00, val | (1 << 25));
7041         }
7042
7043         /* Reprobe ASF enable state.  */
7044         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7045         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7046         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7047         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7048                 u32 nic_cfg;
7049
7050                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7051                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7052                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7053                         tp->last_event_jiffies = jiffies;
7054                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7055                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7056                 }
7057         }
7058
7059         return 0;
7060 }
7061
7062 /* tp->lock is held. */
7063 static void tg3_stop_fw(struct tg3 *tp)
7064 {
7065         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7066            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7067                 /* Wait for RX cpu to ACK the previous event. */
7068                 tg3_wait_for_event_ack(tp);
7069
7070                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7071
7072                 tg3_generate_fw_event(tp);
7073
7074                 /* Wait for RX cpu to ACK this event. */
7075                 tg3_wait_for_event_ack(tp);
7076         }
7077 }
7078
7079 /* tp->lock is held. */
7080 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7081 {
7082         int err;
7083
7084         tg3_stop_fw(tp);
7085
7086         tg3_write_sig_pre_reset(tp, kind);
7087
7088         tg3_abort_hw(tp, silent);
7089         err = tg3_chip_reset(tp);
7090
7091         __tg3_set_mac_addr(tp, 0);
7092
7093         tg3_write_sig_legacy(tp, kind);
7094         tg3_write_sig_post_reset(tp, kind);
7095
7096         if (err)
7097                 return err;
7098
7099         return 0;
7100 }
7101
7102 #define RX_CPU_SCRATCH_BASE     0x30000
7103 #define RX_CPU_SCRATCH_SIZE     0x04000
7104 #define TX_CPU_SCRATCH_BASE     0x34000
7105 #define TX_CPU_SCRATCH_SIZE     0x04000
7106
7107 /* tp->lock is held. */
7108 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7109 {
7110         int i;
7111
7112         BUG_ON(offset == TX_CPU_BASE &&
7113             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7114
7115         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7116                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7117
7118                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7119                 return 0;
7120         }
7121         if (offset == RX_CPU_BASE) {
7122                 for (i = 0; i < 10000; i++) {
7123                         tw32(offset + CPU_STATE, 0xffffffff);
7124                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7125                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7126                                 break;
7127                 }
7128
7129                 tw32(offset + CPU_STATE, 0xffffffff);
7130                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7131                 udelay(10);
7132         } else {
7133                 for (i = 0; i < 10000; i++) {
7134                         tw32(offset + CPU_STATE, 0xffffffff);
7135                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7136                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7137                                 break;
7138                 }
7139         }
7140
7141         if (i >= 10000) {
7142                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7143                        "and %s CPU\n",
7144                        tp->dev->name,
7145                        (offset == RX_CPU_BASE ? "RX" : "TX"));
7146                 return -ENODEV;
7147         }
7148
7149         /* Clear firmware's nvram arbitration. */
7150         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7151                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7152         return 0;
7153 }
7154
7155 struct fw_info {
7156         unsigned int fw_base;
7157         unsigned int fw_len;
7158         const __be32 *fw_data;
7159 };
7160
7161 /* tp->lock is held. */
7162 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7163                                  int cpu_scratch_size, struct fw_info *info)
7164 {
7165         int err, lock_err, i;
7166         void (*write_op)(struct tg3 *, u32, u32);
7167
7168         if (cpu_base == TX_CPU_BASE &&
7169             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7170                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7171                        "TX cpu firmware on %s which is 5705.\n",
7172                        tp->dev->name);
7173                 return -EINVAL;
7174         }
7175
7176         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7177                 write_op = tg3_write_mem;
7178         else
7179                 write_op = tg3_write_indirect_reg32;
7180
7181         /* It is possible that bootcode is still loading at this point.
7182          * Get the nvram lock first before halting the cpu.
7183          */
7184         lock_err = tg3_nvram_lock(tp);
7185         err = tg3_halt_cpu(tp, cpu_base);
7186         if (!lock_err)
7187                 tg3_nvram_unlock(tp);
7188         if (err)
7189                 goto out;
7190
7191         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7192                 write_op(tp, cpu_scratch_base + i, 0);
7193         tw32(cpu_base + CPU_STATE, 0xffffffff);
7194         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7195         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7196                 write_op(tp, (cpu_scratch_base +
7197                               (info->fw_base & 0xffff) +
7198                               (i * sizeof(u32))),
7199                               be32_to_cpu(info->fw_data[i]));
7200
7201         err = 0;
7202
7203 out:
7204         return err;
7205 }
7206
7207 /* tp->lock is held. */
7208 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7209 {
7210         struct fw_info info;
7211         const __be32 *fw_data;
7212         int err, i;
7213
7214         fw_data = (void *)tp->fw->data;
7215
7216         /* Firmware blob starts with version numbers, followed by
7217            start address and length. We are setting complete length.
7218            length = end_address_of_bss - start_address_of_text.
7219            Remainder is the blob to be loaded contiguously
7220            from start address. */
7221
7222         info.fw_base = be32_to_cpu(fw_data[1]);
7223         info.fw_len = tp->fw->size - 12;
7224         info.fw_data = &fw_data[3];
7225
7226         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7227                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7228                                     &info);
7229         if (err)
7230                 return err;
7231
7232         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7233                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7234                                     &info);
7235         if (err)
7236                 return err;
7237
7238         /* Now startup only the RX cpu. */
7239         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7240         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7241
7242         for (i = 0; i < 5; i++) {
7243                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7244                         break;
7245                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7246                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7247                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7248                 udelay(1000);
7249         }
7250         if (i >= 5) {
7251                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7252                        "to set RX CPU PC, is %08x should be %08x\n",
7253                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7254                        info.fw_base);
7255                 return -ENODEV;
7256         }
7257         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7258         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7259
7260         return 0;
7261 }
7262
7263 /* 5705 needs a special version of the TSO firmware.  */
7264
7265 /* tp->lock is held. */
7266 static int tg3_load_tso_firmware(struct tg3 *tp)
7267 {
7268         struct fw_info info;
7269         const __be32 *fw_data;
7270         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7271         int err, i;
7272
7273         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7274                 return 0;
7275
7276         fw_data = (void *)tp->fw->data;
7277
7278         /* Firmware blob starts with version numbers, followed by
7279            start address and length. We are setting complete length.
7280            length = end_address_of_bss - start_address_of_text.
7281            Remainder is the blob to be loaded contiguously
7282            from start address. */
7283
7284         info.fw_base = be32_to_cpu(fw_data[1]);
7285         cpu_scratch_size = tp->fw_len;
7286         info.fw_len = tp->fw->size - 12;
7287         info.fw_data = &fw_data[3];
7288
7289         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7290                 cpu_base = RX_CPU_BASE;
7291                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7292         } else {
7293                 cpu_base = TX_CPU_BASE;
7294                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7295                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7296         }
7297
7298         err = tg3_load_firmware_cpu(tp, cpu_base,
7299                                     cpu_scratch_base, cpu_scratch_size,
7300                                     &info);
7301         if (err)
7302                 return err;
7303
7304         /* Now startup the cpu. */
7305         tw32(cpu_base + CPU_STATE, 0xffffffff);
7306         tw32_f(cpu_base + CPU_PC, info.fw_base);
7307
7308         for (i = 0; i < 5; i++) {
7309                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7310                         break;
7311                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7312                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7313                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7314                 udelay(1000);
7315         }
7316         if (i >= 5) {
7317                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7318                        "to set CPU PC, is %08x should be %08x\n",
7319                        tp->dev->name, tr32(cpu_base + CPU_PC),
7320                        info.fw_base);
7321                 return -ENODEV;
7322         }
7323         tw32(cpu_base + CPU_STATE, 0xffffffff);
7324         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7325         return 0;
7326 }
7327
7328
7329 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7330 {
7331         struct tg3 *tp = netdev_priv(dev);
7332         struct sockaddr *addr = p;
7333         int err = 0, skip_mac_1 = 0;
7334
7335         if (!is_valid_ether_addr(addr->sa_data))
7336                 return -EINVAL;
7337
7338         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7339
7340         if (!netif_running(dev))
7341                 return 0;
7342
7343         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7344                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7345
7346                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7347                 addr0_low = tr32(MAC_ADDR_0_LOW);
7348                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7349                 addr1_low = tr32(MAC_ADDR_1_LOW);
7350
7351                 /* Skip MAC addr 1 if ASF is using it. */
7352                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7353                     !(addr1_high == 0 && addr1_low == 0))
7354                         skip_mac_1 = 1;
7355         }
7356         spin_lock_bh(&tp->lock);
7357         __tg3_set_mac_addr(tp, skip_mac_1);
7358         spin_unlock_bh(&tp->lock);
7359
7360         return err;
7361 }
7362
7363 /* tp->lock is held. */
7364 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7365                            dma_addr_t mapping, u32 maxlen_flags,
7366                            u32 nic_addr)
7367 {
7368         tg3_write_mem(tp,
7369                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7370                       ((u64) mapping >> 32));
7371         tg3_write_mem(tp,
7372                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7373                       ((u64) mapping & 0xffffffff));
7374         tg3_write_mem(tp,
7375                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7376                        maxlen_flags);
7377
7378         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7379                 tg3_write_mem(tp,
7380                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7381                               nic_addr);
7382 }
7383
7384 static void __tg3_set_rx_mode(struct net_device *);
7385 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7386 {
7387         int i;
7388
7389         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7390                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7391                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7392                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7393         } else {
7394                 tw32(HOSTCC_TXCOL_TICKS, 0);
7395                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7396                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7397         }
7398
7399         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7400                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7401                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7402                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7403         } else {
7404                 tw32(HOSTCC_RXCOL_TICKS, 0);
7405                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7406                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7407         }
7408
7409         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7410                 u32 val = ec->stats_block_coalesce_usecs;
7411
7412                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7413                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7414
7415                 if (!netif_carrier_ok(tp->dev))
7416                         val = 0;
7417
7418                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7419         }
7420
7421         for (i = 0; i < tp->irq_cnt - 1; i++) {
7422                 u32 reg;
7423
7424                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7425                 tw32(reg, ec->rx_coalesce_usecs);
7426                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7427                 tw32(reg, ec->rx_max_coalesced_frames);
7428                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7429                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7430
7431                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7432                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7433                         tw32(reg, ec->tx_coalesce_usecs);
7434                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7435                         tw32(reg, ec->tx_max_coalesced_frames);
7436                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7437                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7438                 }
7439         }
7440
7441         for (; i < tp->irq_max - 1; i++) {
7442                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7443                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7444                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7445
7446                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7447                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7448                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7449                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7450                 }
7451         }
7452 }
7453
7454 /* tp->lock is held. */
7455 static void tg3_rings_reset(struct tg3 *tp)
7456 {
7457         int i;
7458         u32 stblk, txrcb, rxrcb, limit;
7459         struct tg3_napi *tnapi = &tp->napi[0];
7460
7461         /* Disable all transmit rings but the first. */
7462         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7463                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7464         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7465                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7466         else
7467                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7468
7469         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7470              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7471                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7472                               BDINFO_FLAGS_DISABLED);
7473
7474
7475         /* Disable all receive return rings but the first. */
7476         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7477                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7478         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7479                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7480         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7481                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7482                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7483         else
7484                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7485
7486         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7487              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7488                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7489                               BDINFO_FLAGS_DISABLED);
7490
7491         /* Disable interrupts */
7492         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7493
7494         /* Zero mailbox registers. */
7495         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7496                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7497                         tp->napi[i].tx_prod = 0;
7498                         tp->napi[i].tx_cons = 0;
7499                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7500                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7501                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7502                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7503                 }
7504                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7505                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7506         } else {
7507                 tp->napi[0].tx_prod = 0;
7508                 tp->napi[0].tx_cons = 0;
7509                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7510                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7511         }
7512
7513         /* Make sure the NIC-based send BD rings are disabled. */
7514         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7515                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7516                 for (i = 0; i < 16; i++)
7517                         tw32_tx_mbox(mbox + i * 8, 0);
7518         }
7519
7520         txrcb = NIC_SRAM_SEND_RCB;
7521         rxrcb = NIC_SRAM_RCV_RET_RCB;
7522
7523         /* Clear status block in ram. */
7524         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7525
7526         /* Set status block DMA address */
7527         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7528              ((u64) tnapi->status_mapping >> 32));
7529         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7530              ((u64) tnapi->status_mapping & 0xffffffff));
7531
7532         if (tnapi->tx_ring) {
7533                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7534                                (TG3_TX_RING_SIZE <<
7535                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7536                                NIC_SRAM_TX_BUFFER_DESC);
7537                 txrcb += TG3_BDINFO_SIZE;
7538         }
7539
7540         if (tnapi->rx_rcb) {
7541                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7542                                (TG3_RX_RCB_RING_SIZE(tp) <<
7543                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7544                 rxrcb += TG3_BDINFO_SIZE;
7545         }
7546
7547         stblk = HOSTCC_STATBLCK_RING1;
7548
7549         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7550                 u64 mapping = (u64)tnapi->status_mapping;
7551                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7552                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7553
7554                 /* Clear status block in ram. */
7555                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7556
7557                 if (tnapi->tx_ring) {
7558                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7559                                        (TG3_TX_RING_SIZE <<
7560                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7561                                        NIC_SRAM_TX_BUFFER_DESC);
7562                         txrcb += TG3_BDINFO_SIZE;
7563                 }
7564
7565                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7566                                (TG3_RX_RCB_RING_SIZE(tp) <<
7567                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7568
7569                 stblk += 8;
7570                 rxrcb += TG3_BDINFO_SIZE;
7571         }
7572 }
7573
7574 /* tp->lock is held. */
7575 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7576 {
7577         u32 val, rdmac_mode;
7578         int i, err, limit;
7579         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7580
7581         tg3_disable_ints(tp);
7582
7583         tg3_stop_fw(tp);
7584
7585         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7586
7587         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7588                 tg3_abort_hw(tp, 1);
7589         }
7590
7591         if (reset_phy &&
7592             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7593                 tg3_phy_reset(tp);
7594
7595         err = tg3_chip_reset(tp);
7596         if (err)
7597                 return err;
7598
7599         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7600
7601         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7602                 val = tr32(TG3_CPMU_CTRL);
7603                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7604                 tw32(TG3_CPMU_CTRL, val);
7605
7606                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7607                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7608                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7609                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7610
7611                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7612                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7613                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7614                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7615
7616                 val = tr32(TG3_CPMU_HST_ACC);
7617                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7618                 val |= CPMU_HST_ACC_MACCLK_6_25;
7619                 tw32(TG3_CPMU_HST_ACC, val);
7620         }
7621
7622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7623                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7624                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7625                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7626                 tw32(PCIE_PWR_MGMT_THRESH, val);
7627
7628                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7629                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7630
7631                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7632
7633                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7634                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7635         }
7636
7637         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7638                 u32 grc_mode = tr32(GRC_MODE);
7639
7640                 /* Access the lower 1K of PL PCIE block registers. */
7641                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7642                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7643
7644                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7645                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7646                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7647
7648                 tw32(GRC_MODE, grc_mode);
7649         }
7650
7651         /* This works around an issue with Athlon chipsets on
7652          * B3 tigon3 silicon.  This bit has no effect on any
7653          * other revision.  But do not set this on PCI Express
7654          * chips and don't even touch the clocks if the CPMU is present.
7655          */
7656         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7657                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7658                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7659                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7660         }
7661
7662         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7663             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7664                 val = tr32(TG3PCI_PCISTATE);
7665                 val |= PCISTATE_RETRY_SAME_DMA;
7666                 tw32(TG3PCI_PCISTATE, val);
7667         }
7668
7669         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7670                 /* Allow reads and writes to the
7671                  * APE register and memory space.
7672                  */
7673                 val = tr32(TG3PCI_PCISTATE);
7674                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7675                        PCISTATE_ALLOW_APE_SHMEM_WR;
7676                 tw32(TG3PCI_PCISTATE, val);
7677         }
7678
7679         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7680                 /* Enable some hw fixes.  */
7681                 val = tr32(TG3PCI_MSI_DATA);
7682                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7683                 tw32(TG3PCI_MSI_DATA, val);
7684         }
7685
7686         /* Descriptor ring init may make accesses to the
7687          * NIC SRAM area to setup the TX descriptors, so we
7688          * can only do this after the hardware has been
7689          * successfully reset.
7690          */
7691         err = tg3_init_rings(tp);
7692         if (err)
7693                 return err;
7694
7695         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7696             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7697                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7698                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7699                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7700         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7701                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7702                 /* This value is determined during the probe time DMA
7703                  * engine test, tg3_test_dma.
7704                  */
7705                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7706         }
7707
7708         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7709                           GRC_MODE_4X_NIC_SEND_RINGS |
7710                           GRC_MODE_NO_TX_PHDR_CSUM |
7711                           GRC_MODE_NO_RX_PHDR_CSUM);
7712         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7713
7714         /* Pseudo-header checksum is done by hardware logic and not
7715          * the offload processers, so make the chip do the pseudo-
7716          * header checksums on receive.  For transmit it is more
7717          * convenient to do the pseudo-header checksum in software
7718          * as Linux does that on transmit for us in all cases.
7719          */
7720         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7721
7722         tw32(GRC_MODE,
7723              tp->grc_mode |
7724              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7725
7726         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7727         val = tr32(GRC_MISC_CFG);
7728         val &= ~0xff;
7729         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7730         tw32(GRC_MISC_CFG, val);
7731
7732         /* Initialize MBUF/DESC pool. */
7733         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7734                 /* Do nothing.  */
7735         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7736                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7737                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7738                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7739                 else
7740                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7741                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7742                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7743         }
7744         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7745                 int fw_len;
7746
7747                 fw_len = tp->fw_len;
7748                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7749                 tw32(BUFMGR_MB_POOL_ADDR,
7750                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7751                 tw32(BUFMGR_MB_POOL_SIZE,
7752                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7753         }
7754
7755         if (tp->dev->mtu <= ETH_DATA_LEN) {
7756                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7757                      tp->bufmgr_config.mbuf_read_dma_low_water);
7758                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7759                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7760                 tw32(BUFMGR_MB_HIGH_WATER,
7761                      tp->bufmgr_config.mbuf_high_water);
7762         } else {
7763                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7764                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7765                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7766                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7767                 tw32(BUFMGR_MB_HIGH_WATER,
7768                      tp->bufmgr_config.mbuf_high_water_jumbo);
7769         }
7770         tw32(BUFMGR_DMA_LOW_WATER,
7771              tp->bufmgr_config.dma_low_water);
7772         tw32(BUFMGR_DMA_HIGH_WATER,
7773              tp->bufmgr_config.dma_high_water);
7774
7775         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7776         for (i = 0; i < 2000; i++) {
7777                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7778                         break;
7779                 udelay(10);
7780         }
7781         if (i >= 2000) {
7782                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7783                        tp->dev->name);
7784                 return -ENODEV;
7785         }
7786
7787         /* Setup replenish threshold. */
7788         val = tp->rx_pending / 8;
7789         if (val == 0)
7790                 val = 1;
7791         else if (val > tp->rx_std_max_post)
7792                 val = tp->rx_std_max_post;
7793         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7794                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7795                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7796
7797                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7798                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7799         }
7800
7801         tw32(RCVBDI_STD_THRESH, val);
7802
7803         /* Initialize TG3_BDINFO's at:
7804          *  RCVDBDI_STD_BD:     standard eth size rx ring
7805          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7806          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7807          *
7808          * like so:
7809          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7810          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7811          *                              ring attribute flags
7812          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7813          *
7814          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7815          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7816          *
7817          * The size of each ring is fixed in the firmware, but the location is
7818          * configurable.
7819          */
7820         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7821              ((u64) tpr->rx_std_mapping >> 32));
7822         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7823              ((u64) tpr->rx_std_mapping & 0xffffffff));
7824         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7825                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7826                      NIC_SRAM_RX_BUFFER_DESC);
7827
7828         /* Disable the mini ring */
7829         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7830                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7831                      BDINFO_FLAGS_DISABLED);
7832
7833         /* Program the jumbo buffer descriptor ring control
7834          * blocks on those devices that have them.
7835          */
7836         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7837             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7838                 /* Setup replenish threshold. */
7839                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7840
7841                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7842                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7843                              ((u64) tpr->rx_jmb_mapping >> 32));
7844                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7845                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7846                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7847                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7848                              BDINFO_FLAGS_USE_EXT_RECV);
7849                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7850                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7851                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7852                 } else {
7853                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7854                              BDINFO_FLAGS_DISABLED);
7855                 }
7856
7857                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7858                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7859                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7860                               (RX_STD_MAX_SIZE << 2);
7861                 else
7862                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7863         } else
7864                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7865
7866         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7867
7868         tpr->rx_std_prod_idx = tp->rx_pending;
7869         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7870
7871         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7872                           tp->rx_jumbo_pending : 0;
7873         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7874
7875         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7876             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7877                 tw32(STD_REPLENISH_LWM, 32);
7878                 tw32(JMB_REPLENISH_LWM, 16);
7879         }
7880
7881         tg3_rings_reset(tp);
7882
7883         /* Initialize MAC address and backoff seed. */
7884         __tg3_set_mac_addr(tp, 0);
7885
7886         /* MTU + ethernet header + FCS + optional VLAN tag */
7887         tw32(MAC_RX_MTU_SIZE,
7888              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7889
7890         /* The slot time is changed by tg3_setup_phy if we
7891          * run at gigabit with half duplex.
7892          */
7893         tw32(MAC_TX_LENGTHS,
7894              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7895              (6 << TX_LENGTHS_IPG_SHIFT) |
7896              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7897
7898         /* Receive rules. */
7899         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7900         tw32(RCVLPC_CONFIG, 0x0181);
7901
7902         /* Calculate RDMAC_MODE setting early, we need it to determine
7903          * the RCVLPC_STATE_ENABLE mask.
7904          */
7905         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7906                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7907                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7908                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7909                       RDMAC_MODE_LNGREAD_ENAB);
7910
7911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7912             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7913             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7914                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7915                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7916                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7917
7918         /* If statement applies to 5705 and 5750 PCI devices only */
7919         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7920              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7921             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7922                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7923                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7924                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7925                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7926                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7927                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7928                 }
7929         }
7930
7931         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7932                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7933
7934         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7935                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7936
7937         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7938             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7940                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7941
7942         /* Receive/send statistics. */
7943         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7944                 val = tr32(RCVLPC_STATS_ENABLE);
7945                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7946                 tw32(RCVLPC_STATS_ENABLE, val);
7947         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7948                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7949                 val = tr32(RCVLPC_STATS_ENABLE);
7950                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7951                 tw32(RCVLPC_STATS_ENABLE, val);
7952         } else {
7953                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7954         }
7955         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7956         tw32(SNDDATAI_STATSENAB, 0xffffff);
7957         tw32(SNDDATAI_STATSCTRL,
7958              (SNDDATAI_SCTRL_ENABLE |
7959               SNDDATAI_SCTRL_FASTUPD));
7960
7961         /* Setup host coalescing engine. */
7962         tw32(HOSTCC_MODE, 0);
7963         for (i = 0; i < 2000; i++) {
7964                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7965                         break;
7966                 udelay(10);
7967         }
7968
7969         __tg3_set_coalesce(tp, &tp->coal);
7970
7971         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7972                 /* Status/statistics block address.  See tg3_timer,
7973                  * the tg3_periodic_fetch_stats call there, and
7974                  * tg3_get_stats to see how this works for 5705/5750 chips.
7975                  */
7976                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7977                      ((u64) tp->stats_mapping >> 32));
7978                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7979                      ((u64) tp->stats_mapping & 0xffffffff));
7980                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7981
7982                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7983
7984                 /* Clear statistics and status block memory areas */
7985                 for (i = NIC_SRAM_STATS_BLK;
7986                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7987                      i += sizeof(u32)) {
7988                         tg3_write_mem(tp, i, 0);
7989                         udelay(40);
7990                 }
7991         }
7992
7993         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7994
7995         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7996         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7997         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7998                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7999
8000         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8001                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8002                 /* reset to prevent losing 1st rx packet intermittently */
8003                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8004                 udelay(10);
8005         }
8006
8007         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8008                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8009         else
8010                 tp->mac_mode = 0;
8011         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8012                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8013         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8014             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8015             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8016                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8017         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8018         udelay(40);
8019
8020         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8021          * If TG3_FLG2_IS_NIC is zero, we should read the
8022          * register to preserve the GPIO settings for LOMs. The GPIOs,
8023          * whether used as inputs or outputs, are set by boot code after
8024          * reset.
8025          */
8026         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8027                 u32 gpio_mask;
8028
8029                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8030                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8031                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8032
8033                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8034                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8035                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8036
8037                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8038                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8039
8040                 tp->grc_local_ctrl &= ~gpio_mask;
8041                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8042
8043                 /* GPIO1 must be driven high for eeprom write protect */
8044                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8045                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8046                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8047         }
8048         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8049         udelay(100);
8050
8051         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8052                 val = tr32(MSGINT_MODE);
8053                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8054                 tw32(MSGINT_MODE, val);
8055         }
8056
8057         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8058                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8059                 udelay(40);
8060         }
8061
8062         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8063                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8064                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8065                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8066                WDMAC_MODE_LNGREAD_ENAB);
8067
8068         /* If statement applies to 5705 and 5750 PCI devices only */
8069         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8070              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8071             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8072                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8073                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8074                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8075                         /* nothing */
8076                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8077                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8078                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8079                         val |= WDMAC_MODE_RX_ACCEL;
8080                 }
8081         }
8082
8083         /* Enable host coalescing bug fix */
8084         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8085                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8086
8087         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8088                 val |= WDMAC_MODE_BURST_ALL_DATA;
8089
8090         tw32_f(WDMAC_MODE, val);
8091         udelay(40);
8092
8093         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8094                 u16 pcix_cmd;
8095
8096                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8097                                      &pcix_cmd);
8098                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8099                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8100                         pcix_cmd |= PCI_X_CMD_READ_2K;
8101                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8102                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8103                         pcix_cmd |= PCI_X_CMD_READ_2K;
8104                 }
8105                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8106                                       pcix_cmd);
8107         }
8108
8109         tw32_f(RDMAC_MODE, rdmac_mode);
8110         udelay(40);
8111
8112         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8113         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8114                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8115
8116         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8117                 tw32(SNDDATAC_MODE,
8118                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8119         else
8120                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8121
8122         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8123         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8124         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8125         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8126         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8127                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8128         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8129         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8130                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8131         tw32(SNDBDI_MODE, val);
8132         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8133
8134         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8135                 err = tg3_load_5701_a0_firmware_fix(tp);
8136                 if (err)
8137                         return err;
8138         }
8139
8140         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8141                 err = tg3_load_tso_firmware(tp);
8142                 if (err)
8143                         return err;
8144         }
8145
8146         tp->tx_mode = TX_MODE_ENABLE;
8147         tw32_f(MAC_TX_MODE, tp->tx_mode);
8148         udelay(100);
8149
8150         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8151                 u32 reg = MAC_RSS_INDIR_TBL_0;
8152                 u8 *ent = (u8 *)&val;
8153
8154                 /* Setup the indirection table */
8155                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8156                         int idx = i % sizeof(val);
8157
8158                         ent[idx] = i % (tp->irq_cnt - 1);
8159                         if (idx == sizeof(val) - 1) {
8160                                 tw32(reg, val);
8161                                 reg += 4;
8162                         }
8163                 }
8164
8165                 /* Setup the "secret" hash key. */
8166                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8167                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8168                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8169                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8170                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8171                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8172                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8173                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8174                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8175                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8176         }
8177
8178         tp->rx_mode = RX_MODE_ENABLE;
8179         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8180                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8181
8182         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8183                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8184                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8185                                RX_MODE_RSS_IPV6_HASH_EN |
8186                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8187                                RX_MODE_RSS_IPV4_HASH_EN |
8188                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8189
8190         tw32_f(MAC_RX_MODE, tp->rx_mode);
8191         udelay(10);
8192
8193         tw32(MAC_LED_CTRL, tp->led_ctrl);
8194
8195         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8196         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8197                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8198                 udelay(10);
8199         }
8200         tw32_f(MAC_RX_MODE, tp->rx_mode);
8201         udelay(10);
8202
8203         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8204                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8205                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8206                         /* Set drive transmission level to 1.2V  */
8207                         /* only if the signal pre-emphasis bit is not set  */
8208                         val = tr32(MAC_SERDES_CFG);
8209                         val &= 0xfffff000;
8210                         val |= 0x880;
8211                         tw32(MAC_SERDES_CFG, val);
8212                 }
8213                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8214                         tw32(MAC_SERDES_CFG, 0x616000);
8215         }
8216
8217         /* Prevent chip from dropping frames when flow control
8218          * is enabled.
8219          */
8220         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8221                 val = 1;
8222         else
8223                 val = 2;
8224         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8225
8226         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8227             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8228                 /* Use hardware link auto-negotiation */
8229                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8230         }
8231
8232         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8233             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8234                 u32 tmp;
8235
8236                 tmp = tr32(SERDES_RX_CTRL);
8237                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8238                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8239                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8240                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8241         }
8242
8243         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8244                 if (tp->link_config.phy_is_low_power) {
8245                         tp->link_config.phy_is_low_power = 0;
8246                         tp->link_config.speed = tp->link_config.orig_speed;
8247                         tp->link_config.duplex = tp->link_config.orig_duplex;
8248                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8249                 }
8250
8251                 err = tg3_setup_phy(tp, 0);
8252                 if (err)
8253                         return err;
8254
8255                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8256                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8257                         u32 tmp;
8258
8259                         /* Clear CRC stats. */
8260                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8261                                 tg3_writephy(tp, MII_TG3_TEST1,
8262                                              tmp | MII_TG3_TEST1_CRC_EN);
8263                                 tg3_readphy(tp, 0x14, &tmp);
8264                         }
8265                 }
8266         }
8267
8268         __tg3_set_rx_mode(tp->dev);
8269
8270         /* Initialize receive rules. */
8271         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8272         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8273         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8274         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8275
8276         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8277             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8278                 limit = 8;
8279         else
8280                 limit = 16;
8281         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8282                 limit -= 4;
8283         switch (limit) {
8284         case 16:
8285                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8286         case 15:
8287                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8288         case 14:
8289                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8290         case 13:
8291                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8292         case 12:
8293                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8294         case 11:
8295                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8296         case 10:
8297                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8298         case 9:
8299                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8300         case 8:
8301                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8302         case 7:
8303                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8304         case 6:
8305                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8306         case 5:
8307                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8308         case 4:
8309                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8310         case 3:
8311                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8312         case 2:
8313         case 1:
8314
8315         default:
8316                 break;
8317         }
8318
8319         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8320                 /* Write our heartbeat update interval to APE. */
8321                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8322                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8323
8324         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8325
8326         return 0;
8327 }
8328
8329 /* Called at device open time to get the chip ready for
8330  * packet processing.  Invoked with tp->lock held.
8331  */
8332 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8333 {
8334         tg3_switch_clocks(tp);
8335
8336         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8337
8338         return tg3_reset_hw(tp, reset_phy);
8339 }
8340
8341 #define TG3_STAT_ADD32(PSTAT, REG) \
8342 do {    u32 __val = tr32(REG); \
8343         (PSTAT)->low += __val; \
8344         if ((PSTAT)->low < __val) \
8345                 (PSTAT)->high += 1; \
8346 } while (0)
8347
8348 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8349 {
8350         struct tg3_hw_stats *sp = tp->hw_stats;
8351
8352         if (!netif_carrier_ok(tp->dev))
8353                 return;
8354
8355         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8356         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8357         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8358         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8359         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8360         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8361         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8362         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8363         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8364         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8365         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8366         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8367         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8368
8369         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8370         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8371         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8372         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8373         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8374         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8375         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8376         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8377         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8378         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8379         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8380         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8381         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8382         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8383
8384         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8385         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8386         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8387 }
8388
8389 static void tg3_timer(unsigned long __opaque)
8390 {
8391         struct tg3 *tp = (struct tg3 *) __opaque;
8392
8393         if (tp->irq_sync)
8394                 goto restart_timer;
8395
8396         spin_lock(&tp->lock);
8397
8398         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8399                 /* All of this garbage is because when using non-tagged
8400                  * IRQ status the mailbox/status_block protocol the chip
8401                  * uses with the cpu is race prone.
8402                  */
8403                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8404                         tw32(GRC_LOCAL_CTRL,
8405                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8406                 } else {
8407                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8408                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8409                 }
8410
8411                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8412                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8413                         spin_unlock(&tp->lock);
8414                         schedule_work(&tp->reset_task);
8415                         return;
8416                 }
8417         }
8418
8419         /* This part only runs once per second. */
8420         if (!--tp->timer_counter) {
8421                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8422                         tg3_periodic_fetch_stats(tp);
8423
8424                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8425                         u32 mac_stat;
8426                         int phy_event;
8427
8428                         mac_stat = tr32(MAC_STATUS);
8429
8430                         phy_event = 0;
8431                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8432                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8433                                         phy_event = 1;
8434                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8435                                 phy_event = 1;
8436
8437                         if (phy_event)
8438                                 tg3_setup_phy(tp, 0);
8439                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8440                         u32 mac_stat = tr32(MAC_STATUS);
8441                         int need_setup = 0;
8442
8443                         if (netif_carrier_ok(tp->dev) &&
8444                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8445                                 need_setup = 1;
8446                         }
8447                         if (! netif_carrier_ok(tp->dev) &&
8448                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8449                                          MAC_STATUS_SIGNAL_DET))) {
8450                                 need_setup = 1;
8451                         }
8452                         if (need_setup) {
8453                                 if (!tp->serdes_counter) {
8454                                         tw32_f(MAC_MODE,
8455                                              (tp->mac_mode &
8456                                               ~MAC_MODE_PORT_MODE_MASK));
8457                                         udelay(40);
8458                                         tw32_f(MAC_MODE, tp->mac_mode);
8459                                         udelay(40);
8460                                 }
8461                                 tg3_setup_phy(tp, 0);
8462                         }
8463                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8464                         tg3_serdes_parallel_detect(tp);
8465
8466                 tp->timer_counter = tp->timer_multiplier;
8467         }
8468
8469         /* Heartbeat is only sent once every 2 seconds.
8470          *
8471          * The heartbeat is to tell the ASF firmware that the host
8472          * driver is still alive.  In the event that the OS crashes,
8473          * ASF needs to reset the hardware to free up the FIFO space
8474          * that may be filled with rx packets destined for the host.
8475          * If the FIFO is full, ASF will no longer function properly.
8476          *
8477          * Unintended resets have been reported on real time kernels
8478          * where the timer doesn't run on time.  Netpoll will also have
8479          * same problem.
8480          *
8481          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8482          * to check the ring condition when the heartbeat is expiring
8483          * before doing the reset.  This will prevent most unintended
8484          * resets.
8485          */
8486         if (!--tp->asf_counter) {
8487                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8488                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8489                         tg3_wait_for_event_ack(tp);
8490
8491                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8492                                       FWCMD_NICDRV_ALIVE3);
8493                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8494                         /* 5 seconds timeout */
8495                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8496
8497                         tg3_generate_fw_event(tp);
8498                 }
8499                 tp->asf_counter = tp->asf_multiplier;
8500         }
8501
8502         spin_unlock(&tp->lock);
8503
8504 restart_timer:
8505         tp->timer.expires = jiffies + tp->timer_offset;
8506         add_timer(&tp->timer);
8507 }
8508
8509 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8510 {
8511         irq_handler_t fn;
8512         unsigned long flags;
8513         char *name;
8514         struct tg3_napi *tnapi = &tp->napi[irq_num];
8515
8516         if (tp->irq_cnt == 1)
8517                 name = tp->dev->name;
8518         else {
8519                 name = &tnapi->irq_lbl[0];
8520                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8521                 name[IFNAMSIZ-1] = 0;
8522         }
8523
8524         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8525                 fn = tg3_msi;
8526                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8527                         fn = tg3_msi_1shot;
8528                 flags = IRQF_SAMPLE_RANDOM;
8529         } else {
8530                 fn = tg3_interrupt;
8531                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8532                         fn = tg3_interrupt_tagged;
8533                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8534         }
8535
8536         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8537 }
8538
8539 static int tg3_test_interrupt(struct tg3 *tp)
8540 {
8541         struct tg3_napi *tnapi = &tp->napi[0];
8542         struct net_device *dev = tp->dev;
8543         int err, i, intr_ok = 0;
8544         u32 val;
8545
8546         if (!netif_running(dev))
8547                 return -ENODEV;
8548
8549         tg3_disable_ints(tp);
8550
8551         free_irq(tnapi->irq_vec, tnapi);
8552
8553         /*
8554          * Turn off MSI one shot mode.  Otherwise this test has no
8555          * observable way to know whether the interrupt was delivered.
8556          */
8557         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8558              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8559             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8560                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8561                 tw32(MSGINT_MODE, val);
8562         }
8563
8564         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8565                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8566         if (err)
8567                 return err;
8568
8569         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8570         tg3_enable_ints(tp);
8571
8572         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8573                tnapi->coal_now);
8574
8575         for (i = 0; i < 5; i++) {
8576                 u32 int_mbox, misc_host_ctrl;
8577
8578                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8579                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8580
8581                 if ((int_mbox != 0) ||
8582                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8583                         intr_ok = 1;
8584                         break;
8585                 }
8586
8587                 msleep(10);
8588         }
8589
8590         tg3_disable_ints(tp);
8591
8592         free_irq(tnapi->irq_vec, tnapi);
8593
8594         err = tg3_request_irq(tp, 0);
8595
8596         if (err)
8597                 return err;
8598
8599         if (intr_ok) {
8600                 /* Reenable MSI one shot mode. */
8601                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8602                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8603                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8604                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8605                         tw32(MSGINT_MODE, val);
8606                 }
8607                 return 0;
8608         }
8609
8610         return -EIO;
8611 }
8612
8613 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8614  * successfully restored
8615  */
8616 static int tg3_test_msi(struct tg3 *tp)
8617 {
8618         int err;
8619         u16 pci_cmd;
8620
8621         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8622                 return 0;
8623
8624         /* Turn off SERR reporting in case MSI terminates with Master
8625          * Abort.
8626          */
8627         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8628         pci_write_config_word(tp->pdev, PCI_COMMAND,
8629                               pci_cmd & ~PCI_COMMAND_SERR);
8630
8631         err = tg3_test_interrupt(tp);
8632
8633         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8634
8635         if (!err)
8636                 return 0;
8637
8638         /* other failures */
8639         if (err != -EIO)
8640                 return err;
8641
8642         /* MSI test failed, go back to INTx mode */
8643         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8644                "switching to INTx mode. Please report this failure to "
8645                "the PCI maintainer and include system chipset information.\n",
8646                        tp->dev->name);
8647
8648         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8649
8650         pci_disable_msi(tp->pdev);
8651
8652         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8653
8654         err = tg3_request_irq(tp, 0);
8655         if (err)
8656                 return err;
8657
8658         /* Need to reset the chip because the MSI cycle may have terminated
8659          * with Master Abort.
8660          */
8661         tg3_full_lock(tp, 1);
8662
8663         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8664         err = tg3_init_hw(tp, 1);
8665
8666         tg3_full_unlock(tp);
8667
8668         if (err)
8669                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8670
8671         return err;
8672 }
8673
8674 static int tg3_request_firmware(struct tg3 *tp)
8675 {
8676         const __be32 *fw_data;
8677
8678         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8679                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8680                        tp->dev->name, tp->fw_needed);
8681                 return -ENOENT;
8682         }
8683
8684         fw_data = (void *)tp->fw->data;
8685
8686         /* Firmware blob starts with version numbers, followed by
8687          * start address and _full_ length including BSS sections
8688          * (which must be longer than the actual data, of course
8689          */
8690
8691         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8692         if (tp->fw_len < (tp->fw->size - 12)) {
8693                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8694                        tp->dev->name, tp->fw_len, tp->fw_needed);
8695                 release_firmware(tp->fw);
8696                 tp->fw = NULL;
8697                 return -EINVAL;
8698         }
8699
8700         /* We no longer need firmware; we have it. */
8701         tp->fw_needed = NULL;
8702         return 0;
8703 }
8704
8705 static bool tg3_enable_msix(struct tg3 *tp)
8706 {
8707         int i, rc, cpus = num_online_cpus();
8708         struct msix_entry msix_ent[tp->irq_max];
8709
8710         if (cpus == 1)
8711                 /* Just fallback to the simpler MSI mode. */
8712                 return false;
8713
8714         /*
8715          * We want as many rx rings enabled as there are cpus.
8716          * The first MSIX vector only deals with link interrupts, etc,
8717          * so we add one to the number of vectors we are requesting.
8718          */
8719         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8720
8721         for (i = 0; i < tp->irq_max; i++) {
8722                 msix_ent[i].entry  = i;
8723                 msix_ent[i].vector = 0;
8724         }
8725
8726         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8727         if (rc != 0) {
8728                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8729                         return false;
8730                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8731                         return false;
8732                 printk(KERN_NOTICE
8733                        "%s: Requested %d MSI-X vectors, received %d\n",
8734                        tp->dev->name, tp->irq_cnt, rc);
8735                 tp->irq_cnt = rc;
8736         }
8737
8738         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8739
8740         for (i = 0; i < tp->irq_max; i++)
8741                 tp->napi[i].irq_vec = msix_ent[i].vector;
8742
8743         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8744                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8745                 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8746         } else
8747                 tp->dev->real_num_tx_queues = 1;
8748
8749         return true;
8750 }
8751
8752 static void tg3_ints_init(struct tg3 *tp)
8753 {
8754         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8755             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8756                 /* All MSI supporting chips should support tagged
8757                  * status.  Assert that this is the case.
8758                  */
8759                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8760                        "Not using MSI.\n", tp->dev->name);
8761                 goto defcfg;
8762         }
8763
8764         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8765                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8766         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8767                  pci_enable_msi(tp->pdev) == 0)
8768                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8769
8770         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8771                 u32 msi_mode = tr32(MSGINT_MODE);
8772                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8773                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8774                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8775         }
8776 defcfg:
8777         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8778                 tp->irq_cnt = 1;
8779                 tp->napi[0].irq_vec = tp->pdev->irq;
8780                 tp->dev->real_num_tx_queues = 1;
8781         }
8782 }
8783
8784 static void tg3_ints_fini(struct tg3 *tp)
8785 {
8786         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8787                 pci_disable_msix(tp->pdev);
8788         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8789                 pci_disable_msi(tp->pdev);
8790         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8791         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8792 }
8793
8794 static int tg3_open(struct net_device *dev)
8795 {
8796         struct tg3 *tp = netdev_priv(dev);
8797         int i, err;
8798
8799         if (tp->fw_needed) {
8800                 err = tg3_request_firmware(tp);
8801                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8802                         if (err)
8803                                 return err;
8804                 } else if (err) {
8805                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8806                                tp->dev->name);
8807                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8808                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8809                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8810                                tp->dev->name);
8811                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8812                 }
8813         }
8814
8815         netif_carrier_off(tp->dev);
8816
8817         err = tg3_set_power_state(tp, PCI_D0);
8818         if (err)
8819                 return err;
8820
8821         tg3_full_lock(tp, 0);
8822
8823         tg3_disable_ints(tp);
8824         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8825
8826         tg3_full_unlock(tp);
8827
8828         /*
8829          * Setup interrupts first so we know how
8830          * many NAPI resources to allocate
8831          */
8832         tg3_ints_init(tp);
8833
8834         /* The placement of this call is tied
8835          * to the setup and use of Host TX descriptors.
8836          */
8837         err = tg3_alloc_consistent(tp);
8838         if (err)
8839                 goto err_out1;
8840
8841         tg3_napi_enable(tp);
8842
8843         for (i = 0; i < tp->irq_cnt; i++) {
8844                 struct tg3_napi *tnapi = &tp->napi[i];
8845                 err = tg3_request_irq(tp, i);
8846                 if (err) {
8847                         for (i--; i >= 0; i--)
8848                                 free_irq(tnapi->irq_vec, tnapi);
8849                         break;
8850                 }
8851         }
8852
8853         if (err)
8854                 goto err_out2;
8855
8856         tg3_full_lock(tp, 0);
8857
8858         err = tg3_init_hw(tp, 1);
8859         if (err) {
8860                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8861                 tg3_free_rings(tp);
8862         } else {
8863                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8864                         tp->timer_offset = HZ;
8865                 else
8866                         tp->timer_offset = HZ / 10;
8867
8868                 BUG_ON(tp->timer_offset > HZ);
8869                 tp->timer_counter = tp->timer_multiplier =
8870                         (HZ / tp->timer_offset);
8871                 tp->asf_counter = tp->asf_multiplier =
8872                         ((HZ / tp->timer_offset) * 2);
8873
8874                 init_timer(&tp->timer);
8875                 tp->timer.expires = jiffies + tp->timer_offset;
8876                 tp->timer.data = (unsigned long) tp;
8877                 tp->timer.function = tg3_timer;
8878         }
8879
8880         tg3_full_unlock(tp);
8881
8882         if (err)
8883                 goto err_out3;
8884
8885         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8886                 err = tg3_test_msi(tp);
8887
8888                 if (err) {
8889                         tg3_full_lock(tp, 0);
8890                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8891                         tg3_free_rings(tp);
8892                         tg3_full_unlock(tp);
8893
8894                         goto err_out2;
8895                 }
8896
8897                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8898                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8899                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8900                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8901                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8902
8903                         tw32(PCIE_TRANSACTION_CFG,
8904                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8905                 }
8906         }
8907
8908         tg3_phy_start(tp);
8909
8910         tg3_full_lock(tp, 0);
8911
8912         add_timer(&tp->timer);
8913         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8914         tg3_enable_ints(tp);
8915
8916         tg3_full_unlock(tp);
8917
8918         netif_tx_start_all_queues(dev);
8919
8920         return 0;
8921
8922 err_out3:
8923         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8924                 struct tg3_napi *tnapi = &tp->napi[i];
8925                 free_irq(tnapi->irq_vec, tnapi);
8926         }
8927
8928 err_out2:
8929         tg3_napi_disable(tp);
8930         tg3_free_consistent(tp);
8931
8932 err_out1:
8933         tg3_ints_fini(tp);
8934         return err;
8935 }
8936
8937 #if 0
8938 /*static*/ void tg3_dump_state(struct tg3 *tp)
8939 {
8940         u32 val32, val32_2, val32_3, val32_4, val32_5;
8941         u16 val16;
8942         int i;
8943         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8944
8945         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8946         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8947         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8948                val16, val32);
8949
8950         /* MAC block */
8951         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8952                tr32(MAC_MODE), tr32(MAC_STATUS));
8953         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8954                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8955         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8956                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8957         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8958                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8959
8960         /* Send data initiator control block */
8961         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8962                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8963         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8964                tr32(SNDDATAI_STATSCTRL));
8965
8966         /* Send data completion control block */
8967         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8968
8969         /* Send BD ring selector block */
8970         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8971                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8972
8973         /* Send BD initiator control block */
8974         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8975                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8976
8977         /* Send BD completion control block */
8978         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8979
8980         /* Receive list placement control block */
8981         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8982                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8983         printk("       RCVLPC_STATSCTRL[%08x]\n",
8984                tr32(RCVLPC_STATSCTRL));
8985
8986         /* Receive data and receive BD initiator control block */
8987         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8988                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8989
8990         /* Receive data completion control block */
8991         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8992                tr32(RCVDCC_MODE));
8993
8994         /* Receive BD initiator control block */
8995         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8996                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8997
8998         /* Receive BD completion control block */
8999         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
9000                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
9001
9002         /* Receive list selector control block */
9003         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
9004                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
9005
9006         /* Mbuf cluster free block */
9007         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
9008                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
9009
9010         /* Host coalescing control block */
9011         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
9012                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
9013         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
9014                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9015                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9016         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
9017                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9018                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9019         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9020                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9021         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9022                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9023
9024         /* Memory arbiter control block */
9025         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9026                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9027
9028         /* Buffer manager control block */
9029         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9030                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9031         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9032                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9033         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9034                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9035                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9036                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9037
9038         /* Read DMA control block */
9039         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9040                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9041
9042         /* Write DMA control block */
9043         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9044                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9045
9046         /* DMA completion block */
9047         printk("DEBUG: DMAC_MODE[%08x]\n",
9048                tr32(DMAC_MODE));
9049
9050         /* GRC block */
9051         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9052                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9053         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9054                tr32(GRC_LOCAL_CTRL));
9055
9056         /* TG3_BDINFOs */
9057         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9058                tr32(RCVDBDI_JUMBO_BD + 0x0),
9059                tr32(RCVDBDI_JUMBO_BD + 0x4),
9060                tr32(RCVDBDI_JUMBO_BD + 0x8),
9061                tr32(RCVDBDI_JUMBO_BD + 0xc));
9062         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9063                tr32(RCVDBDI_STD_BD + 0x0),
9064                tr32(RCVDBDI_STD_BD + 0x4),
9065                tr32(RCVDBDI_STD_BD + 0x8),
9066                tr32(RCVDBDI_STD_BD + 0xc));
9067         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9068                tr32(RCVDBDI_MINI_BD + 0x0),
9069                tr32(RCVDBDI_MINI_BD + 0x4),
9070                tr32(RCVDBDI_MINI_BD + 0x8),
9071                tr32(RCVDBDI_MINI_BD + 0xc));
9072
9073         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9074         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9075         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9076         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9077         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9078                val32, val32_2, val32_3, val32_4);
9079
9080         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9081         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9082         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9083         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9084         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9085                val32, val32_2, val32_3, val32_4);
9086
9087         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9088         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9089         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9090         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9091         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9092         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9093                val32, val32_2, val32_3, val32_4, val32_5);
9094
9095         /* SW status block */
9096         printk(KERN_DEBUG
9097          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9098                sblk->status,
9099                sblk->status_tag,
9100                sblk->rx_jumbo_consumer,
9101                sblk->rx_consumer,
9102                sblk->rx_mini_consumer,
9103                sblk->idx[0].rx_producer,
9104                sblk->idx[0].tx_consumer);
9105
9106         /* SW statistics block */
9107         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9108                ((u32 *)tp->hw_stats)[0],
9109                ((u32 *)tp->hw_stats)[1],
9110                ((u32 *)tp->hw_stats)[2],
9111                ((u32 *)tp->hw_stats)[3]);
9112
9113         /* Mailboxes */
9114         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9115                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9116                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9117                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9118                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9119
9120         /* NIC side send descriptors. */
9121         for (i = 0; i < 6; i++) {
9122                 unsigned long txd;
9123
9124                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9125                         + (i * sizeof(struct tg3_tx_buffer_desc));
9126                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9127                        i,
9128                        readl(txd + 0x0), readl(txd + 0x4),
9129                        readl(txd + 0x8), readl(txd + 0xc));
9130         }
9131
9132         /* NIC side RX descriptors. */
9133         for (i = 0; i < 6; i++) {
9134                 unsigned long rxd;
9135
9136                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9137                         + (i * sizeof(struct tg3_rx_buffer_desc));
9138                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9139                        i,
9140                        readl(rxd + 0x0), readl(rxd + 0x4),
9141                        readl(rxd + 0x8), readl(rxd + 0xc));
9142                 rxd += (4 * sizeof(u32));
9143                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9144                        i,
9145                        readl(rxd + 0x0), readl(rxd + 0x4),
9146                        readl(rxd + 0x8), readl(rxd + 0xc));
9147         }
9148
9149         for (i = 0; i < 6; i++) {
9150                 unsigned long rxd;
9151
9152                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9153                         + (i * sizeof(struct tg3_rx_buffer_desc));
9154                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9155                        i,
9156                        readl(rxd + 0x0), readl(rxd + 0x4),
9157                        readl(rxd + 0x8), readl(rxd + 0xc));
9158                 rxd += (4 * sizeof(u32));
9159                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9160                        i,
9161                        readl(rxd + 0x0), readl(rxd + 0x4),
9162                        readl(rxd + 0x8), readl(rxd + 0xc));
9163         }
9164 }
9165 #endif
9166
9167 static struct net_device_stats *tg3_get_stats(struct net_device *);
9168 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9169
9170 static int tg3_close(struct net_device *dev)
9171 {
9172         int i;
9173         struct tg3 *tp = netdev_priv(dev);
9174
9175         tg3_napi_disable(tp);
9176         cancel_work_sync(&tp->reset_task);
9177
9178         netif_tx_stop_all_queues(dev);
9179
9180         del_timer_sync(&tp->timer);
9181
9182         tg3_phy_stop(tp);
9183
9184         tg3_full_lock(tp, 1);
9185 #if 0
9186         tg3_dump_state(tp);
9187 #endif
9188
9189         tg3_disable_ints(tp);
9190
9191         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9192         tg3_free_rings(tp);
9193         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9194
9195         tg3_full_unlock(tp);
9196
9197         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9198                 struct tg3_napi *tnapi = &tp->napi[i];
9199                 free_irq(tnapi->irq_vec, tnapi);
9200         }
9201
9202         tg3_ints_fini(tp);
9203
9204         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9205                sizeof(tp->net_stats_prev));
9206         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9207                sizeof(tp->estats_prev));
9208
9209         tg3_free_consistent(tp);
9210
9211         tg3_set_power_state(tp, PCI_D3hot);
9212
9213         netif_carrier_off(tp->dev);
9214
9215         return 0;
9216 }
9217
9218 static inline unsigned long get_stat64(tg3_stat64_t *val)
9219 {
9220         unsigned long ret;
9221
9222 #if (BITS_PER_LONG == 32)
9223         ret = val->low;
9224 #else
9225         ret = ((u64)val->high << 32) | ((u64)val->low);
9226 #endif
9227         return ret;
9228 }
9229
9230 static inline u64 get_estat64(tg3_stat64_t *val)
9231 {
9232        return ((u64)val->high << 32) | ((u64)val->low);
9233 }
9234
9235 static unsigned long calc_crc_errors(struct tg3 *tp)
9236 {
9237         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9238
9239         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9240             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9241              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9242                 u32 val;
9243
9244                 spin_lock_bh(&tp->lock);
9245                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9246                         tg3_writephy(tp, MII_TG3_TEST1,
9247                                      val | MII_TG3_TEST1_CRC_EN);
9248                         tg3_readphy(tp, 0x14, &val);
9249                 } else
9250                         val = 0;
9251                 spin_unlock_bh(&tp->lock);
9252
9253                 tp->phy_crc_errors += val;
9254
9255                 return tp->phy_crc_errors;
9256         }
9257
9258         return get_stat64(&hw_stats->rx_fcs_errors);
9259 }
9260
9261 #define ESTAT_ADD(member) \
9262         estats->member =        old_estats->member + \
9263                                 get_estat64(&hw_stats->member)
9264
9265 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9266 {
9267         struct tg3_ethtool_stats *estats = &tp->estats;
9268         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9269         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9270
9271         if (!hw_stats)
9272                 return old_estats;
9273
9274         ESTAT_ADD(rx_octets);
9275         ESTAT_ADD(rx_fragments);
9276         ESTAT_ADD(rx_ucast_packets);
9277         ESTAT_ADD(rx_mcast_packets);
9278         ESTAT_ADD(rx_bcast_packets);
9279         ESTAT_ADD(rx_fcs_errors);
9280         ESTAT_ADD(rx_align_errors);
9281         ESTAT_ADD(rx_xon_pause_rcvd);
9282         ESTAT_ADD(rx_xoff_pause_rcvd);
9283         ESTAT_ADD(rx_mac_ctrl_rcvd);
9284         ESTAT_ADD(rx_xoff_entered);
9285         ESTAT_ADD(rx_frame_too_long_errors);
9286         ESTAT_ADD(rx_jabbers);
9287         ESTAT_ADD(rx_undersize_packets);
9288         ESTAT_ADD(rx_in_length_errors);
9289         ESTAT_ADD(rx_out_length_errors);
9290         ESTAT_ADD(rx_64_or_less_octet_packets);
9291         ESTAT_ADD(rx_65_to_127_octet_packets);
9292         ESTAT_ADD(rx_128_to_255_octet_packets);
9293         ESTAT_ADD(rx_256_to_511_octet_packets);
9294         ESTAT_ADD(rx_512_to_1023_octet_packets);
9295         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9296         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9297         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9298         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9299         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9300
9301         ESTAT_ADD(tx_octets);
9302         ESTAT_ADD(tx_collisions);
9303         ESTAT_ADD(tx_xon_sent);
9304         ESTAT_ADD(tx_xoff_sent);
9305         ESTAT_ADD(tx_flow_control);
9306         ESTAT_ADD(tx_mac_errors);
9307         ESTAT_ADD(tx_single_collisions);
9308         ESTAT_ADD(tx_mult_collisions);
9309         ESTAT_ADD(tx_deferred);
9310         ESTAT_ADD(tx_excessive_collisions);
9311         ESTAT_ADD(tx_late_collisions);
9312         ESTAT_ADD(tx_collide_2times);
9313         ESTAT_ADD(tx_collide_3times);
9314         ESTAT_ADD(tx_collide_4times);
9315         ESTAT_ADD(tx_collide_5times);
9316         ESTAT_ADD(tx_collide_6times);
9317         ESTAT_ADD(tx_collide_7times);
9318         ESTAT_ADD(tx_collide_8times);
9319         ESTAT_ADD(tx_collide_9times);
9320         ESTAT_ADD(tx_collide_10times);
9321         ESTAT_ADD(tx_collide_11times);
9322         ESTAT_ADD(tx_collide_12times);
9323         ESTAT_ADD(tx_collide_13times);
9324         ESTAT_ADD(tx_collide_14times);
9325         ESTAT_ADD(tx_collide_15times);
9326         ESTAT_ADD(tx_ucast_packets);
9327         ESTAT_ADD(tx_mcast_packets);
9328         ESTAT_ADD(tx_bcast_packets);
9329         ESTAT_ADD(tx_carrier_sense_errors);
9330         ESTAT_ADD(tx_discards);
9331         ESTAT_ADD(tx_errors);
9332
9333         ESTAT_ADD(dma_writeq_full);
9334         ESTAT_ADD(dma_write_prioq_full);
9335         ESTAT_ADD(rxbds_empty);
9336         ESTAT_ADD(rx_discards);
9337         ESTAT_ADD(rx_errors);
9338         ESTAT_ADD(rx_threshold_hit);
9339
9340         ESTAT_ADD(dma_readq_full);
9341         ESTAT_ADD(dma_read_prioq_full);
9342         ESTAT_ADD(tx_comp_queue_full);
9343
9344         ESTAT_ADD(ring_set_send_prod_index);
9345         ESTAT_ADD(ring_status_update);
9346         ESTAT_ADD(nic_irqs);
9347         ESTAT_ADD(nic_avoided_irqs);
9348         ESTAT_ADD(nic_tx_threshold_hit);
9349
9350         return estats;
9351 }
9352
9353 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9354 {
9355         struct tg3 *tp = netdev_priv(dev);
9356         struct net_device_stats *stats = &tp->net_stats;
9357         struct net_device_stats *old_stats = &tp->net_stats_prev;
9358         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9359
9360         if (!hw_stats)
9361                 return old_stats;
9362
9363         stats->rx_packets = old_stats->rx_packets +
9364                 get_stat64(&hw_stats->rx_ucast_packets) +
9365                 get_stat64(&hw_stats->rx_mcast_packets) +
9366                 get_stat64(&hw_stats->rx_bcast_packets);
9367
9368         stats->tx_packets = old_stats->tx_packets +
9369                 get_stat64(&hw_stats->tx_ucast_packets) +
9370                 get_stat64(&hw_stats->tx_mcast_packets) +
9371                 get_stat64(&hw_stats->tx_bcast_packets);
9372
9373         stats->rx_bytes = old_stats->rx_bytes +
9374                 get_stat64(&hw_stats->rx_octets);
9375         stats->tx_bytes = old_stats->tx_bytes +
9376                 get_stat64(&hw_stats->tx_octets);
9377
9378         stats->rx_errors = old_stats->rx_errors +
9379                 get_stat64(&hw_stats->rx_errors);
9380         stats->tx_errors = old_stats->tx_errors +
9381                 get_stat64(&hw_stats->tx_errors) +
9382                 get_stat64(&hw_stats->tx_mac_errors) +
9383                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9384                 get_stat64(&hw_stats->tx_discards);
9385
9386         stats->multicast = old_stats->multicast +
9387                 get_stat64(&hw_stats->rx_mcast_packets);
9388         stats->collisions = old_stats->collisions +
9389                 get_stat64(&hw_stats->tx_collisions);
9390
9391         stats->rx_length_errors = old_stats->rx_length_errors +
9392                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9393                 get_stat64(&hw_stats->rx_undersize_packets);
9394
9395         stats->rx_over_errors = old_stats->rx_over_errors +
9396                 get_stat64(&hw_stats->rxbds_empty);
9397         stats->rx_frame_errors = old_stats->rx_frame_errors +
9398                 get_stat64(&hw_stats->rx_align_errors);
9399         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9400                 get_stat64(&hw_stats->tx_discards);
9401         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9402                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9403
9404         stats->rx_crc_errors = old_stats->rx_crc_errors +
9405                 calc_crc_errors(tp);
9406
9407         stats->rx_missed_errors = old_stats->rx_missed_errors +
9408                 get_stat64(&hw_stats->rx_discards);
9409
9410         return stats;
9411 }
9412
9413 static inline u32 calc_crc(unsigned char *buf, int len)
9414 {
9415         u32 reg;
9416         u32 tmp;
9417         int j, k;
9418
9419         reg = 0xffffffff;
9420
9421         for (j = 0; j < len; j++) {
9422                 reg ^= buf[j];
9423
9424                 for (k = 0; k < 8; k++) {
9425                         tmp = reg & 0x01;
9426
9427                         reg >>= 1;
9428
9429                         if (tmp) {
9430                                 reg ^= 0xedb88320;
9431                         }
9432                 }
9433         }
9434
9435         return ~reg;
9436 }
9437
9438 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9439 {
9440         /* accept or reject all multicast frames */
9441         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9442         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9443         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9444         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9445 }
9446
9447 static void __tg3_set_rx_mode(struct net_device *dev)
9448 {
9449         struct tg3 *tp = netdev_priv(dev);
9450         u32 rx_mode;
9451
9452         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9453                                   RX_MODE_KEEP_VLAN_TAG);
9454
9455         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9456          * flag clear.
9457          */
9458 #if TG3_VLAN_TAG_USED
9459         if (!tp->vlgrp &&
9460             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9461                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9462 #else
9463         /* By definition, VLAN is disabled always in this
9464          * case.
9465          */
9466         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9467                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9468 #endif
9469
9470         if (dev->flags & IFF_PROMISC) {
9471                 /* Promiscuous mode. */
9472                 rx_mode |= RX_MODE_PROMISC;
9473         } else if (dev->flags & IFF_ALLMULTI) {
9474                 /* Accept all multicast. */
9475                 tg3_set_multi (tp, 1);
9476         } else if (netdev_mc_empty(dev)) {
9477                 /* Reject all multicast. */
9478                 tg3_set_multi (tp, 0);
9479         } else {
9480                 /* Accept one or more multicast(s). */
9481                 struct dev_mc_list *mclist;
9482                 unsigned int i;
9483                 u32 mc_filter[4] = { 0, };
9484                 u32 regidx;
9485                 u32 bit;
9486                 u32 crc;
9487
9488                 for (i = 0, mclist = dev->mc_list; mclist && i < netdev_mc_count(dev);
9489                      i++, mclist = mclist->next) {
9490
9491                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9492                         bit = ~crc & 0x7f;
9493                         regidx = (bit & 0x60) >> 5;
9494                         bit &= 0x1f;
9495                         mc_filter[regidx] |= (1 << bit);
9496                 }
9497
9498                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9499                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9500                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9501                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9502         }
9503
9504         if (rx_mode != tp->rx_mode) {
9505                 tp->rx_mode = rx_mode;
9506                 tw32_f(MAC_RX_MODE, rx_mode);
9507                 udelay(10);
9508         }
9509 }
9510
9511 static void tg3_set_rx_mode(struct net_device *dev)
9512 {
9513         struct tg3 *tp = netdev_priv(dev);
9514
9515         if (!netif_running(dev))
9516                 return;
9517
9518         tg3_full_lock(tp, 0);
9519         __tg3_set_rx_mode(dev);
9520         tg3_full_unlock(tp);
9521 }
9522
9523 #define TG3_REGDUMP_LEN         (32 * 1024)
9524
9525 static int tg3_get_regs_len(struct net_device *dev)
9526 {
9527         return TG3_REGDUMP_LEN;
9528 }
9529
9530 static void tg3_get_regs(struct net_device *dev,
9531                 struct ethtool_regs *regs, void *_p)
9532 {
9533         u32 *p = _p;
9534         struct tg3 *tp = netdev_priv(dev);
9535         u8 *orig_p = _p;
9536         int i;
9537
9538         regs->version = 0;
9539
9540         memset(p, 0, TG3_REGDUMP_LEN);
9541
9542         if (tp->link_config.phy_is_low_power)
9543                 return;
9544
9545         tg3_full_lock(tp, 0);
9546
9547 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9548 #define GET_REG32_LOOP(base,len)                \
9549 do {    p = (u32 *)(orig_p + (base));           \
9550         for (i = 0; i < len; i += 4)            \
9551                 __GET_REG32((base) + i);        \
9552 } while (0)
9553 #define GET_REG32_1(reg)                        \
9554 do {    p = (u32 *)(orig_p + (reg));            \
9555         __GET_REG32((reg));                     \
9556 } while (0)
9557
9558         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9559         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9560         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9561         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9562         GET_REG32_1(SNDDATAC_MODE);
9563         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9564         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9565         GET_REG32_1(SNDBDC_MODE);
9566         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9567         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9568         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9569         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9570         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9571         GET_REG32_1(RCVDCC_MODE);
9572         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9573         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9574         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9575         GET_REG32_1(MBFREE_MODE);
9576         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9577         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9578         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9579         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9580         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9581         GET_REG32_1(RX_CPU_MODE);
9582         GET_REG32_1(RX_CPU_STATE);
9583         GET_REG32_1(RX_CPU_PGMCTR);
9584         GET_REG32_1(RX_CPU_HWBKPT);
9585         GET_REG32_1(TX_CPU_MODE);
9586         GET_REG32_1(TX_CPU_STATE);
9587         GET_REG32_1(TX_CPU_PGMCTR);
9588         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9589         GET_REG32_LOOP(FTQ_RESET, 0x120);
9590         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9591         GET_REG32_1(DMAC_MODE);
9592         GET_REG32_LOOP(GRC_MODE, 0x4c);
9593         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9594                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9595
9596 #undef __GET_REG32
9597 #undef GET_REG32_LOOP
9598 #undef GET_REG32_1
9599
9600         tg3_full_unlock(tp);
9601 }
9602
9603 static int tg3_get_eeprom_len(struct net_device *dev)
9604 {
9605         struct tg3 *tp = netdev_priv(dev);
9606
9607         return tp->nvram_size;
9608 }
9609
9610 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9611 {
9612         struct tg3 *tp = netdev_priv(dev);
9613         int ret;
9614         u8  *pd;
9615         u32 i, offset, len, b_offset, b_count;
9616         __be32 val;
9617
9618         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9619                 return -EINVAL;
9620
9621         if (tp->link_config.phy_is_low_power)
9622                 return -EAGAIN;
9623
9624         offset = eeprom->offset;
9625         len = eeprom->len;
9626         eeprom->len = 0;
9627
9628         eeprom->magic = TG3_EEPROM_MAGIC;
9629
9630         if (offset & 3) {
9631                 /* adjustments to start on required 4 byte boundary */
9632                 b_offset = offset & 3;
9633                 b_count = 4 - b_offset;
9634                 if (b_count > len) {
9635                         /* i.e. offset=1 len=2 */
9636                         b_count = len;
9637                 }
9638                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9639                 if (ret)
9640                         return ret;
9641                 memcpy(data, ((char*)&val) + b_offset, b_count);
9642                 len -= b_count;
9643                 offset += b_count;
9644                 eeprom->len += b_count;
9645         }
9646
9647         /* read bytes upto the last 4 byte boundary */
9648         pd = &data[eeprom->len];
9649         for (i = 0; i < (len - (len & 3)); i += 4) {
9650                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9651                 if (ret) {
9652                         eeprom->len += i;
9653                         return ret;
9654                 }
9655                 memcpy(pd + i, &val, 4);
9656         }
9657         eeprom->len += i;
9658
9659         if (len & 3) {
9660                 /* read last bytes not ending on 4 byte boundary */
9661                 pd = &data[eeprom->len];
9662                 b_count = len & 3;
9663                 b_offset = offset + len - b_count;
9664                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9665                 if (ret)
9666                         return ret;
9667                 memcpy(pd, &val, b_count);
9668                 eeprom->len += b_count;
9669         }
9670         return 0;
9671 }
9672
9673 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9674
9675 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9676 {
9677         struct tg3 *tp = netdev_priv(dev);
9678         int ret;
9679         u32 offset, len, b_offset, odd_len;
9680         u8 *buf;
9681         __be32 start, end;
9682
9683         if (tp->link_config.phy_is_low_power)
9684                 return -EAGAIN;
9685
9686         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9687             eeprom->magic != TG3_EEPROM_MAGIC)
9688                 return -EINVAL;
9689
9690         offset = eeprom->offset;
9691         len = eeprom->len;
9692
9693         if ((b_offset = (offset & 3))) {
9694                 /* adjustments to start on required 4 byte boundary */
9695                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9696                 if (ret)
9697                         return ret;
9698                 len += b_offset;
9699                 offset &= ~3;
9700                 if (len < 4)
9701                         len = 4;
9702         }
9703
9704         odd_len = 0;
9705         if (len & 3) {
9706                 /* adjustments to end on required 4 byte boundary */
9707                 odd_len = 1;
9708                 len = (len + 3) & ~3;
9709                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9710                 if (ret)
9711                         return ret;
9712         }
9713
9714         buf = data;
9715         if (b_offset || odd_len) {
9716                 buf = kmalloc(len, GFP_KERNEL);
9717                 if (!buf)
9718                         return -ENOMEM;
9719                 if (b_offset)
9720                         memcpy(buf, &start, 4);
9721                 if (odd_len)
9722                         memcpy(buf+len-4, &end, 4);
9723                 memcpy(buf + b_offset, data, eeprom->len);
9724         }
9725
9726         ret = tg3_nvram_write_block(tp, offset, len, buf);
9727
9728         if (buf != data)
9729                 kfree(buf);
9730
9731         return ret;
9732 }
9733
9734 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9735 {
9736         struct tg3 *tp = netdev_priv(dev);
9737
9738         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9739                 struct phy_device *phydev;
9740                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9741                         return -EAGAIN;
9742                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9743                 return phy_ethtool_gset(phydev, cmd);
9744         }
9745
9746         cmd->supported = (SUPPORTED_Autoneg);
9747
9748         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9749                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9750                                    SUPPORTED_1000baseT_Full);
9751
9752         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9753                 cmd->supported |= (SUPPORTED_100baseT_Half |
9754                                   SUPPORTED_100baseT_Full |
9755                                   SUPPORTED_10baseT_Half |
9756                                   SUPPORTED_10baseT_Full |
9757                                   SUPPORTED_TP);
9758                 cmd->port = PORT_TP;
9759         } else {
9760                 cmd->supported |= SUPPORTED_FIBRE;
9761                 cmd->port = PORT_FIBRE;
9762         }
9763
9764         cmd->advertising = tp->link_config.advertising;
9765         if (netif_running(dev)) {
9766                 cmd->speed = tp->link_config.active_speed;
9767                 cmd->duplex = tp->link_config.active_duplex;
9768         }
9769         cmd->phy_address = tp->phy_addr;
9770         cmd->transceiver = XCVR_INTERNAL;
9771         cmd->autoneg = tp->link_config.autoneg;
9772         cmd->maxtxpkt = 0;
9773         cmd->maxrxpkt = 0;
9774         return 0;
9775 }
9776
9777 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9778 {
9779         struct tg3 *tp = netdev_priv(dev);
9780
9781         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9782                 struct phy_device *phydev;
9783                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9784                         return -EAGAIN;
9785                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9786                 return phy_ethtool_sset(phydev, cmd);
9787         }
9788
9789         if (cmd->autoneg != AUTONEG_ENABLE &&
9790             cmd->autoneg != AUTONEG_DISABLE)
9791                 return -EINVAL;
9792
9793         if (cmd->autoneg == AUTONEG_DISABLE &&
9794             cmd->duplex != DUPLEX_FULL &&
9795             cmd->duplex != DUPLEX_HALF)
9796                 return -EINVAL;
9797
9798         if (cmd->autoneg == AUTONEG_ENABLE) {
9799                 u32 mask = ADVERTISED_Autoneg |
9800                            ADVERTISED_Pause |
9801                            ADVERTISED_Asym_Pause;
9802
9803                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9804                         mask |= ADVERTISED_1000baseT_Half |
9805                                 ADVERTISED_1000baseT_Full;
9806
9807                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9808                         mask |= ADVERTISED_100baseT_Half |
9809                                 ADVERTISED_100baseT_Full |
9810                                 ADVERTISED_10baseT_Half |
9811                                 ADVERTISED_10baseT_Full |
9812                                 ADVERTISED_TP;
9813                 else
9814                         mask |= ADVERTISED_FIBRE;
9815
9816                 if (cmd->advertising & ~mask)
9817                         return -EINVAL;
9818
9819                 mask &= (ADVERTISED_1000baseT_Half |
9820                          ADVERTISED_1000baseT_Full |
9821                          ADVERTISED_100baseT_Half |
9822                          ADVERTISED_100baseT_Full |
9823                          ADVERTISED_10baseT_Half |
9824                          ADVERTISED_10baseT_Full);
9825
9826                 cmd->advertising &= mask;
9827         } else {
9828                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9829                         if (cmd->speed != SPEED_1000)
9830                                 return -EINVAL;
9831
9832                         if (cmd->duplex != DUPLEX_FULL)
9833                                 return -EINVAL;
9834                 } else {
9835                         if (cmd->speed != SPEED_100 &&
9836                             cmd->speed != SPEED_10)
9837                                 return -EINVAL;
9838                 }
9839         }
9840
9841         tg3_full_lock(tp, 0);
9842
9843         tp->link_config.autoneg = cmd->autoneg;
9844         if (cmd->autoneg == AUTONEG_ENABLE) {
9845                 tp->link_config.advertising = (cmd->advertising |
9846                                               ADVERTISED_Autoneg);
9847                 tp->link_config.speed = SPEED_INVALID;
9848                 tp->link_config.duplex = DUPLEX_INVALID;
9849         } else {
9850                 tp->link_config.advertising = 0;
9851                 tp->link_config.speed = cmd->speed;
9852                 tp->link_config.duplex = cmd->duplex;
9853         }
9854
9855         tp->link_config.orig_speed = tp->link_config.speed;
9856         tp->link_config.orig_duplex = tp->link_config.duplex;
9857         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9858
9859         if (netif_running(dev))
9860                 tg3_setup_phy(tp, 1);
9861
9862         tg3_full_unlock(tp);
9863
9864         return 0;
9865 }
9866
9867 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9868 {
9869         struct tg3 *tp = netdev_priv(dev);
9870
9871         strcpy(info->driver, DRV_MODULE_NAME);
9872         strcpy(info->version, DRV_MODULE_VERSION);
9873         strcpy(info->fw_version, tp->fw_ver);
9874         strcpy(info->bus_info, pci_name(tp->pdev));
9875 }
9876
9877 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9878 {
9879         struct tg3 *tp = netdev_priv(dev);
9880
9881         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9882             device_can_wakeup(&tp->pdev->dev))
9883                 wol->supported = WAKE_MAGIC;
9884         else
9885                 wol->supported = 0;
9886         wol->wolopts = 0;
9887         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9888             device_can_wakeup(&tp->pdev->dev))
9889                 wol->wolopts = WAKE_MAGIC;
9890         memset(&wol->sopass, 0, sizeof(wol->sopass));
9891 }
9892
9893 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9894 {
9895         struct tg3 *tp = netdev_priv(dev);
9896         struct device *dp = &tp->pdev->dev;
9897
9898         if (wol->wolopts & ~WAKE_MAGIC)
9899                 return -EINVAL;
9900         if ((wol->wolopts & WAKE_MAGIC) &&
9901             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9902                 return -EINVAL;
9903
9904         spin_lock_bh(&tp->lock);
9905         if (wol->wolopts & WAKE_MAGIC) {
9906                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9907                 device_set_wakeup_enable(dp, true);
9908         } else {
9909                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9910                 device_set_wakeup_enable(dp, false);
9911         }
9912         spin_unlock_bh(&tp->lock);
9913
9914         return 0;
9915 }
9916
9917 static u32 tg3_get_msglevel(struct net_device *dev)
9918 {
9919         struct tg3 *tp = netdev_priv(dev);
9920         return tp->msg_enable;
9921 }
9922
9923 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9924 {
9925         struct tg3 *tp = netdev_priv(dev);
9926         tp->msg_enable = value;
9927 }
9928
9929 static int tg3_set_tso(struct net_device *dev, u32 value)
9930 {
9931         struct tg3 *tp = netdev_priv(dev);
9932
9933         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9934                 if (value)
9935                         return -EINVAL;
9936                 return 0;
9937         }
9938         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9939             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9940              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9941                 if (value) {
9942                         dev->features |= NETIF_F_TSO6;
9943                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9944                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9945                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9946                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9947                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9948                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9949                                 dev->features |= NETIF_F_TSO_ECN;
9950                 } else
9951                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9952         }
9953         return ethtool_op_set_tso(dev, value);
9954 }
9955
9956 static int tg3_nway_reset(struct net_device *dev)
9957 {
9958         struct tg3 *tp = netdev_priv(dev);
9959         int r;
9960
9961         if (!netif_running(dev))
9962                 return -EAGAIN;
9963
9964         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9965                 return -EINVAL;
9966
9967         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9968                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9969                         return -EAGAIN;
9970                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9971         } else {
9972                 u32 bmcr;
9973
9974                 spin_lock_bh(&tp->lock);
9975                 r = -EINVAL;
9976                 tg3_readphy(tp, MII_BMCR, &bmcr);
9977                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9978                     ((bmcr & BMCR_ANENABLE) ||
9979                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9980                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9981                                                    BMCR_ANENABLE);
9982                         r = 0;
9983                 }
9984                 spin_unlock_bh(&tp->lock);
9985         }
9986
9987         return r;
9988 }
9989
9990 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9991 {
9992         struct tg3 *tp = netdev_priv(dev);
9993
9994         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9995         ering->rx_mini_max_pending = 0;
9996         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9997                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9998         else
9999                 ering->rx_jumbo_max_pending = 0;
10000
10001         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10002
10003         ering->rx_pending = tp->rx_pending;
10004         ering->rx_mini_pending = 0;
10005         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10006                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10007         else
10008                 ering->rx_jumbo_pending = 0;
10009
10010         ering->tx_pending = tp->napi[0].tx_pending;
10011 }
10012
10013 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10014 {
10015         struct tg3 *tp = netdev_priv(dev);
10016         int i, irq_sync = 0, err = 0;
10017
10018         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
10019             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
10020             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10021             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10022             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10023              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10024                 return -EINVAL;
10025
10026         if (netif_running(dev)) {
10027                 tg3_phy_stop(tp);
10028                 tg3_netif_stop(tp);
10029                 irq_sync = 1;
10030         }
10031
10032         tg3_full_lock(tp, irq_sync);
10033
10034         tp->rx_pending = ering->rx_pending;
10035
10036         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10037             tp->rx_pending > 63)
10038                 tp->rx_pending = 63;
10039         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10040
10041         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
10042                 tp->napi[i].tx_pending = ering->tx_pending;
10043
10044         if (netif_running(dev)) {
10045                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10046                 err = tg3_restart_hw(tp, 1);
10047                 if (!err)
10048                         tg3_netif_start(tp);
10049         }
10050
10051         tg3_full_unlock(tp);
10052
10053         if (irq_sync && !err)
10054                 tg3_phy_start(tp);
10055
10056         return err;
10057 }
10058
10059 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10060 {
10061         struct tg3 *tp = netdev_priv(dev);
10062
10063         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10064
10065         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10066                 epause->rx_pause = 1;
10067         else
10068                 epause->rx_pause = 0;
10069
10070         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10071                 epause->tx_pause = 1;
10072         else
10073                 epause->tx_pause = 0;
10074 }
10075
10076 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10077 {
10078         struct tg3 *tp = netdev_priv(dev);
10079         int err = 0;
10080
10081         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10082                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10083                         return -EAGAIN;
10084
10085                 if (epause->autoneg) {
10086                         u32 newadv;
10087                         struct phy_device *phydev;
10088
10089                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10090
10091                         if (epause->rx_pause) {
10092                                 if (epause->tx_pause)
10093                                         newadv = ADVERTISED_Pause;
10094                                 else
10095                                         newadv = ADVERTISED_Pause |
10096                                                  ADVERTISED_Asym_Pause;
10097                         } else if (epause->tx_pause) {
10098                                 newadv = ADVERTISED_Asym_Pause;
10099                         } else
10100                                 newadv = 0;
10101
10102                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10103                                 u32 oldadv = phydev->advertising &
10104                                              (ADVERTISED_Pause |
10105                                               ADVERTISED_Asym_Pause);
10106                                 if (oldadv != newadv) {
10107                                         phydev->advertising &=
10108                                                 ~(ADVERTISED_Pause |
10109                                                   ADVERTISED_Asym_Pause);
10110                                         phydev->advertising |= newadv;
10111                                         err = phy_start_aneg(phydev);
10112                                 }
10113                         } else {
10114                                 tp->link_config.advertising &=
10115                                                 ~(ADVERTISED_Pause |
10116                                                   ADVERTISED_Asym_Pause);
10117                                 tp->link_config.advertising |= newadv;
10118                         }
10119                 } else {
10120                         if (epause->rx_pause)
10121                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10122                         else
10123                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10124
10125                         if (epause->tx_pause)
10126                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10127                         else
10128                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10129
10130                         if (netif_running(dev))
10131                                 tg3_setup_flow_control(tp, 0, 0);
10132                 }
10133         } else {
10134                 int irq_sync = 0;
10135
10136                 if (netif_running(dev)) {
10137                         tg3_netif_stop(tp);
10138                         irq_sync = 1;
10139                 }
10140
10141                 tg3_full_lock(tp, irq_sync);
10142
10143                 if (epause->autoneg)
10144                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10145                 else
10146                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10147                 if (epause->rx_pause)
10148                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10149                 else
10150                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10151                 if (epause->tx_pause)
10152                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10153                 else
10154                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10155
10156                 if (netif_running(dev)) {
10157                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10158                         err = tg3_restart_hw(tp, 1);
10159                         if (!err)
10160                                 tg3_netif_start(tp);
10161                 }
10162
10163                 tg3_full_unlock(tp);
10164         }
10165
10166         return err;
10167 }
10168
10169 static u32 tg3_get_rx_csum(struct net_device *dev)
10170 {
10171         struct tg3 *tp = netdev_priv(dev);
10172         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10173 }
10174
10175 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10176 {
10177         struct tg3 *tp = netdev_priv(dev);
10178
10179         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10180                 if (data != 0)
10181                         return -EINVAL;
10182                 return 0;
10183         }
10184
10185         spin_lock_bh(&tp->lock);
10186         if (data)
10187                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10188         else
10189                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10190         spin_unlock_bh(&tp->lock);
10191
10192         return 0;
10193 }
10194
10195 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10196 {
10197         struct tg3 *tp = netdev_priv(dev);
10198
10199         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10200                 if (data != 0)
10201                         return -EINVAL;
10202                 return 0;
10203         }
10204
10205         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10206                 ethtool_op_set_tx_ipv6_csum(dev, data);
10207         else
10208                 ethtool_op_set_tx_csum(dev, data);
10209
10210         return 0;
10211 }
10212
10213 static int tg3_get_sset_count (struct net_device *dev, int sset)
10214 {
10215         switch (sset) {
10216         case ETH_SS_TEST:
10217                 return TG3_NUM_TEST;
10218         case ETH_SS_STATS:
10219                 return TG3_NUM_STATS;
10220         default:
10221                 return -EOPNOTSUPP;
10222         }
10223 }
10224
10225 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10226 {
10227         switch (stringset) {
10228         case ETH_SS_STATS:
10229                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10230                 break;
10231         case ETH_SS_TEST:
10232                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10233                 break;
10234         default:
10235                 WARN_ON(1);     /* we need a WARN() */
10236                 break;
10237         }
10238 }
10239
10240 static int tg3_phys_id(struct net_device *dev, u32 data)
10241 {
10242         struct tg3 *tp = netdev_priv(dev);
10243         int i;
10244
10245         if (!netif_running(tp->dev))
10246                 return -EAGAIN;
10247
10248         if (data == 0)
10249                 data = UINT_MAX / 2;
10250
10251         for (i = 0; i < (data * 2); i++) {
10252                 if ((i % 2) == 0)
10253                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10254                                            LED_CTRL_1000MBPS_ON |
10255                                            LED_CTRL_100MBPS_ON |
10256                                            LED_CTRL_10MBPS_ON |
10257                                            LED_CTRL_TRAFFIC_OVERRIDE |
10258                                            LED_CTRL_TRAFFIC_BLINK |
10259                                            LED_CTRL_TRAFFIC_LED);
10260
10261                 else
10262                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10263                                            LED_CTRL_TRAFFIC_OVERRIDE);
10264
10265                 if (msleep_interruptible(500))
10266                         break;
10267         }
10268         tw32(MAC_LED_CTRL, tp->led_ctrl);
10269         return 0;
10270 }
10271
10272 static void tg3_get_ethtool_stats (struct net_device *dev,
10273                                    struct ethtool_stats *estats, u64 *tmp_stats)
10274 {
10275         struct tg3 *tp = netdev_priv(dev);
10276         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10277 }
10278
10279 #define NVRAM_TEST_SIZE 0x100
10280 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10281 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10282 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10283 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10284 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10285
10286 static int tg3_test_nvram(struct tg3 *tp)
10287 {
10288         u32 csum, magic;
10289         __be32 *buf;
10290         int i, j, k, err = 0, size;
10291
10292         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10293                 return 0;
10294
10295         if (tg3_nvram_read(tp, 0, &magic) != 0)
10296                 return -EIO;
10297
10298         if (magic == TG3_EEPROM_MAGIC)
10299                 size = NVRAM_TEST_SIZE;
10300         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10301                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10302                     TG3_EEPROM_SB_FORMAT_1) {
10303                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10304                         case TG3_EEPROM_SB_REVISION_0:
10305                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10306                                 break;
10307                         case TG3_EEPROM_SB_REVISION_2:
10308                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10309                                 break;
10310                         case TG3_EEPROM_SB_REVISION_3:
10311                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10312                                 break;
10313                         default:
10314                                 return 0;
10315                         }
10316                 } else
10317                         return 0;
10318         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10319                 size = NVRAM_SELFBOOT_HW_SIZE;
10320         else
10321                 return -EIO;
10322
10323         buf = kmalloc(size, GFP_KERNEL);
10324         if (buf == NULL)
10325                 return -ENOMEM;
10326
10327         err = -EIO;
10328         for (i = 0, j = 0; i < size; i += 4, j++) {
10329                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10330                 if (err)
10331                         break;
10332         }
10333         if (i < size)
10334                 goto out;
10335
10336         /* Selfboot format */
10337         magic = be32_to_cpu(buf[0]);
10338         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10339             TG3_EEPROM_MAGIC_FW) {
10340                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10341
10342                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10343                     TG3_EEPROM_SB_REVISION_2) {
10344                         /* For rev 2, the csum doesn't include the MBA. */
10345                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10346                                 csum8 += buf8[i];
10347                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10348                                 csum8 += buf8[i];
10349                 } else {
10350                         for (i = 0; i < size; i++)
10351                                 csum8 += buf8[i];
10352                 }
10353
10354                 if (csum8 == 0) {
10355                         err = 0;
10356                         goto out;
10357                 }
10358
10359                 err = -EIO;
10360                 goto out;
10361         }
10362
10363         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10364             TG3_EEPROM_MAGIC_HW) {
10365                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10366                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10367                 u8 *buf8 = (u8 *) buf;
10368
10369                 /* Separate the parity bits and the data bytes.  */
10370                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10371                         if ((i == 0) || (i == 8)) {
10372                                 int l;
10373                                 u8 msk;
10374
10375                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10376                                         parity[k++] = buf8[i] & msk;
10377                                 i++;
10378                         }
10379                         else if (i == 16) {
10380                                 int l;
10381                                 u8 msk;
10382
10383                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10384                                         parity[k++] = buf8[i] & msk;
10385                                 i++;
10386
10387                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10388                                         parity[k++] = buf8[i] & msk;
10389                                 i++;
10390                         }
10391                         data[j++] = buf8[i];
10392                 }
10393
10394                 err = -EIO;
10395                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10396                         u8 hw8 = hweight8(data[i]);
10397
10398                         if ((hw8 & 0x1) && parity[i])
10399                                 goto out;
10400                         else if (!(hw8 & 0x1) && !parity[i])
10401                                 goto out;
10402                 }
10403                 err = 0;
10404                 goto out;
10405         }
10406
10407         /* Bootstrap checksum at offset 0x10 */
10408         csum = calc_crc((unsigned char *) buf, 0x10);
10409         if (csum != be32_to_cpu(buf[0x10/4]))
10410                 goto out;
10411
10412         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10413         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10414         if (csum != be32_to_cpu(buf[0xfc/4]))
10415                 goto out;
10416
10417         err = 0;
10418
10419 out:
10420         kfree(buf);
10421         return err;
10422 }
10423
10424 #define TG3_SERDES_TIMEOUT_SEC  2
10425 #define TG3_COPPER_TIMEOUT_SEC  6
10426
10427 static int tg3_test_link(struct tg3 *tp)
10428 {
10429         int i, max;
10430
10431         if (!netif_running(tp->dev))
10432                 return -ENODEV;
10433
10434         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10435                 max = TG3_SERDES_TIMEOUT_SEC;
10436         else
10437                 max = TG3_COPPER_TIMEOUT_SEC;
10438
10439         for (i = 0; i < max; i++) {
10440                 if (netif_carrier_ok(tp->dev))
10441                         return 0;
10442
10443                 if (msleep_interruptible(1000))
10444                         break;
10445         }
10446
10447         return -EIO;
10448 }
10449
10450 /* Only test the commonly used registers */
10451 static int tg3_test_registers(struct tg3 *tp)
10452 {
10453         int i, is_5705, is_5750;
10454         u32 offset, read_mask, write_mask, val, save_val, read_val;
10455         static struct {
10456                 u16 offset;
10457                 u16 flags;
10458 #define TG3_FL_5705     0x1
10459 #define TG3_FL_NOT_5705 0x2
10460 #define TG3_FL_NOT_5788 0x4
10461 #define TG3_FL_NOT_5750 0x8
10462                 u32 read_mask;
10463                 u32 write_mask;
10464         } reg_tbl[] = {
10465                 /* MAC Control Registers */
10466                 { MAC_MODE, TG3_FL_NOT_5705,
10467                         0x00000000, 0x00ef6f8c },
10468                 { MAC_MODE, TG3_FL_5705,
10469                         0x00000000, 0x01ef6b8c },
10470                 { MAC_STATUS, TG3_FL_NOT_5705,
10471                         0x03800107, 0x00000000 },
10472                 { MAC_STATUS, TG3_FL_5705,
10473                         0x03800100, 0x00000000 },
10474                 { MAC_ADDR_0_HIGH, 0x0000,
10475                         0x00000000, 0x0000ffff },
10476                 { MAC_ADDR_0_LOW, 0x0000,
10477                         0x00000000, 0xffffffff },
10478                 { MAC_RX_MTU_SIZE, 0x0000,
10479                         0x00000000, 0x0000ffff },
10480                 { MAC_TX_MODE, 0x0000,
10481                         0x00000000, 0x00000070 },
10482                 { MAC_TX_LENGTHS, 0x0000,
10483                         0x00000000, 0x00003fff },
10484                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10485                         0x00000000, 0x000007fc },
10486                 { MAC_RX_MODE, TG3_FL_5705,
10487                         0x00000000, 0x000007dc },
10488                 { MAC_HASH_REG_0, 0x0000,
10489                         0x00000000, 0xffffffff },
10490                 { MAC_HASH_REG_1, 0x0000,
10491                         0x00000000, 0xffffffff },
10492                 { MAC_HASH_REG_2, 0x0000,
10493                         0x00000000, 0xffffffff },
10494                 { MAC_HASH_REG_3, 0x0000,
10495                         0x00000000, 0xffffffff },
10496
10497                 /* Receive Data and Receive BD Initiator Control Registers. */
10498                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10499                         0x00000000, 0xffffffff },
10500                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10501                         0x00000000, 0xffffffff },
10502                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10503                         0x00000000, 0x00000003 },
10504                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10505                         0x00000000, 0xffffffff },
10506                 { RCVDBDI_STD_BD+0, 0x0000,
10507                         0x00000000, 0xffffffff },
10508                 { RCVDBDI_STD_BD+4, 0x0000,
10509                         0x00000000, 0xffffffff },
10510                 { RCVDBDI_STD_BD+8, 0x0000,
10511                         0x00000000, 0xffff0002 },
10512                 { RCVDBDI_STD_BD+0xc, 0x0000,
10513                         0x00000000, 0xffffffff },
10514
10515                 /* Receive BD Initiator Control Registers. */
10516                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10517                         0x00000000, 0xffffffff },
10518                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10519                         0x00000000, 0x000003ff },
10520                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10521                         0x00000000, 0xffffffff },
10522
10523                 /* Host Coalescing Control Registers. */
10524                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10525                         0x00000000, 0x00000004 },
10526                 { HOSTCC_MODE, TG3_FL_5705,
10527                         0x00000000, 0x000000f6 },
10528                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10529                         0x00000000, 0xffffffff },
10530                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10531                         0x00000000, 0x000003ff },
10532                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10533                         0x00000000, 0xffffffff },
10534                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10535                         0x00000000, 0x000003ff },
10536                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10537                         0x00000000, 0xffffffff },
10538                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10539                         0x00000000, 0x000000ff },
10540                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10541                         0x00000000, 0xffffffff },
10542                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10543                         0x00000000, 0x000000ff },
10544                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10545                         0x00000000, 0xffffffff },
10546                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10547                         0x00000000, 0xffffffff },
10548                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10549                         0x00000000, 0xffffffff },
10550                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10551                         0x00000000, 0x000000ff },
10552                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10553                         0x00000000, 0xffffffff },
10554                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10555                         0x00000000, 0x000000ff },
10556                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10557                         0x00000000, 0xffffffff },
10558                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10559                         0x00000000, 0xffffffff },
10560                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10561                         0x00000000, 0xffffffff },
10562                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10563                         0x00000000, 0xffffffff },
10564                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10565                         0x00000000, 0xffffffff },
10566                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10567                         0xffffffff, 0x00000000 },
10568                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10569                         0xffffffff, 0x00000000 },
10570
10571                 /* Buffer Manager Control Registers. */
10572                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10573                         0x00000000, 0x007fff80 },
10574                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10575                         0x00000000, 0x007fffff },
10576                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10577                         0x00000000, 0x0000003f },
10578                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10579                         0x00000000, 0x000001ff },
10580                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10581                         0x00000000, 0x000001ff },
10582                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10583                         0xffffffff, 0x00000000 },
10584                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10585                         0xffffffff, 0x00000000 },
10586
10587                 /* Mailbox Registers */
10588                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10589                         0x00000000, 0x000001ff },
10590                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10591                         0x00000000, 0x000001ff },
10592                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10593                         0x00000000, 0x000007ff },
10594                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10595                         0x00000000, 0x000001ff },
10596
10597                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10598         };
10599
10600         is_5705 = is_5750 = 0;
10601         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10602                 is_5705 = 1;
10603                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10604                         is_5750 = 1;
10605         }
10606
10607         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10608                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10609                         continue;
10610
10611                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10612                         continue;
10613
10614                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10615                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10616                         continue;
10617
10618                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10619                         continue;
10620
10621                 offset = (u32) reg_tbl[i].offset;
10622                 read_mask = reg_tbl[i].read_mask;
10623                 write_mask = reg_tbl[i].write_mask;
10624
10625                 /* Save the original register content */
10626                 save_val = tr32(offset);
10627
10628                 /* Determine the read-only value. */
10629                 read_val = save_val & read_mask;
10630
10631                 /* Write zero to the register, then make sure the read-only bits
10632                  * are not changed and the read/write bits are all zeros.
10633                  */
10634                 tw32(offset, 0);
10635
10636                 val = tr32(offset);
10637
10638                 /* Test the read-only and read/write bits. */
10639                 if (((val & read_mask) != read_val) || (val & write_mask))
10640                         goto out;
10641
10642                 /* Write ones to all the bits defined by RdMask and WrMask, then
10643                  * make sure the read-only bits are not changed and the
10644                  * read/write bits are all ones.
10645                  */
10646                 tw32(offset, read_mask | write_mask);
10647
10648                 val = tr32(offset);
10649
10650                 /* Test the read-only bits. */
10651                 if ((val & read_mask) != read_val)
10652                         goto out;
10653
10654                 /* Test the read/write bits. */
10655                 if ((val & write_mask) != write_mask)
10656                         goto out;
10657
10658                 tw32(offset, save_val);
10659         }
10660
10661         return 0;
10662
10663 out:
10664         if (netif_msg_hw(tp))
10665                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10666                        offset);
10667         tw32(offset, save_val);
10668         return -EIO;
10669 }
10670
10671 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10672 {
10673         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10674         int i;
10675         u32 j;
10676
10677         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10678                 for (j = 0; j < len; j += 4) {
10679                         u32 val;
10680
10681                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10682                         tg3_read_mem(tp, offset + j, &val);
10683                         if (val != test_pattern[i])
10684                                 return -EIO;
10685                 }
10686         }
10687         return 0;
10688 }
10689
10690 static int tg3_test_memory(struct tg3 *tp)
10691 {
10692         static struct mem_entry {
10693                 u32 offset;
10694                 u32 len;
10695         } mem_tbl_570x[] = {
10696                 { 0x00000000, 0x00b50},
10697                 { 0x00002000, 0x1c000},
10698                 { 0xffffffff, 0x00000}
10699         }, mem_tbl_5705[] = {
10700                 { 0x00000100, 0x0000c},
10701                 { 0x00000200, 0x00008},
10702                 { 0x00004000, 0x00800},
10703                 { 0x00006000, 0x01000},
10704                 { 0x00008000, 0x02000},
10705                 { 0x00010000, 0x0e000},
10706                 { 0xffffffff, 0x00000}
10707         }, mem_tbl_5755[] = {
10708                 { 0x00000200, 0x00008},
10709                 { 0x00004000, 0x00800},
10710                 { 0x00006000, 0x00800},
10711                 { 0x00008000, 0x02000},
10712                 { 0x00010000, 0x0c000},
10713                 { 0xffffffff, 0x00000}
10714         }, mem_tbl_5906[] = {
10715                 { 0x00000200, 0x00008},
10716                 { 0x00004000, 0x00400},
10717                 { 0x00006000, 0x00400},
10718                 { 0x00008000, 0x01000},
10719                 { 0x00010000, 0x01000},
10720                 { 0xffffffff, 0x00000}
10721         }, mem_tbl_5717[] = {
10722                 { 0x00000200, 0x00008},
10723                 { 0x00010000, 0x0a000},
10724                 { 0x00020000, 0x13c00},
10725                 { 0xffffffff, 0x00000}
10726         }, mem_tbl_57765[] = {
10727                 { 0x00000200, 0x00008},
10728                 { 0x00004000, 0x00800},
10729                 { 0x00006000, 0x09800},
10730                 { 0x00010000, 0x0a000},
10731                 { 0xffffffff, 0x00000}
10732         };
10733         struct mem_entry *mem_tbl;
10734         int err = 0;
10735         int i;
10736
10737         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10738                 mem_tbl = mem_tbl_5717;
10739         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10740                 mem_tbl = mem_tbl_57765;
10741         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10742                 mem_tbl = mem_tbl_5755;
10743         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10744                 mem_tbl = mem_tbl_5906;
10745         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10746                 mem_tbl = mem_tbl_5705;
10747         else
10748                 mem_tbl = mem_tbl_570x;
10749
10750         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10751                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10752                     mem_tbl[i].len)) != 0)
10753                         break;
10754         }
10755
10756         return err;
10757 }
10758
10759 #define TG3_MAC_LOOPBACK        0
10760 #define TG3_PHY_LOOPBACK        1
10761
10762 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10763 {
10764         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10765         u32 desc_idx, coal_now;
10766         struct sk_buff *skb, *rx_skb;
10767         u8 *tx_data;
10768         dma_addr_t map;
10769         int num_pkts, tx_len, rx_len, i, err;
10770         struct tg3_rx_buffer_desc *desc;
10771         struct tg3_napi *tnapi, *rnapi;
10772         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10773
10774         if (tp->irq_cnt > 1) {
10775                 tnapi = &tp->napi[1];
10776                 rnapi = &tp->napi[1];
10777         } else {
10778                 tnapi = &tp->napi[0];
10779                 rnapi = &tp->napi[0];
10780         }
10781         coal_now = tnapi->coal_now | rnapi->coal_now;
10782
10783         if (loopback_mode == TG3_MAC_LOOPBACK) {
10784                 /* HW errata - mac loopback fails in some cases on 5780.
10785                  * Normal traffic and PHY loopback are not affected by
10786                  * errata.
10787                  */
10788                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10789                         return 0;
10790
10791                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10792                            MAC_MODE_PORT_INT_LPBACK;
10793                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10794                         mac_mode |= MAC_MODE_LINK_POLARITY;
10795                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10796                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10797                 else
10798                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10799                 tw32(MAC_MODE, mac_mode);
10800         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10801                 u32 val;
10802
10803                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10804                         tg3_phy_fet_toggle_apd(tp, false);
10805                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10806                 } else
10807                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10808
10809                 tg3_phy_toggle_automdix(tp, 0);
10810
10811                 tg3_writephy(tp, MII_BMCR, val);
10812                 udelay(40);
10813
10814                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10815                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10816                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10817                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10818                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10819                 } else
10820                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10821
10822                 /* reset to prevent losing 1st rx packet intermittently */
10823                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10824                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10825                         udelay(10);
10826                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10827                 }
10828                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10829                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10830                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10831                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10832                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10833                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10834                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10835                 }
10836                 tw32(MAC_MODE, mac_mode);
10837         }
10838         else
10839                 return -EINVAL;
10840
10841         err = -EIO;
10842
10843         tx_len = 1514;
10844         skb = netdev_alloc_skb(tp->dev, tx_len);
10845         if (!skb)
10846                 return -ENOMEM;
10847
10848         tx_data = skb_put(skb, tx_len);
10849         memcpy(tx_data, tp->dev->dev_addr, 6);
10850         memset(tx_data + 6, 0x0, 8);
10851
10852         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10853
10854         for (i = 14; i < tx_len; i++)
10855                 tx_data[i] = (u8) (i & 0xff);
10856
10857         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10858         if (pci_dma_mapping_error(tp->pdev, map)) {
10859                 dev_kfree_skb(skb);
10860                 return -EIO;
10861         }
10862
10863         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10864                rnapi->coal_now);
10865
10866         udelay(10);
10867
10868         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10869
10870         num_pkts = 0;
10871
10872         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10873
10874         tnapi->tx_prod++;
10875         num_pkts++;
10876
10877         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10878         tr32_mailbox(tnapi->prodmbox);
10879
10880         udelay(10);
10881
10882         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10883         for (i = 0; i < 35; i++) {
10884                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10885                        coal_now);
10886
10887                 udelay(10);
10888
10889                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10890                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10891                 if ((tx_idx == tnapi->tx_prod) &&
10892                     (rx_idx == (rx_start_idx + num_pkts)))
10893                         break;
10894         }
10895
10896         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10897         dev_kfree_skb(skb);
10898
10899         if (tx_idx != tnapi->tx_prod)
10900                 goto out;
10901
10902         if (rx_idx != rx_start_idx + num_pkts)
10903                 goto out;
10904
10905         desc = &rnapi->rx_rcb[rx_start_idx];
10906         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10907         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10908         if (opaque_key != RXD_OPAQUE_RING_STD)
10909                 goto out;
10910
10911         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10912             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10913                 goto out;
10914
10915         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10916         if (rx_len != tx_len)
10917                 goto out;
10918
10919         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10920
10921         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10922         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10923
10924         for (i = 14; i < tx_len; i++) {
10925                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10926                         goto out;
10927         }
10928         err = 0;
10929
10930         /* tg3_free_rings will unmap and free the rx_skb */
10931 out:
10932         return err;
10933 }
10934
10935 #define TG3_MAC_LOOPBACK_FAILED         1
10936 #define TG3_PHY_LOOPBACK_FAILED         2
10937 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10938                                          TG3_PHY_LOOPBACK_FAILED)
10939
10940 static int tg3_test_loopback(struct tg3 *tp)
10941 {
10942         int err = 0;
10943         u32 cpmuctrl = 0;
10944
10945         if (!netif_running(tp->dev))
10946                 return TG3_LOOPBACK_FAILED;
10947
10948         err = tg3_reset_hw(tp, 1);
10949         if (err)
10950                 return TG3_LOOPBACK_FAILED;
10951
10952         /* Turn off gphy autopowerdown. */
10953         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10954                 tg3_phy_toggle_apd(tp, false);
10955
10956         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10957                 int i;
10958                 u32 status;
10959
10960                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10961
10962                 /* Wait for up to 40 microseconds to acquire lock. */
10963                 for (i = 0; i < 4; i++) {
10964                         status = tr32(TG3_CPMU_MUTEX_GNT);
10965                         if (status == CPMU_MUTEX_GNT_DRIVER)
10966                                 break;
10967                         udelay(10);
10968                 }
10969
10970                 if (status != CPMU_MUTEX_GNT_DRIVER)
10971                         return TG3_LOOPBACK_FAILED;
10972
10973                 /* Turn off link-based power management. */
10974                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10975                 tw32(TG3_CPMU_CTRL,
10976                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10977                                   CPMU_CTRL_LINK_AWARE_MODE));
10978         }
10979
10980         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10981                 err |= TG3_MAC_LOOPBACK_FAILED;
10982
10983         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10984                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10985
10986                 /* Release the mutex */
10987                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10988         }
10989
10990         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10991             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10992                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10993                         err |= TG3_PHY_LOOPBACK_FAILED;
10994         }
10995
10996         /* Re-enable gphy autopowerdown. */
10997         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10998                 tg3_phy_toggle_apd(tp, true);
10999
11000         return err;
11001 }
11002
11003 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11004                           u64 *data)
11005 {
11006         struct tg3 *tp = netdev_priv(dev);
11007
11008         if (tp->link_config.phy_is_low_power)
11009                 tg3_set_power_state(tp, PCI_D0);
11010
11011         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11012
11013         if (tg3_test_nvram(tp) != 0) {
11014                 etest->flags |= ETH_TEST_FL_FAILED;
11015                 data[0] = 1;
11016         }
11017         if (tg3_test_link(tp) != 0) {
11018                 etest->flags |= ETH_TEST_FL_FAILED;
11019                 data[1] = 1;
11020         }
11021         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11022                 int err, err2 = 0, irq_sync = 0;
11023
11024                 if (netif_running(dev)) {
11025                         tg3_phy_stop(tp);
11026                         tg3_netif_stop(tp);
11027                         irq_sync = 1;
11028                 }
11029
11030                 tg3_full_lock(tp, irq_sync);
11031
11032                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11033                 err = tg3_nvram_lock(tp);
11034                 tg3_halt_cpu(tp, RX_CPU_BASE);
11035                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11036                         tg3_halt_cpu(tp, TX_CPU_BASE);
11037                 if (!err)
11038                         tg3_nvram_unlock(tp);
11039
11040                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
11041                         tg3_phy_reset(tp);
11042
11043                 if (tg3_test_registers(tp) != 0) {
11044                         etest->flags |= ETH_TEST_FL_FAILED;
11045                         data[2] = 1;
11046                 }
11047                 if (tg3_test_memory(tp) != 0) {
11048                         etest->flags |= ETH_TEST_FL_FAILED;
11049                         data[3] = 1;
11050                 }
11051                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11052                         etest->flags |= ETH_TEST_FL_FAILED;
11053
11054                 tg3_full_unlock(tp);
11055
11056                 if (tg3_test_interrupt(tp) != 0) {
11057                         etest->flags |= ETH_TEST_FL_FAILED;
11058                         data[5] = 1;
11059                 }
11060
11061                 tg3_full_lock(tp, 0);
11062
11063                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11064                 if (netif_running(dev)) {
11065                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11066                         err2 = tg3_restart_hw(tp, 1);
11067                         if (!err2)
11068                                 tg3_netif_start(tp);
11069                 }
11070
11071                 tg3_full_unlock(tp);
11072
11073                 if (irq_sync && !err2)
11074                         tg3_phy_start(tp);
11075         }
11076         if (tp->link_config.phy_is_low_power)
11077                 tg3_set_power_state(tp, PCI_D3hot);
11078
11079 }
11080
11081 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11082 {
11083         struct mii_ioctl_data *data = if_mii(ifr);
11084         struct tg3 *tp = netdev_priv(dev);
11085         int err;
11086
11087         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11088                 struct phy_device *phydev;
11089                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11090                         return -EAGAIN;
11091                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11092                 return phy_mii_ioctl(phydev, data, cmd);
11093         }
11094
11095         switch(cmd) {
11096         case SIOCGMIIPHY:
11097                 data->phy_id = tp->phy_addr;
11098
11099                 /* fallthru */
11100         case SIOCGMIIREG: {
11101                 u32 mii_regval;
11102
11103                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11104                         break;                  /* We have no PHY */
11105
11106                 if (tp->link_config.phy_is_low_power)
11107                         return -EAGAIN;
11108
11109                 spin_lock_bh(&tp->lock);
11110                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11111                 spin_unlock_bh(&tp->lock);
11112
11113                 data->val_out = mii_regval;
11114
11115                 return err;
11116         }
11117
11118         case SIOCSMIIREG:
11119                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11120                         break;                  /* We have no PHY */
11121
11122                 if (tp->link_config.phy_is_low_power)
11123                         return -EAGAIN;
11124
11125                 spin_lock_bh(&tp->lock);
11126                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11127                 spin_unlock_bh(&tp->lock);
11128
11129                 return err;
11130
11131         default:
11132                 /* do nothing */
11133                 break;
11134         }
11135         return -EOPNOTSUPP;
11136 }
11137
11138 #if TG3_VLAN_TAG_USED
11139 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11140 {
11141         struct tg3 *tp = netdev_priv(dev);
11142
11143         if (!netif_running(dev)) {
11144                 tp->vlgrp = grp;
11145                 return;
11146         }
11147
11148         tg3_netif_stop(tp);
11149
11150         tg3_full_lock(tp, 0);
11151
11152         tp->vlgrp = grp;
11153
11154         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11155         __tg3_set_rx_mode(dev);
11156
11157         tg3_netif_start(tp);
11158
11159         tg3_full_unlock(tp);
11160 }
11161 #endif
11162
11163 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11164 {
11165         struct tg3 *tp = netdev_priv(dev);
11166
11167         memcpy(ec, &tp->coal, sizeof(*ec));
11168         return 0;
11169 }
11170
11171 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11172 {
11173         struct tg3 *tp = netdev_priv(dev);
11174         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11175         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11176
11177         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11178                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11179                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11180                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11181                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11182         }
11183
11184         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11185             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11186             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11187             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11188             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11189             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11190             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11191             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11192             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11193             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11194                 return -EINVAL;
11195
11196         /* No rx interrupts will be generated if both are zero */
11197         if ((ec->rx_coalesce_usecs == 0) &&
11198             (ec->rx_max_coalesced_frames == 0))
11199                 return -EINVAL;
11200
11201         /* No tx interrupts will be generated if both are zero */
11202         if ((ec->tx_coalesce_usecs == 0) &&
11203             (ec->tx_max_coalesced_frames == 0))
11204                 return -EINVAL;
11205
11206         /* Only copy relevant parameters, ignore all others. */
11207         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11208         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11209         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11210         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11211         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11212         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11213         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11214         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11215         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11216
11217         if (netif_running(dev)) {
11218                 tg3_full_lock(tp, 0);
11219                 __tg3_set_coalesce(tp, &tp->coal);
11220                 tg3_full_unlock(tp);
11221         }
11222         return 0;
11223 }
11224
11225 static const struct ethtool_ops tg3_ethtool_ops = {
11226         .get_settings           = tg3_get_settings,
11227         .set_settings           = tg3_set_settings,
11228         .get_drvinfo            = tg3_get_drvinfo,
11229         .get_regs_len           = tg3_get_regs_len,
11230         .get_regs               = tg3_get_regs,
11231         .get_wol                = tg3_get_wol,
11232         .set_wol                = tg3_set_wol,
11233         .get_msglevel           = tg3_get_msglevel,
11234         .set_msglevel           = tg3_set_msglevel,
11235         .nway_reset             = tg3_nway_reset,
11236         .get_link               = ethtool_op_get_link,
11237         .get_eeprom_len         = tg3_get_eeprom_len,
11238         .get_eeprom             = tg3_get_eeprom,
11239         .set_eeprom             = tg3_set_eeprom,
11240         .get_ringparam          = tg3_get_ringparam,
11241         .set_ringparam          = tg3_set_ringparam,
11242         .get_pauseparam         = tg3_get_pauseparam,
11243         .set_pauseparam         = tg3_set_pauseparam,
11244         .get_rx_csum            = tg3_get_rx_csum,
11245         .set_rx_csum            = tg3_set_rx_csum,
11246         .set_tx_csum            = tg3_set_tx_csum,
11247         .set_sg                 = ethtool_op_set_sg,
11248         .set_tso                = tg3_set_tso,
11249         .self_test              = tg3_self_test,
11250         .get_strings            = tg3_get_strings,
11251         .phys_id                = tg3_phys_id,
11252         .get_ethtool_stats      = tg3_get_ethtool_stats,
11253         .get_coalesce           = tg3_get_coalesce,
11254         .set_coalesce           = tg3_set_coalesce,
11255         .get_sset_count         = tg3_get_sset_count,
11256 };
11257
11258 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11259 {
11260         u32 cursize, val, magic;
11261
11262         tp->nvram_size = EEPROM_CHIP_SIZE;
11263
11264         if (tg3_nvram_read(tp, 0, &magic) != 0)
11265                 return;
11266
11267         if ((magic != TG3_EEPROM_MAGIC) &&
11268             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11269             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11270                 return;
11271
11272         /*
11273          * Size the chip by reading offsets at increasing powers of two.
11274          * When we encounter our validation signature, we know the addressing
11275          * has wrapped around, and thus have our chip size.
11276          */
11277         cursize = 0x10;
11278
11279         while (cursize < tp->nvram_size) {
11280                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11281                         return;
11282
11283                 if (val == magic)
11284                         break;
11285
11286                 cursize <<= 1;
11287         }
11288
11289         tp->nvram_size = cursize;
11290 }
11291
11292 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11293 {
11294         u32 val;
11295
11296         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11297             tg3_nvram_read(tp, 0, &val) != 0)
11298                 return;
11299
11300         /* Selfboot format */
11301         if (val != TG3_EEPROM_MAGIC) {
11302                 tg3_get_eeprom_size(tp);
11303                 return;
11304         }
11305
11306         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11307                 if (val != 0) {
11308                         /* This is confusing.  We want to operate on the
11309                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11310                          * call will read from NVRAM and byteswap the data
11311                          * according to the byteswapping settings for all
11312                          * other register accesses.  This ensures the data we
11313                          * want will always reside in the lower 16-bits.
11314                          * However, the data in NVRAM is in LE format, which
11315                          * means the data from the NVRAM read will always be
11316                          * opposite the endianness of the CPU.  The 16-bit
11317                          * byteswap then brings the data to CPU endianness.
11318                          */
11319                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11320                         return;
11321                 }
11322         }
11323         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11324 }
11325
11326 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11327 {
11328         u32 nvcfg1;
11329
11330         nvcfg1 = tr32(NVRAM_CFG1);
11331         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11332                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11333         } else {
11334                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11335                 tw32(NVRAM_CFG1, nvcfg1);
11336         }
11337
11338         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11339             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11340                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11341                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11342                         tp->nvram_jedecnum = JEDEC_ATMEL;
11343                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11344                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11345                         break;
11346                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11347                         tp->nvram_jedecnum = JEDEC_ATMEL;
11348                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11349                         break;
11350                 case FLASH_VENDOR_ATMEL_EEPROM:
11351                         tp->nvram_jedecnum = JEDEC_ATMEL;
11352                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11353                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11354                         break;
11355                 case FLASH_VENDOR_ST:
11356                         tp->nvram_jedecnum = JEDEC_ST;
11357                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11358                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11359                         break;
11360                 case FLASH_VENDOR_SAIFUN:
11361                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11362                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11363                         break;
11364                 case FLASH_VENDOR_SST_SMALL:
11365                 case FLASH_VENDOR_SST_LARGE:
11366                         tp->nvram_jedecnum = JEDEC_SST;
11367                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11368                         break;
11369                 }
11370         } else {
11371                 tp->nvram_jedecnum = JEDEC_ATMEL;
11372                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11373                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11374         }
11375 }
11376
11377 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11378 {
11379         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11380         case FLASH_5752PAGE_SIZE_256:
11381                 tp->nvram_pagesize = 256;
11382                 break;
11383         case FLASH_5752PAGE_SIZE_512:
11384                 tp->nvram_pagesize = 512;
11385                 break;
11386         case FLASH_5752PAGE_SIZE_1K:
11387                 tp->nvram_pagesize = 1024;
11388                 break;
11389         case FLASH_5752PAGE_SIZE_2K:
11390                 tp->nvram_pagesize = 2048;
11391                 break;
11392         case FLASH_5752PAGE_SIZE_4K:
11393                 tp->nvram_pagesize = 4096;
11394                 break;
11395         case FLASH_5752PAGE_SIZE_264:
11396                 tp->nvram_pagesize = 264;
11397                 break;
11398         case FLASH_5752PAGE_SIZE_528:
11399                 tp->nvram_pagesize = 528;
11400                 break;
11401         }
11402 }
11403
11404 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11405 {
11406         u32 nvcfg1;
11407
11408         nvcfg1 = tr32(NVRAM_CFG1);
11409
11410         /* NVRAM protection for TPM */
11411         if (nvcfg1 & (1 << 27))
11412                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11413
11414         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11415         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11416         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11417                 tp->nvram_jedecnum = JEDEC_ATMEL;
11418                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11419                 break;
11420         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11421                 tp->nvram_jedecnum = JEDEC_ATMEL;
11422                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11423                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11424                 break;
11425         case FLASH_5752VENDOR_ST_M45PE10:
11426         case FLASH_5752VENDOR_ST_M45PE20:
11427         case FLASH_5752VENDOR_ST_M45PE40:
11428                 tp->nvram_jedecnum = JEDEC_ST;
11429                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11430                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11431                 break;
11432         }
11433
11434         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11435                 tg3_nvram_get_pagesize(tp, nvcfg1);
11436         } else {
11437                 /* For eeprom, set pagesize to maximum eeprom size */
11438                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11439
11440                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11441                 tw32(NVRAM_CFG1, nvcfg1);
11442         }
11443 }
11444
11445 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11446 {
11447         u32 nvcfg1, protect = 0;
11448
11449         nvcfg1 = tr32(NVRAM_CFG1);
11450
11451         /* NVRAM protection for TPM */
11452         if (nvcfg1 & (1 << 27)) {
11453                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11454                 protect = 1;
11455         }
11456
11457         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11458         switch (nvcfg1) {
11459         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11460         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11461         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11462         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11463                 tp->nvram_jedecnum = JEDEC_ATMEL;
11464                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11465                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11466                 tp->nvram_pagesize = 264;
11467                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11468                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11469                         tp->nvram_size = (protect ? 0x3e200 :
11470                                           TG3_NVRAM_SIZE_512KB);
11471                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11472                         tp->nvram_size = (protect ? 0x1f200 :
11473                                           TG3_NVRAM_SIZE_256KB);
11474                 else
11475                         tp->nvram_size = (protect ? 0x1f200 :
11476                                           TG3_NVRAM_SIZE_128KB);
11477                 break;
11478         case FLASH_5752VENDOR_ST_M45PE10:
11479         case FLASH_5752VENDOR_ST_M45PE20:
11480         case FLASH_5752VENDOR_ST_M45PE40:
11481                 tp->nvram_jedecnum = JEDEC_ST;
11482                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11483                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11484                 tp->nvram_pagesize = 256;
11485                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11486                         tp->nvram_size = (protect ?
11487                                           TG3_NVRAM_SIZE_64KB :
11488                                           TG3_NVRAM_SIZE_128KB);
11489                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11490                         tp->nvram_size = (protect ?
11491                                           TG3_NVRAM_SIZE_64KB :
11492                                           TG3_NVRAM_SIZE_256KB);
11493                 else
11494                         tp->nvram_size = (protect ?
11495                                           TG3_NVRAM_SIZE_128KB :
11496                                           TG3_NVRAM_SIZE_512KB);
11497                 break;
11498         }
11499 }
11500
11501 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11502 {
11503         u32 nvcfg1;
11504
11505         nvcfg1 = tr32(NVRAM_CFG1);
11506
11507         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11508         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11509         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11510         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11511         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11512                 tp->nvram_jedecnum = JEDEC_ATMEL;
11513                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11514                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11515
11516                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11517                 tw32(NVRAM_CFG1, nvcfg1);
11518                 break;
11519         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11520         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11521         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11522         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11523                 tp->nvram_jedecnum = JEDEC_ATMEL;
11524                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11525                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11526                 tp->nvram_pagesize = 264;
11527                 break;
11528         case FLASH_5752VENDOR_ST_M45PE10:
11529         case FLASH_5752VENDOR_ST_M45PE20:
11530         case FLASH_5752VENDOR_ST_M45PE40:
11531                 tp->nvram_jedecnum = JEDEC_ST;
11532                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11533                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11534                 tp->nvram_pagesize = 256;
11535                 break;
11536         }
11537 }
11538
11539 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11540 {
11541         u32 nvcfg1, protect = 0;
11542
11543         nvcfg1 = tr32(NVRAM_CFG1);
11544
11545         /* NVRAM protection for TPM */
11546         if (nvcfg1 & (1 << 27)) {
11547                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11548                 protect = 1;
11549         }
11550
11551         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11552         switch (nvcfg1) {
11553         case FLASH_5761VENDOR_ATMEL_ADB021D:
11554         case FLASH_5761VENDOR_ATMEL_ADB041D:
11555         case FLASH_5761VENDOR_ATMEL_ADB081D:
11556         case FLASH_5761VENDOR_ATMEL_ADB161D:
11557         case FLASH_5761VENDOR_ATMEL_MDB021D:
11558         case FLASH_5761VENDOR_ATMEL_MDB041D:
11559         case FLASH_5761VENDOR_ATMEL_MDB081D:
11560         case FLASH_5761VENDOR_ATMEL_MDB161D:
11561                 tp->nvram_jedecnum = JEDEC_ATMEL;
11562                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11563                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11564                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11565                 tp->nvram_pagesize = 256;
11566                 break;
11567         case FLASH_5761VENDOR_ST_A_M45PE20:
11568         case FLASH_5761VENDOR_ST_A_M45PE40:
11569         case FLASH_5761VENDOR_ST_A_M45PE80:
11570         case FLASH_5761VENDOR_ST_A_M45PE16:
11571         case FLASH_5761VENDOR_ST_M_M45PE20:
11572         case FLASH_5761VENDOR_ST_M_M45PE40:
11573         case FLASH_5761VENDOR_ST_M_M45PE80:
11574         case FLASH_5761VENDOR_ST_M_M45PE16:
11575                 tp->nvram_jedecnum = JEDEC_ST;
11576                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11577                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11578                 tp->nvram_pagesize = 256;
11579                 break;
11580         }
11581
11582         if (protect) {
11583                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11584         } else {
11585                 switch (nvcfg1) {
11586                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11587                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11588                 case FLASH_5761VENDOR_ST_A_M45PE16:
11589                 case FLASH_5761VENDOR_ST_M_M45PE16:
11590                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11591                         break;
11592                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11593                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11594                 case FLASH_5761VENDOR_ST_A_M45PE80:
11595                 case FLASH_5761VENDOR_ST_M_M45PE80:
11596                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11597                         break;
11598                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11599                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11600                 case FLASH_5761VENDOR_ST_A_M45PE40:
11601                 case FLASH_5761VENDOR_ST_M_M45PE40:
11602                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11603                         break;
11604                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11605                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11606                 case FLASH_5761VENDOR_ST_A_M45PE20:
11607                 case FLASH_5761VENDOR_ST_M_M45PE20:
11608                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11609                         break;
11610                 }
11611         }
11612 }
11613
11614 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11615 {
11616         tp->nvram_jedecnum = JEDEC_ATMEL;
11617         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11618         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11619 }
11620
11621 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11622 {
11623         u32 nvcfg1;
11624
11625         nvcfg1 = tr32(NVRAM_CFG1);
11626
11627         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11628         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11629         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11630                 tp->nvram_jedecnum = JEDEC_ATMEL;
11631                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11632                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11633
11634                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11635                 tw32(NVRAM_CFG1, nvcfg1);
11636                 return;
11637         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11638         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11639         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11640         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11641         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11642         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11643         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11644                 tp->nvram_jedecnum = JEDEC_ATMEL;
11645                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11646                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11647
11648                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11649                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11650                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11651                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11652                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11653                         break;
11654                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11655                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11656                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11657                         break;
11658                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11659                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11660                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11661                         break;
11662                 }
11663                 break;
11664         case FLASH_5752VENDOR_ST_M45PE10:
11665         case FLASH_5752VENDOR_ST_M45PE20:
11666         case FLASH_5752VENDOR_ST_M45PE40:
11667                 tp->nvram_jedecnum = JEDEC_ST;
11668                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11669                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11670
11671                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11672                 case FLASH_5752VENDOR_ST_M45PE10:
11673                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11674                         break;
11675                 case FLASH_5752VENDOR_ST_M45PE20:
11676                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11677                         break;
11678                 case FLASH_5752VENDOR_ST_M45PE40:
11679                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11680                         break;
11681                 }
11682                 break;
11683         default:
11684                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11685                 return;
11686         }
11687
11688         tg3_nvram_get_pagesize(tp, nvcfg1);
11689         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11690                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11691 }
11692
11693
11694 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11695 {
11696         u32 nvcfg1;
11697
11698         nvcfg1 = tr32(NVRAM_CFG1);
11699
11700         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11701         case FLASH_5717VENDOR_ATMEL_EEPROM:
11702         case FLASH_5717VENDOR_MICRO_EEPROM:
11703                 tp->nvram_jedecnum = JEDEC_ATMEL;
11704                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11705                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11706
11707                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11708                 tw32(NVRAM_CFG1, nvcfg1);
11709                 return;
11710         case FLASH_5717VENDOR_ATMEL_MDB011D:
11711         case FLASH_5717VENDOR_ATMEL_ADB011B:
11712         case FLASH_5717VENDOR_ATMEL_ADB011D:
11713         case FLASH_5717VENDOR_ATMEL_MDB021D:
11714         case FLASH_5717VENDOR_ATMEL_ADB021B:
11715         case FLASH_5717VENDOR_ATMEL_ADB021D:
11716         case FLASH_5717VENDOR_ATMEL_45USPT:
11717                 tp->nvram_jedecnum = JEDEC_ATMEL;
11718                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11719                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11720
11721                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11722                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11723                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11724                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11725                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11726                         break;
11727                 default:
11728                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11729                         break;
11730                 }
11731                 break;
11732         case FLASH_5717VENDOR_ST_M_M25PE10:
11733         case FLASH_5717VENDOR_ST_A_M25PE10:
11734         case FLASH_5717VENDOR_ST_M_M45PE10:
11735         case FLASH_5717VENDOR_ST_A_M45PE10:
11736         case FLASH_5717VENDOR_ST_M_M25PE20:
11737         case FLASH_5717VENDOR_ST_A_M25PE20:
11738         case FLASH_5717VENDOR_ST_M_M45PE20:
11739         case FLASH_5717VENDOR_ST_A_M45PE20:
11740         case FLASH_5717VENDOR_ST_25USPT:
11741         case FLASH_5717VENDOR_ST_45USPT:
11742                 tp->nvram_jedecnum = JEDEC_ST;
11743                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11744                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11745
11746                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11747                 case FLASH_5717VENDOR_ST_M_M25PE20:
11748                 case FLASH_5717VENDOR_ST_A_M25PE20:
11749                 case FLASH_5717VENDOR_ST_M_M45PE20:
11750                 case FLASH_5717VENDOR_ST_A_M45PE20:
11751                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11752                         break;
11753                 default:
11754                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11755                         break;
11756                 }
11757                 break;
11758         default:
11759                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11760                 return;
11761         }
11762
11763         tg3_nvram_get_pagesize(tp, nvcfg1);
11764         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11765                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11766 }
11767
11768 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11769 static void __devinit tg3_nvram_init(struct tg3 *tp)
11770 {
11771         tw32_f(GRC_EEPROM_ADDR,
11772              (EEPROM_ADDR_FSM_RESET |
11773               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11774                EEPROM_ADDR_CLKPERD_SHIFT)));
11775
11776         msleep(1);
11777
11778         /* Enable seeprom accesses. */
11779         tw32_f(GRC_LOCAL_CTRL,
11780              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11781         udelay(100);
11782
11783         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11784             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11785                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11786
11787                 if (tg3_nvram_lock(tp)) {
11788                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11789                                "tg3_nvram_init failed.\n", tp->dev->name);
11790                         return;
11791                 }
11792                 tg3_enable_nvram_access(tp);
11793
11794                 tp->nvram_size = 0;
11795
11796                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11797                         tg3_get_5752_nvram_info(tp);
11798                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11799                         tg3_get_5755_nvram_info(tp);
11800                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11801                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11802                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11803                         tg3_get_5787_nvram_info(tp);
11804                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11805                         tg3_get_5761_nvram_info(tp);
11806                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11807                         tg3_get_5906_nvram_info(tp);
11808                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11809                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11810                         tg3_get_57780_nvram_info(tp);
11811                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11812                         tg3_get_5717_nvram_info(tp);
11813                 else
11814                         tg3_get_nvram_info(tp);
11815
11816                 if (tp->nvram_size == 0)
11817                         tg3_get_nvram_size(tp);
11818
11819                 tg3_disable_nvram_access(tp);
11820                 tg3_nvram_unlock(tp);
11821
11822         } else {
11823                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11824
11825                 tg3_get_eeprom_size(tp);
11826         }
11827 }
11828
11829 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11830                                     u32 offset, u32 len, u8 *buf)
11831 {
11832         int i, j, rc = 0;
11833         u32 val;
11834
11835         for (i = 0; i < len; i += 4) {
11836                 u32 addr;
11837                 __be32 data;
11838
11839                 addr = offset + i;
11840
11841                 memcpy(&data, buf + i, 4);
11842
11843                 /*
11844                  * The SEEPROM interface expects the data to always be opposite
11845                  * the native endian format.  We accomplish this by reversing
11846                  * all the operations that would have been performed on the
11847                  * data from a call to tg3_nvram_read_be32().
11848                  */
11849                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11850
11851                 val = tr32(GRC_EEPROM_ADDR);
11852                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11853
11854                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11855                         EEPROM_ADDR_READ);
11856                 tw32(GRC_EEPROM_ADDR, val |
11857                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11858                         (addr & EEPROM_ADDR_ADDR_MASK) |
11859                         EEPROM_ADDR_START |
11860                         EEPROM_ADDR_WRITE);
11861
11862                 for (j = 0; j < 1000; j++) {
11863                         val = tr32(GRC_EEPROM_ADDR);
11864
11865                         if (val & EEPROM_ADDR_COMPLETE)
11866                                 break;
11867                         msleep(1);
11868                 }
11869                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11870                         rc = -EBUSY;
11871                         break;
11872                 }
11873         }
11874
11875         return rc;
11876 }
11877
11878 /* offset and length are dword aligned */
11879 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11880                 u8 *buf)
11881 {
11882         int ret = 0;
11883         u32 pagesize = tp->nvram_pagesize;
11884         u32 pagemask = pagesize - 1;
11885         u32 nvram_cmd;
11886         u8 *tmp;
11887
11888         tmp = kmalloc(pagesize, GFP_KERNEL);
11889         if (tmp == NULL)
11890                 return -ENOMEM;
11891
11892         while (len) {
11893                 int j;
11894                 u32 phy_addr, page_off, size;
11895
11896                 phy_addr = offset & ~pagemask;
11897
11898                 for (j = 0; j < pagesize; j += 4) {
11899                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11900                                                   (__be32 *) (tmp + j));
11901                         if (ret)
11902                                 break;
11903                 }
11904                 if (ret)
11905                         break;
11906
11907                 page_off = offset & pagemask;
11908                 size = pagesize;
11909                 if (len < size)
11910                         size = len;
11911
11912                 len -= size;
11913
11914                 memcpy(tmp + page_off, buf, size);
11915
11916                 offset = offset + (pagesize - page_off);
11917
11918                 tg3_enable_nvram_access(tp);
11919
11920                 /*
11921                  * Before we can erase the flash page, we need
11922                  * to issue a special "write enable" command.
11923                  */
11924                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11925
11926                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11927                         break;
11928
11929                 /* Erase the target page */
11930                 tw32(NVRAM_ADDR, phy_addr);
11931
11932                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11933                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11934
11935                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11936                         break;
11937
11938                 /* Issue another write enable to start the write. */
11939                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11940
11941                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11942                         break;
11943
11944                 for (j = 0; j < pagesize; j += 4) {
11945                         __be32 data;
11946
11947                         data = *((__be32 *) (tmp + j));
11948
11949                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11950
11951                         tw32(NVRAM_ADDR, phy_addr + j);
11952
11953                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11954                                 NVRAM_CMD_WR;
11955
11956                         if (j == 0)
11957                                 nvram_cmd |= NVRAM_CMD_FIRST;
11958                         else if (j == (pagesize - 4))
11959                                 nvram_cmd |= NVRAM_CMD_LAST;
11960
11961                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11962                                 break;
11963                 }
11964                 if (ret)
11965                         break;
11966         }
11967
11968         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11969         tg3_nvram_exec_cmd(tp, nvram_cmd);
11970
11971         kfree(tmp);
11972
11973         return ret;
11974 }
11975
11976 /* offset and length are dword aligned */
11977 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11978                 u8 *buf)
11979 {
11980         int i, ret = 0;
11981
11982         for (i = 0; i < len; i += 4, offset += 4) {
11983                 u32 page_off, phy_addr, nvram_cmd;
11984                 __be32 data;
11985
11986                 memcpy(&data, buf + i, 4);
11987                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11988
11989                 page_off = offset % tp->nvram_pagesize;
11990
11991                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11992
11993                 tw32(NVRAM_ADDR, phy_addr);
11994
11995                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11996
11997                 if ((page_off == 0) || (i == 0))
11998                         nvram_cmd |= NVRAM_CMD_FIRST;
11999                 if (page_off == (tp->nvram_pagesize - 4))
12000                         nvram_cmd |= NVRAM_CMD_LAST;
12001
12002                 if (i == (len - 4))
12003                         nvram_cmd |= NVRAM_CMD_LAST;
12004
12005                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12006                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12007                     (tp->nvram_jedecnum == JEDEC_ST) &&
12008                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12009
12010                         if ((ret = tg3_nvram_exec_cmd(tp,
12011                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12012                                 NVRAM_CMD_DONE)))
12013
12014                                 break;
12015                 }
12016                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12017                         /* We always do complete word writes to eeprom. */
12018                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12019                 }
12020
12021                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12022                         break;
12023         }
12024         return ret;
12025 }
12026
12027 /* offset and length are dword aligned */
12028 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12029 {
12030         int ret;
12031
12032         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12033                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12034                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12035                 udelay(40);
12036         }
12037
12038         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12039                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12040         }
12041         else {
12042                 u32 grc_mode;
12043
12044                 ret = tg3_nvram_lock(tp);
12045                 if (ret)
12046                         return ret;
12047
12048                 tg3_enable_nvram_access(tp);
12049                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12050                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12051                         tw32(NVRAM_WRITE1, 0x406);
12052
12053                 grc_mode = tr32(GRC_MODE);
12054                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12055
12056                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12057                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12058
12059                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12060                                 buf);
12061                 }
12062                 else {
12063                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12064                                 buf);
12065                 }
12066
12067                 grc_mode = tr32(GRC_MODE);
12068                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12069
12070                 tg3_disable_nvram_access(tp);
12071                 tg3_nvram_unlock(tp);
12072         }
12073
12074         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12075                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12076                 udelay(40);
12077         }
12078
12079         return ret;
12080 }
12081
12082 struct subsys_tbl_ent {
12083         u16 subsys_vendor, subsys_devid;
12084         u32 phy_id;
12085 };
12086
12087 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12088         /* Broadcom boards. */
12089         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12090         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12091         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12092         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
12093         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12094         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12095         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
12096         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12097         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12098         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12099         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12100
12101         /* 3com boards. */
12102         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12103         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12104         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
12105         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12106         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12107
12108         /* DELL boards. */
12109         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12110         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12111         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12112         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12113
12114         /* Compaq boards. */
12115         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12116         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12117         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
12118         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12119         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12120
12121         /* IBM boards. */
12122         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12123 };
12124
12125 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12126 {
12127         int i;
12128
12129         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12130                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12131                      tp->pdev->subsystem_vendor) &&
12132                     (subsys_id_to_phy_id[i].subsys_devid ==
12133                      tp->pdev->subsystem_device))
12134                         return &subsys_id_to_phy_id[i];
12135         }
12136         return NULL;
12137 }
12138
12139 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12140 {
12141         u32 val;
12142         u16 pmcsr;
12143
12144         /* On some early chips the SRAM cannot be accessed in D3hot state,
12145          * so need make sure we're in D0.
12146          */
12147         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12148         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12149         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12150         msleep(1);
12151
12152         /* Make sure register accesses (indirect or otherwise)
12153          * will function correctly.
12154          */
12155         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12156                                tp->misc_host_ctrl);
12157
12158         /* The memory arbiter has to be enabled in order for SRAM accesses
12159          * to succeed.  Normally on powerup the tg3 chip firmware will make
12160          * sure it is enabled, but other entities such as system netboot
12161          * code might disable it.
12162          */
12163         val = tr32(MEMARB_MODE);
12164         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12165
12166         tp->phy_id = PHY_ID_INVALID;
12167         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12168
12169         /* Assume an onboard device and WOL capable by default.  */
12170         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12171
12172         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12173                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12174                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12175                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12176                 }
12177                 val = tr32(VCPU_CFGSHDW);
12178                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12179                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12180                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12181                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12182                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12183                 goto done;
12184         }
12185
12186         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12187         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12188                 u32 nic_cfg, led_cfg;
12189                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12190                 int eeprom_phy_serdes = 0;
12191
12192                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12193                 tp->nic_sram_data_cfg = nic_cfg;
12194
12195                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12196                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12197                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12198                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12199                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12200                     (ver > 0) && (ver < 0x100))
12201                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12202
12203                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12204                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12205
12206                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12207                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12208                         eeprom_phy_serdes = 1;
12209
12210                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12211                 if (nic_phy_id != 0) {
12212                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12213                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12214
12215                         eeprom_phy_id  = (id1 >> 16) << 10;
12216                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12217                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12218                 } else
12219                         eeprom_phy_id = 0;
12220
12221                 tp->phy_id = eeprom_phy_id;
12222                 if (eeprom_phy_serdes) {
12223                         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12224                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12225                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12226                         else
12227                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12228                 }
12229
12230                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12231                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12232                                     SHASTA_EXT_LED_MODE_MASK);
12233                 else
12234                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12235
12236                 switch (led_cfg) {
12237                 default:
12238                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12239                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12240                         break;
12241
12242                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12243                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12244                         break;
12245
12246                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12247                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12248
12249                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12250                          * read on some older 5700/5701 bootcode.
12251                          */
12252                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12253                             ASIC_REV_5700 ||
12254                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12255                             ASIC_REV_5701)
12256                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12257
12258                         break;
12259
12260                 case SHASTA_EXT_LED_SHARED:
12261                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12262                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12263                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12264                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12265                                                  LED_CTRL_MODE_PHY_2);
12266                         break;
12267
12268                 case SHASTA_EXT_LED_MAC:
12269                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12270                         break;
12271
12272                 case SHASTA_EXT_LED_COMBO:
12273                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12274                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12275                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12276                                                  LED_CTRL_MODE_PHY_2);
12277                         break;
12278
12279                 }
12280
12281                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12282                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12283                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12284                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12285
12286                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12287                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12288
12289                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12290                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12291                         if ((tp->pdev->subsystem_vendor ==
12292                              PCI_VENDOR_ID_ARIMA) &&
12293                             (tp->pdev->subsystem_device == 0x205a ||
12294                              tp->pdev->subsystem_device == 0x2063))
12295                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12296                 } else {
12297                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12298                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12299                 }
12300
12301                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12302                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12303                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12304                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12305                 }
12306
12307                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12308                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12309                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12310
12311                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12312                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12313                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12314
12315                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12316                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12317                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12318
12319                 if (cfg2 & (1 << 17))
12320                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12321
12322                 /* serdes signal pre-emphasis in register 0x590 set by */
12323                 /* bootcode if bit 18 is set */
12324                 if (cfg2 & (1 << 18))
12325                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12326
12327                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12328                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12329                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12330                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12331
12332                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12333                         u32 cfg3;
12334
12335                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12336                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12337                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12338                 }
12339
12340                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12341                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12342                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12343                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12344                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12345                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12346         }
12347 done:
12348         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12349         device_set_wakeup_enable(&tp->pdev->dev,
12350                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12351 }
12352
12353 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12354 {
12355         int i;
12356         u32 val;
12357
12358         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12359         tw32(OTP_CTRL, cmd);
12360
12361         /* Wait for up to 1 ms for command to execute. */
12362         for (i = 0; i < 100; i++) {
12363                 val = tr32(OTP_STATUS);
12364                 if (val & OTP_STATUS_CMD_DONE)
12365                         break;
12366                 udelay(10);
12367         }
12368
12369         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12370 }
12371
12372 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12373  * configuration is a 32-bit value that straddles the alignment boundary.
12374  * We do two 32-bit reads and then shift and merge the results.
12375  */
12376 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12377 {
12378         u32 bhalf_otp, thalf_otp;
12379
12380         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12381
12382         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12383                 return 0;
12384
12385         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12386
12387         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12388                 return 0;
12389
12390         thalf_otp = tr32(OTP_READ_DATA);
12391
12392         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12393
12394         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12395                 return 0;
12396
12397         bhalf_otp = tr32(OTP_READ_DATA);
12398
12399         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12400 }
12401
12402 static int __devinit tg3_phy_probe(struct tg3 *tp)
12403 {
12404         u32 hw_phy_id_1, hw_phy_id_2;
12405         u32 hw_phy_id, hw_phy_id_masked;
12406         int err;
12407
12408         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12409                 return tg3_phy_init(tp);
12410
12411         /* Reading the PHY ID register can conflict with ASF
12412          * firmware access to the PHY hardware.
12413          */
12414         err = 0;
12415         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12416             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12417                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12418         } else {
12419                 /* Now read the physical PHY_ID from the chip and verify
12420                  * that it is sane.  If it doesn't look good, we fall back
12421                  * to either the hard-coded table based PHY_ID and failing
12422                  * that the value found in the eeprom area.
12423                  */
12424                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12425                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12426
12427                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12428                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12429                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12430
12431                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12432         }
12433
12434         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12435                 tp->phy_id = hw_phy_id;
12436                 if (hw_phy_id_masked == PHY_ID_BCM8002)
12437                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12438                 else
12439                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12440         } else {
12441                 if (tp->phy_id != PHY_ID_INVALID) {
12442                         /* Do nothing, phy ID already set up in
12443                          * tg3_get_eeprom_hw_cfg().
12444                          */
12445                 } else {
12446                         struct subsys_tbl_ent *p;
12447
12448                         /* No eeprom signature?  Try the hardcoded
12449                          * subsys device table.
12450                          */
12451                         p = lookup_by_subsys(tp);
12452                         if (!p)
12453                                 return -ENODEV;
12454
12455                         tp->phy_id = p->phy_id;
12456                         if (!tp->phy_id ||
12457                             tp->phy_id == PHY_ID_BCM8002)
12458                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12459                 }
12460         }
12461
12462         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12463             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12464             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12465                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12466
12467                 tg3_readphy(tp, MII_BMSR, &bmsr);
12468                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12469                     (bmsr & BMSR_LSTATUS))
12470                         goto skip_phy_reset;
12471
12472                 err = tg3_phy_reset(tp);
12473                 if (err)
12474                         return err;
12475
12476                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12477                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12478                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12479                 tg3_ctrl = 0;
12480                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12481                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12482                                     MII_TG3_CTRL_ADV_1000_FULL);
12483                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12484                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12485                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12486                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12487                 }
12488
12489                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12490                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12491                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12492                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12493                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12494
12495                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12496                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12497
12498                         tg3_writephy(tp, MII_BMCR,
12499                                      BMCR_ANENABLE | BMCR_ANRESTART);
12500                 }
12501                 tg3_phy_set_wirespeed(tp);
12502
12503                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12504                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12505                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12506         }
12507
12508 skip_phy_reset:
12509         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12510                 err = tg3_init_5401phy_dsp(tp);
12511                 if (err)
12512                         return err;
12513         }
12514
12515         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12516                 err = tg3_init_5401phy_dsp(tp);
12517         }
12518
12519         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12520                 tp->link_config.advertising =
12521                         (ADVERTISED_1000baseT_Half |
12522                          ADVERTISED_1000baseT_Full |
12523                          ADVERTISED_Autoneg |
12524                          ADVERTISED_FIBRE);
12525         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12526                 tp->link_config.advertising &=
12527                         ~(ADVERTISED_1000baseT_Half |
12528                           ADVERTISED_1000baseT_Full);
12529
12530         return err;
12531 }
12532
12533 static void __devinit tg3_read_partno(struct tg3 *tp)
12534 {
12535         unsigned char vpd_data[TG3_NVM_VPD_LEN];   /* in little-endian format */
12536         unsigned int i;
12537         u32 magic;
12538
12539         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12540             tg3_nvram_read(tp, 0x0, &magic))
12541                 goto out_not_found;
12542
12543         if (magic == TG3_EEPROM_MAGIC) {
12544                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12545                         u32 tmp;
12546
12547                         /* The data is in little-endian format in NVRAM.
12548                          * Use the big-endian read routines to preserve
12549                          * the byte order as it exists in NVRAM.
12550                          */
12551                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12552                                 goto out_not_found;
12553
12554                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12555                 }
12556         } else {
12557                 ssize_t cnt;
12558                 unsigned int pos = 0, i = 0;
12559
12560                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12561                         cnt = pci_read_vpd(tp->pdev, pos,
12562                                            TG3_NVM_VPD_LEN - pos,
12563                                            &vpd_data[pos]);
12564                         if (cnt == -ETIMEDOUT || -EINTR)
12565                                 cnt = 0;
12566                         else if (cnt < 0)
12567                                 goto out_not_found;
12568                 }
12569                 if (pos != TG3_NVM_VPD_LEN)
12570                         goto out_not_found;
12571         }
12572
12573         /* Now parse and find the part number. */
12574         for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
12575                 unsigned char val = vpd_data[i];
12576                 unsigned int block_end;
12577
12578                 if (val == 0x82 || val == 0x91) {
12579                         i = (i + 3 +
12580                              (vpd_data[i + 1] +
12581                               (vpd_data[i + 2] << 8)));
12582                         continue;
12583                 }
12584
12585                 if (val != 0x90)
12586                         goto out_not_found;
12587
12588                 block_end = (i + 3 +
12589                              (vpd_data[i + 1] +
12590                               (vpd_data[i + 2] << 8)));
12591                 i += 3;
12592
12593                 if (block_end > TG3_NVM_VPD_LEN)
12594                         goto out_not_found;
12595
12596                 while (i < (block_end - 2)) {
12597                         if (vpd_data[i + 0] == 'P' &&
12598                             vpd_data[i + 1] == 'N') {
12599                                 int partno_len = vpd_data[i + 2];
12600
12601                                 i += 3;
12602                                 if (partno_len > TG3_BPN_SIZE ||
12603                                     (partno_len + i) > TG3_NVM_VPD_LEN)
12604                                         goto out_not_found;
12605
12606                                 memcpy(tp->board_part_number,
12607                                        &vpd_data[i], partno_len);
12608
12609                                 /* Success. */
12610                                 return;
12611                         }
12612                         i += 3 + vpd_data[i + 2];
12613                 }
12614
12615                 /* Part number not found. */
12616                 goto out_not_found;
12617         }
12618
12619 out_not_found:
12620         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12621                 strcpy(tp->board_part_number, "BCM95906");
12622         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12623                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12624                 strcpy(tp->board_part_number, "BCM57780");
12625         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12626                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12627                 strcpy(tp->board_part_number, "BCM57760");
12628         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12629                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12630                 strcpy(tp->board_part_number, "BCM57790");
12631         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12632                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12633                 strcpy(tp->board_part_number, "BCM57788");
12634         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12635                 strcpy(tp->board_part_number, "BCM57765");
12636         else
12637                 strcpy(tp->board_part_number, "none");
12638 }
12639
12640 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12641 {
12642         u32 val;
12643
12644         if (tg3_nvram_read(tp, offset, &val) ||
12645             (val & 0xfc000000) != 0x0c000000 ||
12646             tg3_nvram_read(tp, offset + 4, &val) ||
12647             val != 0)
12648                 return 0;
12649
12650         return 1;
12651 }
12652
12653 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12654 {
12655         u32 val, offset, start, ver_offset;
12656         int i;
12657         bool newver = false;
12658
12659         if (tg3_nvram_read(tp, 0xc, &offset) ||
12660             tg3_nvram_read(tp, 0x4, &start))
12661                 return;
12662
12663         offset = tg3_nvram_logical_addr(tp, offset);
12664
12665         if (tg3_nvram_read(tp, offset, &val))
12666                 return;
12667
12668         if ((val & 0xfc000000) == 0x0c000000) {
12669                 if (tg3_nvram_read(tp, offset + 4, &val))
12670                         return;
12671
12672                 if (val == 0)
12673                         newver = true;
12674         }
12675
12676         if (newver) {
12677                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12678                         return;
12679
12680                 offset = offset + ver_offset - start;
12681                 for (i = 0; i < 16; i += 4) {
12682                         __be32 v;
12683                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12684                                 return;
12685
12686                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12687                 }
12688         } else {
12689                 u32 major, minor;
12690
12691                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12692                         return;
12693
12694                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12695                         TG3_NVM_BCVER_MAJSFT;
12696                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12697                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12698         }
12699 }
12700
12701 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12702 {
12703         u32 val, major, minor;
12704
12705         /* Use native endian representation */
12706         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12707                 return;
12708
12709         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12710                 TG3_NVM_HWSB_CFG1_MAJSFT;
12711         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12712                 TG3_NVM_HWSB_CFG1_MINSFT;
12713
12714         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12715 }
12716
12717 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12718 {
12719         u32 offset, major, minor, build;
12720
12721         tp->fw_ver[0] = 's';
12722         tp->fw_ver[1] = 'b';
12723         tp->fw_ver[2] = '\0';
12724
12725         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12726                 return;
12727
12728         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12729         case TG3_EEPROM_SB_REVISION_0:
12730                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12731                 break;
12732         case TG3_EEPROM_SB_REVISION_2:
12733                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12734                 break;
12735         case TG3_EEPROM_SB_REVISION_3:
12736                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12737                 break;
12738         default:
12739                 return;
12740         }
12741
12742         if (tg3_nvram_read(tp, offset, &val))
12743                 return;
12744
12745         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12746                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12747         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12748                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12749         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12750
12751         if (minor > 99 || build > 26)
12752                 return;
12753
12754         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12755
12756         if (build > 0) {
12757                 tp->fw_ver[8] = 'a' + build - 1;
12758                 tp->fw_ver[9] = '\0';
12759         }
12760 }
12761
12762 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12763 {
12764         u32 val, offset, start;
12765         int i, vlen;
12766
12767         for (offset = TG3_NVM_DIR_START;
12768              offset < TG3_NVM_DIR_END;
12769              offset += TG3_NVM_DIRENT_SIZE) {
12770                 if (tg3_nvram_read(tp, offset, &val))
12771                         return;
12772
12773                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12774                         break;
12775         }
12776
12777         if (offset == TG3_NVM_DIR_END)
12778                 return;
12779
12780         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12781                 start = 0x08000000;
12782         else if (tg3_nvram_read(tp, offset - 4, &start))
12783                 return;
12784
12785         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12786             !tg3_fw_img_is_valid(tp, offset) ||
12787             tg3_nvram_read(tp, offset + 8, &val))
12788                 return;
12789
12790         offset += val - start;
12791
12792         vlen = strlen(tp->fw_ver);
12793
12794         tp->fw_ver[vlen++] = ',';
12795         tp->fw_ver[vlen++] = ' ';
12796
12797         for (i = 0; i < 4; i++) {
12798                 __be32 v;
12799                 if (tg3_nvram_read_be32(tp, offset, &v))
12800                         return;
12801
12802                 offset += sizeof(v);
12803
12804                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12805                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12806                         break;
12807                 }
12808
12809                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12810                 vlen += sizeof(v);
12811         }
12812 }
12813
12814 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12815 {
12816         int vlen;
12817         u32 apedata;
12818
12819         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12820             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12821                 return;
12822
12823         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12824         if (apedata != APE_SEG_SIG_MAGIC)
12825                 return;
12826
12827         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12828         if (!(apedata & APE_FW_STATUS_READY))
12829                 return;
12830
12831         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12832
12833         vlen = strlen(tp->fw_ver);
12834
12835         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12836                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12837                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12838                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12839                  (apedata & APE_FW_VERSION_BLDMSK));
12840 }
12841
12842 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12843 {
12844         u32 val;
12845
12846         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12847                 tp->fw_ver[0] = 's';
12848                 tp->fw_ver[1] = 'b';
12849                 tp->fw_ver[2] = '\0';
12850
12851                 return;
12852         }
12853
12854         if (tg3_nvram_read(tp, 0, &val))
12855                 return;
12856
12857         if (val == TG3_EEPROM_MAGIC)
12858                 tg3_read_bc_ver(tp);
12859         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12860                 tg3_read_sb_ver(tp, val);
12861         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12862                 tg3_read_hwsb_ver(tp);
12863         else
12864                 return;
12865
12866         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12867              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12868                 return;
12869
12870         tg3_read_mgmtfw_ver(tp);
12871
12872         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12873 }
12874
12875 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12876
12877 static int __devinit tg3_get_invariants(struct tg3 *tp)
12878 {
12879         static struct pci_device_id write_reorder_chipsets[] = {
12880                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12881                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12882                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12883                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12884                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12885                              PCI_DEVICE_ID_VIA_8385_0) },
12886                 { },
12887         };
12888         u32 misc_ctrl_reg;
12889         u32 pci_state_reg, grc_misc_cfg;
12890         u32 val;
12891         u16 pci_cmd;
12892         int err;
12893
12894         /* Force memory write invalidate off.  If we leave it on,
12895          * then on 5700_BX chips we have to enable a workaround.
12896          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12897          * to match the cacheline size.  The Broadcom driver have this
12898          * workaround but turns MWI off all the times so never uses
12899          * it.  This seems to suggest that the workaround is insufficient.
12900          */
12901         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12902         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12903         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12904
12905         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12906          * has the register indirect write enable bit set before
12907          * we try to access any of the MMIO registers.  It is also
12908          * critical that the PCI-X hw workaround situation is decided
12909          * before that as well.
12910          */
12911         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12912                               &misc_ctrl_reg);
12913
12914         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12915                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12916         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12917                 u32 prod_id_asic_rev;
12918
12919                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12920                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12921                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12922                         pci_read_config_dword(tp->pdev,
12923                                               TG3PCI_GEN2_PRODID_ASICREV,
12924                                               &prod_id_asic_rev);
12925                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12926                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12927                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12928                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12929                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12930                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12931                         pci_read_config_dword(tp->pdev,
12932                                               TG3PCI_GEN15_PRODID_ASICREV,
12933                                               &prod_id_asic_rev);
12934                 else
12935                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12936                                               &prod_id_asic_rev);
12937
12938                 tp->pci_chip_rev_id = prod_id_asic_rev;
12939         }
12940
12941         /* Wrong chip ID in 5752 A0. This code can be removed later
12942          * as A0 is not in production.
12943          */
12944         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12945                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12946
12947         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12948          * we need to disable memory and use config. cycles
12949          * only to access all registers. The 5702/03 chips
12950          * can mistakenly decode the special cycles from the
12951          * ICH chipsets as memory write cycles, causing corruption
12952          * of register and memory space. Only certain ICH bridges
12953          * will drive special cycles with non-zero data during the
12954          * address phase which can fall within the 5703's address
12955          * range. This is not an ICH bug as the PCI spec allows
12956          * non-zero address during special cycles. However, only
12957          * these ICH bridges are known to drive non-zero addresses
12958          * during special cycles.
12959          *
12960          * Since special cycles do not cross PCI bridges, we only
12961          * enable this workaround if the 5703 is on the secondary
12962          * bus of these ICH bridges.
12963          */
12964         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12965             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12966                 static struct tg3_dev_id {
12967                         u32     vendor;
12968                         u32     device;
12969                         u32     rev;
12970                 } ich_chipsets[] = {
12971                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12972                           PCI_ANY_ID },
12973                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12974                           PCI_ANY_ID },
12975                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12976                           0xa },
12977                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12978                           PCI_ANY_ID },
12979                         { },
12980                 };
12981                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12982                 struct pci_dev *bridge = NULL;
12983
12984                 while (pci_id->vendor != 0) {
12985                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12986                                                 bridge);
12987                         if (!bridge) {
12988                                 pci_id++;
12989                                 continue;
12990                         }
12991                         if (pci_id->rev != PCI_ANY_ID) {
12992                                 if (bridge->revision > pci_id->rev)
12993                                         continue;
12994                         }
12995                         if (bridge->subordinate &&
12996                             (bridge->subordinate->number ==
12997                              tp->pdev->bus->number)) {
12998
12999                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13000                                 pci_dev_put(bridge);
13001                                 break;
13002                         }
13003                 }
13004         }
13005
13006         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13007                 static struct tg3_dev_id {
13008                         u32     vendor;
13009                         u32     device;
13010                 } bridge_chipsets[] = {
13011                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13012                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13013                         { },
13014                 };
13015                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13016                 struct pci_dev *bridge = NULL;
13017
13018                 while (pci_id->vendor != 0) {
13019                         bridge = pci_get_device(pci_id->vendor,
13020                                                 pci_id->device,
13021                                                 bridge);
13022                         if (!bridge) {
13023                                 pci_id++;
13024                                 continue;
13025                         }
13026                         if (bridge->subordinate &&
13027                             (bridge->subordinate->number <=
13028                              tp->pdev->bus->number) &&
13029                             (bridge->subordinate->subordinate >=
13030                              tp->pdev->bus->number)) {
13031                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13032                                 pci_dev_put(bridge);
13033                                 break;
13034                         }
13035                 }
13036         }
13037
13038         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13039          * DMA addresses > 40-bit. This bridge may have other additional
13040          * 57xx devices behind it in some 4-port NIC designs for example.
13041          * Any tg3 device found behind the bridge will also need the 40-bit
13042          * DMA workaround.
13043          */
13044         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13046                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13047                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13048                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13049         }
13050         else {
13051                 struct pci_dev *bridge = NULL;
13052
13053                 do {
13054                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13055                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13056                                                 bridge);
13057                         if (bridge && bridge->subordinate &&
13058                             (bridge->subordinate->number <=
13059                              tp->pdev->bus->number) &&
13060                             (bridge->subordinate->subordinate >=
13061                              tp->pdev->bus->number)) {
13062                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13063                                 pci_dev_put(bridge);
13064                                 break;
13065                         }
13066                 } while (bridge);
13067         }
13068
13069         /* Initialize misc host control in PCI block. */
13070         tp->misc_host_ctrl |= (misc_ctrl_reg &
13071                                MISC_HOST_CTRL_CHIPREV);
13072         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13073                                tp->misc_host_ctrl);
13074
13075         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13076             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13077             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13078                 tp->pdev_peer = tg3_find_peer(tp);
13079
13080         /* Intentionally exclude ASIC_REV_5906 */
13081         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13082             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13083             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13084             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13085             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13086             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13087             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13088             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13089                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13090
13091         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13092             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13093             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13094             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13095             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13096                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13097
13098         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13099             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13100                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13101
13102         /* 5700 B0 chips do not support checksumming correctly due
13103          * to hardware bugs.
13104          */
13105         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13106                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13107         else {
13108                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13109                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13110                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13111                         tp->dev->features |= NETIF_F_IPV6_CSUM;
13112         }
13113
13114         /* Determine TSO capabilities */
13115         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13116             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13117                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13118         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13119                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13120                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13121         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13122                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13123                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13124                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13125                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13126         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13127                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13128                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13129                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13130                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13131                         tp->fw_needed = FIRMWARE_TG3TSO5;
13132                 else
13133                         tp->fw_needed = FIRMWARE_TG3TSO;
13134         }
13135
13136         tp->irq_max = 1;
13137
13138         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13139                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13140                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13141                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13142                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13143                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13144                      tp->pdev_peer == tp->pdev))
13145                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13146
13147                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13148                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13149                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13150                 }
13151
13152                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13153                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13154                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13155                         tp->irq_max = TG3_IRQ_MAX_VECS;
13156                 }
13157         }
13158
13159         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13160             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13161                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13162         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13163                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13164                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13165         }
13166
13167         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13168             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13169                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13170
13171         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13172              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13173                  (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13174                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13175
13176         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13177                               &pci_state_reg);
13178
13179         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13180         if (tp->pcie_cap != 0) {
13181                 u16 lnkctl;
13182
13183                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13184
13185                 pcie_set_readrq(tp->pdev, 4096);
13186
13187                 pci_read_config_word(tp->pdev,
13188                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13189                                      &lnkctl);
13190                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13191                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13192                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13193                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13194                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13195                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13196                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13197                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13198                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13199                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13200                 }
13201         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13202                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13203         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13204                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13205                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13206                 if (!tp->pcix_cap) {
13207                         printk(KERN_ERR PFX "Cannot find PCI-X "
13208                                             "capability, aborting.\n");
13209                         return -EIO;
13210                 }
13211
13212                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13213                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13214         }
13215
13216         /* If we have an AMD 762 or VIA K8T800 chipset, write
13217          * reordering to the mailbox registers done by the host
13218          * controller can cause major troubles.  We read back from
13219          * every mailbox register write to force the writes to be
13220          * posted to the chip in order.
13221          */
13222         if (pci_dev_present(write_reorder_chipsets) &&
13223             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13224                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13225
13226         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13227                              &tp->pci_cacheline_sz);
13228         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13229                              &tp->pci_lat_timer);
13230         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13231             tp->pci_lat_timer < 64) {
13232                 tp->pci_lat_timer = 64;
13233                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13234                                       tp->pci_lat_timer);
13235         }
13236
13237         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13238                 /* 5700 BX chips need to have their TX producer index
13239                  * mailboxes written twice to workaround a bug.
13240                  */
13241                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13242
13243                 /* If we are in PCI-X mode, enable register write workaround.
13244                  *
13245                  * The workaround is to use indirect register accesses
13246                  * for all chip writes not to mailbox registers.
13247                  */
13248                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13249                         u32 pm_reg;
13250
13251                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13252
13253                         /* The chip can have it's power management PCI config
13254                          * space registers clobbered due to this bug.
13255                          * So explicitly force the chip into D0 here.
13256                          */
13257                         pci_read_config_dword(tp->pdev,
13258                                               tp->pm_cap + PCI_PM_CTRL,
13259                                               &pm_reg);
13260                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13261                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13262                         pci_write_config_dword(tp->pdev,
13263                                                tp->pm_cap + PCI_PM_CTRL,
13264                                                pm_reg);
13265
13266                         /* Also, force SERR#/PERR# in PCI command. */
13267                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13268                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13269                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13270                 }
13271         }
13272
13273         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13274                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13275         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13276                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13277
13278         /* Chip-specific fixup from Broadcom driver */
13279         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13280             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13281                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13282                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13283         }
13284
13285         /* Default fast path register access methods */
13286         tp->read32 = tg3_read32;
13287         tp->write32 = tg3_write32;
13288         tp->read32_mbox = tg3_read32;
13289         tp->write32_mbox = tg3_write32;
13290         tp->write32_tx_mbox = tg3_write32;
13291         tp->write32_rx_mbox = tg3_write32;
13292
13293         /* Various workaround register access methods */
13294         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13295                 tp->write32 = tg3_write_indirect_reg32;
13296         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13297                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13298                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13299                 /*
13300                  * Back to back register writes can cause problems on these
13301                  * chips, the workaround is to read back all reg writes
13302                  * except those to mailbox regs.
13303                  *
13304                  * See tg3_write_indirect_reg32().
13305                  */
13306                 tp->write32 = tg3_write_flush_reg32;
13307         }
13308
13309         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13310             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13311                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13312                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13313                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13314         }
13315
13316         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13317                 tp->read32 = tg3_read_indirect_reg32;
13318                 tp->write32 = tg3_write_indirect_reg32;
13319                 tp->read32_mbox = tg3_read_indirect_mbox;
13320                 tp->write32_mbox = tg3_write_indirect_mbox;
13321                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13322                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13323
13324                 iounmap(tp->regs);
13325                 tp->regs = NULL;
13326
13327                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13328                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13329                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13330         }
13331         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13332                 tp->read32_mbox = tg3_read32_mbox_5906;
13333                 tp->write32_mbox = tg3_write32_mbox_5906;
13334                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13335                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13336         }
13337
13338         if (tp->write32 == tg3_write_indirect_reg32 ||
13339             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13340              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13341               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13342                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13343
13344         /* Get eeprom hw config before calling tg3_set_power_state().
13345          * In particular, the TG3_FLG2_IS_NIC flag must be
13346          * determined before calling tg3_set_power_state() so that
13347          * we know whether or not to switch out of Vaux power.
13348          * When the flag is set, it means that GPIO1 is used for eeprom
13349          * write protect and also implies that it is a LOM where GPIOs
13350          * are not used to switch power.
13351          */
13352         tg3_get_eeprom_hw_cfg(tp);
13353
13354         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13355                 /* Allow reads and writes to the
13356                  * APE register and memory space.
13357                  */
13358                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13359                                  PCISTATE_ALLOW_APE_SHMEM_WR;
13360                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13361                                        pci_state_reg);
13362         }
13363
13364         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13365             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13366             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13367             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13368             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13369             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13370                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13371
13372         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13373          * GPIO1 driven high will bring 5700's external PHY out of reset.
13374          * It is also used as eeprom write protect on LOMs.
13375          */
13376         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13377         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13378             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13379                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13380                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13381         /* Unused GPIO3 must be driven as output on 5752 because there
13382          * are no pull-up resistors on unused GPIO pins.
13383          */
13384         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13385                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13386
13387         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13388             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13389             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13390                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13391
13392         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13393             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13394                 /* Turn off the debug UART. */
13395                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13396                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13397                         /* Keep VMain power. */
13398                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13399                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13400         }
13401
13402         /* Force the chip into D0. */
13403         err = tg3_set_power_state(tp, PCI_D0);
13404         if (err) {
13405                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13406                        pci_name(tp->pdev));
13407                 return err;
13408         }
13409
13410         /* Derive initial jumbo mode from MTU assigned in
13411          * ether_setup() via the alloc_etherdev() call
13412          */
13413         if (tp->dev->mtu > ETH_DATA_LEN &&
13414             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13415                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13416
13417         /* Determine WakeOnLan speed to use. */
13418         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13419             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13420             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13421             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13422                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13423         } else {
13424                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13425         }
13426
13427         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13428                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13429
13430         /* A few boards don't want Ethernet@WireSpeed phy feature */
13431         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13432             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13433              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13434              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13435             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13436             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13437                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13438
13439         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13440             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13441                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13442         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13443                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13444
13445         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13446             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13447             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13448             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13449             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13450             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13451                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13452                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13453                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13454                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13455                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13456                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13457                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13458                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13459                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13460                 } else
13461                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13462         }
13463
13464         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13465             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13466                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13467                 if (tp->phy_otp == 0)
13468                         tp->phy_otp = TG3_OTP_DEFAULT;
13469         }
13470
13471         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13472                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13473         else
13474                 tp->mi_mode = MAC_MI_MODE_BASE;
13475
13476         tp->coalesce_mode = 0;
13477         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13478             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13479                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13480
13481         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13482             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13483                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13484
13485         err = tg3_mdio_init(tp);
13486         if (err)
13487                 return err;
13488
13489         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13490             (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13491                  (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13492                 return -ENOTSUPP;
13493
13494         /* Initialize data/descriptor byte/word swapping. */
13495         val = tr32(GRC_MODE);
13496         val &= GRC_MODE_HOST_STACKUP;
13497         tw32(GRC_MODE, val | tp->grc_mode);
13498
13499         tg3_switch_clocks(tp);
13500
13501         /* Clear this out for sanity. */
13502         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13503
13504         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13505                               &pci_state_reg);
13506         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13507             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13508                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13509
13510                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13511                     chiprevid == CHIPREV_ID_5701_B0 ||
13512                     chiprevid == CHIPREV_ID_5701_B2 ||
13513                     chiprevid == CHIPREV_ID_5701_B5) {
13514                         void __iomem *sram_base;
13515
13516                         /* Write some dummy words into the SRAM status block
13517                          * area, see if it reads back correctly.  If the return
13518                          * value is bad, force enable the PCIX workaround.
13519                          */
13520                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13521
13522                         writel(0x00000000, sram_base);
13523                         writel(0x00000000, sram_base + 4);
13524                         writel(0xffffffff, sram_base + 4);
13525                         if (readl(sram_base) != 0x00000000)
13526                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13527                 }
13528         }
13529
13530         udelay(50);
13531         tg3_nvram_init(tp);
13532
13533         grc_misc_cfg = tr32(GRC_MISC_CFG);
13534         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13535
13536         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13537             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13538              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13539                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13540
13541         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13542             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13543                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13544         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13545                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13546                                       HOSTCC_MODE_CLRTICK_TXBD);
13547
13548                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13549                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13550                                        tp->misc_host_ctrl);
13551         }
13552
13553         /* Preserve the APE MAC_MODE bits */
13554         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13555                 tp->mac_mode = tr32(MAC_MODE) |
13556                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13557         else
13558                 tp->mac_mode = TG3_DEF_MAC_MODE;
13559
13560         /* these are limited to 10/100 only */
13561         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13562              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13563             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13564              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13565              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13566               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13567               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13568             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13569              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13570               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13571               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13572             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13573             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13574                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13575
13576         err = tg3_phy_probe(tp);
13577         if (err) {
13578                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13579                        pci_name(tp->pdev), err);
13580                 /* ... but do not return immediately ... */
13581                 tg3_mdio_fini(tp);
13582         }
13583
13584         tg3_read_partno(tp);
13585         tg3_read_fw_ver(tp);
13586
13587         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13588                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13589         } else {
13590                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13591                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13592                 else
13593                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13594         }
13595
13596         /* 5700 {AX,BX} chips have a broken status block link
13597          * change bit implementation, so we must use the
13598          * status register in those cases.
13599          */
13600         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13601                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13602         else
13603                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13604
13605         /* The led_ctrl is set during tg3_phy_probe, here we might
13606          * have to force the link status polling mechanism based
13607          * upon subsystem IDs.
13608          */
13609         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13610             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13611             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13612                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13613                                   TG3_FLAG_USE_LINKCHG_REG);
13614         }
13615
13616         /* For all SERDES we poll the MAC status register. */
13617         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13618                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13619         else
13620                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13621
13622         tp->rx_offset = NET_IP_ALIGN;
13623         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13624             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13625                 tp->rx_offset = 0;
13626
13627         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13628
13629         /* Increment the rx prod index on the rx std ring by at most
13630          * 8 for these chips to workaround hw errata.
13631          */
13632         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13633             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13634             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13635                 tp->rx_std_max_post = 8;
13636
13637         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13638                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13639                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13640
13641         return err;
13642 }
13643
13644 #ifdef CONFIG_SPARC
13645 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13646 {
13647         struct net_device *dev = tp->dev;
13648         struct pci_dev *pdev = tp->pdev;
13649         struct device_node *dp = pci_device_to_OF_node(pdev);
13650         const unsigned char *addr;
13651         int len;
13652
13653         addr = of_get_property(dp, "local-mac-address", &len);
13654         if (addr && len == 6) {
13655                 memcpy(dev->dev_addr, addr, 6);
13656                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13657                 return 0;
13658         }
13659         return -ENODEV;
13660 }
13661
13662 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13663 {
13664         struct net_device *dev = tp->dev;
13665
13666         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13667         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13668         return 0;
13669 }
13670 #endif
13671
13672 static int __devinit tg3_get_device_address(struct tg3 *tp)
13673 {
13674         struct net_device *dev = tp->dev;
13675         u32 hi, lo, mac_offset;
13676         int addr_ok = 0;
13677
13678 #ifdef CONFIG_SPARC
13679         if (!tg3_get_macaddr_sparc(tp))
13680                 return 0;
13681 #endif
13682
13683         mac_offset = 0x7c;
13684         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13685             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13686                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13687                         mac_offset = 0xcc;
13688                 if (tg3_nvram_lock(tp))
13689                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13690                 else
13691                         tg3_nvram_unlock(tp);
13692         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13693                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13694                         mac_offset = 0xcc;
13695         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13696                 mac_offset = 0x10;
13697
13698         /* First try to get it from MAC address mailbox. */
13699         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13700         if ((hi >> 16) == 0x484b) {
13701                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13702                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13703
13704                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13705                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13706                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13707                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13708                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13709
13710                 /* Some old bootcode may report a 0 MAC address in SRAM */
13711                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13712         }
13713         if (!addr_ok) {
13714                 /* Next, try NVRAM. */
13715                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13716                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13717                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13718                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13719                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13720                 }
13721                 /* Finally just fetch it out of the MAC control regs. */
13722                 else {
13723                         hi = tr32(MAC_ADDR_0_HIGH);
13724                         lo = tr32(MAC_ADDR_0_LOW);
13725
13726                         dev->dev_addr[5] = lo & 0xff;
13727                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13728                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13729                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13730                         dev->dev_addr[1] = hi & 0xff;
13731                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13732                 }
13733         }
13734
13735         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13736 #ifdef CONFIG_SPARC
13737                 if (!tg3_get_default_macaddr_sparc(tp))
13738                         return 0;
13739 #endif
13740                 return -EINVAL;
13741         }
13742         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13743         return 0;
13744 }
13745
13746 #define BOUNDARY_SINGLE_CACHELINE       1
13747 #define BOUNDARY_MULTI_CACHELINE        2
13748
13749 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13750 {
13751         int cacheline_size;
13752         u8 byte;
13753         int goal;
13754
13755         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13756         if (byte == 0)
13757                 cacheline_size = 1024;
13758         else
13759                 cacheline_size = (int) byte * 4;
13760
13761         /* On 5703 and later chips, the boundary bits have no
13762          * effect.
13763          */
13764         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13765             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13766             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13767                 goto out;
13768
13769 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13770         goal = BOUNDARY_MULTI_CACHELINE;
13771 #else
13772 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13773         goal = BOUNDARY_SINGLE_CACHELINE;
13774 #else
13775         goal = 0;
13776 #endif
13777 #endif
13778
13779         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13780             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13781                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13782                 goto out;
13783         }
13784
13785         if (!goal)
13786                 goto out;
13787
13788         /* PCI controllers on most RISC systems tend to disconnect
13789          * when a device tries to burst across a cache-line boundary.
13790          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13791          *
13792          * Unfortunately, for PCI-E there are only limited
13793          * write-side controls for this, and thus for reads
13794          * we will still get the disconnects.  We'll also waste
13795          * these PCI cycles for both read and write for chips
13796          * other than 5700 and 5701 which do not implement the
13797          * boundary bits.
13798          */
13799         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13800             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13801                 switch (cacheline_size) {
13802                 case 16:
13803                 case 32:
13804                 case 64:
13805                 case 128:
13806                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13807                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13808                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13809                         } else {
13810                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13811                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13812                         }
13813                         break;
13814
13815                 case 256:
13816                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13817                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13818                         break;
13819
13820                 default:
13821                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13822                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13823                         break;
13824                 }
13825         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13826                 switch (cacheline_size) {
13827                 case 16:
13828                 case 32:
13829                 case 64:
13830                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13831                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13832                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13833                                 break;
13834                         }
13835                         /* fallthrough */
13836                 case 128:
13837                 default:
13838                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13839                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13840                         break;
13841                 }
13842         } else {
13843                 switch (cacheline_size) {
13844                 case 16:
13845                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13846                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13847                                         DMA_RWCTRL_WRITE_BNDRY_16);
13848                                 break;
13849                         }
13850                         /* fallthrough */
13851                 case 32:
13852                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13853                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13854                                         DMA_RWCTRL_WRITE_BNDRY_32);
13855                                 break;
13856                         }
13857                         /* fallthrough */
13858                 case 64:
13859                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13860                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13861                                         DMA_RWCTRL_WRITE_BNDRY_64);
13862                                 break;
13863                         }
13864                         /* fallthrough */
13865                 case 128:
13866                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13867                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13868                                         DMA_RWCTRL_WRITE_BNDRY_128);
13869                                 break;
13870                         }
13871                         /* fallthrough */
13872                 case 256:
13873                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13874                                 DMA_RWCTRL_WRITE_BNDRY_256);
13875                         break;
13876                 case 512:
13877                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13878                                 DMA_RWCTRL_WRITE_BNDRY_512);
13879                         break;
13880                 case 1024:
13881                 default:
13882                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13883                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13884                         break;
13885                 }
13886         }
13887
13888 out:
13889         return val;
13890 }
13891
13892 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13893 {
13894         struct tg3_internal_buffer_desc test_desc;
13895         u32 sram_dma_descs;
13896         int i, ret;
13897
13898         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13899
13900         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13901         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13902         tw32(RDMAC_STATUS, 0);
13903         tw32(WDMAC_STATUS, 0);
13904
13905         tw32(BUFMGR_MODE, 0);
13906         tw32(FTQ_RESET, 0);
13907
13908         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13909         test_desc.addr_lo = buf_dma & 0xffffffff;
13910         test_desc.nic_mbuf = 0x00002100;
13911         test_desc.len = size;
13912
13913         /*
13914          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13915          * the *second* time the tg3 driver was getting loaded after an
13916          * initial scan.
13917          *
13918          * Broadcom tells me:
13919          *   ...the DMA engine is connected to the GRC block and a DMA
13920          *   reset may affect the GRC block in some unpredictable way...
13921          *   The behavior of resets to individual blocks has not been tested.
13922          *
13923          * Broadcom noted the GRC reset will also reset all sub-components.
13924          */
13925         if (to_device) {
13926                 test_desc.cqid_sqid = (13 << 8) | 2;
13927
13928                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13929                 udelay(40);
13930         } else {
13931                 test_desc.cqid_sqid = (16 << 8) | 7;
13932
13933                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13934                 udelay(40);
13935         }
13936         test_desc.flags = 0x00000005;
13937
13938         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13939                 u32 val;
13940
13941                 val = *(((u32 *)&test_desc) + i);
13942                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13943                                        sram_dma_descs + (i * sizeof(u32)));
13944                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13945         }
13946         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13947
13948         if (to_device) {
13949                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13950         } else {
13951                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13952         }
13953
13954         ret = -ENODEV;
13955         for (i = 0; i < 40; i++) {
13956                 u32 val;
13957
13958                 if (to_device)
13959                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13960                 else
13961                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13962                 if ((val & 0xffff) == sram_dma_descs) {
13963                         ret = 0;
13964                         break;
13965                 }
13966
13967                 udelay(100);
13968         }
13969
13970         return ret;
13971 }
13972
13973 #define TEST_BUFFER_SIZE        0x2000
13974
13975 static int __devinit tg3_test_dma(struct tg3 *tp)
13976 {
13977         dma_addr_t buf_dma;
13978         u32 *buf, saved_dma_rwctrl;
13979         int ret = 0;
13980
13981         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13982         if (!buf) {
13983                 ret = -ENOMEM;
13984                 goto out_nofree;
13985         }
13986
13987         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13988                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13989
13990         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13991
13992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13993             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13994                 goto out;
13995
13996         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13997                 /* DMA read watermark not used on PCIE */
13998                 tp->dma_rwctrl |= 0x00180000;
13999         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14000                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14001                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14002                         tp->dma_rwctrl |= 0x003f0000;
14003                 else
14004                         tp->dma_rwctrl |= 0x003f000f;
14005         } else {
14006                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14007                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14008                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14009                         u32 read_water = 0x7;
14010
14011                         /* If the 5704 is behind the EPB bridge, we can
14012                          * do the less restrictive ONE_DMA workaround for
14013                          * better performance.
14014                          */
14015                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14016                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14017                                 tp->dma_rwctrl |= 0x8000;
14018                         else if (ccval == 0x6 || ccval == 0x7)
14019                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14020
14021                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14022                                 read_water = 4;
14023                         /* Set bit 23 to enable PCIX hw bug fix */
14024                         tp->dma_rwctrl |=
14025                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14026                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14027                                 (1 << 23);
14028                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14029                         /* 5780 always in PCIX mode */
14030                         tp->dma_rwctrl |= 0x00144000;
14031                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14032                         /* 5714 always in PCIX mode */
14033                         tp->dma_rwctrl |= 0x00148000;
14034                 } else {
14035                         tp->dma_rwctrl |= 0x001b000f;
14036                 }
14037         }
14038
14039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14040             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14041                 tp->dma_rwctrl &= 0xfffffff0;
14042
14043         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14044             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14045                 /* Remove this if it causes problems for some boards. */
14046                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14047
14048                 /* On 5700/5701 chips, we need to set this bit.
14049                  * Otherwise the chip will issue cacheline transactions
14050                  * to streamable DMA memory with not all the byte
14051                  * enables turned on.  This is an error on several
14052                  * RISC PCI controllers, in particular sparc64.
14053                  *
14054                  * On 5703/5704 chips, this bit has been reassigned
14055                  * a different meaning.  In particular, it is used
14056                  * on those chips to enable a PCI-X workaround.
14057                  */
14058                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14059         }
14060
14061         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14062
14063 #if 0
14064         /* Unneeded, already done by tg3_get_invariants.  */
14065         tg3_switch_clocks(tp);
14066 #endif
14067
14068         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14069             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14070                 goto out;
14071
14072         /* It is best to perform DMA test with maximum write burst size
14073          * to expose the 5700/5701 write DMA bug.
14074          */
14075         saved_dma_rwctrl = tp->dma_rwctrl;
14076         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14077         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14078
14079         while (1) {
14080                 u32 *p = buf, i;
14081
14082                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14083                         p[i] = i;
14084
14085                 /* Send the buffer to the chip. */
14086                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14087                 if (ret) {
14088                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14089                         break;
14090                 }
14091
14092 #if 0
14093                 /* validate data reached card RAM correctly. */
14094                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14095                         u32 val;
14096                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14097                         if (le32_to_cpu(val) != p[i]) {
14098                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
14099                                 /* ret = -ENODEV here? */
14100                         }
14101                         p[i] = 0;
14102                 }
14103 #endif
14104                 /* Now read it back. */
14105                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14106                 if (ret) {
14107                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14108
14109                         break;
14110                 }
14111
14112                 /* Verify it. */
14113                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14114                         if (p[i] == i)
14115                                 continue;
14116
14117                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14118                             DMA_RWCTRL_WRITE_BNDRY_16) {
14119                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14120                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14121                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14122                                 break;
14123                         } else {
14124                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14125                                 ret = -ENODEV;
14126                                 goto out;
14127                         }
14128                 }
14129
14130                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14131                         /* Success. */
14132                         ret = 0;
14133                         break;
14134                 }
14135         }
14136         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14137             DMA_RWCTRL_WRITE_BNDRY_16) {
14138                 static struct pci_device_id dma_wait_state_chipsets[] = {
14139                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14140                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14141                         { },
14142                 };
14143
14144                 /* DMA test passed without adjusting DMA boundary,
14145                  * now look for chipsets that are known to expose the
14146                  * DMA bug without failing the test.
14147                  */
14148                 if (pci_dev_present(dma_wait_state_chipsets)) {
14149                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14150                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14151                 }
14152                 else
14153                         /* Safe to use the calculated DMA boundary. */
14154                         tp->dma_rwctrl = saved_dma_rwctrl;
14155
14156                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14157         }
14158
14159 out:
14160         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14161 out_nofree:
14162         return ret;
14163 }
14164
14165 static void __devinit tg3_init_link_config(struct tg3 *tp)
14166 {
14167         tp->link_config.advertising =
14168                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14169                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14170                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14171                  ADVERTISED_Autoneg | ADVERTISED_MII);
14172         tp->link_config.speed = SPEED_INVALID;
14173         tp->link_config.duplex = DUPLEX_INVALID;
14174         tp->link_config.autoneg = AUTONEG_ENABLE;
14175         tp->link_config.active_speed = SPEED_INVALID;
14176         tp->link_config.active_duplex = DUPLEX_INVALID;
14177         tp->link_config.phy_is_low_power = 0;
14178         tp->link_config.orig_speed = SPEED_INVALID;
14179         tp->link_config.orig_duplex = DUPLEX_INVALID;
14180         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14181 }
14182
14183 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14184 {
14185         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14186             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14187                 tp->bufmgr_config.mbuf_read_dma_low_water =
14188                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14189                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14190                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14191                 tp->bufmgr_config.mbuf_high_water =
14192                         DEFAULT_MB_HIGH_WATER_57765;
14193
14194                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14195                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14196                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14197                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14198                 tp->bufmgr_config.mbuf_high_water_jumbo =
14199                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14200         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14201                 tp->bufmgr_config.mbuf_read_dma_low_water =
14202                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14203                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14204                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14205                 tp->bufmgr_config.mbuf_high_water =
14206                         DEFAULT_MB_HIGH_WATER_5705;
14207                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14208                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14209                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14210                         tp->bufmgr_config.mbuf_high_water =
14211                                 DEFAULT_MB_HIGH_WATER_5906;
14212                 }
14213
14214                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14215                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14216                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14217                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14218                 tp->bufmgr_config.mbuf_high_water_jumbo =
14219                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14220         } else {
14221                 tp->bufmgr_config.mbuf_read_dma_low_water =
14222                         DEFAULT_MB_RDMA_LOW_WATER;
14223                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14224                         DEFAULT_MB_MACRX_LOW_WATER;
14225                 tp->bufmgr_config.mbuf_high_water =
14226                         DEFAULT_MB_HIGH_WATER;
14227
14228                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14229                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14230                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14231                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14232                 tp->bufmgr_config.mbuf_high_water_jumbo =
14233                         DEFAULT_MB_HIGH_WATER_JUMBO;
14234         }
14235
14236         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14237         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14238 }
14239
14240 static char * __devinit tg3_phy_string(struct tg3 *tp)
14241 {
14242         switch (tp->phy_id & PHY_ID_MASK) {
14243         case PHY_ID_BCM5400:    return "5400";
14244         case PHY_ID_BCM5401:    return "5401";
14245         case PHY_ID_BCM5411:    return "5411";
14246         case PHY_ID_BCM5701:    return "5701";
14247         case PHY_ID_BCM5703:    return "5703";
14248         case PHY_ID_BCM5704:    return "5704";
14249         case PHY_ID_BCM5705:    return "5705";
14250         case PHY_ID_BCM5750:    return "5750";
14251         case PHY_ID_BCM5752:    return "5752";
14252         case PHY_ID_BCM5714:    return "5714";
14253         case PHY_ID_BCM5780:    return "5780";
14254         case PHY_ID_BCM5755:    return "5755";
14255         case PHY_ID_BCM5787:    return "5787";
14256         case PHY_ID_BCM5784:    return "5784";
14257         case PHY_ID_BCM5756:    return "5722/5756";
14258         case PHY_ID_BCM5906:    return "5906";
14259         case PHY_ID_BCM5761:    return "5761";
14260         case PHY_ID_BCM5718C:   return "5718C";
14261         case PHY_ID_BCM5718S:   return "5718S";
14262         case PHY_ID_BCM57765:   return "57765";
14263         case PHY_ID_BCM8002:    return "8002/serdes";
14264         case 0:                 return "serdes";
14265         default:                return "unknown";
14266         }
14267 }
14268
14269 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14270 {
14271         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14272                 strcpy(str, "PCI Express");
14273                 return str;
14274         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14275                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14276
14277                 strcpy(str, "PCIX:");
14278
14279                 if ((clock_ctrl == 7) ||
14280                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14281                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14282                         strcat(str, "133MHz");
14283                 else if (clock_ctrl == 0)
14284                         strcat(str, "33MHz");
14285                 else if (clock_ctrl == 2)
14286                         strcat(str, "50MHz");
14287                 else if (clock_ctrl == 4)
14288                         strcat(str, "66MHz");
14289                 else if (clock_ctrl == 6)
14290                         strcat(str, "100MHz");
14291         } else {
14292                 strcpy(str, "PCI:");
14293                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14294                         strcat(str, "66MHz");
14295                 else
14296                         strcat(str, "33MHz");
14297         }
14298         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14299                 strcat(str, ":32-bit");
14300         else
14301                 strcat(str, ":64-bit");
14302         return str;
14303 }
14304
14305 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14306 {
14307         struct pci_dev *peer;
14308         unsigned int func, devnr = tp->pdev->devfn & ~7;
14309
14310         for (func = 0; func < 8; func++) {
14311                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14312                 if (peer && peer != tp->pdev)
14313                         break;
14314                 pci_dev_put(peer);
14315         }
14316         /* 5704 can be configured in single-port mode, set peer to
14317          * tp->pdev in that case.
14318          */
14319         if (!peer) {
14320                 peer = tp->pdev;
14321                 return peer;
14322         }
14323
14324         /*
14325          * We don't need to keep the refcount elevated; there's no way
14326          * to remove one half of this device without removing the other
14327          */
14328         pci_dev_put(peer);
14329
14330         return peer;
14331 }
14332
14333 static void __devinit tg3_init_coal(struct tg3 *tp)
14334 {
14335         struct ethtool_coalesce *ec = &tp->coal;
14336
14337         memset(ec, 0, sizeof(*ec));
14338         ec->cmd = ETHTOOL_GCOALESCE;
14339         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14340         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14341         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14342         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14343         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14344         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14345         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14346         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14347         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14348
14349         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14350                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14351                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14352                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14353                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14354                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14355         }
14356
14357         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14358                 ec->rx_coalesce_usecs_irq = 0;
14359                 ec->tx_coalesce_usecs_irq = 0;
14360                 ec->stats_block_coalesce_usecs = 0;
14361         }
14362 }
14363
14364 static const struct net_device_ops tg3_netdev_ops = {
14365         .ndo_open               = tg3_open,
14366         .ndo_stop               = tg3_close,
14367         .ndo_start_xmit         = tg3_start_xmit,
14368         .ndo_get_stats          = tg3_get_stats,
14369         .ndo_validate_addr      = eth_validate_addr,
14370         .ndo_set_multicast_list = tg3_set_rx_mode,
14371         .ndo_set_mac_address    = tg3_set_mac_addr,
14372         .ndo_do_ioctl           = tg3_ioctl,
14373         .ndo_tx_timeout         = tg3_tx_timeout,
14374         .ndo_change_mtu         = tg3_change_mtu,
14375 #if TG3_VLAN_TAG_USED
14376         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14377 #endif
14378 #ifdef CONFIG_NET_POLL_CONTROLLER
14379         .ndo_poll_controller    = tg3_poll_controller,
14380 #endif
14381 };
14382
14383 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14384         .ndo_open               = tg3_open,
14385         .ndo_stop               = tg3_close,
14386         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14387         .ndo_get_stats          = tg3_get_stats,
14388         .ndo_validate_addr      = eth_validate_addr,
14389         .ndo_set_multicast_list = tg3_set_rx_mode,
14390         .ndo_set_mac_address    = tg3_set_mac_addr,
14391         .ndo_do_ioctl           = tg3_ioctl,
14392         .ndo_tx_timeout         = tg3_tx_timeout,
14393         .ndo_change_mtu         = tg3_change_mtu,
14394 #if TG3_VLAN_TAG_USED
14395         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14396 #endif
14397 #ifdef CONFIG_NET_POLL_CONTROLLER
14398         .ndo_poll_controller    = tg3_poll_controller,
14399 #endif
14400 };
14401
14402 static int __devinit tg3_init_one(struct pci_dev *pdev,
14403                                   const struct pci_device_id *ent)
14404 {
14405         static int tg3_version_printed = 0;
14406         struct net_device *dev;
14407         struct tg3 *tp;
14408         int i, err, pm_cap;
14409         u32 sndmbx, rcvmbx, intmbx;
14410         char str[40];
14411         u64 dma_mask, persist_dma_mask;
14412
14413         if (tg3_version_printed++ == 0)
14414                 printk(KERN_INFO "%s", version);
14415
14416         err = pci_enable_device(pdev);
14417         if (err) {
14418                 printk(KERN_ERR PFX "Cannot enable PCI device, "
14419                        "aborting.\n");
14420                 return err;
14421         }
14422
14423         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14424         if (err) {
14425                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14426                        "aborting.\n");
14427                 goto err_out_disable_pdev;
14428         }
14429
14430         pci_set_master(pdev);
14431
14432         /* Find power-management capability. */
14433         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14434         if (pm_cap == 0) {
14435                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14436                        "aborting.\n");
14437                 err = -EIO;
14438                 goto err_out_free_res;
14439         }
14440
14441         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14442         if (!dev) {
14443                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14444                 err = -ENOMEM;
14445                 goto err_out_free_res;
14446         }
14447
14448         SET_NETDEV_DEV(dev, &pdev->dev);
14449
14450 #if TG3_VLAN_TAG_USED
14451         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14452 #endif
14453
14454         tp = netdev_priv(dev);
14455         tp->pdev = pdev;
14456         tp->dev = dev;
14457         tp->pm_cap = pm_cap;
14458         tp->rx_mode = TG3_DEF_RX_MODE;
14459         tp->tx_mode = TG3_DEF_TX_MODE;
14460
14461         if (tg3_debug > 0)
14462                 tp->msg_enable = tg3_debug;
14463         else
14464                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14465
14466         /* The word/byte swap controls here control register access byte
14467          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14468          * setting below.
14469          */
14470         tp->misc_host_ctrl =
14471                 MISC_HOST_CTRL_MASK_PCI_INT |
14472                 MISC_HOST_CTRL_WORD_SWAP |
14473                 MISC_HOST_CTRL_INDIR_ACCESS |
14474                 MISC_HOST_CTRL_PCISTATE_RW;
14475
14476         /* The NONFRM (non-frame) byte/word swap controls take effect
14477          * on descriptor entries, anything which isn't packet data.
14478          *
14479          * The StrongARM chips on the board (one for tx, one for rx)
14480          * are running in big-endian mode.
14481          */
14482         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14483                         GRC_MODE_WSWAP_NONFRM_DATA);
14484 #ifdef __BIG_ENDIAN
14485         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14486 #endif
14487         spin_lock_init(&tp->lock);
14488         spin_lock_init(&tp->indirect_lock);
14489         INIT_WORK(&tp->reset_task, tg3_reset_task);
14490
14491         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14492         if (!tp->regs) {
14493                 printk(KERN_ERR PFX "Cannot map device registers, "
14494                        "aborting.\n");
14495                 err = -ENOMEM;
14496                 goto err_out_free_dev;
14497         }
14498
14499         tg3_init_link_config(tp);
14500
14501         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14502         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14503
14504         dev->ethtool_ops = &tg3_ethtool_ops;
14505         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14506         dev->irq = pdev->irq;
14507
14508         err = tg3_get_invariants(tp);
14509         if (err) {
14510                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14511                        "aborting.\n");
14512                 goto err_out_iounmap;
14513         }
14514
14515         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14516             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14517                 dev->netdev_ops = &tg3_netdev_ops;
14518         else
14519                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14520
14521
14522         /* The EPB bridge inside 5714, 5715, and 5780 and any
14523          * device behind the EPB cannot support DMA addresses > 40-bit.
14524          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14525          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14526          * do DMA address check in tg3_start_xmit().
14527          */
14528         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14529                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14530         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14531                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14532 #ifdef CONFIG_HIGHMEM
14533                 dma_mask = DMA_BIT_MASK(64);
14534 #endif
14535         } else
14536                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14537
14538         /* Configure DMA attributes. */
14539         if (dma_mask > DMA_BIT_MASK(32)) {
14540                 err = pci_set_dma_mask(pdev, dma_mask);
14541                 if (!err) {
14542                         dev->features |= NETIF_F_HIGHDMA;
14543                         err = pci_set_consistent_dma_mask(pdev,
14544                                                           persist_dma_mask);
14545                         if (err < 0) {
14546                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14547                                        "DMA for consistent allocations\n");
14548                                 goto err_out_iounmap;
14549                         }
14550                 }
14551         }
14552         if (err || dma_mask == DMA_BIT_MASK(32)) {
14553                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14554                 if (err) {
14555                         printk(KERN_ERR PFX "No usable DMA configuration, "
14556                                "aborting.\n");
14557                         goto err_out_iounmap;
14558                 }
14559         }
14560
14561         tg3_init_bufmgr_config(tp);
14562
14563         /* Selectively allow TSO based on operating conditions */
14564         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14565             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14566                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14567         else {
14568                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14569                 tp->fw_needed = NULL;
14570         }
14571
14572         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14573                 tp->fw_needed = FIRMWARE_TG3;
14574
14575         /* TSO is on by default on chips that support hardware TSO.
14576          * Firmware TSO on older chips gives lower performance, so it
14577          * is off by default, but can be enabled using ethtool.
14578          */
14579         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14580             (dev->features & NETIF_F_IP_CSUM))
14581                 dev->features |= NETIF_F_TSO;
14582
14583         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14584             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14585                 if (dev->features & NETIF_F_IPV6_CSUM)
14586                         dev->features |= NETIF_F_TSO6;
14587                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14588                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14589                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14590                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14591                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14592                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14593                         dev->features |= NETIF_F_TSO_ECN;
14594         }
14595
14596         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14597             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14598             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14599                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14600                 tp->rx_pending = 63;
14601         }
14602
14603         err = tg3_get_device_address(tp);
14604         if (err) {
14605                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14606                        "aborting.\n");
14607                 goto err_out_iounmap;
14608         }
14609
14610         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14611                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14612                 if (!tp->aperegs) {
14613                         printk(KERN_ERR PFX "Cannot map APE registers, "
14614                                "aborting.\n");
14615                         err = -ENOMEM;
14616                         goto err_out_iounmap;
14617                 }
14618
14619                 tg3_ape_lock_init(tp);
14620
14621                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14622                         tg3_read_dash_ver(tp);
14623         }
14624
14625         /*
14626          * Reset chip in case UNDI or EFI driver did not shutdown
14627          * DMA self test will enable WDMAC and we'll see (spurious)
14628          * pending DMA on the PCI bus at that point.
14629          */
14630         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14631             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14632                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14633                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14634         }
14635
14636         err = tg3_test_dma(tp);
14637         if (err) {
14638                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14639                 goto err_out_apeunmap;
14640         }
14641
14642         /* flow control autonegotiation is default behavior */
14643         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14644         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14645
14646         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14647         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14648         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14649         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14650                 struct tg3_napi *tnapi = &tp->napi[i];
14651
14652                 tnapi->tp = tp;
14653                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14654
14655                 tnapi->int_mbox = intmbx;
14656                 if (i < 4)
14657                         intmbx += 0x8;
14658                 else
14659                         intmbx += 0x4;
14660
14661                 tnapi->consmbox = rcvmbx;
14662                 tnapi->prodmbox = sndmbx;
14663
14664                 if (i) {
14665                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14666                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14667                 } else {
14668                         tnapi->coal_now = HOSTCC_MODE_NOW;
14669                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14670                 }
14671
14672                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14673                         break;
14674
14675                 /*
14676                  * If we support MSIX, we'll be using RSS.  If we're using
14677                  * RSS, the first vector only handles link interrupts and the
14678                  * remaining vectors handle rx and tx interrupts.  Reuse the
14679                  * mailbox values for the next iteration.  The values we setup
14680                  * above are still useful for the single vectored mode.
14681                  */
14682                 if (!i)
14683                         continue;
14684
14685                 rcvmbx += 0x8;
14686
14687                 if (sndmbx & 0x4)
14688                         sndmbx -= 0x4;
14689                 else
14690                         sndmbx += 0xc;
14691         }
14692
14693         tg3_init_coal(tp);
14694
14695         pci_set_drvdata(pdev, dev);
14696
14697         err = register_netdev(dev);
14698         if (err) {
14699                 printk(KERN_ERR PFX "Cannot register net device, "
14700                        "aborting.\n");
14701                 goto err_out_apeunmap;
14702         }
14703
14704         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14705                dev->name,
14706                tp->board_part_number,
14707                tp->pci_chip_rev_id,
14708                tg3_bus_string(tp, str),
14709                dev->dev_addr);
14710
14711         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14712                 struct phy_device *phydev;
14713                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14714                 printk(KERN_INFO
14715                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14716                        tp->dev->name, phydev->drv->name,
14717                        dev_name(&phydev->dev));
14718         } else
14719                 printk(KERN_INFO
14720                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14721                        tp->dev->name, tg3_phy_string(tp),
14722                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14723                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14724                          "10/100/1000Base-T")),
14725                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14726
14727         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14728                dev->name,
14729                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14730                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14731                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14732                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14733                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14734         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14735                dev->name, tp->dma_rwctrl,
14736                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14737                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14738
14739         return 0;
14740
14741 err_out_apeunmap:
14742         if (tp->aperegs) {
14743                 iounmap(tp->aperegs);
14744                 tp->aperegs = NULL;
14745         }
14746
14747 err_out_iounmap:
14748         if (tp->regs) {
14749                 iounmap(tp->regs);
14750                 tp->regs = NULL;
14751         }
14752
14753 err_out_free_dev:
14754         free_netdev(dev);
14755
14756 err_out_free_res:
14757         pci_release_regions(pdev);
14758
14759 err_out_disable_pdev:
14760         pci_disable_device(pdev);
14761         pci_set_drvdata(pdev, NULL);
14762         return err;
14763 }
14764
14765 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14766 {
14767         struct net_device *dev = pci_get_drvdata(pdev);
14768
14769         if (dev) {
14770                 struct tg3 *tp = netdev_priv(dev);
14771
14772                 if (tp->fw)
14773                         release_firmware(tp->fw);
14774
14775                 flush_scheduled_work();
14776
14777                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14778                         tg3_phy_fini(tp);
14779                         tg3_mdio_fini(tp);
14780                 }
14781
14782                 unregister_netdev(dev);
14783                 if (tp->aperegs) {
14784                         iounmap(tp->aperegs);
14785                         tp->aperegs = NULL;
14786                 }
14787                 if (tp->regs) {
14788                         iounmap(tp->regs);
14789                         tp->regs = NULL;
14790                 }
14791                 free_netdev(dev);
14792                 pci_release_regions(pdev);
14793                 pci_disable_device(pdev);
14794                 pci_set_drvdata(pdev, NULL);
14795         }
14796 }
14797
14798 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14799 {
14800         struct net_device *dev = pci_get_drvdata(pdev);
14801         struct tg3 *tp = netdev_priv(dev);
14802         pci_power_t target_state;
14803         int err;
14804
14805         /* PCI register 4 needs to be saved whether netif_running() or not.
14806          * MSI address and data need to be saved if using MSI and
14807          * netif_running().
14808          */
14809         pci_save_state(pdev);
14810
14811         if (!netif_running(dev))
14812                 return 0;
14813
14814         flush_scheduled_work();
14815         tg3_phy_stop(tp);
14816         tg3_netif_stop(tp);
14817
14818         del_timer_sync(&tp->timer);
14819
14820         tg3_full_lock(tp, 1);
14821         tg3_disable_ints(tp);
14822         tg3_full_unlock(tp);
14823
14824         netif_device_detach(dev);
14825
14826         tg3_full_lock(tp, 0);
14827         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14828         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14829         tg3_full_unlock(tp);
14830
14831         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14832
14833         err = tg3_set_power_state(tp, target_state);
14834         if (err) {
14835                 int err2;
14836
14837                 tg3_full_lock(tp, 0);
14838
14839                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14840                 err2 = tg3_restart_hw(tp, 1);
14841                 if (err2)
14842                         goto out;
14843
14844                 tp->timer.expires = jiffies + tp->timer_offset;
14845                 add_timer(&tp->timer);
14846
14847                 netif_device_attach(dev);
14848                 tg3_netif_start(tp);
14849
14850 out:
14851                 tg3_full_unlock(tp);
14852
14853                 if (!err2)
14854                         tg3_phy_start(tp);
14855         }
14856
14857         return err;
14858 }
14859
14860 static int tg3_resume(struct pci_dev *pdev)
14861 {
14862         struct net_device *dev = pci_get_drvdata(pdev);
14863         struct tg3 *tp = netdev_priv(dev);
14864         int err;
14865
14866         pci_restore_state(tp->pdev);
14867
14868         if (!netif_running(dev))
14869                 return 0;
14870
14871         err = tg3_set_power_state(tp, PCI_D0);
14872         if (err)
14873                 return err;
14874
14875         netif_device_attach(dev);
14876
14877         tg3_full_lock(tp, 0);
14878
14879         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14880         err = tg3_restart_hw(tp, 1);
14881         if (err)
14882                 goto out;
14883
14884         tp->timer.expires = jiffies + tp->timer_offset;
14885         add_timer(&tp->timer);
14886
14887         tg3_netif_start(tp);
14888
14889 out:
14890         tg3_full_unlock(tp);
14891
14892         if (!err)
14893                 tg3_phy_start(tp);
14894
14895         return err;
14896 }
14897
14898 static struct pci_driver tg3_driver = {
14899         .name           = DRV_MODULE_NAME,
14900         .id_table       = tg3_pci_tbl,
14901         .probe          = tg3_init_one,
14902         .remove         = __devexit_p(tg3_remove_one),
14903         .suspend        = tg3_suspend,
14904         .resume         = tg3_resume
14905 };
14906
14907 static int __init tg3_init(void)
14908 {
14909         return pci_register_driver(&tg3_driver);
14910 }
14911
14912 static void __exit tg3_cleanup(void)
14913 {
14914         pci_unregister_driver(&tg3_driver);
14915 }
14916
14917 module_init(tg3_init);
14918 module_exit(tg3_cleanup);