drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43 #include <net/ip.h>
  44
  45 #include <asm/system.h>
  46 #include <asm/io.h>
  47 #include <asm/byteorder.h>
  48 #include <asm/uaccess.h>
  49
  50 #ifdef CONFIG_SPARC
  51 #include <asm/idprom.h>
  52 #include <asm/prom.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #define TG3_TSO_SUPPORT 1
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define PFX DRV_MODULE_NAME     ": "
  67 #define DRV_MODULE_VERSION      "3.76"
  68 #define DRV_MODULE_RELDATE      "May 5, 2007"
  69
  70 #define TG3_DEF_MAC_MODE        0
  71 #define TG3_DEF_RX_MODE         0
  72 #define TG3_DEF_TX_MODE         0
  73 #define TG3_DEF_MSG_ENABLE        \
  74         (NETIF_MSG_DRV          | \
  75          NETIF_MSG_PROBE        | \
  76          NETIF_MSG_LINK         | \
  77          NETIF_MSG_TIMER        | \
  78          NETIF_MSG_IFDOWN       | \
  79          NETIF_MSG_IFUP         | \
  80          NETIF_MSG_RX_ERR       | \
  81          NETIF_MSG_TX_ERR)
  82
  83 /* length of time before we decide the hardware is borked,
  84  * and dev->tx_timeout() should be called to fix the problem
  85  */
  86 #define TG3_TX_TIMEOUT                  (5 * HZ)
  87
  88 /* hardware minimum and maximum for a single frame's data payload */
  89 #define TG3_MIN_MTU                     60
  90 #define TG3_MAX_MTU(tp) \
  91         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  92
  93 /* These numbers seem to be hard coded in the NIC firmware somehow.
  94  * You can't change the ring sizes, but you can change where you place
  95  * them in the NIC onboard memory.
  96  */
  97 #define TG3_RX_RING_SIZE                512
  98 #define TG3_DEF_RX_RING_PENDING         200
  99 #define TG3_RX_JUMBO_RING_SIZE          256
 100 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 101
 102 /* Do not place this n-ring entries value into the tp struct itself,
 103  * we really want to expose these constants to GCC so that modulo et
 104  * al.  operations are done with shifts and masks instead of with
 105  * hw multiply/modulo instructions.  Another solution would be to
 106  * replace things like '% foo' with '& (foo - 1)'.
 107  */
 108 #define TG3_RX_RCB_RING_SIZE(tp)        \
 109         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 110
 111 #define TG3_TX_RING_SIZE                512
 112 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 113
 114 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 115                                  TG3_RX_RING_SIZE)
 116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_JUMBO_RING_SIZE)
 118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 119                                    TG3_RX_RCB_RING_SIZE(tp))
 120 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 121                                  TG3_TX_RING_SIZE)
 122 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 123
 124 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 125 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 126
 127 /* minimum number of free TX descriptors required to wake up TX process */
 128 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 129
 130 /* number of ETHTOOL_GSTATS u64's */
 131 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 132
 133 #define TG3_NUM_TEST            6
 134
 135 static char version[] __devinitdata =
 136         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 137
 138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142
 143 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 144 module_param(tg3_debug, int, 0);
 145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 146
 147 static struct pci_device_id tg3_pci_tbl[] = {
 148         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 208         {}
 209 };
 210
 211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 212
 213 static const struct {
 214         const char string[ETH_GSTRING_LEN];
 215 } ethtool_stats_keys[TG3_NUM_STATS] = {
 216         { "rx_octets" },
 217         { "rx_fragments" },
 218         { "rx_ucast_packets" },
 219         { "rx_mcast_packets" },
 220         { "rx_bcast_packets" },
 221         { "rx_fcs_errors" },
 222         { "rx_align_errors" },
 223         { "rx_xon_pause_rcvd" },
 224         { "rx_xoff_pause_rcvd" },
 225         { "rx_mac_ctrl_rcvd" },
 226         { "rx_xoff_entered" },
 227         { "rx_frame_too_long_errors" },
 228         { "rx_jabbers" },
 229         { "rx_undersize_packets" },
 230         { "rx_in_length_errors" },
 231         { "rx_out_length_errors" },
 232         { "rx_64_or_less_octet_packets" },
 233         { "rx_65_to_127_octet_packets" },
 234         { "rx_128_to_255_octet_packets" },
 235         { "rx_256_to_511_octet_packets" },
 236         { "rx_512_to_1023_octet_packets" },
 237         { "rx_1024_to_1522_octet_packets" },
 238         { "rx_1523_to_2047_octet_packets" },
 239         { "rx_2048_to_4095_octet_packets" },
 240         { "rx_4096_to_8191_octet_packets" },
 241         { "rx_8192_to_9022_octet_packets" },
 242
 243         { "tx_octets" },
 244         { "tx_collisions" },
 245
 246         { "tx_xon_sent" },
 247         { "tx_xoff_sent" },
 248         { "tx_flow_control" },
 249         { "tx_mac_errors" },
 250         { "tx_single_collisions" },
 251         { "tx_mult_collisions" },
 252         { "tx_deferred" },
 253         { "tx_excessive_collisions" },
 254         { "tx_late_collisions" },
 255         { "tx_collide_2times" },
 256         { "tx_collide_3times" },
 257         { "tx_collide_4times" },
 258         { "tx_collide_5times" },
 259         { "tx_collide_6times" },
 260         { "tx_collide_7times" },
 261         { "tx_collide_8times" },
 262         { "tx_collide_9times" },
 263         { "tx_collide_10times" },
 264         { "tx_collide_11times" },
 265         { "tx_collide_12times" },
 266         { "tx_collide_13times" },
 267         { "tx_collide_14times" },
 268         { "tx_collide_15times" },
 269         { "tx_ucast_packets" },
 270         { "tx_mcast_packets" },
 271         { "tx_bcast_packets" },
 272         { "tx_carrier_sense_errors" },
 273         { "tx_discards" },
 274         { "tx_errors" },
 275
 276         { "dma_writeq_full" },
 277         { "dma_write_prioq_full" },
 278         { "rxbds_empty" },
 279         { "rx_discards" },
 280         { "rx_errors" },
 281         { "rx_threshold_hit" },
 282
 283         { "dma_readq_full" },
 284         { "dma_read_prioq_full" },
 285         { "tx_comp_queue_full" },
 286
 287         { "ring_set_send_prod_index" },
 288         { "ring_status_update" },
 289         { "nic_irqs" },
 290         { "nic_avoided_irqs" },
 291         { "nic_tx_threshold_hit" }
 292 };
 293
 294 static const struct {
 295         const char string[ETH_GSTRING_LEN];
 296 } ethtool_test_keys[TG3_NUM_TEST] = {
 297         { "nvram test     (online) " },
 298         { "link test      (online) " },
 299         { "register test  (offline)" },
 300         { "memory test    (offline)" },
 301         { "loopback test  (offline)" },
 302         { "interrupt test (offline)" },
 303 };
 304
 305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 306 {
 307         writel(val, tp->regs + off);
 308 }
 309
 310 static u32 tg3_read32(struct tg3 *tp, u32 off)
 311 {
 312         return (readl(tp->regs + off));
 313 }
 314
 315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 316 {
 317         unsigned long flags;
 318
 319         spin_lock_irqsave(&tp->indirect_lock, flags);
 320         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 321         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 322         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 323 }
 324
 325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 326 {
 327         writel(val, tp->regs + off);
 328         readl(tp->regs + off);
 329 }
 330
 331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 332 {
 333         unsigned long flags;
 334         u32 val;
 335
 336         spin_lock_irqsave(&tp->indirect_lock, flags);
 337         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 338         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 339         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 340         return val;
 341 }
 342
 343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 344 {
 345         unsigned long flags;
 346
 347         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 348                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 349                                        TG3_64BIT_REG_LOW, val);
 350                 return;
 351         }
 352         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 353                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 354                                        TG3_64BIT_REG_LOW, val);
 355                 return;
 356         }
 357
 358         spin_lock_irqsave(&tp->indirect_lock, flags);
 359         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 360         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 361         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 362
 363         /* In indirect mode when disabling interrupts, we also need
 364          * to clear the interrupt bit in the GRC local ctrl register.
 365          */
 366         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 367             (val == 0x1)) {
 368                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 369                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 370         }
 371 }
 372
 373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 374 {
 375         unsigned long flags;
 376         u32 val;
 377
 378         spin_lock_irqsave(&tp->indirect_lock, flags);
 379         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 380         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 381         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 382         return val;
 383 }
 384
 385 /* usec_wait specifies the wait time in usec when writing to certain registers
 386  * where it is unsafe to read back the register without some delay.
 387  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 388  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 389  */
 390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 391 {
 392         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 393             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 394                 /* Non-posted methods */
 395                 tp->write32(tp, off, val);
 396         else {
 397                 /* Posted method */
 398                 tg3_write32(tp, off, val);
 399                 if (usec_wait)
 400                         udelay(usec_wait);
 401                 tp->read32(tp, off);
 402         }
 403         /* Wait again after the read for the posted method to guarantee that
 404          * the wait time is met.
 405          */
 406         if (usec_wait)
 407                 udelay(usec_wait);
 408 }
 409
 410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 411 {
 412         tp->write32_mbox(tp, off, val);
 413         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 414             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 415                 tp->read32_mbox(tp, off);
 416 }
 417
 418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 419 {
 420         void __iomem *mbox = tp->regs + off;
 421         writel(val, mbox);
 422         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 423                 writel(val, mbox);
 424         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 425                 readl(mbox);
 426 }
 427
 428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 429 {
 430         return (readl(tp->regs + off + GRCMBOX_BASE));
 431 }
 432
 433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 434 {
 435         writel(val, tp->regs + off + GRCMBOX_BASE);
 436 }
 437
 438 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 439 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 440 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 441 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 442 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 443
 444 #define tw32(reg,val)           tp->write32(tp, reg, val)
 445 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 447 #define tr32(reg)               tp->read32(tp, reg)
 448
 449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 450 {
 451         unsigned long flags;
 452
 453         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 454             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 455                 return;
 456
 457         spin_lock_irqsave(&tp->indirect_lock, flags);
 458         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 459                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 460                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 461
 462                 /* Always leave this as zero. */
 463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 464         } else {
 465                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 466                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 467
 468                 /* Always leave this as zero. */
 469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 470         }
 471         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 472 }
 473
 474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 475 {
 476         unsigned long flags;
 477
 478         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 479             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 480                 *val = 0;
 481                 return;
 482         }
 483
 484         spin_lock_irqsave(&tp->indirect_lock, flags);
 485         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 486                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 487                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 488
 489                 /* Always leave this as zero. */
 490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 491         } else {
 492                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 493                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 494
 495                 /* Always leave this as zero. */
 496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 497         }
 498         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 499 }
 500
 501 static void tg3_disable_ints(struct tg3 *tp)
 502 {
 503         tw32(TG3PCI_MISC_HOST_CTRL,
 504              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 505         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 506 }
 507
 508 static inline void tg3_cond_int(struct tg3 *tp)
 509 {
 510         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 511             (tp->hw_status->status & SD_STATUS_UPDATED))
 512                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 513         else
 514                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 515                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 516 }
 517
 518 static void tg3_enable_ints(struct tg3 *tp)
 519 {
 520         tp->irq_sync = 0;
 521         wmb();
 522
 523         tw32(TG3PCI_MISC_HOST_CTRL,
 524              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 525         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 526                        (tp->last_tag << 24));
 527         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 528                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 529                                (tp->last_tag << 24));
 530         tg3_cond_int(tp);
 531 }
 532
 533 static inline unsigned int tg3_has_work(struct tg3 *tp)
 534 {
 535         struct tg3_hw_status *sblk = tp->hw_status;
 536         unsigned int work_exists = 0;
 537
 538         /* check for phy events */
 539         if (!(tp->tg3_flags &
 540               (TG3_FLAG_USE_LINKCHG_REG |
 541                TG3_FLAG_POLL_SERDES))) {
 542                 if (sblk->status & SD_STATUS_LINK_CHG)
 543                         work_exists = 1;
 544         }
 545         /* check for RX/TX work to do */
 546         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 547             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 548                 work_exists = 1;
 549
 550         return work_exists;
 551 }
 552
 553 /* tg3_restart_ints
 554  *  similar to tg3_enable_ints, but it accurately determines whether there
 555  *  is new work pending and can return without flushing the PIO write
 556  *  which reenables interrupts
 557  */
 558 static void tg3_restart_ints(struct tg3 *tp)
 559 {
 560         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 561                      tp->last_tag << 24);
 562         mmiowb();
 563
 564         /* When doing tagged status, this work check is unnecessary.
 565          * The last_tag we write above tells the chip which piece of
 566          * work we've completed.
 567          */
 568         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 569             tg3_has_work(tp))
 570                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 571                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 572 }
 573
 574 static inline void tg3_netif_stop(struct tg3 *tp)
 575 {
 576         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 577         netif_poll_disable(tp->dev);
 578         netif_tx_disable(tp->dev);
 579 }
 580
 581 static inline void tg3_netif_start(struct tg3 *tp)
 582 {
 583         netif_wake_queue(tp->dev);
 584         /* NOTE: unconditional netif_wake_queue is only appropriate
 585          * so long as all callers are assured to have free tx slots
 586          * (such as after tg3_init_hw)
 587          */
 588         netif_poll_enable(tp->dev);
 589         tp->hw_status->status |= SD_STATUS_UPDATED;
 590         tg3_enable_ints(tp);
 591 }
 592
 593 static void tg3_switch_clocks(struct tg3 *tp)
 594 {
 595         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 596         u32 orig_clock_ctrl;
 597
 598         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 599                 return;
 600
 601         orig_clock_ctrl = clock_ctrl;
 602         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 603                        CLOCK_CTRL_CLKRUN_OENABLE |
 604                        0x1f);
 605         tp->pci_clock_ctrl = clock_ctrl;
 606
 607         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 608                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 609                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 610                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 611                 }
 612         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 613                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 614                             clock_ctrl |
 615                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 616                             40);
 617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 618                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 619                             40);
 620         }
 621         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 622 }
 623
 624 #define PHY_BUSY_LOOPS  5000
 625
 626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 627 {
 628         u32 frame_val;
 629         unsigned int loops;
 630         int ret;
 631
 632         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 633                 tw32_f(MAC_MI_MODE,
 634                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 635                 udelay(80);
 636         }
 637
 638         *val = 0x0;
 639
 640         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 641                       MI_COM_PHY_ADDR_MASK);
 642         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 643                       MI_COM_REG_ADDR_MASK);
 644         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 645
 646         tw32_f(MAC_MI_COM, frame_val);
 647
 648         loops = PHY_BUSY_LOOPS;
 649         while (loops != 0) {
 650                 udelay(10);
 651                 frame_val = tr32(MAC_MI_COM);
 652
 653                 if ((frame_val & MI_COM_BUSY) == 0) {
 654                         udelay(5);
 655                         frame_val = tr32(MAC_MI_COM);
 656                         break;
 657                 }
 658                 loops -= 1;
 659         }
 660
 661         ret = -EBUSY;
 662         if (loops != 0) {
 663                 *val = frame_val & MI_COM_DATA_MASK;
 664                 ret = 0;
 665         }
 666
 667         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 668                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 669                 udelay(80);
 670         }
 671
 672         return ret;
 673 }
 674
 675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 676 {
 677         u32 frame_val;
 678         unsigned int loops;
 679         int ret;
 680
 681         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 682             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 683                 return 0;
 684
 685         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 686                 tw32_f(MAC_MI_MODE,
 687                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 688                 udelay(80);
 689         }
 690
 691         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 692                       MI_COM_PHY_ADDR_MASK);
 693         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 694                       MI_COM_REG_ADDR_MASK);
 695         frame_val |= (val & MI_COM_DATA_MASK);
 696         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 697
 698         tw32_f(MAC_MI_COM, frame_val);
 699
 700         loops = PHY_BUSY_LOOPS;
 701         while (loops != 0) {
 702                 udelay(10);
 703                 frame_val = tr32(MAC_MI_COM);
 704                 if ((frame_val & MI_COM_BUSY) == 0) {
 705                         udelay(5);
 706                         frame_val = tr32(MAC_MI_COM);
 707                         break;
 708                 }
 709                 loops -= 1;
 710         }
 711
 712         ret = -EBUSY;
 713         if (loops != 0)
 714                 ret = 0;
 715
 716         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 717                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 718                 udelay(80);
 719         }
 720
 721         return ret;
 722 }
 723
 724 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 725 {
 726         u32 val;
 727
 728         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 729                 return;
 730
 731         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 732             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 733                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 734                              (val | (1 << 15) | (1 << 4)));
 735 }
 736
 737 static int tg3_bmcr_reset(struct tg3 *tp)
 738 {
 739         u32 phy_control;
 740         int limit, err;
 741
 742         /* OK, reset it, and poll the BMCR_RESET bit until it
 743          * clears or we time out.
 744          */
 745         phy_control = BMCR_RESET;
 746         err = tg3_writephy(tp, MII_BMCR, phy_control);
 747         if (err != 0)
 748                 return -EBUSY;
 749
 750         limit = 5000;
 751         while (limit--) {
 752                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 753                 if (err != 0)
 754                         return -EBUSY;
 755
 756                 if ((phy_control & BMCR_RESET) == 0) {
 757                         udelay(40);
 758                         break;
 759                 }
 760                 udelay(10);
 761         }
 762         if (limit <= 0)
 763                 return -EBUSY;
 764
 765         return 0;
 766 }
 767
 768 static int tg3_wait_macro_done(struct tg3 *tp)
 769 {
 770         int limit = 100;
 771
 772         while (limit--) {
 773                 u32 tmp32;
 774
 775                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 776                         if ((tmp32 & 0x1000) == 0)
 777                                 break;
 778                 }
 779         }
 780         if (limit <= 0)
 781                 return -EBUSY;
 782
 783         return 0;
 784 }
 785
 786 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 787 {
 788         static const u32 test_pat[4][6] = {
 789         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 790         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 791         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 792         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 793         };
 794         int chan;
 795
 796         for (chan = 0; chan < 4; chan++) {
 797                 int i;
 798
 799                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 800                              (chan * 0x2000) | 0x0200);
 801                 tg3_writephy(tp, 0x16, 0x0002);
 802
 803                 for (i = 0; i < 6; i++)
 804                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 805                                      test_pat[chan][i]);
 806
 807                 tg3_writephy(tp, 0x16, 0x0202);
 808                 if (tg3_wait_macro_done(tp)) {
 809                         *resetp = 1;
 810                         return -EBUSY;
 811                 }
 812
 813                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 814                              (chan * 0x2000) | 0x0200);
 815                 tg3_writephy(tp, 0x16, 0x0082);
 816                 if (tg3_wait_macro_done(tp)) {
 817                         *resetp = 1;
 818                         return -EBUSY;
 819                 }
 820
 821                 tg3_writephy(tp, 0x16, 0x0802);
 822                 if (tg3_wait_macro_done(tp)) {
 823                         *resetp = 1;
 824                         return -EBUSY;
 825                 }
 826
 827                 for (i = 0; i < 6; i += 2) {
 828                         u32 low, high;
 829
 830                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 831                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 832                             tg3_wait_macro_done(tp)) {
 833                                 *resetp = 1;
 834                                 return -EBUSY;
 835                         }
 836                         low &= 0x7fff;
 837                         high &= 0x000f;
 838                         if (low != test_pat[chan][i] ||
 839                             high != test_pat[chan][i+1]) {
 840                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 841                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 842                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 843
 844                                 return -EBUSY;
 845                         }
 846                 }
 847         }
 848
 849         return 0;
 850 }
 851
 852 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 853 {
 854         int chan;
 855
 856         for (chan = 0; chan < 4; chan++) {
 857                 int i;
 858
 859                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 860                              (chan * 0x2000) | 0x0200);
 861                 tg3_writephy(tp, 0x16, 0x0002);
 862                 for (i = 0; i < 6; i++)
 863                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 864                 tg3_writephy(tp, 0x16, 0x0202);
 865                 if (tg3_wait_macro_done(tp))
 866                         return -EBUSY;
 867         }
 868
 869         return 0;
 870 }
 871
 872 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 873 {
 874         u32 reg32, phy9_orig;
 875         int retries, do_phy_reset, err;
 876
 877         retries = 10;
 878         do_phy_reset = 1;
 879         do {
 880                 if (do_phy_reset) {
 881                         err = tg3_bmcr_reset(tp);
 882                         if (err)
 883                                 return err;
 884                         do_phy_reset = 0;
 885                 }
 886
 887                 /* Disable transmitter and interrupt.  */
 888                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 889                         continue;
 890
 891                 reg32 |= 0x3000;
 892                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 893
 894                 /* Set full-duplex, 1000 mbps.  */
 895                 tg3_writephy(tp, MII_BMCR,
 896                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 897
 898                 /* Set to master mode.  */
 899                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 900                         continue;
 901
 902                 tg3_writephy(tp, MII_TG3_CTRL,
 903                              (MII_TG3_CTRL_AS_MASTER |
 904                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 905
 906                 /* Enable SM_DSP_CLOCK and 6dB.  */
 907                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 908
 909                 /* Block the PHY control access.  */
 910                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 911                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 912
 913                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 914                 if (!err)
 915                         break;
 916         } while (--retries);
 917
 918         err = tg3_phy_reset_chanpat(tp);
 919         if (err)
 920                 return err;
 921
 922         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 923         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 924
 925         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 926         tg3_writephy(tp, 0x16, 0x0000);
 927
 928         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 929             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 930                 /* Set Extended packet length bit for jumbo frames */
 931                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 932         }
 933         else {
 934                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 935         }
 936
 937         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 938
 939         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 940                 reg32 &= ~0x3000;
 941                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 942         } else if (!err)
 943                 err = -EBUSY;
 944
 945         return err;
 946 }
 947
 948 static void tg3_link_report(struct tg3 *);
 949
 950 /* This will reset the tigon3 PHY if there is no valid
 951  * link unless the FORCE argument is non-zero.
 952  */
 953 static int tg3_phy_reset(struct tg3 *tp)
 954 {
 955         u32 phy_status;
 956         int err;
 957
 958         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 959                 u32 val;
 960
 961                 val = tr32(GRC_MISC_CFG);
 962                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
 963                 udelay(40);
 964         }
 965         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 966         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 967         if (err != 0)
 968                 return -EBUSY;
 969
 970         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 971                 netif_carrier_off(tp->dev);
 972                 tg3_link_report(tp);
 973         }
 974
 975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 978                 err = tg3_phy_reset_5703_4_5(tp);
 979                 if (err)
 980                         return err;
 981                 goto out;
 982         }
 983
 984         err = tg3_bmcr_reset(tp);
 985         if (err)
 986                 return err;
 987
 988 out:
 989         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 990                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 991                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 992                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 993                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 994                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 996         }
 997         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 998                 tg3_writephy(tp, 0x1c, 0x8d68);
 999                 tg3_writephy(tp, 0x1c, 0x8d68);
1000         }
1001         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010         }
1011         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1014                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016                         tg3_writephy(tp, MII_TG3_TEST1,
1017                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1018                 } else
1019                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021         }
1022         /* Set Extended packet length bit (bit 14) on all chips that */
1023         /* support jumbo frames */
1024         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025                 /* Cannot do read-modify-write on 5401 */
1026                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1027         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1028                 u32 phy_reg;
1029
1030                 /* Set bit 14 with read-modify-write to preserve other bits */
1031                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034         }
1035
1036         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037          * jumbo frames transmission.
1038          */
1039         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1040                 u32 phy_reg;
1041
1042                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045         }
1046
1047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048                 u32 phy_reg;
1049
1050                 /* adjust output voltage */
1051                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054                         u32 phy_reg2;
1055
1056                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058                         /* Enable auto-MDIX */
1059                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062                 }
1063         }
1064
1065         tg3_phy_set_wirespeed(tp);
1066         return 0;
1067 }
1068
1069 static void tg3_frob_aux_power(struct tg3 *tp)
1070 {
1071         struct tg3 *tp_peer = tp;
1072
1073         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1074                 return;
1075
1076         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078                 struct net_device *dev_peer;
1079
1080                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1081                 /* remove_one() may have been run on the peer. */
1082                 if (!dev_peer)
1083                         tp_peer = tp;
1084                 else
1085                         tp_peer = netdev_priv(dev_peer);
1086         }
1087
1088         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1089             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1092                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095                                     (GRC_LCLCTRL_GPIO_OE0 |
1096                                      GRC_LCLCTRL_GPIO_OE1 |
1097                                      GRC_LCLCTRL_GPIO_OE2 |
1098                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1099                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1100                                     100);
1101                 } else {
1102                         u32 no_gpio2;
1103                         u32 grc_local_ctrl = 0;
1104
1105                         if (tp_peer != tp &&
1106                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107                                 return;
1108
1109                         /* Workaround to prevent overdrawing Amps. */
1110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111                             ASIC_REV_5714) {
1112                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1113                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114                                             grc_local_ctrl, 100);
1115                         }
1116
1117                         /* On 5753 and variants, GPIO2 cannot be used. */
1118                         no_gpio2 = tp->nic_sram_data_cfg &
1119                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
1121                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1122                                          GRC_LCLCTRL_GPIO_OE1 |
1123                                          GRC_LCLCTRL_GPIO_OE2 |
1124                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1125                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1126                         if (no_gpio2) {
1127                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1129                         }
1130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131                                                     grc_local_ctrl, 100);
1132
1133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
1135                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136                                                     grc_local_ctrl, 100);
1137
1138                         if (!no_gpio2) {
1139                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1140                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141                                             grc_local_ctrl, 100);
1142                         }
1143                 }
1144         } else {
1145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147                         if (tp_peer != tp &&
1148                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149                                 return;
1150
1151                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152                                     (GRC_LCLCTRL_GPIO_OE1 |
1153                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1154
1155                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156                                     GRC_LCLCTRL_GPIO_OE1, 100);
1157
1158                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159                                     (GRC_LCLCTRL_GPIO_OE1 |
1160                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1161                 }
1162         }
1163 }
1164
1165 static int tg3_setup_phy(struct tg3 *, int);
1166
1167 #define RESET_KIND_SHUTDOWN     0
1168 #define RESET_KIND_INIT         1
1169 #define RESET_KIND_SUSPEND      2
1170
1171 static void tg3_write_sig_post_reset(struct tg3 *, int);
1172 static int tg3_halt_cpu(struct tg3 *, u32);
1173 static int tg3_nvram_lock(struct tg3 *);
1174 static void tg3_nvram_unlock(struct tg3 *);
1175
1176 static void tg3_power_down_phy(struct tg3 *tp)
1177 {
1178         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1179                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1180                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1181                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1182
1183                         sg_dig_ctrl |=
1184                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1185                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1186                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1187                 }
1188                 return;
1189         }
1190
1191         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1192                 u32 val;
1193
1194                 tg3_bmcr_reset(tp);
1195                 val = tr32(GRC_MISC_CFG);
1196                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1197                 udelay(40);
1198                 return;
1199         } else {
1200                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1201                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1202                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1203         }
1204
1205         /* The PHY should not be powered down on some chips because
1206          * of bugs.
1207          */
1208         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1209             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1210             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1211              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1212                 return;
1213         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1214 }
1215
1216 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1217 {
1218         u32 misc_host_ctrl;
1219         u16 power_control, power_caps;
1220         int pm = tp->pm_cap;
1221
1222         /* Make sure register accesses (indirect or otherwise)
1223          * will function correctly.
1224          */
1225         pci_write_config_dword(tp->pdev,
1226                                TG3PCI_MISC_HOST_CTRL,
1227                                tp->misc_host_ctrl);
1228
1229         pci_read_config_word(tp->pdev,
1230                              pm + PCI_PM_CTRL,
1231                              &power_control);
1232         power_control |= PCI_PM_CTRL_PME_STATUS;
1233         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1234         switch (state) {
1235         case PCI_D0:
1236                 power_control |= 0;
1237                 pci_write_config_word(tp->pdev,
1238                                       pm + PCI_PM_CTRL,
1239                                       power_control);
1240                 udelay(100);    /* Delay after power state change */
1241
1242                 /* Switch out of Vaux if it is a NIC */
1243                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1244                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1245
1246                 return 0;
1247
1248         case PCI_D1:
1249                 power_control |= 1;
1250                 break;
1251
1252         case PCI_D2:
1253                 power_control |= 2;
1254                 break;
1255
1256         case PCI_D3hot:
1257                 power_control |= 3;
1258                 break;
1259
1260         default:
1261                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1262                        "requested.\n",
1263                        tp->dev->name, state);
1264                 return -EINVAL;
1265         };
1266
1267         power_control |= PCI_PM_CTRL_PME_ENABLE;
1268
1269         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1270         tw32(TG3PCI_MISC_HOST_CTRL,
1271              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1272
1273         if (tp->link_config.phy_is_low_power == 0) {
1274                 tp->link_config.phy_is_low_power = 1;
1275                 tp->link_config.orig_speed = tp->link_config.speed;
1276                 tp->link_config.orig_duplex = tp->link_config.duplex;
1277                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1278         }
1279
1280         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1281                 tp->link_config.speed = SPEED_10;
1282                 tp->link_config.duplex = DUPLEX_HALF;
1283                 tp->link_config.autoneg = AUTONEG_ENABLE;
1284                 tg3_setup_phy(tp, 0);
1285         }
1286
1287         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1288                 u32 val;
1289
1290                 val = tr32(GRC_VCPU_EXT_CTRL);
1291                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1292         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1293                 int i;
1294                 u32 val;
1295
1296                 for (i = 0; i < 200; i++) {
1297                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1298                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1299                                 break;
1300                         msleep(1);
1301                 }
1302         }
1303         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1304                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1305                                                      WOL_DRV_STATE_SHUTDOWN |
1306                                                      WOL_DRV_WOL |
1307                                                      WOL_SET_MAGIC_PKT);
1308
1309         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1310
1311         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1312                 u32 mac_mode;
1313
1314                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1315                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1316                         udelay(40);
1317
1318                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1319                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1320                         else
1321                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1322
1323                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1324                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1325                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1326                 } else {
1327                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1328                 }
1329
1330                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1331                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1332
1333                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1334                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1335                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1336
1337                 tw32_f(MAC_MODE, mac_mode);
1338                 udelay(100);
1339
1340                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1341                 udelay(10);
1342         }
1343
1344         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1345             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1346              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1347                 u32 base_val;
1348
1349                 base_val = tp->pci_clock_ctrl;
1350                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1351                              CLOCK_CTRL_TXCLK_DISABLE);
1352
1353                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1354                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1355         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1356                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1357                 /* do nothing */
1358         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1359                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1360                 u32 newbits1, newbits2;
1361
1362                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1363                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1364                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1365                                     CLOCK_CTRL_TXCLK_DISABLE |
1366                                     CLOCK_CTRL_ALTCLK);
1367                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1368                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1369                         newbits1 = CLOCK_CTRL_625_CORE;
1370                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1371                 } else {
1372                         newbits1 = CLOCK_CTRL_ALTCLK;
1373                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1374                 }
1375
1376                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1377                             40);
1378
1379                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1380                             40);
1381
1382                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1383                         u32 newbits3;
1384
1385                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1386                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1387                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1388                                             CLOCK_CTRL_TXCLK_DISABLE |
1389                                             CLOCK_CTRL_44MHZ_CORE);
1390                         } else {
1391                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1392                         }
1393
1394                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1395                                     tp->pci_clock_ctrl | newbits3, 40);
1396                 }
1397         }
1398
1399         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1400             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1401                 tg3_power_down_phy(tp);
1402
1403         tg3_frob_aux_power(tp);
1404
1405         /* Workaround for unstable PLL clock */
1406         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1407             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1408                 u32 val = tr32(0x7d00);
1409
1410                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1411                 tw32(0x7d00, val);
1412                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1413                         int err;
1414
1415                         err = tg3_nvram_lock(tp);
1416                         tg3_halt_cpu(tp, RX_CPU_BASE);
1417                         if (!err)
1418                                 tg3_nvram_unlock(tp);
1419                 }
1420         }
1421
1422         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1423
1424         /* Finally, set the new power state. */
1425         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1426         udelay(100);    /* Delay after power state change */
1427
1428         return 0;
1429 }
1430
1431 static void tg3_link_report(struct tg3 *tp)
1432 {
1433         if (!netif_carrier_ok(tp->dev)) {
1434                 if (netif_msg_link(tp))
1435                         printk(KERN_INFO PFX "%s: Link is down.\n",
1436                                tp->dev->name);
1437         } else if (netif_msg_link(tp)) {
1438                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1439                        tp->dev->name,
1440                        (tp->link_config.active_speed == SPEED_1000 ?
1441                         1000 :
1442                         (tp->link_config.active_speed == SPEED_100 ?
1443                          100 : 10)),
1444                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1445                         "full" : "half"));
1446
1447                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1448                        "%s for RX.\n",
1449                        tp->dev->name,
1450                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1451                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1452         }
1453 }
1454
1455 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1456 {
1457         u32 new_tg3_flags = 0;
1458         u32 old_rx_mode = tp->rx_mode;
1459         u32 old_tx_mode = tp->tx_mode;
1460
1461         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1462
1463                 /* Convert 1000BaseX flow control bits to 1000BaseT
1464                  * bits before resolving flow control.
1465                  */
1466                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1467                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1468                                        ADVERTISE_PAUSE_ASYM);
1469                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1470
1471                         if (local_adv & ADVERTISE_1000XPAUSE)
1472                                 local_adv |= ADVERTISE_PAUSE_CAP;
1473                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1474                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1475                         if (remote_adv & LPA_1000XPAUSE)
1476                                 remote_adv |= LPA_PAUSE_CAP;
1477                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1478                                 remote_adv |= LPA_PAUSE_ASYM;
1479                 }
1480
1481                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1482                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1483                                 if (remote_adv & LPA_PAUSE_CAP)
1484                                         new_tg3_flags |=
1485                                                 (TG3_FLAG_RX_PAUSE |
1486                                                 TG3_FLAG_TX_PAUSE);
1487                                 else if (remote_adv & LPA_PAUSE_ASYM)
1488                                         new_tg3_flags |=
1489                                                 (TG3_FLAG_RX_PAUSE);
1490                         } else {
1491                                 if (remote_adv & LPA_PAUSE_CAP)
1492                                         new_tg3_flags |=
1493                                                 (TG3_FLAG_RX_PAUSE |
1494                                                 TG3_FLAG_TX_PAUSE);
1495                         }
1496                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1497                         if ((remote_adv & LPA_PAUSE_CAP) &&
1498                         (remote_adv & LPA_PAUSE_ASYM))
1499                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1500                 }
1501
1502                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1503                 tp->tg3_flags |= new_tg3_flags;
1504         } else {
1505                 new_tg3_flags = tp->tg3_flags;
1506         }
1507
1508         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1509                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1510         else
1511                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1512
1513         if (old_rx_mode != tp->rx_mode) {
1514                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1515         }
1516
1517         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1518                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1519         else
1520                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1521
1522         if (old_tx_mode != tp->tx_mode) {
1523                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1524         }
1525 }
1526
1527 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1528 {
1529         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1530         case MII_TG3_AUX_STAT_10HALF:
1531                 *speed = SPEED_10;
1532                 *duplex = DUPLEX_HALF;
1533                 break;
1534
1535         case MII_TG3_AUX_STAT_10FULL:
1536                 *speed = SPEED_10;
1537                 *duplex = DUPLEX_FULL;
1538                 break;
1539
1540         case MII_TG3_AUX_STAT_100HALF:
1541                 *speed = SPEED_100;
1542                 *duplex = DUPLEX_HALF;
1543                 break;
1544
1545         case MII_TG3_AUX_STAT_100FULL:
1546                 *speed = SPEED_100;
1547                 *duplex = DUPLEX_FULL;
1548                 break;
1549
1550         case MII_TG3_AUX_STAT_1000HALF:
1551                 *speed = SPEED_1000;
1552                 *duplex = DUPLEX_HALF;
1553                 break;
1554
1555         case MII_TG3_AUX_STAT_1000FULL:
1556                 *speed = SPEED_1000;
1557                 *duplex = DUPLEX_FULL;
1558                 break;
1559
1560         default:
1561                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1562                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1563                                  SPEED_10;
1564                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1565                                   DUPLEX_HALF;
1566                         break;
1567                 }
1568                 *speed = SPEED_INVALID;
1569                 *duplex = DUPLEX_INVALID;
1570                 break;
1571         };
1572 }
1573
1574 static void tg3_phy_copper_begin(struct tg3 *tp)
1575 {
1576         u32 new_adv;
1577         int i;
1578
1579         if (tp->link_config.phy_is_low_power) {
1580                 /* Entering low power mode.  Disable gigabit and
1581                  * 100baseT advertisements.
1582                  */
1583                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1584
1585                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1586                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1587                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1588                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1589
1590                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1591         } else if (tp->link_config.speed == SPEED_INVALID) {
1592                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1593                         tp->link_config.advertising &=
1594                                 ~(ADVERTISED_1000baseT_Half |
1595                                   ADVERTISED_1000baseT_Full);
1596
1597                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1598                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1599                         new_adv |= ADVERTISE_10HALF;
1600                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1601                         new_adv |= ADVERTISE_10FULL;
1602                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1603                         new_adv |= ADVERTISE_100HALF;
1604                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1605                         new_adv |= ADVERTISE_100FULL;
1606                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1607
1608                 if (tp->link_config.advertising &
1609                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1610                         new_adv = 0;
1611                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1612                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1613                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1614                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1615                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1616                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1617                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1618                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1619                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1620                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1621                 } else {
1622                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1623                 }
1624         } else {
1625                 /* Asking for a specific link mode. */
1626                 if (tp->link_config.speed == SPEED_1000) {
1627                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1628                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1629
1630                         if (tp->link_config.duplex == DUPLEX_FULL)
1631                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1632                         else
1633                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1634                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1635                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1636                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1637                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1638                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1639                 } else {
1640                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1641
1642                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1643                         if (tp->link_config.speed == SPEED_100) {
1644                                 if (tp->link_config.duplex == DUPLEX_FULL)
1645                                         new_adv |= ADVERTISE_100FULL;
1646                                 else
1647                                         new_adv |= ADVERTISE_100HALF;
1648                         } else {
1649                                 if (tp->link_config.duplex == DUPLEX_FULL)
1650                                         new_adv |= ADVERTISE_10FULL;
1651                                 else
1652                                         new_adv |= ADVERTISE_10HALF;
1653                         }
1654                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1655                 }
1656         }
1657
1658         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1659             tp->link_config.speed != SPEED_INVALID) {
1660                 u32 bmcr, orig_bmcr;
1661
1662                 tp->link_config.active_speed = tp->link_config.speed;
1663                 tp->link_config.active_duplex = tp->link_config.duplex;
1664
1665                 bmcr = 0;
1666                 switch (tp->link_config.speed) {
1667                 default:
1668                 case SPEED_10:
1669                         break;
1670
1671                 case SPEED_100:
1672                         bmcr |= BMCR_SPEED100;
1673                         break;
1674
1675                 case SPEED_1000:
1676                         bmcr |= TG3_BMCR_SPEED1000;
1677                         break;
1678                 };
1679
1680                 if (tp->link_config.duplex == DUPLEX_FULL)
1681                         bmcr |= BMCR_FULLDPLX;
1682
1683                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1684                     (bmcr != orig_bmcr)) {
1685                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1686                         for (i = 0; i < 1500; i++) {
1687                                 u32 tmp;
1688
1689                                 udelay(10);
1690                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1691                                     tg3_readphy(tp, MII_BMSR, &tmp))
1692                                         continue;
1693                                 if (!(tmp & BMSR_LSTATUS)) {
1694                                         udelay(40);
1695                                         break;
1696                                 }
1697                         }
1698                         tg3_writephy(tp, MII_BMCR, bmcr);
1699                         udelay(40);
1700                 }
1701         } else {
1702                 tg3_writephy(tp, MII_BMCR,
1703                              BMCR_ANENABLE | BMCR_ANRESTART);
1704         }
1705 }
1706
1707 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1708 {
1709         int err;
1710
1711         /* Turn off tap power management. */
1712         /* Set Extended packet length bit */
1713         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1714
1715         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1716         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1717
1718         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1719         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1720
1721         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1722         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1723
1724         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1725         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1726
1727         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1728         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1729
1730         udelay(40);
1731
1732         return err;
1733 }
1734
1735 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1736 {
1737         u32 adv_reg, all_mask = 0;
1738
1739         if (mask & ADVERTISED_10baseT_Half)
1740                 all_mask |= ADVERTISE_10HALF;
1741         if (mask & ADVERTISED_10baseT_Full)
1742                 all_mask |= ADVERTISE_10FULL;
1743         if (mask & ADVERTISED_100baseT_Half)
1744                 all_mask |= ADVERTISE_100HALF;
1745         if (mask & ADVERTISED_100baseT_Full)
1746                 all_mask |= ADVERTISE_100FULL;
1747
1748         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1749                 return 0;
1750
1751         if ((adv_reg & all_mask) != all_mask)
1752                 return 0;
1753         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1754                 u32 tg3_ctrl;
1755
1756                 all_mask = 0;
1757                 if (mask & ADVERTISED_1000baseT_Half)
1758                         all_mask |= ADVERTISE_1000HALF;
1759                 if (mask & ADVERTISED_1000baseT_Full)
1760                         all_mask |= ADVERTISE_1000FULL;
1761
1762                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1763                         return 0;
1764
1765                 if ((tg3_ctrl & all_mask) != all_mask)
1766                         return 0;
1767         }
1768         return 1;
1769 }
1770
1771 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1772 {
1773         int current_link_up;
1774         u32 bmsr, dummy;
1775         u16 current_speed;
1776         u8 current_duplex;
1777         int i, err;
1778
1779         tw32(MAC_EVENT, 0);
1780
1781         tw32_f(MAC_STATUS,
1782              (MAC_STATUS_SYNC_CHANGED |
1783               MAC_STATUS_CFG_CHANGED |
1784               MAC_STATUS_MI_COMPLETION |
1785               MAC_STATUS_LNKSTATE_CHANGED));
1786         udelay(40);
1787
1788         tp->mi_mode = MAC_MI_MODE_BASE;
1789         tw32_f(MAC_MI_MODE, tp->mi_mode);
1790         udelay(80);
1791
1792         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1793
1794         /* Some third-party PHYs need to be reset on link going
1795          * down.
1796          */
1797         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1798              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1799              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1800             netif_carrier_ok(tp->dev)) {
1801                 tg3_readphy(tp, MII_BMSR, &bmsr);
1802                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1803                     !(bmsr & BMSR_LSTATUS))
1804                         force_reset = 1;
1805         }
1806         if (force_reset)
1807                 tg3_phy_reset(tp);
1808
1809         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1810                 tg3_readphy(tp, MII_BMSR, &bmsr);
1811                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1812                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1813                         bmsr = 0;
1814
1815                 if (!(bmsr & BMSR_LSTATUS)) {
1816                         err = tg3_init_5401phy_dsp(tp);
1817                         if (err)
1818                                 return err;
1819
1820                         tg3_readphy(tp, MII_BMSR, &bmsr);
1821                         for (i = 0; i < 1000; i++) {
1822                                 udelay(10);
1823                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1824                                     (bmsr & BMSR_LSTATUS)) {
1825                                         udelay(40);
1826                                         break;
1827                                 }
1828                         }
1829
1830                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1831                             !(bmsr & BMSR_LSTATUS) &&
1832                             tp->link_config.active_speed == SPEED_1000) {
1833                                 err = tg3_phy_reset(tp);
1834                                 if (!err)
1835                                         err = tg3_init_5401phy_dsp(tp);
1836                                 if (err)
1837                                         return err;
1838                         }
1839                 }
1840         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1841                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1842                 /* 5701 {A0,B0} CRC bug workaround */
1843                 tg3_writephy(tp, 0x15, 0x0a75);
1844                 tg3_writephy(tp, 0x1c, 0x8c68);
1845                 tg3_writephy(tp, 0x1c, 0x8d68);
1846                 tg3_writephy(tp, 0x1c, 0x8c68);
1847         }
1848
1849         /* Clear pending interrupts... */
1850         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1851         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1852
1853         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1854                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1855         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1856                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1857
1858         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1859             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1860                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1861                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1862                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1863                 else
1864                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1865         }
1866
1867         current_link_up = 0;
1868         current_speed = SPEED_INVALID;
1869         current_duplex = DUPLEX_INVALID;
1870
1871         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1872                 u32 val;
1873
1874                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1875                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1876                 if (!(val & (1 << 10))) {
1877                         val |= (1 << 10);
1878                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1879                         goto relink;
1880                 }
1881         }
1882
1883         bmsr = 0;
1884         for (i = 0; i < 100; i++) {
1885                 tg3_readphy(tp, MII_BMSR, &bmsr);
1886                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1887                     (bmsr & BMSR_LSTATUS))
1888                         break;
1889                 udelay(40);
1890         }
1891
1892         if (bmsr & BMSR_LSTATUS) {
1893                 u32 aux_stat, bmcr;
1894
1895                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1896                 for (i = 0; i < 2000; i++) {
1897                         udelay(10);
1898                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1899                             aux_stat)
1900                                 break;
1901                 }
1902
1903                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1904                                              &current_speed,
1905                                              &current_duplex);
1906
1907                 bmcr = 0;
1908                 for (i = 0; i < 200; i++) {
1909                         tg3_readphy(tp, MII_BMCR, &bmcr);
1910                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1911                                 continue;
1912                         if (bmcr && bmcr != 0x7fff)
1913                                 break;
1914                         udelay(10);
1915                 }
1916
1917                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1918                         if (bmcr & BMCR_ANENABLE) {
1919                                 current_link_up = 1;
1920
1921                                 /* Force autoneg restart if we are exiting
1922                                  * low power mode.
1923                                  */
1924                                 if (!tg3_copper_is_advertising_all(tp,
1925                                                 tp->link_config.advertising))
1926                                         current_link_up = 0;
1927                         } else {
1928                                 current_link_up = 0;
1929                         }
1930                 } else {
1931                         if (!(bmcr & BMCR_ANENABLE) &&
1932                             tp->link_config.speed == current_speed &&
1933                             tp->link_config.duplex == current_duplex) {
1934                                 current_link_up = 1;
1935                         } else {
1936                                 current_link_up = 0;
1937                         }
1938                 }
1939
1940                 tp->link_config.active_speed = current_speed;
1941                 tp->link_config.active_duplex = current_duplex;
1942         }
1943
1944         if (current_link_up == 1 &&
1945             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1946             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1947                 u32 local_adv, remote_adv;
1948
1949                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1950                         local_adv = 0;
1951                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1952
1953                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1954                         remote_adv = 0;
1955
1956                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1957
1958                 /* If we are not advertising full pause capability,
1959                  * something is wrong.  Bring the link down and reconfigure.
1960                  */
1961                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1962                         current_link_up = 0;
1963                 } else {
1964                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1965                 }
1966         }
1967 relink:
1968         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1969                 u32 tmp;
1970
1971                 tg3_phy_copper_begin(tp);
1972
1973                 tg3_readphy(tp, MII_BMSR, &tmp);
1974                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1975                     (tmp & BMSR_LSTATUS))
1976                         current_link_up = 1;
1977         }
1978
1979         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1980         if (current_link_up == 1) {
1981                 if (tp->link_config.active_speed == SPEED_100 ||
1982                     tp->link_config.active_speed == SPEED_10)
1983                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1984                 else
1985                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1986         } else
1987                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1988
1989         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1990         if (tp->link_config.active_duplex == DUPLEX_HALF)
1991                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1992
1993         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1994         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1995                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1996                     (current_link_up == 1 &&
1997                      tp->link_config.active_speed == SPEED_10))
1998                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1999         } else {
2000                 if (current_link_up == 1)
2001                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2002         }
2003
2004         /* ??? Without this setting Netgear GA302T PHY does not
2005          * ??? send/receive packets...
2006          */
2007         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2008             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2009                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2010                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2011                 udelay(80);
2012         }
2013
2014         tw32_f(MAC_MODE, tp->mac_mode);
2015         udelay(40);
2016
2017         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2018                 /* Polled via timer. */
2019                 tw32_f(MAC_EVENT, 0);
2020         } else {
2021                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2022         }
2023         udelay(40);
2024
2025         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2026             current_link_up == 1 &&
2027             tp->link_config.active_speed == SPEED_1000 &&
2028             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2029              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2030                 udelay(120);
2031                 tw32_f(MAC_STATUS,
2032                      (MAC_STATUS_SYNC_CHANGED |
2033                       MAC_STATUS_CFG_CHANGED));
2034                 udelay(40);
2035                 tg3_write_mem(tp,
2036                               NIC_SRAM_FIRMWARE_MBOX,
2037                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2038         }
2039
2040         if (current_link_up != netif_carrier_ok(tp->dev)) {
2041                 if (current_link_up)
2042                         netif_carrier_on(tp->dev);
2043                 else
2044                         netif_carrier_off(tp->dev);
2045                 tg3_link_report(tp);
2046         }
2047
2048         return 0;
2049 }
2050
2051 struct tg3_fiber_aneginfo {
2052         int state;
2053 #define ANEG_STATE_UNKNOWN              0
2054 #define ANEG_STATE_AN_ENABLE            1
2055 #define ANEG_STATE_RESTART_INIT         2
2056 #define ANEG_STATE_RESTART              3
2057 #define ANEG_STATE_DISABLE_LINK_OK      4
2058 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2059 #define ANEG_STATE_ABILITY_DETECT       6
2060 #define ANEG_STATE_ACK_DETECT_INIT      7
2061 #define ANEG_STATE_ACK_DETECT           8
2062 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2063 #define ANEG_STATE_COMPLETE_ACK         10
2064 #define ANEG_STATE_IDLE_DETECT_INIT     11
2065 #define ANEG_STATE_IDLE_DETECT          12
2066 #define ANEG_STATE_LINK_OK              13
2067 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2068 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2069
2070         u32 flags;
2071 #define MR_AN_ENABLE            0x00000001
2072 #define MR_RESTART_AN           0x00000002
2073 #define MR_AN_COMPLETE          0x00000004
2074 #define MR_PAGE_RX              0x00000008
2075 #define MR_NP_LOADED            0x00000010
2076 #define MR_TOGGLE_TX            0x00000020
2077 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2078 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2079 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2080 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2081 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2082 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2083 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2084 #define MR_TOGGLE_RX            0x00002000
2085 #define MR_NP_RX                0x00004000
2086
2087 #define MR_LINK_OK              0x80000000
2088
2089         unsigned long link_time, cur_time;
2090
2091         u32 ability_match_cfg;
2092         int ability_match_count;
2093
2094         char ability_match, idle_match, ack_match;
2095
2096         u32 txconfig, rxconfig;
2097 #define ANEG_CFG_NP             0x00000080
2098 #define ANEG_CFG_ACK            0x00000040
2099 #define ANEG_CFG_RF2            0x00000020
2100 #define ANEG_CFG_RF1            0x00000010
2101 #define ANEG_CFG_PS2            0x00000001
2102 #define ANEG_CFG_PS1            0x00008000
2103 #define ANEG_CFG_HD             0x00004000
2104 #define ANEG_CFG_FD             0x00002000
2105 #define ANEG_CFG_INVAL          0x00001f06
2106
2107 };
2108 #define ANEG_OK         0
2109 #define ANEG_DONE       1
2110 #define ANEG_TIMER_ENAB 2
2111 #define ANEG_FAILED     -1
2112
2113 #define ANEG_STATE_SETTLE_TIME  10000
2114
2115 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2116                                    struct tg3_fiber_aneginfo *ap)
2117 {
2118         unsigned long delta;
2119         u32 rx_cfg_reg;
2120         int ret;
2121
2122         if (ap->state == ANEG_STATE_UNKNOWN) {
2123                 ap->rxconfig = 0;
2124                 ap->link_time = 0;
2125                 ap->cur_time = 0;
2126                 ap->ability_match_cfg = 0;
2127                 ap->ability_match_count = 0;
2128                 ap->ability_match = 0;
2129                 ap->idle_match = 0;
2130                 ap->ack_match = 0;
2131         }
2132         ap->cur_time++;
2133
2134         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2135                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2136
2137                 if (rx_cfg_reg != ap->ability_match_cfg) {
2138                         ap->ability_match_cfg = rx_cfg_reg;
2139                         ap->ability_match = 0;
2140                         ap->ability_match_count = 0;
2141                 } else {
2142                         if (++ap->ability_match_count > 1) {
2143                                 ap->ability_match = 1;
2144                                 ap->ability_match_cfg = rx_cfg_reg;
2145                         }
2146                 }
2147                 if (rx_cfg_reg & ANEG_CFG_ACK)
2148                         ap->ack_match = 1;
2149                 else
2150                         ap->ack_match = 0;
2151
2152                 ap->idle_match = 0;
2153         } else {
2154                 ap->idle_match = 1;
2155                 ap->ability_match_cfg = 0;
2156                 ap->ability_match_count = 0;
2157                 ap->ability_match = 0;
2158                 ap->ack_match = 0;
2159
2160                 rx_cfg_reg = 0;
2161         }
2162
2163         ap->rxconfig = rx_cfg_reg;
2164         ret = ANEG_OK;
2165
2166         switch(ap->state) {
2167         case ANEG_STATE_UNKNOWN:
2168                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2169                         ap->state = ANEG_STATE_AN_ENABLE;
2170
2171                 /* fallthru */
2172         case ANEG_STATE_AN_ENABLE:
2173                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2174                 if (ap->flags & MR_AN_ENABLE) {
2175                         ap->link_time = 0;
2176                         ap->cur_time = 0;
2177                         ap->ability_match_cfg = 0;
2178                         ap->ability_match_count = 0;
2179                         ap->ability_match = 0;
2180                         ap->idle_match = 0;
2181                         ap->ack_match = 0;
2182
2183                         ap->state = ANEG_STATE_RESTART_INIT;
2184                 } else {
2185                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2186                 }
2187                 break;
2188
2189         case ANEG_STATE_RESTART_INIT:
2190                 ap->link_time = ap->cur_time;
2191                 ap->flags &= ~(MR_NP_LOADED);
2192                 ap->txconfig = 0;
2193                 tw32(MAC_TX_AUTO_NEG, 0);
2194                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2195                 tw32_f(MAC_MODE, tp->mac_mode);
2196                 udelay(40);
2197
2198                 ret = ANEG_TIMER_ENAB;
2199                 ap->state = ANEG_STATE_RESTART;
2200
2201                 /* fallthru */
2202         case ANEG_STATE_RESTART:
2203                 delta = ap->cur_time - ap->link_time;
2204                 if (delta > ANEG_STATE_SETTLE_TIME) {
2205                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2206                 } else {
2207                         ret = ANEG_TIMER_ENAB;
2208                 }
2209                 break;
2210
2211         case ANEG_STATE_DISABLE_LINK_OK:
2212                 ret = ANEG_DONE;
2213                 break;
2214
2215         case ANEG_STATE_ABILITY_DETECT_INIT:
2216                 ap->flags &= ~(MR_TOGGLE_TX);
2217                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2218                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2219                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2220                 tw32_f(MAC_MODE, tp->mac_mode);
2221                 udelay(40);
2222
2223                 ap->state = ANEG_STATE_ABILITY_DETECT;
2224                 break;
2225
2226         case ANEG_STATE_ABILITY_DETECT:
2227                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2228                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2229                 }
2230                 break;
2231
2232         case ANEG_STATE_ACK_DETECT_INIT:
2233                 ap->txconfig |= ANEG_CFG_ACK;
2234                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2235                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2236                 tw32_f(MAC_MODE, tp->mac_mode);
2237                 udelay(40);
2238
2239                 ap->state = ANEG_STATE_ACK_DETECT;
2240
2241                 /* fallthru */
2242         case ANEG_STATE_ACK_DETECT:
2243                 if (ap->ack_match != 0) {
2244                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2245                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2246                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2247                         } else {
2248                                 ap->state = ANEG_STATE_AN_ENABLE;
2249                         }
2250                 } else if (ap->ability_match != 0 &&
2251                            ap->rxconfig == 0) {
2252                         ap->state = ANEG_STATE_AN_ENABLE;
2253                 }
2254                 break;
2255
2256         case ANEG_STATE_COMPLETE_ACK_INIT:
2257                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2258                         ret = ANEG_FAILED;
2259                         break;
2260                 }
2261                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2262                                MR_LP_ADV_HALF_DUPLEX |
2263                                MR_LP_ADV_SYM_PAUSE |
2264                                MR_LP_ADV_ASYM_PAUSE |
2265                                MR_LP_ADV_REMOTE_FAULT1 |
2266                                MR_LP_ADV_REMOTE_FAULT2 |
2267                                MR_LP_ADV_NEXT_PAGE |
2268                                MR_TOGGLE_RX |
2269                                MR_NP_RX);
2270                 if (ap->rxconfig & ANEG_CFG_FD)
2271                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2272                 if (ap->rxconfig & ANEG_CFG_HD)
2273                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2274                 if (ap->rxconfig & ANEG_CFG_PS1)
2275                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2276                 if (ap->rxconfig & ANEG_CFG_PS2)
2277                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2278                 if (ap->rxconfig & ANEG_CFG_RF1)
2279                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2280                 if (ap->rxconfig & ANEG_CFG_RF2)
2281                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2282                 if (ap->rxconfig & ANEG_CFG_NP)
2283                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2284
2285                 ap->link_time = ap->cur_time;
2286
2287                 ap->flags ^= (MR_TOGGLE_TX);
2288                 if (ap->rxconfig & 0x0008)
2289                         ap->flags |= MR_TOGGLE_RX;
2290                 if (ap->rxconfig & ANEG_CFG_NP)
2291                         ap->flags |= MR_NP_RX;
2292                 ap->flags |= MR_PAGE_RX;
2293
2294                 ap->state = ANEG_STATE_COMPLETE_ACK;
2295                 ret = ANEG_TIMER_ENAB;
2296                 break;
2297
2298         case ANEG_STATE_COMPLETE_ACK:
2299                 if (ap->ability_match != 0 &&
2300                     ap->rxconfig == 0) {
2301                         ap->state = ANEG_STATE_AN_ENABLE;
2302                         break;
2303                 }
2304                 delta = ap->cur_time - ap->link_time;
2305                 if (delta > ANEG_STATE_SETTLE_TIME) {
2306                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2307                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2308                         } else {
2309                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2310                                     !(ap->flags & MR_NP_RX)) {
2311                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2312                                 } else {
2313                                         ret = ANEG_FAILED;
2314                                 }
2315                         }
2316                 }
2317                 break;
2318
2319         case ANEG_STATE_IDLE_DETECT_INIT:
2320                 ap->link_time = ap->cur_time;
2321                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2322                 tw32_f(MAC_MODE, tp->mac_mode);
2323                 udelay(40);
2324
2325                 ap->state = ANEG_STATE_IDLE_DETECT;
2326                 ret = ANEG_TIMER_ENAB;
2327                 break;
2328
2329         case ANEG_STATE_IDLE_DETECT:
2330                 if (ap->ability_match != 0 &&
2331                     ap->rxconfig == 0) {
2332                         ap->state = ANEG_STATE_AN_ENABLE;
2333                         break;
2334                 }
2335                 delta = ap->cur_time - ap->link_time;
2336                 if (delta > ANEG_STATE_SETTLE_TIME) {
2337                         /* XXX another gem from the Broadcom driver :( */
2338                         ap->state = ANEG_STATE_LINK_OK;
2339                 }
2340                 break;
2341
2342         case ANEG_STATE_LINK_OK:
2343                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2344                 ret = ANEG_DONE;
2345                 break;
2346
2347         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2348                 /* ??? unimplemented */
2349                 break;
2350
2351         case ANEG_STATE_NEXT_PAGE_WAIT:
2352                 /* ??? unimplemented */
2353                 break;
2354
2355         default:
2356                 ret = ANEG_FAILED;
2357                 break;
2358         };
2359
2360         return ret;
2361 }
2362
2363 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2364 {
2365         int res = 0;
2366         struct tg3_fiber_aneginfo aninfo;
2367         int status = ANEG_FAILED;
2368         unsigned int tick;
2369         u32 tmp;
2370
2371         tw32_f(MAC_TX_AUTO_NEG, 0);
2372
2373         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2374         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2375         udelay(40);
2376
2377         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2378         udelay(40);
2379
2380         memset(&aninfo, 0, sizeof(aninfo));
2381         aninfo.flags |= MR_AN_ENABLE;
2382         aninfo.state = ANEG_STATE_UNKNOWN;
2383         aninfo.cur_time = 0;
2384         tick = 0;
2385         while (++tick < 195000) {
2386                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2387                 if (status == ANEG_DONE || status == ANEG_FAILED)
2388                         break;
2389
2390                 udelay(1);
2391         }
2392
2393         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2394         tw32_f(MAC_MODE, tp->mac_mode);
2395         udelay(40);
2396
2397         *flags = aninfo.flags;
2398
2399         if (status == ANEG_DONE &&
2400             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2401                              MR_LP_ADV_FULL_DUPLEX)))
2402                 res = 1;
2403
2404         return res;
2405 }
2406
2407 static void tg3_init_bcm8002(struct tg3 *tp)
2408 {
2409         u32 mac_status = tr32(MAC_STATUS);
2410         int i;
2411
2412         /* Reset when initting first time or we have a link. */
2413         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2414             !(mac_status & MAC_STATUS_PCS_SYNCED))
2415                 return;
2416
2417         /* Set PLL lock range. */
2418         tg3_writephy(tp, 0x16, 0x8007);
2419
2420         /* SW reset */
2421         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2422
2423         /* Wait for reset to complete. */
2424         /* XXX schedule_timeout() ... */
2425         for (i = 0; i < 500; i++)
2426                 udelay(10);
2427
2428         /* Config mode; select PMA/Ch 1 regs. */
2429         tg3_writephy(tp, 0x10, 0x8411);
2430
2431         /* Enable auto-lock and comdet, select txclk for tx. */
2432         tg3_writephy(tp, 0x11, 0x0a10);
2433
2434         tg3_writephy(tp, 0x18, 0x00a0);
2435         tg3_writephy(tp, 0x16, 0x41ff);
2436
2437         /* Assert and deassert POR. */
2438         tg3_writephy(tp, 0x13, 0x0400);
2439         udelay(40);
2440         tg3_writephy(tp, 0x13, 0x0000);
2441
2442         tg3_writephy(tp, 0x11, 0x0a50);
2443         udelay(40);
2444         tg3_writephy(tp, 0x11, 0x0a10);
2445
2446         /* Wait for signal to stabilize */
2447         /* XXX schedule_timeout() ... */
2448         for (i = 0; i < 15000; i++)
2449                 udelay(10);
2450
2451         /* Deselect the channel register so we can read the PHYID
2452          * later.
2453          */
2454         tg3_writephy(tp, 0x10, 0x8011);
2455 }
2456
2457 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2458 {
2459         u32 sg_dig_ctrl, sg_dig_status;
2460         u32 serdes_cfg, expected_sg_dig_ctrl;
2461         int workaround, port_a;
2462         int current_link_up;
2463
2464         serdes_cfg = 0;
2465         expected_sg_dig_ctrl = 0;
2466         workaround = 0;
2467         port_a = 1;
2468         current_link_up = 0;
2469
2470         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2471             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2472                 workaround = 1;
2473                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2474                         port_a = 0;
2475
2476                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2477                 /* preserve bits 20-23 for voltage regulator */
2478                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2479         }
2480
2481         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2482
2483         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2484                 if (sg_dig_ctrl & (1 << 31)) {
2485                         if (workaround) {
2486                                 u32 val = serdes_cfg;
2487
2488                                 if (port_a)
2489                                         val |= 0xc010000;
2490                                 else
2491                                         val |= 0x4010000;
2492                                 tw32_f(MAC_SERDES_CFG, val);
2493                         }
2494                         tw32_f(SG_DIG_CTRL, 0x01388400);
2495                 }
2496                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2497                         tg3_setup_flow_control(tp, 0, 0);
2498                         current_link_up = 1;
2499                 }
2500                 goto out;
2501         }
2502
2503         /* Want auto-negotiation.  */
2504         expected_sg_dig_ctrl = 0x81388400;
2505
2506         /* Pause capability */
2507         expected_sg_dig_ctrl |= (1 << 11);
2508
2509         /* Asymettric pause */
2510         expected_sg_dig_ctrl |= (1 << 12);
2511
2512         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2513                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2514                     tp->serdes_counter &&
2515                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2516                                     MAC_STATUS_RCVD_CFG)) ==
2517                      MAC_STATUS_PCS_SYNCED)) {
2518                         tp->serdes_counter--;
2519                         current_link_up = 1;
2520                         goto out;
2521                 }
2522 restart_autoneg:
2523                 if (workaround)
2524                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2525                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2526                 udelay(5);
2527                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2528
2529                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2530                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2531         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2532                                  MAC_STATUS_SIGNAL_DET)) {
2533                 sg_dig_status = tr32(SG_DIG_STATUS);
2534                 mac_status = tr32(MAC_STATUS);
2535
2536                 if ((sg_dig_status & (1 << 1)) &&
2537                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2538                         u32 local_adv, remote_adv;
2539
2540                         local_adv = ADVERTISE_PAUSE_CAP;
2541                         remote_adv = 0;
2542                         if (sg_dig_status & (1 << 19))
2543                                 remote_adv |= LPA_PAUSE_CAP;
2544                         if (sg_dig_status & (1 << 20))
2545                                 remote_adv |= LPA_PAUSE_ASYM;
2546
2547                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2548                         current_link_up = 1;
2549                         tp->serdes_counter = 0;
2550                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2551                 } else if (!(sg_dig_status & (1 << 1))) {
2552                         if (tp->serdes_counter)
2553                                 tp->serdes_counter--;
2554                         else {
2555                                 if (workaround) {
2556                                         u32 val = serdes_cfg;
2557
2558                                         if (port_a)
2559                                                 val |= 0xc010000;
2560                                         else
2561                                                 val |= 0x4010000;
2562
2563                                         tw32_f(MAC_SERDES_CFG, val);
2564                                 }
2565
2566                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2567                                 udelay(40);
2568
2569                                 /* Link parallel detection - link is up */
2570                                 /* only if we have PCS_SYNC and not */
2571                                 /* receiving config code words */
2572                                 mac_status = tr32(MAC_STATUS);
2573                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2574                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2575                                         tg3_setup_flow_control(tp, 0, 0);
2576                                         current_link_up = 1;
2577                                         tp->tg3_flags2 |=
2578                                                 TG3_FLG2_PARALLEL_DETECT;
2579                                         tp->serdes_counter =
2580                                                 SERDES_PARALLEL_DET_TIMEOUT;
2581                                 } else
2582                                         goto restart_autoneg;
2583                         }
2584                 }
2585         } else {
2586                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2587                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2588         }
2589
2590 out:
2591         return current_link_up;
2592 }
2593
2594 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2595 {
2596         int current_link_up = 0;
2597
2598         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2599                 goto out;
2600
2601         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2602                 u32 flags;
2603                 int i;
2604
2605                 if (fiber_autoneg(tp, &flags)) {
2606                         u32 local_adv, remote_adv;
2607
2608                         local_adv = ADVERTISE_PAUSE_CAP;
2609                         remote_adv = 0;
2610                         if (flags & MR_LP_ADV_SYM_PAUSE)
2611                                 remote_adv |= LPA_PAUSE_CAP;
2612                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2613                                 remote_adv |= LPA_PAUSE_ASYM;
2614
2615                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2616
2617                         current_link_up = 1;
2618                 }
2619                 for (i = 0; i < 30; i++) {
2620                         udelay(20);
2621                         tw32_f(MAC_STATUS,
2622                                (MAC_STATUS_SYNC_CHANGED |
2623                                 MAC_STATUS_CFG_CHANGED));
2624                         udelay(40);
2625                         if ((tr32(MAC_STATUS) &
2626                              (MAC_STATUS_SYNC_CHANGED |
2627                               MAC_STATUS_CFG_CHANGED)) == 0)
2628                                 break;
2629                 }
2630
2631                 mac_status = tr32(MAC_STATUS);
2632                 if (current_link_up == 0 &&
2633                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2634                     !(mac_status & MAC_STATUS_RCVD_CFG))
2635                         current_link_up = 1;
2636         } else {
2637                 /* Forcing 1000FD link up. */
2638                 current_link_up = 1;
2639
2640                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2641                 udelay(40);
2642         }
2643
2644 out:
2645         return current_link_up;
2646 }
2647
2648 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2649 {
2650         u32 orig_pause_cfg;
2651         u16 orig_active_speed;
2652         u8 orig_active_duplex;
2653         u32 mac_status;
2654         int current_link_up;
2655         int i;
2656
2657         orig_pause_cfg =
2658                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2659                                   TG3_FLAG_TX_PAUSE));
2660         orig_active_speed = tp->link_config.active_speed;
2661         orig_active_duplex = tp->link_config.active_duplex;
2662
2663         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2664             netif_carrier_ok(tp->dev) &&
2665             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2666                 mac_status = tr32(MAC_STATUS);
2667                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2668                                MAC_STATUS_SIGNAL_DET |
2669                                MAC_STATUS_CFG_CHANGED |
2670                                MAC_STATUS_RCVD_CFG);
2671                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2672                                    MAC_STATUS_SIGNAL_DET)) {
2673                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2674                                             MAC_STATUS_CFG_CHANGED));
2675                         return 0;
2676                 }
2677         }
2678
2679         tw32_f(MAC_TX_AUTO_NEG, 0);
2680
2681         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2682         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2683         tw32_f(MAC_MODE, tp->mac_mode);
2684         udelay(40);
2685
2686         if (tp->phy_id == PHY_ID_BCM8002)
2687                 tg3_init_bcm8002(tp);
2688
2689         /* Enable link change event even when serdes polling.  */
2690         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2691         udelay(40);
2692
2693         current_link_up = 0;
2694         mac_status = tr32(MAC_STATUS);
2695
2696         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2697                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2698         else
2699                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2700
2701         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2702         tw32_f(MAC_MODE, tp->mac_mode);
2703         udelay(40);
2704
2705         tp->hw_status->status =
2706                 (SD_STATUS_UPDATED |
2707                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2708
2709         for (i = 0; i < 100; i++) {
2710                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2711                                     MAC_STATUS_CFG_CHANGED));
2712                 udelay(5);
2713                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2714                                          MAC_STATUS_CFG_CHANGED |
2715                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2716                         break;
2717         }
2718
2719         mac_status = tr32(MAC_STATUS);
2720         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2721                 current_link_up = 0;
2722                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2723                     tp->serdes_counter == 0) {
2724                         tw32_f(MAC_MODE, (tp->mac_mode |
2725                                           MAC_MODE_SEND_CONFIGS));
2726                         udelay(1);
2727                         tw32_f(MAC_MODE, tp->mac_mode);
2728                 }
2729         }
2730
2731         if (current_link_up == 1) {
2732                 tp->link_config.active_speed = SPEED_1000;
2733                 tp->link_config.active_duplex = DUPLEX_FULL;
2734                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2735                                     LED_CTRL_LNKLED_OVERRIDE |
2736                                     LED_CTRL_1000MBPS_ON));
2737         } else {
2738                 tp->link_config.active_speed = SPEED_INVALID;
2739                 tp->link_config.active_duplex = DUPLEX_INVALID;
2740                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2741                                     LED_CTRL_LNKLED_OVERRIDE |
2742                                     LED_CTRL_TRAFFIC_OVERRIDE));
2743         }
2744
2745         if (current_link_up != netif_carrier_ok(tp->dev)) {
2746                 if (current_link_up)
2747                         netif_carrier_on(tp->dev);
2748                 else
2749                         netif_carrier_off(tp->dev);
2750                 tg3_link_report(tp);
2751         } else {
2752                 u32 now_pause_cfg =
2753                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2754                                          TG3_FLAG_TX_PAUSE);
2755                 if (orig_pause_cfg != now_pause_cfg ||
2756                     orig_active_speed != tp->link_config.active_speed ||
2757                     orig_active_duplex != tp->link_config.active_duplex)
2758                         tg3_link_report(tp);
2759         }
2760
2761         return 0;
2762 }
2763
2764 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2765 {
2766         int current_link_up, err = 0;
2767         u32 bmsr, bmcr;
2768         u16 current_speed;
2769         u8 current_duplex;
2770
2771         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2772         tw32_f(MAC_MODE, tp->mac_mode);
2773         udelay(40);
2774
2775         tw32(MAC_EVENT, 0);
2776
2777         tw32_f(MAC_STATUS,
2778              (MAC_STATUS_SYNC_CHANGED |
2779               MAC_STATUS_CFG_CHANGED |
2780               MAC_STATUS_MI_COMPLETION |
2781               MAC_STATUS_LNKSTATE_CHANGED));
2782         udelay(40);
2783
2784         if (force_reset)
2785                 tg3_phy_reset(tp);
2786
2787         current_link_up = 0;
2788         current_speed = SPEED_INVALID;
2789         current_duplex = DUPLEX_INVALID;
2790
2791         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2792         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2793         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2794                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2795                         bmsr |= BMSR_LSTATUS;
2796                 else
2797                         bmsr &= ~BMSR_LSTATUS;
2798         }
2799
2800         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2801
2802         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2803             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2804                 /* do nothing, just check for link up at the end */
2805         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2806                 u32 adv, new_adv;
2807
2808                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2809                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2810                                   ADVERTISE_1000XPAUSE |
2811                                   ADVERTISE_1000XPSE_ASYM |
2812                                   ADVERTISE_SLCT);
2813
2814                 /* Always advertise symmetric PAUSE just like copper */
2815                 new_adv |= ADVERTISE_1000XPAUSE;
2816
2817                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2818                         new_adv |= ADVERTISE_1000XHALF;
2819                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2820                         new_adv |= ADVERTISE_1000XFULL;
2821
2822                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2823                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2824                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2825                         tg3_writephy(tp, MII_BMCR, bmcr);
2826
2827                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2828                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2829                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2830
2831                         return err;
2832                 }
2833         } else {
2834                 u32 new_bmcr;
2835
2836                 bmcr &= ~BMCR_SPEED1000;
2837                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2838
2839                 if (tp->link_config.duplex == DUPLEX_FULL)
2840                         new_bmcr |= BMCR_FULLDPLX;
2841
2842                 if (new_bmcr != bmcr) {
2843                         /* BMCR_SPEED1000 is a reserved bit that needs
2844                          * to be set on write.
2845                          */
2846                         new_bmcr |= BMCR_SPEED1000;
2847
2848                         /* Force a linkdown */
2849                         if (netif_carrier_ok(tp->dev)) {
2850                                 u32 adv;
2851
2852                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2853                                 adv &= ~(ADVERTISE_1000XFULL |
2854                                          ADVERTISE_1000XHALF |
2855                                          ADVERTISE_SLCT);
2856                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2857                                 tg3_writephy(tp, MII_BMCR, bmcr |
2858                                                            BMCR_ANRESTART |
2859                                                            BMCR_ANENABLE);
2860                                 udelay(10);
2861                                 netif_carrier_off(tp->dev);
2862                         }
2863                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2864                         bmcr = new_bmcr;
2865                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2866                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2867                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2868                             ASIC_REV_5714) {
2869                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2870                                         bmsr |= BMSR_LSTATUS;
2871                                 else
2872                                         bmsr &= ~BMSR_LSTATUS;
2873                         }
2874                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2875                 }
2876         }
2877
2878         if (bmsr & BMSR_LSTATUS) {
2879                 current_speed = SPEED_1000;
2880                 current_link_up = 1;
2881                 if (bmcr & BMCR_FULLDPLX)
2882                         current_duplex = DUPLEX_FULL;
2883                 else
2884                         current_duplex = DUPLEX_HALF;
2885
2886                 if (bmcr & BMCR_ANENABLE) {
2887                         u32 local_adv, remote_adv, common;
2888
2889                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2890                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2891                         common = local_adv & remote_adv;
2892                         if (common & (ADVERTISE_1000XHALF |
2893                                       ADVERTISE_1000XFULL)) {
2894                                 if (common & ADVERTISE_1000XFULL)
2895                                         current_duplex = DUPLEX_FULL;
2896                                 else
2897                                         current_duplex = DUPLEX_HALF;
2898
2899                                 tg3_setup_flow_control(tp, local_adv,
2900                                                        remote_adv);
2901                         }
2902                         else
2903                                 current_link_up = 0;
2904                 }
2905         }
2906
2907         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2908         if (tp->link_config.active_duplex == DUPLEX_HALF)
2909                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2910
2911         tw32_f(MAC_MODE, tp->mac_mode);
2912         udelay(40);
2913
2914         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2915
2916         tp->link_config.active_speed = current_speed;
2917         tp->link_config.active_duplex = current_duplex;
2918
2919         if (current_link_up != netif_carrier_ok(tp->dev)) {
2920                 if (current_link_up)
2921                         netif_carrier_on(tp->dev);
2922                 else {
2923                         netif_carrier_off(tp->dev);
2924                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2925                 }
2926                 tg3_link_report(tp);
2927         }
2928         return err;
2929 }
2930
2931 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2932 {
2933         if (tp->serdes_counter) {
2934                 /* Give autoneg time to complete. */
2935                 tp->serdes_counter--;
2936                 return;
2937         }
2938         if (!netif_carrier_ok(tp->dev) &&
2939             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2940                 u32 bmcr;
2941
2942                 tg3_readphy(tp, MII_BMCR, &bmcr);
2943                 if (bmcr & BMCR_ANENABLE) {
2944                         u32 phy1, phy2;
2945
2946                         /* Select shadow register 0x1f */
2947                         tg3_writephy(tp, 0x1c, 0x7c00);
2948                         tg3_readphy(tp, 0x1c, &phy1);
2949
2950                         /* Select expansion interrupt status register */
2951                         tg3_writephy(tp, 0x17, 0x0f01);
2952                         tg3_readphy(tp, 0x15, &phy2);
2953                         tg3_readphy(tp, 0x15, &phy2);
2954
2955                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2956                                 /* We have signal detect and not receiving
2957                                  * config code words, link is up by parallel
2958                                  * detection.
2959                                  */
2960
2961                                 bmcr &= ~BMCR_ANENABLE;
2962                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2963                                 tg3_writephy(tp, MII_BMCR, bmcr);
2964                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2965                         }
2966                 }
2967         }
2968         else if (netif_carrier_ok(tp->dev) &&
2969                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2970                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2971                 u32 phy2;
2972
2973                 /* Select expansion interrupt status register */
2974                 tg3_writephy(tp, 0x17, 0x0f01);
2975                 tg3_readphy(tp, 0x15, &phy2);
2976                 if (phy2 & 0x20) {
2977                         u32 bmcr;
2978
2979                         /* Config code words received, turn on autoneg. */
2980                         tg3_readphy(tp, MII_BMCR, &bmcr);
2981                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2982
2983                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2984
2985                 }
2986         }
2987 }
2988
2989 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2990 {
2991         int err;
2992
2993         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2994                 err = tg3_setup_fiber_phy(tp, force_reset);
2995         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2996                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2997         } else {
2998                 err = tg3_setup_copper_phy(tp, force_reset);
2999         }
3000
3001         if (tp->link_config.active_speed == SPEED_1000 &&
3002             tp->link_config.active_duplex == DUPLEX_HALF)
3003                 tw32(MAC_TX_LENGTHS,
3004                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3005                       (6 << TX_LENGTHS_IPG_SHIFT) |
3006                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3007         else
3008                 tw32(MAC_TX_LENGTHS,
3009                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3010                       (6 << TX_LENGTHS_IPG_SHIFT) |
3011                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3012
3013         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3014                 if (netif_carrier_ok(tp->dev)) {
3015                         tw32(HOSTCC_STAT_COAL_TICKS,
3016                              tp->coal.stats_block_coalesce_usecs);
3017                 } else {
3018                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3019                 }
3020         }
3021
3022         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3023                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3024                 if (!netif_carrier_ok(tp->dev))
3025                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3026                               tp->pwrmgmt_thresh;
3027                 else
3028                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3029                 tw32(PCIE_PWR_MGMT_THRESH, val);
3030         }
3031
3032         return err;
3033 }
3034
3035 /* This is called whenever we suspect that the system chipset is re-
3036  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3037  * is bogus tx completions. We try to recover by setting the
3038  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3039  * in the workqueue.
3040  */
3041 static void tg3_tx_recover(struct tg3 *tp)
3042 {
3043         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3044                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3045
3046         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3047                "mapped I/O cycles to the network device, attempting to "
3048                "recover. Please report the problem to the driver maintainer "
3049                "and include system chipset information.\n", tp->dev->name);
3050
3051         spin_lock(&tp->lock);
3052         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3053         spin_unlock(&tp->lock);
3054 }
3055
3056 static inline u32 tg3_tx_avail(struct tg3 *tp)
3057 {
3058         smp_mb();
3059         return (tp->tx_pending -
3060                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3061 }
3062
3063 /* Tigon3 never reports partial packet sends.  So we do not
3064  * need special logic to handle SKBs that have not had all
3065  * of their frags sent yet, like SunGEM does.
3066  */
3067 static void tg3_tx(struct tg3 *tp)
3068 {
3069         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3070         u32 sw_idx = tp->tx_cons;
3071
3072         while (sw_idx != hw_idx) {
3073                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3074                 struct sk_buff *skb = ri->skb;
3075                 int i, tx_bug = 0;
3076
3077                 if (unlikely(skb == NULL)) {
3078                         tg3_tx_recover(tp);
3079                         return;
3080                 }
3081
3082                 pci_unmap_single(tp->pdev,
3083                                  pci_unmap_addr(ri, mapping),
3084                                  skb_headlen(skb),
3085                                  PCI_DMA_TODEVICE);
3086
3087                 ri->skb = NULL;
3088
3089                 sw_idx = NEXT_TX(sw_idx);
3090
3091                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3092                         ri = &tp->tx_buffers[sw_idx];
3093                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3094                                 tx_bug = 1;
3095
3096                         pci_unmap_page(tp->pdev,
3097                                        pci_unmap_addr(ri, mapping),
3098                                        skb_shinfo(skb)->frags[i].size,
3099                                        PCI_DMA_TODEVICE);
3100
3101                         sw_idx = NEXT_TX(sw_idx);
3102                 }
3103
3104                 dev_kfree_skb(skb);
3105
3106                 if (unlikely(tx_bug)) {
3107                         tg3_tx_recover(tp);
3108                         return;
3109                 }
3110         }
3111
3112         tp->tx_cons = sw_idx;
3113
3114         /* Need to make the tx_cons update visible to tg3_start_xmit()
3115          * before checking for netif_queue_stopped().  Without the
3116          * memory barrier, there is a small possibility that tg3_start_xmit()
3117          * will miss it and cause the queue to be stopped forever.
3118          */
3119         smp_mb();
3120
3121         if (unlikely(netif_queue_stopped(tp->dev) &&
3122                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3123                 netif_tx_lock(tp->dev);
3124                 if (netif_queue_stopped(tp->dev) &&
3125                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3126                         netif_wake_queue(tp->dev);
3127                 netif_tx_unlock(tp->dev);
3128         }
3129 }
3130
3131 /* Returns size of skb allocated or < 0 on error.
3132  *
3133  * We only need to fill in the address because the other members
3134  * of the RX descriptor are invariant, see tg3_init_rings.
3135  *
3136  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3137  * posting buffers we only dirty the first cache line of the RX
3138  * descriptor (containing the address).  Whereas for the RX status
3139  * buffers the cpu only reads the last cacheline of the RX descriptor
3140  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3141  */
3142 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3143                             int src_idx, u32 dest_idx_unmasked)
3144 {
3145         struct tg3_rx_buffer_desc *desc;
3146         struct ring_info *map, *src_map;
3147         struct sk_buff *skb;
3148         dma_addr_t mapping;
3149         int skb_size, dest_idx;
3150
3151         src_map = NULL;
3152         switch (opaque_key) {
3153         case RXD_OPAQUE_RING_STD:
3154                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3155                 desc = &tp->rx_std[dest_idx];
3156                 map = &tp->rx_std_buffers[dest_idx];
3157                 if (src_idx >= 0)
3158                         src_map = &tp->rx_std_buffers[src_idx];
3159                 skb_size = tp->rx_pkt_buf_sz;
3160                 break;
3161
3162         case RXD_OPAQUE_RING_JUMBO:
3163                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3164                 desc = &tp->rx_jumbo[dest_idx];
3165                 map = &tp->rx_jumbo_buffers[dest_idx];
3166                 if (src_idx >= 0)
3167                         src_map = &tp->rx_jumbo_buffers[src_idx];
3168                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3169                 break;
3170
3171         default:
3172                 return -EINVAL;
3173         };
3174
3175         /* Do not overwrite any of the map or rp information
3176          * until we are sure we can commit to a new buffer.
3177          *
3178          * Callers depend upon this behavior and assume that
3179          * we leave everything unchanged if we fail.
3180          */
3181         skb = netdev_alloc_skb(tp->dev, skb_size);
3182         if (skb == NULL)
3183                 return -ENOMEM;
3184
3185         skb_reserve(skb, tp->rx_offset);
3186
3187         mapping = pci_map_single(tp->pdev, skb->data,
3188                                  skb_size - tp->rx_offset,
3189                                  PCI_DMA_FROMDEVICE);
3190
3191         map->skb = skb;
3192         pci_unmap_addr_set(map, mapping, mapping);
3193
3194         if (src_map != NULL)
3195                 src_map->skb = NULL;
3196
3197         desc->addr_hi = ((u64)mapping >> 32);
3198         desc->addr_lo = ((u64)mapping & 0xffffffff);
3199
3200         return skb_size;
3201 }
3202
3203 /* We only need to move over in the address because the other
3204  * members of the RX descriptor are invariant.  See notes above
3205  * tg3_alloc_rx_skb for full details.
3206  */
3207 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3208                            int src_idx, u32 dest_idx_unmasked)
3209 {
3210         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3211         struct ring_info *src_map, *dest_map;
3212         int dest_idx;
3213
3214         switch (opaque_key) {
3215         case RXD_OPAQUE_RING_STD:
3216                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3217                 dest_desc = &tp->rx_std[dest_idx];
3218                 dest_map = &tp->rx_std_buffers[dest_idx];
3219                 src_desc = &tp->rx_std[src_idx];
3220                 src_map = &tp->rx_std_buffers[src_idx];
3221                 break;
3222
3223         case RXD_OPAQUE_RING_JUMBO:
3224                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3225                 dest_desc = &tp->rx_jumbo[dest_idx];
3226                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3227                 src_desc = &tp->rx_jumbo[src_idx];
3228                 src_map = &tp->rx_jumbo_buffers[src_idx];
3229                 break;
3230
3231         default:
3232                 return;
3233         };
3234
3235         dest_map->skb = src_map->skb;
3236         pci_unmap_addr_set(dest_map, mapping,
3237                            pci_unmap_addr(src_map, mapping));
3238         dest_desc->addr_hi = src_desc->addr_hi;
3239         dest_desc->addr_lo = src_desc->addr_lo;
3240
3241         src_map->skb = NULL;
3242 }
3243
3244 #if TG3_VLAN_TAG_USED
3245 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3246 {
3247         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3248 }
3249 #endif
3250
3251 /* The RX ring scheme is composed of multiple rings which post fresh
3252  * buffers to the chip, and one special ring the chip uses to report
3253  * status back to the host.
3254  *
3255  * The special ring reports the status of received packets to the
3256  * host.  The chip does not write into the original descriptor the
3257  * RX buffer was obtained from.  The chip simply takes the original
3258  * descriptor as provided by the host, updates the status and length
3259  * field, then writes this into the next status ring entry.
3260  *
3261  * Each ring the host uses to post buffers to the chip is described
3262  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3263  * it is first placed into the on-chip ram.  When the packet's length
3264  * is known, it walks down the TG3_BDINFO entries to select the ring.
3265  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3266  * which is within the range of the new packet's length is chosen.
3267  *
3268  * The "separate ring for rx status" scheme may sound queer, but it makes
3269  * sense from a cache coherency perspective.  If only the host writes
3270  * to the buffer post rings, and only the chip writes to the rx status
3271  * rings, then cache lines never move beyond shared-modified state.
3272  * If both the host and chip were to write into the same ring, cache line
3273  * eviction could occur since both entities want it in an exclusive state.
3274  */
3275 static int tg3_rx(struct tg3 *tp, int budget)
3276 {
3277         u32 work_mask, rx_std_posted = 0;
3278         u32 sw_idx = tp->rx_rcb_ptr;
3279         u16 hw_idx;
3280         int received;
3281
3282         hw_idx = tp->hw_status->idx[0].rx_producer;
3283         /*
3284          * We need to order the read of hw_idx and the read of
3285          * the opaque cookie.
3286          */
3287         rmb();
3288         work_mask = 0;
3289         received = 0;
3290         while (sw_idx != hw_idx && budget > 0) {
3291                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3292                 unsigned int len;
3293                 struct sk_buff *skb;
3294                 dma_addr_t dma_addr;
3295                 u32 opaque_key, desc_idx, *post_ptr;
3296
3297                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3298                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3299                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3300                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3301                                                   mapping);
3302                         skb = tp->rx_std_buffers[desc_idx].skb;
3303                         post_ptr = &tp->rx_std_ptr;
3304                         rx_std_posted++;
3305                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3306                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3307                                                   mapping);
3308                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3309                         post_ptr = &tp->rx_jumbo_ptr;
3310                 }
3311                 else {
3312                         goto next_pkt_nopost;
3313                 }
3314
3315                 work_mask |= opaque_key;
3316
3317                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3318                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3319                 drop_it:
3320                         tg3_recycle_rx(tp, opaque_key,
3321                                        desc_idx, *post_ptr);
3322                 drop_it_no_recycle:
3323                         /* Other statistics kept track of by card. */
3324                         tp->net_stats.rx_dropped++;
3325                         goto next_pkt;
3326                 }
3327
3328                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3329
3330                 if (len > RX_COPY_THRESHOLD
3331                         && tp->rx_offset == 2
3332                         /* rx_offset != 2 iff this is a 5701 card running
3333                          * in PCI-X mode [see tg3_get_invariants()] */
3334                 ) {
3335                         int skb_size;
3336
3337                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3338                                                     desc_idx, *post_ptr);
3339                         if (skb_size < 0)
3340                                 goto drop_it;
3341
3342                         pci_unmap_single(tp->pdev, dma_addr,
3343                                          skb_size - tp->rx_offset,
3344                                          PCI_DMA_FROMDEVICE);
3345
3346                         skb_put(skb, len);
3347                 } else {
3348                         struct sk_buff *copy_skb;
3349
3350                         tg3_recycle_rx(tp, opaque_key,
3351                                        desc_idx, *post_ptr);
3352
3353                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3354                         if (copy_skb == NULL)
3355                                 goto drop_it_no_recycle;
3356
3357                         skb_reserve(copy_skb, 2);
3358                         skb_put(copy_skb, len);
3359                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3360                         skb_copy_from_linear_data(skb, copy_skb->data, len);
3361                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3362
3363                         /* We'll reuse the original ring buffer. */
3364                         skb = copy_skb;
3365                 }
3366
3367                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3368                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3369                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3370                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3371                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3372                 else
3373                         skb->ip_summed = CHECKSUM_NONE;
3374
3375                 skb->protocol = eth_type_trans(skb, tp->dev);
3376 #if TG3_VLAN_TAG_USED
3377                 if (tp->vlgrp != NULL &&
3378                     desc->type_flags & RXD_FLAG_VLAN) {
3379                         tg3_vlan_rx(tp, skb,
3380                                     desc->err_vlan & RXD_VLAN_MASK);
3381                 } else
3382 #endif
3383                         netif_receive_skb(skb);
3384
3385                 tp->dev->last_rx = jiffies;
3386                 received++;
3387                 budget--;
3388
3389 next_pkt:
3390                 (*post_ptr)++;
3391
3392                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3393                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3394
3395                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3396                                      TG3_64BIT_REG_LOW, idx);
3397                         work_mask &= ~RXD_OPAQUE_RING_STD;
3398                         rx_std_posted = 0;
3399                 }
3400 next_pkt_nopost:
3401                 sw_idx++;
3402                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3403
3404                 /* Refresh hw_idx to see if there is new work */
3405                 if (sw_idx == hw_idx) {
3406                         hw_idx = tp->hw_status->idx[0].rx_producer;
3407                         rmb();
3408                 }
3409         }
3410
3411         /* ACK the status ring. */
3412         tp->rx_rcb_ptr = sw_idx;
3413         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3414
3415         /* Refill RX ring(s). */
3416         if (work_mask & RXD_OPAQUE_RING_STD) {
3417                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3418                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3419                              sw_idx);
3420         }
3421         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3422                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3423                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3424                              sw_idx);
3425         }
3426         mmiowb();
3427
3428         return received;
3429 }
3430
3431 static int tg3_poll(struct net_device *netdev, int *budget)
3432 {
3433         struct tg3 *tp = netdev_priv(netdev);
3434         struct tg3_hw_status *sblk = tp->hw_status;
3435         int done;
3436
3437         /* handle link change and other phy events */
3438         if (!(tp->tg3_flags &
3439               (TG3_FLAG_USE_LINKCHG_REG |
3440                TG3_FLAG_POLL_SERDES))) {
3441                 if (sblk->status & SD_STATUS_LINK_CHG) {
3442                         sblk->status = SD_STATUS_UPDATED |
3443                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3444                         spin_lock(&tp->lock);
3445                         tg3_setup_phy(tp, 0);
3446                         spin_unlock(&tp->lock);
3447                 }
3448         }
3449
3450         /* run TX completion thread */
3451         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3452                 tg3_tx(tp);
3453                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3454                         netif_rx_complete(netdev);
3455                         schedule_work(&tp->reset_task);
3456                         return 0;
3457                 }
3458         }
3459
3460         /* run RX thread, within the bounds set by NAPI.
3461          * All RX "locking" is done by ensuring outside
3462          * code synchronizes with dev->poll()
3463          */
3464         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3465                 int orig_budget = *budget;
3466                 int work_done;
3467
3468                 if (orig_budget > netdev->quota)
3469                         orig_budget = netdev->quota;
3470
3471                 work_done = tg3_rx(tp, orig_budget);
3472
3473                 *budget -= work_done;
3474                 netdev->quota -= work_done;
3475         }
3476
3477         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3478                 tp->last_tag = sblk->status_tag;
3479                 rmb();
3480         } else
3481                 sblk->status &= ~SD_STATUS_UPDATED;
3482
3483         /* if no more work, tell net stack and NIC we're done */
3484         done = !tg3_has_work(tp);
3485         if (done) {
3486                 netif_rx_complete(netdev);
3487                 tg3_restart_ints(tp);
3488         }
3489
3490         return (done ? 0 : 1);
3491 }
3492
3493 static void tg3_irq_quiesce(struct tg3 *tp)
3494 {
3495         BUG_ON(tp->irq_sync);
3496
3497         tp->irq_sync = 1;
3498         smp_mb();
3499
3500         synchronize_irq(tp->pdev->irq);
3501 }
3502
3503 static inline int tg3_irq_sync(struct tg3 *tp)
3504 {
3505         return tp->irq_sync;
3506 }
3507
3508 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3509  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3510  * with as well.  Most of the time, this is not necessary except when
3511  * shutting down the device.
3512  */
3513 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3514 {
3515         if (irq_sync)
3516                 tg3_irq_quiesce(tp);
3517         spin_lock_bh(&tp->lock);
3518 }
3519
3520 static inline void tg3_full_unlock(struct tg3 *tp)
3521 {
3522         spin_unlock_bh(&tp->lock);
3523 }
3524
3525 /* One-shot MSI handler - Chip automatically disables interrupt
3526  * after sending MSI so driver doesn't have to do it.
3527  */
3528 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3529 {
3530         struct net_device *dev = dev_id;
3531         struct tg3 *tp = netdev_priv(dev);
3532
3533         prefetch(tp->hw_status);
3534         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3535
3536         if (likely(!tg3_irq_sync(tp)))
3537                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3538
3539         return IRQ_HANDLED;
3540 }
3541
3542 /* MSI ISR - No need to check for interrupt sharing and no need to
3543  * flush status block and interrupt mailbox. PCI ordering rules
3544  * guarantee that MSI will arrive after the status block.
3545  */
3546 static irqreturn_t tg3_msi(int irq, void *dev_id)
3547 {
3548         struct net_device *dev = dev_id;
3549         struct tg3 *tp = netdev_priv(dev);
3550
3551         prefetch(tp->hw_status);
3552         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3553         /*
3554          * Writing any value to intr-mbox-0 clears PCI INTA# and
3555          * chip-internal interrupt pending events.
3556          * Writing non-zero to intr-mbox-0 additional tells the
3557          * NIC to stop sending us irqs, engaging "in-intr-handler"
3558          * event coalescing.
3559          */
3560         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3561         if (likely(!tg3_irq_sync(tp)))
3562                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3563
3564         return IRQ_RETVAL(1);
3565 }
3566
3567 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3568 {
3569         struct net_device *dev = dev_id;
3570         struct tg3 *tp = netdev_priv(dev);
3571         struct tg3_hw_status *sblk = tp->hw_status;
3572         unsigned int handled = 1;
3573
3574         /* In INTx mode, it is possible for the interrupt to arrive at
3575          * the CPU before the status block posted prior to the interrupt.
3576          * Reading the PCI State register will confirm whether the
3577          * interrupt is ours and will flush the status block.
3578          */
3579         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3580                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3581                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3582                         handled = 0;
3583                         goto out;
3584                 }
3585         }
3586
3587         /*
3588          * Writing any value to intr-mbox-0 clears PCI INTA# and
3589          * chip-internal interrupt pending events.
3590          * Writing non-zero to intr-mbox-0 additional tells the
3591          * NIC to stop sending us irqs, engaging "in-intr-handler"
3592          * event coalescing.
3593          *
3594          * Flush the mailbox to de-assert the IRQ immediately to prevent
3595          * spurious interrupts.  The flush impacts performance but
3596          * excessive spurious interrupts can be worse in some cases.
3597          */
3598         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3599         if (tg3_irq_sync(tp))
3600                 goto out;
3601         sblk->status &= ~SD_STATUS_UPDATED;
3602         if (likely(tg3_has_work(tp))) {
3603                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3604                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3605         } else {
3606                 /* No work, shared interrupt perhaps?  re-enable
3607                  * interrupts, and flush that PCI write
3608                  */
3609                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3610                                0x00000000);
3611         }
3612 out:
3613         return IRQ_RETVAL(handled);
3614 }
3615
3616 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3617 {
3618         struct net_device *dev = dev_id;
3619         struct tg3 *tp = netdev_priv(dev);
3620         struct tg3_hw_status *sblk = tp->hw_status;
3621         unsigned int handled = 1;
3622
3623         /* In INTx mode, it is possible for the interrupt to arrive at
3624          * the CPU before the status block posted prior to the interrupt.
3625          * Reading the PCI State register will confirm whether the
3626          * interrupt is ours and will flush the status block.
3627          */
3628         if (unlikely(sblk->status_tag == tp->last_tag)) {
3629                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3630                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3631                         handled = 0;
3632                         goto out;
3633                 }
3634         }
3635
3636         /*
3637          * writing any value to intr-mbox-0 clears PCI INTA# and
3638          * chip-internal interrupt pending events.
3639          * writing non-zero to intr-mbox-0 additional tells the
3640          * NIC to stop sending us irqs, engaging "in-intr-handler"
3641          * event coalescing.
3642          *
3643          * Flush the mailbox to de-assert the IRQ immediately to prevent
3644          * spurious interrupts.  The flush impacts performance but
3645          * excessive spurious interrupts can be worse in some cases.
3646          */
3647         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3648         if (tg3_irq_sync(tp))
3649                 goto out;
3650         if (netif_rx_schedule_prep(dev)) {
3651                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3652                 /* Update last_tag to mark that this status has been
3653                  * seen. Because interrupt may be shared, we may be
3654                  * racing with tg3_poll(), so only update last_tag
3655                  * if tg3_poll() is not scheduled.
3656                  */
3657                 tp->last_tag = sblk->status_tag;
3658                 __netif_rx_schedule(dev);
3659         }
3660 out:
3661         return IRQ_RETVAL(handled);
3662 }
3663
3664 /* ISR for interrupt test */
3665 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3666 {
3667         struct net_device *dev = dev_id;
3668         struct tg3 *tp = netdev_priv(dev);
3669         struct tg3_hw_status *sblk = tp->hw_status;
3670
3671         if ((sblk->status & SD_STATUS_UPDATED) ||
3672             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3673                 tg3_disable_ints(tp);
3674                 return IRQ_RETVAL(1);
3675         }
3676         return IRQ_RETVAL(0);
3677 }
3678
3679 static int tg3_init_hw(struct tg3 *, int);
3680 static int tg3_halt(struct tg3 *, int, int);
3681
3682 /* Restart hardware after configuration changes, self-test, etc.
3683  * Invoked with tp->lock held.
3684  */
3685 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3686 {
3687         int err;
3688
3689         err = tg3_init_hw(tp, reset_phy);
3690         if (err) {
3691                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3692                        "aborting.\n", tp->dev->name);
3693                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3694                 tg3_full_unlock(tp);
3695                 del_timer_sync(&tp->timer);
3696                 tp->irq_sync = 0;
3697                 netif_poll_enable(tp->dev);
3698                 dev_close(tp->dev);
3699                 tg3_full_lock(tp, 0);
3700         }
3701         return err;
3702 }
3703
3704 #ifdef CONFIG_NET_POLL_CONTROLLER
3705 static void tg3_poll_controller(struct net_device *dev)
3706 {
3707         struct tg3 *tp = netdev_priv(dev);
3708
3709         tg3_interrupt(tp->pdev->irq, dev);
3710 }
3711 #endif
3712
3713 static void tg3_reset_task(struct work_struct *work)
3714 {
3715         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3716         unsigned int restart_timer;
3717
3718         tg3_full_lock(tp, 0);
3719         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3720
3721         if (!netif_running(tp->dev)) {
3722                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3723                 tg3_full_unlock(tp);
3724                 return;
3725         }
3726
3727         tg3_full_unlock(tp);
3728
3729         tg3_netif_stop(tp);
3730
3731         tg3_full_lock(tp, 1);
3732
3733         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3734         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3735
3736         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3737                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3738                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3739                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3740                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3741         }
3742
3743         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3744         if (tg3_init_hw(tp, 1))
3745                 goto out;
3746
3747         tg3_netif_start(tp);
3748
3749         if (restart_timer)
3750                 mod_timer(&tp->timer, jiffies + 1);
3751
3752 out:
3753         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3754
3755         tg3_full_unlock(tp);
3756 }
3757
3758 static void tg3_dump_short_state(struct tg3 *tp)
3759 {
3760         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3761                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3762         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3763                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3764 }
3765
3766 static void tg3_tx_timeout(struct net_device *dev)
3767 {
3768         struct tg3 *tp = netdev_priv(dev);
3769
3770         if (netif_msg_tx_err(tp)) {
3771                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3772                        dev->name);
3773                 tg3_dump_short_state(tp);
3774         }
3775
3776         schedule_work(&tp->reset_task);
3777 }
3778
3779 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3780 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3781 {
3782         u32 base = (u32) mapping & 0xffffffff;
3783
3784         return ((base > 0xffffdcc0) &&
3785                 (base + len + 8 < base));
3786 }
3787
3788 /* Test for DMA addresses > 40-bit */
3789 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3790                                           int len)
3791 {
3792 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3793         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3794                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3795         return 0;
3796 #else
3797         return 0;
3798 #endif
3799 }
3800
3801 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3802
3803 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3804 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3805                                        u32 last_plus_one, u32 *start,
3806                                        u32 base_flags, u32 mss)
3807 {
3808         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3809         dma_addr_t new_addr = 0;
3810         u32 entry = *start;
3811         int i, ret = 0;
3812
3813         if (!new_skb) {
3814                 ret = -1;
3815         } else {
3816                 /* New SKB is guaranteed to be linear. */
3817                 entry = *start;
3818                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3819                                           PCI_DMA_TODEVICE);
3820                 /* Make sure new skb does not cross any 4G boundaries.
3821                  * Drop the packet if it does.
3822                  */
3823                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3824                         ret = -1;
3825                         dev_kfree_skb(new_skb);
3826                         new_skb = NULL;
3827                 } else {
3828                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3829                                     base_flags, 1 | (mss << 1));
3830                         *start = NEXT_TX(entry);
3831                 }
3832         }
3833
3834         /* Now clean up the sw ring entries. */
3835         i = 0;
3836         while (entry != last_plus_one) {
3837                 int len;
3838
3839                 if (i == 0)
3840                         len = skb_headlen(skb);
3841                 else
3842                         len = skb_shinfo(skb)->frags[i-1].size;
3843                 pci_unmap_single(tp->pdev,
3844                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3845                                  len, PCI_DMA_TODEVICE);
3846                 if (i == 0) {
3847                         tp->tx_buffers[entry].skb = new_skb;
3848                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3849                 } else {
3850                         tp->tx_buffers[entry].skb = NULL;
3851                 }
3852                 entry = NEXT_TX(entry);
3853                 i++;
3854         }
3855
3856         dev_kfree_skb(skb);
3857
3858         return ret;
3859 }
3860
3861 static void tg3_set_txd(struct tg3 *tp, int entry,
3862                         dma_addr_t mapping, int len, u32 flags,
3863                         u32 mss_and_is_end)
3864 {
3865         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3866         int is_end = (mss_and_is_end & 0x1);
3867         u32 mss = (mss_and_is_end >> 1);
3868         u32 vlan_tag = 0;
3869
3870         if (is_end)
3871                 flags |= TXD_FLAG_END;
3872         if (flags & TXD_FLAG_VLAN) {
3873                 vlan_tag = flags >> 16;
3874                 flags &= 0xffff;
3875         }
3876         vlan_tag |= (mss << TXD_MSS_SHIFT);
3877
3878         txd->addr_hi = ((u64) mapping >> 32);
3879         txd->addr_lo = ((u64) mapping & 0xffffffff);
3880         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3881         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3882 }
3883
3884 /* hard_start_xmit for devices that don't have any bugs and
3885  * support TG3_FLG2_HW_TSO_2 only.
3886  */
3887 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3888 {
3889         struct tg3 *tp = netdev_priv(dev);
3890         dma_addr_t mapping;
3891         u32 len, entry, base_flags, mss;
3892
3893         len = skb_headlen(skb);
3894
3895         /* We are running in BH disabled context with netif_tx_lock
3896          * and TX reclaim runs via tp->poll inside of a software
3897          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3898          * no IRQ context deadlocks to worry about either.  Rejoice!
3899          */
3900         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3901                 if (!netif_queue_stopped(dev)) {
3902                         netif_stop_queue(dev);
3903
3904                         /* This is a hard error, log it. */
3905                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3906                                "queue awake!\n", dev->name);
3907                 }
3908                 return NETDEV_TX_BUSY;
3909         }
3910
3911         entry = tp->tx_prod;
3912         base_flags = 0;
3913         mss = 0;
3914         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3915                 int tcp_opt_len, ip_tcp_len;
3916
3917                 if (skb_header_cloned(skb) &&
3918                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3919                         dev_kfree_skb(skb);
3920                         goto out_unlock;
3921                 }
3922
3923                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3924                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3925                 else {
3926                         struct iphdr *iph = ip_hdr(skb);
3927
3928                         tcp_opt_len = tcp_optlen(skb);
3929                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3930
3931                         iph->check = 0;
3932                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3933                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3934                 }
3935
3936                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3937                                TXD_FLAG_CPU_POST_DMA);
3938
3939                 tcp_hdr(skb)->check = 0;
3940
3941         }
3942         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3943                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3944 #if TG3_VLAN_TAG_USED
3945         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3946                 base_flags |= (TXD_FLAG_VLAN |
3947                                (vlan_tx_tag_get(skb) << 16));
3948 #endif
3949
3950         /* Queue skb data, a.k.a. the main skb fragment. */
3951         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3952
3953         tp->tx_buffers[entry].skb = skb;
3954         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3955
3956         tg3_set_txd(tp, entry, mapping, len, base_flags,
3957                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3958
3959         entry = NEXT_TX(entry);
3960
3961         /* Now loop through additional data fragments, and queue them. */
3962         if (skb_shinfo(skb)->nr_frags > 0) {
3963                 unsigned int i, last;
3964
3965                 last = skb_shinfo(skb)->nr_frags - 1;
3966                 for (i = 0; i <= last; i++) {
3967                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3968
3969                         len = frag->size;
3970                         mapping = pci_map_page(tp->pdev,
3971                                                frag->page,
3972                                                frag->page_offset,
3973                                                len, PCI_DMA_TODEVICE);
3974
3975                         tp->tx_buffers[entry].skb = NULL;
3976                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3977
3978                         tg3_set_txd(tp, entry, mapping, len,
3979                                     base_flags, (i == last) | (mss << 1));
3980
3981                         entry = NEXT_TX(entry);
3982                 }
3983         }
3984
3985         /* Packets are ready, update Tx producer idx local and on card. */
3986         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3987
3988         tp->tx_prod = entry;
3989         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3990                 netif_stop_queue(dev);
3991                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3992                         netif_wake_queue(tp->dev);
3993         }
3994
3995 out_unlock:
3996         mmiowb();
3997
3998         dev->trans_start = jiffies;
3999
4000         return NETDEV_TX_OK;
4001 }
4002
4003 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4004
4005 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4006  * TSO header is greater than 80 bytes.
4007  */
4008 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4009 {
4010         struct sk_buff *segs, *nskb;
4011
4012         /* Estimate the number of fragments in the worst case */
4013         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4014                 netif_stop_queue(tp->dev);
4015                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4016                         return NETDEV_TX_BUSY;
4017
4018                 netif_wake_queue(tp->dev);
4019         }
4020
4021         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4022         if (unlikely(IS_ERR(segs)))
4023                 goto tg3_tso_bug_end;
4024
4025         do {
4026                 nskb = segs;
4027                 segs = segs->next;
4028                 nskb->next = NULL;
4029                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4030         } while (segs);
4031
4032 tg3_tso_bug_end:
4033         dev_kfree_skb(skb);
4034
4035         return NETDEV_TX_OK;
4036 }
4037
4038 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4039  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4040  */
4041 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4042 {
4043         struct tg3 *tp = netdev_priv(dev);
4044         dma_addr_t mapping;
4045         u32 len, entry, base_flags, mss;
4046         int would_hit_hwbug;
4047
4048         len = skb_headlen(skb);
4049
4050         /* We are running in BH disabled context with netif_tx_lock
4051          * and TX reclaim runs via tp->poll inside of a software
4052          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4053          * no IRQ context deadlocks to worry about either.  Rejoice!
4054          */
4055         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4056                 if (!netif_queue_stopped(dev)) {
4057                         netif_stop_queue(dev);
4058
4059                         /* This is a hard error, log it. */
4060                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4061                                "queue awake!\n", dev->name);
4062                 }
4063                 return NETDEV_TX_BUSY;
4064         }
4065
4066         entry = tp->tx_prod;
4067         base_flags = 0;
4068         if (skb->ip_summed == CHECKSUM_PARTIAL)
4069                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4070         mss = 0;
4071         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4072                 struct iphdr *iph;
4073                 int tcp_opt_len, ip_tcp_len, hdr_len;
4074
4075                 if (skb_header_cloned(skb) &&
4076                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4077                         dev_kfree_skb(skb);
4078                         goto out_unlock;
4079                 }
4080
4081                 tcp_opt_len = tcp_optlen(skb);
4082                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4083
4084                 hdr_len = ip_tcp_len + tcp_opt_len;
4085                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4086                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4087                         return (tg3_tso_bug(tp, skb));
4088
4089                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4090                                TXD_FLAG_CPU_POST_DMA);
4091
4092                 iph = ip_hdr(skb);
4093                 iph->check = 0;
4094                 iph->tot_len = htons(mss + hdr_len);
4095                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4096                         tcp_hdr(skb)->check = 0;
4097                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4098                 } else
4099                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4100                                                                  iph->daddr, 0,
4101                                                                  IPPROTO_TCP,
4102                                                                  0);
4103
4104                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4105                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4106                         if (tcp_opt_len || iph->ihl > 5) {
4107                                 int tsflags;
4108
4109                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4110                                 mss |= (tsflags << 11);
4111                         }
4112                 } else {
4113                         if (tcp_opt_len || iph->ihl > 5) {
4114                                 int tsflags;
4115
4116                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4117                                 base_flags |= tsflags << 12;
4118                         }
4119                 }
4120         }
4121 #if TG3_VLAN_TAG_USED
4122         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4123                 base_flags |= (TXD_FLAG_VLAN |
4124                                (vlan_tx_tag_get(skb) << 16));
4125 #endif
4126
4127         /* Queue skb data, a.k.a. the main skb fragment. */
4128         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4129
4130         tp->tx_buffers[entry].skb = skb;
4131         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4132
4133         would_hit_hwbug = 0;
4134
4135         if (tg3_4g_overflow_test(mapping, len))
4136                 would_hit_hwbug = 1;
4137
4138         tg3_set_txd(tp, entry, mapping, len, base_flags,
4139                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4140
4141         entry = NEXT_TX(entry);
4142
4143         /* Now loop through additional data fragments, and queue them. */
4144         if (skb_shinfo(skb)->nr_frags > 0) {
4145                 unsigned int i, last;
4146
4147                 last = skb_shinfo(skb)->nr_frags - 1;
4148                 for (i = 0; i <= last; i++) {
4149                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4150
4151                         len = frag->size;
4152                         mapping = pci_map_page(tp->pdev,
4153                                                frag->page,
4154                                                frag->page_offset,
4155                                                len, PCI_DMA_TODEVICE);
4156
4157                         tp->tx_buffers[entry].skb = NULL;
4158                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4159
4160                         if (tg3_4g_overflow_test(mapping, len))
4161                                 would_hit_hwbug = 1;
4162
4163                         if (tg3_40bit_overflow_test(tp, mapping, len))
4164                                 would_hit_hwbug = 1;
4165
4166                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4167                                 tg3_set_txd(tp, entry, mapping, len,
4168                                             base_flags, (i == last)|(mss << 1));
4169                         else
4170                                 tg3_set_txd(tp, entry, mapping, len,
4171                                             base_flags, (i == last));
4172
4173                         entry = NEXT_TX(entry);
4174                 }
4175         }
4176
4177         if (would_hit_hwbug) {
4178                 u32 last_plus_one = entry;
4179                 u32 start;
4180
4181                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4182                 start &= (TG3_TX_RING_SIZE - 1);
4183
4184                 /* If the workaround fails due to memory/mapping
4185                  * failure, silently drop this packet.
4186                  */
4187                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4188                                                 &start, base_flags, mss))
4189                         goto out_unlock;
4190
4191                 entry = start;
4192         }
4193
4194         /* Packets are ready, update Tx producer idx local and on card. */
4195         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4196
4197         tp->tx_prod = entry;
4198         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4199                 netif_stop_queue(dev);
4200                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4201                         netif_wake_queue(tp->dev);
4202         }
4203
4204 out_unlock:
4205         mmiowb();
4206
4207         dev->trans_start = jiffies;
4208
4209         return NETDEV_TX_OK;
4210 }
4211
4212 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4213                                int new_mtu)
4214 {
4215         dev->mtu = new_mtu;
4216
4217         if (new_mtu > ETH_DATA_LEN) {
4218                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4219                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4220                         ethtool_op_set_tso(dev, 0);
4221                 }
4222                 else
4223                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4224         } else {
4225                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4226                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4227                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4228         }
4229 }
4230
4231 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4232 {
4233         struct tg3 *tp = netdev_priv(dev);
4234         int err;
4235
4236         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4237                 return -EINVAL;
4238
4239         if (!netif_running(dev)) {
4240                 /* We'll just catch it later when the
4241                  * device is up'd.
4242                  */
4243                 tg3_set_mtu(dev, tp, new_mtu);
4244                 return 0;
4245         }
4246
4247         tg3_netif_stop(tp);
4248
4249         tg3_full_lock(tp, 1);
4250
4251         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4252
4253         tg3_set_mtu(dev, tp, new_mtu);
4254
4255         err = tg3_restart_hw(tp, 0);
4256
4257         if (!err)
4258                 tg3_netif_start(tp);
4259
4260         tg3_full_unlock(tp);
4261
4262         return err;
4263 }
4264
4265 /* Free up pending packets in all rx/tx rings.
4266  *
4267  * The chip has been shut down and the driver detached from
4268  * the networking, so no interrupts or new tx packets will
4269  * end up in the driver.  tp->{tx,}lock is not held and we are not
4270  * in an interrupt context and thus may sleep.
4271  */
4272 static void tg3_free_rings(struct tg3 *tp)
4273 {
4274         struct ring_info *rxp;
4275         int i;
4276
4277         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4278                 rxp = &tp->rx_std_buffers[i];
4279
4280                 if (rxp->skb == NULL)
4281                         continue;
4282                 pci_unmap_single(tp->pdev,
4283                                  pci_unmap_addr(rxp, mapping),
4284                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4285                                  PCI_DMA_FROMDEVICE);
4286                 dev_kfree_skb_any(rxp->skb);
4287                 rxp->skb = NULL;
4288         }
4289
4290         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4291                 rxp = &tp->rx_jumbo_buffers[i];
4292
4293                 if (rxp->skb == NULL)
4294                         continue;
4295                 pci_unmap_single(tp->pdev,
4296                                  pci_unmap_addr(rxp, mapping),
4297                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4298                                  PCI_DMA_FROMDEVICE);
4299                 dev_kfree_skb_any(rxp->skb);
4300                 rxp->skb = NULL;
4301         }
4302
4303         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4304                 struct tx_ring_info *txp;
4305                 struct sk_buff *skb;
4306                 int j;
4307
4308                 txp = &tp->tx_buffers[i];
4309                 skb = txp->skb;
4310
4311                 if (skb == NULL) {
4312                         i++;
4313                         continue;
4314                 }
4315
4316                 pci_unmap_single(tp->pdev,
4317                                  pci_unmap_addr(txp, mapping),
4318                                  skb_headlen(skb),
4319                                  PCI_DMA_TODEVICE);
4320                 txp->skb = NULL;
4321
4322                 i++;
4323
4324                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4325                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4326                         pci_unmap_page(tp->pdev,
4327                                        pci_unmap_addr(txp, mapping),
4328                                        skb_shinfo(skb)->frags[j].size,
4329                                        PCI_DMA_TODEVICE);
4330                         i++;
4331                 }
4332
4333                 dev_kfree_skb_any(skb);
4334         }
4335 }
4336
4337 /* Initialize tx/rx rings for packet processing.
4338  *
4339  * The chip has been shut down and the driver detached from
4340  * the networking, so no interrupts or new tx packets will
4341  * end up in the driver.  tp->{tx,}lock are held and thus
4342  * we may not sleep.
4343  */
4344 static int tg3_init_rings(struct tg3 *tp)
4345 {
4346         u32 i;
4347
4348         /* Free up all the SKBs. */
4349         tg3_free_rings(tp);
4350
4351         /* Zero out all descriptors. */
4352         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4353         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4354         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4355         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4356
4357         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4358         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4359             (tp->dev->mtu > ETH_DATA_LEN))
4360                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4361
4362         /* Initialize invariants of the rings, we only set this
4363          * stuff once.  This works because the card does not
4364          * write into the rx buffer posting rings.
4365          */
4366         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4367                 struct tg3_rx_buffer_desc *rxd;
4368
4369                 rxd = &tp->rx_std[i];
4370                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4371                         << RXD_LEN_SHIFT;
4372                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4373                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4374                                (i << RXD_OPAQUE_INDEX_SHIFT));
4375         }
4376
4377         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4378                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4379                         struct tg3_rx_buffer_desc *rxd;
4380
4381                         rxd = &tp->rx_jumbo[i];
4382                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4383                                 << RXD_LEN_SHIFT;
4384                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4385                                 RXD_FLAG_JUMBO;
4386                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4387                                (i << RXD_OPAQUE_INDEX_SHIFT));
4388                 }
4389         }
4390
4391         /* Now allocate fresh SKBs for each rx ring. */
4392         for (i = 0; i < tp->rx_pending; i++) {
4393                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4394                         printk(KERN_WARNING PFX
4395                                "%s: Using a smaller RX standard ring, "
4396                                "only %d out of %d buffers were allocated "
4397                                "successfully.\n",
4398                                tp->dev->name, i, tp->rx_pending);
4399                         if (i == 0)
4400                                 return -ENOMEM;
4401                         tp->rx_pending = i;
4402                         break;
4403                 }
4404         }
4405
4406         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4407                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4408                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4409                                              -1, i) < 0) {
4410                                 printk(KERN_WARNING PFX
4411                                        "%s: Using a smaller RX jumbo ring, "
4412                                        "only %d out of %d buffers were "
4413                                        "allocated successfully.\n",
4414                                        tp->dev->name, i, tp->rx_jumbo_pending);
4415                                 if (i == 0) {
4416                                         tg3_free_rings(tp);
4417                                         return -ENOMEM;
4418                                 }
4419                                 tp->rx_jumbo_pending = i;
4420                                 break;
4421                         }
4422                 }
4423         }
4424         return 0;
4425 }
4426
4427 /*
4428  * Must not be invoked with interrupt sources disabled and
4429  * the hardware shutdown down.
4430  */
4431 static void tg3_free_consistent(struct tg3 *tp)
4432 {
4433         kfree(tp->rx_std_buffers);
4434         tp->rx_std_buffers = NULL;
4435         if (tp->rx_std) {
4436                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4437                                     tp->rx_std, tp->rx_std_mapping);
4438                 tp->rx_std = NULL;
4439         }
4440         if (tp->rx_jumbo) {
4441                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4442                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4443                 tp->rx_jumbo = NULL;
4444         }
4445         if (tp->rx_rcb) {
4446                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4447                                     tp->rx_rcb, tp->rx_rcb_mapping);
4448                 tp->rx_rcb = NULL;
4449         }
4450         if (tp->tx_ring) {
4451                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4452                         tp->tx_ring, tp->tx_desc_mapping);
4453                 tp->tx_ring = NULL;
4454         }
4455         if (tp->hw_status) {
4456                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4457                                     tp->hw_status, tp->status_mapping);
4458                 tp->hw_status = NULL;
4459         }
4460         if (tp->hw_stats) {
4461                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4462                                     tp->hw_stats, tp->stats_mapping);
4463                 tp->hw_stats = NULL;
4464         }
4465 }
4466
4467 /*
4468  * Must not be invoked with interrupt sources disabled and
4469  * the hardware shutdown down.  Can sleep.
4470  */
4471 static int tg3_alloc_consistent(struct tg3 *tp)
4472 {
4473         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4474                                       (TG3_RX_RING_SIZE +
4475                                        TG3_RX_JUMBO_RING_SIZE)) +
4476                                      (sizeof(struct tx_ring_info) *
4477                                       TG3_TX_RING_SIZE),
4478                                      GFP_KERNEL);
4479         if (!tp->rx_std_buffers)
4480                 return -ENOMEM;
4481
4482         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4483         tp->tx_buffers = (struct tx_ring_info *)
4484                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4485
4486         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4487                                           &tp->rx_std_mapping);
4488         if (!tp->rx_std)
4489                 goto err_out;
4490
4491         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4492                                             &tp->rx_jumbo_mapping);
4493
4494         if (!tp->rx_jumbo)
4495                 goto err_out;
4496
4497         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4498                                           &tp->rx_rcb_mapping);
4499         if (!tp->rx_rcb)
4500                 goto err_out;
4501
4502         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4503                                            &tp->tx_desc_mapping);
4504         if (!tp->tx_ring)
4505                 goto err_out;
4506
4507         tp->hw_status = pci_alloc_consistent(tp->pdev,
4508                                              TG3_HW_STATUS_SIZE,
4509                                              &tp->status_mapping);
4510         if (!tp->hw_status)
4511                 goto err_out;
4512
4513         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4514                                             sizeof(struct tg3_hw_stats),
4515                                             &tp->stats_mapping);
4516         if (!tp->hw_stats)
4517                 goto err_out;
4518
4519         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4520         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4521
4522         return 0;
4523
4524 err_out:
4525         tg3_free_consistent(tp);
4526         return -ENOMEM;
4527 }
4528
4529 #define MAX_WAIT_CNT 1000
4530
4531 /* To stop a block, clear the enable bit and poll till it
4532  * clears.  tp->lock is held.
4533  */
4534 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4535 {
4536         unsigned int i;
4537         u32 val;
4538
4539         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4540                 switch (ofs) {
4541                 case RCVLSC_MODE:
4542                 case DMAC_MODE:
4543                 case MBFREE_MODE:
4544                 case BUFMGR_MODE:
4545                 case MEMARB_MODE:
4546                         /* We can't enable/disable these bits of the
4547                          * 5705/5750, just say success.
4548                          */
4549                         return 0;
4550
4551                 default:
4552                         break;
4553                 };
4554         }
4555
4556         val = tr32(ofs);
4557         val &= ~enable_bit;
4558         tw32_f(ofs, val);
4559
4560         for (i = 0; i < MAX_WAIT_CNT; i++) {
4561                 udelay(100);
4562                 val = tr32(ofs);
4563                 if ((val & enable_bit) == 0)
4564                         break;
4565         }
4566
4567         if (i == MAX_WAIT_CNT && !silent) {
4568                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4569                        "ofs=%lx enable_bit=%x\n",
4570                        ofs, enable_bit);
4571                 return -ENODEV;
4572         }
4573
4574         return 0;
4575 }
4576
4577 /* tp->lock is held. */
4578 static int tg3_abort_hw(struct tg3 *tp, int silent)
4579 {
4580         int i, err;
4581
4582         tg3_disable_ints(tp);
4583
4584         tp->rx_mode &= ~RX_MODE_ENABLE;
4585         tw32_f(MAC_RX_MODE, tp->rx_mode);
4586         udelay(10);
4587
4588         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4589         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4590         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4591         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4592         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4593         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4594
4595         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4596         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4597         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4598         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4599         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4600         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4601         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4602
4603         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4604         tw32_f(MAC_MODE, tp->mac_mode);
4605         udelay(40);
4606
4607         tp->tx_mode &= ~TX_MODE_ENABLE;
4608         tw32_f(MAC_TX_MODE, tp->tx_mode);
4609
4610         for (i = 0; i < MAX_WAIT_CNT; i++) {
4611                 udelay(100);
4612                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4613                         break;
4614         }
4615         if (i >= MAX_WAIT_CNT) {
4616                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4617                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4618                        tp->dev->name, tr32(MAC_TX_MODE));
4619                 err |= -ENODEV;
4620         }
4621
4622         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4623         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4624         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4625
4626         tw32(FTQ_RESET, 0xffffffff);
4627         tw32(FTQ_RESET, 0x00000000);
4628
4629         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4630         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4631
4632         if (tp->hw_status)
4633                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4634         if (tp->hw_stats)
4635                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4636
4637         return err;
4638 }
4639
4640 /* tp->lock is held. */
4641 static int tg3_nvram_lock(struct tg3 *tp)
4642 {
4643         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4644                 int i;
4645
4646                 if (tp->nvram_lock_cnt == 0) {
4647                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4648                         for (i = 0; i < 8000; i++) {
4649                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4650                                         break;
4651                                 udelay(20);
4652                         }
4653                         if (i == 8000) {
4654                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4655                                 return -ENODEV;
4656                         }
4657                 }
4658                 tp->nvram_lock_cnt++;
4659         }
4660         return 0;
4661 }
4662
4663 /* tp->lock is held. */
4664 static void tg3_nvram_unlock(struct tg3 *tp)
4665 {
4666         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4667                 if (tp->nvram_lock_cnt > 0)
4668                         tp->nvram_lock_cnt--;
4669                 if (tp->nvram_lock_cnt == 0)
4670                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4671         }
4672 }
4673
4674 /* tp->lock is held. */
4675 static void tg3_enable_nvram_access(struct tg3 *tp)
4676 {
4677         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4678             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4679                 u32 nvaccess = tr32(NVRAM_ACCESS);
4680
4681                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4682         }
4683 }
4684
4685 /* tp->lock is held. */
4686 static void tg3_disable_nvram_access(struct tg3 *tp)
4687 {
4688         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4689             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4690                 u32 nvaccess = tr32(NVRAM_ACCESS);
4691
4692                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4693         }
4694 }
4695
4696 /* tp->lock is held. */
4697 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4698 {
4699         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4700                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4701
4702         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4703                 switch (kind) {
4704                 case RESET_KIND_INIT:
4705                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4706                                       DRV_STATE_START);
4707                         break;
4708
4709                 case RESET_KIND_SHUTDOWN:
4710                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4711                                       DRV_STATE_UNLOAD);
4712                         break;
4713
4714                 case RESET_KIND_SUSPEND:
4715                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4716                                       DRV_STATE_SUSPEND);
4717                         break;
4718
4719                 default:
4720                         break;
4721                 };
4722         }
4723 }
4724
4725 /* tp->lock is held. */
4726 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4727 {
4728         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4729                 switch (kind) {
4730                 case RESET_KIND_INIT:
4731                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4732                                       DRV_STATE_START_DONE);
4733                         break;
4734
4735                 case RESET_KIND_SHUTDOWN:
4736                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4737                                       DRV_STATE_UNLOAD_DONE);
4738                         break;
4739
4740                 default:
4741                         break;
4742                 };
4743         }
4744 }
4745
4746 /* tp->lock is held. */
4747 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4748 {
4749         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4750                 switch (kind) {
4751                 case RESET_KIND_INIT:
4752                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4753                                       DRV_STATE_START);
4754                         break;
4755
4756                 case RESET_KIND_SHUTDOWN:
4757                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4758                                       DRV_STATE_UNLOAD);
4759                         break;
4760
4761                 case RESET_KIND_SUSPEND:
4762                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4763                                       DRV_STATE_SUSPEND);
4764                         break;
4765
4766                 default:
4767                         break;
4768                 };
4769         }
4770 }
4771
4772 static int tg3_poll_fw(struct tg3 *tp)
4773 {
4774         int i;
4775         u32 val;
4776
4777         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4778                 /* Wait up to 20ms for init done. */
4779                 for (i = 0; i < 200; i++) {
4780                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4781                                 return 0;
4782                         udelay(100);
4783                 }
4784                 return -ENODEV;
4785         }
4786
4787         /* Wait for firmware initialization to complete. */
4788         for (i = 0; i < 100000; i++) {
4789                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4790                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4791                         break;
4792                 udelay(10);
4793         }
4794
4795         /* Chip might not be fitted with firmware.  Some Sun onboard
4796          * parts are configured like that.  So don't signal the timeout
4797          * of the above loop as an error, but do report the lack of
4798          * running firmware once.
4799          */
4800         if (i >= 100000 &&
4801             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4802                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4803
4804                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4805                        tp->dev->name);
4806         }
4807
4808         return 0;
4809 }
4810
4811 static void tg3_stop_fw(struct tg3 *);
4812
4813 /* tp->lock is held. */
4814 static int tg3_chip_reset(struct tg3 *tp)
4815 {
4816         u32 val;
4817         void (*write_op)(struct tg3 *, u32, u32);
4818         int err;
4819
4820         tg3_nvram_lock(tp);
4821
4822         /* No matching tg3_nvram_unlock() after this because
4823          * chip reset below will undo the nvram lock.
4824          */
4825         tp->nvram_lock_cnt = 0;
4826
4827         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4828             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4829             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4830                 tw32(GRC_FASTBOOT_PC, 0);
4831
4832         /*
4833          * We must avoid the readl() that normally takes place.
4834          * It locks machines, causes machine checks, and other
4835          * fun things.  So, temporarily disable the 5701
4836          * hardware workaround, while we do the reset.
4837          */
4838         write_op = tp->write32;
4839         if (write_op == tg3_write_flush_reg32)
4840                 tp->write32 = tg3_write32;
4841
4842         /* Prevent the irq handler from reading or writing PCI registers
4843          * during chip reset when the memory enable bit in the PCI command
4844          * register may be cleared.  The chip does not generate interrupt
4845          * at this time, but the irq handler may still be called due to irq
4846          * sharing or irqpoll.
4847          */
4848         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4849         if (tp->hw_status) {
4850                 tp->hw_status->status = 0;
4851                 tp->hw_status->status_tag = 0;
4852         }
4853         tp->last_tag = 0;
4854         smp_mb();
4855         synchronize_irq(tp->pdev->irq);
4856
4857         /* do the reset */
4858         val = GRC_MISC_CFG_CORECLK_RESET;
4859
4860         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4861                 if (tr32(0x7e2c) == 0x60) {
4862                         tw32(0x7e2c, 0x20);
4863                 }
4864                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4865                         tw32(GRC_MISC_CFG, (1 << 29));
4866                         val |= (1 << 29);
4867                 }
4868         }
4869
4870         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4871                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4872                 tw32(GRC_VCPU_EXT_CTRL,
4873                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4874         }
4875
4876         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4877                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4878         tw32(GRC_MISC_CFG, val);
4879
4880         /* restore 5701 hardware bug workaround write method */
4881         tp->write32 = write_op;
4882
4883         /* Unfortunately, we have to delay before the PCI read back.
4884          * Some 575X chips even will not respond to a PCI cfg access
4885          * when the reset command is given to the chip.
4886          *
4887          * How do these hardware designers expect things to work
4888          * properly if the PCI write is posted for a long period
4889          * of time?  It is always necessary to have some method by
4890          * which a register read back can occur to push the write
4891          * out which does the reset.
4892          *
4893          * For most tg3 variants the trick below was working.
4894          * Ho hum...
4895          */
4896         udelay(120);
4897
4898         /* Flush PCI posted writes.  The normal MMIO registers
4899          * are inaccessible at this time so this is the only
4900          * way to make this reliably (actually, this is no longer
4901          * the case, see above).  I tried to use indirect
4902          * register read/write but this upset some 5701 variants.
4903          */
4904         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4905
4906         udelay(120);
4907
4908         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4909                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4910                         int i;
4911                         u32 cfg_val;
4912
4913                         /* Wait for link training to complete.  */
4914                         for (i = 0; i < 5000; i++)
4915                                 udelay(100);
4916
4917                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4918                         pci_write_config_dword(tp->pdev, 0xc4,
4919                                                cfg_val | (1 << 15));
4920                 }
4921                 /* Set PCIE max payload size and clear error status.  */
4922                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4923         }
4924
4925         /* Re-enable indirect register accesses. */
4926         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4927                                tp->misc_host_ctrl);
4928
4929         /* Set MAX PCI retry to zero. */
4930         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4931         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4932             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4933                 val |= PCISTATE_RETRY_SAME_DMA;
4934         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4935
4936         pci_restore_state(tp->pdev);
4937
4938         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4939
4940         /* Make sure PCI-X relaxed ordering bit is clear. */
4941         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4942         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4943         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4944
4945         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4946                 u32 val;
4947
4948                 /* Chip reset on 5780 will reset MSI enable bit,
4949                  * so need to restore it.
4950                  */
4951                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4952                         u16 ctrl;
4953
4954                         pci_read_config_word(tp->pdev,
4955                                              tp->msi_cap + PCI_MSI_FLAGS,
4956                                              &ctrl);
4957                         pci_write_config_word(tp->pdev,
4958                                               tp->msi_cap + PCI_MSI_FLAGS,
4959                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4960                         val = tr32(MSGINT_MODE);
4961                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4962                 }
4963
4964                 val = tr32(MEMARB_MODE);
4965                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4966
4967         } else
4968                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4969
4970         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4971                 tg3_stop_fw(tp);
4972                 tw32(0x5000, 0x400);
4973         }
4974
4975         tw32(GRC_MODE, tp->grc_mode);
4976
4977         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4978                 u32 val = tr32(0xc4);
4979
4980                 tw32(0xc4, val | (1 << 15));
4981         }
4982
4983         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4984             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4985                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4986                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4987                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4988                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4989         }
4990
4991         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4992                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4993                 tw32_f(MAC_MODE, tp->mac_mode);
4994         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4995                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4996                 tw32_f(MAC_MODE, tp->mac_mode);
4997         } else
4998                 tw32_f(MAC_MODE, 0);
4999         udelay(40);
5000
5001         err = tg3_poll_fw(tp);
5002         if (err)
5003                 return err;
5004
5005         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5006             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5007                 u32 val = tr32(0x7c00);
5008
5009                 tw32(0x7c00, val | (1 << 25));
5010         }
5011
5012         /* Reprobe ASF enable state.  */
5013         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5014         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5015         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5016         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5017                 u32 nic_cfg;
5018
5019                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5020                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5021                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5022                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5023                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5024                 }
5025         }
5026
5027         return 0;
5028 }
5029
5030 /* tp->lock is held. */
5031 static void tg3_stop_fw(struct tg3 *tp)
5032 {
5033         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5034                 u32 val;
5035                 int i;
5036
5037                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5038                 val = tr32(GRC_RX_CPU_EVENT);
5039                 val |= (1 << 14);
5040                 tw32(GRC_RX_CPU_EVENT, val);
5041
5042                 /* Wait for RX cpu to ACK the event.  */
5043                 for (i = 0; i < 100; i++) {
5044                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5045                                 break;
5046                         udelay(1);
5047                 }
5048         }
5049 }
5050
5051 /* tp->lock is held. */
5052 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5053 {
5054         int err;
5055
5056         tg3_stop_fw(tp);
5057
5058         tg3_write_sig_pre_reset(tp, kind);
5059
5060         tg3_abort_hw(tp, silent);
5061         err = tg3_chip_reset(tp);
5062
5063         tg3_write_sig_legacy(tp, kind);
5064         tg3_write_sig_post_reset(tp, kind);
5065
5066         if (err)
5067                 return err;
5068
5069         return 0;
5070 }
5071
5072 #define TG3_FW_RELEASE_MAJOR    0x0
5073 #define TG3_FW_RELASE_MINOR     0x0
5074 #define TG3_FW_RELEASE_FIX      0x0
5075 #define TG3_FW_START_ADDR       0x08000000
5076 #define TG3_FW_TEXT_ADDR        0x08000000
5077 #define TG3_FW_TEXT_LEN         0x9c0
5078 #define TG3_FW_RODATA_ADDR      0x080009c0
5079 #define TG3_FW_RODATA_LEN       0x60
5080 #define TG3_FW_DATA_ADDR        0x08000a40
5081 #define TG3_FW_DATA_LEN         0x20
5082 #define TG3_FW_SBSS_ADDR        0x08000a60
5083 #define TG3_FW_SBSS_LEN         0xc
5084 #define TG3_FW_BSS_ADDR         0x08000a70
5085 #define TG3_FW_BSS_LEN          0x10
5086
5087 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5088         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5089         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5090         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5091         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5092         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5093         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5094         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5095         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5096         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5097         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5098         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5099         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5100         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5101         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5102         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5103         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5104         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5105         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5106         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5107         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5108         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5109         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5110         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5111         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5112         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5113         0, 0, 0, 0, 0, 0,
5114         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5115         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5116         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5117         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5118         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5119         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5120         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5121         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5122         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5123         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5124         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5125         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5126         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5127         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5128         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5129         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5130         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5131         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5132         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5133         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5134         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5135         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5136         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5137         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5138         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5139         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5140         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5141         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5142         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5143         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5144         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5145         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5146         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5147         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5148         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5149         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5150         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5151         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5152         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5153         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5154         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5155         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5156         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5157         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5158         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5159         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5160         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5161         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5162         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5163         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5164         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5165         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5166         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5167         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5168         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5169         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5170         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5171         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5172         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5173         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5174         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5175         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5176         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5177         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5178         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5179 };
5180
5181 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5182         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5183         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5184         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5185         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5186         0x00000000
5187 };
5188
5189 #if 0 /* All zeros, don't eat up space with it. */
5190 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5191         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5192         0x00000000, 0x00000000, 0x00000000, 0x00000000
5193 };
5194 #endif
5195
5196 #define RX_CPU_SCRATCH_BASE     0x30000
5197 #define RX_CPU_SCRATCH_SIZE     0x04000
5198 #define TX_CPU_SCRATCH_BASE     0x34000
5199 #define TX_CPU_SCRATCH_SIZE     0x04000
5200
5201 /* tp->lock is held. */
5202 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5203 {
5204         int i;
5205
5206         BUG_ON(offset == TX_CPU_BASE &&
5207             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5208
5209         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5210                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5211
5212                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5213                 return 0;
5214         }
5215         if (offset == RX_CPU_BASE) {
5216                 for (i = 0; i < 10000; i++) {
5217                         tw32(offset + CPU_STATE, 0xffffffff);
5218                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5219                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5220                                 break;
5221                 }
5222
5223                 tw32(offset + CPU_STATE, 0xffffffff);
5224                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5225                 udelay(10);
5226         } else {
5227                 for (i = 0; i < 10000; i++) {
5228                         tw32(offset + CPU_STATE, 0xffffffff);
5229                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5230                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5231                                 break;
5232                 }
5233         }
5234
5235         if (i >= 10000) {
5236                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5237                        "and %s CPU\n",
5238                        tp->dev->name,
5239                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5240                 return -ENODEV;
5241         }
5242
5243         /* Clear firmware's nvram arbitration. */
5244         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5245                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5246         return 0;
5247 }
5248
5249 struct fw_info {
5250         unsigned int text_base;
5251         unsigned int text_len;
5252         const u32 *text_data;
5253         unsigned int rodata_base;
5254         unsigned int rodata_len;
5255         const u32 *rodata_data;
5256         unsigned int data_base;
5257         unsigned int data_len;
5258         const u32 *data_data;
5259 };
5260
5261 /* tp->lock is held. */
5262 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5263                                  int cpu_scratch_size, struct fw_info *info)
5264 {
5265         int err, lock_err, i;
5266         void (*write_op)(struct tg3 *, u32, u32);
5267
5268         if (cpu_base == TX_CPU_BASE &&
5269             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5270                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5271                        "TX cpu firmware on %s which is 5705.\n",
5272                        tp->dev->name);
5273                 return -EINVAL;
5274         }
5275
5276         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5277                 write_op = tg3_write_mem;
5278         else
5279                 write_op = tg3_write_indirect_reg32;
5280
5281         /* It is possible that bootcode is still loading at this point.
5282          * Get the nvram lock first before halting the cpu.
5283          */
5284         lock_err = tg3_nvram_lock(tp);
5285         err = tg3_halt_cpu(tp, cpu_base);
5286         if (!lock_err)
5287                 tg3_nvram_unlock(tp);
5288         if (err)
5289                 goto out;
5290
5291         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5292                 write_op(tp, cpu_scratch_base + i, 0);
5293         tw32(cpu_base + CPU_STATE, 0xffffffff);
5294         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5295         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5296                 write_op(tp, (cpu_scratch_base +
5297                               (info->text_base & 0xffff) +
5298                               (i * sizeof(u32))),
5299                          (info->text_data ?
5300                           info->text_data[i] : 0));
5301         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5302                 write_op(tp, (cpu_scratch_base +
5303                               (info->rodata_base & 0xffff) +
5304                               (i * sizeof(u32))),
5305                          (info->rodata_data ?
5306                           info->rodata_data[i] : 0));
5307         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5308                 write_op(tp, (cpu_scratch_base +
5309                               (info->data_base & 0xffff) +
5310                               (i * sizeof(u32))),
5311                          (info->data_data ?
5312                           info->data_data[i] : 0));
5313
5314         err = 0;
5315
5316 out:
5317         return err;
5318 }
5319
5320 /* tp->lock is held. */
5321 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5322 {
5323         struct fw_info info;
5324         int err, i;
5325
5326         info.text_base = TG3_FW_TEXT_ADDR;
5327         info.text_len = TG3_FW_TEXT_LEN;
5328         info.text_data = &tg3FwText[0];
5329         info.rodata_base = TG3_FW_RODATA_ADDR;
5330         info.rodata_len = TG3_FW_RODATA_LEN;
5331         info.rodata_data = &tg3FwRodata[0];
5332         info.data_base = TG3_FW_DATA_ADDR;
5333         info.data_len = TG3_FW_DATA_LEN;
5334         info.data_data = NULL;
5335
5336         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5337                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5338                                     &info);
5339         if (err)
5340                 return err;
5341
5342         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5343                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5344                                     &info);
5345         if (err)
5346                 return err;
5347
5348         /* Now startup only the RX cpu. */
5349         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5350         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5351
5352         for (i = 0; i < 5; i++) {
5353                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5354                         break;
5355                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5356                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5357                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5358                 udelay(1000);
5359         }
5360         if (i >= 5) {
5361                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5362                        "to set RX CPU PC, is %08x should be %08x\n",
5363                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5364                        TG3_FW_TEXT_ADDR);
5365                 return -ENODEV;
5366         }
5367         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5368         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5369
5370         return 0;
5371 }
5372
5373
5374 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5375 #define TG3_TSO_FW_RELASE_MINOR         0x6
5376 #define TG3_TSO_FW_RELEASE_FIX          0x0
5377 #define TG3_TSO_FW_START_ADDR           0x08000000
5378 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5379 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5380 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5381 #define TG3_TSO_FW_RODATA_LEN           0x60
5382 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5383 #define TG3_TSO_FW_DATA_LEN             0x30
5384 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5385 #define TG3_TSO_FW_SBSS_LEN             0x2c
5386 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5387 #define TG3_TSO_FW_BSS_LEN              0x894
5388
5389 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5390         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5391         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5392         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5393         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5394         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5395         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5396         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5397         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5398         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5399         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5400         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5401         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5402         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5403         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5404         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5405         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5406         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5407         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5408         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5409         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5410         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5411         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5412         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5413         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5414         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5415         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5416         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5417         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5418         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5419         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5420         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5421         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5422         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5423         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5424         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5425         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5426         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5427         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5428         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5429         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5430         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5431         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5432         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5433         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5434         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5435         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5436         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5437         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5438         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5439         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5440         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5441         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5442         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5443         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5444         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5445         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5446         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5447         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5448         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5449         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5450         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5451         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5452         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5453         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5454         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5455         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5456         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5457         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5458         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5459         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5460         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5461         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5462         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5463         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5464         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5465         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5466         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5467         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5468         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5469         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5470         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5471         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5472         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5473         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5474         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5475         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5476         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5477         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5478         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5479         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5480         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5481         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5482         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5483         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5484         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5485         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5486         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5487         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5488         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5489         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5490         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5491         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5492         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5493         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5494         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5495         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5496         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5497         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5498         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5499         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5500         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5501         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5502         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5503         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5504         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5505         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5506         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5507         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5508         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5509         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5510         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5511         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5512         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5513         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5514         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5515         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5516         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5517         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5518         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5519         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5520         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5521         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5522         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5523         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5524         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5525         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5526         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5527         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5528         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5529         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5530         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5531         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5532         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5533         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5534         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5535         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5536         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5537         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5538         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5539         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5540         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5541         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5542         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5543         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5544         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5545         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5546         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5547         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5548         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5549         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5550         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5551         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5552         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5553         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5554         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5555         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5556         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5557         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5558         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5559         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5560         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5561         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5562         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5563         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5564         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5565         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5566         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5567         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5568         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5569         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5570         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5571         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5572         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5573         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5574         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5575         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5576         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5577         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5578         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5579         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5580         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5581         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5582         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5583         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5584         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5585         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5586         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5587         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5588         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5589         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5590         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5591         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5592         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5593         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5594         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5595         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5596         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5597         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5598         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5599         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5600         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5601         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5602         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5603         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5604         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5605         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5606         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5607         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5608         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5609         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5610         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5611         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5612         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5613         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5614         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5615         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5616         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5617         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5618         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5619         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5620         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5621         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5622         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5623         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5624         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5625         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5626         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5627         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5628         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5629         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5630         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5631         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5632         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5633         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5634         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5635         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5636         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5637         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5638         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5639         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5640         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5641         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5642         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5643         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5644         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5645         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5646         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5647         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5648         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5649         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5650         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5651         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5652         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5653         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5654         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5655         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5656         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5657         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5658         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5659         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5660         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5661         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5662         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5663         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5664         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5665         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5666         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5667         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5668         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5669         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5670         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5671         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5672         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5673         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5674 };
5675
5676 static const u32 tg3TsoFwRodata[] = {
5677         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5678         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5679         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5680         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5681         0x00000000,
5682 };
5683
5684 static const u32 tg3TsoFwData[] = {
5685         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5686         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5687         0x00000000,
5688 };
5689
5690 /* 5705 needs a special version of the TSO firmware.  */
5691 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5692 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5693 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5694 #define TG3_TSO5_FW_START_ADDR          0x00010000
5695 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5696 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5697 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5698 #define TG3_TSO5_FW_RODATA_LEN          0x50
5699 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5700 #define TG3_TSO5_FW_DATA_LEN            0x20
5701 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5702 #define TG3_TSO5_FW_SBSS_LEN            0x28
5703 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5704 #define TG3_TSO5_FW_BSS_LEN             0x88
5705
5706 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5707         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5708         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5709         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5710         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5711         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5712         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5713         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5714         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5715         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5716         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5717         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5718         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5719         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5720         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5721         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5722         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5723         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5724         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5725         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5726         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5727         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5728         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5729         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5730         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5731         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5732         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5733         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5734         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5735         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5736         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5737         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5738         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5739         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5740         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5741         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5742         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5743         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5744         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5745         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5746         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5747         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5748         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5749         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5750         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5751         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5752         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5753         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5754         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5755         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5756         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5757         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5758         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5759         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5760         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5761         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5762         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5763         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5764         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5765         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5766         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5767         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5768         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5769         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5770         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5771         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5772         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5773         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5774         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5775         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5776         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5777         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5778         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5779         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5780         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5781         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5782         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5783         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5784         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5785         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5786         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5787         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5788         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5789         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5790         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5791         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5792         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5793         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5794         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5795         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5796         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5797         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5798         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5799         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5800         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5801         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5802         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5803         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5804         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5805         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5806         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5807         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5808         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5809         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5810         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5811         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5812         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5813         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5814         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5815         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5816         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5817         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5818         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5819         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5820         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5821         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5822         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5823         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5824         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5825         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5826         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5827         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5828         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5829         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5830         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5831         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5832         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5833         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5834         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5835         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5836         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5837         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5838         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5839         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5840         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5841         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5842         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5843         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5844         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5845         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5846         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5847         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5848         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5849         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5850         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5851         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5852         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5853         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5854         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5855         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5856         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5857         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5858         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5859         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5860         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5861         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5862         0x00000000, 0x00000000, 0x00000000,
5863 };
5864
5865 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5866         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5867         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5868         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5869         0x00000000, 0x00000000, 0x00000000,
5870 };
5871
5872 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5873         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5874         0x00000000, 0x00000000, 0x00000000,
5875 };
5876
5877 /* tp->lock is held. */
5878 static int tg3_load_tso_firmware(struct tg3 *tp)
5879 {
5880         struct fw_info info;
5881         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5882         int err, i;
5883
5884         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5885                 return 0;
5886
5887         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5888                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5889                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5890                 info.text_data = &tg3Tso5FwText[0];
5891                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5892                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5893                 info.rodata_data = &tg3Tso5FwRodata[0];
5894                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5895                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5896                 info.data_data = &tg3Tso5FwData[0];
5897                 cpu_base = RX_CPU_BASE;
5898                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5899                 cpu_scratch_size = (info.text_len +
5900                                     info.rodata_len +
5901                                     info.data_len +
5902                                     TG3_TSO5_FW_SBSS_LEN +
5903                                     TG3_TSO5_FW_BSS_LEN);
5904         } else {
5905                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5906                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5907                 info.text_data = &tg3TsoFwText[0];
5908                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5909                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5910                 info.rodata_data = &tg3TsoFwRodata[0];
5911                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5912                 info.data_len = TG3_TSO_FW_DATA_LEN;
5913                 info.data_data = &tg3TsoFwData[0];
5914                 cpu_base = TX_CPU_BASE;
5915                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5916                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5917         }
5918
5919         err = tg3_load_firmware_cpu(tp, cpu_base,
5920                                     cpu_scratch_base, cpu_scratch_size,
5921                                     &info);
5922         if (err)
5923                 return err;
5924
5925         /* Now startup the cpu. */
5926         tw32(cpu_base + CPU_STATE, 0xffffffff);
5927         tw32_f(cpu_base + CPU_PC,    info.text_base);
5928
5929         for (i = 0; i < 5; i++) {
5930                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5931                         break;
5932                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5933                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5934                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5935                 udelay(1000);
5936         }
5937         if (i >= 5) {
5938                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5939                        "to set CPU PC, is %08x should be %08x\n",
5940                        tp->dev->name, tr32(cpu_base + CPU_PC),
5941                        info.text_base);
5942                 return -ENODEV;
5943         }
5944         tw32(cpu_base + CPU_STATE, 0xffffffff);
5945         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5946         return 0;
5947 }
5948
5949
5950 /* tp->lock is held. */
5951 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
5952 {
5953         u32 addr_high, addr_low;
5954         int i;
5955
5956         addr_high = ((tp->dev->dev_addr[0] << 8) |
5957                      tp->dev->dev_addr[1]);
5958         addr_low = ((tp->dev->dev_addr[2] << 24) |
5959                     (tp->dev->dev_addr[3] << 16) |
5960                     (tp->dev->dev_addr[4] <<  8) |
5961                     (tp->dev->dev_addr[5] <<  0));
5962         for (i = 0; i < 4; i++) {
5963                 if (i == 1 && skip_mac_1)
5964                         continue;
5965                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5966                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5967         }
5968
5969         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5970             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5971                 for (i = 0; i < 12; i++) {
5972                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5973                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5974                 }
5975         }
5976
5977         addr_high = (tp->dev->dev_addr[0] +
5978                      tp->dev->dev_addr[1] +
5979                      tp->dev->dev_addr[2] +
5980                      tp->dev->dev_addr[3] +
5981                      tp->dev->dev_addr[4] +
5982                      tp->dev->dev_addr[5]) &
5983                 TX_BACKOFF_SEED_MASK;
5984         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5985 }
5986
5987 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5988 {
5989         struct tg3 *tp = netdev_priv(dev);
5990         struct sockaddr *addr = p;
5991         int err = 0, skip_mac_1 = 0;
5992
5993         if (!is_valid_ether_addr(addr->sa_data))
5994                 return -EINVAL;
5995
5996         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5997
5998         if (!netif_running(dev))
5999                 return 0;
6000
6001         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6002                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6003
6004                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6005                 addr0_low = tr32(MAC_ADDR_0_LOW);
6006                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6007                 addr1_low = tr32(MAC_ADDR_1_LOW);
6008
6009                 /* Skip MAC addr 1 if ASF is using it. */
6010                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6011                     !(addr1_high == 0 && addr1_low == 0))
6012                         skip_mac_1 = 1;
6013         }
6014         spin_lock_bh(&tp->lock);
6015         __tg3_set_mac_addr(tp, skip_mac_1);
6016         spin_unlock_bh(&tp->lock);
6017
6018         return err;
6019 }
6020
6021 /* tp->lock is held. */
6022 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6023                            dma_addr_t mapping, u32 maxlen_flags,
6024                            u32 nic_addr)
6025 {
6026         tg3_write_mem(tp,
6027                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6028                       ((u64) mapping >> 32));
6029         tg3_write_mem(tp,
6030                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6031                       ((u64) mapping & 0xffffffff));
6032         tg3_write_mem(tp,
6033                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6034                        maxlen_flags);
6035
6036         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6037                 tg3_write_mem(tp,
6038                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6039                               nic_addr);
6040 }
6041
6042 static void __tg3_set_rx_mode(struct net_device *);
6043 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6044 {
6045         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6046         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6047         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6048         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6049         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6050                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6051                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6052         }
6053         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6054         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6055         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6056                 u32 val = ec->stats_block_coalesce_usecs;
6057
6058                 if (!netif_carrier_ok(tp->dev))
6059                         val = 0;
6060
6061                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6062         }
6063 }
6064
6065 /* tp->lock is held. */
6066 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6067 {
6068         u32 val, rdmac_mode;
6069         int i, err, limit;
6070
6071         tg3_disable_ints(tp);
6072
6073         tg3_stop_fw(tp);
6074
6075         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6076
6077         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6078                 tg3_abort_hw(tp, 1);
6079         }
6080
6081         if (reset_phy)
6082                 tg3_phy_reset(tp);
6083
6084         err = tg3_chip_reset(tp);
6085         if (err)
6086                 return err;
6087
6088         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6089
6090         /* This works around an issue with Athlon chipsets on
6091          * B3 tigon3 silicon.  This bit has no effect on any
6092          * other revision.  But do not set this on PCI Express
6093          * chips.
6094          */
6095         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6096                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6097         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6098
6099         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6100             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6101                 val = tr32(TG3PCI_PCISTATE);
6102                 val |= PCISTATE_RETRY_SAME_DMA;
6103                 tw32(TG3PCI_PCISTATE, val);
6104         }
6105
6106         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6107                 /* Enable some hw fixes.  */
6108                 val = tr32(TG3PCI_MSI_DATA);
6109                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6110                 tw32(TG3PCI_MSI_DATA, val);
6111         }
6112
6113         /* Descriptor ring init may make accesses to the
6114          * NIC SRAM area to setup the TX descriptors, so we
6115          * can only do this after the hardware has been
6116          * successfully reset.
6117          */
6118         err = tg3_init_rings(tp);
6119         if (err)
6120                 return err;
6121
6122         /* This value is determined during the probe time DMA
6123          * engine test, tg3_test_dma.
6124          */
6125         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6126
6127         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6128                           GRC_MODE_4X_NIC_SEND_RINGS |
6129                           GRC_MODE_NO_TX_PHDR_CSUM |
6130                           GRC_MODE_NO_RX_PHDR_CSUM);
6131         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6132
6133         /* Pseudo-header checksum is done by hardware logic and not
6134          * the offload processers, so make the chip do the pseudo-
6135          * header checksums on receive.  For transmit it is more
6136          * convenient to do the pseudo-header checksum in software
6137          * as Linux does that on transmit for us in all cases.
6138          */
6139         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6140
6141         tw32(GRC_MODE,
6142              tp->grc_mode |
6143              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6144
6145         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6146         val = tr32(GRC_MISC_CFG);
6147         val &= ~0xff;
6148         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6149         tw32(GRC_MISC_CFG, val);
6150
6151         /* Initialize MBUF/DESC pool. */
6152         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6153                 /* Do nothing.  */
6154         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6155                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6156                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6157                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6158                 else
6159                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6160                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6161                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6162         }
6163         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6164                 int fw_len;
6165
6166                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6167                           TG3_TSO5_FW_RODATA_LEN +
6168                           TG3_TSO5_FW_DATA_LEN +
6169                           TG3_TSO5_FW_SBSS_LEN +
6170                           TG3_TSO5_FW_BSS_LEN);
6171                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6172                 tw32(BUFMGR_MB_POOL_ADDR,
6173                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6174                 tw32(BUFMGR_MB_POOL_SIZE,
6175                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6176         }
6177
6178         if (tp->dev->mtu <= ETH_DATA_LEN) {
6179                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6180                      tp->bufmgr_config.mbuf_read_dma_low_water);
6181                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6182                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6183                 tw32(BUFMGR_MB_HIGH_WATER,
6184                      tp->bufmgr_config.mbuf_high_water);
6185         } else {
6186                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6187                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6188                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6189                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6190                 tw32(BUFMGR_MB_HIGH_WATER,
6191                      tp->bufmgr_config.mbuf_high_water_jumbo);
6192         }
6193         tw32(BUFMGR_DMA_LOW_WATER,
6194              tp->bufmgr_config.dma_low_water);
6195         tw32(BUFMGR_DMA_HIGH_WATER,
6196              tp->bufmgr_config.dma_high_water);
6197
6198         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6199         for (i = 0; i < 2000; i++) {
6200                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6201                         break;
6202                 udelay(10);
6203         }
6204         if (i >= 2000) {
6205                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6206                        tp->dev->name);
6207                 return -ENODEV;
6208         }
6209
6210         /* Setup replenish threshold. */
6211         val = tp->rx_pending / 8;
6212         if (val == 0)
6213                 val = 1;
6214         else if (val > tp->rx_std_max_post)
6215                 val = tp->rx_std_max_post;
6216         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6217                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6218                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6219
6220                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6221                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6222         }
6223
6224         tw32(RCVBDI_STD_THRESH, val);
6225
6226         /* Initialize TG3_BDINFO's at:
6227          *  RCVDBDI_STD_BD:     standard eth size rx ring
6228          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6229          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6230          *
6231          * like so:
6232          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6233          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6234          *                              ring attribute flags
6235          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6236          *
6237          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6238          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6239          *
6240          * The size of each ring is fixed in the firmware, but the location is
6241          * configurable.
6242          */
6243         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6244              ((u64) tp->rx_std_mapping >> 32));
6245         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6246              ((u64) tp->rx_std_mapping & 0xffffffff));
6247         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6248              NIC_SRAM_RX_BUFFER_DESC);
6249
6250         /* Don't even try to program the JUMBO/MINI buffer descriptor
6251          * configs on 5705.
6252          */
6253         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6254                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6255                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6256         } else {
6257                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6258                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6259
6260                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6261                      BDINFO_FLAGS_DISABLED);
6262
6263                 /* Setup replenish threshold. */
6264                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6265
6266                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6267                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6268                              ((u64) tp->rx_jumbo_mapping >> 32));
6269                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6270                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6271                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6272                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6273                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6274                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6275                 } else {
6276                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6277                              BDINFO_FLAGS_DISABLED);
6278                 }
6279
6280         }
6281
6282         /* There is only one send ring on 5705/5750, no need to explicitly
6283          * disable the others.
6284          */
6285         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6286                 /* Clear out send RCB ring in SRAM. */
6287                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6288                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6289                                       BDINFO_FLAGS_DISABLED);
6290         }
6291
6292         tp->tx_prod = 0;
6293         tp->tx_cons = 0;
6294         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6295         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6296
6297         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6298                        tp->tx_desc_mapping,
6299                        (TG3_TX_RING_SIZE <<
6300                         BDINFO_FLAGS_MAXLEN_SHIFT),
6301                        NIC_SRAM_TX_BUFFER_DESC);
6302
6303         /* There is only one receive return ring on 5705/5750, no need
6304          * to explicitly disable the others.
6305          */
6306         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6307                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6308                      i += TG3_BDINFO_SIZE) {
6309                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6310                                       BDINFO_FLAGS_DISABLED);
6311                 }
6312         }
6313
6314         tp->rx_rcb_ptr = 0;
6315         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6316
6317         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6318                        tp->rx_rcb_mapping,
6319                        (TG3_RX_RCB_RING_SIZE(tp) <<
6320                         BDINFO_FLAGS_MAXLEN_SHIFT),
6321                        0);
6322
6323         tp->rx_std_ptr = tp->rx_pending;
6324         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6325                      tp->rx_std_ptr);
6326
6327         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6328                                                 tp->rx_jumbo_pending : 0;
6329         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6330                      tp->rx_jumbo_ptr);
6331
6332         /* Initialize MAC address and backoff seed. */
6333         __tg3_set_mac_addr(tp, 0);
6334
6335         /* MTU + ethernet header + FCS + optional VLAN tag */
6336         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6337
6338         /* The slot time is changed by tg3_setup_phy if we
6339          * run at gigabit with half duplex.
6340          */
6341         tw32(MAC_TX_LENGTHS,
6342              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6343              (6 << TX_LENGTHS_IPG_SHIFT) |
6344              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6345
6346         /* Receive rules. */
6347         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6348         tw32(RCVLPC_CONFIG, 0x0181);
6349
6350         /* Calculate RDMAC_MODE setting early, we need it to determine
6351          * the RCVLPC_STATE_ENABLE mask.
6352          */
6353         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6354                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6355                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6356                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6357                       RDMAC_MODE_LNGREAD_ENAB);
6358
6359         /* If statement applies to 5705 and 5750 PCI devices only */
6360         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6361              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6362             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6363                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6364                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6365                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6366                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6367                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6368                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6369                 }
6370         }
6371
6372         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6373                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6374
6375         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6376                 rdmac_mode |= (1 << 27);
6377
6378         /* Receive/send statistics. */
6379         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6380                 val = tr32(RCVLPC_STATS_ENABLE);
6381                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6382                 tw32(RCVLPC_STATS_ENABLE, val);
6383         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6384                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6385                 val = tr32(RCVLPC_STATS_ENABLE);
6386                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6387                 tw32(RCVLPC_STATS_ENABLE, val);
6388         } else {
6389                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6390         }
6391         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6392         tw32(SNDDATAI_STATSENAB, 0xffffff);
6393         tw32(SNDDATAI_STATSCTRL,
6394              (SNDDATAI_SCTRL_ENABLE |
6395               SNDDATAI_SCTRL_FASTUPD));
6396
6397         /* Setup host coalescing engine. */
6398         tw32(HOSTCC_MODE, 0);
6399         for (i = 0; i < 2000; i++) {
6400                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6401                         break;
6402                 udelay(10);
6403         }
6404
6405         __tg3_set_coalesce(tp, &tp->coal);
6406
6407         /* set status block DMA address */
6408         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6409              ((u64) tp->status_mapping >> 32));
6410         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6411              ((u64) tp->status_mapping & 0xffffffff));
6412
6413         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6414                 /* Status/statistics block address.  See tg3_timer,
6415                  * the tg3_periodic_fetch_stats call there, and
6416                  * tg3_get_stats to see how this works for 5705/5750 chips.
6417                  */
6418                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6419                      ((u64) tp->stats_mapping >> 32));
6420                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6421                      ((u64) tp->stats_mapping & 0xffffffff));
6422                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6423                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6424         }
6425
6426         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6427
6428         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6429         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6430         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6431                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6432
6433         /* Clear statistics/status block in chip, and status block in ram. */
6434         for (i = NIC_SRAM_STATS_BLK;
6435              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6436              i += sizeof(u32)) {
6437                 tg3_write_mem(tp, i, 0);
6438                 udelay(40);
6439         }
6440         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6441
6442         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6443                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6444                 /* reset to prevent losing 1st rx packet intermittently */
6445                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6446                 udelay(10);
6447         }
6448
6449         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6450                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6451         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6452         udelay(40);
6453
6454         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6455          * If TG3_FLG2_IS_NIC is zero, we should read the
6456          * register to preserve the GPIO settings for LOMs. The GPIOs,
6457          * whether used as inputs or outputs, are set by boot code after
6458          * reset.
6459          */
6460         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6461                 u32 gpio_mask;
6462
6463                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6464                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6465                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6466
6467                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6468                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6469                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6470
6471                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6472                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6473
6474                 tp->grc_local_ctrl &= ~gpio_mask;
6475                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6476
6477                 /* GPIO1 must be driven high for eeprom write protect */
6478                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6479                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6480                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6481         }
6482         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6483         udelay(100);
6484
6485         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6486         tp->last_tag = 0;
6487
6488         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6489                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6490                 udelay(40);
6491         }
6492
6493         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6494                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6495                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6496                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6497                WDMAC_MODE_LNGREAD_ENAB);
6498
6499         /* If statement applies to 5705 and 5750 PCI devices only */
6500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6501              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6502             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6503                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6504                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6505                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6506                         /* nothing */
6507                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6508                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6509                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6510                         val |= WDMAC_MODE_RX_ACCEL;
6511                 }
6512         }
6513
6514         /* Enable host coalescing bug fix */
6515         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6516             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6517                 val |= (1 << 29);
6518
6519         tw32_f(WDMAC_MODE, val);
6520         udelay(40);
6521
6522         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6523                 val = tr32(TG3PCI_X_CAPS);
6524                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6525                         val &= ~PCIX_CAPS_BURST_MASK;
6526                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6527                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6528                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6529                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6530                 }
6531                 tw32(TG3PCI_X_CAPS, val);
6532         }
6533
6534         tw32_f(RDMAC_MODE, rdmac_mode);
6535         udelay(40);
6536
6537         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6538         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6539                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6540         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6541         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6542         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6543         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6544         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6545         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6546                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6547         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6548         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6549
6550         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6551                 err = tg3_load_5701_a0_firmware_fix(tp);
6552                 if (err)
6553                         return err;
6554         }
6555
6556         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6557                 err = tg3_load_tso_firmware(tp);
6558                 if (err)
6559                         return err;
6560         }
6561
6562         tp->tx_mode = TX_MODE_ENABLE;
6563         tw32_f(MAC_TX_MODE, tp->tx_mode);
6564         udelay(100);
6565
6566         tp->rx_mode = RX_MODE_ENABLE;
6567         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6568                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6569
6570         tw32_f(MAC_RX_MODE, tp->rx_mode);
6571         udelay(10);
6572
6573         if (tp->link_config.phy_is_low_power) {
6574                 tp->link_config.phy_is_low_power = 0;
6575                 tp->link_config.speed = tp->link_config.orig_speed;
6576                 tp->link_config.duplex = tp->link_config.orig_duplex;
6577                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6578         }
6579
6580         tp->mi_mode = MAC_MI_MODE_BASE;
6581         tw32_f(MAC_MI_MODE, tp->mi_mode);
6582         udelay(80);
6583
6584         tw32(MAC_LED_CTRL, tp->led_ctrl);
6585
6586         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6587         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6588                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6589                 udelay(10);
6590         }
6591         tw32_f(MAC_RX_MODE, tp->rx_mode);
6592         udelay(10);
6593
6594         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6595                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6596                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6597                         /* Set drive transmission level to 1.2V  */
6598                         /* only if the signal pre-emphasis bit is not set  */
6599                         val = tr32(MAC_SERDES_CFG);
6600                         val &= 0xfffff000;
6601                         val |= 0x880;
6602                         tw32(MAC_SERDES_CFG, val);
6603                 }
6604                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6605                         tw32(MAC_SERDES_CFG, 0x616000);
6606         }
6607
6608         /* Prevent chip from dropping frames when flow control
6609          * is enabled.
6610          */
6611         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6612
6613         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6614             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6615                 /* Use hardware link auto-negotiation */
6616                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6617         }
6618
6619         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6620             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6621                 u32 tmp;
6622
6623                 tmp = tr32(SERDES_RX_CTRL);
6624                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6625                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6626                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6627                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6628         }
6629
6630         err = tg3_setup_phy(tp, 0);
6631         if (err)
6632                 return err;
6633
6634         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6635             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6636                 u32 tmp;
6637
6638                 /* Clear CRC stats. */
6639                 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6640                         tg3_writephy(tp, MII_TG3_TEST1,
6641                                      tmp | MII_TG3_TEST1_CRC_EN);
6642                         tg3_readphy(tp, 0x14, &tmp);
6643                 }
6644         }
6645
6646         __tg3_set_rx_mode(tp->dev);
6647
6648         /* Initialize receive rules. */
6649         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6650         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6651         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6652         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6653
6654         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6655             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6656                 limit = 8;
6657         else
6658                 limit = 16;
6659         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6660                 limit -= 4;
6661         switch (limit) {
6662         case 16:
6663                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6664         case 15:
6665                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6666         case 14:
6667                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6668         case 13:
6669                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6670         case 12:
6671                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6672         case 11:
6673                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6674         case 10:
6675                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6676         case 9:
6677                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6678         case 8:
6679                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6680         case 7:
6681                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6682         case 6:
6683                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6684         case 5:
6685                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6686         case 4:
6687                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6688         case 3:
6689                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6690         case 2:
6691         case 1:
6692
6693         default:
6694                 break;
6695         };
6696
6697         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6698
6699         return 0;
6700 }
6701
6702 /* Called at device open time to get the chip ready for
6703  * packet processing.  Invoked with tp->lock held.
6704  */
6705 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6706 {
6707         int err;
6708
6709         /* Force the chip into D0. */
6710         err = tg3_set_power_state(tp, PCI_D0);
6711         if (err)
6712                 goto out;
6713
6714         tg3_switch_clocks(tp);
6715
6716         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6717
6718         err = tg3_reset_hw(tp, reset_phy);
6719
6720 out:
6721         return err;
6722 }
6723
6724 #define TG3_STAT_ADD32(PSTAT, REG) \
6725 do {    u32 __val = tr32(REG); \
6726         (PSTAT)->low += __val; \
6727         if ((PSTAT)->low < __val) \
6728                 (PSTAT)->high += 1; \
6729 } while (0)
6730
6731 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6732 {
6733         struct tg3_hw_stats *sp = tp->hw_stats;
6734
6735         if (!netif_carrier_ok(tp->dev))
6736                 return;
6737
6738         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6739         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6740         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6741         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6742         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6743         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6744         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6745         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6746         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6747         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6748         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6749         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6750         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6751
6752         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6753         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6754         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6755         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6756         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6757         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6758         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6759         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6760         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6761         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6762         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6763         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6764         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6765         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6766
6767         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6768         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6769         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6770 }
6771
6772 static void tg3_timer(unsigned long __opaque)
6773 {
6774         struct tg3 *tp = (struct tg3 *) __opaque;
6775
6776         if (tp->irq_sync)
6777                 goto restart_timer;
6778
6779         spin_lock(&tp->lock);
6780
6781         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6782                 /* All of this garbage is because when using non-tagged
6783                  * IRQ status the mailbox/status_block protocol the chip
6784                  * uses with the cpu is race prone.
6785                  */
6786                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6787                         tw32(GRC_LOCAL_CTRL,
6788                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6789                 } else {
6790                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6791                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6792                 }
6793
6794                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6795                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6796                         spin_unlock(&tp->lock);
6797                         schedule_work(&tp->reset_task);
6798                         return;
6799                 }
6800         }
6801
6802         /* This part only runs once per second. */
6803         if (!--tp->timer_counter) {
6804                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6805                         tg3_periodic_fetch_stats(tp);
6806
6807                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6808                         u32 mac_stat;
6809                         int phy_event;
6810
6811                         mac_stat = tr32(MAC_STATUS);
6812
6813                         phy_event = 0;
6814                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6815                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6816                                         phy_event = 1;
6817                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6818                                 phy_event = 1;
6819
6820                         if (phy_event)
6821                                 tg3_setup_phy(tp, 0);
6822                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6823                         u32 mac_stat = tr32(MAC_STATUS);
6824                         int need_setup = 0;
6825
6826                         if (netif_carrier_ok(tp->dev) &&
6827                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6828                                 need_setup = 1;
6829                         }
6830                         if (! netif_carrier_ok(tp->dev) &&
6831                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6832                                          MAC_STATUS_SIGNAL_DET))) {
6833                                 need_setup = 1;
6834                         }
6835                         if (need_setup) {
6836                                 if (!tp->serdes_counter) {
6837                                         tw32_f(MAC_MODE,
6838                                              (tp->mac_mode &
6839                                               ~MAC_MODE_PORT_MODE_MASK));
6840                                         udelay(40);
6841                                         tw32_f(MAC_MODE, tp->mac_mode);
6842                                         udelay(40);
6843                                 }
6844                                 tg3_setup_phy(tp, 0);
6845                         }
6846                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6847                         tg3_serdes_parallel_detect(tp);
6848
6849                 tp->timer_counter = tp->timer_multiplier;
6850         }
6851
6852         /* Heartbeat is only sent once every 2 seconds.
6853          *
6854          * The heartbeat is to tell the ASF firmware that the host
6855          * driver is still alive.  In the event that the OS crashes,
6856          * ASF needs to reset the hardware to free up the FIFO space
6857          * that may be filled with rx packets destined for the host.
6858          * If the FIFO is full, ASF will no longer function properly.
6859          *
6860          * Unintended resets have been reported on real time kernels
6861          * where the timer doesn't run on time.  Netpoll will also have
6862          * same problem.
6863          *
6864          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6865          * to check the ring condition when the heartbeat is expiring
6866          * before doing the reset.  This will prevent most unintended
6867          * resets.
6868          */
6869         if (!--tp->asf_counter) {
6870                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6871                         u32 val;
6872
6873                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6874                                       FWCMD_NICDRV_ALIVE3);
6875                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6876                         /* 5 seconds timeout */
6877                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6878                         val = tr32(GRC_RX_CPU_EVENT);
6879                         val |= (1 << 14);
6880                         tw32(GRC_RX_CPU_EVENT, val);
6881                 }
6882                 tp->asf_counter = tp->asf_multiplier;
6883         }
6884
6885         spin_unlock(&tp->lock);
6886
6887 restart_timer:
6888         tp->timer.expires = jiffies + tp->timer_offset;
6889         add_timer(&tp->timer);
6890 }
6891
6892 static int tg3_request_irq(struct tg3 *tp)
6893 {
6894         irq_handler_t fn;
6895         unsigned long flags;
6896         struct net_device *dev = tp->dev;
6897
6898         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6899                 fn = tg3_msi;
6900                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6901                         fn = tg3_msi_1shot;
6902                 flags = IRQF_SAMPLE_RANDOM;
6903         } else {
6904                 fn = tg3_interrupt;
6905                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6906                         fn = tg3_interrupt_tagged;
6907                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6908         }
6909         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6910 }
6911
6912 static int tg3_test_interrupt(struct tg3 *tp)
6913 {
6914         struct net_device *dev = tp->dev;
6915         int err, i, intr_ok = 0;
6916
6917         if (!netif_running(dev))
6918                 return -ENODEV;
6919
6920         tg3_disable_ints(tp);
6921
6922         free_irq(tp->pdev->irq, dev);
6923
6924         err = request_irq(tp->pdev->irq, tg3_test_isr,
6925                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6926         if (err)
6927                 return err;
6928
6929         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6930         tg3_enable_ints(tp);
6931
6932         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6933                HOSTCC_MODE_NOW);
6934
6935         for (i = 0; i < 5; i++) {
6936                 u32 int_mbox, misc_host_ctrl;
6937
6938                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6939                                         TG3_64BIT_REG_LOW);
6940                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6941
6942                 if ((int_mbox != 0) ||
6943                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6944                         intr_ok = 1;
6945                         break;
6946                 }
6947
6948                 msleep(10);
6949         }
6950
6951         tg3_disable_ints(tp);
6952
6953         free_irq(tp->pdev->irq, dev);
6954
6955         err = tg3_request_irq(tp);
6956
6957         if (err)
6958                 return err;
6959
6960         if (intr_ok)
6961                 return 0;
6962
6963         return -EIO;
6964 }
6965
6966 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6967  * successfully restored
6968  */
6969 static int tg3_test_msi(struct tg3 *tp)
6970 {
6971         struct net_device *dev = tp->dev;
6972         int err;
6973         u16 pci_cmd;
6974
6975         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6976                 return 0;
6977
6978         /* Turn off SERR reporting in case MSI terminates with Master
6979          * Abort.
6980          */
6981         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6982         pci_write_config_word(tp->pdev, PCI_COMMAND,
6983                               pci_cmd & ~PCI_COMMAND_SERR);
6984
6985         err = tg3_test_interrupt(tp);
6986
6987         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6988
6989         if (!err)
6990                 return 0;
6991
6992         /* other failures */
6993         if (err != -EIO)
6994                 return err;
6995
6996         /* MSI test failed, go back to INTx mode */
6997         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6998                "switching to INTx mode. Please report this failure to "
6999                "the PCI maintainer and include system chipset information.\n",
7000                        tp->dev->name);
7001
7002         free_irq(tp->pdev->irq, dev);
7003         pci_disable_msi(tp->pdev);
7004
7005         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7006
7007         err = tg3_request_irq(tp);
7008         if (err)
7009                 return err;
7010
7011         /* Need to reset the chip because the MSI cycle may have terminated
7012          * with Master Abort.
7013          */
7014         tg3_full_lock(tp, 1);
7015
7016         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7017         err = tg3_init_hw(tp, 1);
7018
7019         tg3_full_unlock(tp);
7020
7021         if (err)
7022                 free_irq(tp->pdev->irq, dev);
7023
7024         return err;
7025 }
7026
7027 static int tg3_open(struct net_device *dev)
7028 {
7029         struct tg3 *tp = netdev_priv(dev);
7030         int err;
7031
7032         netif_carrier_off(tp->dev);
7033
7034         tg3_full_lock(tp, 0);
7035
7036         err = tg3_set_power_state(tp, PCI_D0);
7037         if (err) {
7038                 tg3_full_unlock(tp);
7039                 return err;
7040         }
7041
7042         tg3_disable_ints(tp);
7043         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7044
7045         tg3_full_unlock(tp);
7046
7047         /* The placement of this call is tied
7048          * to the setup and use of Host TX descriptors.
7049          */
7050         err = tg3_alloc_consistent(tp);
7051         if (err)
7052                 return err;
7053
7054         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7055                 /* All MSI supporting chips should support tagged
7056                  * status.  Assert that this is the case.
7057                  */
7058                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7059                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7060                                "Not using MSI.\n", tp->dev->name);
7061                 } else if (pci_enable_msi(tp->pdev) == 0) {
7062                         u32 msi_mode;
7063
7064                         msi_mode = tr32(MSGINT_MODE);
7065                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7066                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7067                 }
7068         }
7069         err = tg3_request_irq(tp);
7070
7071         if (err) {
7072                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7073                         pci_disable_msi(tp->pdev);
7074                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7075                 }
7076                 tg3_free_consistent(tp);
7077                 return err;
7078         }
7079
7080         tg3_full_lock(tp, 0);
7081
7082         err = tg3_init_hw(tp, 1);
7083         if (err) {
7084                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7085                 tg3_free_rings(tp);
7086         } else {
7087                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7088                         tp->timer_offset = HZ;
7089                 else
7090                         tp->timer_offset = HZ / 10;
7091
7092                 BUG_ON(tp->timer_offset > HZ);
7093                 tp->timer_counter = tp->timer_multiplier =
7094                         (HZ / tp->timer_offset);
7095                 tp->asf_counter = tp->asf_multiplier =
7096                         ((HZ / tp->timer_offset) * 2);
7097
7098                 init_timer(&tp->timer);
7099                 tp->timer.expires = jiffies + tp->timer_offset;
7100                 tp->timer.data = (unsigned long) tp;
7101                 tp->timer.function = tg3_timer;
7102         }
7103
7104         tg3_full_unlock(tp);
7105
7106         if (err) {
7107                 free_irq(tp->pdev->irq, dev);
7108                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7109                         pci_disable_msi(tp->pdev);
7110                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7111                 }
7112                 tg3_free_consistent(tp);
7113                 return err;
7114         }
7115
7116         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7117                 err = tg3_test_msi(tp);
7118
7119                 if (err) {
7120                         tg3_full_lock(tp, 0);
7121
7122                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7123                                 pci_disable_msi(tp->pdev);
7124                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7125                         }
7126                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7127                         tg3_free_rings(tp);
7128                         tg3_free_consistent(tp);
7129
7130                         tg3_full_unlock(tp);
7131
7132                         return err;
7133                 }
7134
7135                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7136                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7137                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7138
7139                                 tw32(PCIE_TRANSACTION_CFG,
7140                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7141                         }
7142                 }
7143         }
7144
7145         tg3_full_lock(tp, 0);
7146
7147         add_timer(&tp->timer);
7148         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7149         tg3_enable_ints(tp);
7150
7151         tg3_full_unlock(tp);
7152
7153         netif_start_queue(dev);
7154
7155         return 0;
7156 }
7157
7158 #if 0
7159 /*static*/ void tg3_dump_state(struct tg3 *tp)
7160 {
7161         u32 val32, val32_2, val32_3, val32_4, val32_5;
7162         u16 val16;
7163         int i;
7164
7165         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7166         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7167         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7168                val16, val32);
7169
7170         /* MAC block */
7171         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7172                tr32(MAC_MODE), tr32(MAC_STATUS));
7173         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7174                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7175         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7176                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7177         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7178                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7179
7180         /* Send data initiator control block */
7181         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7182                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7183         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7184                tr32(SNDDATAI_STATSCTRL));
7185
7186         /* Send data completion control block */
7187         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7188
7189         /* Send BD ring selector block */
7190         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7191                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7192
7193         /* Send BD initiator control block */
7194         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7195                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7196
7197         /* Send BD completion control block */
7198         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7199
7200         /* Receive list placement control block */
7201         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7202                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7203         printk("       RCVLPC_STATSCTRL[%08x]\n",
7204                tr32(RCVLPC_STATSCTRL));
7205
7206         /* Receive data and receive BD initiator control block */
7207         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7208                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7209
7210         /* Receive data completion control block */
7211         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7212                tr32(RCVDCC_MODE));
7213
7214         /* Receive BD initiator control block */
7215         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7216                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7217
7218         /* Receive BD completion control block */
7219         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7220                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7221
7222         /* Receive list selector control block */
7223         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7224                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7225
7226         /* Mbuf cluster free block */
7227         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7228                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7229
7230         /* Host coalescing control block */
7231         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7232                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7233         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7234                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7235                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7236         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7237                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7238                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7239         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7240                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7241         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7242                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7243
7244         /* Memory arbiter control block */
7245         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7246                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7247
7248         /* Buffer manager control block */
7249         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7250                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7251         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7252                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7253         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7254                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7255                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7256                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7257
7258         /* Read DMA control block */
7259         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7260                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7261
7262         /* Write DMA control block */
7263         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7264                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7265
7266         /* DMA completion block */
7267         printk("DEBUG: DMAC_MODE[%08x]\n",
7268                tr32(DMAC_MODE));
7269
7270         /* GRC block */
7271         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7272                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7273         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7274                tr32(GRC_LOCAL_CTRL));
7275
7276         /* TG3_BDINFOs */
7277         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7278                tr32(RCVDBDI_JUMBO_BD + 0x0),
7279                tr32(RCVDBDI_JUMBO_BD + 0x4),
7280                tr32(RCVDBDI_JUMBO_BD + 0x8),
7281                tr32(RCVDBDI_JUMBO_BD + 0xc));
7282         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7283                tr32(RCVDBDI_STD_BD + 0x0),
7284                tr32(RCVDBDI_STD_BD + 0x4),
7285                tr32(RCVDBDI_STD_BD + 0x8),
7286                tr32(RCVDBDI_STD_BD + 0xc));
7287         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7288                tr32(RCVDBDI_MINI_BD + 0x0),
7289                tr32(RCVDBDI_MINI_BD + 0x4),
7290                tr32(RCVDBDI_MINI_BD + 0x8),
7291                tr32(RCVDBDI_MINI_BD + 0xc));
7292
7293         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7294         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7295         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7296         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7297         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7298                val32, val32_2, val32_3, val32_4);
7299
7300         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7301         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7302         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7303         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7304         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7305                val32, val32_2, val32_3, val32_4);
7306
7307         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7308         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7309         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7310         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7311         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7312         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7313                val32, val32_2, val32_3, val32_4, val32_5);
7314
7315         /* SW status block */
7316         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7317                tp->hw_status->status,
7318                tp->hw_status->status_tag,
7319                tp->hw_status->rx_jumbo_consumer,
7320                tp->hw_status->rx_consumer,
7321                tp->hw_status->rx_mini_consumer,
7322                tp->hw_status->idx[0].rx_producer,
7323                tp->hw_status->idx[0].tx_consumer);
7324
7325         /* SW statistics block */
7326         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7327                ((u32 *)tp->hw_stats)[0],
7328                ((u32 *)tp->hw_stats)[1],
7329                ((u32 *)tp->hw_stats)[2],
7330                ((u32 *)tp->hw_stats)[3]);
7331
7332         /* Mailboxes */
7333         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7334                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7335                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7336                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7337                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7338
7339         /* NIC side send descriptors. */
7340         for (i = 0; i < 6; i++) {
7341                 unsigned long txd;
7342
7343                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7344                         + (i * sizeof(struct tg3_tx_buffer_desc));
7345                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7346                        i,
7347                        readl(txd + 0x0), readl(txd + 0x4),
7348                        readl(txd + 0x8), readl(txd + 0xc));
7349         }
7350
7351         /* NIC side RX descriptors. */
7352         for (i = 0; i < 6; i++) {
7353                 unsigned long rxd;
7354
7355                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7356                         + (i * sizeof(struct tg3_rx_buffer_desc));
7357                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7358                        i,
7359                        readl(rxd + 0x0), readl(rxd + 0x4),
7360                        readl(rxd + 0x8), readl(rxd + 0xc));
7361                 rxd += (4 * sizeof(u32));
7362                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7363                        i,
7364                        readl(rxd + 0x0), readl(rxd + 0x4),
7365                        readl(rxd + 0x8), readl(rxd + 0xc));
7366         }
7367
7368         for (i = 0; i < 6; i++) {
7369                 unsigned long rxd;
7370
7371                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7372                         + (i * sizeof(struct tg3_rx_buffer_desc));
7373                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7374                        i,
7375                        readl(rxd + 0x0), readl(rxd + 0x4),
7376                        readl(rxd + 0x8), readl(rxd + 0xc));
7377                 rxd += (4 * sizeof(u32));
7378                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7379                        i,
7380                        readl(rxd + 0x0), readl(rxd + 0x4),
7381                        readl(rxd + 0x8), readl(rxd + 0xc));
7382         }
7383 }
7384 #endif
7385
7386 static struct net_device_stats *tg3_get_stats(struct net_device *);
7387 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7388
7389 static int tg3_close(struct net_device *dev)
7390 {
7391         struct tg3 *tp = netdev_priv(dev);
7392
7393         /* Calling flush_scheduled_work() may deadlock because
7394          * linkwatch_event() may be on the workqueue and it will try to get
7395          * the rtnl_lock which we are holding.
7396          */
7397         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7398                 msleep(1);
7399
7400         netif_stop_queue(dev);
7401
7402         del_timer_sync(&tp->timer);
7403
7404         tg3_full_lock(tp, 1);
7405 #if 0
7406         tg3_dump_state(tp);
7407 #endif
7408
7409         tg3_disable_ints(tp);
7410
7411         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7412         tg3_free_rings(tp);
7413         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7414
7415         tg3_full_unlock(tp);
7416
7417         free_irq(tp->pdev->irq, dev);
7418         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7419                 pci_disable_msi(tp->pdev);
7420                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7421         }
7422
7423         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7424                sizeof(tp->net_stats_prev));
7425         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7426                sizeof(tp->estats_prev));
7427
7428         tg3_free_consistent(tp);
7429
7430         tg3_set_power_state(tp, PCI_D3hot);
7431
7432         netif_carrier_off(tp->dev);
7433
7434         return 0;
7435 }
7436
7437 static inline unsigned long get_stat64(tg3_stat64_t *val)
7438 {
7439         unsigned long ret;
7440
7441 #if (BITS_PER_LONG == 32)
7442         ret = val->low;
7443 #else
7444         ret = ((u64)val->high << 32) | ((u64)val->low);
7445 #endif
7446         return ret;
7447 }
7448
7449 static unsigned long calc_crc_errors(struct tg3 *tp)
7450 {
7451         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7452
7453         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7454             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7455              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7456                 u32 val;
7457
7458                 spin_lock_bh(&tp->lock);
7459                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7460                         tg3_writephy(tp, MII_TG3_TEST1,
7461                                      val | MII_TG3_TEST1_CRC_EN);
7462                         tg3_readphy(tp, 0x14, &val);
7463                 } else
7464                         val = 0;
7465                 spin_unlock_bh(&tp->lock);
7466
7467                 tp->phy_crc_errors += val;
7468
7469                 return tp->phy_crc_errors;
7470         }
7471
7472         return get_stat64(&hw_stats->rx_fcs_errors);
7473 }
7474
7475 #define ESTAT_ADD(member) \
7476         estats->member =        old_estats->member + \
7477                                 get_stat64(&hw_stats->member)
7478
7479 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7480 {
7481         struct tg3_ethtool_stats *estats = &tp->estats;
7482         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7483         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7484
7485         if (!hw_stats)
7486                 return old_estats;
7487
7488         ESTAT_ADD(rx_octets);
7489         ESTAT_ADD(rx_fragments);
7490         ESTAT_ADD(rx_ucast_packets);
7491         ESTAT_ADD(rx_mcast_packets);
7492         ESTAT_ADD(rx_bcast_packets);
7493         ESTAT_ADD(rx_fcs_errors);
7494         ESTAT_ADD(rx_align_errors);
7495         ESTAT_ADD(rx_xon_pause_rcvd);
7496         ESTAT_ADD(rx_xoff_pause_rcvd);
7497         ESTAT_ADD(rx_mac_ctrl_rcvd);
7498         ESTAT_ADD(rx_xoff_entered);
7499         ESTAT_ADD(rx_frame_too_long_errors);
7500         ESTAT_ADD(rx_jabbers);
7501         ESTAT_ADD(rx_undersize_packets);
7502         ESTAT_ADD(rx_in_length_errors);
7503         ESTAT_ADD(rx_out_length_errors);
7504         ESTAT_ADD(rx_64_or_less_octet_packets);
7505         ESTAT_ADD(rx_65_to_127_octet_packets);
7506         ESTAT_ADD(rx_128_to_255_octet_packets);
7507         ESTAT_ADD(rx_256_to_511_octet_packets);
7508         ESTAT_ADD(rx_512_to_1023_octet_packets);
7509         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7510         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7511         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7512         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7513         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7514
7515         ESTAT_ADD(tx_octets);
7516         ESTAT_ADD(tx_collisions);
7517         ESTAT_ADD(tx_xon_sent);
7518         ESTAT_ADD(tx_xoff_sent);
7519         ESTAT_ADD(tx_flow_control);
7520         ESTAT_ADD(tx_mac_errors);
7521         ESTAT_ADD(tx_single_collisions);
7522         ESTAT_ADD(tx_mult_collisions);
7523         ESTAT_ADD(tx_deferred);
7524         ESTAT_ADD(tx_excessive_collisions);
7525         ESTAT_ADD(tx_late_collisions);
7526         ESTAT_ADD(tx_collide_2times);
7527         ESTAT_ADD(tx_collide_3times);
7528         ESTAT_ADD(tx_collide_4times);
7529         ESTAT_ADD(tx_collide_5times);
7530         ESTAT_ADD(tx_collide_6times);
7531         ESTAT_ADD(tx_collide_7times);
7532         ESTAT_ADD(tx_collide_8times);
7533         ESTAT_ADD(tx_collide_9times);
7534         ESTAT_ADD(tx_collide_10times);
7535         ESTAT_ADD(tx_collide_11times);
7536         ESTAT_ADD(tx_collide_12times);
7537         ESTAT_ADD(tx_collide_13times);
7538         ESTAT_ADD(tx_collide_14times);
7539         ESTAT_ADD(tx_collide_15times);
7540         ESTAT_ADD(tx_ucast_packets);
7541         ESTAT_ADD(tx_mcast_packets);
7542         ESTAT_ADD(tx_bcast_packets);
7543         ESTAT_ADD(tx_carrier_sense_errors);
7544         ESTAT_ADD(tx_discards);
7545         ESTAT_ADD(tx_errors);
7546
7547         ESTAT_ADD(dma_writeq_full);
7548         ESTAT_ADD(dma_write_prioq_full);
7549         ESTAT_ADD(rxbds_empty);
7550         ESTAT_ADD(rx_discards);
7551         ESTAT_ADD(rx_errors);
7552         ESTAT_ADD(rx_threshold_hit);
7553
7554         ESTAT_ADD(dma_readq_full);
7555         ESTAT_ADD(dma_read_prioq_full);
7556         ESTAT_ADD(tx_comp_queue_full);
7557
7558         ESTAT_ADD(ring_set_send_prod_index);
7559         ESTAT_ADD(ring_status_update);
7560         ESTAT_ADD(nic_irqs);
7561         ESTAT_ADD(nic_avoided_irqs);
7562         ESTAT_ADD(nic_tx_threshold_hit);
7563
7564         return estats;
7565 }
7566
7567 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7568 {
7569         struct tg3 *tp = netdev_priv(dev);
7570         struct net_device_stats *stats = &tp->net_stats;
7571         struct net_device_stats *old_stats = &tp->net_stats_prev;
7572         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7573
7574         if (!hw_stats)
7575                 return old_stats;
7576
7577         stats->rx_packets = old_stats->rx_packets +
7578                 get_stat64(&hw_stats->rx_ucast_packets) +
7579                 get_stat64(&hw_stats->rx_mcast_packets) +
7580                 get_stat64(&hw_stats->rx_bcast_packets);
7581
7582         stats->tx_packets = old_stats->tx_packets +
7583                 get_stat64(&hw_stats->tx_ucast_packets) +
7584                 get_stat64(&hw_stats->tx_mcast_packets) +
7585                 get_stat64(&hw_stats->tx_bcast_packets);
7586
7587         stats->rx_bytes = old_stats->rx_bytes +
7588                 get_stat64(&hw_stats->rx_octets);
7589         stats->tx_bytes = old_stats->tx_bytes +
7590                 get_stat64(&hw_stats->tx_octets);
7591
7592         stats->rx_errors = old_stats->rx_errors +
7593                 get_stat64(&hw_stats->rx_errors);
7594         stats->tx_errors = old_stats->tx_errors +
7595                 get_stat64(&hw_stats->tx_errors) +
7596                 get_stat64(&hw_stats->tx_mac_errors) +
7597                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7598                 get_stat64(&hw_stats->tx_discards);
7599
7600         stats->multicast = old_stats->multicast +
7601                 get_stat64(&hw_stats->rx_mcast_packets);
7602         stats->collisions = old_stats->collisions +
7603                 get_stat64(&hw_stats->tx_collisions);
7604
7605         stats->rx_length_errors = old_stats->rx_length_errors +
7606                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7607                 get_stat64(&hw_stats->rx_undersize_packets);
7608
7609         stats->rx_over_errors = old_stats->rx_over_errors +
7610                 get_stat64(&hw_stats->rxbds_empty);
7611         stats->rx_frame_errors = old_stats->rx_frame_errors +
7612                 get_stat64(&hw_stats->rx_align_errors);
7613         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7614                 get_stat64(&hw_stats->tx_discards);
7615         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7616                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7617
7618         stats->rx_crc_errors = old_stats->rx_crc_errors +
7619                 calc_crc_errors(tp);
7620
7621         stats->rx_missed_errors = old_stats->rx_missed_errors +
7622                 get_stat64(&hw_stats->rx_discards);
7623
7624         return stats;
7625 }
7626
7627 static inline u32 calc_crc(unsigned char *buf, int len)
7628 {
7629         u32 reg;
7630         u32 tmp;
7631         int j, k;
7632
7633         reg = 0xffffffff;
7634
7635         for (j = 0; j < len; j++) {
7636                 reg ^= buf[j];
7637
7638                 for (k = 0; k < 8; k++) {
7639                         tmp = reg & 0x01;
7640
7641                         reg >>= 1;
7642
7643                         if (tmp) {
7644                                 reg ^= 0xedb88320;
7645                         }
7646                 }
7647         }
7648
7649         return ~reg;
7650 }
7651
7652 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7653 {
7654         /* accept or reject all multicast frames */
7655         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7656         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7657         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7658         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7659 }
7660
7661 static void __tg3_set_rx_mode(struct net_device *dev)
7662 {
7663         struct tg3 *tp = netdev_priv(dev);
7664         u32 rx_mode;
7665
7666         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7667                                   RX_MODE_KEEP_VLAN_TAG);
7668
7669         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7670          * flag clear.
7671          */
7672 #if TG3_VLAN_TAG_USED
7673         if (!tp->vlgrp &&
7674             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7675                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7676 #else
7677         /* By definition, VLAN is disabled always in this
7678          * case.
7679          */
7680         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7681                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7682 #endif
7683
7684         if (dev->flags & IFF_PROMISC) {
7685                 /* Promiscuous mode. */
7686                 rx_mode |= RX_MODE_PROMISC;
7687         } else if (dev->flags & IFF_ALLMULTI) {
7688                 /* Accept all multicast. */
7689                 tg3_set_multi (tp, 1);
7690         } else if (dev->mc_count < 1) {
7691                 /* Reject all multicast. */
7692                 tg3_set_multi (tp, 0);
7693         } else {
7694                 /* Accept one or more multicast(s). */
7695                 struct dev_mc_list *mclist;
7696                 unsigned int i;
7697                 u32 mc_filter[4] = { 0, };
7698                 u32 regidx;
7699                 u32 bit;
7700                 u32 crc;
7701
7702                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7703                      i++, mclist = mclist->next) {
7704
7705                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7706                         bit = ~crc & 0x7f;
7707                         regidx = (bit & 0x60) >> 5;
7708                         bit &= 0x1f;
7709                         mc_filter[regidx] |= (1 << bit);
7710                 }
7711
7712                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7713                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7714                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7715                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7716         }
7717
7718         if (rx_mode != tp->rx_mode) {
7719                 tp->rx_mode = rx_mode;
7720                 tw32_f(MAC_RX_MODE, rx_mode);
7721                 udelay(10);
7722         }
7723 }
7724
7725 static void tg3_set_rx_mode(struct net_device *dev)
7726 {
7727         struct tg3 *tp = netdev_priv(dev);
7728
7729         if (!netif_running(dev))
7730                 return;
7731
7732         tg3_full_lock(tp, 0);
7733         __tg3_set_rx_mode(dev);
7734         tg3_full_unlock(tp);
7735 }
7736
7737 #define TG3_REGDUMP_LEN         (32 * 1024)
7738
7739 static int tg3_get_regs_len(struct net_device *dev)
7740 {
7741         return TG3_REGDUMP_LEN;
7742 }
7743
7744 static void tg3_get_regs(struct net_device *dev,
7745                 struct ethtool_regs *regs, void *_p)
7746 {
7747         u32 *p = _p;
7748         struct tg3 *tp = netdev_priv(dev);
7749         u8 *orig_p = _p;
7750         int i;
7751
7752         regs->version = 0;
7753
7754         memset(p, 0, TG3_REGDUMP_LEN);
7755
7756         if (tp->link_config.phy_is_low_power)
7757                 return;
7758
7759         tg3_full_lock(tp, 0);
7760
7761 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7762 #define GET_REG32_LOOP(base,len)                \
7763 do {    p = (u32 *)(orig_p + (base));           \
7764         for (i = 0; i < len; i += 4)            \
7765                 __GET_REG32((base) + i);        \
7766 } while (0)
7767 #define GET_REG32_1(reg)                        \
7768 do {    p = (u32 *)(orig_p + (reg));            \
7769         __GET_REG32((reg));                     \
7770 } while (0)
7771
7772         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7773         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7774         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7775         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7776         GET_REG32_1(SNDDATAC_MODE);
7777         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7778         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7779         GET_REG32_1(SNDBDC_MODE);
7780         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7781         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7782         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7783         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7784         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7785         GET_REG32_1(RCVDCC_MODE);
7786         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7787         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7788         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7789         GET_REG32_1(MBFREE_MODE);
7790         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7791         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7792         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7793         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7794         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7795         GET_REG32_1(RX_CPU_MODE);
7796         GET_REG32_1(RX_CPU_STATE);
7797         GET_REG32_1(RX_CPU_PGMCTR);
7798         GET_REG32_1(RX_CPU_HWBKPT);
7799         GET_REG32_1(TX_CPU_MODE);
7800         GET_REG32_1(TX_CPU_STATE);
7801         GET_REG32_1(TX_CPU_PGMCTR);
7802         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7803         GET_REG32_LOOP(FTQ_RESET, 0x120);
7804         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7805         GET_REG32_1(DMAC_MODE);
7806         GET_REG32_LOOP(GRC_MODE, 0x4c);
7807         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7808                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7809
7810 #undef __GET_REG32
7811 #undef GET_REG32_LOOP
7812 #undef GET_REG32_1
7813
7814         tg3_full_unlock(tp);
7815 }
7816
7817 static int tg3_get_eeprom_len(struct net_device *dev)
7818 {
7819         struct tg3 *tp = netdev_priv(dev);
7820
7821         return tp->nvram_size;
7822 }
7823
7824 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7825 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7826
7827 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7828 {
7829         struct tg3 *tp = netdev_priv(dev);
7830         int ret;
7831         u8  *pd;
7832         u32 i, offset, len, val, b_offset, b_count;
7833
7834         if (tp->link_config.phy_is_low_power)
7835                 return -EAGAIN;
7836
7837         offset = eeprom->offset;
7838         len = eeprom->len;
7839         eeprom->len = 0;
7840
7841         eeprom->magic = TG3_EEPROM_MAGIC;
7842
7843         if (offset & 3) {
7844                 /* adjustments to start on required 4 byte boundary */
7845                 b_offset = offset & 3;
7846                 b_count = 4 - b_offset;
7847                 if (b_count > len) {
7848                         /* i.e. offset=1 len=2 */
7849                         b_count = len;
7850                 }
7851                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7852                 if (ret)
7853                         return ret;
7854                 val = cpu_to_le32(val);
7855                 memcpy(data, ((char*)&val) + b_offset, b_count);
7856                 len -= b_count;
7857                 offset += b_count;
7858                 eeprom->len += b_count;
7859         }
7860
7861         /* read bytes upto the last 4 byte boundary */
7862         pd = &data[eeprom->len];
7863         for (i = 0; i < (len - (len & 3)); i += 4) {
7864                 ret = tg3_nvram_read(tp, offset + i, &val);
7865                 if (ret) {
7866                         eeprom->len += i;
7867                         return ret;
7868                 }
7869                 val = cpu_to_le32(val);
7870                 memcpy(pd + i, &val, 4);
7871         }
7872         eeprom->len += i;
7873
7874         if (len & 3) {
7875                 /* read last bytes not ending on 4 byte boundary */
7876                 pd = &data[eeprom->len];
7877                 b_count = len & 3;
7878                 b_offset = offset + len - b_count;
7879                 ret = tg3_nvram_read(tp, b_offset, &val);
7880                 if (ret)
7881                         return ret;
7882                 val = cpu_to_le32(val);
7883                 memcpy(pd, ((char*)&val), b_count);
7884                 eeprom->len += b_count;
7885         }
7886         return 0;
7887 }
7888
7889 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7890
7891 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7892 {
7893         struct tg3 *tp = netdev_priv(dev);
7894         int ret;
7895         u32 offset, len, b_offset, odd_len, start, end;
7896         u8 *buf;
7897
7898         if (tp->link_config.phy_is_low_power)
7899                 return -EAGAIN;
7900
7901         if (eeprom->magic != TG3_EEPROM_MAGIC)
7902                 return -EINVAL;
7903
7904         offset = eeprom->offset;
7905         len = eeprom->len;
7906
7907         if ((b_offset = (offset & 3))) {
7908                 /* adjustments to start on required 4 byte boundary */
7909                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7910                 if (ret)
7911                         return ret;
7912                 start = cpu_to_le32(start);
7913                 len += b_offset;
7914                 offset &= ~3;
7915                 if (len < 4)
7916                         len = 4;
7917         }
7918
7919         odd_len = 0;
7920         if (len & 3) {
7921                 /* adjustments to end on required 4 byte boundary */
7922                 odd_len = 1;
7923                 len = (len + 3) & ~3;
7924                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7925                 if (ret)
7926                         return ret;
7927                 end = cpu_to_le32(end);
7928         }
7929
7930         buf = data;
7931         if (b_offset || odd_len) {
7932                 buf = kmalloc(len, GFP_KERNEL);
7933                 if (buf == 0)
7934                         return -ENOMEM;
7935                 if (b_offset)
7936                         memcpy(buf, &start, 4);
7937                 if (odd_len)
7938                         memcpy(buf+len-4, &end, 4);
7939                 memcpy(buf + b_offset, data, eeprom->len);
7940         }
7941
7942         ret = tg3_nvram_write_block(tp, offset, len, buf);
7943
7944         if (buf != data)
7945                 kfree(buf);
7946
7947         return ret;
7948 }
7949
7950 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7951 {
7952         struct tg3 *tp = netdev_priv(dev);
7953
7954         cmd->supported = (SUPPORTED_Autoneg);
7955
7956         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7957                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7958                                    SUPPORTED_1000baseT_Full);
7959
7960         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7961                 cmd->supported |= (SUPPORTED_100baseT_Half |
7962                                   SUPPORTED_100baseT_Full |
7963                                   SUPPORTED_10baseT_Half |
7964                                   SUPPORTED_10baseT_Full |
7965                                   SUPPORTED_MII);
7966                 cmd->port = PORT_TP;
7967         } else {
7968                 cmd->supported |= SUPPORTED_FIBRE;
7969                 cmd->port = PORT_FIBRE;
7970         }
7971
7972         cmd->advertising = tp->link_config.advertising;
7973         if (netif_running(dev)) {
7974                 cmd->speed = tp->link_config.active_speed;
7975                 cmd->duplex = tp->link_config.active_duplex;
7976         }
7977         cmd->phy_address = PHY_ADDR;
7978         cmd->transceiver = 0;
7979         cmd->autoneg = tp->link_config.autoneg;
7980         cmd->maxtxpkt = 0;
7981         cmd->maxrxpkt = 0;
7982         return 0;
7983 }
7984
7985 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7986 {
7987         struct tg3 *tp = netdev_priv(dev);
7988
7989         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7990                 /* These are the only valid advertisement bits allowed.  */
7991                 if (cmd->autoneg == AUTONEG_ENABLE &&
7992                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7993                                           ADVERTISED_1000baseT_Full |
7994                                           ADVERTISED_Autoneg |
7995                                           ADVERTISED_FIBRE)))
7996                         return -EINVAL;
7997                 /* Fiber can only do SPEED_1000.  */
7998                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7999                          (cmd->speed != SPEED_1000))
8000                         return -EINVAL;
8001         /* Copper cannot force SPEED_1000.  */
8002         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8003                    (cmd->speed == SPEED_1000))
8004                 return -EINVAL;
8005         else if ((cmd->speed == SPEED_1000) &&
8006                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8007                 return -EINVAL;
8008
8009         tg3_full_lock(tp, 0);
8010
8011         tp->link_config.autoneg = cmd->autoneg;
8012         if (cmd->autoneg == AUTONEG_ENABLE) {
8013                 tp->link_config.advertising = cmd->advertising;
8014                 tp->link_config.speed = SPEED_INVALID;
8015                 tp->link_config.duplex = DUPLEX_INVALID;
8016         } else {
8017                 tp->link_config.advertising = 0;
8018                 tp->link_config.speed = cmd->speed;
8019                 tp->link_config.duplex = cmd->duplex;
8020         }
8021
8022         tp->link_config.orig_speed = tp->link_config.speed;
8023         tp->link_config.orig_duplex = tp->link_config.duplex;
8024         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8025
8026         if (netif_running(dev))
8027                 tg3_setup_phy(tp, 1);
8028
8029         tg3_full_unlock(tp);
8030
8031         return 0;
8032 }
8033
8034 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8035 {
8036         struct tg3 *tp = netdev_priv(dev);
8037
8038         strcpy(info->driver, DRV_MODULE_NAME);
8039         strcpy(info->version, DRV_MODULE_VERSION);
8040         strcpy(info->fw_version, tp->fw_ver);
8041         strcpy(info->bus_info, pci_name(tp->pdev));
8042 }
8043
8044 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8045 {
8046         struct tg3 *tp = netdev_priv(dev);
8047
8048         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8049                 wol->supported = WAKE_MAGIC;
8050         else
8051                 wol->supported = 0;
8052         wol->wolopts = 0;
8053         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8054                 wol->wolopts = WAKE_MAGIC;
8055         memset(&wol->sopass, 0, sizeof(wol->sopass));
8056 }
8057
8058 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8059 {
8060         struct tg3 *tp = netdev_priv(dev);
8061
8062         if (wol->wolopts & ~WAKE_MAGIC)
8063                 return -EINVAL;
8064         if ((wol->wolopts & WAKE_MAGIC) &&
8065             !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8066                 return -EINVAL;
8067
8068         spin_lock_bh(&tp->lock);
8069         if (wol->wolopts & WAKE_MAGIC)
8070                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8071         else
8072                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8073         spin_unlock_bh(&tp->lock);
8074
8075         return 0;
8076 }
8077
8078 static u32 tg3_get_msglevel(struct net_device *dev)
8079 {
8080         struct tg3 *tp = netdev_priv(dev);
8081         return tp->msg_enable;
8082 }
8083
8084 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8085 {
8086         struct tg3 *tp = netdev_priv(dev);
8087         tp->msg_enable = value;
8088 }
8089
8090 static int tg3_set_tso(struct net_device *dev, u32 value)
8091 {
8092         struct tg3 *tp = netdev_priv(dev);
8093
8094         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8095                 if (value)
8096                         return -EINVAL;
8097                 return 0;
8098         }
8099         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8100             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8101                 if (value)
8102                         dev->features |= NETIF_F_TSO6;
8103                 else
8104                         dev->features &= ~NETIF_F_TSO6;
8105         }
8106         return ethtool_op_set_tso(dev, value);
8107 }
8108
8109 static int tg3_nway_reset(struct net_device *dev)
8110 {
8111         struct tg3 *tp = netdev_priv(dev);
8112         u32 bmcr;
8113         int r;
8114
8115         if (!netif_running(dev))
8116                 return -EAGAIN;
8117
8118         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8119                 return -EINVAL;
8120
8121         spin_lock_bh(&tp->lock);
8122         r = -EINVAL;
8123         tg3_readphy(tp, MII_BMCR, &bmcr);
8124         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8125             ((bmcr & BMCR_ANENABLE) ||
8126              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8127                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8128                                            BMCR_ANENABLE);
8129                 r = 0;
8130         }
8131         spin_unlock_bh(&tp->lock);
8132
8133         return r;
8134 }
8135
8136 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8137 {
8138         struct tg3 *tp = netdev_priv(dev);
8139
8140         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8141         ering->rx_mini_max_pending = 0;
8142         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8143                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8144         else
8145                 ering->rx_jumbo_max_pending = 0;
8146
8147         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8148
8149         ering->rx_pending = tp->rx_pending;
8150         ering->rx_mini_pending = 0;
8151         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8152                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8153         else
8154                 ering->rx_jumbo_pending = 0;
8155
8156         ering->tx_pending = tp->tx_pending;
8157 }
8158
8159 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8160 {
8161         struct tg3 *tp = netdev_priv(dev);
8162         int irq_sync = 0, err = 0;
8163
8164         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8165             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8166             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8167             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8168             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8169              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8170                 return -EINVAL;
8171
8172         if (netif_running(dev)) {
8173                 tg3_netif_stop(tp);
8174                 irq_sync = 1;
8175         }
8176
8177         tg3_full_lock(tp, irq_sync);
8178
8179         tp->rx_pending = ering->rx_pending;
8180
8181         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8182             tp->rx_pending > 63)
8183                 tp->rx_pending = 63;
8184         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8185         tp->tx_pending = ering->tx_pending;
8186
8187         if (netif_running(dev)) {
8188                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8189                 err = tg3_restart_hw(tp, 1);
8190                 if (!err)
8191                         tg3_netif_start(tp);
8192         }
8193
8194         tg3_full_unlock(tp);
8195
8196         return err;
8197 }
8198
8199 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8200 {
8201         struct tg3 *tp = netdev_priv(dev);
8202
8203         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8204         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8205         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8206 }
8207
8208 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8209 {
8210         struct tg3 *tp = netdev_priv(dev);
8211         int irq_sync = 0, err = 0;
8212
8213         if (netif_running(dev)) {
8214                 tg3_netif_stop(tp);
8215                 irq_sync = 1;
8216         }
8217
8218         tg3_full_lock(tp, irq_sync);
8219
8220         if (epause->autoneg)
8221                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8222         else
8223                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8224         if (epause->rx_pause)
8225                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8226         else
8227                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8228         if (epause->tx_pause)
8229                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8230         else
8231                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8232
8233         if (netif_running(dev)) {
8234                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8235                 err = tg3_restart_hw(tp, 1);
8236                 if (!err)
8237                         tg3_netif_start(tp);
8238         }
8239
8240         tg3_full_unlock(tp);
8241
8242         return err;
8243 }
8244
8245 static u32 tg3_get_rx_csum(struct net_device *dev)
8246 {
8247         struct tg3 *tp = netdev_priv(dev);
8248         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8249 }
8250
8251 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8252 {
8253         struct tg3 *tp = netdev_priv(dev);
8254
8255         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8256                 if (data != 0)
8257                         return -EINVAL;
8258                 return 0;
8259         }
8260
8261         spin_lock_bh(&tp->lock);
8262         if (data)
8263                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8264         else
8265                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8266         spin_unlock_bh(&tp->lock);
8267
8268         return 0;
8269 }
8270
8271 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8272 {
8273         struct tg3 *tp = netdev_priv(dev);
8274
8275         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8276                 if (data != 0)
8277                         return -EINVAL;
8278                 return 0;
8279         }
8280
8281         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8282             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8283                 ethtool_op_set_tx_hw_csum(dev, data);
8284         else
8285                 ethtool_op_set_tx_csum(dev, data);
8286
8287         return 0;
8288 }
8289
8290 static int tg3_get_stats_count (struct net_device *dev)
8291 {
8292         return TG3_NUM_STATS;
8293 }
8294
8295 static int tg3_get_test_count (struct net_device *dev)
8296 {
8297         return TG3_NUM_TEST;
8298 }
8299
8300 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8301 {
8302         switch (stringset) {
8303         case ETH_SS_STATS:
8304                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8305                 break;
8306         case ETH_SS_TEST:
8307                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8308                 break;
8309         default:
8310                 WARN_ON(1);     /* we need a WARN() */
8311                 break;
8312         }
8313 }
8314
8315 static int tg3_phys_id(struct net_device *dev, u32 data)
8316 {
8317         struct tg3 *tp = netdev_priv(dev);
8318         int i;
8319
8320         if (!netif_running(tp->dev))
8321                 return -EAGAIN;
8322
8323         if (data == 0)
8324                 data = 2;
8325
8326         for (i = 0; i < (data * 2); i++) {
8327                 if ((i % 2) == 0)
8328                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8329                                            LED_CTRL_1000MBPS_ON |
8330                                            LED_CTRL_100MBPS_ON |
8331                                            LED_CTRL_10MBPS_ON |
8332                                            LED_CTRL_TRAFFIC_OVERRIDE |
8333                                            LED_CTRL_TRAFFIC_BLINK |
8334                                            LED_CTRL_TRAFFIC_LED);
8335
8336                 else
8337                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8338                                            LED_CTRL_TRAFFIC_OVERRIDE);
8339
8340                 if (msleep_interruptible(500))
8341                         break;
8342         }
8343         tw32(MAC_LED_CTRL, tp->led_ctrl);
8344         return 0;
8345 }
8346
8347 static void tg3_get_ethtool_stats (struct net_device *dev,
8348                                    struct ethtool_stats *estats, u64 *tmp_stats)
8349 {
8350         struct tg3 *tp = netdev_priv(dev);
8351         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8352 }
8353
8354 #define NVRAM_TEST_SIZE 0x100
8355 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8356 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8357 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8358
8359 static int tg3_test_nvram(struct tg3 *tp)
8360 {
8361         u32 *buf, csum, magic;
8362         int i, j, err = 0, size;
8363
8364         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8365                 return -EIO;
8366
8367         if (magic == TG3_EEPROM_MAGIC)
8368                 size = NVRAM_TEST_SIZE;
8369         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8370                 if ((magic & 0xe00000) == 0x200000)
8371                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8372                 else
8373                         return 0;
8374         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8375                 size = NVRAM_SELFBOOT_HW_SIZE;
8376         else
8377                 return -EIO;
8378
8379         buf = kmalloc(size, GFP_KERNEL);
8380         if (buf == NULL)
8381                 return -ENOMEM;
8382
8383         err = -EIO;
8384         for (i = 0, j = 0; i < size; i += 4, j++) {
8385                 u32 val;
8386
8387                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8388                         break;
8389                 buf[j] = cpu_to_le32(val);
8390         }
8391         if (i < size)
8392                 goto out;
8393
8394         /* Selfboot format */
8395         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8396             TG3_EEPROM_MAGIC_FW) {
8397                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8398
8399                 for (i = 0; i < size; i++)
8400                         csum8 += buf8[i];
8401
8402                 if (csum8 == 0) {
8403                         err = 0;
8404                         goto out;
8405                 }
8406
8407                 err = -EIO;
8408                 goto out;
8409         }
8410
8411         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8412             TG3_EEPROM_MAGIC_HW) {
8413                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8414                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8415                 u8 *buf8 = (u8 *) buf;
8416                 int j, k;
8417
8418                 /* Separate the parity bits and the data bytes.  */
8419                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8420                         if ((i == 0) || (i == 8)) {
8421                                 int l;
8422                                 u8 msk;
8423
8424                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8425                                         parity[k++] = buf8[i] & msk;
8426                                 i++;
8427                         }
8428                         else if (i == 16) {
8429                                 int l;
8430                                 u8 msk;
8431
8432                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8433                                         parity[k++] = buf8[i] & msk;
8434                                 i++;
8435
8436                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8437                                         parity[k++] = buf8[i] & msk;
8438                                 i++;
8439                         }
8440                         data[j++] = buf8[i];
8441                 }
8442
8443                 err = -EIO;
8444                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8445                         u8 hw8 = hweight8(data[i]);
8446
8447                         if ((hw8 & 0x1) && parity[i])
8448                                 goto out;
8449                         else if (!(hw8 & 0x1) && !parity[i])
8450                                 goto out;
8451                 }
8452                 err = 0;
8453                 goto out;
8454         }
8455
8456         /* Bootstrap checksum at offset 0x10 */
8457         csum = calc_crc((unsigned char *) buf, 0x10);
8458         if(csum != cpu_to_le32(buf[0x10/4]))
8459                 goto out;
8460
8461         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8462         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8463         if (csum != cpu_to_le32(buf[0xfc/4]))
8464                  goto out;
8465
8466         err = 0;
8467
8468 out:
8469         kfree(buf);
8470         return err;
8471 }
8472
8473 #define TG3_SERDES_TIMEOUT_SEC  2
8474 #define TG3_COPPER_TIMEOUT_SEC  6
8475
8476 static int tg3_test_link(struct tg3 *tp)
8477 {
8478         int i, max;
8479
8480         if (!netif_running(tp->dev))
8481                 return -ENODEV;
8482
8483         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8484                 max = TG3_SERDES_TIMEOUT_SEC;
8485         else
8486                 max = TG3_COPPER_TIMEOUT_SEC;
8487
8488         for (i = 0; i < max; i++) {
8489                 if (netif_carrier_ok(tp->dev))
8490                         return 0;
8491
8492                 if (msleep_interruptible(1000))
8493                         break;
8494         }
8495
8496         return -EIO;
8497 }
8498
8499 /* Only test the commonly used registers */
8500 static int tg3_test_registers(struct tg3 *tp)
8501 {
8502         int i, is_5705, is_5750;
8503         u32 offset, read_mask, write_mask, val, save_val, read_val;
8504         static struct {
8505                 u16 offset;
8506                 u16 flags;
8507 #define TG3_FL_5705     0x1
8508 #define TG3_FL_NOT_5705 0x2
8509 #define TG3_FL_NOT_5788 0x4
8510 #define TG3_FL_NOT_5750 0x8
8511                 u32 read_mask;
8512                 u32 write_mask;
8513         } reg_tbl[] = {
8514                 /* MAC Control Registers */
8515                 { MAC_MODE, TG3_FL_NOT_5705,
8516                         0x00000000, 0x00ef6f8c },
8517                 { MAC_MODE, TG3_FL_5705,
8518                         0x00000000, 0x01ef6b8c },
8519                 { MAC_STATUS, TG3_FL_NOT_5705,
8520                         0x03800107, 0x00000000 },
8521                 { MAC_STATUS, TG3_FL_5705,
8522                         0x03800100, 0x00000000 },
8523                 { MAC_ADDR_0_HIGH, 0x0000,
8524                         0x00000000, 0x0000ffff },
8525                 { MAC_ADDR_0_LOW, 0x0000,
8526                         0x00000000, 0xffffffff },
8527                 { MAC_RX_MTU_SIZE, 0x0000,
8528                         0x00000000, 0x0000ffff },
8529                 { MAC_TX_MODE, 0x0000,
8530                         0x00000000, 0x00000070 },
8531                 { MAC_TX_LENGTHS, 0x0000,
8532                         0x00000000, 0x00003fff },
8533                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8534                         0x00000000, 0x000007fc },
8535                 { MAC_RX_MODE, TG3_FL_5705,
8536                         0x00000000, 0x000007dc },
8537                 { MAC_HASH_REG_0, 0x0000,
8538                         0x00000000, 0xffffffff },
8539                 { MAC_HASH_REG_1, 0x0000,
8540                         0x00000000, 0xffffffff },
8541                 { MAC_HASH_REG_2, 0x0000,
8542                         0x00000000, 0xffffffff },
8543                 { MAC_HASH_REG_3, 0x0000,
8544                         0x00000000, 0xffffffff },
8545
8546                 /* Receive Data and Receive BD Initiator Control Registers. */
8547                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8548                         0x00000000, 0xffffffff },
8549                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8550                         0x00000000, 0xffffffff },
8551                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8552                         0x00000000, 0x00000003 },
8553                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8554                         0x00000000, 0xffffffff },
8555                 { RCVDBDI_STD_BD+0, 0x0000,
8556                         0x00000000, 0xffffffff },
8557                 { RCVDBDI_STD_BD+4, 0x0000,
8558                         0x00000000, 0xffffffff },
8559                 { RCVDBDI_STD_BD+8, 0x0000,
8560                         0x00000000, 0xffff0002 },
8561                 { RCVDBDI_STD_BD+0xc, 0x0000,
8562                         0x00000000, 0xffffffff },
8563
8564                 /* Receive BD Initiator Control Registers. */
8565                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8566                         0x00000000, 0xffffffff },
8567                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8568                         0x00000000, 0x000003ff },
8569                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8570                         0x00000000, 0xffffffff },
8571
8572                 /* Host Coalescing Control Registers. */
8573                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8574                         0x00000000, 0x00000004 },
8575                 { HOSTCC_MODE, TG3_FL_5705,
8576                         0x00000000, 0x000000f6 },
8577                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8578                         0x00000000, 0xffffffff },
8579                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8580                         0x00000000, 0x000003ff },
8581                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8582                         0x00000000, 0xffffffff },
8583                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8584                         0x00000000, 0x000003ff },
8585                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8586                         0x00000000, 0xffffffff },
8587                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8588                         0x00000000, 0x000000ff },
8589                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8590                         0x00000000, 0xffffffff },
8591                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8592                         0x00000000, 0x000000ff },
8593                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8594                         0x00000000, 0xffffffff },
8595                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8596                         0x00000000, 0xffffffff },
8597                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8598                         0x00000000, 0xffffffff },
8599                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8600                         0x00000000, 0x000000ff },
8601                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8602                         0x00000000, 0xffffffff },
8603                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8604                         0x00000000, 0x000000ff },
8605                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8606                         0x00000000, 0xffffffff },
8607                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8608                         0x00000000, 0xffffffff },
8609                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8610                         0x00000000, 0xffffffff },
8611                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8612                         0x00000000, 0xffffffff },
8613                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8614                         0x00000000, 0xffffffff },
8615                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8616                         0xffffffff, 0x00000000 },
8617                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8618                         0xffffffff, 0x00000000 },
8619
8620                 /* Buffer Manager Control Registers. */
8621                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8622                         0x00000000, 0x007fff80 },
8623                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8624                         0x00000000, 0x007fffff },
8625                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8626                         0x00000000, 0x0000003f },
8627                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8628                         0x00000000, 0x000001ff },
8629                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8630                         0x00000000, 0x000001ff },
8631                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8632                         0xffffffff, 0x00000000 },
8633                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8634                         0xffffffff, 0x00000000 },
8635
8636                 /* Mailbox Registers */
8637                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8638                         0x00000000, 0x000001ff },
8639                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8640                         0x00000000, 0x000001ff },
8641                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8642                         0x00000000, 0x000007ff },
8643                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8644                         0x00000000, 0x000001ff },
8645
8646                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8647         };
8648
8649         is_5705 = is_5750 = 0;
8650         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8651                 is_5705 = 1;
8652                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8653                         is_5750 = 1;
8654         }
8655
8656         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8657                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8658                         continue;
8659
8660                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8661                         continue;
8662
8663                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8664                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8665                         continue;
8666
8667                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8668                         continue;
8669
8670                 offset = (u32) reg_tbl[i].offset;
8671                 read_mask = reg_tbl[i].read_mask;
8672                 write_mask = reg_tbl[i].write_mask;
8673
8674                 /* Save the original register content */
8675                 save_val = tr32(offset);
8676
8677                 /* Determine the read-only value. */
8678                 read_val = save_val & read_mask;
8679
8680                 /* Write zero to the register, then make sure the read-only bits
8681                  * are not changed and the read/write bits are all zeros.
8682                  */
8683                 tw32(offset, 0);
8684
8685                 val = tr32(offset);
8686
8687                 /* Test the read-only and read/write bits. */
8688                 if (((val & read_mask) != read_val) || (val & write_mask))
8689                         goto out;
8690
8691                 /* Write ones to all the bits defined by RdMask and WrMask, then
8692                  * make sure the read-only bits are not changed and the
8693                  * read/write bits are all ones.
8694                  */
8695                 tw32(offset, read_mask | write_mask);
8696
8697                 val = tr32(offset);
8698
8699                 /* Test the read-only bits. */
8700                 if ((val & read_mask) != read_val)
8701                         goto out;
8702
8703                 /* Test the read/write bits. */
8704                 if ((val & write_mask) != write_mask)
8705                         goto out;
8706
8707                 tw32(offset, save_val);
8708         }
8709
8710         return 0;
8711
8712 out:
8713         if (netif_msg_hw(tp))
8714                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8715                        offset);
8716         tw32(offset, save_val);
8717         return -EIO;
8718 }
8719
8720 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8721 {
8722         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8723         int i;
8724         u32 j;
8725
8726         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8727                 for (j = 0; j < len; j += 4) {
8728                         u32 val;
8729
8730                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8731                         tg3_read_mem(tp, offset + j, &val);
8732                         if (val != test_pattern[i])
8733                                 return -EIO;
8734                 }
8735         }
8736         return 0;
8737 }
8738
8739 static int tg3_test_memory(struct tg3 *tp)
8740 {
8741         static struct mem_entry {
8742                 u32 offset;
8743                 u32 len;
8744         } mem_tbl_570x[] = {
8745                 { 0x00000000, 0x00b50},
8746                 { 0x00002000, 0x1c000},
8747                 { 0xffffffff, 0x00000}
8748         }, mem_tbl_5705[] = {
8749                 { 0x00000100, 0x0000c},
8750                 { 0x00000200, 0x00008},
8751                 { 0x00004000, 0x00800},
8752                 { 0x00006000, 0x01000},
8753                 { 0x00008000, 0x02000},
8754                 { 0x00010000, 0x0e000},
8755                 { 0xffffffff, 0x00000}
8756         }, mem_tbl_5755[] = {
8757                 { 0x00000200, 0x00008},
8758                 { 0x00004000, 0x00800},
8759                 { 0x00006000, 0x00800},
8760                 { 0x00008000, 0x02000},
8761                 { 0x00010000, 0x0c000},
8762                 { 0xffffffff, 0x00000}
8763         }, mem_tbl_5906[] = {
8764                 { 0x00000200, 0x00008},
8765                 { 0x00004000, 0x00400},
8766                 { 0x00006000, 0x00400},
8767                 { 0x00008000, 0x01000},
8768                 { 0x00010000, 0x01000},
8769                 { 0xffffffff, 0x00000}
8770         };
8771         struct mem_entry *mem_tbl;
8772         int err = 0;
8773         int i;
8774
8775         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8776                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8777                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8778                         mem_tbl = mem_tbl_5755;
8779                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8780                         mem_tbl = mem_tbl_5906;
8781                 else
8782                         mem_tbl = mem_tbl_5705;
8783         } else
8784                 mem_tbl = mem_tbl_570x;
8785
8786         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8787                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8788                     mem_tbl[i].len)) != 0)
8789                         break;
8790         }
8791
8792         return err;
8793 }
8794
8795 #define TG3_MAC_LOOPBACK        0
8796 #define TG3_PHY_LOOPBACK        1
8797
8798 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8799 {
8800         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8801         u32 desc_idx;
8802         struct sk_buff *skb, *rx_skb;
8803         u8 *tx_data;
8804         dma_addr_t map;
8805         int num_pkts, tx_len, rx_len, i, err;
8806         struct tg3_rx_buffer_desc *desc;
8807
8808         if (loopback_mode == TG3_MAC_LOOPBACK) {
8809                 /* HW errata - mac loopback fails in some cases on 5780.
8810                  * Normal traffic and PHY loopback are not affected by
8811                  * errata.
8812                  */
8813                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8814                         return 0;
8815
8816                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8817                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8818                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8819                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8820                 else
8821                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8822                 tw32(MAC_MODE, mac_mode);
8823         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8824                 u32 val;
8825
8826                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8827                         u32 phytest;
8828
8829                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8830                                 u32 phy;
8831
8832                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8833                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8834                                 if (!tg3_readphy(tp, 0x1b, &phy))
8835                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8836                                 if (!tg3_readphy(tp, 0x10, &phy))
8837                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
8838                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8839                         }
8840                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8841                 } else
8842                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8843
8844                 tg3_writephy(tp, MII_BMCR, val);
8845                 udelay(40);
8846
8847                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8848                            MAC_MODE_LINK_POLARITY;
8849                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8850                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8851                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8852                 } else
8853                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8854
8855                 /* reset to prevent losing 1st rx packet intermittently */
8856                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8857                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8858                         udelay(10);
8859                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8860                 }
8861                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8862                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8863                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8864                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8865                 }
8866                 tw32(MAC_MODE, mac_mode);
8867         }
8868         else
8869                 return -EINVAL;
8870
8871         err = -EIO;
8872
8873         tx_len = 1514;
8874         skb = netdev_alloc_skb(tp->dev, tx_len);
8875         if (!skb)
8876                 return -ENOMEM;
8877
8878         tx_data = skb_put(skb, tx_len);
8879         memcpy(tx_data, tp->dev->dev_addr, 6);
8880         memset(tx_data + 6, 0x0, 8);
8881
8882         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8883
8884         for (i = 14; i < tx_len; i++)
8885                 tx_data[i] = (u8) (i & 0xff);
8886
8887         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8888
8889         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8890              HOSTCC_MODE_NOW);
8891
8892         udelay(10);
8893
8894         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8895
8896         num_pkts = 0;
8897
8898         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8899
8900         tp->tx_prod++;
8901         num_pkts++;
8902
8903         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8904                      tp->tx_prod);
8905         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8906
8907         udelay(10);
8908
8909         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8910         for (i = 0; i < 25; i++) {
8911                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8912                        HOSTCC_MODE_NOW);
8913
8914                 udelay(10);
8915
8916                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8917                 rx_idx = tp->hw_status->idx[0].rx_producer;
8918                 if ((tx_idx == tp->tx_prod) &&
8919                     (rx_idx == (rx_start_idx + num_pkts)))
8920                         break;
8921         }
8922
8923         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8924         dev_kfree_skb(skb);
8925
8926         if (tx_idx != tp->tx_prod)
8927                 goto out;
8928
8929         if (rx_idx != rx_start_idx + num_pkts)
8930                 goto out;
8931
8932         desc = &tp->rx_rcb[rx_start_idx];
8933         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8934         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8935         if (opaque_key != RXD_OPAQUE_RING_STD)
8936                 goto out;
8937
8938         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8939             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8940                 goto out;
8941
8942         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8943         if (rx_len != tx_len)
8944                 goto out;
8945
8946         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8947
8948         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8949         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8950
8951         for (i = 14; i < tx_len; i++) {
8952                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8953                         goto out;
8954         }
8955         err = 0;
8956
8957         /* tg3_free_rings will unmap and free the rx_skb */
8958 out:
8959         return err;
8960 }
8961
8962 #define TG3_MAC_LOOPBACK_FAILED         1
8963 #define TG3_PHY_LOOPBACK_FAILED         2
8964 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8965                                          TG3_PHY_LOOPBACK_FAILED)
8966
8967 static int tg3_test_loopback(struct tg3 *tp)
8968 {
8969         int err = 0;
8970
8971         if (!netif_running(tp->dev))
8972                 return TG3_LOOPBACK_FAILED;
8973
8974         err = tg3_reset_hw(tp, 1);
8975         if (err)
8976                 return TG3_LOOPBACK_FAILED;
8977
8978         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8979                 err |= TG3_MAC_LOOPBACK_FAILED;
8980         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8981                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8982                         err |= TG3_PHY_LOOPBACK_FAILED;
8983         }
8984
8985         return err;
8986 }
8987
8988 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8989                           u64 *data)
8990 {
8991         struct tg3 *tp = netdev_priv(dev);
8992
8993         if (tp->link_config.phy_is_low_power)
8994                 tg3_set_power_state(tp, PCI_D0);
8995
8996         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8997
8998         if (tg3_test_nvram(tp) != 0) {
8999                 etest->flags |= ETH_TEST_FL_FAILED;
9000                 data[0] = 1;
9001         }
9002         if (tg3_test_link(tp) != 0) {
9003                 etest->flags |= ETH_TEST_FL_FAILED;
9004                 data[1] = 1;
9005         }
9006         if (etest->flags & ETH_TEST_FL_OFFLINE) {
9007                 int err, irq_sync = 0;
9008
9009                 if (netif_running(dev)) {
9010                         tg3_netif_stop(tp);
9011                         irq_sync = 1;
9012                 }
9013
9014                 tg3_full_lock(tp, irq_sync);
9015
9016                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9017                 err = tg3_nvram_lock(tp);
9018                 tg3_halt_cpu(tp, RX_CPU_BASE);
9019                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9020                         tg3_halt_cpu(tp, TX_CPU_BASE);
9021                 if (!err)
9022                         tg3_nvram_unlock(tp);
9023
9024                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9025                         tg3_phy_reset(tp);
9026
9027                 if (tg3_test_registers(tp) != 0) {
9028                         etest->flags |= ETH_TEST_FL_FAILED;
9029                         data[2] = 1;
9030                 }
9031                 if (tg3_test_memory(tp) != 0) {
9032                         etest->flags |= ETH_TEST_FL_FAILED;
9033                         data[3] = 1;
9034                 }
9035                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9036                         etest->flags |= ETH_TEST_FL_FAILED;
9037
9038                 tg3_full_unlock(tp);
9039
9040                 if (tg3_test_interrupt(tp) != 0) {
9041                         etest->flags |= ETH_TEST_FL_FAILED;
9042                         data[5] = 1;
9043                 }
9044
9045                 tg3_full_lock(tp, 0);
9046
9047                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9048                 if (netif_running(dev)) {
9049                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9050                         if (!tg3_restart_hw(tp, 1))
9051                                 tg3_netif_start(tp);
9052                 }
9053
9054                 tg3_full_unlock(tp);
9055         }
9056         if (tp->link_config.phy_is_low_power)
9057                 tg3_set_power_state(tp, PCI_D3hot);
9058
9059 }
9060
9061 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9062 {
9063         struct mii_ioctl_data *data = if_mii(ifr);
9064         struct tg3 *tp = netdev_priv(dev);
9065         int err;
9066
9067         switch(cmd) {
9068         case SIOCGMIIPHY:
9069                 data->phy_id = PHY_ADDR;
9070
9071                 /* fallthru */
9072         case SIOCGMIIREG: {
9073                 u32 mii_regval;
9074
9075                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9076                         break;                  /* We have no PHY */
9077
9078                 if (tp->link_config.phy_is_low_power)
9079                         return -EAGAIN;
9080
9081                 spin_lock_bh(&tp->lock);
9082                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9083                 spin_unlock_bh(&tp->lock);
9084
9085                 data->val_out = mii_regval;
9086
9087                 return err;
9088         }
9089
9090         case SIOCSMIIREG:
9091                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9092                         break;                  /* We have no PHY */
9093
9094                 if (!capable(CAP_NET_ADMIN))
9095                         return -EPERM;
9096
9097                 if (tp->link_config.phy_is_low_power)
9098                         return -EAGAIN;
9099
9100                 spin_lock_bh(&tp->lock);
9101                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9102                 spin_unlock_bh(&tp->lock);
9103
9104                 return err;
9105
9106         default:
9107                 /* do nothing */
9108                 break;
9109         }
9110         return -EOPNOTSUPP;
9111 }
9112
9113 #if TG3_VLAN_TAG_USED
9114 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9115 {
9116         struct tg3 *tp = netdev_priv(dev);
9117
9118         if (netif_running(dev))
9119                 tg3_netif_stop(tp);
9120
9121         tg3_full_lock(tp, 0);
9122
9123         tp->vlgrp = grp;
9124
9125         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9126         __tg3_set_rx_mode(dev);
9127
9128         tg3_full_unlock(tp);
9129
9130         if (netif_running(dev))
9131                 tg3_netif_start(tp);
9132 }
9133
9134 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9135 {
9136         struct tg3 *tp = netdev_priv(dev);
9137
9138         if (netif_running(dev))
9139                 tg3_netif_stop(tp);
9140
9141         tg3_full_lock(tp, 0);
9142         vlan_group_set_device(tp->vlgrp, vid, NULL);
9143         tg3_full_unlock(tp);
9144
9145         if (netif_running(dev))
9146                 tg3_netif_start(tp);
9147 }
9148 #endif
9149
9150 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9151 {
9152         struct tg3 *tp = netdev_priv(dev);
9153
9154         memcpy(ec, &tp->coal, sizeof(*ec));
9155         return 0;
9156 }
9157
9158 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9159 {
9160         struct tg3 *tp = netdev_priv(dev);
9161         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9162         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9163
9164         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9165                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9166                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9167                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9168                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9169         }
9170
9171         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9172             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9173             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9174             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9175             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9176             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9177             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9178             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9179             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9180             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9181                 return -EINVAL;
9182
9183         /* No rx interrupts will be generated if both are zero */
9184         if ((ec->rx_coalesce_usecs == 0) &&
9185             (ec->rx_max_coalesced_frames == 0))
9186                 return -EINVAL;
9187
9188         /* No tx interrupts will be generated if both are zero */
9189         if ((ec->tx_coalesce_usecs == 0) &&
9190             (ec->tx_max_coalesced_frames == 0))
9191                 return -EINVAL;
9192
9193         /* Only copy relevant parameters, ignore all others. */
9194         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9195         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9196         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9197         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9198         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9199         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9200         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9201         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9202         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9203
9204         if (netif_running(dev)) {
9205                 tg3_full_lock(tp, 0);
9206                 __tg3_set_coalesce(tp, &tp->coal);
9207                 tg3_full_unlock(tp);
9208         }
9209         return 0;
9210 }
9211
9212 static const struct ethtool_ops tg3_ethtool_ops = {
9213         .get_settings           = tg3_get_settings,
9214         .set_settings           = tg3_set_settings,
9215         .get_drvinfo            = tg3_get_drvinfo,
9216         .get_regs_len           = tg3_get_regs_len,
9217         .get_regs               = tg3_get_regs,
9218         .get_wol                = tg3_get_wol,
9219         .set_wol                = tg3_set_wol,
9220         .get_msglevel           = tg3_get_msglevel,
9221         .set_msglevel           = tg3_set_msglevel,
9222         .nway_reset             = tg3_nway_reset,
9223         .get_link               = ethtool_op_get_link,
9224         .get_eeprom_len         = tg3_get_eeprom_len,
9225         .get_eeprom             = tg3_get_eeprom,
9226         .set_eeprom             = tg3_set_eeprom,
9227         .get_ringparam          = tg3_get_ringparam,
9228         .set_ringparam          = tg3_set_ringparam,
9229         .get_pauseparam         = tg3_get_pauseparam,
9230         .set_pauseparam         = tg3_set_pauseparam,
9231         .get_rx_csum            = tg3_get_rx_csum,
9232         .set_rx_csum            = tg3_set_rx_csum,
9233         .get_tx_csum            = ethtool_op_get_tx_csum,
9234         .set_tx_csum            = tg3_set_tx_csum,
9235         .get_sg                 = ethtool_op_get_sg,
9236         .set_sg                 = ethtool_op_set_sg,
9237         .get_tso                = ethtool_op_get_tso,
9238         .set_tso                = tg3_set_tso,
9239         .self_test_count        = tg3_get_test_count,
9240         .self_test              = tg3_self_test,
9241         .get_strings            = tg3_get_strings,
9242         .phys_id                = tg3_phys_id,
9243         .get_stats_count        = tg3_get_stats_count,
9244         .get_ethtool_stats      = tg3_get_ethtool_stats,
9245         .get_coalesce           = tg3_get_coalesce,
9246         .set_coalesce           = tg3_set_coalesce,
9247         .get_perm_addr          = ethtool_op_get_perm_addr,
9248 };
9249
9250 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9251 {
9252         u32 cursize, val, magic;
9253
9254         tp->nvram_size = EEPROM_CHIP_SIZE;
9255
9256         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9257                 return;
9258
9259         if ((magic != TG3_EEPROM_MAGIC) &&
9260             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9261             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9262                 return;
9263
9264         /*
9265          * Size the chip by reading offsets at increasing powers of two.
9266          * When we encounter our validation signature, we know the addressing
9267          * has wrapped around, and thus have our chip size.
9268          */
9269         cursize = 0x10;
9270
9271         while (cursize < tp->nvram_size) {
9272                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9273                         return;
9274
9275                 if (val == magic)
9276                         break;
9277
9278                 cursize <<= 1;
9279         }
9280
9281         tp->nvram_size = cursize;
9282 }
9283
9284 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9285 {
9286         u32 val;
9287
9288         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9289                 return;
9290
9291         /* Selfboot format */
9292         if (val != TG3_EEPROM_MAGIC) {
9293                 tg3_get_eeprom_size(tp);
9294                 return;
9295         }
9296
9297         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9298                 if (val != 0) {
9299                         tp->nvram_size = (val >> 16) * 1024;
9300                         return;
9301                 }
9302         }
9303         tp->nvram_size = 0x80000;
9304 }
9305
9306 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9307 {
9308         u32 nvcfg1;
9309
9310         nvcfg1 = tr32(NVRAM_CFG1);
9311         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9312                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9313         }
9314         else {
9315                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9316                 tw32(NVRAM_CFG1, nvcfg1);
9317         }
9318
9319         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9320             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9321                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9322                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9323                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9324                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9325                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9326                                 break;
9327                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9328                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9329                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9330                                 break;
9331                         case FLASH_VENDOR_ATMEL_EEPROM:
9332                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9333                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9334                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9335                                 break;
9336                         case FLASH_VENDOR_ST:
9337                                 tp->nvram_jedecnum = JEDEC_ST;
9338                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9339                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9340                                 break;
9341                         case FLASH_VENDOR_SAIFUN:
9342                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9343                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9344                                 break;
9345                         case FLASH_VENDOR_SST_SMALL:
9346                         case FLASH_VENDOR_SST_LARGE:
9347                                 tp->nvram_jedecnum = JEDEC_SST;
9348                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9349                                 break;
9350                 }
9351         }
9352         else {
9353                 tp->nvram_jedecnum = JEDEC_ATMEL;
9354                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9355                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9356         }
9357 }
9358
9359 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9360 {
9361         u32 nvcfg1;
9362
9363         nvcfg1 = tr32(NVRAM_CFG1);
9364
9365         /* NVRAM protection for TPM */
9366         if (nvcfg1 & (1 << 27))
9367                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9368
9369         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9370                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9371                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9372                         tp->nvram_jedecnum = JEDEC_ATMEL;
9373                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9374                         break;
9375                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9376                         tp->nvram_jedecnum = JEDEC_ATMEL;
9377                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9378                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9379                         break;
9380                 case FLASH_5752VENDOR_ST_M45PE10:
9381                 case FLASH_5752VENDOR_ST_M45PE20:
9382                 case FLASH_5752VENDOR_ST_M45PE40:
9383                         tp->nvram_jedecnum = JEDEC_ST;
9384                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9385                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9386                         break;
9387         }
9388
9389         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9390                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9391                         case FLASH_5752PAGE_SIZE_256:
9392                                 tp->nvram_pagesize = 256;
9393                                 break;
9394                         case FLASH_5752PAGE_SIZE_512:
9395                                 tp->nvram_pagesize = 512;
9396                                 break;
9397                         case FLASH_5752PAGE_SIZE_1K:
9398                                 tp->nvram_pagesize = 1024;
9399                                 break;
9400                         case FLASH_5752PAGE_SIZE_2K:
9401                                 tp->nvram_pagesize = 2048;
9402                                 break;
9403                         case FLASH_5752PAGE_SIZE_4K:
9404                                 tp->nvram_pagesize = 4096;
9405                                 break;
9406                         case FLASH_5752PAGE_SIZE_264:
9407                                 tp->nvram_pagesize = 264;
9408                                 break;
9409                 }
9410         }
9411         else {
9412                 /* For eeprom, set pagesize to maximum eeprom size */
9413                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9414
9415                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9416                 tw32(NVRAM_CFG1, nvcfg1);
9417         }
9418 }
9419
9420 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9421 {
9422         u32 nvcfg1, protect = 0;
9423
9424         nvcfg1 = tr32(NVRAM_CFG1);
9425
9426         /* NVRAM protection for TPM */
9427         if (nvcfg1 & (1 << 27)) {
9428                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9429                 protect = 1;
9430         }
9431
9432         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9433         switch (nvcfg1) {
9434                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9435                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9436                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9437                         tp->nvram_jedecnum = JEDEC_ATMEL;
9438                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9439                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9440                         tp->nvram_pagesize = 264;
9441                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1)
9442                                 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9443                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9444                                 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9445                         else
9446                                 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
9447                         break;
9448                 case FLASH_5752VENDOR_ST_M45PE10:
9449                 case FLASH_5752VENDOR_ST_M45PE20:
9450                 case FLASH_5752VENDOR_ST_M45PE40:
9451                         tp->nvram_jedecnum = JEDEC_ST;
9452                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9453                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9454                         tp->nvram_pagesize = 256;
9455                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9456                                 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9457                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9458                                 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9459                         else
9460                                 tp->nvram_size = (protect ? 0x20000 : 0x80000);
9461                         break;
9462         }
9463 }
9464
9465 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9466 {
9467         u32 nvcfg1;
9468
9469         nvcfg1 = tr32(NVRAM_CFG1);
9470
9471         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9472                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9473                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9474                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9475                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9476                         tp->nvram_jedecnum = JEDEC_ATMEL;
9477                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9478                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9479
9480                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9481                         tw32(NVRAM_CFG1, nvcfg1);
9482                         break;
9483                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9484                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9485                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9486                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9487                         tp->nvram_jedecnum = JEDEC_ATMEL;
9488                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9489                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9490                         tp->nvram_pagesize = 264;
9491                         break;
9492                 case FLASH_5752VENDOR_ST_M45PE10:
9493                 case FLASH_5752VENDOR_ST_M45PE20:
9494                 case FLASH_5752VENDOR_ST_M45PE40:
9495                         tp->nvram_jedecnum = JEDEC_ST;
9496                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9497                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9498                         tp->nvram_pagesize = 256;
9499                         break;
9500         }
9501 }
9502
9503 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9504 {
9505         tp->nvram_jedecnum = JEDEC_ATMEL;
9506         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9507         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9508 }
9509
9510 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9511 static void __devinit tg3_nvram_init(struct tg3 *tp)
9512 {
9513         tw32_f(GRC_EEPROM_ADDR,
9514              (EEPROM_ADDR_FSM_RESET |
9515               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9516                EEPROM_ADDR_CLKPERD_SHIFT)));
9517
9518         msleep(1);
9519
9520         /* Enable seeprom accesses. */
9521         tw32_f(GRC_LOCAL_CTRL,
9522              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9523         udelay(100);
9524
9525         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9526             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9527                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9528
9529                 if (tg3_nvram_lock(tp)) {
9530                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9531                                "tg3_nvram_init failed.\n", tp->dev->name);
9532                         return;
9533                 }
9534                 tg3_enable_nvram_access(tp);
9535
9536                 tp->nvram_size = 0;
9537
9538                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9539                         tg3_get_5752_nvram_info(tp);
9540                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9541                         tg3_get_5755_nvram_info(tp);
9542                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9543                         tg3_get_5787_nvram_info(tp);
9544                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9545                         tg3_get_5906_nvram_info(tp);
9546                 else
9547                         tg3_get_nvram_info(tp);
9548
9549                 if (tp->nvram_size == 0)
9550                         tg3_get_nvram_size(tp);
9551
9552                 tg3_disable_nvram_access(tp);
9553                 tg3_nvram_unlock(tp);
9554
9555         } else {
9556                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9557
9558                 tg3_get_eeprom_size(tp);
9559         }
9560 }
9561
9562 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9563                                         u32 offset, u32 *val)
9564 {
9565         u32 tmp;
9566         int i;
9567
9568         if (offset > EEPROM_ADDR_ADDR_MASK ||
9569             (offset % 4) != 0)
9570                 return -EINVAL;
9571
9572         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9573                                         EEPROM_ADDR_DEVID_MASK |
9574                                         EEPROM_ADDR_READ);
9575         tw32(GRC_EEPROM_ADDR,
9576              tmp |
9577              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9578              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9579               EEPROM_ADDR_ADDR_MASK) |
9580              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9581
9582         for (i = 0; i < 1000; i++) {
9583                 tmp = tr32(GRC_EEPROM_ADDR);
9584
9585                 if (tmp & EEPROM_ADDR_COMPLETE)
9586                         break;
9587                 msleep(1);
9588         }
9589         if (!(tmp & EEPROM_ADDR_COMPLETE))
9590                 return -EBUSY;
9591
9592         *val = tr32(GRC_EEPROM_DATA);
9593         return 0;
9594 }
9595
9596 #define NVRAM_CMD_TIMEOUT 10000
9597
9598 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9599 {
9600         int i;
9601
9602         tw32(NVRAM_CMD, nvram_cmd);
9603         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9604                 udelay(10);
9605                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9606                         udelay(10);
9607                         break;
9608                 }
9609         }
9610         if (i == NVRAM_CMD_TIMEOUT) {
9611                 return -EBUSY;
9612         }
9613         return 0;
9614 }
9615
9616 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9617 {
9618         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9619             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9620             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9621             (tp->nvram_jedecnum == JEDEC_ATMEL))
9622
9623                 addr = ((addr / tp->nvram_pagesize) <<
9624                         ATMEL_AT45DB0X1B_PAGE_POS) +
9625                        (addr % tp->nvram_pagesize);
9626
9627         return addr;
9628 }
9629
9630 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9631 {
9632         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9633             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9634             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9635             (tp->nvram_jedecnum == JEDEC_ATMEL))
9636
9637                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9638                         tp->nvram_pagesize) +
9639                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9640
9641         return addr;
9642 }
9643
9644 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9645 {
9646         int ret;
9647
9648         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9649                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9650
9651         offset = tg3_nvram_phys_addr(tp, offset);
9652
9653         if (offset > NVRAM_ADDR_MSK)
9654                 return -EINVAL;
9655
9656         ret = tg3_nvram_lock(tp);
9657         if (ret)
9658                 return ret;
9659
9660         tg3_enable_nvram_access(tp);
9661
9662         tw32(NVRAM_ADDR, offset);
9663         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9664                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9665
9666         if (ret == 0)
9667                 *val = swab32(tr32(NVRAM_RDDATA));
9668
9669         tg3_disable_nvram_access(tp);
9670
9671         tg3_nvram_unlock(tp);
9672
9673         return ret;
9674 }
9675
9676 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9677 {
9678         int err;
9679         u32 tmp;
9680
9681         err = tg3_nvram_read(tp, offset, &tmp);
9682         *val = swab32(tmp);
9683         return err;
9684 }
9685
9686 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9687                                     u32 offset, u32 len, u8 *buf)
9688 {
9689         int i, j, rc = 0;
9690         u32 val;
9691
9692         for (i = 0; i < len; i += 4) {
9693                 u32 addr, data;
9694
9695                 addr = offset + i;
9696
9697                 memcpy(&data, buf + i, 4);
9698
9699                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9700
9701                 val = tr32(GRC_EEPROM_ADDR);
9702                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9703
9704                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9705                         EEPROM_ADDR_READ);
9706                 tw32(GRC_EEPROM_ADDR, val |
9707                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9708                         (addr & EEPROM_ADDR_ADDR_MASK) |
9709                         EEPROM_ADDR_START |
9710                         EEPROM_ADDR_WRITE);
9711
9712                 for (j = 0; j < 1000; j++) {
9713                         val = tr32(GRC_EEPROM_ADDR);
9714
9715                         if (val & EEPROM_ADDR_COMPLETE)
9716                                 break;
9717                         msleep(1);
9718                 }
9719                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9720                         rc = -EBUSY;
9721                         break;
9722                 }
9723         }
9724
9725         return rc;
9726 }
9727
9728 /* offset and length are dword aligned */
9729 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9730                 u8 *buf)
9731 {
9732         int ret = 0;
9733         u32 pagesize = tp->nvram_pagesize;
9734         u32 pagemask = pagesize - 1;
9735         u32 nvram_cmd;
9736         u8 *tmp;
9737
9738         tmp = kmalloc(pagesize, GFP_KERNEL);
9739         if (tmp == NULL)
9740                 return -ENOMEM;
9741
9742         while (len) {
9743                 int j;
9744                 u32 phy_addr, page_off, size;
9745
9746                 phy_addr = offset & ~pagemask;
9747
9748                 for (j = 0; j < pagesize; j += 4) {
9749                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9750                                                 (u32 *) (tmp + j))))
9751                                 break;
9752                 }
9753                 if (ret)
9754                         break;
9755
9756                 page_off = offset & pagemask;
9757                 size = pagesize;
9758                 if (len < size)
9759                         size = len;
9760
9761                 len -= size;
9762
9763                 memcpy(tmp + page_off, buf, size);
9764
9765                 offset = offset + (pagesize - page_off);
9766
9767                 tg3_enable_nvram_access(tp);
9768
9769                 /*
9770                  * Before we can erase the flash page, we need
9771                  * to issue a special "write enable" command.
9772                  */
9773                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9774
9775                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9776                         break;
9777
9778                 /* Erase the target page */
9779                 tw32(NVRAM_ADDR, phy_addr);
9780
9781                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9782                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9783
9784                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9785                         break;
9786
9787                 /* Issue another write enable to start the write. */
9788                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9789
9790                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9791                         break;
9792
9793                 for (j = 0; j < pagesize; j += 4) {
9794                         u32 data;
9795
9796                         data = *((u32 *) (tmp + j));
9797                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9798
9799                         tw32(NVRAM_ADDR, phy_addr + j);
9800
9801                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9802                                 NVRAM_CMD_WR;
9803
9804                         if (j == 0)
9805                                 nvram_cmd |= NVRAM_CMD_FIRST;
9806                         else if (j == (pagesize - 4))
9807                                 nvram_cmd |= NVRAM_CMD_LAST;
9808
9809                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9810                                 break;
9811                 }
9812                 if (ret)
9813                         break;
9814         }
9815
9816         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9817         tg3_nvram_exec_cmd(tp, nvram_cmd);
9818
9819         kfree(tmp);
9820
9821         return ret;
9822 }
9823
9824 /* offset and length are dword aligned */
9825 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9826                 u8 *buf)
9827 {
9828         int i, ret = 0;
9829
9830         for (i = 0; i < len; i += 4, offset += 4) {
9831                 u32 data, page_off, phy_addr, nvram_cmd;
9832
9833                 memcpy(&data, buf + i, 4);
9834                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9835
9836                 page_off = offset % tp->nvram_pagesize;
9837
9838                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9839
9840                 tw32(NVRAM_ADDR, phy_addr);
9841
9842                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9843
9844                 if ((page_off == 0) || (i == 0))
9845                         nvram_cmd |= NVRAM_CMD_FIRST;
9846                 if (page_off == (tp->nvram_pagesize - 4))
9847                         nvram_cmd |= NVRAM_CMD_LAST;
9848
9849                 if (i == (len - 4))
9850                         nvram_cmd |= NVRAM_CMD_LAST;
9851
9852                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9853                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9854                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9855                     (tp->nvram_jedecnum == JEDEC_ST) &&
9856                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9857
9858                         if ((ret = tg3_nvram_exec_cmd(tp,
9859                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9860                                 NVRAM_CMD_DONE)))
9861
9862                                 break;
9863                 }
9864                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9865                         /* We always do complete word writes to eeprom. */
9866                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9867                 }
9868
9869                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9870                         break;
9871         }
9872         return ret;
9873 }
9874
9875 /* offset and length are dword aligned */
9876 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9877 {
9878         int ret;
9879
9880         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9881                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9882                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9883                 udelay(40);
9884         }
9885
9886         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9887                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9888         }
9889         else {
9890                 u32 grc_mode;
9891
9892                 ret = tg3_nvram_lock(tp);
9893                 if (ret)
9894                         return ret;
9895
9896                 tg3_enable_nvram_access(tp);
9897                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9898                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9899                         tw32(NVRAM_WRITE1, 0x406);
9900
9901                 grc_mode = tr32(GRC_MODE);
9902                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9903
9904                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9905                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9906
9907                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9908                                 buf);
9909                 }
9910                 else {
9911                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9912                                 buf);
9913                 }
9914
9915                 grc_mode = tr32(GRC_MODE);
9916                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9917
9918                 tg3_disable_nvram_access(tp);
9919                 tg3_nvram_unlock(tp);
9920         }
9921
9922         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9923                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9924                 udelay(40);
9925         }
9926
9927         return ret;
9928 }
9929
9930 struct subsys_tbl_ent {
9931         u16 subsys_vendor, subsys_devid;
9932         u32 phy_id;
9933 };
9934
9935 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9936         /* Broadcom boards. */
9937         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9938         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9939         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9940         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9941         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9942         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9943         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9944         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9945         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9946         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9947         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9948
9949         /* 3com boards. */
9950         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9951         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9952         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9953         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9954         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9955
9956         /* DELL boards. */
9957         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9958         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9959         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9960         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9961
9962         /* Compaq boards. */
9963         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9964         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9965         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9966         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9967         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9968
9969         /* IBM boards. */
9970         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9971 };
9972
9973 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9974 {
9975         int i;
9976
9977         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9978                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9979                      tp->pdev->subsystem_vendor) &&
9980                     (subsys_id_to_phy_id[i].subsys_devid ==
9981                      tp->pdev->subsystem_device))
9982                         return &subsys_id_to_phy_id[i];
9983         }
9984         return NULL;
9985 }
9986
9987 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9988 {
9989         u32 val;
9990         u16 pmcsr;
9991
9992         /* On some early chips the SRAM cannot be accessed in D3hot state,
9993          * so need make sure we're in D0.
9994          */
9995         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9996         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9997         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9998         msleep(1);
9999
10000         /* Make sure register accesses (indirect or otherwise)
10001          * will function correctly.
10002          */
10003         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10004                                tp->misc_host_ctrl);
10005
10006         /* The memory arbiter has to be enabled in order for SRAM accesses
10007          * to succeed.  Normally on powerup the tg3 chip firmware will make
10008          * sure it is enabled, but other entities such as system netboot
10009          * code might disable it.
10010          */
10011         val = tr32(MEMARB_MODE);
10012         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10013
10014         tp->phy_id = PHY_ID_INVALID;
10015         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10016
10017         /* Assume an onboard device and WOL capable by default.  */
10018         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10019
10020         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10021                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10022                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10023                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10024                 }
10025                 if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
10026                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10027                 return;
10028         }
10029
10030         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10031         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10032                 u32 nic_cfg, led_cfg;
10033                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10034                 int eeprom_phy_serdes = 0;
10035
10036                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10037                 tp->nic_sram_data_cfg = nic_cfg;
10038
10039                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10040                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10041                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10042                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10043                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10044                     (ver > 0) && (ver < 0x100))
10045                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10046
10047                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10048                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10049                         eeprom_phy_serdes = 1;
10050
10051                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10052                 if (nic_phy_id != 0) {
10053                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10054                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10055
10056                         eeprom_phy_id  = (id1 >> 16) << 10;
10057                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10058                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10059                 } else
10060                         eeprom_phy_id = 0;
10061
10062                 tp->phy_id = eeprom_phy_id;
10063                 if (eeprom_phy_serdes) {
10064                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10065                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10066                         else
10067                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10068                 }
10069
10070                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10071                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10072                                     SHASTA_EXT_LED_MODE_MASK);
10073                 else
10074                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10075
10076                 switch (led_cfg) {
10077                 default:
10078                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10079                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10080                         break;
10081
10082                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10083                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10084                         break;
10085
10086                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10087                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10088
10089                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10090                          * read on some older 5700/5701 bootcode.
10091                          */
10092                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10093                             ASIC_REV_5700 ||
10094                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10095                             ASIC_REV_5701)
10096                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10097
10098                         break;
10099
10100                 case SHASTA_EXT_LED_SHARED:
10101                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10102                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10103                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10104                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10105                                                  LED_CTRL_MODE_PHY_2);
10106                         break;
10107
10108                 case SHASTA_EXT_LED_MAC:
10109                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10110                         break;
10111
10112                 case SHASTA_EXT_LED_COMBO:
10113                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10114                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10115                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10116                                                  LED_CTRL_MODE_PHY_2);
10117                         break;
10118
10119                 };
10120
10121                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10122                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10123                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10124                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10125
10126                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10127                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10128                         if ((tp->pdev->subsystem_vendor ==
10129                              PCI_VENDOR_ID_ARIMA) &&
10130                             (tp->pdev->subsystem_device == 0x205a ||
10131                              tp->pdev->subsystem_device == 0x2063))
10132                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10133                 } else {
10134                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10135                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10136                 }
10137
10138                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10139                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10140                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10141                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10142                 }
10143                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10144                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10145                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10146
10147                 if (cfg2 & (1 << 17))
10148                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10149
10150                 /* serdes signal pre-emphasis in register 0x590 set by */
10151                 /* bootcode if bit 18 is set */
10152                 if (cfg2 & (1 << 18))
10153                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10154
10155                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10156                         u32 cfg3;
10157
10158                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10159                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10160                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10161                 }
10162         }
10163 }
10164
10165 static int __devinit tg3_phy_probe(struct tg3 *tp)
10166 {
10167         u32 hw_phy_id_1, hw_phy_id_2;
10168         u32 hw_phy_id, hw_phy_id_masked;
10169         int err;
10170
10171         /* Reading the PHY ID register can conflict with ASF
10172          * firwmare access to the PHY hardware.
10173          */
10174         err = 0;
10175         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10176                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10177         } else {
10178                 /* Now read the physical PHY_ID from the chip and verify
10179                  * that it is sane.  If it doesn't look good, we fall back
10180                  * to either the hard-coded table based PHY_ID and failing
10181                  * that the value found in the eeprom area.
10182                  */
10183                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10184                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10185
10186                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10187                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10188                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10189
10190                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10191         }
10192
10193         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10194                 tp->phy_id = hw_phy_id;
10195                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10196                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10197                 else
10198                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10199         } else {
10200                 if (tp->phy_id != PHY_ID_INVALID) {
10201                         /* Do nothing, phy ID already set up in
10202                          * tg3_get_eeprom_hw_cfg().
10203                          */
10204                 } else {
10205                         struct subsys_tbl_ent *p;
10206
10207                         /* No eeprom signature?  Try the hardcoded
10208                          * subsys device table.
10209                          */
10210                         p = lookup_by_subsys(tp);
10211                         if (!p)
10212                                 return -ENODEV;
10213
10214                         tp->phy_id = p->phy_id;
10215                         if (!tp->phy_id ||
10216                             tp->phy_id == PHY_ID_BCM8002)
10217                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10218                 }
10219         }
10220
10221         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10222             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10223                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10224
10225                 tg3_readphy(tp, MII_BMSR, &bmsr);
10226                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10227                     (bmsr & BMSR_LSTATUS))
10228                         goto skip_phy_reset;
10229
10230                 err = tg3_phy_reset(tp);
10231                 if (err)
10232                         return err;
10233
10234                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10235                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10236                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10237                 tg3_ctrl = 0;
10238                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10239                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10240                                     MII_TG3_CTRL_ADV_1000_FULL);
10241                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10242                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10243                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10244                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10245                 }
10246
10247                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10248                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10249                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10250                 if (!tg3_copper_is_advertising_all(tp, mask)) {
10251                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10252
10253                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10254                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10255
10256                         tg3_writephy(tp, MII_BMCR,
10257                                      BMCR_ANENABLE | BMCR_ANRESTART);
10258                 }
10259                 tg3_phy_set_wirespeed(tp);
10260
10261                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10262                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10263                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10264         }
10265
10266 skip_phy_reset:
10267         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10268                 err = tg3_init_5401phy_dsp(tp);
10269                 if (err)
10270                         return err;
10271         }
10272
10273         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10274                 err = tg3_init_5401phy_dsp(tp);
10275         }
10276
10277         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10278                 tp->link_config.advertising =
10279                         (ADVERTISED_1000baseT_Half |
10280                          ADVERTISED_1000baseT_Full |
10281                          ADVERTISED_Autoneg |
10282                          ADVERTISED_FIBRE);
10283         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10284                 tp->link_config.advertising &=
10285                         ~(ADVERTISED_1000baseT_Half |
10286                           ADVERTISED_1000baseT_Full);
10287
10288         return err;
10289 }
10290
10291 static void __devinit tg3_read_partno(struct tg3 *tp)
10292 {
10293         unsigned char vpd_data[256];
10294         unsigned int i;
10295         u32 magic;
10296
10297         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10298                 goto out_not_found;
10299
10300         if (magic == TG3_EEPROM_MAGIC) {
10301                 for (i = 0; i < 256; i += 4) {
10302                         u32 tmp;
10303
10304                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10305                                 goto out_not_found;
10306
10307                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10308                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10309                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10310                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10311                 }
10312         } else {
10313                 int vpd_cap;
10314
10315                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10316                 for (i = 0; i < 256; i += 4) {
10317                         u32 tmp, j = 0;
10318                         u16 tmp16;
10319
10320                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10321                                               i);
10322                         while (j++ < 100) {
10323                                 pci_read_config_word(tp->pdev, vpd_cap +
10324                                                      PCI_VPD_ADDR, &tmp16);
10325                                 if (tmp16 & 0x8000)
10326                                         break;
10327                                 msleep(1);
10328                         }
10329                         if (!(tmp16 & 0x8000))
10330                                 goto out_not_found;
10331
10332                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10333                                               &tmp);
10334                         tmp = cpu_to_le32(tmp);
10335                         memcpy(&vpd_data[i], &tmp, 4);
10336                 }
10337         }
10338
10339         /* Now parse and find the part number. */
10340         for (i = 0; i < 254; ) {
10341                 unsigned char val = vpd_data[i];
10342                 unsigned int block_end;
10343
10344                 if (val == 0x82 || val == 0x91) {
10345                         i = (i + 3 +
10346                              (vpd_data[i + 1] +
10347                               (vpd_data[i + 2] << 8)));
10348                         continue;
10349                 }
10350
10351                 if (val != 0x90)
10352                         goto out_not_found;
10353
10354                 block_end = (i + 3 +
10355                              (vpd_data[i + 1] +
10356                               (vpd_data[i + 2] << 8)));
10357                 i += 3;
10358
10359                 if (block_end > 256)
10360                         goto out_not_found;
10361
10362                 while (i < (block_end - 2)) {
10363                         if (vpd_data[i + 0] == 'P' &&
10364                             vpd_data[i + 1] == 'N') {
10365                                 int partno_len = vpd_data[i + 2];
10366
10367                                 i += 3;
10368                                 if (partno_len > 24 || (partno_len + i) > 256)
10369                                         goto out_not_found;
10370
10371                                 memcpy(tp->board_part_number,
10372                                        &vpd_data[i], partno_len);
10373
10374                                 /* Success. */
10375                                 return;
10376                         }
10377                         i += 3 + vpd_data[i + 2];
10378                 }
10379
10380                 /* Part number not found. */
10381                 goto out_not_found;
10382         }
10383
10384 out_not_found:
10385         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10386                 strcpy(tp->board_part_number, "BCM95906");
10387         else
10388                 strcpy(tp->board_part_number, "none");
10389 }
10390
10391 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10392 {
10393         u32 val, offset, start;
10394
10395         if (tg3_nvram_read_swab(tp, 0, &val))
10396                 return;
10397
10398         if (val != TG3_EEPROM_MAGIC)
10399                 return;
10400
10401         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10402             tg3_nvram_read_swab(tp, 0x4, &start))
10403                 return;
10404
10405         offset = tg3_nvram_logical_addr(tp, offset);
10406         if (tg3_nvram_read_swab(tp, offset, &val))
10407                 return;
10408
10409         if ((val & 0xfc000000) == 0x0c000000) {
10410                 u32 ver_offset, addr;
10411                 int i;
10412
10413                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10414                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10415                         return;
10416
10417                 if (val != 0)
10418                         return;
10419
10420                 addr = offset + ver_offset - start;
10421                 for (i = 0; i < 16; i += 4) {
10422                         if (tg3_nvram_read(tp, addr + i, &val))
10423                                 return;
10424
10425                         val = cpu_to_le32(val);
10426                         memcpy(tp->fw_ver + i, &val, 4);
10427                 }
10428         }
10429 }
10430
10431 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
10432
10433 static int __devinit tg3_get_invariants(struct tg3 *tp)
10434 {
10435         static struct pci_device_id write_reorder_chipsets[] = {
10436                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10437                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10438                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10439                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10440                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10441                              PCI_DEVICE_ID_VIA_8385_0) },
10442                 { },
10443         };
10444         u32 misc_ctrl_reg;
10445         u32 cacheline_sz_reg;
10446         u32 pci_state_reg, grc_misc_cfg;
10447         u32 val;
10448         u16 pci_cmd;
10449         int err, pcie_cap;
10450
10451         /* Force memory write invalidate off.  If we leave it on,
10452          * then on 5700_BX chips we have to enable a workaround.
10453          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10454          * to match the cacheline size.  The Broadcom driver have this
10455          * workaround but turns MWI off all the times so never uses
10456          * it.  This seems to suggest that the workaround is insufficient.
10457          */
10458         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10459         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10460         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10461
10462         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10463          * has the register indirect write enable bit set before
10464          * we try to access any of the MMIO registers.  It is also
10465          * critical that the PCI-X hw workaround situation is decided
10466          * before that as well.
10467          */
10468         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10469                               &misc_ctrl_reg);
10470
10471         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10472                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10473
10474         /* Wrong chip ID in 5752 A0. This code can be removed later
10475          * as A0 is not in production.
10476          */
10477         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10478                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10479
10480         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10481          * we need to disable memory and use config. cycles
10482          * only to access all registers. The 5702/03 chips
10483          * can mistakenly decode the special cycles from the
10484          * ICH chipsets as memory write cycles, causing corruption
10485          * of register and memory space. Only certain ICH bridges
10486          * will drive special cycles with non-zero data during the
10487          * address phase which can fall within the 5703's address
10488          * range. This is not an ICH bug as the PCI spec allows
10489          * non-zero address during special cycles. However, only
10490          * these ICH bridges are known to drive non-zero addresses
10491          * during special cycles.
10492          *
10493          * Since special cycles do not cross PCI bridges, we only
10494          * enable this workaround if the 5703 is on the secondary
10495          * bus of these ICH bridges.
10496          */
10497         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10498             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10499                 static struct tg3_dev_id {
10500                         u32     vendor;
10501                         u32     device;
10502                         u32     rev;
10503                 } ich_chipsets[] = {
10504                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10505                           PCI_ANY_ID },
10506                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10507                           PCI_ANY_ID },
10508                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10509                           0xa },
10510                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10511                           PCI_ANY_ID },
10512                         { },
10513                 };
10514                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10515                 struct pci_dev *bridge = NULL;
10516
10517                 while (pci_id->vendor != 0) {
10518                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10519                                                 bridge);
10520                         if (!bridge) {
10521                                 pci_id++;
10522                                 continue;
10523                         }
10524                         if (pci_id->rev != PCI_ANY_ID) {
10525                                 u8 rev;
10526
10527                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10528                                                      &rev);
10529                                 if (rev > pci_id->rev)
10530                                         continue;
10531                         }
10532                         if (bridge->subordinate &&
10533                             (bridge->subordinate->number ==
10534                              tp->pdev->bus->number)) {
10535
10536                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10537                                 pci_dev_put(bridge);
10538                                 break;
10539                         }
10540                 }
10541         }
10542
10543         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10544          * DMA addresses > 40-bit. This bridge may have other additional
10545          * 57xx devices behind it in some 4-port NIC designs for example.
10546          * Any tg3 device found behind the bridge will also need the 40-bit
10547          * DMA workaround.
10548          */
10549         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10550             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10551                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10552                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10553                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10554         }
10555         else {
10556                 struct pci_dev *bridge = NULL;
10557
10558                 do {
10559                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10560                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10561                                                 bridge);
10562                         if (bridge && bridge->subordinate &&
10563                             (bridge->subordinate->number <=
10564                              tp->pdev->bus->number) &&
10565                             (bridge->subordinate->subordinate >=
10566                              tp->pdev->bus->number)) {
10567                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10568                                 pci_dev_put(bridge);
10569                                 break;
10570                         }
10571                 } while (bridge);
10572         }
10573
10574         /* Initialize misc host control in PCI block. */
10575         tp->misc_host_ctrl |= (misc_ctrl_reg &
10576                                MISC_HOST_CTRL_CHIPREV);
10577         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10578                                tp->misc_host_ctrl);
10579
10580         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10581                               &cacheline_sz_reg);
10582
10583         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10584         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10585         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10586         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10587
10588         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10589             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10590                 tp->pdev_peer = tg3_find_peer(tp);
10591
10592         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10593             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10594             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10595             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10596             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10597             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10598                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10599
10600         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10601             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10602                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10603
10604         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10605                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
10606                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
10607                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
10608                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
10609                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
10610                      tp->pdev_peer == tp->pdev))
10611                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
10612
10613                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10614                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10615                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10616                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10617                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10618                 } else {
10619                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10620                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10621                                 ASIC_REV_5750 &&
10622                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10623                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10624                 }
10625         }
10626
10627         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10628             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10629             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10630             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10631             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10632             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10633                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10634
10635         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10636         if (pcie_cap != 0) {
10637                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10638                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10639                         u16 lnkctl;
10640
10641                         pci_read_config_word(tp->pdev,
10642                                              pcie_cap + PCI_EXP_LNKCTL,
10643                                              &lnkctl);
10644                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10645                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10646                 }
10647         }
10648
10649         /* If we have an AMD 762 or VIA K8T800 chipset, write
10650          * reordering to the mailbox registers done by the host
10651          * controller can cause major troubles.  We read back from
10652          * every mailbox register write to force the writes to be
10653          * posted to the chip in order.
10654          */
10655         if (pci_dev_present(write_reorder_chipsets) &&
10656             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10657                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10658
10659         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10660             tp->pci_lat_timer < 64) {
10661                 tp->pci_lat_timer = 64;
10662
10663                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10664                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10665                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10666                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10667
10668                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10669                                        cacheline_sz_reg);
10670         }
10671
10672         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10673                               &pci_state_reg);
10674
10675         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10676                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10677
10678                 /* If this is a 5700 BX chipset, and we are in PCI-X
10679                  * mode, enable register write workaround.
10680                  *
10681                  * The workaround is to use indirect register accesses
10682                  * for all chip writes not to mailbox registers.
10683                  */
10684                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10685                         u32 pm_reg;
10686                         u16 pci_cmd;
10687
10688                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10689
10690                         /* The chip can have it's power management PCI config
10691                          * space registers clobbered due to this bug.
10692                          * So explicitly force the chip into D0 here.
10693                          */
10694                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10695                                               &pm_reg);
10696                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10697                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10698                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10699                                                pm_reg);
10700
10701                         /* Also, force SERR#/PERR# in PCI command. */
10702                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10703                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10704                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10705                 }
10706         }
10707
10708         /* 5700 BX chips need to have their TX producer index mailboxes
10709          * written twice to workaround a bug.
10710          */
10711         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10712                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10713
10714         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10715                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10716         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10717                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10718
10719         /* Chip-specific fixup from Broadcom driver */
10720         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10721             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10722                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10723                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10724         }
10725
10726         /* Default fast path register access methods */
10727         tp->read32 = tg3_read32;
10728         tp->write32 = tg3_write32;
10729         tp->read32_mbox = tg3_read32;
10730         tp->write32_mbox = tg3_write32;
10731         tp->write32_tx_mbox = tg3_write32;
10732         tp->write32_rx_mbox = tg3_write32;
10733
10734         /* Various workaround register access methods */
10735         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10736                 tp->write32 = tg3_write_indirect_reg32;
10737         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10738                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10739                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
10740                 /*
10741                  * Back to back register writes can cause problems on these
10742                  * chips, the workaround is to read back all reg writes
10743                  * except those to mailbox regs.
10744                  *
10745                  * See tg3_write_indirect_reg32().
10746                  */
10747                 tp->write32 = tg3_write_flush_reg32;
10748         }
10749
10750
10751         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10752             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10753                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10754                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10755                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10756         }
10757
10758         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10759                 tp->read32 = tg3_read_indirect_reg32;
10760                 tp->write32 = tg3_write_indirect_reg32;
10761                 tp->read32_mbox = tg3_read_indirect_mbox;
10762                 tp->write32_mbox = tg3_write_indirect_mbox;
10763                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10764                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10765
10766                 iounmap(tp->regs);
10767                 tp->regs = NULL;
10768
10769                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10770                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10771                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10772         }
10773         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10774                 tp->read32_mbox = tg3_read32_mbox_5906;
10775                 tp->write32_mbox = tg3_write32_mbox_5906;
10776                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10777                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10778         }
10779
10780         if (tp->write32 == tg3_write_indirect_reg32 ||
10781             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10782              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10783               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10784                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10785
10786         /* Get eeprom hw config before calling tg3_set_power_state().
10787          * In particular, the TG3_FLG2_IS_NIC flag must be
10788          * determined before calling tg3_set_power_state() so that
10789          * we know whether or not to switch out of Vaux power.
10790          * When the flag is set, it means that GPIO1 is used for eeprom
10791          * write protect and also implies that it is a LOM where GPIOs
10792          * are not used to switch power.
10793          */
10794         tg3_get_eeprom_hw_cfg(tp);
10795
10796         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10797          * GPIO1 driven high will bring 5700's external PHY out of reset.
10798          * It is also used as eeprom write protect on LOMs.
10799          */
10800         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10801         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10802             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10803                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10804                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10805         /* Unused GPIO3 must be driven as output on 5752 because there
10806          * are no pull-up resistors on unused GPIO pins.
10807          */
10808         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10809                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10810
10811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10812                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10813
10814         /* Force the chip into D0. */
10815         err = tg3_set_power_state(tp, PCI_D0);
10816         if (err) {
10817                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10818                        pci_name(tp->pdev));
10819                 return err;
10820         }
10821
10822         /* 5700 B0 chips do not support checksumming correctly due
10823          * to hardware bugs.
10824          */
10825         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10826                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10827
10828         /* Derive initial jumbo mode from MTU assigned in
10829          * ether_setup() via the alloc_etherdev() call
10830          */
10831         if (tp->dev->mtu > ETH_DATA_LEN &&
10832             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10833                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10834
10835         /* Determine WakeOnLan speed to use. */
10836         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10837             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10838             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10839             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10840                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10841         } else {
10842                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10843         }
10844
10845         /* A few boards don't want Ethernet@WireSpeed phy feature */
10846         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10847             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10848              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10849              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10850             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10851             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10852                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10853
10854         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10855             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10856                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10857         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10858                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10859
10860         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10861                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10862                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10863                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10864                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10865                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10866                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10867                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10868                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10869                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10870         }
10871
10872         tp->coalesce_mode = 0;
10873         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10874             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10875                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10876
10877         /* Initialize MAC MI mode, polling disabled. */
10878         tw32_f(MAC_MI_MODE, tp->mi_mode);
10879         udelay(80);
10880
10881         /* Initialize data/descriptor byte/word swapping. */
10882         val = tr32(GRC_MODE);
10883         val &= GRC_MODE_HOST_STACKUP;
10884         tw32(GRC_MODE, val | tp->grc_mode);
10885
10886         tg3_switch_clocks(tp);
10887
10888         /* Clear this out for sanity. */
10889         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10890
10891         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10892                               &pci_state_reg);
10893         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10894             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10895                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10896
10897                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10898                     chiprevid == CHIPREV_ID_5701_B0 ||
10899                     chiprevid == CHIPREV_ID_5701_B2 ||
10900                     chiprevid == CHIPREV_ID_5701_B5) {
10901                         void __iomem *sram_base;
10902
10903                         /* Write some dummy words into the SRAM status block
10904                          * area, see if it reads back correctly.  If the return
10905                          * value is bad, force enable the PCIX workaround.
10906                          */
10907                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10908
10909                         writel(0x00000000, sram_base);
10910                         writel(0x00000000, sram_base + 4);
10911                         writel(0xffffffff, sram_base + 4);
10912                         if (readl(sram_base) != 0x00000000)
10913                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10914                 }
10915         }
10916
10917         udelay(50);
10918         tg3_nvram_init(tp);
10919
10920         grc_misc_cfg = tr32(GRC_MISC_CFG);
10921         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10922
10923         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10924             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10925              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10926                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10927
10928         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10929             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10930                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10931         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10932                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10933                                       HOSTCC_MODE_CLRTICK_TXBD);
10934
10935                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10936                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10937                                        tp->misc_host_ctrl);
10938         }
10939
10940         /* these are limited to 10/100 only */
10941         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10942              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10943             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10944              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10945              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10946               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10947               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10948             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10949              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10950               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10951               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10952             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10953                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10954
10955         err = tg3_phy_probe(tp);
10956         if (err) {
10957                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10958                        pci_name(tp->pdev), err);
10959                 /* ... but do not return immediately ... */
10960         }
10961
10962         tg3_read_partno(tp);
10963         tg3_read_fw_ver(tp);
10964
10965         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10966                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10967         } else {
10968                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10969                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10970                 else
10971                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10972         }
10973
10974         /* 5700 {AX,BX} chips have a broken status block link
10975          * change bit implementation, so we must use the
10976          * status register in those cases.
10977          */
10978         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10979                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10980         else
10981                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10982
10983         /* The led_ctrl is set during tg3_phy_probe, here we might
10984          * have to force the link status polling mechanism based
10985          * upon subsystem IDs.
10986          */
10987         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10988             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10989                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10990                                   TG3_FLAG_USE_LINKCHG_REG);
10991         }
10992
10993         /* For all SERDES we poll the MAC status register. */
10994         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10995                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10996         else
10997                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10998
10999         /* All chips before 5787 can get confused if TX buffers
11000          * straddle the 4GB address boundary in some cases.
11001          */
11002         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11003             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11005                 tp->dev->hard_start_xmit = tg3_start_xmit;
11006         else
11007                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
11008
11009         tp->rx_offset = 2;
11010         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11011             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11012                 tp->rx_offset = 0;
11013
11014         tp->rx_std_max_post = TG3_RX_RING_SIZE;
11015
11016         /* Increment the rx prod index on the rx std ring by at most
11017          * 8 for these chips to workaround hw errata.
11018          */
11019         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11020             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11021             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11022                 tp->rx_std_max_post = 8;
11023
11024         /* By default, disable wake-on-lan.  User can change this
11025          * using ETHTOOL_SWOL.
11026          */
11027         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
11028
11029         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11030                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11031                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
11032
11033         return err;
11034 }
11035
11036 #ifdef CONFIG_SPARC
11037 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11038 {
11039         struct net_device *dev = tp->dev;
11040         struct pci_dev *pdev = tp->pdev;
11041         struct device_node *dp = pci_device_to_OF_node(pdev);
11042         const unsigned char *addr;
11043         int len;
11044
11045         addr = of_get_property(dp, "local-mac-address", &len);
11046         if (addr && len == 6) {
11047                 memcpy(dev->dev_addr, addr, 6);
11048                 memcpy(dev->perm_addr, dev->dev_addr, 6);
11049                 return 0;
11050         }
11051         return -ENODEV;
11052 }
11053
11054 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11055 {
11056         struct net_device *dev = tp->dev;
11057
11058         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11059         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11060         return 0;
11061 }
11062 #endif
11063
11064 static int __devinit tg3_get_device_address(struct tg3 *tp)
11065 {
11066         struct net_device *dev = tp->dev;
11067         u32 hi, lo, mac_offset;
11068         int addr_ok = 0;
11069
11070 #ifdef CONFIG_SPARC
11071         if (!tg3_get_macaddr_sparc(tp))
11072                 return 0;
11073 #endif
11074
11075         mac_offset = 0x7c;
11076         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11077             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11078                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11079                         mac_offset = 0xcc;
11080                 if (tg3_nvram_lock(tp))
11081                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11082                 else
11083                         tg3_nvram_unlock(tp);
11084         }
11085         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11086                 mac_offset = 0x10;
11087
11088         /* First try to get it from MAC address mailbox. */
11089         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11090         if ((hi >> 16) == 0x484b) {
11091                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11092                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11093
11094                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11095                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11096                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11097                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11098                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11099
11100                 /* Some old bootcode may report a 0 MAC address in SRAM */
11101                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11102         }
11103         if (!addr_ok) {
11104                 /* Next, try NVRAM. */
11105                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11106                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11107                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11108                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11109                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11110                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11111                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11112                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11113                 }
11114                 /* Finally just fetch it out of the MAC control regs. */
11115                 else {
11116                         hi = tr32(MAC_ADDR_0_HIGH);
11117                         lo = tr32(MAC_ADDR_0_LOW);
11118
11119                         dev->dev_addr[5] = lo & 0xff;
11120                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11121                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11122                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11123                         dev->dev_addr[1] = hi & 0xff;
11124                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11125                 }
11126         }
11127
11128         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11129 #ifdef CONFIG_SPARC64
11130                 if (!tg3_get_default_macaddr_sparc(tp))
11131                         return 0;
11132 #endif
11133                 return -EINVAL;
11134         }
11135         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11136         return 0;
11137 }
11138
11139 #define BOUNDARY_SINGLE_CACHELINE       1
11140 #define BOUNDARY_MULTI_CACHELINE        2
11141
11142 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11143 {
11144         int cacheline_size;
11145         u8 byte;
11146         int goal;
11147
11148         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11149         if (byte == 0)
11150                 cacheline_size = 1024;
11151         else
11152                 cacheline_size = (int) byte * 4;
11153
11154         /* On 5703 and later chips, the boundary bits have no
11155          * effect.
11156          */
11157         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11158             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11159             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11160                 goto out;
11161
11162 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11163         goal = BOUNDARY_MULTI_CACHELINE;
11164 #else
11165 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11166         goal = BOUNDARY_SINGLE_CACHELINE;
11167 #else
11168         goal = 0;
11169 #endif
11170 #endif
11171
11172         if (!goal)
11173                 goto out;
11174
11175         /* PCI controllers on most RISC systems tend to disconnect
11176          * when a device tries to burst across a cache-line boundary.
11177          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11178          *
11179          * Unfortunately, for PCI-E there are only limited
11180          * write-side controls for this, and thus for reads
11181          * we will still get the disconnects.  We'll also waste
11182          * these PCI cycles for both read and write for chips
11183          * other than 5700 and 5701 which do not implement the
11184          * boundary bits.
11185          */
11186         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11187             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11188                 switch (cacheline_size) {
11189                 case 16:
11190                 case 32:
11191                 case 64:
11192                 case 128:
11193                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11194                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11195                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11196                         } else {
11197                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11198                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11199                         }
11200                         break;
11201
11202                 case 256:
11203                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11204                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11205                         break;
11206
11207                 default:
11208                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11209                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11210                         break;
11211                 };
11212         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11213                 switch (cacheline_size) {
11214                 case 16:
11215                 case 32:
11216                 case 64:
11217                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11218                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11219                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11220                                 break;
11221                         }
11222                         /* fallthrough */
11223                 case 128:
11224                 default:
11225                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11226                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11227                         break;
11228                 };
11229         } else {
11230                 switch (cacheline_size) {
11231                 case 16:
11232                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11233                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11234                                         DMA_RWCTRL_WRITE_BNDRY_16);
11235                                 break;
11236                         }
11237                         /* fallthrough */
11238                 case 32:
11239                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11240                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11241                                         DMA_RWCTRL_WRITE_BNDRY_32);
11242                                 break;
11243                         }
11244                         /* fallthrough */
11245                 case 64:
11246                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11247                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11248                                         DMA_RWCTRL_WRITE_BNDRY_64);
11249                                 break;
11250                         }
11251                         /* fallthrough */
11252                 case 128:
11253                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11254                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11255                                         DMA_RWCTRL_WRITE_BNDRY_128);
11256                                 break;
11257                         }
11258                         /* fallthrough */
11259                 case 256:
11260                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11261                                 DMA_RWCTRL_WRITE_BNDRY_256);
11262                         break;
11263                 case 512:
11264                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11265                                 DMA_RWCTRL_WRITE_BNDRY_512);
11266                         break;
11267                 case 1024:
11268                 default:
11269                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11270                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11271                         break;
11272                 };
11273         }
11274
11275 out:
11276         return val;
11277 }
11278
11279 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11280 {
11281         struct tg3_internal_buffer_desc test_desc;
11282         u32 sram_dma_descs;
11283         int i, ret;
11284
11285         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11286
11287         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11288         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11289         tw32(RDMAC_STATUS, 0);
11290         tw32(WDMAC_STATUS, 0);
11291
11292         tw32(BUFMGR_MODE, 0);
11293         tw32(FTQ_RESET, 0);
11294
11295         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11296         test_desc.addr_lo = buf_dma & 0xffffffff;
11297         test_desc.nic_mbuf = 0x00002100;
11298         test_desc.len = size;
11299
11300         /*
11301          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11302          * the *second* time the tg3 driver was getting loaded after an
11303          * initial scan.
11304          *
11305          * Broadcom tells me:
11306          *   ...the DMA engine is connected to the GRC block and a DMA
11307          *   reset may affect the GRC block in some unpredictable way...
11308          *   The behavior of resets to individual blocks has not been tested.
11309          *
11310          * Broadcom noted the GRC reset will also reset all sub-components.
11311          */
11312         if (to_device) {
11313                 test_desc.cqid_sqid = (13 << 8) | 2;
11314
11315                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11316                 udelay(40);
11317         } else {
11318                 test_desc.cqid_sqid = (16 << 8) | 7;
11319
11320                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11321                 udelay(40);
11322         }
11323         test_desc.flags = 0x00000005;
11324
11325         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11326                 u32 val;
11327
11328                 val = *(((u32 *)&test_desc) + i);
11329                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11330                                        sram_dma_descs + (i * sizeof(u32)));
11331                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11332         }
11333         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11334
11335         if (to_device) {
11336                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11337         } else {
11338                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11339         }
11340
11341         ret = -ENODEV;
11342         for (i = 0; i < 40; i++) {
11343                 u32 val;
11344
11345                 if (to_device)
11346                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11347                 else
11348                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11349                 if ((val & 0xffff) == sram_dma_descs) {
11350                         ret = 0;
11351                         break;
11352                 }
11353
11354                 udelay(100);
11355         }
11356
11357         return ret;
11358 }
11359
11360 #define TEST_BUFFER_SIZE        0x2000
11361
11362 static int __devinit tg3_test_dma(struct tg3 *tp)
11363 {
11364         dma_addr_t buf_dma;
11365         u32 *buf, saved_dma_rwctrl;
11366         int ret;
11367
11368         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11369         if (!buf) {
11370                 ret = -ENOMEM;
11371                 goto out_nofree;
11372         }
11373
11374         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11375                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11376
11377         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11378
11379         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11380                 /* DMA read watermark not used on PCIE */
11381                 tp->dma_rwctrl |= 0x00180000;
11382         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11383                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11384                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11385                         tp->dma_rwctrl |= 0x003f0000;
11386                 else
11387                         tp->dma_rwctrl |= 0x003f000f;
11388         } else {
11389                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11390                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11391                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11392                         u32 read_water = 0x7;
11393
11394                         /* If the 5704 is behind the EPB bridge, we can
11395                          * do the less restrictive ONE_DMA workaround for
11396                          * better performance.
11397                          */
11398                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11399                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11400                                 tp->dma_rwctrl |= 0x8000;
11401                         else if (ccval == 0x6 || ccval == 0x7)
11402                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11403
11404                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11405                                 read_water = 4;
11406                         /* Set bit 23 to enable PCIX hw bug fix */
11407                         tp->dma_rwctrl |=
11408                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11409                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11410                                 (1 << 23);
11411                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11412                         /* 5780 always in PCIX mode */
11413                         tp->dma_rwctrl |= 0x00144000;
11414                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11415                         /* 5714 always in PCIX mode */
11416                         tp->dma_rwctrl |= 0x00148000;
11417                 } else {
11418                         tp->dma_rwctrl |= 0x001b000f;
11419                 }
11420         }
11421
11422         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11423             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11424                 tp->dma_rwctrl &= 0xfffffff0;
11425
11426         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11427             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11428                 /* Remove this if it causes problems for some boards. */
11429                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11430
11431                 /* On 5700/5701 chips, we need to set this bit.
11432                  * Otherwise the chip will issue cacheline transactions
11433                  * to streamable DMA memory with not all the byte
11434                  * enables turned on.  This is an error on several
11435                  * RISC PCI controllers, in particular sparc64.
11436                  *
11437                  * On 5703/5704 chips, this bit has been reassigned
11438                  * a different meaning.  In particular, it is used
11439                  * on those chips to enable a PCI-X workaround.
11440                  */
11441                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11442         }
11443
11444         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11445
11446 #if 0
11447         /* Unneeded, already done by tg3_get_invariants.  */
11448         tg3_switch_clocks(tp);
11449 #endif
11450
11451         ret = 0;
11452         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11453             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11454                 goto out;
11455
11456         /* It is best to perform DMA test with maximum write burst size
11457          * to expose the 5700/5701 write DMA bug.
11458          */
11459         saved_dma_rwctrl = tp->dma_rwctrl;
11460         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11461         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11462
11463         while (1) {
11464                 u32 *p = buf, i;
11465
11466                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11467                         p[i] = i;
11468
11469                 /* Send the buffer to the chip. */
11470                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11471                 if (ret) {
11472                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11473                         break;
11474                 }
11475
11476 #if 0
11477                 /* validate data reached card RAM correctly. */
11478                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11479                         u32 val;
11480                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11481                         if (le32_to_cpu(val) != p[i]) {
11482                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11483                                 /* ret = -ENODEV here? */
11484                         }
11485                         p[i] = 0;
11486                 }
11487 #endif
11488                 /* Now read it back. */
11489                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11490                 if (ret) {
11491                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11492
11493                         break;
11494                 }
11495
11496                 /* Verify it. */
11497                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11498                         if (p[i] == i)
11499                                 continue;
11500
11501                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11502                             DMA_RWCTRL_WRITE_BNDRY_16) {
11503                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11504                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11505                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11506                                 break;
11507                         } else {
11508                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11509                                 ret = -ENODEV;
11510                                 goto out;
11511                         }
11512                 }
11513
11514                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11515                         /* Success. */
11516                         ret = 0;
11517                         break;
11518                 }
11519         }
11520         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11521             DMA_RWCTRL_WRITE_BNDRY_16) {
11522                 static struct pci_device_id dma_wait_state_chipsets[] = {
11523                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11524                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11525                         { },
11526                 };
11527
11528                 /* DMA test passed without adjusting DMA boundary,
11529                  * now look for chipsets that are known to expose the
11530                  * DMA bug without failing the test.
11531                  */
11532                 if (pci_dev_present(dma_wait_state_chipsets)) {
11533                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11534                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11535                 }
11536                 else
11537                         /* Safe to use the calculated DMA boundary. */
11538                         tp->dma_rwctrl = saved_dma_rwctrl;
11539
11540                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11541         }
11542
11543 out:
11544         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11545 out_nofree:
11546         return ret;
11547 }
11548
11549 static void __devinit tg3_init_link_config(struct tg3 *tp)
11550 {
11551         tp->link_config.advertising =
11552                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11553                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11554                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11555                  ADVERTISED_Autoneg | ADVERTISED_MII);
11556         tp->link_config.speed = SPEED_INVALID;
11557         tp->link_config.duplex = DUPLEX_INVALID;
11558         tp->link_config.autoneg = AUTONEG_ENABLE;
11559         tp->link_config.active_speed = SPEED_INVALID;
11560         tp->link_config.active_duplex = DUPLEX_INVALID;
11561         tp->link_config.phy_is_low_power = 0;
11562         tp->link_config.orig_speed = SPEED_INVALID;
11563         tp->link_config.orig_duplex = DUPLEX_INVALID;
11564         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11565 }
11566
11567 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11568 {
11569         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11570                 tp->bufmgr_config.mbuf_read_dma_low_water =
11571                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11572                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11573                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11574                 tp->bufmgr_config.mbuf_high_water =
11575                         DEFAULT_MB_HIGH_WATER_5705;
11576                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11577                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11578                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11579                         tp->bufmgr_config.mbuf_high_water =
11580                                 DEFAULT_MB_HIGH_WATER_5906;
11581                 }
11582
11583                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11584                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11585                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11586                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11587                 tp->bufmgr_config.mbuf_high_water_jumbo =
11588                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11589         } else {
11590                 tp->bufmgr_config.mbuf_read_dma_low_water =
11591                         DEFAULT_MB_RDMA_LOW_WATER;
11592                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11593                         DEFAULT_MB_MACRX_LOW_WATER;
11594                 tp->bufmgr_config.mbuf_high_water =
11595                         DEFAULT_MB_HIGH_WATER;
11596
11597                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11598                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11599                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11600                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11601                 tp->bufmgr_config.mbuf_high_water_jumbo =
11602                         DEFAULT_MB_HIGH_WATER_JUMBO;
11603         }
11604
11605         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11606         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11607 }
11608
11609 static char * __devinit tg3_phy_string(struct tg3 *tp)
11610 {
11611         switch (tp->phy_id & PHY_ID_MASK) {
11612         case PHY_ID_BCM5400:    return "5400";
11613         case PHY_ID_BCM5401:    return "5401";
11614         case PHY_ID_BCM5411:    return "5411";
11615         case PHY_ID_BCM5701:    return "5701";
11616         case PHY_ID_BCM5703:    return "5703";
11617         case PHY_ID_BCM5704:    return "5704";
11618         case PHY_ID_BCM5705:    return "5705";
11619         case PHY_ID_BCM5750:    return "5750";
11620         case PHY_ID_BCM5752:    return "5752";
11621         case PHY_ID_BCM5714:    return "5714";
11622         case PHY_ID_BCM5780:    return "5780";
11623         case PHY_ID_BCM5755:    return "5755";
11624         case PHY_ID_BCM5787:    return "5787";
11625         case PHY_ID_BCM5756:    return "5722/5756";
11626         case PHY_ID_BCM5906:    return "5906";
11627         case PHY_ID_BCM8002:    return "8002/serdes";
11628         case 0:                 return "serdes";
11629         default:                return "unknown";
11630         };
11631 }
11632
11633 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11634 {
11635         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11636                 strcpy(str, "PCI Express");
11637                 return str;
11638         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11639                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11640
11641                 strcpy(str, "PCIX:");
11642
11643                 if ((clock_ctrl == 7) ||
11644                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11645                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11646                         strcat(str, "133MHz");
11647                 else if (clock_ctrl == 0)
11648                         strcat(str, "33MHz");
11649                 else if (clock_ctrl == 2)
11650                         strcat(str, "50MHz");
11651                 else if (clock_ctrl == 4)
11652                         strcat(str, "66MHz");
11653                 else if (clock_ctrl == 6)
11654                         strcat(str, "100MHz");
11655         } else {
11656                 strcpy(str, "PCI:");
11657                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11658                         strcat(str, "66MHz");
11659                 else
11660                         strcat(str, "33MHz");
11661         }
11662         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11663                 strcat(str, ":32-bit");
11664         else
11665                 strcat(str, ":64-bit");
11666         return str;
11667 }
11668
11669 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11670 {
11671         struct pci_dev *peer;
11672         unsigned int func, devnr = tp->pdev->devfn & ~7;
11673
11674         for (func = 0; func < 8; func++) {
11675                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11676                 if (peer && peer != tp->pdev)
11677                         break;
11678                 pci_dev_put(peer);
11679         }
11680         /* 5704 can be configured in single-port mode, set peer to
11681          * tp->pdev in that case.
11682          */
11683         if (!peer) {
11684                 peer = tp->pdev;
11685                 return peer;
11686         }
11687
11688         /*
11689          * We don't need to keep the refcount elevated; there's no way
11690          * to remove one half of this device without removing the other
11691          */
11692         pci_dev_put(peer);
11693
11694         return peer;
11695 }
11696
11697 static void __devinit tg3_init_coal(struct tg3 *tp)
11698 {
11699         struct ethtool_coalesce *ec = &tp->coal;
11700
11701         memset(ec, 0, sizeof(*ec));
11702         ec->cmd = ETHTOOL_GCOALESCE;
11703         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11704         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11705         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11706         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11707         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11708         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11709         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11710         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11711         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11712
11713         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11714                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11715                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11716                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11717                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11718                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11719         }
11720
11721         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11722                 ec->rx_coalesce_usecs_irq = 0;
11723                 ec->tx_coalesce_usecs_irq = 0;
11724                 ec->stats_block_coalesce_usecs = 0;
11725         }
11726 }
11727
11728 static int __devinit tg3_init_one(struct pci_dev *pdev,
11729                                   const struct pci_device_id *ent)
11730 {
11731         static int tg3_version_printed = 0;
11732         unsigned long tg3reg_base, tg3reg_len;
11733         struct net_device *dev;
11734         struct tg3 *tp;
11735         int i, err, pm_cap;
11736         char str[40];
11737         u64 dma_mask, persist_dma_mask;
11738
11739         if (tg3_version_printed++ == 0)
11740                 printk(KERN_INFO "%s", version);
11741
11742         err = pci_enable_device(pdev);
11743         if (err) {
11744                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11745                        "aborting.\n");
11746                 return err;
11747         }
11748
11749         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11750                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11751                        "base address, aborting.\n");
11752                 err = -ENODEV;
11753                 goto err_out_disable_pdev;
11754         }
11755
11756         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11757         if (err) {
11758                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11759                        "aborting.\n");
11760                 goto err_out_disable_pdev;
11761         }
11762
11763         pci_set_master(pdev);
11764
11765         /* Find power-management capability. */
11766         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11767         if (pm_cap == 0) {
11768                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11769                        "aborting.\n");
11770                 err = -EIO;
11771                 goto err_out_free_res;
11772         }
11773
11774         tg3reg_base = pci_resource_start(pdev, 0);
11775         tg3reg_len = pci_resource_len(pdev, 0);
11776
11777         dev = alloc_etherdev(sizeof(*tp));
11778         if (!dev) {
11779                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11780                 err = -ENOMEM;
11781                 goto err_out_free_res;
11782         }
11783
11784         SET_MODULE_OWNER(dev);
11785         SET_NETDEV_DEV(dev, &pdev->dev);
11786
11787 #if TG3_VLAN_TAG_USED
11788         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11789         dev->vlan_rx_register = tg3_vlan_rx_register;
11790         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11791 #endif
11792
11793         tp = netdev_priv(dev);
11794         tp->pdev = pdev;
11795         tp->dev = dev;
11796         tp->pm_cap = pm_cap;
11797         tp->mac_mode = TG3_DEF_MAC_MODE;
11798         tp->rx_mode = TG3_DEF_RX_MODE;
11799         tp->tx_mode = TG3_DEF_TX_MODE;
11800         tp->mi_mode = MAC_MI_MODE_BASE;
11801         if (tg3_debug > 0)
11802                 tp->msg_enable = tg3_debug;
11803         else
11804                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11805
11806         /* The word/byte swap controls here control register access byte
11807          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11808          * setting below.
11809          */
11810         tp->misc_host_ctrl =
11811                 MISC_HOST_CTRL_MASK_PCI_INT |
11812                 MISC_HOST_CTRL_WORD_SWAP |
11813                 MISC_HOST_CTRL_INDIR_ACCESS |
11814                 MISC_HOST_CTRL_PCISTATE_RW;
11815
11816         /* The NONFRM (non-frame) byte/word swap controls take effect
11817          * on descriptor entries, anything which isn't packet data.
11818          *
11819          * The StrongARM chips on the board (one for tx, one for rx)
11820          * are running in big-endian mode.
11821          */
11822         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11823                         GRC_MODE_WSWAP_NONFRM_DATA);
11824 #ifdef __BIG_ENDIAN
11825         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11826 #endif
11827         spin_lock_init(&tp->lock);
11828         spin_lock_init(&tp->indirect_lock);
11829         INIT_WORK(&tp->reset_task, tg3_reset_task);
11830
11831         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11832         if (tp->regs == 0UL) {
11833                 printk(KERN_ERR PFX "Cannot map device registers, "
11834                        "aborting.\n");
11835                 err = -ENOMEM;
11836                 goto err_out_free_dev;
11837         }
11838
11839         tg3_init_link_config(tp);
11840
11841         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11842         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11843         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11844
11845         dev->open = tg3_open;
11846         dev->stop = tg3_close;
11847         dev->get_stats = tg3_get_stats;
11848         dev->set_multicast_list = tg3_set_rx_mode;
11849         dev->set_mac_address = tg3_set_mac_addr;
11850         dev->do_ioctl = tg3_ioctl;
11851         dev->tx_timeout = tg3_tx_timeout;
11852         dev->poll = tg3_poll;
11853         dev->ethtool_ops = &tg3_ethtool_ops;
11854         dev->weight = 64;
11855         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11856         dev->change_mtu = tg3_change_mtu;
11857         dev->irq = pdev->irq;
11858 #ifdef CONFIG_NET_POLL_CONTROLLER
11859         dev->poll_controller = tg3_poll_controller;
11860 #endif
11861
11862         err = tg3_get_invariants(tp);
11863         if (err) {
11864                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11865                        "aborting.\n");
11866                 goto err_out_iounmap;
11867         }
11868
11869         /* The EPB bridge inside 5714, 5715, and 5780 and any
11870          * device behind the EPB cannot support DMA addresses > 40-bit.
11871          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11872          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11873          * do DMA address check in tg3_start_xmit().
11874          */
11875         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11876                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11877         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11878                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11879 #ifdef CONFIG_HIGHMEM
11880                 dma_mask = DMA_64BIT_MASK;
11881 #endif
11882         } else
11883                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11884
11885         /* Configure DMA attributes. */
11886         if (dma_mask > DMA_32BIT_MASK) {
11887                 err = pci_set_dma_mask(pdev, dma_mask);
11888                 if (!err) {
11889                         dev->features |= NETIF_F_HIGHDMA;
11890                         err = pci_set_consistent_dma_mask(pdev,
11891                                                           persist_dma_mask);
11892                         if (err < 0) {
11893                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11894                                        "DMA for consistent allocations\n");
11895                                 goto err_out_iounmap;
11896                         }
11897                 }
11898         }
11899         if (err || dma_mask == DMA_32BIT_MASK) {
11900                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11901                 if (err) {
11902                         printk(KERN_ERR PFX "No usable DMA configuration, "
11903                                "aborting.\n");
11904                         goto err_out_iounmap;
11905                 }
11906         }
11907
11908         tg3_init_bufmgr_config(tp);
11909
11910         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11911                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11912         }
11913         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11914             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11915             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11916             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11917             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11918                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11919         } else {
11920                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11921         }
11922
11923         /* TSO is on by default on chips that support hardware TSO.
11924          * Firmware TSO on older chips gives lower performance, so it
11925          * is off by default, but can be enabled using ethtool.
11926          */
11927         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11928                 dev->features |= NETIF_F_TSO;
11929                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11930                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11931                         dev->features |= NETIF_F_TSO6;
11932         }
11933
11934
11935         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11936             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11937             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11938                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11939                 tp->rx_pending = 63;
11940         }
11941
11942         err = tg3_get_device_address(tp);
11943         if (err) {
11944                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11945                        "aborting.\n");
11946                 goto err_out_iounmap;
11947         }
11948
11949         /*
11950          * Reset chip in case UNDI or EFI driver did not shutdown
11951          * DMA self test will enable WDMAC and we'll see (spurious)
11952          * pending DMA on the PCI bus at that point.
11953          */
11954         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11955             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11956                 pci_save_state(tp->pdev);
11957                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11958                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11959         }
11960
11961         err = tg3_test_dma(tp);
11962         if (err) {
11963                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11964                 goto err_out_iounmap;
11965         }
11966
11967         /* Tigon3 can do ipv4 only... and some chips have buggy
11968          * checksumming.
11969          */
11970         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11971                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11972                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11973                         dev->features |= NETIF_F_HW_CSUM;
11974                 else
11975                         dev->features |= NETIF_F_IP_CSUM;
11976                 dev->features |= NETIF_F_SG;
11977                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11978         } else
11979                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11980
11981         /* flow control autonegotiation is default behavior */
11982         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11983
11984         tg3_init_coal(tp);
11985
11986         /* Now that we have fully setup the chip, save away a snapshot
11987          * of the PCI config space.  We need to restore this after
11988          * GRC_MISC_CFG core clock resets and some resume events.
11989          */
11990         pci_save_state(tp->pdev);
11991
11992         pci_set_drvdata(pdev, dev);
11993
11994         err = register_netdev(dev);
11995         if (err) {
11996                 printk(KERN_ERR PFX "Cannot register net device, "
11997                        "aborting.\n");
11998                 goto err_out_iounmap;
11999         }
12000
12001         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
12002                dev->name,
12003                tp->board_part_number,
12004                tp->pci_chip_rev_id,
12005                tg3_phy_string(tp),
12006                tg3_bus_string(tp, str),
12007                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12008                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12009                  "10/100/1000Base-T")));
12010
12011         for (i = 0; i < 6; i++)
12012                 printk("%2.2x%c", dev->dev_addr[i],
12013                        i == 5 ? '\n' : ':');
12014
12015         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
12016                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
12017                dev->name,
12018                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12019                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12020                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12021                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
12022                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12023                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
12024         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12025                dev->name, tp->dma_rwctrl,
12026                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12027                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
12028
12029         return 0;
12030
12031 err_out_iounmap:
12032         if (tp->regs) {
12033                 iounmap(tp->regs);
12034                 tp->regs = NULL;
12035         }
12036
12037 err_out_free_dev:
12038         free_netdev(dev);
12039
12040 err_out_free_res:
12041         pci_release_regions(pdev);
12042
12043 err_out_disable_pdev:
12044         pci_disable_device(pdev);
12045         pci_set_drvdata(pdev, NULL);
12046         return err;
12047 }
12048
12049 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12050 {
12051         struct net_device *dev = pci_get_drvdata(pdev);
12052
12053         if (dev) {
12054                 struct tg3 *tp = netdev_priv(dev);
12055
12056                 flush_scheduled_work();
12057                 unregister_netdev(dev);
12058                 if (tp->regs) {
12059                         iounmap(tp->regs);
12060                         tp->regs = NULL;
12061                 }
12062                 free_netdev(dev);
12063                 pci_release_regions(pdev);
12064                 pci_disable_device(pdev);
12065                 pci_set_drvdata(pdev, NULL);
12066         }
12067 }
12068
12069 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12070 {
12071         struct net_device *dev = pci_get_drvdata(pdev);
12072         struct tg3 *tp = netdev_priv(dev);
12073         int err;
12074
12075         if (!netif_running(dev))
12076                 return 0;
12077
12078         flush_scheduled_work();
12079         tg3_netif_stop(tp);
12080
12081         del_timer_sync(&tp->timer);
12082
12083         tg3_full_lock(tp, 1);
12084         tg3_disable_ints(tp);
12085         tg3_full_unlock(tp);
12086
12087         netif_device_detach(dev);
12088
12089         tg3_full_lock(tp, 0);
12090         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12091         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12092         tg3_full_unlock(tp);
12093
12094         /* Save MSI address and data for resume.  */
12095         pci_save_state(pdev);
12096
12097         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12098         if (err) {
12099                 tg3_full_lock(tp, 0);
12100
12101                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12102                 if (tg3_restart_hw(tp, 1))
12103                         goto out;
12104
12105                 tp->timer.expires = jiffies + tp->timer_offset;
12106                 add_timer(&tp->timer);
12107
12108                 netif_device_attach(dev);
12109                 tg3_netif_start(tp);
12110
12111 out:
12112                 tg3_full_unlock(tp);
12113         }
12114
12115         return err;
12116 }
12117
12118 static int tg3_resume(struct pci_dev *pdev)
12119 {
12120         struct net_device *dev = pci_get_drvdata(pdev);
12121         struct tg3 *tp = netdev_priv(dev);
12122         int err;
12123
12124         if (!netif_running(dev))
12125                 return 0;
12126
12127         pci_restore_state(tp->pdev);
12128
12129         err = tg3_set_power_state(tp, PCI_D0);
12130         if (err)
12131                 return err;
12132
12133         netif_device_attach(dev);
12134
12135         tg3_full_lock(tp, 0);
12136
12137         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12138         err = tg3_restart_hw(tp, 1);
12139         if (err)
12140                 goto out;
12141
12142         tp->timer.expires = jiffies + tp->timer_offset;
12143         add_timer(&tp->timer);
12144
12145         tg3_netif_start(tp);
12146
12147 out:
12148         tg3_full_unlock(tp);
12149
12150         return err;
12151 }
12152
12153 static struct pci_driver tg3_driver = {
12154         .name           = DRV_MODULE_NAME,
12155         .id_table       = tg3_pci_tbl,
12156         .probe          = tg3_init_one,
12157         .remove         = __devexit_p(tg3_remove_one),
12158         .suspend        = tg3_suspend,
12159         .resume         = tg3_resume
12160 };
12161
12162 static int __init tg3_init(void)
12163 {
12164         return pci_register_driver(&tg3_driver);
12165 }
12166
12167 static void __exit tg3_cleanup(void)
12168 {
12169         pci_unregister_driver(&tg3_driver);
12170 }
12171
12172 module_init(tg3_init);
12173 module_exit(tg3_cleanup);