drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.103"
  72 #define DRV_MODULE_RELDATE      "November 2, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 /* minimum number of free TX descriptors required to wake up TX process */
 141 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 142
 143 #define TG3_RAW_IP_ALIGN 2
 144
 145 /* number of ETHTOOL_GSTATS u64's */
 146 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 147
 148 #define TG3_NUM_TEST            6
 149
 150 #define FIRMWARE_TG3            "tigon/tg3.bin"
 151 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 152 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 153
 154 static char version[] __devinitdata =
 155         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 156
 157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_MODULE_VERSION);
 161 MODULE_FIRMWARE(FIRMWARE_TG3);
 162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 164
 165 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 166
 167 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 168 module_param(tg3_debug, int, 0);
 169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 170
 171 static struct pci_device_id tg3_pci_tbl[] = {
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 245         {}
 246 };
 247
 248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 249
 250 static const struct {
 251         const char string[ETH_GSTRING_LEN];
 252 } ethtool_stats_keys[TG3_NUM_STATS] = {
 253         { "rx_octets" },
 254         { "rx_fragments" },
 255         { "rx_ucast_packets" },
 256         { "rx_mcast_packets" },
 257         { "rx_bcast_packets" },
 258         { "rx_fcs_errors" },
 259         { "rx_align_errors" },
 260         { "rx_xon_pause_rcvd" },
 261         { "rx_xoff_pause_rcvd" },
 262         { "rx_mac_ctrl_rcvd" },
 263         { "rx_xoff_entered" },
 264         { "rx_frame_too_long_errors" },
 265         { "rx_jabbers" },
 266         { "rx_undersize_packets" },
 267         { "rx_in_length_errors" },
 268         { "rx_out_length_errors" },
 269         { "rx_64_or_less_octet_packets" },
 270         { "rx_65_to_127_octet_packets" },
 271         { "rx_128_to_255_octet_packets" },
 272         { "rx_256_to_511_octet_packets" },
 273         { "rx_512_to_1023_octet_packets" },
 274         { "rx_1024_to_1522_octet_packets" },
 275         { "rx_1523_to_2047_octet_packets" },
 276         { "rx_2048_to_4095_octet_packets" },
 277         { "rx_4096_to_8191_octet_packets" },
 278         { "rx_8192_to_9022_octet_packets" },
 279
 280         { "tx_octets" },
 281         { "tx_collisions" },
 282
 283         { "tx_xon_sent" },
 284         { "tx_xoff_sent" },
 285         { "tx_flow_control" },
 286         { "tx_mac_errors" },
 287         { "tx_single_collisions" },
 288         { "tx_mult_collisions" },
 289         { "tx_deferred" },
 290         { "tx_excessive_collisions" },
 291         { "tx_late_collisions" },
 292         { "tx_collide_2times" },
 293         { "tx_collide_3times" },
 294         { "tx_collide_4times" },
 295         { "tx_collide_5times" },
 296         { "tx_collide_6times" },
 297         { "tx_collide_7times" },
 298         { "tx_collide_8times" },
 299         { "tx_collide_9times" },
 300         { "tx_collide_10times" },
 301         { "tx_collide_11times" },
 302         { "tx_collide_12times" },
 303         { "tx_collide_13times" },
 304         { "tx_collide_14times" },
 305         { "tx_collide_15times" },
 306         { "tx_ucast_packets" },
 307         { "tx_mcast_packets" },
 308         { "tx_bcast_packets" },
 309         { "tx_carrier_sense_errors" },
 310         { "tx_discards" },
 311         { "tx_errors" },
 312
 313         { "dma_writeq_full" },
 314         { "dma_write_prioq_full" },
 315         { "rxbds_empty" },
 316         { "rx_discards" },
 317         { "rx_errors" },
 318         { "rx_threshold_hit" },
 319
 320         { "dma_readq_full" },
 321         { "dma_read_prioq_full" },
 322         { "tx_comp_queue_full" },
 323
 324         { "ring_set_send_prod_index" },
 325         { "ring_status_update" },
 326         { "nic_irqs" },
 327         { "nic_avoided_irqs" },
 328         { "nic_tx_threshold_hit" }
 329 };
 330
 331 static const struct {
 332         const char string[ETH_GSTRING_LEN];
 333 } ethtool_test_keys[TG3_NUM_TEST] = {
 334         { "nvram test     (online) " },
 335         { "link test      (online) " },
 336         { "register test  (offline)" },
 337         { "memory test    (offline)" },
 338         { "loopback test  (offline)" },
 339         { "interrupt test (offline)" },
 340 };
 341
 342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 343 {
 344         writel(val, tp->regs + off);
 345 }
 346
 347 static u32 tg3_read32(struct tg3 *tp, u32 off)
 348 {
 349         return (readl(tp->regs + off));
 350 }
 351
 352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 353 {
 354         writel(val, tp->aperegs + off);
 355 }
 356
 357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 358 {
 359         return (readl(tp->aperegs + off));
 360 }
 361
 362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 363 {
 364         unsigned long flags;
 365
 366         spin_lock_irqsave(&tp->indirect_lock, flags);
 367         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 368         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 369         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 370 }
 371
 372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         writel(val, tp->regs + off);
 375         readl(tp->regs + off);
 376 }
 377
 378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 379 {
 380         unsigned long flags;
 381         u32 val;
 382
 383         spin_lock_irqsave(&tp->indirect_lock, flags);
 384         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 385         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 386         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 387         return val;
 388 }
 389
 390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 391 {
 392         unsigned long flags;
 393
 394         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 395                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 396                                        TG3_64BIT_REG_LOW, val);
 397                 return;
 398         }
 399         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 400                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 401                                        TG3_64BIT_REG_LOW, val);
 402                 return;
 403         }
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409
 410         /* In indirect mode when disabling interrupts, we also need
 411          * to clear the interrupt bit in the GRC local ctrl register.
 412          */
 413         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 414             (val == 0x1)) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 416                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 417         }
 418 }
 419
 420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 421 {
 422         unsigned long flags;
 423         u32 val;
 424
 425         spin_lock_irqsave(&tp->indirect_lock, flags);
 426         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 427         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 428         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 429         return val;
 430 }
 431
 432 /* usec_wait specifies the wait time in usec when writing to certain registers
 433  * where it is unsafe to read back the register without some delay.
 434  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 435  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 436  */
 437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 438 {
 439         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 440             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 441                 /* Non-posted methods */
 442                 tp->write32(tp, off, val);
 443         else {
 444                 /* Posted method */
 445                 tg3_write32(tp, off, val);
 446                 if (usec_wait)
 447                         udelay(usec_wait);
 448                 tp->read32(tp, off);
 449         }
 450         /* Wait again after the read for the posted method to guarantee that
 451          * the wait time is met.
 452          */
 453         if (usec_wait)
 454                 udelay(usec_wait);
 455 }
 456
 457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 458 {
 459         tp->write32_mbox(tp, off, val);
 460         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 461             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 462                 tp->read32_mbox(tp, off);
 463 }
 464
 465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 466 {
 467         void __iomem *mbox = tp->regs + off;
 468         writel(val, mbox);
 469         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 470                 writel(val, mbox);
 471         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 472                 readl(mbox);
 473 }
 474
 475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 476 {
 477         return (readl(tp->regs + off + GRCMBOX_BASE));
 478 }
 479
 480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         writel(val, tp->regs + off + GRCMBOX_BASE);
 483 }
 484
 485 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 486 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 487 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 488 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 489 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 490
 491 #define tw32(reg,val)           tp->write32(tp, reg, val)
 492 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 494 #define tr32(reg)               tp->read32(tp, reg)
 495
 496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         unsigned long flags;
 499
 500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 501             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 502                 return;
 503
 504         spin_lock_irqsave(&tp->indirect_lock, flags);
 505         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 508
 509                 /* Always leave this as zero. */
 510                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 511         } else {
 512                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 513                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 514
 515                 /* Always leave this as zero. */
 516                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 517         }
 518         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 519 }
 520
 521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 522 {
 523         unsigned long flags;
 524
 525         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 526             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 527                 *val = 0;
 528                 return;
 529         }
 530
 531         spin_lock_irqsave(&tp->indirect_lock, flags);
 532         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 533                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 534                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 535
 536                 /* Always leave this as zero. */
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 538         } else {
 539                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 540                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 541
 542                 /* Always leave this as zero. */
 543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 544         }
 545         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 546 }
 547
 548 static void tg3_ape_lock_init(struct tg3 *tp)
 549 {
 550         int i;
 551
 552         /* Make sure the driver hasn't any stale locks. */
 553         for (i = 0; i < 8; i++)
 554                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 555                                 APE_LOCK_GRANT_DRIVER);
 556 }
 557
 558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 559 {
 560         int i, off;
 561         int ret = 0;
 562         u32 status;
 563
 564         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 565                 return 0;
 566
 567         switch (locknum) {
 568                 case TG3_APE_LOCK_GRC:
 569                 case TG3_APE_LOCK_MEM:
 570                         break;
 571                 default:
 572                         return -EINVAL;
 573         }
 574
 575         off = 4 * locknum;
 576
 577         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 578
 579         /* Wait for up to 1 millisecond to acquire lock. */
 580         for (i = 0; i < 100; i++) {
 581                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 582                 if (status == APE_LOCK_GRANT_DRIVER)
 583                         break;
 584                 udelay(10);
 585         }
 586
 587         if (status != APE_LOCK_GRANT_DRIVER) {
 588                 /* Revoke the lock request. */
 589                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 590                                 APE_LOCK_GRANT_DRIVER);
 591
 592                 ret = -EBUSY;
 593         }
 594
 595         return ret;
 596 }
 597
 598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 599 {
 600         int off;
 601
 602         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 603                 return;
 604
 605         switch (locknum) {
 606                 case TG3_APE_LOCK_GRC:
 607                 case TG3_APE_LOCK_MEM:
 608                         break;
 609                 default:
 610                         return;
 611         }
 612
 613         off = 4 * locknum;
 614         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 615 }
 616
 617 static void tg3_disable_ints(struct tg3 *tp)
 618 {
 619         int i;
 620
 621         tw32(TG3PCI_MISC_HOST_CTRL,
 622              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 623         for (i = 0; i < tp->irq_max; i++)
 624                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 625 }
 626
 627 static void tg3_enable_ints(struct tg3 *tp)
 628 {
 629         int i;
 630         u32 coal_now = 0;
 631
 632         tp->irq_sync = 0;
 633         wmb();
 634
 635         tw32(TG3PCI_MISC_HOST_CTRL,
 636              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 637
 638         for (i = 0; i < tp->irq_cnt; i++) {
 639                 struct tg3_napi *tnapi = &tp->napi[i];
 640                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 641                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 642                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 643
 644                 coal_now |= tnapi->coal_now;
 645         }
 646
 647         /* Force an initial interrupt */
 648         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 649             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 650                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 651         else
 652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 653                      HOSTCC_MODE_ENABLE | coal_now);
 654 }
 655
 656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 657 {
 658         struct tg3 *tp = tnapi->tp;
 659         struct tg3_hw_status *sblk = tnapi->hw_status;
 660         unsigned int work_exists = 0;
 661
 662         /* check for phy events */
 663         if (!(tp->tg3_flags &
 664               (TG3_FLAG_USE_LINKCHG_REG |
 665                TG3_FLAG_POLL_SERDES))) {
 666                 if (sblk->status & SD_STATUS_LINK_CHG)
 667                         work_exists = 1;
 668         }
 669         /* check for RX/TX work to do */
 670         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 671             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 672                 work_exists = 1;
 673
 674         return work_exists;
 675 }
 676
 677 /* tg3_int_reenable
 678  *  similar to tg3_enable_ints, but it accurately determines whether there
 679  *  is new work pending and can return without flushing the PIO write
 680  *  which reenables interrupts
 681  */
 682 static void tg3_int_reenable(struct tg3_napi *tnapi)
 683 {
 684         struct tg3 *tp = tnapi->tp;
 685
 686         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 687         mmiowb();
 688
 689         /* When doing tagged status, this work check is unnecessary.
 690          * The last_tag we write above tells the chip which piece of
 691          * work we've completed.
 692          */
 693         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 694             tg3_has_work(tnapi))
 695                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 696                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 697 }
 698
 699 static void tg3_napi_disable(struct tg3 *tp)
 700 {
 701         int i;
 702
 703         for (i = tp->irq_cnt - 1; i >= 0; i--)
 704                 napi_disable(&tp->napi[i].napi);
 705 }
 706
 707 static void tg3_napi_enable(struct tg3 *tp)
 708 {
 709         int i;
 710
 711         for (i = 0; i < tp->irq_cnt; i++)
 712                 napi_enable(&tp->napi[i].napi);
 713 }
 714
 715 static inline void tg3_netif_stop(struct tg3 *tp)
 716 {
 717         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 718         tg3_napi_disable(tp);
 719         netif_tx_disable(tp->dev);
 720 }
 721
 722 static inline void tg3_netif_start(struct tg3 *tp)
 723 {
 724         /* NOTE: unconditional netif_tx_wake_all_queues is only
 725          * appropriate so long as all callers are assured to
 726          * have free tx slots (such as after tg3_init_hw)
 727          */
 728         netif_tx_wake_all_queues(tp->dev);
 729
 730         tg3_napi_enable(tp);
 731         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 732         tg3_enable_ints(tp);
 733 }
 734
 735 static void tg3_switch_clocks(struct tg3 *tp)
 736 {
 737         u32 clock_ctrl;
 738         u32 orig_clock_ctrl;
 739
 740         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 741             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 742                 return;
 743
 744         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 745
 746         orig_clock_ctrl = clock_ctrl;
 747         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 748                        CLOCK_CTRL_CLKRUN_OENABLE |
 749                        0x1f);
 750         tp->pci_clock_ctrl = clock_ctrl;
 751
 752         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 753                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 754                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 755                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 756                 }
 757         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 758                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 759                             clock_ctrl |
 760                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 761                             40);
 762                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 763                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 764                             40);
 765         }
 766         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 767 }
 768
 769 #define PHY_BUSY_LOOPS  5000
 770
 771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 772 {
 773         u32 frame_val;
 774         unsigned int loops;
 775         int ret;
 776
 777         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 778                 tw32_f(MAC_MI_MODE,
 779                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 780                 udelay(80);
 781         }
 782
 783         *val = 0x0;
 784
 785         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 786                       MI_COM_PHY_ADDR_MASK);
 787         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 788                       MI_COM_REG_ADDR_MASK);
 789         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 790
 791         tw32_f(MAC_MI_COM, frame_val);
 792
 793         loops = PHY_BUSY_LOOPS;
 794         while (loops != 0) {
 795                 udelay(10);
 796                 frame_val = tr32(MAC_MI_COM);
 797
 798                 if ((frame_val & MI_COM_BUSY) == 0) {
 799                         udelay(5);
 800                         frame_val = tr32(MAC_MI_COM);
 801                         break;
 802                 }
 803                 loops -= 1;
 804         }
 805
 806         ret = -EBUSY;
 807         if (loops != 0) {
 808                 *val = frame_val & MI_COM_DATA_MASK;
 809                 ret = 0;
 810         }
 811
 812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 813                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 814                 udelay(80);
 815         }
 816
 817         return ret;
 818 }
 819
 820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 821 {
 822         u32 frame_val;
 823         unsigned int loops;
 824         int ret;
 825
 826         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 827             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 828                 return 0;
 829
 830         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 831                 tw32_f(MAC_MI_MODE,
 832                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 833                 udelay(80);
 834         }
 835
 836         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 837                       MI_COM_PHY_ADDR_MASK);
 838         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 839                       MI_COM_REG_ADDR_MASK);
 840         frame_val |= (val & MI_COM_DATA_MASK);
 841         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 842
 843         tw32_f(MAC_MI_COM, frame_val);
 844
 845         loops = PHY_BUSY_LOOPS;
 846         while (loops != 0) {
 847                 udelay(10);
 848                 frame_val = tr32(MAC_MI_COM);
 849                 if ((frame_val & MI_COM_BUSY) == 0) {
 850                         udelay(5);
 851                         frame_val = tr32(MAC_MI_COM);
 852                         break;
 853                 }
 854                 loops -= 1;
 855         }
 856
 857         ret = -EBUSY;
 858         if (loops != 0)
 859                 ret = 0;
 860
 861         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 862                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 863                 udelay(80);
 864         }
 865
 866         return ret;
 867 }
 868
 869 static int tg3_bmcr_reset(struct tg3 *tp)
 870 {
 871         u32 phy_control;
 872         int limit, err;
 873
 874         /* OK, reset it, and poll the BMCR_RESET bit until it
 875          * clears or we time out.
 876          */
 877         phy_control = BMCR_RESET;
 878         err = tg3_writephy(tp, MII_BMCR, phy_control);
 879         if (err != 0)
 880                 return -EBUSY;
 881
 882         limit = 5000;
 883         while (limit--) {
 884                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 885                 if (err != 0)
 886                         return -EBUSY;
 887
 888                 if ((phy_control & BMCR_RESET) == 0) {
 889                         udelay(40);
 890                         break;
 891                 }
 892                 udelay(10);
 893         }
 894         if (limit < 0)
 895                 return -EBUSY;
 896
 897         return 0;
 898 }
 899
 900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 901 {
 902         struct tg3 *tp = bp->priv;
 903         u32 val;
 904
 905         spin_lock_bh(&tp->lock);
 906
 907         if (tg3_readphy(tp, reg, &val))
 908                 val = -EIO;
 909
 910         spin_unlock_bh(&tp->lock);
 911
 912         return val;
 913 }
 914
 915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 ret = 0;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_writephy(tp, reg, val))
 923                 ret = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return ret;
 928 }
 929
 930 static int tg3_mdio_reset(struct mii_bus *bp)
 931 {
 932         return 0;
 933 }
 934
 935 static void tg3_mdio_config_5785(struct tg3 *tp)
 936 {
 937         u32 val;
 938         struct phy_device *phydev;
 939
 940         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 941         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 942         case TG3_PHY_ID_BCM50610:
 943         case TG3_PHY_ID_BCM50610M:
 944                 val = MAC_PHYCFG2_50610_LED_MODES;
 945                 break;
 946         case TG3_PHY_ID_BCMAC131:
 947                 val = MAC_PHYCFG2_AC131_LED_MODES;
 948                 break;
 949         case TG3_PHY_ID_RTL8211C:
 950                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 951                 break;
 952         case TG3_PHY_ID_RTL8201E:
 953                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 954                 break;
 955         default:
 956                 return;
 957         }
 958
 959         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 960                 tw32(MAC_PHYCFG2, val);
 961
 962                 val = tr32(MAC_PHYCFG1);
 963                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 964                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 965                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 966                 tw32(MAC_PHYCFG1, val);
 967
 968                 return;
 969         }
 970
 971         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 972                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 973                        MAC_PHYCFG2_FMODE_MASK_MASK |
 974                        MAC_PHYCFG2_GMODE_MASK_MASK |
 975                        MAC_PHYCFG2_ACT_MASK_MASK   |
 976                        MAC_PHYCFG2_QUAL_MASK_MASK |
 977                        MAC_PHYCFG2_INBAND_ENABLE;
 978
 979         tw32(MAC_PHYCFG2, val);
 980
 981         val = tr32(MAC_PHYCFG1);
 982         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 983                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 984         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 985                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 986                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 987                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 988                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 989         }
 990         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 991                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 992         tw32(MAC_PHYCFG1, val);
 993
 994         val = tr32(MAC_EXT_RGMII_MODE);
 995         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 996                  MAC_RGMII_MODE_RX_QUALITY |
 997                  MAC_RGMII_MODE_RX_ACTIVITY |
 998                  MAC_RGMII_MODE_RX_ENG_DET |
 999                  MAC_RGMII_MODE_TX_ENABLE |
1000                  MAC_RGMII_MODE_TX_LOWPWR |
1001                  MAC_RGMII_MODE_TX_RESET);
1002         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1003                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004                         val |= MAC_RGMII_MODE_RX_INT_B |
1005                                MAC_RGMII_MODE_RX_QUALITY |
1006                                MAC_RGMII_MODE_RX_ACTIVITY |
1007                                MAC_RGMII_MODE_RX_ENG_DET;
1008                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009                         val |= MAC_RGMII_MODE_TX_ENABLE |
1010                                MAC_RGMII_MODE_TX_LOWPWR |
1011                                MAC_RGMII_MODE_TX_RESET;
1012         }
1013         tw32(MAC_EXT_RGMII_MODE, val);
1014 }
1015
1016 static void tg3_mdio_start(struct tg3 *tp)
1017 {
1018         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019         tw32_f(MAC_MI_MODE, tp->mi_mode);
1020         udelay(80);
1021
1022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023                 u32 funcnum, is_serdes;
1024
1025                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026                 if (funcnum)
1027                         tp->phy_addr = 2;
1028                 else
1029                         tp->phy_addr = 1;
1030
1031                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032                 if (is_serdes)
1033                         tp->phy_addr += 7;
1034         } else
1035                 tp->phy_addr = TG3_PHY_MII_ADDR;
1036
1037         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039                 tg3_mdio_config_5785(tp);
1040 }
1041
1042 static int tg3_mdio_init(struct tg3 *tp)
1043 {
1044         int i;
1045         u32 reg;
1046         struct phy_device *phydev;
1047
1048         tg3_mdio_start(tp);
1049
1050         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052                 return 0;
1053
1054         tp->mdio_bus = mdiobus_alloc();
1055         if (tp->mdio_bus == NULL)
1056                 return -ENOMEM;
1057
1058         tp->mdio_bus->name     = "tg3 mdio bus";
1059         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1060                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1061         tp->mdio_bus->priv     = tp;
1062         tp->mdio_bus->parent   = &tp->pdev->dev;
1063         tp->mdio_bus->read     = &tg3_mdio_read;
1064         tp->mdio_bus->write    = &tg3_mdio_write;
1065         tp->mdio_bus->reset    = &tg3_mdio_reset;
1066         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1067         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1068
1069         for (i = 0; i < PHY_MAX_ADDR; i++)
1070                 tp->mdio_bus->irq[i] = PHY_POLL;
1071
1072         /* The bus registration will look for all the PHYs on the mdio bus.
1073          * Unfortunately, it does not ensure the PHY is powered up before
1074          * accessing the PHY ID registers.  A chip reset is the
1075          * quickest way to bring the device back to an operational state..
1076          */
1077         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078                 tg3_bmcr_reset(tp);
1079
1080         i = mdiobus_register(tp->mdio_bus);
1081         if (i) {
1082                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083                         tp->dev->name, i);
1084                 mdiobus_free(tp->mdio_bus);
1085                 return i;
1086         }
1087
1088         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1089
1090         if (!phydev || !phydev->drv) {
1091                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092                 mdiobus_unregister(tp->mdio_bus);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return -ENODEV;
1095         }
1096
1097         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1098         case TG3_PHY_ID_BCM57780:
1099                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1100                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1101                 break;
1102         case TG3_PHY_ID_BCM50610:
1103         case TG3_PHY_ID_BCM50610M:
1104                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1105                                      PHY_BRCM_RX_REFCLK_UNUSED |
1106                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1107                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1108                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1109                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1110                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1111                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1112                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1113                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1114                 /* fallthru */
1115         case TG3_PHY_ID_RTL8211C:
1116                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1117                 break;
1118         case TG3_PHY_ID_RTL8201E:
1119         case TG3_PHY_ID_BCMAC131:
1120                 phydev->interface = PHY_INTERFACE_MODE_MII;
1121                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1122                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1123                 break;
1124         }
1125
1126         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1127
1128         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1129                 tg3_mdio_config_5785(tp);
1130
1131         return 0;
1132 }
1133
1134 static void tg3_mdio_fini(struct tg3 *tp)
1135 {
1136         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1137                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1138                 mdiobus_unregister(tp->mdio_bus);
1139                 mdiobus_free(tp->mdio_bus);
1140         }
1141 }
1142
1143 /* tp->lock is held. */
1144 static inline void tg3_generate_fw_event(struct tg3 *tp)
1145 {
1146         u32 val;
1147
1148         val = tr32(GRC_RX_CPU_EVENT);
1149         val |= GRC_RX_CPU_DRIVER_EVENT;
1150         tw32_f(GRC_RX_CPU_EVENT, val);
1151
1152         tp->last_event_jiffies = jiffies;
1153 }
1154
1155 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1156
1157 /* tp->lock is held. */
1158 static void tg3_wait_for_event_ack(struct tg3 *tp)
1159 {
1160         int i;
1161         unsigned int delay_cnt;
1162         long time_remain;
1163
1164         /* If enough time has passed, no wait is necessary. */
1165         time_remain = (long)(tp->last_event_jiffies + 1 +
1166                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1167                       (long)jiffies;
1168         if (time_remain < 0)
1169                 return;
1170
1171         /* Check if we can shorten the wait time. */
1172         delay_cnt = jiffies_to_usecs(time_remain);
1173         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1174                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1175         delay_cnt = (delay_cnt >> 3) + 1;
1176
1177         for (i = 0; i < delay_cnt; i++) {
1178                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1179                         break;
1180                 udelay(8);
1181         }
1182 }
1183
1184 /* tp->lock is held. */
1185 static void tg3_ump_link_report(struct tg3 *tp)
1186 {
1187         u32 reg;
1188         u32 val;
1189
1190         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1191             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1192                 return;
1193
1194         tg3_wait_for_event_ack(tp);
1195
1196         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1197
1198         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1199
1200         val = 0;
1201         if (!tg3_readphy(tp, MII_BMCR, &reg))
1202                 val = reg << 16;
1203         if (!tg3_readphy(tp, MII_BMSR, &reg))
1204                 val |= (reg & 0xffff);
1205         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1206
1207         val = 0;
1208         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1209                 val = reg << 16;
1210         if (!tg3_readphy(tp, MII_LPA, &reg))
1211                 val |= (reg & 0xffff);
1212         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1213
1214         val = 0;
1215         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1216                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1217                         val = reg << 16;
1218                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1219                         val |= (reg & 0xffff);
1220         }
1221         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1222
1223         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1224                 val = reg << 16;
1225         else
1226                 val = 0;
1227         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1228
1229         tg3_generate_fw_event(tp);
1230 }
1231
1232 static void tg3_link_report(struct tg3 *tp)
1233 {
1234         if (!netif_carrier_ok(tp->dev)) {
1235                 if (netif_msg_link(tp))
1236                         printk(KERN_INFO PFX "%s: Link is down.\n",
1237                                tp->dev->name);
1238                 tg3_ump_link_report(tp);
1239         } else if (netif_msg_link(tp)) {
1240                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1241                        tp->dev->name,
1242                        (tp->link_config.active_speed == SPEED_1000 ?
1243                         1000 :
1244                         (tp->link_config.active_speed == SPEED_100 ?
1245                          100 : 10)),
1246                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1247                         "full" : "half"));
1248
1249                 printk(KERN_INFO PFX
1250                        "%s: Flow control is %s for TX and %s for RX.\n",
1251                        tp->dev->name,
1252                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1253                        "on" : "off",
1254                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1255                        "on" : "off");
1256                 tg3_ump_link_report(tp);
1257         }
1258 }
1259
1260 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1261 {
1262         u16 miireg;
1263
1264         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1265                 miireg = ADVERTISE_PAUSE_CAP;
1266         else if (flow_ctrl & FLOW_CTRL_TX)
1267                 miireg = ADVERTISE_PAUSE_ASYM;
1268         else if (flow_ctrl & FLOW_CTRL_RX)
1269                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1270         else
1271                 miireg = 0;
1272
1273         return miireg;
1274 }
1275
1276 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1277 {
1278         u16 miireg;
1279
1280         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1281                 miireg = ADVERTISE_1000XPAUSE;
1282         else if (flow_ctrl & FLOW_CTRL_TX)
1283                 miireg = ADVERTISE_1000XPSE_ASYM;
1284         else if (flow_ctrl & FLOW_CTRL_RX)
1285                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1286         else
1287                 miireg = 0;
1288
1289         return miireg;
1290 }
1291
1292 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1293 {
1294         u8 cap = 0;
1295
1296         if (lcladv & ADVERTISE_1000XPAUSE) {
1297                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1298                         if (rmtadv & LPA_1000XPAUSE)
1299                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1300                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1301                                 cap = FLOW_CTRL_RX;
1302                 } else {
1303                         if (rmtadv & LPA_1000XPAUSE)
1304                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1305                 }
1306         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1308                         cap = FLOW_CTRL_TX;
1309         }
1310
1311         return cap;
1312 }
1313
1314 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1315 {
1316         u8 autoneg;
1317         u8 flowctrl = 0;
1318         u32 old_rx_mode = tp->rx_mode;
1319         u32 old_tx_mode = tp->tx_mode;
1320
1321         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1322                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1323         else
1324                 autoneg = tp->link_config.autoneg;
1325
1326         if (autoneg == AUTONEG_ENABLE &&
1327             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1328                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1329                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1330                 else
1331                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1332         } else
1333                 flowctrl = tp->link_config.flowctrl;
1334
1335         tp->link_config.active_flowctrl = flowctrl;
1336
1337         if (flowctrl & FLOW_CTRL_RX)
1338                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1339         else
1340                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1341
1342         if (old_rx_mode != tp->rx_mode)
1343                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1344
1345         if (flowctrl & FLOW_CTRL_TX)
1346                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1347         else
1348                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1349
1350         if (old_tx_mode != tp->tx_mode)
1351                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1352 }
1353
1354 static void tg3_adjust_link(struct net_device *dev)
1355 {
1356         u8 oldflowctrl, linkmesg = 0;
1357         u32 mac_mode, lcl_adv, rmt_adv;
1358         struct tg3 *tp = netdev_priv(dev);
1359         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1360
1361         spin_lock_bh(&tp->lock);
1362
1363         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1364                                     MAC_MODE_HALF_DUPLEX);
1365
1366         oldflowctrl = tp->link_config.active_flowctrl;
1367
1368         if (phydev->link) {
1369                 lcl_adv = 0;
1370                 rmt_adv = 0;
1371
1372                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1373                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1374                 else if (phydev->speed == SPEED_1000 ||
1375                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1376                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1377                 else
1378                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1379
1380                 if (phydev->duplex == DUPLEX_HALF)
1381                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1382                 else {
1383                         lcl_adv = tg3_advert_flowctrl_1000T(
1384                                   tp->link_config.flowctrl);
1385
1386                         if (phydev->pause)
1387                                 rmt_adv = LPA_PAUSE_CAP;
1388                         if (phydev->asym_pause)
1389                                 rmt_adv |= LPA_PAUSE_ASYM;
1390                 }
1391
1392                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1393         } else
1394                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1395
1396         if (mac_mode != tp->mac_mode) {
1397                 tp->mac_mode = mac_mode;
1398                 tw32_f(MAC_MODE, tp->mac_mode);
1399                 udelay(40);
1400         }
1401
1402         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1403                 if (phydev->speed == SPEED_10)
1404                         tw32(MAC_MI_STAT,
1405                              MAC_MI_STAT_10MBPS_MODE |
1406                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1407                 else
1408                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1409         }
1410
1411         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1412                 tw32(MAC_TX_LENGTHS,
1413                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1414                       (6 << TX_LENGTHS_IPG_SHIFT) |
1415                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1416         else
1417                 tw32(MAC_TX_LENGTHS,
1418                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1419                       (6 << TX_LENGTHS_IPG_SHIFT) |
1420                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1421
1422         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1423             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1424             phydev->speed != tp->link_config.active_speed ||
1425             phydev->duplex != tp->link_config.active_duplex ||
1426             oldflowctrl != tp->link_config.active_flowctrl)
1427             linkmesg = 1;
1428
1429         tp->link_config.active_speed = phydev->speed;
1430         tp->link_config.active_duplex = phydev->duplex;
1431
1432         spin_unlock_bh(&tp->lock);
1433
1434         if (linkmesg)
1435                 tg3_link_report(tp);
1436 }
1437
1438 static int tg3_phy_init(struct tg3 *tp)
1439 {
1440         struct phy_device *phydev;
1441
1442         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1443                 return 0;
1444
1445         /* Bring the PHY back to a known state. */
1446         tg3_bmcr_reset(tp);
1447
1448         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1449
1450         /* Attach the MAC to the PHY. */
1451         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1452                              phydev->dev_flags, phydev->interface);
1453         if (IS_ERR(phydev)) {
1454                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1455                 return PTR_ERR(phydev);
1456         }
1457
1458         /* Mask with MAC supported features. */
1459         switch (phydev->interface) {
1460         case PHY_INTERFACE_MODE_GMII:
1461         case PHY_INTERFACE_MODE_RGMII:
1462                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1463                         phydev->supported &= (PHY_GBIT_FEATURES |
1464                                               SUPPORTED_Pause |
1465                                               SUPPORTED_Asym_Pause);
1466                         break;
1467                 }
1468                 /* fallthru */
1469         case PHY_INTERFACE_MODE_MII:
1470                 phydev->supported &= (PHY_BASIC_FEATURES |
1471                                       SUPPORTED_Pause |
1472                                       SUPPORTED_Asym_Pause);
1473                 break;
1474         default:
1475                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1476                 return -EINVAL;
1477         }
1478
1479         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1480
1481         phydev->advertising = phydev->supported;
1482
1483         return 0;
1484 }
1485
1486 static void tg3_phy_start(struct tg3 *tp)
1487 {
1488         struct phy_device *phydev;
1489
1490         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1491                 return;
1492
1493         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1494
1495         if (tp->link_config.phy_is_low_power) {
1496                 tp->link_config.phy_is_low_power = 0;
1497                 phydev->speed = tp->link_config.orig_speed;
1498                 phydev->duplex = tp->link_config.orig_duplex;
1499                 phydev->autoneg = tp->link_config.orig_autoneg;
1500                 phydev->advertising = tp->link_config.orig_advertising;
1501         }
1502
1503         phy_start(phydev);
1504
1505         phy_start_aneg(phydev);
1506 }
1507
1508 static void tg3_phy_stop(struct tg3 *tp)
1509 {
1510         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511                 return;
1512
1513         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1514 }
1515
1516 static void tg3_phy_fini(struct tg3 *tp)
1517 {
1518         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1519                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1520                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1521         }
1522 }
1523
1524 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1525 {
1526         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1527         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1528 }
1529
1530 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1531 {
1532         u32 phytest;
1533
1534         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1535                 u32 phy;
1536
1537                 tg3_writephy(tp, MII_TG3_FET_TEST,
1538                              phytest | MII_TG3_FET_SHADOW_EN);
1539                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1540                         if (enable)
1541                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1542                         else
1543                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1544                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1545                 }
1546                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1547         }
1548 }
1549
1550 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1551 {
1552         u32 reg;
1553
1554         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1555                 return;
1556
1557         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1558                 tg3_phy_fet_toggle_apd(tp, enable);
1559                 return;
1560         }
1561
1562         reg = MII_TG3_MISC_SHDW_WREN |
1563               MII_TG3_MISC_SHDW_SCR5_SEL |
1564               MII_TG3_MISC_SHDW_SCR5_LPED |
1565               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1566               MII_TG3_MISC_SHDW_SCR5_SDTL |
1567               MII_TG3_MISC_SHDW_SCR5_C125OE;
1568         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1569                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1570
1571         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1572
1573
1574         reg = MII_TG3_MISC_SHDW_WREN |
1575               MII_TG3_MISC_SHDW_APD_SEL |
1576               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1577         if (enable)
1578                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1579
1580         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581 }
1582
1583 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1584 {
1585         u32 phy;
1586
1587         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1588             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1589                 return;
1590
1591         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1592                 u32 ephy;
1593
1594                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1595                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1596
1597                         tg3_writephy(tp, MII_TG3_FET_TEST,
1598                                      ephy | MII_TG3_FET_SHADOW_EN);
1599                         if (!tg3_readphy(tp, reg, &phy)) {
1600                                 if (enable)
1601                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1602                                 else
1603                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1604                                 tg3_writephy(tp, reg, phy);
1605                         }
1606                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1607                 }
1608         } else {
1609                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1610                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1611                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1612                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1613                         if (enable)
1614                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1615                         else
1616                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1617                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1618                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1619                 }
1620         }
1621 }
1622
1623 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1624 {
1625         u32 val;
1626
1627         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1628                 return;
1629
1630         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1631             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1632                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1633                              (val | (1 << 15) | (1 << 4)));
1634 }
1635
1636 static void tg3_phy_apply_otp(struct tg3 *tp)
1637 {
1638         u32 otp, phy;
1639
1640         if (!tp->phy_otp)
1641                 return;
1642
1643         otp = tp->phy_otp;
1644
1645         /* Enable SM_DSP clock and tx 6dB coding. */
1646         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1647               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1648               MII_TG3_AUXCTL_ACTL_TX_6DB;
1649         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1650
1651         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1652         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1653         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1654
1655         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1656               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1657         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1658
1659         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1660         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1661         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1662
1663         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1664         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1665
1666         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1667         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1668
1669         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1670               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1671         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1672
1673         /* Turn off SM_DSP clock. */
1674         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1675               MII_TG3_AUXCTL_ACTL_TX_6DB;
1676         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1677 }
1678
1679 static int tg3_wait_macro_done(struct tg3 *tp)
1680 {
1681         int limit = 100;
1682
1683         while (limit--) {
1684                 u32 tmp32;
1685
1686                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1687                         if ((tmp32 & 0x1000) == 0)
1688                                 break;
1689                 }
1690         }
1691         if (limit < 0)
1692                 return -EBUSY;
1693
1694         return 0;
1695 }
1696
1697 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1698 {
1699         static const u32 test_pat[4][6] = {
1700         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1701         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1702         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1703         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1704         };
1705         int chan;
1706
1707         for (chan = 0; chan < 4; chan++) {
1708                 int i;
1709
1710                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1711                              (chan * 0x2000) | 0x0200);
1712                 tg3_writephy(tp, 0x16, 0x0002);
1713
1714                 for (i = 0; i < 6; i++)
1715                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1716                                      test_pat[chan][i]);
1717
1718                 tg3_writephy(tp, 0x16, 0x0202);
1719                 if (tg3_wait_macro_done(tp)) {
1720                         *resetp = 1;
1721                         return -EBUSY;
1722                 }
1723
1724                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1725                              (chan * 0x2000) | 0x0200);
1726                 tg3_writephy(tp, 0x16, 0x0082);
1727                 if (tg3_wait_macro_done(tp)) {
1728                         *resetp = 1;
1729                         return -EBUSY;
1730                 }
1731
1732                 tg3_writephy(tp, 0x16, 0x0802);
1733                 if (tg3_wait_macro_done(tp)) {
1734                         *resetp = 1;
1735                         return -EBUSY;
1736                 }
1737
1738                 for (i = 0; i < 6; i += 2) {
1739                         u32 low, high;
1740
1741                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1742                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1743                             tg3_wait_macro_done(tp)) {
1744                                 *resetp = 1;
1745                                 return -EBUSY;
1746                         }
1747                         low &= 0x7fff;
1748                         high &= 0x000f;
1749                         if (low != test_pat[chan][i] ||
1750                             high != test_pat[chan][i+1]) {
1751                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1752                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1753                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1754
1755                                 return -EBUSY;
1756                         }
1757                 }
1758         }
1759
1760         return 0;
1761 }
1762
1763 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1764 {
1765         int chan;
1766
1767         for (chan = 0; chan < 4; chan++) {
1768                 int i;
1769
1770                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1771                              (chan * 0x2000) | 0x0200);
1772                 tg3_writephy(tp, 0x16, 0x0002);
1773                 for (i = 0; i < 6; i++)
1774                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1775                 tg3_writephy(tp, 0x16, 0x0202);
1776                 if (tg3_wait_macro_done(tp))
1777                         return -EBUSY;
1778         }
1779
1780         return 0;
1781 }
1782
1783 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1784 {
1785         u32 reg32, phy9_orig;
1786         int retries, do_phy_reset, err;
1787
1788         retries = 10;
1789         do_phy_reset = 1;
1790         do {
1791                 if (do_phy_reset) {
1792                         err = tg3_bmcr_reset(tp);
1793                         if (err)
1794                                 return err;
1795                         do_phy_reset = 0;
1796                 }
1797
1798                 /* Disable transmitter and interrupt.  */
1799                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1800                         continue;
1801
1802                 reg32 |= 0x3000;
1803                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1804
1805                 /* Set full-duplex, 1000 mbps.  */
1806                 tg3_writephy(tp, MII_BMCR,
1807                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1808
1809                 /* Set to master mode.  */
1810                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1811                         continue;
1812
1813                 tg3_writephy(tp, MII_TG3_CTRL,
1814                              (MII_TG3_CTRL_AS_MASTER |
1815                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1816
1817                 /* Enable SM_DSP_CLOCK and 6dB.  */
1818                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1819
1820                 /* Block the PHY control access.  */
1821                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1822                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1823
1824                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1825                 if (!err)
1826                         break;
1827         } while (--retries);
1828
1829         err = tg3_phy_reset_chanpat(tp);
1830         if (err)
1831                 return err;
1832
1833         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1834         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1835
1836         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1837         tg3_writephy(tp, 0x16, 0x0000);
1838
1839         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1840             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1841                 /* Set Extended packet length bit for jumbo frames */
1842                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1843         }
1844         else {
1845                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1846         }
1847
1848         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1849
1850         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1851                 reg32 &= ~0x3000;
1852                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1853         } else if (!err)
1854                 err = -EBUSY;
1855
1856         return err;
1857 }
1858
1859 /* This will reset the tigon3 PHY if there is no valid
1860  * link unless the FORCE argument is non-zero.
1861  */
1862 static int tg3_phy_reset(struct tg3 *tp)
1863 {
1864         u32 cpmuctrl;
1865         u32 phy_status;
1866         int err;
1867
1868         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1869                 u32 val;
1870
1871                 val = tr32(GRC_MISC_CFG);
1872                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1873                 udelay(40);
1874         }
1875         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1876         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1877         if (err != 0)
1878                 return -EBUSY;
1879
1880         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1881                 netif_carrier_off(tp->dev);
1882                 tg3_link_report(tp);
1883         }
1884
1885         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1886             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1887             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1888                 err = tg3_phy_reset_5703_4_5(tp);
1889                 if (err)
1890                         return err;
1891                 goto out;
1892         }
1893
1894         cpmuctrl = 0;
1895         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1896             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1897                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1898                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1899                         tw32(TG3_CPMU_CTRL,
1900                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1901         }
1902
1903         err = tg3_bmcr_reset(tp);
1904         if (err)
1905                 return err;
1906
1907         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1908                 u32 phy;
1909
1910                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1911                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1912
1913                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1914         }
1915
1916         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1917             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1918                 u32 val;
1919
1920                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1921                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1922                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1923                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1924                         udelay(40);
1925                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1926                 }
1927         }
1928
1929         tg3_phy_apply_otp(tp);
1930
1931         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1932                 tg3_phy_toggle_apd(tp, true);
1933         else
1934                 tg3_phy_toggle_apd(tp, false);
1935
1936 out:
1937         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1939                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1940                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1941                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1942                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1943                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1944         }
1945         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1946                 tg3_writephy(tp, 0x1c, 0x8d68);
1947                 tg3_writephy(tp, 0x1c, 0x8d68);
1948         }
1949         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1950                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1951                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1952                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1953                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1954                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1955                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1956                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1957                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958         }
1959         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1961                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1962                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1963                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1964                         tg3_writephy(tp, MII_TG3_TEST1,
1965                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1966                 } else
1967                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1969         }
1970         /* Set Extended packet length bit (bit 14) on all chips that */
1971         /* support jumbo frames */
1972         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1973                 /* Cannot do read-modify-write on 5401 */
1974                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1975         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1976                 u32 phy_reg;
1977
1978                 /* Set bit 14 with read-modify-write to preserve other bits */
1979                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1980                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1981                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1982         }
1983
1984         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1985          * jumbo frames transmission.
1986          */
1987         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1988                 u32 phy_reg;
1989
1990                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1991                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1992                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1993         }
1994
1995         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1996                 /* adjust output voltage */
1997                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1998         }
1999
2000         tg3_phy_toggle_automdix(tp, 1);
2001         tg3_phy_set_wirespeed(tp);
2002         return 0;
2003 }
2004
2005 static void tg3_frob_aux_power(struct tg3 *tp)
2006 {
2007         struct tg3 *tp_peer = tp;
2008
2009         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2010                 return;
2011
2012         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2013             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2015                 struct net_device *dev_peer;
2016
2017                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2018                 /* remove_one() may have been run on the peer. */
2019                 if (!dev_peer)
2020                         tp_peer = tp;
2021                 else
2022                         tp_peer = netdev_priv(dev_peer);
2023         }
2024
2025         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2026             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2027             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2028             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2029                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2030                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2031                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2032                                     (GRC_LCLCTRL_GPIO_OE0 |
2033                                      GRC_LCLCTRL_GPIO_OE1 |
2034                                      GRC_LCLCTRL_GPIO_OE2 |
2035                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2036                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2037                                     100);
2038                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2039                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2040                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2041                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2042                                              GRC_LCLCTRL_GPIO_OE1 |
2043                                              GRC_LCLCTRL_GPIO_OE2 |
2044                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2045                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2046                                              tp->grc_local_ctrl;
2047                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2048
2049                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2050                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2051
2052                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2053                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2054                 } else {
2055                         u32 no_gpio2;
2056                         u32 grc_local_ctrl = 0;
2057
2058                         if (tp_peer != tp &&
2059                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2060                                 return;
2061
2062                         /* Workaround to prevent overdrawing Amps. */
2063                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2064                             ASIC_REV_5714) {
2065                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2066                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067                                             grc_local_ctrl, 100);
2068                         }
2069
2070                         /* On 5753 and variants, GPIO2 cannot be used. */
2071                         no_gpio2 = tp->nic_sram_data_cfg &
2072                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2073
2074                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2075                                          GRC_LCLCTRL_GPIO_OE1 |
2076                                          GRC_LCLCTRL_GPIO_OE2 |
2077                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2078                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2079                         if (no_gpio2) {
2080                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2081                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2082                         }
2083                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2084                                                     grc_local_ctrl, 100);
2085
2086                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2087
2088                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089                                                     grc_local_ctrl, 100);
2090
2091                         if (!no_gpio2) {
2092                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2093                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094                                             grc_local_ctrl, 100);
2095                         }
2096                 }
2097         } else {
2098                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2099                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2100                         if (tp_peer != tp &&
2101                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2102                                 return;
2103
2104                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105                                     (GRC_LCLCTRL_GPIO_OE1 |
2106                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2107
2108                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109                                     GRC_LCLCTRL_GPIO_OE1, 100);
2110
2111                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112                                     (GRC_LCLCTRL_GPIO_OE1 |
2113                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2114                 }
2115         }
2116 }
2117
2118 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2119 {
2120         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2121                 return 1;
2122         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2123                 if (speed != SPEED_10)
2124                         return 1;
2125         } else if (speed == SPEED_10)
2126                 return 1;
2127
2128         return 0;
2129 }
2130
2131 static int tg3_setup_phy(struct tg3 *, int);
2132
2133 #define RESET_KIND_SHUTDOWN     0
2134 #define RESET_KIND_INIT         1
2135 #define RESET_KIND_SUSPEND      2
2136
2137 static void tg3_write_sig_post_reset(struct tg3 *, int);
2138 static int tg3_halt_cpu(struct tg3 *, u32);
2139
2140 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2141 {
2142         u32 val;
2143
2144         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2146                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2147                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2148
2149                         sg_dig_ctrl |=
2150                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2151                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2152                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2153                 }
2154                 return;
2155         }
2156
2157         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2158                 tg3_bmcr_reset(tp);
2159                 val = tr32(GRC_MISC_CFG);
2160                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2161                 udelay(40);
2162                 return;
2163         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2164                 u32 phytest;
2165                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2166                         u32 phy;
2167
2168                         tg3_writephy(tp, MII_ADVERTISE, 0);
2169                         tg3_writephy(tp, MII_BMCR,
2170                                      BMCR_ANENABLE | BMCR_ANRESTART);
2171
2172                         tg3_writephy(tp, MII_TG3_FET_TEST,
2173                                      phytest | MII_TG3_FET_SHADOW_EN);
2174                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2175                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2176                                 tg3_writephy(tp,
2177                                              MII_TG3_FET_SHDW_AUXMODE4,
2178                                              phy);
2179                         }
2180                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2181                 }
2182                 return;
2183         } else if (do_low_power) {
2184                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2185                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2186
2187                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2188                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2189                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2190                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2191                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2192         }
2193
2194         /* The PHY should not be powered down on some chips because
2195          * of bugs.
2196          */
2197         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2198             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2199             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2200              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2201                 return;
2202
2203         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2204             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2205                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2206                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2207                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2208                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2209         }
2210
2211         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2212 }
2213
2214 /* tp->lock is held. */
2215 static int tg3_nvram_lock(struct tg3 *tp)
2216 {
2217         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2218                 int i;
2219
2220                 if (tp->nvram_lock_cnt == 0) {
2221                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2222                         for (i = 0; i < 8000; i++) {
2223                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2224                                         break;
2225                                 udelay(20);
2226                         }
2227                         if (i == 8000) {
2228                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2229                                 return -ENODEV;
2230                         }
2231                 }
2232                 tp->nvram_lock_cnt++;
2233         }
2234         return 0;
2235 }
2236
2237 /* tp->lock is held. */
2238 static void tg3_nvram_unlock(struct tg3 *tp)
2239 {
2240         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2241                 if (tp->nvram_lock_cnt > 0)
2242                         tp->nvram_lock_cnt--;
2243                 if (tp->nvram_lock_cnt == 0)
2244                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2245         }
2246 }
2247
2248 /* tp->lock is held. */
2249 static void tg3_enable_nvram_access(struct tg3 *tp)
2250 {
2251         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2252             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2253                 u32 nvaccess = tr32(NVRAM_ACCESS);
2254
2255                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2256         }
2257 }
2258
2259 /* tp->lock is held. */
2260 static void tg3_disable_nvram_access(struct tg3 *tp)
2261 {
2262         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2263             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2264                 u32 nvaccess = tr32(NVRAM_ACCESS);
2265
2266                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2267         }
2268 }
2269
2270 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2271                                         u32 offset, u32 *val)
2272 {
2273         u32 tmp;
2274         int i;
2275
2276         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2277                 return -EINVAL;
2278
2279         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2280                                         EEPROM_ADDR_DEVID_MASK |
2281                                         EEPROM_ADDR_READ);
2282         tw32(GRC_EEPROM_ADDR,
2283              tmp |
2284              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2285              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2286               EEPROM_ADDR_ADDR_MASK) |
2287              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2288
2289         for (i = 0; i < 1000; i++) {
2290                 tmp = tr32(GRC_EEPROM_ADDR);
2291
2292                 if (tmp & EEPROM_ADDR_COMPLETE)
2293                         break;
2294                 msleep(1);
2295         }
2296         if (!(tmp & EEPROM_ADDR_COMPLETE))
2297                 return -EBUSY;
2298
2299         tmp = tr32(GRC_EEPROM_DATA);
2300
2301         /*
2302          * The data will always be opposite the native endian
2303          * format.  Perform a blind byteswap to compensate.
2304          */
2305         *val = swab32(tmp);
2306
2307         return 0;
2308 }
2309
2310 #define NVRAM_CMD_TIMEOUT 10000
2311
2312 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2313 {
2314         int i;
2315
2316         tw32(NVRAM_CMD, nvram_cmd);
2317         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2318                 udelay(10);
2319                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2320                         udelay(10);
2321                         break;
2322                 }
2323         }
2324
2325         if (i == NVRAM_CMD_TIMEOUT)
2326                 return -EBUSY;
2327
2328         return 0;
2329 }
2330
2331 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2332 {
2333         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2334             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2335             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2336            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2337             (tp->nvram_jedecnum == JEDEC_ATMEL))
2338
2339                 addr = ((addr / tp->nvram_pagesize) <<
2340                         ATMEL_AT45DB0X1B_PAGE_POS) +
2341                        (addr % tp->nvram_pagesize);
2342
2343         return addr;
2344 }
2345
2346 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2347 {
2348         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352             (tp->nvram_jedecnum == JEDEC_ATMEL))
2353
2354                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2355                         tp->nvram_pagesize) +
2356                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2357
2358         return addr;
2359 }
2360
2361 /* NOTE: Data read in from NVRAM is byteswapped according to
2362  * the byteswapping settings for all other register accesses.
2363  * tg3 devices are BE devices, so on a BE machine, the data
2364  * returned will be exactly as it is seen in NVRAM.  On a LE
2365  * machine, the 32-bit value will be byteswapped.
2366  */
2367 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2368 {
2369         int ret;
2370
2371         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2372                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2373
2374         offset = tg3_nvram_phys_addr(tp, offset);
2375
2376         if (offset > NVRAM_ADDR_MSK)
2377                 return -EINVAL;
2378
2379         ret = tg3_nvram_lock(tp);
2380         if (ret)
2381                 return ret;
2382
2383         tg3_enable_nvram_access(tp);
2384
2385         tw32(NVRAM_ADDR, offset);
2386         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2387                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2388
2389         if (ret == 0)
2390                 *val = tr32(NVRAM_RDDATA);
2391
2392         tg3_disable_nvram_access(tp);
2393
2394         tg3_nvram_unlock(tp);
2395
2396         return ret;
2397 }
2398
2399 /* Ensures NVRAM data is in bytestream format. */
2400 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2401 {
2402         u32 v;
2403         int res = tg3_nvram_read(tp, offset, &v);
2404         if (!res)
2405                 *val = cpu_to_be32(v);
2406         return res;
2407 }
2408
2409 /* tp->lock is held. */
2410 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2411 {
2412         u32 addr_high, addr_low;
2413         int i;
2414
2415         addr_high = ((tp->dev->dev_addr[0] << 8) |
2416                      tp->dev->dev_addr[1]);
2417         addr_low = ((tp->dev->dev_addr[2] << 24) |
2418                     (tp->dev->dev_addr[3] << 16) |
2419                     (tp->dev->dev_addr[4] <<  8) |
2420                     (tp->dev->dev_addr[5] <<  0));
2421         for (i = 0; i < 4; i++) {
2422                 if (i == 1 && skip_mac_1)
2423                         continue;
2424                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2425                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2426         }
2427
2428         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2429             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2430                 for (i = 0; i < 12; i++) {
2431                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2432                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2433                 }
2434         }
2435
2436         addr_high = (tp->dev->dev_addr[0] +
2437                      tp->dev->dev_addr[1] +
2438                      tp->dev->dev_addr[2] +
2439                      tp->dev->dev_addr[3] +
2440                      tp->dev->dev_addr[4] +
2441                      tp->dev->dev_addr[5]) &
2442                 TX_BACKOFF_SEED_MASK;
2443         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2444 }
2445
2446 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2447 {
2448         u32 misc_host_ctrl;
2449         bool device_should_wake, do_low_power;
2450
2451         /* Make sure register accesses (indirect or otherwise)
2452          * will function correctly.
2453          */
2454         pci_write_config_dword(tp->pdev,
2455                                TG3PCI_MISC_HOST_CTRL,
2456                                tp->misc_host_ctrl);
2457
2458         switch (state) {
2459         case PCI_D0:
2460                 pci_enable_wake(tp->pdev, state, false);
2461                 pci_set_power_state(tp->pdev, PCI_D0);
2462
2463                 /* Switch out of Vaux if it is a NIC */
2464                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2465                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2466
2467                 return 0;
2468
2469         case PCI_D1:
2470         case PCI_D2:
2471         case PCI_D3hot:
2472                 break;
2473
2474         default:
2475                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2476                         tp->dev->name, state);
2477                 return -EINVAL;
2478         }
2479
2480         /* Restore the CLKREQ setting. */
2481         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2482                 u16 lnkctl;
2483
2484                 pci_read_config_word(tp->pdev,
2485                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2486                                      &lnkctl);
2487                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2488                 pci_write_config_word(tp->pdev,
2489                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2490                                       lnkctl);
2491         }
2492
2493         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2494         tw32(TG3PCI_MISC_HOST_CTRL,
2495              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2496
2497         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2498                              device_may_wakeup(&tp->pdev->dev) &&
2499                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2500
2501         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2502                 do_low_power = false;
2503                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2504                     !tp->link_config.phy_is_low_power) {
2505                         struct phy_device *phydev;
2506                         u32 phyid, advertising;
2507
2508                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2509
2510                         tp->link_config.phy_is_low_power = 1;
2511
2512                         tp->link_config.orig_speed = phydev->speed;
2513                         tp->link_config.orig_duplex = phydev->duplex;
2514                         tp->link_config.orig_autoneg = phydev->autoneg;
2515                         tp->link_config.orig_advertising = phydev->advertising;
2516
2517                         advertising = ADVERTISED_TP |
2518                                       ADVERTISED_Pause |
2519                                       ADVERTISED_Autoneg |
2520                                       ADVERTISED_10baseT_Half;
2521
2522                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2523                             device_should_wake) {
2524                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2525                                         advertising |=
2526                                                 ADVERTISED_100baseT_Half |
2527                                                 ADVERTISED_100baseT_Full |
2528                                                 ADVERTISED_10baseT_Full;
2529                                 else
2530                                         advertising |= ADVERTISED_10baseT_Full;
2531                         }
2532
2533                         phydev->advertising = advertising;
2534
2535                         phy_start_aneg(phydev);
2536
2537                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2538                         if (phyid != TG3_PHY_ID_BCMAC131) {
2539                                 phyid &= TG3_PHY_OUI_MASK;
2540                                 if (phyid == TG3_PHY_OUI_1 ||
2541                                     phyid == TG3_PHY_OUI_2 ||
2542                                     phyid == TG3_PHY_OUI_3)
2543                                         do_low_power = true;
2544                         }
2545                 }
2546         } else {
2547                 do_low_power = true;
2548
2549                 if (tp->link_config.phy_is_low_power == 0) {
2550                         tp->link_config.phy_is_low_power = 1;
2551                         tp->link_config.orig_speed = tp->link_config.speed;
2552                         tp->link_config.orig_duplex = tp->link_config.duplex;
2553                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2554                 }
2555
2556                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2557                         tp->link_config.speed = SPEED_10;
2558                         tp->link_config.duplex = DUPLEX_HALF;
2559                         tp->link_config.autoneg = AUTONEG_ENABLE;
2560                         tg3_setup_phy(tp, 0);
2561                 }
2562         }
2563
2564         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2565                 u32 val;
2566
2567                 val = tr32(GRC_VCPU_EXT_CTRL);
2568                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2569         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2570                 int i;
2571                 u32 val;
2572
2573                 for (i = 0; i < 200; i++) {
2574                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2575                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2576                                 break;
2577                         msleep(1);
2578                 }
2579         }
2580         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2581                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2582                                                      WOL_DRV_STATE_SHUTDOWN |
2583                                                      WOL_DRV_WOL |
2584                                                      WOL_SET_MAGIC_PKT);
2585
2586         if (device_should_wake) {
2587                 u32 mac_mode;
2588
2589                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2590                         if (do_low_power) {
2591                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2592                                 udelay(40);
2593                         }
2594
2595                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2596                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2597                         else
2598                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2599
2600                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2601                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2602                             ASIC_REV_5700) {
2603                                 u32 speed = (tp->tg3_flags &
2604                                              TG3_FLAG_WOL_SPEED_100MB) ?
2605                                              SPEED_100 : SPEED_10;
2606                                 if (tg3_5700_link_polarity(tp, speed))
2607                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2608                                 else
2609                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2610                         }
2611                 } else {
2612                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2613                 }
2614
2615                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2616                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2617
2618                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2619                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2620                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2621                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2622                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2623                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2624
2625                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2626                         mac_mode |= tp->mac_mode &
2627                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2628                         if (mac_mode & MAC_MODE_APE_TX_EN)
2629                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2630                 }
2631
2632                 tw32_f(MAC_MODE, mac_mode);
2633                 udelay(100);
2634
2635                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2636                 udelay(10);
2637         }
2638
2639         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2640             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2641              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2642                 u32 base_val;
2643
2644                 base_val = tp->pci_clock_ctrl;
2645                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2646                              CLOCK_CTRL_TXCLK_DISABLE);
2647
2648                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2649                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2650         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2651                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2652                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2653                 /* do nothing */
2654         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2655                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2656                 u32 newbits1, newbits2;
2657
2658                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2659                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2660                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2661                                     CLOCK_CTRL_TXCLK_DISABLE |
2662                                     CLOCK_CTRL_ALTCLK);
2663                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2664                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2665                         newbits1 = CLOCK_CTRL_625_CORE;
2666                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2667                 } else {
2668                         newbits1 = CLOCK_CTRL_ALTCLK;
2669                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2670                 }
2671
2672                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2673                             40);
2674
2675                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2676                             40);
2677
2678                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2679                         u32 newbits3;
2680
2681                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2682                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2683                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2684                                             CLOCK_CTRL_TXCLK_DISABLE |
2685                                             CLOCK_CTRL_44MHZ_CORE);
2686                         } else {
2687                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2688                         }
2689
2690                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2691                                     tp->pci_clock_ctrl | newbits3, 40);
2692                 }
2693         }
2694
2695         if (!(device_should_wake) &&
2696             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2697                 tg3_power_down_phy(tp, do_low_power);
2698
2699         tg3_frob_aux_power(tp);
2700
2701         /* Workaround for unstable PLL clock */
2702         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2703             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2704                 u32 val = tr32(0x7d00);
2705
2706                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2707                 tw32(0x7d00, val);
2708                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2709                         int err;
2710
2711                         err = tg3_nvram_lock(tp);
2712                         tg3_halt_cpu(tp, RX_CPU_BASE);
2713                         if (!err)
2714                                 tg3_nvram_unlock(tp);
2715                 }
2716         }
2717
2718         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2719
2720         if (device_should_wake)
2721                 pci_enable_wake(tp->pdev, state, true);
2722
2723         /* Finally, set the new power state. */
2724         pci_set_power_state(tp->pdev, state);
2725
2726         return 0;
2727 }
2728
2729 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2730 {
2731         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2732         case MII_TG3_AUX_STAT_10HALF:
2733                 *speed = SPEED_10;
2734                 *duplex = DUPLEX_HALF;
2735                 break;
2736
2737         case MII_TG3_AUX_STAT_10FULL:
2738                 *speed = SPEED_10;
2739                 *duplex = DUPLEX_FULL;
2740                 break;
2741
2742         case MII_TG3_AUX_STAT_100HALF:
2743                 *speed = SPEED_100;
2744                 *duplex = DUPLEX_HALF;
2745                 break;
2746
2747         case MII_TG3_AUX_STAT_100FULL:
2748                 *speed = SPEED_100;
2749                 *duplex = DUPLEX_FULL;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_1000HALF:
2753                 *speed = SPEED_1000;
2754                 *duplex = DUPLEX_HALF;
2755                 break;
2756
2757         case MII_TG3_AUX_STAT_1000FULL:
2758                 *speed = SPEED_1000;
2759                 *duplex = DUPLEX_FULL;
2760                 break;
2761
2762         default:
2763                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2764                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2765                                  SPEED_10;
2766                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2767                                   DUPLEX_HALF;
2768                         break;
2769                 }
2770                 *speed = SPEED_INVALID;
2771                 *duplex = DUPLEX_INVALID;
2772                 break;
2773         }
2774 }
2775
2776 static void tg3_phy_copper_begin(struct tg3 *tp)
2777 {
2778         u32 new_adv;
2779         int i;
2780
2781         if (tp->link_config.phy_is_low_power) {
2782                 /* Entering low power mode.  Disable gigabit and
2783                  * 100baseT advertisements.
2784                  */
2785                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2786
2787                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2788                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2789                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2790                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2791
2792                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2793         } else if (tp->link_config.speed == SPEED_INVALID) {
2794                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2795                         tp->link_config.advertising &=
2796                                 ~(ADVERTISED_1000baseT_Half |
2797                                   ADVERTISED_1000baseT_Full);
2798
2799                 new_adv = ADVERTISE_CSMA;
2800                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2801                         new_adv |= ADVERTISE_10HALF;
2802                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2803                         new_adv |= ADVERTISE_10FULL;
2804                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2805                         new_adv |= ADVERTISE_100HALF;
2806                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2807                         new_adv |= ADVERTISE_100FULL;
2808
2809                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2810
2811                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2812
2813                 if (tp->link_config.advertising &
2814                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2815                         new_adv = 0;
2816                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2817                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2818                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2819                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2820                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2821                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2822                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2823                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2824                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2825                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2826                 } else {
2827                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2828                 }
2829         } else {
2830                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2831                 new_adv |= ADVERTISE_CSMA;
2832
2833                 /* Asking for a specific link mode. */
2834                 if (tp->link_config.speed == SPEED_1000) {
2835                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2836
2837                         if (tp->link_config.duplex == DUPLEX_FULL)
2838                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2839                         else
2840                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2841                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2842                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2843                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2844                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2845                 } else {
2846                         if (tp->link_config.speed == SPEED_100) {
2847                                 if (tp->link_config.duplex == DUPLEX_FULL)
2848                                         new_adv |= ADVERTISE_100FULL;
2849                                 else
2850                                         new_adv |= ADVERTISE_100HALF;
2851                         } else {
2852                                 if (tp->link_config.duplex == DUPLEX_FULL)
2853                                         new_adv |= ADVERTISE_10FULL;
2854                                 else
2855                                         new_adv |= ADVERTISE_10HALF;
2856                         }
2857                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2858
2859                         new_adv = 0;
2860                 }
2861
2862                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2863         }
2864
2865         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2866             tp->link_config.speed != SPEED_INVALID) {
2867                 u32 bmcr, orig_bmcr;
2868
2869                 tp->link_config.active_speed = tp->link_config.speed;
2870                 tp->link_config.active_duplex = tp->link_config.duplex;
2871
2872                 bmcr = 0;
2873                 switch (tp->link_config.speed) {
2874                 default:
2875                 case SPEED_10:
2876                         break;
2877
2878                 case SPEED_100:
2879                         bmcr |= BMCR_SPEED100;
2880                         break;
2881
2882                 case SPEED_1000:
2883                         bmcr |= TG3_BMCR_SPEED1000;
2884                         break;
2885                 }
2886
2887                 if (tp->link_config.duplex == DUPLEX_FULL)
2888                         bmcr |= BMCR_FULLDPLX;
2889
2890                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2891                     (bmcr != orig_bmcr)) {
2892                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2893                         for (i = 0; i < 1500; i++) {
2894                                 u32 tmp;
2895
2896                                 udelay(10);
2897                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2898                                     tg3_readphy(tp, MII_BMSR, &tmp))
2899                                         continue;
2900                                 if (!(tmp & BMSR_LSTATUS)) {
2901                                         udelay(40);
2902                                         break;
2903                                 }
2904                         }
2905                         tg3_writephy(tp, MII_BMCR, bmcr);
2906                         udelay(40);
2907                 }
2908         } else {
2909                 tg3_writephy(tp, MII_BMCR,
2910                              BMCR_ANENABLE | BMCR_ANRESTART);
2911         }
2912 }
2913
2914 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2915 {
2916         int err;
2917
2918         /* Turn off tap power management. */
2919         /* Set Extended packet length bit */
2920         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2921
2922         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2923         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2924
2925         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2926         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2927
2928         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2929         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2930
2931         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2932         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2933
2934         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2935         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2936
2937         udelay(40);
2938
2939         return err;
2940 }
2941
2942 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2943 {
2944         u32 adv_reg, all_mask = 0;
2945
2946         if (mask & ADVERTISED_10baseT_Half)
2947                 all_mask |= ADVERTISE_10HALF;
2948         if (mask & ADVERTISED_10baseT_Full)
2949                 all_mask |= ADVERTISE_10FULL;
2950         if (mask & ADVERTISED_100baseT_Half)
2951                 all_mask |= ADVERTISE_100HALF;
2952         if (mask & ADVERTISED_100baseT_Full)
2953                 all_mask |= ADVERTISE_100FULL;
2954
2955         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2956                 return 0;
2957
2958         if ((adv_reg & all_mask) != all_mask)
2959                 return 0;
2960         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2961                 u32 tg3_ctrl;
2962
2963                 all_mask = 0;
2964                 if (mask & ADVERTISED_1000baseT_Half)
2965                         all_mask |= ADVERTISE_1000HALF;
2966                 if (mask & ADVERTISED_1000baseT_Full)
2967                         all_mask |= ADVERTISE_1000FULL;
2968
2969                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2970                         return 0;
2971
2972                 if ((tg3_ctrl & all_mask) != all_mask)
2973                         return 0;
2974         }
2975         return 1;
2976 }
2977
2978 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2979 {
2980         u32 curadv, reqadv;
2981
2982         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2983                 return 1;
2984
2985         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2986         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2987
2988         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2989                 if (curadv != reqadv)
2990                         return 0;
2991
2992                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2993                         tg3_readphy(tp, MII_LPA, rmtadv);
2994         } else {
2995                 /* Reprogram the advertisement register, even if it
2996                  * does not affect the current link.  If the link
2997                  * gets renegotiated in the future, we can save an
2998                  * additional renegotiation cycle by advertising
2999                  * it correctly in the first place.
3000                  */
3001                 if (curadv != reqadv) {
3002                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3003                                      ADVERTISE_PAUSE_ASYM);
3004                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3005                 }
3006         }
3007
3008         return 1;
3009 }
3010
3011 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3012 {
3013         int current_link_up;
3014         u32 bmsr, dummy;
3015         u32 lcl_adv, rmt_adv;
3016         u16 current_speed;
3017         u8 current_duplex;
3018         int i, err;
3019
3020         tw32(MAC_EVENT, 0);
3021
3022         tw32_f(MAC_STATUS,
3023              (MAC_STATUS_SYNC_CHANGED |
3024               MAC_STATUS_CFG_CHANGED |
3025               MAC_STATUS_MI_COMPLETION |
3026               MAC_STATUS_LNKSTATE_CHANGED));
3027         udelay(40);
3028
3029         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3030                 tw32_f(MAC_MI_MODE,
3031                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3032                 udelay(80);
3033         }
3034
3035         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3036
3037         /* Some third-party PHYs need to be reset on link going
3038          * down.
3039          */
3040         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3041              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3042              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3043             netif_carrier_ok(tp->dev)) {
3044                 tg3_readphy(tp, MII_BMSR, &bmsr);
3045                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3046                     !(bmsr & BMSR_LSTATUS))
3047                         force_reset = 1;
3048         }
3049         if (force_reset)
3050                 tg3_phy_reset(tp);
3051
3052         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3053                 tg3_readphy(tp, MII_BMSR, &bmsr);
3054                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3055                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3056                         bmsr = 0;
3057
3058                 if (!(bmsr & BMSR_LSTATUS)) {
3059                         err = tg3_init_5401phy_dsp(tp);
3060                         if (err)
3061                                 return err;
3062
3063                         tg3_readphy(tp, MII_BMSR, &bmsr);
3064                         for (i = 0; i < 1000; i++) {
3065                                 udelay(10);
3066                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067                                     (bmsr & BMSR_LSTATUS)) {
3068                                         udelay(40);
3069                                         break;
3070                                 }
3071                         }
3072
3073                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3074                             !(bmsr & BMSR_LSTATUS) &&
3075                             tp->link_config.active_speed == SPEED_1000) {
3076                                 err = tg3_phy_reset(tp);
3077                                 if (!err)
3078                                         err = tg3_init_5401phy_dsp(tp);
3079                                 if (err)
3080                                         return err;
3081                         }
3082                 }
3083         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3084                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3085                 /* 5701 {A0,B0} CRC bug workaround */
3086                 tg3_writephy(tp, 0x15, 0x0a75);
3087                 tg3_writephy(tp, 0x1c, 0x8c68);
3088                 tg3_writephy(tp, 0x1c, 0x8d68);
3089                 tg3_writephy(tp, 0x1c, 0x8c68);
3090         }
3091
3092         /* Clear pending interrupts... */
3093         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3094         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3095
3096         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3097                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3098         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3099                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3100
3101         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3102             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3103                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3104                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3105                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3106                 else
3107                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3108         }
3109
3110         current_link_up = 0;
3111         current_speed = SPEED_INVALID;
3112         current_duplex = DUPLEX_INVALID;
3113
3114         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3115                 u32 val;
3116
3117                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119                 if (!(val & (1 << 10))) {
3120                         val |= (1 << 10);
3121                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3122                         goto relink;
3123                 }
3124         }
3125
3126         bmsr = 0;
3127         for (i = 0; i < 100; i++) {
3128                 tg3_readphy(tp, MII_BMSR, &bmsr);
3129                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130                     (bmsr & BMSR_LSTATUS))
3131                         break;
3132                 udelay(40);
3133         }
3134
3135         if (bmsr & BMSR_LSTATUS) {
3136                 u32 aux_stat, bmcr;
3137
3138                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139                 for (i = 0; i < 2000; i++) {
3140                         udelay(10);
3141                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3142                             aux_stat)
3143                                 break;
3144                 }
3145
3146                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3147                                              &current_speed,
3148                                              &current_duplex);
3149
3150                 bmcr = 0;
3151                 for (i = 0; i < 200; i++) {
3152                         tg3_readphy(tp, MII_BMCR, &bmcr);
3153                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3154                                 continue;
3155                         if (bmcr && bmcr != 0x7fff)
3156                                 break;
3157                         udelay(10);
3158                 }
3159
3160                 lcl_adv = 0;
3161                 rmt_adv = 0;
3162
3163                 tp->link_config.active_speed = current_speed;
3164                 tp->link_config.active_duplex = current_duplex;
3165
3166                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167                         if ((bmcr & BMCR_ANENABLE) &&
3168                             tg3_copper_is_advertising_all(tp,
3169                                                 tp->link_config.advertising)) {
3170                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3171                                                                   &rmt_adv))
3172                                         current_link_up = 1;
3173                         }
3174                 } else {
3175                         if (!(bmcr & BMCR_ANENABLE) &&
3176                             tp->link_config.speed == current_speed &&
3177                             tp->link_config.duplex == current_duplex &&
3178                             tp->link_config.flowctrl ==
3179                             tp->link_config.active_flowctrl) {
3180                                 current_link_up = 1;
3181                         }
3182                 }
3183
3184                 if (current_link_up == 1 &&
3185                     tp->link_config.active_duplex == DUPLEX_FULL)
3186                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3187         }
3188
3189 relink:
3190         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3191                 u32 tmp;
3192
3193                 tg3_phy_copper_begin(tp);
3194
3195                 tg3_readphy(tp, MII_BMSR, &tmp);
3196                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3197                     (tmp & BMSR_LSTATUS))
3198                         current_link_up = 1;
3199         }
3200
3201         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3202         if (current_link_up == 1) {
3203                 if (tp->link_config.active_speed == SPEED_100 ||
3204                     tp->link_config.active_speed == SPEED_10)
3205                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3206                 else
3207                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3208         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3209                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3210         else
3211                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3212
3213         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3214         if (tp->link_config.active_duplex == DUPLEX_HALF)
3215                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3216
3217         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3218                 if (current_link_up == 1 &&
3219                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3220                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3221                 else
3222                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3223         }
3224
3225         /* ??? Without this setting Netgear GA302T PHY does not
3226          * ??? send/receive packets...
3227          */
3228         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3229             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3230                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3231                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3232                 udelay(80);
3233         }
3234
3235         tw32_f(MAC_MODE, tp->mac_mode);
3236         udelay(40);
3237
3238         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3239                 /* Polled via timer. */
3240                 tw32_f(MAC_EVENT, 0);
3241         } else {
3242                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3243         }
3244         udelay(40);
3245
3246         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3247             current_link_up == 1 &&
3248             tp->link_config.active_speed == SPEED_1000 &&
3249             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3250              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3251                 udelay(120);
3252                 tw32_f(MAC_STATUS,
3253                      (MAC_STATUS_SYNC_CHANGED |
3254                       MAC_STATUS_CFG_CHANGED));
3255                 udelay(40);
3256                 tg3_write_mem(tp,
3257                               NIC_SRAM_FIRMWARE_MBOX,
3258                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3259         }
3260
3261         /* Prevent send BD corruption. */
3262         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3263                 u16 oldlnkctl, newlnkctl;
3264
3265                 pci_read_config_word(tp->pdev,
3266                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3267                                      &oldlnkctl);
3268                 if (tp->link_config.active_speed == SPEED_100 ||
3269                     tp->link_config.active_speed == SPEED_10)
3270                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3271                 else
3272                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3273                 if (newlnkctl != oldlnkctl)
3274                         pci_write_config_word(tp->pdev,
3275                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3276                                               newlnkctl);
3277         }
3278
3279         if (current_link_up != netif_carrier_ok(tp->dev)) {
3280                 if (current_link_up)
3281                         netif_carrier_on(tp->dev);
3282                 else
3283                         netif_carrier_off(tp->dev);
3284                 tg3_link_report(tp);
3285         }
3286
3287         return 0;
3288 }
3289
3290 struct tg3_fiber_aneginfo {
3291         int state;
3292 #define ANEG_STATE_UNKNOWN              0
3293 #define ANEG_STATE_AN_ENABLE            1
3294 #define ANEG_STATE_RESTART_INIT         2
3295 #define ANEG_STATE_RESTART              3
3296 #define ANEG_STATE_DISABLE_LINK_OK      4
3297 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3298 #define ANEG_STATE_ABILITY_DETECT       6
3299 #define ANEG_STATE_ACK_DETECT_INIT      7
3300 #define ANEG_STATE_ACK_DETECT           8
3301 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3302 #define ANEG_STATE_COMPLETE_ACK         10
3303 #define ANEG_STATE_IDLE_DETECT_INIT     11
3304 #define ANEG_STATE_IDLE_DETECT          12
3305 #define ANEG_STATE_LINK_OK              13
3306 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3307 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3308
3309         u32 flags;
3310 #define MR_AN_ENABLE            0x00000001
3311 #define MR_RESTART_AN           0x00000002
3312 #define MR_AN_COMPLETE          0x00000004
3313 #define MR_PAGE_RX              0x00000008
3314 #define MR_NP_LOADED            0x00000010
3315 #define MR_TOGGLE_TX            0x00000020
3316 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3317 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3318 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3319 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3320 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3321 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3322 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3323 #define MR_TOGGLE_RX            0x00002000
3324 #define MR_NP_RX                0x00004000
3325
3326 #define MR_LINK_OK              0x80000000
3327
3328         unsigned long link_time, cur_time;
3329
3330         u32 ability_match_cfg;
3331         int ability_match_count;
3332
3333         char ability_match, idle_match, ack_match;
3334
3335         u32 txconfig, rxconfig;
3336 #define ANEG_CFG_NP             0x00000080
3337 #define ANEG_CFG_ACK            0x00000040
3338 #define ANEG_CFG_RF2            0x00000020
3339 #define ANEG_CFG_RF1            0x00000010
3340 #define ANEG_CFG_PS2            0x00000001
3341 #define ANEG_CFG_PS1            0x00008000
3342 #define ANEG_CFG_HD             0x00004000
3343 #define ANEG_CFG_FD             0x00002000
3344 #define ANEG_CFG_INVAL          0x00001f06
3345
3346 };
3347 #define ANEG_OK         0
3348 #define ANEG_DONE       1
3349 #define ANEG_TIMER_ENAB 2
3350 #define ANEG_FAILED     -1
3351
3352 #define ANEG_STATE_SETTLE_TIME  10000
3353
3354 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3355                                    struct tg3_fiber_aneginfo *ap)
3356 {
3357         u16 flowctrl;
3358         unsigned long delta;
3359         u32 rx_cfg_reg;
3360         int ret;
3361
3362         if (ap->state == ANEG_STATE_UNKNOWN) {
3363                 ap->rxconfig = 0;
3364                 ap->link_time = 0;
3365                 ap->cur_time = 0;
3366                 ap->ability_match_cfg = 0;
3367                 ap->ability_match_count = 0;
3368                 ap->ability_match = 0;
3369                 ap->idle_match = 0;
3370                 ap->ack_match = 0;
3371         }
3372         ap->cur_time++;
3373
3374         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3375                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3376
3377                 if (rx_cfg_reg != ap->ability_match_cfg) {
3378                         ap->ability_match_cfg = rx_cfg_reg;
3379                         ap->ability_match = 0;
3380                         ap->ability_match_count = 0;
3381                 } else {
3382                         if (++ap->ability_match_count > 1) {
3383                                 ap->ability_match = 1;
3384                                 ap->ability_match_cfg = rx_cfg_reg;
3385                         }
3386                 }
3387                 if (rx_cfg_reg & ANEG_CFG_ACK)
3388                         ap->ack_match = 1;
3389                 else
3390                         ap->ack_match = 0;
3391
3392                 ap->idle_match = 0;
3393         } else {
3394                 ap->idle_match = 1;
3395                 ap->ability_match_cfg = 0;
3396                 ap->ability_match_count = 0;
3397                 ap->ability_match = 0;
3398                 ap->ack_match = 0;
3399
3400                 rx_cfg_reg = 0;
3401         }
3402
3403         ap->rxconfig = rx_cfg_reg;
3404         ret = ANEG_OK;
3405
3406         switch(ap->state) {
3407         case ANEG_STATE_UNKNOWN:
3408                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3409                         ap->state = ANEG_STATE_AN_ENABLE;
3410
3411                 /* fallthru */
3412         case ANEG_STATE_AN_ENABLE:
3413                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3414                 if (ap->flags & MR_AN_ENABLE) {
3415                         ap->link_time = 0;
3416                         ap->cur_time = 0;
3417                         ap->ability_match_cfg = 0;
3418                         ap->ability_match_count = 0;
3419                         ap->ability_match = 0;
3420                         ap->idle_match = 0;
3421                         ap->ack_match = 0;
3422
3423                         ap->state = ANEG_STATE_RESTART_INIT;
3424                 } else {
3425                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3426                 }
3427                 break;
3428
3429         case ANEG_STATE_RESTART_INIT:
3430                 ap->link_time = ap->cur_time;
3431                 ap->flags &= ~(MR_NP_LOADED);
3432                 ap->txconfig = 0;
3433                 tw32(MAC_TX_AUTO_NEG, 0);
3434                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3435                 tw32_f(MAC_MODE, tp->mac_mode);
3436                 udelay(40);
3437
3438                 ret = ANEG_TIMER_ENAB;
3439                 ap->state = ANEG_STATE_RESTART;
3440
3441                 /* fallthru */
3442         case ANEG_STATE_RESTART:
3443                 delta = ap->cur_time - ap->link_time;
3444                 if (delta > ANEG_STATE_SETTLE_TIME) {
3445                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3446                 } else {
3447                         ret = ANEG_TIMER_ENAB;
3448                 }
3449                 break;
3450
3451         case ANEG_STATE_DISABLE_LINK_OK:
3452                 ret = ANEG_DONE;
3453                 break;
3454
3455         case ANEG_STATE_ABILITY_DETECT_INIT:
3456                 ap->flags &= ~(MR_TOGGLE_TX);
3457                 ap->txconfig = ANEG_CFG_FD;
3458                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3459                 if (flowctrl & ADVERTISE_1000XPAUSE)
3460                         ap->txconfig |= ANEG_CFG_PS1;
3461                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3462                         ap->txconfig |= ANEG_CFG_PS2;
3463                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3464                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3465                 tw32_f(MAC_MODE, tp->mac_mode);
3466                 udelay(40);
3467
3468                 ap->state = ANEG_STATE_ABILITY_DETECT;
3469                 break;
3470
3471         case ANEG_STATE_ABILITY_DETECT:
3472                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3473                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3474                 }
3475                 break;
3476
3477         case ANEG_STATE_ACK_DETECT_INIT:
3478                 ap->txconfig |= ANEG_CFG_ACK;
3479                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3480                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3481                 tw32_f(MAC_MODE, tp->mac_mode);
3482                 udelay(40);
3483
3484                 ap->state = ANEG_STATE_ACK_DETECT;
3485
3486                 /* fallthru */
3487         case ANEG_STATE_ACK_DETECT:
3488                 if (ap->ack_match != 0) {
3489                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3490                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3491                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3492                         } else {
3493                                 ap->state = ANEG_STATE_AN_ENABLE;
3494                         }
3495                 } else if (ap->ability_match != 0 &&
3496                            ap->rxconfig == 0) {
3497                         ap->state = ANEG_STATE_AN_ENABLE;
3498                 }
3499                 break;
3500
3501         case ANEG_STATE_COMPLETE_ACK_INIT:
3502                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3503                         ret = ANEG_FAILED;
3504                         break;
3505                 }
3506                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3507                                MR_LP_ADV_HALF_DUPLEX |
3508                                MR_LP_ADV_SYM_PAUSE |
3509                                MR_LP_ADV_ASYM_PAUSE |
3510                                MR_LP_ADV_REMOTE_FAULT1 |
3511                                MR_LP_ADV_REMOTE_FAULT2 |
3512                                MR_LP_ADV_NEXT_PAGE |
3513                                MR_TOGGLE_RX |
3514                                MR_NP_RX);
3515                 if (ap->rxconfig & ANEG_CFG_FD)
3516                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3517                 if (ap->rxconfig & ANEG_CFG_HD)
3518                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3519                 if (ap->rxconfig & ANEG_CFG_PS1)
3520                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3521                 if (ap->rxconfig & ANEG_CFG_PS2)
3522                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3523                 if (ap->rxconfig & ANEG_CFG_RF1)
3524                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3525                 if (ap->rxconfig & ANEG_CFG_RF2)
3526                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3527                 if (ap->rxconfig & ANEG_CFG_NP)
3528                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3529
3530                 ap->link_time = ap->cur_time;
3531
3532                 ap->flags ^= (MR_TOGGLE_TX);
3533                 if (ap->rxconfig & 0x0008)
3534                         ap->flags |= MR_TOGGLE_RX;
3535                 if (ap->rxconfig & ANEG_CFG_NP)
3536                         ap->flags |= MR_NP_RX;
3537                 ap->flags |= MR_PAGE_RX;
3538
3539                 ap->state = ANEG_STATE_COMPLETE_ACK;
3540                 ret = ANEG_TIMER_ENAB;
3541                 break;
3542
3543         case ANEG_STATE_COMPLETE_ACK:
3544                 if (ap->ability_match != 0 &&
3545                     ap->rxconfig == 0) {
3546                         ap->state = ANEG_STATE_AN_ENABLE;
3547                         break;
3548                 }
3549                 delta = ap->cur_time - ap->link_time;
3550                 if (delta > ANEG_STATE_SETTLE_TIME) {
3551                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3552                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553                         } else {
3554                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3555                                     !(ap->flags & MR_NP_RX)) {
3556                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3557                                 } else {
3558                                         ret = ANEG_FAILED;
3559                                 }
3560                         }
3561                 }
3562                 break;
3563
3564         case ANEG_STATE_IDLE_DETECT_INIT:
3565                 ap->link_time = ap->cur_time;
3566                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3567                 tw32_f(MAC_MODE, tp->mac_mode);
3568                 udelay(40);
3569
3570                 ap->state = ANEG_STATE_IDLE_DETECT;
3571                 ret = ANEG_TIMER_ENAB;
3572                 break;
3573
3574         case ANEG_STATE_IDLE_DETECT:
3575                 if (ap->ability_match != 0 &&
3576                     ap->rxconfig == 0) {
3577                         ap->state = ANEG_STATE_AN_ENABLE;
3578                         break;
3579                 }
3580                 delta = ap->cur_time - ap->link_time;
3581                 if (delta > ANEG_STATE_SETTLE_TIME) {
3582                         /* XXX another gem from the Broadcom driver :( */
3583                         ap->state = ANEG_STATE_LINK_OK;
3584                 }
3585                 break;
3586
3587         case ANEG_STATE_LINK_OK:
3588                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3589                 ret = ANEG_DONE;
3590                 break;
3591
3592         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3593                 /* ??? unimplemented */
3594                 break;
3595
3596         case ANEG_STATE_NEXT_PAGE_WAIT:
3597                 /* ??? unimplemented */
3598                 break;
3599
3600         default:
3601                 ret = ANEG_FAILED;
3602                 break;
3603         }
3604
3605         return ret;
3606 }
3607
3608 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3609 {
3610         int res = 0;
3611         struct tg3_fiber_aneginfo aninfo;
3612         int status = ANEG_FAILED;
3613         unsigned int tick;
3614         u32 tmp;
3615
3616         tw32_f(MAC_TX_AUTO_NEG, 0);
3617
3618         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3619         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3620         udelay(40);
3621
3622         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3623         udelay(40);
3624
3625         memset(&aninfo, 0, sizeof(aninfo));
3626         aninfo.flags |= MR_AN_ENABLE;
3627         aninfo.state = ANEG_STATE_UNKNOWN;
3628         aninfo.cur_time = 0;
3629         tick = 0;
3630         while (++tick < 195000) {
3631                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3632                 if (status == ANEG_DONE || status == ANEG_FAILED)
3633                         break;
3634
3635                 udelay(1);
3636         }
3637
3638         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3639         tw32_f(MAC_MODE, tp->mac_mode);
3640         udelay(40);
3641
3642         *txflags = aninfo.txconfig;
3643         *rxflags = aninfo.flags;
3644
3645         if (status == ANEG_DONE &&
3646             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3647                              MR_LP_ADV_FULL_DUPLEX)))
3648                 res = 1;
3649
3650         return res;
3651 }
3652
3653 static void tg3_init_bcm8002(struct tg3 *tp)
3654 {
3655         u32 mac_status = tr32(MAC_STATUS);
3656         int i;
3657
3658         /* Reset when initting first time or we have a link. */
3659         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3660             !(mac_status & MAC_STATUS_PCS_SYNCED))
3661                 return;
3662
3663         /* Set PLL lock range. */
3664         tg3_writephy(tp, 0x16, 0x8007);
3665
3666         /* SW reset */
3667         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3668
3669         /* Wait for reset to complete. */
3670         /* XXX schedule_timeout() ... */
3671         for (i = 0; i < 500; i++)
3672                 udelay(10);
3673
3674         /* Config mode; select PMA/Ch 1 regs. */
3675         tg3_writephy(tp, 0x10, 0x8411);
3676
3677         /* Enable auto-lock and comdet, select txclk for tx. */
3678         tg3_writephy(tp, 0x11, 0x0a10);
3679
3680         tg3_writephy(tp, 0x18, 0x00a0);
3681         tg3_writephy(tp, 0x16, 0x41ff);
3682
3683         /* Assert and deassert POR. */
3684         tg3_writephy(tp, 0x13, 0x0400);
3685         udelay(40);
3686         tg3_writephy(tp, 0x13, 0x0000);
3687
3688         tg3_writephy(tp, 0x11, 0x0a50);
3689         udelay(40);
3690         tg3_writephy(tp, 0x11, 0x0a10);
3691
3692         /* Wait for signal to stabilize */
3693         /* XXX schedule_timeout() ... */
3694         for (i = 0; i < 15000; i++)
3695                 udelay(10);
3696
3697         /* Deselect the channel register so we can read the PHYID
3698          * later.
3699          */
3700         tg3_writephy(tp, 0x10, 0x8011);
3701 }
3702
3703 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3704 {
3705         u16 flowctrl;
3706         u32 sg_dig_ctrl, sg_dig_status;
3707         u32 serdes_cfg, expected_sg_dig_ctrl;
3708         int workaround, port_a;
3709         int current_link_up;
3710
3711         serdes_cfg = 0;
3712         expected_sg_dig_ctrl = 0;
3713         workaround = 0;
3714         port_a = 1;
3715         current_link_up = 0;
3716
3717         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3718             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3719                 workaround = 1;
3720                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3721                         port_a = 0;
3722
3723                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3724                 /* preserve bits 20-23 for voltage regulator */
3725                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3726         }
3727
3728         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3729
3730         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3731                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3732                         if (workaround) {
3733                                 u32 val = serdes_cfg;
3734
3735                                 if (port_a)
3736                                         val |= 0xc010000;
3737                                 else
3738                                         val |= 0x4010000;
3739                                 tw32_f(MAC_SERDES_CFG, val);
3740                         }
3741
3742                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3743                 }
3744                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3745                         tg3_setup_flow_control(tp, 0, 0);
3746                         current_link_up = 1;
3747                 }
3748                 goto out;
3749         }
3750
3751         /* Want auto-negotiation.  */
3752         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3753
3754         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3755         if (flowctrl & ADVERTISE_1000XPAUSE)
3756                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3757         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3758                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3759
3760         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3761                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3762                     tp->serdes_counter &&
3763                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3764                                     MAC_STATUS_RCVD_CFG)) ==
3765                      MAC_STATUS_PCS_SYNCED)) {
3766                         tp->serdes_counter--;
3767                         current_link_up = 1;
3768                         goto out;
3769                 }
3770 restart_autoneg:
3771                 if (workaround)
3772                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3773                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3774                 udelay(5);
3775                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3776
3777                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3778                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3779         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3780                                  MAC_STATUS_SIGNAL_DET)) {
3781                 sg_dig_status = tr32(SG_DIG_STATUS);
3782                 mac_status = tr32(MAC_STATUS);
3783
3784                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3785                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3786                         u32 local_adv = 0, remote_adv = 0;
3787
3788                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3789                                 local_adv |= ADVERTISE_1000XPAUSE;
3790                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3791                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3792
3793                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3794                                 remote_adv |= LPA_1000XPAUSE;
3795                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3796                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3797
3798                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3799                         current_link_up = 1;
3800                         tp->serdes_counter = 0;
3801                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3802                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3803                         if (tp->serdes_counter)
3804                                 tp->serdes_counter--;
3805                         else {
3806                                 if (workaround) {
3807                                         u32 val = serdes_cfg;
3808
3809                                         if (port_a)
3810                                                 val |= 0xc010000;
3811                                         else
3812                                                 val |= 0x4010000;
3813
3814                                         tw32_f(MAC_SERDES_CFG, val);
3815                                 }
3816
3817                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3818                                 udelay(40);
3819
3820                                 /* Link parallel detection - link is up */
3821                                 /* only if we have PCS_SYNC and not */
3822                                 /* receiving config code words */
3823                                 mac_status = tr32(MAC_STATUS);
3824                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3825                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3826                                         tg3_setup_flow_control(tp, 0, 0);
3827                                         current_link_up = 1;
3828                                         tp->tg3_flags2 |=
3829                                                 TG3_FLG2_PARALLEL_DETECT;
3830                                         tp->serdes_counter =
3831                                                 SERDES_PARALLEL_DET_TIMEOUT;
3832                                 } else
3833                                         goto restart_autoneg;
3834                         }
3835                 }
3836         } else {
3837                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3838                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3839         }
3840
3841 out:
3842         return current_link_up;
3843 }
3844
3845 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3846 {
3847         int current_link_up = 0;
3848
3849         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3850                 goto out;
3851
3852         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3853                 u32 txflags, rxflags;
3854                 int i;
3855
3856                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3857                         u32 local_adv = 0, remote_adv = 0;
3858
3859                         if (txflags & ANEG_CFG_PS1)
3860                                 local_adv |= ADVERTISE_1000XPAUSE;
3861                         if (txflags & ANEG_CFG_PS2)
3862                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3863
3864                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3865                                 remote_adv |= LPA_1000XPAUSE;
3866                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3867                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3868
3869                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3870
3871                         current_link_up = 1;
3872                 }
3873                 for (i = 0; i < 30; i++) {
3874                         udelay(20);
3875                         tw32_f(MAC_STATUS,
3876                                (MAC_STATUS_SYNC_CHANGED |
3877                                 MAC_STATUS_CFG_CHANGED));
3878                         udelay(40);
3879                         if ((tr32(MAC_STATUS) &
3880                              (MAC_STATUS_SYNC_CHANGED |
3881                               MAC_STATUS_CFG_CHANGED)) == 0)
3882                                 break;
3883                 }
3884
3885                 mac_status = tr32(MAC_STATUS);
3886                 if (current_link_up == 0 &&
3887                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3888                     !(mac_status & MAC_STATUS_RCVD_CFG))
3889                         current_link_up = 1;
3890         } else {
3891                 tg3_setup_flow_control(tp, 0, 0);
3892
3893                 /* Forcing 1000FD link up. */
3894                 current_link_up = 1;
3895
3896                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3897                 udelay(40);
3898
3899                 tw32_f(MAC_MODE, tp->mac_mode);
3900                 udelay(40);
3901         }
3902
3903 out:
3904         return current_link_up;
3905 }
3906
3907 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3908 {
3909         u32 orig_pause_cfg;
3910         u16 orig_active_speed;
3911         u8 orig_active_duplex;
3912         u32 mac_status;
3913         int current_link_up;
3914         int i;
3915
3916         orig_pause_cfg = tp->link_config.active_flowctrl;
3917         orig_active_speed = tp->link_config.active_speed;
3918         orig_active_duplex = tp->link_config.active_duplex;
3919
3920         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3921             netif_carrier_ok(tp->dev) &&
3922             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3923                 mac_status = tr32(MAC_STATUS);
3924                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3925                                MAC_STATUS_SIGNAL_DET |
3926                                MAC_STATUS_CFG_CHANGED |
3927                                MAC_STATUS_RCVD_CFG);
3928                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3929                                    MAC_STATUS_SIGNAL_DET)) {
3930                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3931                                             MAC_STATUS_CFG_CHANGED));
3932                         return 0;
3933                 }
3934         }
3935
3936         tw32_f(MAC_TX_AUTO_NEG, 0);
3937
3938         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3939         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3940         tw32_f(MAC_MODE, tp->mac_mode);
3941         udelay(40);
3942
3943         if (tp->phy_id == PHY_ID_BCM8002)
3944                 tg3_init_bcm8002(tp);
3945
3946         /* Enable link change event even when serdes polling.  */
3947         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3948         udelay(40);
3949
3950         current_link_up = 0;
3951         mac_status = tr32(MAC_STATUS);
3952
3953         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3954                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3955         else
3956                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3957
3958         tp->napi[0].hw_status->status =
3959                 (SD_STATUS_UPDATED |
3960                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3961
3962         for (i = 0; i < 100; i++) {
3963                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3964                                     MAC_STATUS_CFG_CHANGED));
3965                 udelay(5);
3966                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3967                                          MAC_STATUS_CFG_CHANGED |
3968                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3969                         break;
3970         }
3971
3972         mac_status = tr32(MAC_STATUS);
3973         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3974                 current_link_up = 0;
3975                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3976                     tp->serdes_counter == 0) {
3977                         tw32_f(MAC_MODE, (tp->mac_mode |
3978                                           MAC_MODE_SEND_CONFIGS));
3979                         udelay(1);
3980                         tw32_f(MAC_MODE, tp->mac_mode);
3981                 }
3982         }
3983
3984         if (current_link_up == 1) {
3985                 tp->link_config.active_speed = SPEED_1000;
3986                 tp->link_config.active_duplex = DUPLEX_FULL;
3987                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3988                                     LED_CTRL_LNKLED_OVERRIDE |
3989                                     LED_CTRL_1000MBPS_ON));
3990         } else {
3991                 tp->link_config.active_speed = SPEED_INVALID;
3992                 tp->link_config.active_duplex = DUPLEX_INVALID;
3993                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3994                                     LED_CTRL_LNKLED_OVERRIDE |
3995                                     LED_CTRL_TRAFFIC_OVERRIDE));
3996         }
3997
3998         if (current_link_up != netif_carrier_ok(tp->dev)) {
3999                 if (current_link_up)
4000                         netif_carrier_on(tp->dev);
4001                 else
4002                         netif_carrier_off(tp->dev);
4003                 tg3_link_report(tp);
4004         } else {
4005                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4006                 if (orig_pause_cfg != now_pause_cfg ||
4007                     orig_active_speed != tp->link_config.active_speed ||
4008                     orig_active_duplex != tp->link_config.active_duplex)
4009                         tg3_link_report(tp);
4010         }
4011
4012         return 0;
4013 }
4014
4015 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4016 {
4017         int current_link_up, err = 0;
4018         u32 bmsr, bmcr;
4019         u16 current_speed;
4020         u8 current_duplex;
4021         u32 local_adv, remote_adv;
4022
4023         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4024         tw32_f(MAC_MODE, tp->mac_mode);
4025         udelay(40);
4026
4027         tw32(MAC_EVENT, 0);
4028
4029         tw32_f(MAC_STATUS,
4030              (MAC_STATUS_SYNC_CHANGED |
4031               MAC_STATUS_CFG_CHANGED |
4032               MAC_STATUS_MI_COMPLETION |
4033               MAC_STATUS_LNKSTATE_CHANGED));
4034         udelay(40);
4035
4036         if (force_reset)
4037                 tg3_phy_reset(tp);
4038
4039         current_link_up = 0;
4040         current_speed = SPEED_INVALID;
4041         current_duplex = DUPLEX_INVALID;
4042
4043         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4044         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4045         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4046                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4047                         bmsr |= BMSR_LSTATUS;
4048                 else
4049                         bmsr &= ~BMSR_LSTATUS;
4050         }
4051
4052         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4053
4054         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4055             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4056                 /* do nothing, just check for link up at the end */
4057         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4058                 u32 adv, new_adv;
4059
4060                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4061                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4062                                   ADVERTISE_1000XPAUSE |
4063                                   ADVERTISE_1000XPSE_ASYM |
4064                                   ADVERTISE_SLCT);
4065
4066                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4067
4068                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4069                         new_adv |= ADVERTISE_1000XHALF;
4070                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4071                         new_adv |= ADVERTISE_1000XFULL;
4072
4073                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4074                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4075                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4076                         tg3_writephy(tp, MII_BMCR, bmcr);
4077
4078                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4079                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4080                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4081
4082                         return err;
4083                 }
4084         } else {
4085                 u32 new_bmcr;
4086
4087                 bmcr &= ~BMCR_SPEED1000;
4088                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4089
4090                 if (tp->link_config.duplex == DUPLEX_FULL)
4091                         new_bmcr |= BMCR_FULLDPLX;
4092
4093                 if (new_bmcr != bmcr) {
4094                         /* BMCR_SPEED1000 is a reserved bit that needs
4095                          * to be set on write.
4096                          */
4097                         new_bmcr |= BMCR_SPEED1000;
4098
4099                         /* Force a linkdown */
4100                         if (netif_carrier_ok(tp->dev)) {
4101                                 u32 adv;
4102
4103                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4104                                 adv &= ~(ADVERTISE_1000XFULL |
4105                                          ADVERTISE_1000XHALF |
4106                                          ADVERTISE_SLCT);
4107                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4108                                 tg3_writephy(tp, MII_BMCR, bmcr |
4109                                                            BMCR_ANRESTART |
4110                                                            BMCR_ANENABLE);
4111                                 udelay(10);
4112                                 netif_carrier_off(tp->dev);
4113                         }
4114                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4115                         bmcr = new_bmcr;
4116                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4117                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4118                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4119                             ASIC_REV_5714) {
4120                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4121                                         bmsr |= BMSR_LSTATUS;
4122                                 else
4123                                         bmsr &= ~BMSR_LSTATUS;
4124                         }
4125                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126                 }
4127         }
4128
4129         if (bmsr & BMSR_LSTATUS) {
4130                 current_speed = SPEED_1000;
4131                 current_link_up = 1;
4132                 if (bmcr & BMCR_FULLDPLX)
4133                         current_duplex = DUPLEX_FULL;
4134                 else
4135                         current_duplex = DUPLEX_HALF;
4136
4137                 local_adv = 0;
4138                 remote_adv = 0;
4139
4140                 if (bmcr & BMCR_ANENABLE) {
4141                         u32 common;
4142
4143                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4144                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4145                         common = local_adv & remote_adv;
4146                         if (common & (ADVERTISE_1000XHALF |
4147                                       ADVERTISE_1000XFULL)) {
4148                                 if (common & ADVERTISE_1000XFULL)
4149                                         current_duplex = DUPLEX_FULL;
4150                                 else
4151                                         current_duplex = DUPLEX_HALF;
4152                         }
4153                         else
4154                                 current_link_up = 0;
4155                 }
4156         }
4157
4158         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4159                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4160
4161         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4162         if (tp->link_config.active_duplex == DUPLEX_HALF)
4163                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4164
4165         tw32_f(MAC_MODE, tp->mac_mode);
4166         udelay(40);
4167
4168         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4169
4170         tp->link_config.active_speed = current_speed;
4171         tp->link_config.active_duplex = current_duplex;
4172
4173         if (current_link_up != netif_carrier_ok(tp->dev)) {
4174                 if (current_link_up)
4175                         netif_carrier_on(tp->dev);
4176                 else {
4177                         netif_carrier_off(tp->dev);
4178                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4179                 }
4180                 tg3_link_report(tp);
4181         }
4182         return err;
4183 }
4184
4185 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4186 {
4187         if (tp->serdes_counter) {
4188                 /* Give autoneg time to complete. */
4189                 tp->serdes_counter--;
4190                 return;
4191         }
4192         if (!netif_carrier_ok(tp->dev) &&
4193             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4194                 u32 bmcr;
4195
4196                 tg3_readphy(tp, MII_BMCR, &bmcr);
4197                 if (bmcr & BMCR_ANENABLE) {
4198                         u32 phy1, phy2;
4199
4200                         /* Select shadow register 0x1f */
4201                         tg3_writephy(tp, 0x1c, 0x7c00);
4202                         tg3_readphy(tp, 0x1c, &phy1);
4203
4204                         /* Select expansion interrupt status register */
4205                         tg3_writephy(tp, 0x17, 0x0f01);
4206                         tg3_readphy(tp, 0x15, &phy2);
4207                         tg3_readphy(tp, 0x15, &phy2);
4208
4209                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210                                 /* We have signal detect and not receiving
4211                                  * config code words, link is up by parallel
4212                                  * detection.
4213                                  */
4214
4215                                 bmcr &= ~BMCR_ANENABLE;
4216                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217                                 tg3_writephy(tp, MII_BMCR, bmcr);
4218                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4219                         }
4220                 }
4221         }
4222         else if (netif_carrier_ok(tp->dev) &&
4223                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4224                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4225                 u32 phy2;
4226
4227                 /* Select expansion interrupt status register */
4228                 tg3_writephy(tp, 0x17, 0x0f01);
4229                 tg3_readphy(tp, 0x15, &phy2);
4230                 if (phy2 & 0x20) {
4231                         u32 bmcr;
4232
4233                         /* Config code words received, turn on autoneg. */
4234                         tg3_readphy(tp, MII_BMCR, &bmcr);
4235                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4236
4237                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4238
4239                 }
4240         }
4241 }
4242
4243 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4244 {
4245         int err;
4246
4247         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4248                 err = tg3_setup_fiber_phy(tp, force_reset);
4249         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4250                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4251         } else {
4252                 err = tg3_setup_copper_phy(tp, force_reset);
4253         }
4254
4255         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4256                 u32 val, scale;
4257
4258                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4259                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4260                         scale = 65;
4261                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4262                         scale = 6;
4263                 else
4264                         scale = 12;
4265
4266                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4267                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4268                 tw32(GRC_MISC_CFG, val);
4269         }
4270
4271         if (tp->link_config.active_speed == SPEED_1000 &&
4272             tp->link_config.active_duplex == DUPLEX_HALF)
4273                 tw32(MAC_TX_LENGTHS,
4274                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275                       (6 << TX_LENGTHS_IPG_SHIFT) |
4276                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277         else
4278                 tw32(MAC_TX_LENGTHS,
4279                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4280                       (6 << TX_LENGTHS_IPG_SHIFT) |
4281                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4282
4283         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4284                 if (netif_carrier_ok(tp->dev)) {
4285                         tw32(HOSTCC_STAT_COAL_TICKS,
4286                              tp->coal.stats_block_coalesce_usecs);
4287                 } else {
4288                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4289                 }
4290         }
4291
4292         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4293                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4294                 if (!netif_carrier_ok(tp->dev))
4295                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4296                               tp->pwrmgmt_thresh;
4297                 else
4298                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4299                 tw32(PCIE_PWR_MGMT_THRESH, val);
4300         }
4301
4302         return err;
4303 }
4304
4305 /* This is called whenever we suspect that the system chipset is re-
4306  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4307  * is bogus tx completions. We try to recover by setting the
4308  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4309  * in the workqueue.
4310  */
4311 static void tg3_tx_recover(struct tg3 *tp)
4312 {
4313         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4314                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4315
4316         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4317                "mapped I/O cycles to the network device, attempting to "
4318                "recover. Please report the problem to the driver maintainer "
4319                "and include system chipset information.\n", tp->dev->name);
4320
4321         spin_lock(&tp->lock);
4322         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4323         spin_unlock(&tp->lock);
4324 }
4325
4326 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4327 {
4328         smp_mb();
4329         return tnapi->tx_pending -
4330                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4331 }
4332
4333 /* Tigon3 never reports partial packet sends.  So we do not
4334  * need special logic to handle SKBs that have not had all
4335  * of their frags sent yet, like SunGEM does.
4336  */
4337 static void tg3_tx(struct tg3_napi *tnapi)
4338 {
4339         struct tg3 *tp = tnapi->tp;
4340         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4341         u32 sw_idx = tnapi->tx_cons;
4342         struct netdev_queue *txq;
4343         int index = tnapi - tp->napi;
4344
4345         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4346                 index--;
4347
4348         txq = netdev_get_tx_queue(tp->dev, index);
4349
4350         while (sw_idx != hw_idx) {
4351                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4352                 struct sk_buff *skb = ri->skb;
4353                 int i, tx_bug = 0;
4354
4355                 if (unlikely(skb == NULL)) {
4356                         tg3_tx_recover(tp);
4357                         return;
4358                 }
4359
4360                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4361
4362                 ri->skb = NULL;
4363
4364                 sw_idx = NEXT_TX(sw_idx);
4365
4366                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4367                         ri = &tnapi->tx_buffers[sw_idx];
4368                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4369                                 tx_bug = 1;
4370                         sw_idx = NEXT_TX(sw_idx);
4371                 }
4372
4373                 dev_kfree_skb(skb);
4374
4375                 if (unlikely(tx_bug)) {
4376                         tg3_tx_recover(tp);
4377                         return;
4378                 }
4379         }
4380
4381         tnapi->tx_cons = sw_idx;
4382
4383         /* Need to make the tx_cons update visible to tg3_start_xmit()
4384          * before checking for netif_queue_stopped().  Without the
4385          * memory barrier, there is a small possibility that tg3_start_xmit()
4386          * will miss it and cause the queue to be stopped forever.
4387          */
4388         smp_mb();
4389
4390         if (unlikely(netif_tx_queue_stopped(txq) &&
4391                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4392                 __netif_tx_lock(txq, smp_processor_id());
4393                 if (netif_tx_queue_stopped(txq) &&
4394                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4395                         netif_tx_wake_queue(txq);
4396                 __netif_tx_unlock(txq);
4397         }
4398 }
4399
4400 /* Returns size of skb allocated or < 0 on error.
4401  *
4402  * We only need to fill in the address because the other members
4403  * of the RX descriptor are invariant, see tg3_init_rings.
4404  *
4405  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4406  * posting buffers we only dirty the first cache line of the RX
4407  * descriptor (containing the address).  Whereas for the RX status
4408  * buffers the cpu only reads the last cacheline of the RX descriptor
4409  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4410  */
4411 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4412                             int src_idx, u32 dest_idx_unmasked)
4413 {
4414         struct tg3 *tp = tnapi->tp;
4415         struct tg3_rx_buffer_desc *desc;
4416         struct ring_info *map, *src_map;
4417         struct sk_buff *skb;
4418         dma_addr_t mapping;
4419         int skb_size, dest_idx;
4420         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4421
4422         src_map = NULL;
4423         switch (opaque_key) {
4424         case RXD_OPAQUE_RING_STD:
4425                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4426                 desc = &tpr->rx_std[dest_idx];
4427                 map = &tpr->rx_std_buffers[dest_idx];
4428                 if (src_idx >= 0)
4429                         src_map = &tpr->rx_std_buffers[src_idx];
4430                 skb_size = tp->rx_pkt_map_sz;
4431                 break;
4432
4433         case RXD_OPAQUE_RING_JUMBO:
4434                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4435                 desc = &tpr->rx_jmb[dest_idx].std;
4436                 map = &tpr->rx_jmb_buffers[dest_idx];
4437                 if (src_idx >= 0)
4438                         src_map = &tpr->rx_jmb_buffers[src_idx];
4439                 skb_size = TG3_RX_JMB_MAP_SZ;
4440                 break;
4441
4442         default:
4443                 return -EINVAL;
4444         }
4445
4446         /* Do not overwrite any of the map or rp information
4447          * until we are sure we can commit to a new buffer.
4448          *
4449          * Callers depend upon this behavior and assume that
4450          * we leave everything unchanged if we fail.
4451          */
4452         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4453         if (skb == NULL)
4454                 return -ENOMEM;
4455
4456         skb_reserve(skb, tp->rx_offset);
4457
4458         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4459                                  PCI_DMA_FROMDEVICE);
4460         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4461                 dev_kfree_skb(skb);
4462                 return -EIO;
4463         }
4464
4465         map->skb = skb;
4466         pci_unmap_addr_set(map, mapping, mapping);
4467
4468         if (src_map != NULL)
4469                 src_map->skb = NULL;
4470
4471         desc->addr_hi = ((u64)mapping >> 32);
4472         desc->addr_lo = ((u64)mapping & 0xffffffff);
4473
4474         return skb_size;
4475 }
4476
4477 /* We only need to move over in the address because the other
4478  * members of the RX descriptor are invariant.  See notes above
4479  * tg3_alloc_rx_skb for full details.
4480  */
4481 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4482                            int src_idx, u32 dest_idx_unmasked)
4483 {
4484         struct tg3 *tp = tnapi->tp;
4485         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4486         struct ring_info *src_map, *dest_map;
4487         int dest_idx;
4488         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4489
4490         switch (opaque_key) {
4491         case RXD_OPAQUE_RING_STD:
4492                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4493                 dest_desc = &tpr->rx_std[dest_idx];
4494                 dest_map = &tpr->rx_std_buffers[dest_idx];
4495                 src_desc = &tpr->rx_std[src_idx];
4496                 src_map = &tpr->rx_std_buffers[src_idx];
4497                 break;
4498
4499         case RXD_OPAQUE_RING_JUMBO:
4500                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4501                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4502                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4503                 src_desc = &tpr->rx_jmb[src_idx].std;
4504                 src_map = &tpr->rx_jmb_buffers[src_idx];
4505                 break;
4506
4507         default:
4508                 return;
4509         }
4510
4511         dest_map->skb = src_map->skb;
4512         pci_unmap_addr_set(dest_map, mapping,
4513                            pci_unmap_addr(src_map, mapping));
4514         dest_desc->addr_hi = src_desc->addr_hi;
4515         dest_desc->addr_lo = src_desc->addr_lo;
4516
4517         src_map->skb = NULL;
4518 }
4519
4520 /* The RX ring scheme is composed of multiple rings which post fresh
4521  * buffers to the chip, and one special ring the chip uses to report
4522  * status back to the host.
4523  *
4524  * The special ring reports the status of received packets to the
4525  * host.  The chip does not write into the original descriptor the
4526  * RX buffer was obtained from.  The chip simply takes the original
4527  * descriptor as provided by the host, updates the status and length
4528  * field, then writes this into the next status ring entry.
4529  *
4530  * Each ring the host uses to post buffers to the chip is described
4531  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4532  * it is first placed into the on-chip ram.  When the packet's length
4533  * is known, it walks down the TG3_BDINFO entries to select the ring.
4534  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4535  * which is within the range of the new packet's length is chosen.
4536  *
4537  * The "separate ring for rx status" scheme may sound queer, but it makes
4538  * sense from a cache coherency perspective.  If only the host writes
4539  * to the buffer post rings, and only the chip writes to the rx status
4540  * rings, then cache lines never move beyond shared-modified state.
4541  * If both the host and chip were to write into the same ring, cache line
4542  * eviction could occur since both entities want it in an exclusive state.
4543  */
4544 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4545 {
4546         struct tg3 *tp = tnapi->tp;
4547         u32 work_mask, rx_std_posted = 0;
4548         u32 sw_idx = tnapi->rx_rcb_ptr;
4549         u16 hw_idx;
4550         int received;
4551         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4552
4553         hw_idx = *(tnapi->rx_rcb_prod_idx);
4554         /*
4555          * We need to order the read of hw_idx and the read of
4556          * the opaque cookie.
4557          */
4558         rmb();
4559         work_mask = 0;
4560         received = 0;
4561         while (sw_idx != hw_idx && budget > 0) {
4562                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4563                 unsigned int len;
4564                 struct sk_buff *skb;
4565                 dma_addr_t dma_addr;
4566                 u32 opaque_key, desc_idx, *post_ptr;
4567
4568                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4569                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4570                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4571                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4572                         dma_addr = pci_unmap_addr(ri, mapping);
4573                         skb = ri->skb;
4574                         post_ptr = &tpr->rx_std_ptr;
4575                         rx_std_posted++;
4576                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4577                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4578                         dma_addr = pci_unmap_addr(ri, mapping);
4579                         skb = ri->skb;
4580                         post_ptr = &tpr->rx_jmb_ptr;
4581                 } else
4582                         goto next_pkt_nopost;
4583
4584                 work_mask |= opaque_key;
4585
4586                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4587                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4588                 drop_it:
4589                         tg3_recycle_rx(tnapi, opaque_key,
4590                                        desc_idx, *post_ptr);
4591                 drop_it_no_recycle:
4592                         /* Other statistics kept track of by card. */
4593                         tp->net_stats.rx_dropped++;
4594                         goto next_pkt;
4595                 }
4596
4597                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4598                       ETH_FCS_LEN;
4599
4600                 if (len > RX_COPY_THRESHOLD
4601                         && tp->rx_offset == NET_IP_ALIGN
4602                         /* rx_offset will likely not equal NET_IP_ALIGN
4603                          * if this is a 5701 card running in PCI-X mode
4604                          * [see tg3_get_invariants()]
4605                          */
4606                 ) {
4607                         int skb_size;
4608
4609                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4610                                                     desc_idx, *post_ptr);
4611                         if (skb_size < 0)
4612                                 goto drop_it;
4613
4614                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4615                                          PCI_DMA_FROMDEVICE);
4616
4617                         skb_put(skb, len);
4618                 } else {
4619                         struct sk_buff *copy_skb;
4620
4621                         tg3_recycle_rx(tnapi, opaque_key,
4622                                        desc_idx, *post_ptr);
4623
4624                         copy_skb = netdev_alloc_skb(tp->dev,
4625                                                     len + TG3_RAW_IP_ALIGN);
4626                         if (copy_skb == NULL)
4627                                 goto drop_it_no_recycle;
4628
4629                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4630                         skb_put(copy_skb, len);
4631                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4632                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4633                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4634
4635                         /* We'll reuse the original ring buffer. */
4636                         skb = copy_skb;
4637                 }
4638
4639                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4640                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4641                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4642                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4643                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4644                 else
4645                         skb->ip_summed = CHECKSUM_NONE;
4646
4647                 skb->protocol = eth_type_trans(skb, tp->dev);
4648
4649                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4650                     skb->protocol != htons(ETH_P_8021Q)) {
4651                         dev_kfree_skb(skb);
4652                         goto next_pkt;
4653                 }
4654
4655 #if TG3_VLAN_TAG_USED
4656                 if (tp->vlgrp != NULL &&
4657                     desc->type_flags & RXD_FLAG_VLAN) {
4658                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4659                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4660                 } else
4661 #endif
4662                         napi_gro_receive(&tnapi->napi, skb);
4663
4664                 received++;
4665                 budget--;
4666
4667 next_pkt:
4668                 (*post_ptr)++;
4669
4670                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4671                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4672
4673                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4674                                      TG3_64BIT_REG_LOW, idx);
4675                         work_mask &= ~RXD_OPAQUE_RING_STD;
4676                         rx_std_posted = 0;
4677                 }
4678 next_pkt_nopost:
4679                 sw_idx++;
4680                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4681
4682                 /* Refresh hw_idx to see if there is new work */
4683                 if (sw_idx == hw_idx) {
4684                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4685                         rmb();
4686                 }
4687         }
4688
4689         /* ACK the status ring. */
4690         tnapi->rx_rcb_ptr = sw_idx;
4691         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4692
4693         /* Refill RX ring(s). */
4694         if (work_mask & RXD_OPAQUE_RING_STD) {
4695                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4696                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4697                              sw_idx);
4698         }
4699         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4700                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4701                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4702                              sw_idx);
4703         }
4704         mmiowb();
4705
4706         return received;
4707 }
4708
4709 static void tg3_poll_link(struct tg3 *tp)
4710 {
4711         /* handle link change and other phy events */
4712         if (!(tp->tg3_flags &
4713               (TG3_FLAG_USE_LINKCHG_REG |
4714                TG3_FLAG_POLL_SERDES))) {
4715                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4716
4717                 if (sblk->status & SD_STATUS_LINK_CHG) {
4718                         sblk->status = SD_STATUS_UPDATED |
4719                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4720                         spin_lock(&tp->lock);
4721                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4722                                 tw32_f(MAC_STATUS,
4723                                      (MAC_STATUS_SYNC_CHANGED |
4724                                       MAC_STATUS_CFG_CHANGED |
4725                                       MAC_STATUS_MI_COMPLETION |
4726                                       MAC_STATUS_LNKSTATE_CHANGED));
4727                                 udelay(40);
4728                         } else
4729                                 tg3_setup_phy(tp, 0);
4730                         spin_unlock(&tp->lock);
4731                 }
4732         }
4733 }
4734
4735 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4736 {
4737         struct tg3 *tp = tnapi->tp;
4738
4739         /* run TX completion thread */
4740         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4741                 tg3_tx(tnapi);
4742                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4743                         return work_done;
4744         }
4745
4746         /* run RX thread, within the bounds set by NAPI.
4747          * All RX "locking" is done by ensuring outside
4748          * code synchronizes with tg3->napi.poll()
4749          */
4750         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4751                 work_done += tg3_rx(tnapi, budget - work_done);
4752
4753         return work_done;
4754 }
4755
4756 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4757 {
4758         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4759         struct tg3 *tp = tnapi->tp;
4760         int work_done = 0;
4761         struct tg3_hw_status *sblk = tnapi->hw_status;
4762
4763         while (1) {
4764                 work_done = tg3_poll_work(tnapi, work_done, budget);
4765
4766                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4767                         goto tx_recovery;
4768
4769                 if (unlikely(work_done >= budget))
4770                         break;
4771
4772                 /* tp->last_tag is used in tg3_restart_ints() below
4773                  * to tell the hw how much work has been processed,
4774                  * so we must read it before checking for more work.
4775                  */
4776                 tnapi->last_tag = sblk->status_tag;
4777                 tnapi->last_irq_tag = tnapi->last_tag;
4778                 rmb();
4779
4780                 /* check for RX/TX work to do */
4781                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4782                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4783                         napi_complete(napi);
4784                         /* Reenable interrupts. */
4785                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4786                         mmiowb();
4787                         break;
4788                 }
4789         }
4790
4791         return work_done;
4792
4793 tx_recovery:
4794         /* work_done is guaranteed to be less than budget. */
4795         napi_complete(napi);
4796         schedule_work(&tp->reset_task);
4797         return work_done;
4798 }
4799
4800 static int tg3_poll(struct napi_struct *napi, int budget)
4801 {
4802         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4803         struct tg3 *tp = tnapi->tp;
4804         int work_done = 0;
4805         struct tg3_hw_status *sblk = tnapi->hw_status;
4806
4807         while (1) {
4808                 tg3_poll_link(tp);
4809
4810                 work_done = tg3_poll_work(tnapi, work_done, budget);
4811
4812                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4813                         goto tx_recovery;
4814
4815                 if (unlikely(work_done >= budget))
4816                         break;
4817
4818                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4819                         /* tp->last_tag is used in tg3_int_reenable() below
4820                          * to tell the hw how much work has been processed,
4821                          * so we must read it before checking for more work.
4822                          */
4823                         tnapi->last_tag = sblk->status_tag;
4824                         tnapi->last_irq_tag = tnapi->last_tag;
4825                         rmb();
4826                 } else
4827                         sblk->status &= ~SD_STATUS_UPDATED;
4828
4829                 if (likely(!tg3_has_work(tnapi))) {
4830                         napi_complete(napi);
4831                         tg3_int_reenable(tnapi);
4832                         break;
4833                 }
4834         }
4835
4836         return work_done;
4837
4838 tx_recovery:
4839         /* work_done is guaranteed to be less than budget. */
4840         napi_complete(napi);
4841         schedule_work(&tp->reset_task);
4842         return work_done;
4843 }
4844
4845 static void tg3_irq_quiesce(struct tg3 *tp)
4846 {
4847         int i;
4848
4849         BUG_ON(tp->irq_sync);
4850
4851         tp->irq_sync = 1;
4852         smp_mb();
4853
4854         for (i = 0; i < tp->irq_cnt; i++)
4855                 synchronize_irq(tp->napi[i].irq_vec);
4856 }
4857
4858 static inline int tg3_irq_sync(struct tg3 *tp)
4859 {
4860         return tp->irq_sync;
4861 }
4862
4863 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4864  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4865  * with as well.  Most of the time, this is not necessary except when
4866  * shutting down the device.
4867  */
4868 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4869 {
4870         spin_lock_bh(&tp->lock);
4871         if (irq_sync)
4872                 tg3_irq_quiesce(tp);
4873 }
4874
4875 static inline void tg3_full_unlock(struct tg3 *tp)
4876 {
4877         spin_unlock_bh(&tp->lock);
4878 }
4879
4880 /* One-shot MSI handler - Chip automatically disables interrupt
4881  * after sending MSI so driver doesn't have to do it.
4882  */
4883 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4884 {
4885         struct tg3_napi *tnapi = dev_id;
4886         struct tg3 *tp = tnapi->tp;
4887
4888         prefetch(tnapi->hw_status);
4889         if (tnapi->rx_rcb)
4890                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4891
4892         if (likely(!tg3_irq_sync(tp)))
4893                 napi_schedule(&tnapi->napi);
4894
4895         return IRQ_HANDLED;
4896 }
4897
4898 /* MSI ISR - No need to check for interrupt sharing and no need to
4899  * flush status block and interrupt mailbox. PCI ordering rules
4900  * guarantee that MSI will arrive after the status block.
4901  */
4902 static irqreturn_t tg3_msi(int irq, void *dev_id)
4903 {
4904         struct tg3_napi *tnapi = dev_id;
4905         struct tg3 *tp = tnapi->tp;
4906
4907         prefetch(tnapi->hw_status);
4908         if (tnapi->rx_rcb)
4909                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4910         /*
4911          * Writing any value to intr-mbox-0 clears PCI INTA# and
4912          * chip-internal interrupt pending events.
4913          * Writing non-zero to intr-mbox-0 additional tells the
4914          * NIC to stop sending us irqs, engaging "in-intr-handler"
4915          * event coalescing.
4916          */
4917         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4918         if (likely(!tg3_irq_sync(tp)))
4919                 napi_schedule(&tnapi->napi);
4920
4921         return IRQ_RETVAL(1);
4922 }
4923
4924 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4925 {
4926         struct tg3_napi *tnapi = dev_id;
4927         struct tg3 *tp = tnapi->tp;
4928         struct tg3_hw_status *sblk = tnapi->hw_status;
4929         unsigned int handled = 1;
4930
4931         /* In INTx mode, it is possible for the interrupt to arrive at
4932          * the CPU before the status block posted prior to the interrupt.
4933          * Reading the PCI State register will confirm whether the
4934          * interrupt is ours and will flush the status block.
4935          */
4936         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4937                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4938                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4939                         handled = 0;
4940                         goto out;
4941                 }
4942         }
4943
4944         /*
4945          * Writing any value to intr-mbox-0 clears PCI INTA# and
4946          * chip-internal interrupt pending events.
4947          * Writing non-zero to intr-mbox-0 additional tells the
4948          * NIC to stop sending us irqs, engaging "in-intr-handler"
4949          * event coalescing.
4950          *
4951          * Flush the mailbox to de-assert the IRQ immediately to prevent
4952          * spurious interrupts.  The flush impacts performance but
4953          * excessive spurious interrupts can be worse in some cases.
4954          */
4955         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4956         if (tg3_irq_sync(tp))
4957                 goto out;
4958         sblk->status &= ~SD_STATUS_UPDATED;
4959         if (likely(tg3_has_work(tnapi))) {
4960                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4961                 napi_schedule(&tnapi->napi);
4962         } else {
4963                 /* No work, shared interrupt perhaps?  re-enable
4964                  * interrupts, and flush that PCI write
4965                  */
4966                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4967                                0x00000000);
4968         }
4969 out:
4970         return IRQ_RETVAL(handled);
4971 }
4972
4973 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4974 {
4975         struct tg3_napi *tnapi = dev_id;
4976         struct tg3 *tp = tnapi->tp;
4977         struct tg3_hw_status *sblk = tnapi->hw_status;
4978         unsigned int handled = 1;
4979
4980         /* In INTx mode, it is possible for the interrupt to arrive at
4981          * the CPU before the status block posted prior to the interrupt.
4982          * Reading the PCI State register will confirm whether the
4983          * interrupt is ours and will flush the status block.
4984          */
4985         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4986                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4987                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4988                         handled = 0;
4989                         goto out;
4990                 }
4991         }
4992
4993         /*
4994          * writing any value to intr-mbox-0 clears PCI INTA# and
4995          * chip-internal interrupt pending events.
4996          * writing non-zero to intr-mbox-0 additional tells the
4997          * NIC to stop sending us irqs, engaging "in-intr-handler"
4998          * event coalescing.
4999          *
5000          * Flush the mailbox to de-assert the IRQ immediately to prevent
5001          * spurious interrupts.  The flush impacts performance but
5002          * excessive spurious interrupts can be worse in some cases.
5003          */
5004         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5005
5006         /*
5007          * In a shared interrupt configuration, sometimes other devices'
5008          * interrupts will scream.  We record the current status tag here
5009          * so that the above check can report that the screaming interrupts
5010          * are unhandled.  Eventually they will be silenced.
5011          */
5012         tnapi->last_irq_tag = sblk->status_tag;
5013
5014         if (tg3_irq_sync(tp))
5015                 goto out;
5016
5017         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5018
5019         napi_schedule(&tnapi->napi);
5020
5021 out:
5022         return IRQ_RETVAL(handled);
5023 }
5024
5025 /* ISR for interrupt test */
5026 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5027 {
5028         struct tg3_napi *tnapi = dev_id;
5029         struct tg3 *tp = tnapi->tp;
5030         struct tg3_hw_status *sblk = tnapi->hw_status;
5031
5032         if ((sblk->status & SD_STATUS_UPDATED) ||
5033             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5034                 tg3_disable_ints(tp);
5035                 return IRQ_RETVAL(1);
5036         }
5037         return IRQ_RETVAL(0);
5038 }
5039
5040 static int tg3_init_hw(struct tg3 *, int);
5041 static int tg3_halt(struct tg3 *, int, int);
5042
5043 /* Restart hardware after configuration changes, self-test, etc.
5044  * Invoked with tp->lock held.
5045  */
5046 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5047         __releases(tp->lock)
5048         __acquires(tp->lock)
5049 {
5050         int err;
5051
5052         err = tg3_init_hw(tp, reset_phy);
5053         if (err) {
5054                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5055                        "aborting.\n", tp->dev->name);
5056                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5057                 tg3_full_unlock(tp);
5058                 del_timer_sync(&tp->timer);
5059                 tp->irq_sync = 0;
5060                 tg3_napi_enable(tp);
5061                 dev_close(tp->dev);
5062                 tg3_full_lock(tp, 0);
5063         }
5064         return err;
5065 }
5066
5067 #ifdef CONFIG_NET_POLL_CONTROLLER
5068 static void tg3_poll_controller(struct net_device *dev)
5069 {
5070         int i;
5071         struct tg3 *tp = netdev_priv(dev);
5072
5073         for (i = 0; i < tp->irq_cnt; i++)
5074                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5075 }
5076 #endif
5077
5078 static void tg3_reset_task(struct work_struct *work)
5079 {
5080         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5081         int err;
5082         unsigned int restart_timer;
5083
5084         tg3_full_lock(tp, 0);
5085
5086         if (!netif_running(tp->dev)) {
5087                 tg3_full_unlock(tp);
5088                 return;
5089         }
5090
5091         tg3_full_unlock(tp);
5092
5093         tg3_phy_stop(tp);
5094
5095         tg3_netif_stop(tp);
5096
5097         tg3_full_lock(tp, 1);
5098
5099         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5100         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5101
5102         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5103                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5104                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5105                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5106                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5107         }
5108
5109         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5110         err = tg3_init_hw(tp, 1);
5111         if (err)
5112                 goto out;
5113
5114         tg3_netif_start(tp);
5115
5116         if (restart_timer)
5117                 mod_timer(&tp->timer, jiffies + 1);
5118
5119 out:
5120         tg3_full_unlock(tp);
5121
5122         if (!err)
5123                 tg3_phy_start(tp);
5124 }
5125
5126 static void tg3_dump_short_state(struct tg3 *tp)
5127 {
5128         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5129                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5130         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5131                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5132 }
5133
5134 static void tg3_tx_timeout(struct net_device *dev)
5135 {
5136         struct tg3 *tp = netdev_priv(dev);
5137
5138         if (netif_msg_tx_err(tp)) {
5139                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5140                        dev->name);
5141                 tg3_dump_short_state(tp);
5142         }
5143
5144         schedule_work(&tp->reset_task);
5145 }
5146
5147 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5148 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5149 {
5150         u32 base = (u32) mapping & 0xffffffff;
5151
5152         return ((base > 0xffffdcc0) &&
5153                 (base + len + 8 < base));
5154 }
5155
5156 /* Test for DMA addresses > 40-bit */
5157 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5158                                           int len)
5159 {
5160 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5161         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5162                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5163         return 0;
5164 #else
5165         return 0;
5166 #endif
5167 }
5168
5169 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5170
5171 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5172 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5173                                        struct sk_buff *skb, u32 last_plus_one,
5174                                        u32 *start, u32 base_flags, u32 mss)
5175 {
5176         struct tg3 *tp = tnapi->tp;
5177         struct sk_buff *new_skb;
5178         dma_addr_t new_addr = 0;
5179         u32 entry = *start;
5180         int i, ret = 0;
5181
5182         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5183                 new_skb = skb_copy(skb, GFP_ATOMIC);
5184         else {
5185                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5186
5187                 new_skb = skb_copy_expand(skb,
5188                                           skb_headroom(skb) + more_headroom,
5189                                           skb_tailroom(skb), GFP_ATOMIC);
5190         }
5191
5192         if (!new_skb) {
5193                 ret = -1;
5194         } else {
5195                 /* New SKB is guaranteed to be linear. */
5196                 entry = *start;
5197                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5198                 new_addr = skb_shinfo(new_skb)->dma_head;
5199
5200                 /* Make sure new skb does not cross any 4G boundaries.
5201                  * Drop the packet if it does.
5202                  */
5203                 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5204                             tg3_4g_overflow_test(new_addr, new_skb->len))) {
5205                         if (!ret)
5206                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5207                                               DMA_TO_DEVICE);
5208                         ret = -1;
5209                         dev_kfree_skb(new_skb);
5210                         new_skb = NULL;
5211                 } else {
5212                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5213                                     base_flags, 1 | (mss << 1));
5214                         *start = NEXT_TX(entry);
5215                 }
5216         }
5217
5218         /* Now clean up the sw ring entries. */
5219         i = 0;
5220         while (entry != last_plus_one) {
5221                 if (i == 0)
5222                         tnapi->tx_buffers[entry].skb = new_skb;
5223                 else
5224                         tnapi->tx_buffers[entry].skb = NULL;
5225                 entry = NEXT_TX(entry);
5226                 i++;
5227         }
5228
5229         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5230         dev_kfree_skb(skb);
5231
5232         return ret;
5233 }
5234
5235 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5236                         dma_addr_t mapping, int len, u32 flags,
5237                         u32 mss_and_is_end)
5238 {
5239         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5240         int is_end = (mss_and_is_end & 0x1);
5241         u32 mss = (mss_and_is_end >> 1);
5242         u32 vlan_tag = 0;
5243
5244         if (is_end)
5245                 flags |= TXD_FLAG_END;
5246         if (flags & TXD_FLAG_VLAN) {
5247                 vlan_tag = flags >> 16;
5248                 flags &= 0xffff;
5249         }
5250         vlan_tag |= (mss << TXD_MSS_SHIFT);
5251
5252         txd->addr_hi = ((u64) mapping >> 32);
5253         txd->addr_lo = ((u64) mapping & 0xffffffff);
5254         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5255         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5256 }
5257
5258 /* hard_start_xmit for devices that don't have any bugs and
5259  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5260  */
5261 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5262                                   struct net_device *dev)
5263 {
5264         struct tg3 *tp = netdev_priv(dev);
5265         u32 len, entry, base_flags, mss;
5266         struct skb_shared_info *sp;
5267         dma_addr_t mapping;
5268         struct tg3_napi *tnapi;
5269         struct netdev_queue *txq;
5270
5271         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5272         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5273         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5274                 tnapi++;
5275
5276         /* We are running in BH disabled context with netif_tx_lock
5277          * and TX reclaim runs via tp->napi.poll inside of a software
5278          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5279          * no IRQ context deadlocks to worry about either.  Rejoice!
5280          */
5281         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5282                 if (!netif_tx_queue_stopped(txq)) {
5283                         netif_tx_stop_queue(txq);
5284
5285                         /* This is a hard error, log it. */
5286                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5287                                "queue awake!\n", dev->name);
5288                 }
5289                 return NETDEV_TX_BUSY;
5290         }
5291
5292         entry = tnapi->tx_prod;
5293         base_flags = 0;
5294         mss = 0;
5295         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5296                 int tcp_opt_len, ip_tcp_len;
5297                 u32 hdrlen;
5298
5299                 if (skb_header_cloned(skb) &&
5300                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5301                         dev_kfree_skb(skb);
5302                         goto out_unlock;
5303                 }
5304
5305                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5306                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5307                 else {
5308                         struct iphdr *iph = ip_hdr(skb);
5309
5310                         tcp_opt_len = tcp_optlen(skb);
5311                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5312
5313                         iph->check = 0;
5314                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5315                         hdrlen = ip_tcp_len + tcp_opt_len;
5316                 }
5317
5318                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5319                         mss |= (hdrlen & 0xc) << 12;
5320                         if (hdrlen & 0x10)
5321                                 base_flags |= 0x00000010;
5322                         base_flags |= (hdrlen & 0x3e0) << 5;
5323                 } else
5324                         mss |= hdrlen << 9;
5325
5326                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5327                                TXD_FLAG_CPU_POST_DMA);
5328
5329                 tcp_hdr(skb)->check = 0;
5330
5331         }
5332         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5333                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5334 #if TG3_VLAN_TAG_USED
5335         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5336                 base_flags |= (TXD_FLAG_VLAN |
5337                                (vlan_tx_tag_get(skb) << 16));
5338 #endif
5339
5340         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5341                 dev_kfree_skb(skb);
5342                 goto out_unlock;
5343         }
5344
5345         sp = skb_shinfo(skb);
5346
5347         mapping = sp->dma_head;
5348
5349         tnapi->tx_buffers[entry].skb = skb;
5350
5351         len = skb_headlen(skb);
5352
5353         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5354             !mss && skb->len > ETH_DATA_LEN)
5355                 base_flags |= TXD_FLAG_JMB_PKT;
5356
5357         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5358                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5359
5360         entry = NEXT_TX(entry);
5361
5362         /* Now loop through additional data fragments, and queue them. */
5363         if (skb_shinfo(skb)->nr_frags > 0) {
5364                 unsigned int i, last;
5365
5366                 last = skb_shinfo(skb)->nr_frags - 1;
5367                 for (i = 0; i <= last; i++) {
5368                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5369
5370                         len = frag->size;
5371                         mapping = sp->dma_maps[i];
5372                         tnapi->tx_buffers[entry].skb = NULL;
5373
5374                         tg3_set_txd(tnapi, entry, mapping, len,
5375                                     base_flags, (i == last) | (mss << 1));
5376
5377                         entry = NEXT_TX(entry);
5378                 }
5379         }
5380
5381         /* Packets are ready, update Tx producer idx local and on card. */
5382         tw32_tx_mbox(tnapi->prodmbox, entry);
5383
5384         tnapi->tx_prod = entry;
5385         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5386                 netif_tx_stop_queue(txq);
5387                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5388                         netif_tx_wake_queue(txq);
5389         }
5390
5391 out_unlock:
5392         mmiowb();
5393
5394         return NETDEV_TX_OK;
5395 }
5396
5397 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5398                                           struct net_device *);
5399
5400 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5401  * TSO header is greater than 80 bytes.
5402  */
5403 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5404 {
5405         struct sk_buff *segs, *nskb;
5406         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5407
5408         /* Estimate the number of fragments in the worst case */
5409         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5410                 netif_stop_queue(tp->dev);
5411                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5412                         return NETDEV_TX_BUSY;
5413
5414                 netif_wake_queue(tp->dev);
5415         }
5416
5417         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5418         if (IS_ERR(segs))
5419                 goto tg3_tso_bug_end;
5420
5421         do {
5422                 nskb = segs;
5423                 segs = segs->next;
5424                 nskb->next = NULL;
5425                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5426         } while (segs);
5427
5428 tg3_tso_bug_end:
5429         dev_kfree_skb(skb);
5430
5431         return NETDEV_TX_OK;
5432 }
5433
5434 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5435  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5436  */
5437 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5438                                           struct net_device *dev)
5439 {
5440         struct tg3 *tp = netdev_priv(dev);
5441         u32 len, entry, base_flags, mss;
5442         struct skb_shared_info *sp;
5443         int would_hit_hwbug;
5444         dma_addr_t mapping;
5445         struct tg3_napi *tnapi;
5446         struct netdev_queue *txq;
5447
5448         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5449         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5450         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5451                 tnapi++;
5452
5453         /* We are running in BH disabled context with netif_tx_lock
5454          * and TX reclaim runs via tp->napi.poll inside of a software
5455          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5456          * no IRQ context deadlocks to worry about either.  Rejoice!
5457          */
5458         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5459                 if (!netif_tx_queue_stopped(txq)) {
5460                         netif_tx_stop_queue(txq);
5461
5462                         /* This is a hard error, log it. */
5463                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5464                                "queue awake!\n", dev->name);
5465                 }
5466                 return NETDEV_TX_BUSY;
5467         }
5468
5469         entry = tnapi->tx_prod;
5470         base_flags = 0;
5471         if (skb->ip_summed == CHECKSUM_PARTIAL)
5472                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5473
5474         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5475                 struct iphdr *iph;
5476                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5477
5478                 if (skb_header_cloned(skb) &&
5479                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5480                         dev_kfree_skb(skb);
5481                         goto out_unlock;
5482                 }
5483
5484                 tcp_opt_len = tcp_optlen(skb);
5485                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5486
5487                 hdr_len = ip_tcp_len + tcp_opt_len;
5488                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5489                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5490                         return (tg3_tso_bug(tp, skb));
5491
5492                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5493                                TXD_FLAG_CPU_POST_DMA);
5494
5495                 iph = ip_hdr(skb);
5496                 iph->check = 0;
5497                 iph->tot_len = htons(mss + hdr_len);
5498                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5499                         tcp_hdr(skb)->check = 0;
5500                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5501                 } else
5502                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5503                                                                  iph->daddr, 0,
5504                                                                  IPPROTO_TCP,
5505                                                                  0);
5506
5507                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5508                         mss |= (hdr_len & 0xc) << 12;
5509                         if (hdr_len & 0x10)
5510                                 base_flags |= 0x00000010;
5511                         base_flags |= (hdr_len & 0x3e0) << 5;
5512                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5513                         mss |= hdr_len << 9;
5514                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5515                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5516                         if (tcp_opt_len || iph->ihl > 5) {
5517                                 int tsflags;
5518
5519                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5520                                 mss |= (tsflags << 11);
5521                         }
5522                 } else {
5523                         if (tcp_opt_len || iph->ihl > 5) {
5524                                 int tsflags;
5525
5526                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5527                                 base_flags |= tsflags << 12;
5528                         }
5529                 }
5530         }
5531 #if TG3_VLAN_TAG_USED
5532         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5533                 base_flags |= (TXD_FLAG_VLAN |
5534                                (vlan_tx_tag_get(skb) << 16));
5535 #endif
5536
5537         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5538             !mss && skb->len > ETH_DATA_LEN)
5539                 base_flags |= TXD_FLAG_JMB_PKT;
5540
5541         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5542                 dev_kfree_skb(skb);
5543                 goto out_unlock;
5544         }
5545
5546         sp = skb_shinfo(skb);
5547
5548         mapping = sp->dma_head;
5549
5550         tnapi->tx_buffers[entry].skb = skb;
5551
5552         would_hit_hwbug = 0;
5553
5554         len = skb_headlen(skb);
5555
5556         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5557                 would_hit_hwbug = 1;
5558
5559         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5560             tg3_4g_overflow_test(mapping, len))
5561                 would_hit_hwbug = 1;
5562
5563         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5564             tg3_40bit_overflow_test(tp, mapping, len))
5565                 would_hit_hwbug = 1;
5566
5567         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5568                 would_hit_hwbug = 1;
5569
5570         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5571                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5572
5573         entry = NEXT_TX(entry);
5574
5575         /* Now loop through additional data fragments, and queue them. */
5576         if (skb_shinfo(skb)->nr_frags > 0) {
5577                 unsigned int i, last;
5578
5579                 last = skb_shinfo(skb)->nr_frags - 1;
5580                 for (i = 0; i <= last; i++) {
5581                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5582
5583                         len = frag->size;
5584                         mapping = sp->dma_maps[i];
5585
5586                         tnapi->tx_buffers[entry].skb = NULL;
5587
5588                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5589                             len <= 8)
5590                                 would_hit_hwbug = 1;
5591
5592                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5593                             tg3_4g_overflow_test(mapping, len))
5594                                 would_hit_hwbug = 1;
5595
5596                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5597                             tg3_40bit_overflow_test(tp, mapping, len))
5598                                 would_hit_hwbug = 1;
5599
5600                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5601                                 tg3_set_txd(tnapi, entry, mapping, len,
5602                                             base_flags, (i == last)|(mss << 1));
5603                         else
5604                                 tg3_set_txd(tnapi, entry, mapping, len,
5605                                             base_flags, (i == last));
5606
5607                         entry = NEXT_TX(entry);
5608                 }
5609         }
5610
5611         if (would_hit_hwbug) {
5612                 u32 last_plus_one = entry;
5613                 u32 start;
5614
5615                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5616                 start &= (TG3_TX_RING_SIZE - 1);
5617
5618                 /* If the workaround fails due to memory/mapping
5619                  * failure, silently drop this packet.
5620                  */
5621                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5622                                                 &start, base_flags, mss))
5623                         goto out_unlock;
5624
5625                 entry = start;
5626         }
5627
5628         /* Packets are ready, update Tx producer idx local and on card. */
5629         tw32_tx_mbox(tnapi->prodmbox, entry);
5630
5631         tnapi->tx_prod = entry;
5632         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5633                 netif_tx_stop_queue(txq);
5634                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5635                         netif_tx_wake_queue(txq);
5636         }
5637
5638 out_unlock:
5639         mmiowb();
5640
5641         return NETDEV_TX_OK;
5642 }
5643
5644 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5645                                int new_mtu)
5646 {
5647         dev->mtu = new_mtu;
5648
5649         if (new_mtu > ETH_DATA_LEN) {
5650                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5651                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5652                         ethtool_op_set_tso(dev, 0);
5653                 }
5654                 else
5655                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5656         } else {
5657                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5658                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5659                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5660         }
5661 }
5662
5663 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5664 {
5665         struct tg3 *tp = netdev_priv(dev);
5666         int err;
5667
5668         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5669                 return -EINVAL;
5670
5671         if (!netif_running(dev)) {
5672                 /* We'll just catch it later when the
5673                  * device is up'd.
5674                  */
5675                 tg3_set_mtu(dev, tp, new_mtu);
5676                 return 0;
5677         }
5678
5679         tg3_phy_stop(tp);
5680
5681         tg3_netif_stop(tp);
5682
5683         tg3_full_lock(tp, 1);
5684
5685         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5686
5687         tg3_set_mtu(dev, tp, new_mtu);
5688
5689         err = tg3_restart_hw(tp, 0);
5690
5691         if (!err)
5692                 tg3_netif_start(tp);
5693
5694         tg3_full_unlock(tp);
5695
5696         if (!err)
5697                 tg3_phy_start(tp);
5698
5699         return err;
5700 }
5701
5702 static void tg3_rx_prodring_free(struct tg3 *tp,
5703                                  struct tg3_rx_prodring_set *tpr)
5704 {
5705         int i;
5706         struct ring_info *rxp;
5707
5708         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5709                 rxp = &tpr->rx_std_buffers[i];
5710
5711                 if (rxp->skb == NULL)
5712                         continue;
5713
5714                 pci_unmap_single(tp->pdev,
5715                                  pci_unmap_addr(rxp, mapping),
5716                                  tp->rx_pkt_map_sz,
5717                                  PCI_DMA_FROMDEVICE);
5718                 dev_kfree_skb_any(rxp->skb);
5719                 rxp->skb = NULL;
5720         }
5721
5722         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5723                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5724                         rxp = &tpr->rx_jmb_buffers[i];
5725
5726                         if (rxp->skb == NULL)
5727                                 continue;
5728
5729                         pci_unmap_single(tp->pdev,
5730                                          pci_unmap_addr(rxp, mapping),
5731                                          TG3_RX_JMB_MAP_SZ,
5732                                          PCI_DMA_FROMDEVICE);
5733                         dev_kfree_skb_any(rxp->skb);
5734                         rxp->skb = NULL;
5735                 }
5736         }
5737 }
5738
5739 /* Initialize tx/rx rings for packet processing.
5740  *
5741  * The chip has been shut down and the driver detached from
5742  * the networking, so no interrupts or new tx packets will
5743  * end up in the driver.  tp->{tx,}lock are held and thus
5744  * we may not sleep.
5745  */
5746 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5747                                  struct tg3_rx_prodring_set *tpr)
5748 {
5749         u32 i, rx_pkt_dma_sz;
5750         struct tg3_napi *tnapi = &tp->napi[0];
5751
5752         /* Zero out all descriptors. */
5753         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5754
5755         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5756         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5757             tp->dev->mtu > ETH_DATA_LEN)
5758                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5759         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5760
5761         /* Initialize invariants of the rings, we only set this
5762          * stuff once.  This works because the card does not
5763          * write into the rx buffer posting rings.
5764          */
5765         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5766                 struct tg3_rx_buffer_desc *rxd;
5767
5768                 rxd = &tpr->rx_std[i];
5769                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5770                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5771                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5772                                (i << RXD_OPAQUE_INDEX_SHIFT));
5773         }
5774
5775         /* Now allocate fresh SKBs for each rx ring. */
5776         for (i = 0; i < tp->rx_pending; i++) {
5777                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5778                         printk(KERN_WARNING PFX
5779                                "%s: Using a smaller RX standard ring, "
5780                                "only %d out of %d buffers were allocated "
5781                                "successfully.\n",
5782                                tp->dev->name, i, tp->rx_pending);
5783                         if (i == 0)
5784                                 goto initfail;
5785                         tp->rx_pending = i;
5786                         break;
5787                 }
5788         }
5789
5790         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5791                 goto done;
5792
5793         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5794
5795         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5796                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5797                         struct tg3_rx_buffer_desc *rxd;
5798
5799                         rxd = &tpr->rx_jmb[i].std;
5800                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5801                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5802                                 RXD_FLAG_JUMBO;
5803                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5804                                (i << RXD_OPAQUE_INDEX_SHIFT));
5805                 }
5806
5807                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5808                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5809                                              -1, i) < 0) {
5810                                 printk(KERN_WARNING PFX
5811                                        "%s: Using a smaller RX jumbo ring, "
5812                                        "only %d out of %d buffers were "
5813                                        "allocated successfully.\n",
5814                                        tp->dev->name, i, tp->rx_jumbo_pending);
5815                                 if (i == 0)
5816                                         goto initfail;
5817                                 tp->rx_jumbo_pending = i;
5818                                 break;
5819                         }
5820                 }
5821         }
5822
5823 done:
5824         return 0;
5825
5826 initfail:
5827         tg3_rx_prodring_free(tp, tpr);
5828         return -ENOMEM;
5829 }
5830
5831 static void tg3_rx_prodring_fini(struct tg3 *tp,
5832                                  struct tg3_rx_prodring_set *tpr)
5833 {
5834         kfree(tpr->rx_std_buffers);
5835         tpr->rx_std_buffers = NULL;
5836         kfree(tpr->rx_jmb_buffers);
5837         tpr->rx_jmb_buffers = NULL;
5838         if (tpr->rx_std) {
5839                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5840                                     tpr->rx_std, tpr->rx_std_mapping);
5841                 tpr->rx_std = NULL;
5842         }
5843         if (tpr->rx_jmb) {
5844                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5845                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5846                 tpr->rx_jmb = NULL;
5847         }
5848 }
5849
5850 static int tg3_rx_prodring_init(struct tg3 *tp,
5851                                 struct tg3_rx_prodring_set *tpr)
5852 {
5853         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5854                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5855         if (!tpr->rx_std_buffers)
5856                 return -ENOMEM;
5857
5858         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5859                                            &tpr->rx_std_mapping);
5860         if (!tpr->rx_std)
5861                 goto err_out;
5862
5863         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5864                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5865                                               TG3_RX_JUMBO_RING_SIZE,
5866                                               GFP_KERNEL);
5867                 if (!tpr->rx_jmb_buffers)
5868                         goto err_out;
5869
5870                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5871                                                    TG3_RX_JUMBO_RING_BYTES,
5872                                                    &tpr->rx_jmb_mapping);
5873                 if (!tpr->rx_jmb)
5874                         goto err_out;
5875         }
5876
5877         return 0;
5878
5879 err_out:
5880         tg3_rx_prodring_fini(tp, tpr);
5881         return -ENOMEM;
5882 }
5883
5884 /* Free up pending packets in all rx/tx rings.
5885  *
5886  * The chip has been shut down and the driver detached from
5887  * the networking, so no interrupts or new tx packets will
5888  * end up in the driver.  tp->{tx,}lock is not held and we are not
5889  * in an interrupt context and thus may sleep.
5890  */
5891 static void tg3_free_rings(struct tg3 *tp)
5892 {
5893         int i, j;
5894
5895         for (j = 0; j < tp->irq_cnt; j++) {
5896                 struct tg3_napi *tnapi = &tp->napi[j];
5897
5898                 if (!tnapi->tx_buffers)
5899                         continue;
5900
5901                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5902                         struct tx_ring_info *txp;
5903                         struct sk_buff *skb;
5904
5905                         txp = &tnapi->tx_buffers[i];
5906                         skb = txp->skb;
5907
5908                         if (skb == NULL) {
5909                                 i++;
5910                                 continue;
5911                         }
5912
5913                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5914
5915                         txp->skb = NULL;
5916
5917                         i += skb_shinfo(skb)->nr_frags + 1;
5918
5919                         dev_kfree_skb_any(skb);
5920                 }
5921         }
5922
5923         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5924 }
5925
5926 /* Initialize tx/rx rings for packet processing.
5927  *
5928  * The chip has been shut down and the driver detached from
5929  * the networking, so no interrupts or new tx packets will
5930  * end up in the driver.  tp->{tx,}lock are held and thus
5931  * we may not sleep.
5932  */
5933 static int tg3_init_rings(struct tg3 *tp)
5934 {
5935         int i;
5936
5937         /* Free up all the SKBs. */
5938         tg3_free_rings(tp);
5939
5940         for (i = 0; i < tp->irq_cnt; i++) {
5941                 struct tg3_napi *tnapi = &tp->napi[i];
5942
5943                 tnapi->last_tag = 0;
5944                 tnapi->last_irq_tag = 0;
5945                 tnapi->hw_status->status = 0;
5946                 tnapi->hw_status->status_tag = 0;
5947                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5948
5949                 tnapi->tx_prod = 0;
5950                 tnapi->tx_cons = 0;
5951                 if (tnapi->tx_ring)
5952                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5953
5954                 tnapi->rx_rcb_ptr = 0;
5955                 if (tnapi->rx_rcb)
5956                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5957         }
5958
5959         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5960 }
5961
5962 /*
5963  * Must not be invoked with interrupt sources disabled and
5964  * the hardware shutdown down.
5965  */
5966 static void tg3_free_consistent(struct tg3 *tp)
5967 {
5968         int i;
5969
5970         for (i = 0; i < tp->irq_cnt; i++) {
5971                 struct tg3_napi *tnapi = &tp->napi[i];
5972
5973                 if (tnapi->tx_ring) {
5974                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5975                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5976                         tnapi->tx_ring = NULL;
5977                 }
5978
5979                 kfree(tnapi->tx_buffers);
5980                 tnapi->tx_buffers = NULL;
5981
5982                 if (tnapi->rx_rcb) {
5983                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5984                                             tnapi->rx_rcb,
5985                                             tnapi->rx_rcb_mapping);
5986                         tnapi->rx_rcb = NULL;
5987                 }
5988
5989                 if (tnapi->hw_status) {
5990                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5991                                             tnapi->hw_status,
5992                                             tnapi->status_mapping);
5993                         tnapi->hw_status = NULL;
5994                 }
5995         }
5996
5997         if (tp->hw_stats) {
5998                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5999                                     tp->hw_stats, tp->stats_mapping);
6000                 tp->hw_stats = NULL;
6001         }
6002
6003         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
6004 }
6005
6006 /*
6007  * Must not be invoked with interrupt sources disabled and
6008  * the hardware shutdown down.  Can sleep.
6009  */
6010 static int tg3_alloc_consistent(struct tg3 *tp)
6011 {
6012         int i;
6013
6014         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
6015                 return -ENOMEM;
6016
6017         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6018                                             sizeof(struct tg3_hw_stats),
6019                                             &tp->stats_mapping);
6020         if (!tp->hw_stats)
6021                 goto err_out;
6022
6023         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6024
6025         for (i = 0; i < tp->irq_cnt; i++) {
6026                 struct tg3_napi *tnapi = &tp->napi[i];
6027                 struct tg3_hw_status *sblk;
6028
6029                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6030                                                         TG3_HW_STATUS_SIZE,
6031                                                         &tnapi->status_mapping);
6032                 if (!tnapi->hw_status)
6033                         goto err_out;
6034
6035                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6036                 sblk = tnapi->hw_status;
6037
6038                 /*
6039                  * When RSS is enabled, the status block format changes
6040                  * slightly.  The "rx_jumbo_consumer", "reserved",
6041                  * and "rx_mini_consumer" members get mapped to the
6042                  * other three rx return ring producer indexes.
6043                  */
6044                 switch (i) {
6045                 default:
6046                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6047                         break;
6048                 case 2:
6049                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6050                         break;
6051                 case 3:
6052                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6053                         break;
6054                 case 4:
6055                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6056                         break;
6057                 }
6058
6059                 /*
6060                  * If multivector RSS is enabled, vector 0 does not handle
6061                  * rx or tx interrupts.  Don't allocate any resources for it.
6062                  */
6063                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6064                         continue;
6065
6066                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6067                                                      TG3_RX_RCB_RING_BYTES(tp),
6068                                                      &tnapi->rx_rcb_mapping);
6069                 if (!tnapi->rx_rcb)
6070                         goto err_out;
6071
6072                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6073
6074                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6075                                             TG3_TX_RING_SIZE, GFP_KERNEL);
6076                 if (!tnapi->tx_buffers)
6077                         goto err_out;
6078
6079                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6080                                                       TG3_TX_RING_BYTES,
6081                                                       &tnapi->tx_desc_mapping);
6082                 if (!tnapi->tx_ring)
6083                         goto err_out;
6084         }
6085
6086         return 0;
6087
6088 err_out:
6089         tg3_free_consistent(tp);
6090         return -ENOMEM;
6091 }
6092
6093 #define MAX_WAIT_CNT 1000
6094
6095 /* To stop a block, clear the enable bit and poll till it
6096  * clears.  tp->lock is held.
6097  */
6098 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6099 {
6100         unsigned int i;
6101         u32 val;
6102
6103         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6104                 switch (ofs) {
6105                 case RCVLSC_MODE:
6106                 case DMAC_MODE:
6107                 case MBFREE_MODE:
6108                 case BUFMGR_MODE:
6109                 case MEMARB_MODE:
6110                         /* We can't enable/disable these bits of the
6111                          * 5705/5750, just say success.
6112                          */
6113                         return 0;
6114
6115                 default:
6116                         break;
6117                 }
6118         }
6119
6120         val = tr32(ofs);
6121         val &= ~enable_bit;
6122         tw32_f(ofs, val);
6123
6124         for (i = 0; i < MAX_WAIT_CNT; i++) {
6125                 udelay(100);
6126                 val = tr32(ofs);
6127                 if ((val & enable_bit) == 0)
6128                         break;
6129         }
6130
6131         if (i == MAX_WAIT_CNT && !silent) {
6132                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6133                        "ofs=%lx enable_bit=%x\n",
6134                        ofs, enable_bit);
6135                 return -ENODEV;
6136         }
6137
6138         return 0;
6139 }
6140
6141 /* tp->lock is held. */
6142 static int tg3_abort_hw(struct tg3 *tp, int silent)
6143 {
6144         int i, err;
6145
6146         tg3_disable_ints(tp);
6147
6148         tp->rx_mode &= ~RX_MODE_ENABLE;
6149         tw32_f(MAC_RX_MODE, tp->rx_mode);
6150         udelay(10);
6151
6152         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6153         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6154         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6155         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6156         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6157         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6158
6159         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6160         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6161         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6162         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6163         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6164         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6165         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6166
6167         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6168         tw32_f(MAC_MODE, tp->mac_mode);
6169         udelay(40);
6170
6171         tp->tx_mode &= ~TX_MODE_ENABLE;
6172         tw32_f(MAC_TX_MODE, tp->tx_mode);
6173
6174         for (i = 0; i < MAX_WAIT_CNT; i++) {
6175                 udelay(100);
6176                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6177                         break;
6178         }
6179         if (i >= MAX_WAIT_CNT) {
6180                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6181                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6182                        tp->dev->name, tr32(MAC_TX_MODE));
6183                 err |= -ENODEV;
6184         }
6185
6186         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6187         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6188         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6189
6190         tw32(FTQ_RESET, 0xffffffff);
6191         tw32(FTQ_RESET, 0x00000000);
6192
6193         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6194         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6195
6196         for (i = 0; i < tp->irq_cnt; i++) {
6197                 struct tg3_napi *tnapi = &tp->napi[i];
6198                 if (tnapi->hw_status)
6199                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6200         }
6201         if (tp->hw_stats)
6202                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6203
6204         return err;
6205 }
6206
6207 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6208 {
6209         int i;
6210         u32 apedata;
6211
6212         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6213         if (apedata != APE_SEG_SIG_MAGIC)
6214                 return;
6215
6216         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6217         if (!(apedata & APE_FW_STATUS_READY))
6218                 return;
6219
6220         /* Wait for up to 1 millisecond for APE to service previous event. */
6221         for (i = 0; i < 10; i++) {
6222                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6223                         return;
6224
6225                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6226
6227                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6228                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6229                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6230
6231                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6232
6233                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6234                         break;
6235
6236                 udelay(100);
6237         }
6238
6239         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6240                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6241 }
6242
6243 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6244 {
6245         u32 event;
6246         u32 apedata;
6247
6248         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6249                 return;
6250
6251         switch (kind) {
6252                 case RESET_KIND_INIT:
6253                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6254                                         APE_HOST_SEG_SIG_MAGIC);
6255                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6256                                         APE_HOST_SEG_LEN_MAGIC);
6257                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6258                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6259                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6260                                         APE_HOST_DRIVER_ID_MAGIC);
6261                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6262                                         APE_HOST_BEHAV_NO_PHYLOCK);
6263
6264                         event = APE_EVENT_STATUS_STATE_START;
6265                         break;
6266                 case RESET_KIND_SHUTDOWN:
6267                         /* With the interface we are currently using,
6268                          * APE does not track driver state.  Wiping
6269                          * out the HOST SEGMENT SIGNATURE forces
6270                          * the APE to assume OS absent status.
6271                          */
6272                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6273
6274                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6275                         break;
6276                 case RESET_KIND_SUSPEND:
6277                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6278                         break;
6279                 default:
6280                         return;
6281         }
6282
6283         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6284
6285         tg3_ape_send_event(tp, event);
6286 }
6287
6288 /* tp->lock is held. */
6289 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6290 {
6291         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6292                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6293
6294         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6295                 switch (kind) {
6296                 case RESET_KIND_INIT:
6297                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6298                                       DRV_STATE_START);
6299                         break;
6300
6301                 case RESET_KIND_SHUTDOWN:
6302                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6303                                       DRV_STATE_UNLOAD);
6304                         break;
6305
6306                 case RESET_KIND_SUSPEND:
6307                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6308                                       DRV_STATE_SUSPEND);
6309                         break;
6310
6311                 default:
6312                         break;
6313                 }
6314         }
6315
6316         if (kind == RESET_KIND_INIT ||
6317             kind == RESET_KIND_SUSPEND)
6318                 tg3_ape_driver_state_change(tp, kind);
6319 }
6320
6321 /* tp->lock is held. */
6322 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6323 {
6324         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6325                 switch (kind) {
6326                 case RESET_KIND_INIT:
6327                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6328                                       DRV_STATE_START_DONE);
6329                         break;
6330
6331                 case RESET_KIND_SHUTDOWN:
6332                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6333                                       DRV_STATE_UNLOAD_DONE);
6334                         break;
6335
6336                 default:
6337                         break;
6338                 }
6339         }
6340
6341         if (kind == RESET_KIND_SHUTDOWN)
6342                 tg3_ape_driver_state_change(tp, kind);
6343 }
6344
6345 /* tp->lock is held. */
6346 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6347 {
6348         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6349                 switch (kind) {
6350                 case RESET_KIND_INIT:
6351                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6352                                       DRV_STATE_START);
6353                         break;
6354
6355                 case RESET_KIND_SHUTDOWN:
6356                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6357                                       DRV_STATE_UNLOAD);
6358                         break;
6359
6360                 case RESET_KIND_SUSPEND:
6361                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6362                                       DRV_STATE_SUSPEND);
6363                         break;
6364
6365                 default:
6366                         break;
6367                 }
6368         }
6369 }
6370
6371 static int tg3_poll_fw(struct tg3 *tp)
6372 {
6373         int i;
6374         u32 val;
6375
6376         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6377                 /* Wait up to 20ms for init done. */
6378                 for (i = 0; i < 200; i++) {
6379                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6380                                 return 0;
6381                         udelay(100);
6382                 }
6383                 return -ENODEV;
6384         }
6385
6386         /* Wait for firmware initialization to complete. */
6387         for (i = 0; i < 100000; i++) {
6388                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6389                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6390                         break;
6391                 udelay(10);
6392         }
6393
6394         /* Chip might not be fitted with firmware.  Some Sun onboard
6395          * parts are configured like that.  So don't signal the timeout
6396          * of the above loop as an error, but do report the lack of
6397          * running firmware once.
6398          */
6399         if (i >= 100000 &&
6400             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6401                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6402
6403                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6404                        tp->dev->name);
6405         }
6406
6407         return 0;
6408 }
6409
6410 /* Save PCI command register before chip reset */
6411 static void tg3_save_pci_state(struct tg3 *tp)
6412 {
6413         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6414 }
6415
6416 /* Restore PCI state after chip reset */
6417 static void tg3_restore_pci_state(struct tg3 *tp)
6418 {
6419         u32 val;
6420
6421         /* Re-enable indirect register accesses. */
6422         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6423                                tp->misc_host_ctrl);
6424
6425         /* Set MAX PCI retry to zero. */
6426         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6427         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6428             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6429                 val |= PCISTATE_RETRY_SAME_DMA;
6430         /* Allow reads and writes to the APE register and memory space. */
6431         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6432                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6433                        PCISTATE_ALLOW_APE_SHMEM_WR;
6434         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6435
6436         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6437
6438         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6439                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6440                         pcie_set_readrq(tp->pdev, 4096);
6441                 else {
6442                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6443                                               tp->pci_cacheline_sz);
6444                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6445                                               tp->pci_lat_timer);
6446                 }
6447         }
6448
6449         /* Make sure PCI-X relaxed ordering bit is clear. */
6450         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6451                 u16 pcix_cmd;
6452
6453                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6454                                      &pcix_cmd);
6455                 pcix_cmd &= ~PCI_X_CMD_ERO;
6456                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6457                                       pcix_cmd);
6458         }
6459
6460         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6461
6462                 /* Chip reset on 5780 will reset MSI enable bit,
6463                  * so need to restore it.
6464                  */
6465                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6466                         u16 ctrl;
6467
6468                         pci_read_config_word(tp->pdev,
6469                                              tp->msi_cap + PCI_MSI_FLAGS,
6470                                              &ctrl);
6471                         pci_write_config_word(tp->pdev,
6472                                               tp->msi_cap + PCI_MSI_FLAGS,
6473                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6474                         val = tr32(MSGINT_MODE);
6475                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6476                 }
6477         }
6478 }
6479
6480 static void tg3_stop_fw(struct tg3 *);
6481
6482 /* tp->lock is held. */
6483 static int tg3_chip_reset(struct tg3 *tp)
6484 {
6485         u32 val;
6486         void (*write_op)(struct tg3 *, u32, u32);
6487         int i, err;
6488
6489         tg3_nvram_lock(tp);
6490
6491         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6492
6493         /* No matching tg3_nvram_unlock() after this because
6494          * chip reset below will undo the nvram lock.
6495          */
6496         tp->nvram_lock_cnt = 0;
6497
6498         /* GRC_MISC_CFG core clock reset will clear the memory
6499          * enable bit in PCI register 4 and the MSI enable bit
6500          * on some chips, so we save relevant registers here.
6501          */
6502         tg3_save_pci_state(tp);
6503
6504         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6505             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6506                 tw32(GRC_FASTBOOT_PC, 0);
6507
6508         /*
6509          * We must avoid the readl() that normally takes place.
6510          * It locks machines, causes machine checks, and other
6511          * fun things.  So, temporarily disable the 5701
6512          * hardware workaround, while we do the reset.
6513          */
6514         write_op = tp->write32;
6515         if (write_op == tg3_write_flush_reg32)
6516                 tp->write32 = tg3_write32;
6517
6518         /* Prevent the irq handler from reading or writing PCI registers
6519          * during chip reset when the memory enable bit in the PCI command
6520          * register may be cleared.  The chip does not generate interrupt
6521          * at this time, but the irq handler may still be called due to irq
6522          * sharing or irqpoll.
6523          */
6524         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6525         for (i = 0; i < tp->irq_cnt; i++) {
6526                 struct tg3_napi *tnapi = &tp->napi[i];
6527                 if (tnapi->hw_status) {
6528                         tnapi->hw_status->status = 0;
6529                         tnapi->hw_status->status_tag = 0;
6530                 }
6531                 tnapi->last_tag = 0;
6532                 tnapi->last_irq_tag = 0;
6533         }
6534         smp_mb();
6535
6536         for (i = 0; i < tp->irq_cnt; i++)
6537                 synchronize_irq(tp->napi[i].irq_vec);
6538
6539         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6540                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6541                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6542         }
6543
6544         /* do the reset */
6545         val = GRC_MISC_CFG_CORECLK_RESET;
6546
6547         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6548                 if (tr32(0x7e2c) == 0x60) {
6549                         tw32(0x7e2c, 0x20);
6550                 }
6551                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6552                         tw32(GRC_MISC_CFG, (1 << 29));
6553                         val |= (1 << 29);
6554                 }
6555         }
6556
6557         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6558                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6559                 tw32(GRC_VCPU_EXT_CTRL,
6560                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6561         }
6562
6563         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6564                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6565         tw32(GRC_MISC_CFG, val);
6566
6567         /* restore 5701 hardware bug workaround write method */
6568         tp->write32 = write_op;
6569
6570         /* Unfortunately, we have to delay before the PCI read back.
6571          * Some 575X chips even will not respond to a PCI cfg access
6572          * when the reset command is given to the chip.
6573          *
6574          * How do these hardware designers expect things to work
6575          * properly if the PCI write is posted for a long period
6576          * of time?  It is always necessary to have some method by
6577          * which a register read back can occur to push the write
6578          * out which does the reset.
6579          *
6580          * For most tg3 variants the trick below was working.
6581          * Ho hum...
6582          */
6583         udelay(120);
6584
6585         /* Flush PCI posted writes.  The normal MMIO registers
6586          * are inaccessible at this time so this is the only
6587          * way to make this reliably (actually, this is no longer
6588          * the case, see above).  I tried to use indirect
6589          * register read/write but this upset some 5701 variants.
6590          */
6591         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6592
6593         udelay(120);
6594
6595         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6596                 u16 val16;
6597
6598                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6599                         int i;
6600                         u32 cfg_val;
6601
6602                         /* Wait for link training to complete.  */
6603                         for (i = 0; i < 5000; i++)
6604                                 udelay(100);
6605
6606                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6607                         pci_write_config_dword(tp->pdev, 0xc4,
6608                                                cfg_val | (1 << 15));
6609                 }
6610
6611                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6612                 pci_read_config_word(tp->pdev,
6613                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6614                                      &val16);
6615                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6616                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6617                 /*
6618                  * Older PCIe devices only support the 128 byte
6619                  * MPS setting.  Enforce the restriction.
6620                  */
6621                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6622                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6623                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6624                 pci_write_config_word(tp->pdev,
6625                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6626                                       val16);
6627
6628                 pcie_set_readrq(tp->pdev, 4096);
6629
6630                 /* Clear error status */
6631                 pci_write_config_word(tp->pdev,
6632                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6633                                       PCI_EXP_DEVSTA_CED |
6634                                       PCI_EXP_DEVSTA_NFED |
6635                                       PCI_EXP_DEVSTA_FED |
6636                                       PCI_EXP_DEVSTA_URD);
6637         }
6638
6639         tg3_restore_pci_state(tp);
6640
6641         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6642
6643         val = 0;
6644         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6645                 val = tr32(MEMARB_MODE);
6646         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6647
6648         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6649                 tg3_stop_fw(tp);
6650                 tw32(0x5000, 0x400);
6651         }
6652
6653         tw32(GRC_MODE, tp->grc_mode);
6654
6655         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6656                 val = tr32(0xc4);
6657
6658                 tw32(0xc4, val | (1 << 15));
6659         }
6660
6661         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6662             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6663                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6664                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6665                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6666                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6667         }
6668
6669         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6670                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6671                 tw32_f(MAC_MODE, tp->mac_mode);
6672         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6673                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6674                 tw32_f(MAC_MODE, tp->mac_mode);
6675         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6676                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6677                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6678                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6679                 tw32_f(MAC_MODE, tp->mac_mode);
6680         } else
6681                 tw32_f(MAC_MODE, 0);
6682         udelay(40);
6683
6684         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6685
6686         err = tg3_poll_fw(tp);
6687         if (err)
6688                 return err;
6689
6690         tg3_mdio_start(tp);
6691
6692         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6693                 u8 phy_addr;
6694
6695                 phy_addr = tp->phy_addr;
6696                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6697
6698                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6699                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6700                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6701                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6702                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6703                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6704                 udelay(10);
6705
6706                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6707                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6708                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6709                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6710                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6711                 udelay(10);
6712
6713                 tp->phy_addr = phy_addr;
6714         }
6715
6716         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6717             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6718             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6719             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6720                 val = tr32(0x7c00);
6721
6722                 tw32(0x7c00, val | (1 << 25));
6723         }
6724
6725         /* Reprobe ASF enable state.  */
6726         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6727         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6728         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6729         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6730                 u32 nic_cfg;
6731
6732                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6733                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6734                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6735                         tp->last_event_jiffies = jiffies;
6736                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6737                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6738                 }
6739         }
6740
6741         return 0;
6742 }
6743
6744 /* tp->lock is held. */
6745 static void tg3_stop_fw(struct tg3 *tp)
6746 {
6747         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6748            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6749                 /* Wait for RX cpu to ACK the previous event. */
6750                 tg3_wait_for_event_ack(tp);
6751
6752                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6753
6754                 tg3_generate_fw_event(tp);
6755
6756                 /* Wait for RX cpu to ACK this event. */
6757                 tg3_wait_for_event_ack(tp);
6758         }
6759 }
6760
6761 /* tp->lock is held. */
6762 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6763 {
6764         int err;
6765
6766         tg3_stop_fw(tp);
6767
6768         tg3_write_sig_pre_reset(tp, kind);
6769
6770         tg3_abort_hw(tp, silent);
6771         err = tg3_chip_reset(tp);
6772
6773         __tg3_set_mac_addr(tp, 0);
6774
6775         tg3_write_sig_legacy(tp, kind);
6776         tg3_write_sig_post_reset(tp, kind);
6777
6778         if (err)
6779                 return err;
6780
6781         return 0;
6782 }
6783
6784 #define RX_CPU_SCRATCH_BASE     0x30000
6785 #define RX_CPU_SCRATCH_SIZE     0x04000
6786 #define TX_CPU_SCRATCH_BASE     0x34000
6787 #define TX_CPU_SCRATCH_SIZE     0x04000
6788
6789 /* tp->lock is held. */
6790 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6791 {
6792         int i;
6793
6794         BUG_ON(offset == TX_CPU_BASE &&
6795             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6796
6797         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6798                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6799
6800                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6801                 return 0;
6802         }
6803         if (offset == RX_CPU_BASE) {
6804                 for (i = 0; i < 10000; i++) {
6805                         tw32(offset + CPU_STATE, 0xffffffff);
6806                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6807                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6808                                 break;
6809                 }
6810
6811                 tw32(offset + CPU_STATE, 0xffffffff);
6812                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6813                 udelay(10);
6814         } else {
6815                 for (i = 0; i < 10000; i++) {
6816                         tw32(offset + CPU_STATE, 0xffffffff);
6817                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6818                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6819                                 break;
6820                 }
6821         }
6822
6823         if (i >= 10000) {
6824                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6825                        "and %s CPU\n",
6826                        tp->dev->name,
6827                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6828                 return -ENODEV;
6829         }
6830
6831         /* Clear firmware's nvram arbitration. */
6832         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6833                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6834         return 0;
6835 }
6836
6837 struct fw_info {
6838         unsigned int fw_base;
6839         unsigned int fw_len;
6840         const __be32 *fw_data;
6841 };
6842
6843 /* tp->lock is held. */
6844 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6845                                  int cpu_scratch_size, struct fw_info *info)
6846 {
6847         int err, lock_err, i;
6848         void (*write_op)(struct tg3 *, u32, u32);
6849
6850         if (cpu_base == TX_CPU_BASE &&
6851             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6852                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6853                        "TX cpu firmware on %s which is 5705.\n",
6854                        tp->dev->name);
6855                 return -EINVAL;
6856         }
6857
6858         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6859                 write_op = tg3_write_mem;
6860         else
6861                 write_op = tg3_write_indirect_reg32;
6862
6863         /* It is possible that bootcode is still loading at this point.
6864          * Get the nvram lock first before halting the cpu.
6865          */
6866         lock_err = tg3_nvram_lock(tp);
6867         err = tg3_halt_cpu(tp, cpu_base);
6868         if (!lock_err)
6869                 tg3_nvram_unlock(tp);
6870         if (err)
6871                 goto out;
6872
6873         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6874                 write_op(tp, cpu_scratch_base + i, 0);
6875         tw32(cpu_base + CPU_STATE, 0xffffffff);
6876         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6877         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6878                 write_op(tp, (cpu_scratch_base +
6879                               (info->fw_base & 0xffff) +
6880                               (i * sizeof(u32))),
6881                               be32_to_cpu(info->fw_data[i]));
6882
6883         err = 0;
6884
6885 out:
6886         return err;
6887 }
6888
6889 /* tp->lock is held. */
6890 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6891 {
6892         struct fw_info info;
6893         const __be32 *fw_data;
6894         int err, i;
6895
6896         fw_data = (void *)tp->fw->data;
6897
6898         /* Firmware blob starts with version numbers, followed by
6899            start address and length. We are setting complete length.
6900            length = end_address_of_bss - start_address_of_text.
6901            Remainder is the blob to be loaded contiguously
6902            from start address. */
6903
6904         info.fw_base = be32_to_cpu(fw_data[1]);
6905         info.fw_len = tp->fw->size - 12;
6906         info.fw_data = &fw_data[3];
6907
6908         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6909                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6910                                     &info);
6911         if (err)
6912                 return err;
6913
6914         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6915                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6916                                     &info);
6917         if (err)
6918                 return err;
6919
6920         /* Now startup only the RX cpu. */
6921         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6922         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6923
6924         for (i = 0; i < 5; i++) {
6925                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6926                         break;
6927                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6928                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6929                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6930                 udelay(1000);
6931         }
6932         if (i >= 5) {
6933                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6934                        "to set RX CPU PC, is %08x should be %08x\n",
6935                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6936                        info.fw_base);
6937                 return -ENODEV;
6938         }
6939         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6940         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6941
6942         return 0;
6943 }
6944
6945 /* 5705 needs a special version of the TSO firmware.  */
6946
6947 /* tp->lock is held. */
6948 static int tg3_load_tso_firmware(struct tg3 *tp)
6949 {
6950         struct fw_info info;
6951         const __be32 *fw_data;
6952         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6953         int err, i;
6954
6955         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6956                 return 0;
6957
6958         fw_data = (void *)tp->fw->data;
6959
6960         /* Firmware blob starts with version numbers, followed by
6961            start address and length. We are setting complete length.
6962            length = end_address_of_bss - start_address_of_text.
6963            Remainder is the blob to be loaded contiguously
6964            from start address. */
6965
6966         info.fw_base = be32_to_cpu(fw_data[1]);
6967         cpu_scratch_size = tp->fw_len;
6968         info.fw_len = tp->fw->size - 12;
6969         info.fw_data = &fw_data[3];
6970
6971         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6972                 cpu_base = RX_CPU_BASE;
6973                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6974         } else {
6975                 cpu_base = TX_CPU_BASE;
6976                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6977                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6978         }
6979
6980         err = tg3_load_firmware_cpu(tp, cpu_base,
6981                                     cpu_scratch_base, cpu_scratch_size,
6982                                     &info);
6983         if (err)
6984                 return err;
6985
6986         /* Now startup the cpu. */
6987         tw32(cpu_base + CPU_STATE, 0xffffffff);
6988         tw32_f(cpu_base + CPU_PC, info.fw_base);
6989
6990         for (i = 0; i < 5; i++) {
6991                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6992                         break;
6993                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6994                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6995                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6996                 udelay(1000);
6997         }
6998         if (i >= 5) {
6999                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7000                        "to set CPU PC, is %08x should be %08x\n",
7001                        tp->dev->name, tr32(cpu_base + CPU_PC),
7002                        info.fw_base);
7003                 return -ENODEV;
7004         }
7005         tw32(cpu_base + CPU_STATE, 0xffffffff);
7006         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7007         return 0;
7008 }
7009
7010
7011 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7012 {
7013         struct tg3 *tp = netdev_priv(dev);
7014         struct sockaddr *addr = p;
7015         int err = 0, skip_mac_1 = 0;
7016
7017         if (!is_valid_ether_addr(addr->sa_data))
7018                 return -EINVAL;
7019
7020         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7021
7022         if (!netif_running(dev))
7023                 return 0;
7024
7025         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7026                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7027
7028                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7029                 addr0_low = tr32(MAC_ADDR_0_LOW);
7030                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7031                 addr1_low = tr32(MAC_ADDR_1_LOW);
7032
7033                 /* Skip MAC addr 1 if ASF is using it. */
7034                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7035                     !(addr1_high == 0 && addr1_low == 0))
7036                         skip_mac_1 = 1;
7037         }
7038         spin_lock_bh(&tp->lock);
7039         __tg3_set_mac_addr(tp, skip_mac_1);
7040         spin_unlock_bh(&tp->lock);
7041
7042         return err;
7043 }
7044
7045 /* tp->lock is held. */
7046 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7047                            dma_addr_t mapping, u32 maxlen_flags,
7048                            u32 nic_addr)
7049 {
7050         tg3_write_mem(tp,
7051                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7052                       ((u64) mapping >> 32));
7053         tg3_write_mem(tp,
7054                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7055                       ((u64) mapping & 0xffffffff));
7056         tg3_write_mem(tp,
7057                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7058                        maxlen_flags);
7059
7060         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7061                 tg3_write_mem(tp,
7062                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7063                               nic_addr);
7064 }
7065
7066 static void __tg3_set_rx_mode(struct net_device *);
7067 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7068 {
7069         int i;
7070
7071         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7072                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7073                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7074                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7075
7076                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7077                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7078                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7079         } else {
7080                 tw32(HOSTCC_TXCOL_TICKS, 0);
7081                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7082                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7083
7084                 tw32(HOSTCC_RXCOL_TICKS, 0);
7085                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7086                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7087         }
7088
7089         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7090                 u32 val = ec->stats_block_coalesce_usecs;
7091
7092                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7093                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7094
7095                 if (!netif_carrier_ok(tp->dev))
7096                         val = 0;
7097
7098                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7099         }
7100
7101         for (i = 0; i < tp->irq_cnt - 1; i++) {
7102                 u32 reg;
7103
7104                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7105                 tw32(reg, ec->rx_coalesce_usecs);
7106                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7107                 tw32(reg, ec->tx_coalesce_usecs);
7108                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7109                 tw32(reg, ec->rx_max_coalesced_frames);
7110                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7111                 tw32(reg, ec->tx_max_coalesced_frames);
7112                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7113                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7114                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7115                 tw32(reg, ec->tx_max_coalesced_frames_irq);
7116         }
7117
7118         for (; i < tp->irq_max - 1; i++) {
7119                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7120                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7121                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7122                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7123                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7124                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7125         }
7126 }
7127
7128 /* tp->lock is held. */
7129 static void tg3_rings_reset(struct tg3 *tp)
7130 {
7131         int i;
7132         u32 stblk, txrcb, rxrcb, limit;
7133         struct tg3_napi *tnapi = &tp->napi[0];
7134
7135         /* Disable all transmit rings but the first. */
7136         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7137                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7138         else
7139                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7140
7141         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7142              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7143                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7144                               BDINFO_FLAGS_DISABLED);
7145
7146
7147         /* Disable all receive return rings but the first. */
7148         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7149                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7150         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7151                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7152         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7153                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7154         else
7155                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7156
7157         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7158              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7159                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7160                               BDINFO_FLAGS_DISABLED);
7161
7162         /* Disable interrupts */
7163         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7164
7165         /* Zero mailbox registers. */
7166         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7167                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7168                         tp->napi[i].tx_prod = 0;
7169                         tp->napi[i].tx_cons = 0;
7170                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7171                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7172                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7173                 }
7174         } else {
7175                 tp->napi[0].tx_prod = 0;
7176                 tp->napi[0].tx_cons = 0;
7177                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7178                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7179         }
7180
7181         /* Make sure the NIC-based send BD rings are disabled. */
7182         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7183                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7184                 for (i = 0; i < 16; i++)
7185                         tw32_tx_mbox(mbox + i * 8, 0);
7186         }
7187
7188         txrcb = NIC_SRAM_SEND_RCB;
7189         rxrcb = NIC_SRAM_RCV_RET_RCB;
7190
7191         /* Clear status block in ram. */
7192         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7193
7194         /* Set status block DMA address */
7195         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7196              ((u64) tnapi->status_mapping >> 32));
7197         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7198              ((u64) tnapi->status_mapping & 0xffffffff));
7199
7200         if (tnapi->tx_ring) {
7201                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7202                                (TG3_TX_RING_SIZE <<
7203                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7204                                NIC_SRAM_TX_BUFFER_DESC);
7205                 txrcb += TG3_BDINFO_SIZE;
7206         }
7207
7208         if (tnapi->rx_rcb) {
7209                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7210                                (TG3_RX_RCB_RING_SIZE(tp) <<
7211                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7212                 rxrcb += TG3_BDINFO_SIZE;
7213         }
7214
7215         stblk = HOSTCC_STATBLCK_RING1;
7216
7217         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7218                 u64 mapping = (u64)tnapi->status_mapping;
7219                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7220                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7221
7222                 /* Clear status block in ram. */
7223                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7224
7225                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7226                                (TG3_TX_RING_SIZE <<
7227                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7228                                NIC_SRAM_TX_BUFFER_DESC);
7229
7230                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7231                                (TG3_RX_RCB_RING_SIZE(tp) <<
7232                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7233
7234                 stblk += 8;
7235                 txrcb += TG3_BDINFO_SIZE;
7236                 rxrcb += TG3_BDINFO_SIZE;
7237         }
7238 }
7239
7240 /* tp->lock is held. */
7241 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7242 {
7243         u32 val, rdmac_mode;
7244         int i, err, limit;
7245         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7246
7247         tg3_disable_ints(tp);
7248
7249         tg3_stop_fw(tp);
7250
7251         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7252
7253         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7254                 tg3_abort_hw(tp, 1);
7255         }
7256
7257         if (reset_phy &&
7258             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7259                 tg3_phy_reset(tp);
7260
7261         err = tg3_chip_reset(tp);
7262         if (err)
7263                 return err;
7264
7265         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7266
7267         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7268                 val = tr32(TG3_CPMU_CTRL);
7269                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7270                 tw32(TG3_CPMU_CTRL, val);
7271
7272                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7273                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7274                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7275                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7276
7277                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7278                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7279                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7280                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7281
7282                 val = tr32(TG3_CPMU_HST_ACC);
7283                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7284                 val |= CPMU_HST_ACC_MACCLK_6_25;
7285                 tw32(TG3_CPMU_HST_ACC, val);
7286         }
7287
7288         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7289                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7290                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7291                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7292                 tw32(PCIE_PWR_MGMT_THRESH, val);
7293
7294                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7295                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7296
7297                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7298
7299                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7300                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7301         }
7302
7303         /* This works around an issue with Athlon chipsets on
7304          * B3 tigon3 silicon.  This bit has no effect on any
7305          * other revision.  But do not set this on PCI Express
7306          * chips and don't even touch the clocks if the CPMU is present.
7307          */
7308         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7309                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7310                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7311                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7312         }
7313
7314         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7315             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7316                 val = tr32(TG3PCI_PCISTATE);
7317                 val |= PCISTATE_RETRY_SAME_DMA;
7318                 tw32(TG3PCI_PCISTATE, val);
7319         }
7320
7321         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7322                 /* Allow reads and writes to the
7323                  * APE register and memory space.
7324                  */
7325                 val = tr32(TG3PCI_PCISTATE);
7326                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7327                        PCISTATE_ALLOW_APE_SHMEM_WR;
7328                 tw32(TG3PCI_PCISTATE, val);
7329         }
7330
7331         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7332                 /* Enable some hw fixes.  */
7333                 val = tr32(TG3PCI_MSI_DATA);
7334                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7335                 tw32(TG3PCI_MSI_DATA, val);
7336         }
7337
7338         /* Descriptor ring init may make accesses to the
7339          * NIC SRAM area to setup the TX descriptors, so we
7340          * can only do this after the hardware has been
7341          * successfully reset.
7342          */
7343         err = tg3_init_rings(tp);
7344         if (err)
7345                 return err;
7346
7347         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7348                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7349                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7350                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7351         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7352                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7353                 /* This value is determined during the probe time DMA
7354                  * engine test, tg3_test_dma.
7355                  */
7356                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7357         }
7358
7359         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7360                           GRC_MODE_4X_NIC_SEND_RINGS |
7361                           GRC_MODE_NO_TX_PHDR_CSUM |
7362                           GRC_MODE_NO_RX_PHDR_CSUM);
7363         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7364
7365         /* Pseudo-header checksum is done by hardware logic and not
7366          * the offload processers, so make the chip do the pseudo-
7367          * header checksums on receive.  For transmit it is more
7368          * convenient to do the pseudo-header checksum in software
7369          * as Linux does that on transmit for us in all cases.
7370          */
7371         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7372
7373         tw32(GRC_MODE,
7374              tp->grc_mode |
7375              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7376
7377         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7378         val = tr32(GRC_MISC_CFG);
7379         val &= ~0xff;
7380         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7381         tw32(GRC_MISC_CFG, val);
7382
7383         /* Initialize MBUF/DESC pool. */
7384         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7385                 /* Do nothing.  */
7386         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7387                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7388                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7389                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7390                 else
7391                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7392                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7393                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7394         }
7395         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7396                 int fw_len;
7397
7398                 fw_len = tp->fw_len;
7399                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7400                 tw32(BUFMGR_MB_POOL_ADDR,
7401                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7402                 tw32(BUFMGR_MB_POOL_SIZE,
7403                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7404         }
7405
7406         if (tp->dev->mtu <= ETH_DATA_LEN) {
7407                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7408                      tp->bufmgr_config.mbuf_read_dma_low_water);
7409                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7410                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7411                 tw32(BUFMGR_MB_HIGH_WATER,
7412                      tp->bufmgr_config.mbuf_high_water);
7413         } else {
7414                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7415                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7416                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7417                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7418                 tw32(BUFMGR_MB_HIGH_WATER,
7419                      tp->bufmgr_config.mbuf_high_water_jumbo);
7420         }
7421         tw32(BUFMGR_DMA_LOW_WATER,
7422              tp->bufmgr_config.dma_low_water);
7423         tw32(BUFMGR_DMA_HIGH_WATER,
7424              tp->bufmgr_config.dma_high_water);
7425
7426         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7427         for (i = 0; i < 2000; i++) {
7428                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7429                         break;
7430                 udelay(10);
7431         }
7432         if (i >= 2000) {
7433                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7434                        tp->dev->name);
7435                 return -ENODEV;
7436         }
7437
7438         /* Setup replenish threshold. */
7439         val = tp->rx_pending / 8;
7440         if (val == 0)
7441                 val = 1;
7442         else if (val > tp->rx_std_max_post)
7443                 val = tp->rx_std_max_post;
7444         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7445                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7446                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7447
7448                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7449                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7450         }
7451
7452         tw32(RCVBDI_STD_THRESH, val);
7453
7454         /* Initialize TG3_BDINFO's at:
7455          *  RCVDBDI_STD_BD:     standard eth size rx ring
7456          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7457          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7458          *
7459          * like so:
7460          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7461          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7462          *                              ring attribute flags
7463          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7464          *
7465          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7466          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7467          *
7468          * The size of each ring is fixed in the firmware, but the location is
7469          * configurable.
7470          */
7471         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7472              ((u64) tpr->rx_std_mapping >> 32));
7473         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7474              ((u64) tpr->rx_std_mapping & 0xffffffff));
7475         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7476                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7477                      NIC_SRAM_RX_BUFFER_DESC);
7478
7479         /* Disable the mini ring */
7480         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7481                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7482                      BDINFO_FLAGS_DISABLED);
7483
7484         /* Program the jumbo buffer descriptor ring control
7485          * blocks on those devices that have them.
7486          */
7487         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7488             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7489                 /* Setup replenish threshold. */
7490                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7491
7492                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7493                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7494                              ((u64) tpr->rx_jmb_mapping >> 32));
7495                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7496                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7497                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7498                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7499                              BDINFO_FLAGS_USE_EXT_RECV);
7500                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7501                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7502                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7503                 } else {
7504                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7505                              BDINFO_FLAGS_DISABLED);
7506                 }
7507
7508                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7509                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7510                               (RX_STD_MAX_SIZE << 2);
7511                 else
7512                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7513         } else
7514                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7515
7516         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7517
7518         tpr->rx_std_ptr = tp->rx_pending;
7519         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7520                      tpr->rx_std_ptr);
7521
7522         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7523                           tp->rx_jumbo_pending : 0;
7524         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7525                      tpr->rx_jmb_ptr);
7526
7527         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7528                 tw32(STD_REPLENISH_LWM, 32);
7529                 tw32(JMB_REPLENISH_LWM, 16);
7530         }
7531
7532         tg3_rings_reset(tp);
7533
7534         /* Initialize MAC address and backoff seed. */
7535         __tg3_set_mac_addr(tp, 0);
7536
7537         /* MTU + ethernet header + FCS + optional VLAN tag */
7538         tw32(MAC_RX_MTU_SIZE,
7539              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7540
7541         /* The slot time is changed by tg3_setup_phy if we
7542          * run at gigabit with half duplex.
7543          */
7544         tw32(MAC_TX_LENGTHS,
7545              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7546              (6 << TX_LENGTHS_IPG_SHIFT) |
7547              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7548
7549         /* Receive rules. */
7550         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7551         tw32(RCVLPC_CONFIG, 0x0181);
7552
7553         /* Calculate RDMAC_MODE setting early, we need it to determine
7554          * the RCVLPC_STATE_ENABLE mask.
7555          */
7556         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7557                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7558                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7559                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7560                       RDMAC_MODE_LNGREAD_ENAB);
7561
7562         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7563             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7564             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7565                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7566                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7567                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7568
7569         /* If statement applies to 5705 and 5750 PCI devices only */
7570         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7571              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7572             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7573                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7574                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7575                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7576                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7577                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7578                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7579                 }
7580         }
7581
7582         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7583                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7584
7585         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7586                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7587
7588         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7589             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7590             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7591                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7592
7593         /* Receive/send statistics. */
7594         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7595                 val = tr32(RCVLPC_STATS_ENABLE);
7596                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7597                 tw32(RCVLPC_STATS_ENABLE, val);
7598         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7599                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7600                 val = tr32(RCVLPC_STATS_ENABLE);
7601                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7602                 tw32(RCVLPC_STATS_ENABLE, val);
7603         } else {
7604                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7605         }
7606         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7607         tw32(SNDDATAI_STATSENAB, 0xffffff);
7608         tw32(SNDDATAI_STATSCTRL,
7609              (SNDDATAI_SCTRL_ENABLE |
7610               SNDDATAI_SCTRL_FASTUPD));
7611
7612         /* Setup host coalescing engine. */
7613         tw32(HOSTCC_MODE, 0);
7614         for (i = 0; i < 2000; i++) {
7615                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7616                         break;
7617                 udelay(10);
7618         }
7619
7620         __tg3_set_coalesce(tp, &tp->coal);
7621
7622         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7623                 /* Status/statistics block address.  See tg3_timer,
7624                  * the tg3_periodic_fetch_stats call there, and
7625                  * tg3_get_stats to see how this works for 5705/5750 chips.
7626                  */
7627                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7628                      ((u64) tp->stats_mapping >> 32));
7629                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7630                      ((u64) tp->stats_mapping & 0xffffffff));
7631                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7632
7633                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7634
7635                 /* Clear statistics and status block memory areas */
7636                 for (i = NIC_SRAM_STATS_BLK;
7637                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7638                      i += sizeof(u32)) {
7639                         tg3_write_mem(tp, i, 0);
7640                         udelay(40);
7641                 }
7642         }
7643
7644         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7645
7646         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7647         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7648         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7649                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7650
7651         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7652                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7653                 /* reset to prevent losing 1st rx packet intermittently */
7654                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7655                 udelay(10);
7656         }
7657
7658         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7659                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7660         else
7661                 tp->mac_mode = 0;
7662         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7663                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7664         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7665             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7666             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7667                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7668         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7669         udelay(40);
7670
7671         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7672          * If TG3_FLG2_IS_NIC is zero, we should read the
7673          * register to preserve the GPIO settings for LOMs. The GPIOs,
7674          * whether used as inputs or outputs, are set by boot code after
7675          * reset.
7676          */
7677         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7678                 u32 gpio_mask;
7679
7680                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7681                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7682                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7683
7684                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7685                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7686                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7687
7688                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7689                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7690
7691                 tp->grc_local_ctrl &= ~gpio_mask;
7692                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7693
7694                 /* GPIO1 must be driven high for eeprom write protect */
7695                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7696                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7697                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7698         }
7699         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7700         udelay(100);
7701
7702         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7703                 val = tr32(MSGINT_MODE);
7704                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7705                 tw32(MSGINT_MODE, val);
7706         }
7707
7708         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7709                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7710                 udelay(40);
7711         }
7712
7713         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7714                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7715                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7716                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7717                WDMAC_MODE_LNGREAD_ENAB);
7718
7719         /* If statement applies to 5705 and 5750 PCI devices only */
7720         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7721              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7722             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7723                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7724                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7725                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7726                         /* nothing */
7727                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7728                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7729                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7730                         val |= WDMAC_MODE_RX_ACCEL;
7731                 }
7732         }
7733
7734         /* Enable host coalescing bug fix */
7735         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7736                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7737
7738         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7739                 val |= WDMAC_MODE_BURST_ALL_DATA;
7740
7741         tw32_f(WDMAC_MODE, val);
7742         udelay(40);
7743
7744         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7745                 u16 pcix_cmd;
7746
7747                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7748                                      &pcix_cmd);
7749                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7750                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7751                         pcix_cmd |= PCI_X_CMD_READ_2K;
7752                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7753                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7754                         pcix_cmd |= PCI_X_CMD_READ_2K;
7755                 }
7756                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7757                                       pcix_cmd);
7758         }
7759
7760         tw32_f(RDMAC_MODE, rdmac_mode);
7761         udelay(40);
7762
7763         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7764         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7765                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7766
7767         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7768                 tw32(SNDDATAC_MODE,
7769                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7770         else
7771                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7772
7773         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7774         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7775         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7776         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7777         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7778                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7779         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7780         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7781                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7782         tw32(SNDBDI_MODE, val);
7783         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7784
7785         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7786                 err = tg3_load_5701_a0_firmware_fix(tp);
7787                 if (err)
7788                         return err;
7789         }
7790
7791         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7792                 err = tg3_load_tso_firmware(tp);
7793                 if (err)
7794                         return err;
7795         }
7796
7797         tp->tx_mode = TX_MODE_ENABLE;
7798         tw32_f(MAC_TX_MODE, tp->tx_mode);
7799         udelay(100);
7800
7801         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7802                 u32 reg = MAC_RSS_INDIR_TBL_0;
7803                 u8 *ent = (u8 *)&val;
7804
7805                 /* Setup the indirection table */
7806                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7807                         int idx = i % sizeof(val);
7808
7809                         ent[idx] = i % (tp->irq_cnt - 1);
7810                         if (idx == sizeof(val) - 1) {
7811                                 tw32(reg, val);
7812                                 reg += 4;
7813                         }
7814                 }
7815
7816                 /* Setup the "secret" hash key. */
7817                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7818                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7819                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7820                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7821                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7822                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7823                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7824                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7825                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7826                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7827         }
7828
7829         tp->rx_mode = RX_MODE_ENABLE;
7830         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7831                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7832
7833         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7834                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7835                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7836                                RX_MODE_RSS_IPV6_HASH_EN |
7837                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7838                                RX_MODE_RSS_IPV4_HASH_EN |
7839                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7840
7841         tw32_f(MAC_RX_MODE, tp->rx_mode);
7842         udelay(10);
7843
7844         tw32(MAC_LED_CTRL, tp->led_ctrl);
7845
7846         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7847         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7848                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7849                 udelay(10);
7850         }
7851         tw32_f(MAC_RX_MODE, tp->rx_mode);
7852         udelay(10);
7853
7854         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7855                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7856                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7857                         /* Set drive transmission level to 1.2V  */
7858                         /* only if the signal pre-emphasis bit is not set  */
7859                         val = tr32(MAC_SERDES_CFG);
7860                         val &= 0xfffff000;
7861                         val |= 0x880;
7862                         tw32(MAC_SERDES_CFG, val);
7863                 }
7864                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7865                         tw32(MAC_SERDES_CFG, 0x616000);
7866         }
7867
7868         /* Prevent chip from dropping frames when flow control
7869          * is enabled.
7870          */
7871         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7872
7873         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7874             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7875                 /* Use hardware link auto-negotiation */
7876                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7877         }
7878
7879         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7880             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7881                 u32 tmp;
7882
7883                 tmp = tr32(SERDES_RX_CTRL);
7884                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7885                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7886                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7887                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7888         }
7889
7890         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7891                 if (tp->link_config.phy_is_low_power) {
7892                         tp->link_config.phy_is_low_power = 0;
7893                         tp->link_config.speed = tp->link_config.orig_speed;
7894                         tp->link_config.duplex = tp->link_config.orig_duplex;
7895                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7896                 }
7897
7898                 err = tg3_setup_phy(tp, 0);
7899                 if (err)
7900                         return err;
7901
7902                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7903                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7904                         u32 tmp;
7905
7906                         /* Clear CRC stats. */
7907                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7908                                 tg3_writephy(tp, MII_TG3_TEST1,
7909                                              tmp | MII_TG3_TEST1_CRC_EN);
7910                                 tg3_readphy(tp, 0x14, &tmp);
7911                         }
7912                 }
7913         }
7914
7915         __tg3_set_rx_mode(tp->dev);
7916
7917         /* Initialize receive rules. */
7918         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7919         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7920         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7921         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7922
7923         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7924             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7925                 limit = 8;
7926         else
7927                 limit = 16;
7928         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7929                 limit -= 4;
7930         switch (limit) {
7931         case 16:
7932                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7933         case 15:
7934                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7935         case 14:
7936                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7937         case 13:
7938                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7939         case 12:
7940                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7941         case 11:
7942                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7943         case 10:
7944                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7945         case 9:
7946                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7947         case 8:
7948                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7949         case 7:
7950                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7951         case 6:
7952                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7953         case 5:
7954                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7955         case 4:
7956                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7957         case 3:
7958                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7959         case 2:
7960         case 1:
7961
7962         default:
7963                 break;
7964         }
7965
7966         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7967                 /* Write our heartbeat update interval to APE. */
7968                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7969                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7970
7971         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7972
7973         return 0;
7974 }
7975
7976 /* Called at device open time to get the chip ready for
7977  * packet processing.  Invoked with tp->lock held.
7978  */
7979 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7980 {
7981         tg3_switch_clocks(tp);
7982
7983         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7984
7985         return tg3_reset_hw(tp, reset_phy);
7986 }
7987
7988 #define TG3_STAT_ADD32(PSTAT, REG) \
7989 do {    u32 __val = tr32(REG); \
7990         (PSTAT)->low += __val; \
7991         if ((PSTAT)->low < __val) \
7992                 (PSTAT)->high += 1; \
7993 } while (0)
7994
7995 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7996 {
7997         struct tg3_hw_stats *sp = tp->hw_stats;
7998
7999         if (!netif_carrier_ok(tp->dev))
8000                 return;
8001
8002         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8003         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8004         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8005         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8006         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8007         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8008         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8009         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8010         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8011         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8012         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8013         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8014         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8015
8016         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8017         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8018         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8019         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8020         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8021         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8022         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8023         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8024         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8025         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8026         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8027         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8028         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8029         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8030
8031         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8032         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8033         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8034 }
8035
8036 static void tg3_timer(unsigned long __opaque)
8037 {
8038         struct tg3 *tp = (struct tg3 *) __opaque;
8039
8040         if (tp->irq_sync)
8041                 goto restart_timer;
8042
8043         spin_lock(&tp->lock);
8044
8045         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8046                 /* All of this garbage is because when using non-tagged
8047                  * IRQ status the mailbox/status_block protocol the chip
8048                  * uses with the cpu is race prone.
8049                  */
8050                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8051                         tw32(GRC_LOCAL_CTRL,
8052                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8053                 } else {
8054                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8055                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8056                 }
8057
8058                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8059                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8060                         spin_unlock(&tp->lock);
8061                         schedule_work(&tp->reset_task);
8062                         return;
8063                 }
8064         }
8065
8066         /* This part only runs once per second. */
8067         if (!--tp->timer_counter) {
8068                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8069                         tg3_periodic_fetch_stats(tp);
8070
8071                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8072                         u32 mac_stat;
8073                         int phy_event;
8074
8075                         mac_stat = tr32(MAC_STATUS);
8076
8077                         phy_event = 0;
8078                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8079                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8080                                         phy_event = 1;
8081                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8082                                 phy_event = 1;
8083
8084                         if (phy_event)
8085                                 tg3_setup_phy(tp, 0);
8086                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8087                         u32 mac_stat = tr32(MAC_STATUS);
8088                         int need_setup = 0;
8089
8090                         if (netif_carrier_ok(tp->dev) &&
8091                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8092                                 need_setup = 1;
8093                         }
8094                         if (! netif_carrier_ok(tp->dev) &&
8095                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8096                                          MAC_STATUS_SIGNAL_DET))) {
8097                                 need_setup = 1;
8098                         }
8099                         if (need_setup) {
8100                                 if (!tp->serdes_counter) {
8101                                         tw32_f(MAC_MODE,
8102                                              (tp->mac_mode &
8103                                               ~MAC_MODE_PORT_MODE_MASK));
8104                                         udelay(40);
8105                                         tw32_f(MAC_MODE, tp->mac_mode);
8106                                         udelay(40);
8107                                 }
8108                                 tg3_setup_phy(tp, 0);
8109                         }
8110                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8111                         tg3_serdes_parallel_detect(tp);
8112
8113                 tp->timer_counter = tp->timer_multiplier;
8114         }
8115
8116         /* Heartbeat is only sent once every 2 seconds.
8117          *
8118          * The heartbeat is to tell the ASF firmware that the host
8119          * driver is still alive.  In the event that the OS crashes,
8120          * ASF needs to reset the hardware to free up the FIFO space
8121          * that may be filled with rx packets destined for the host.
8122          * If the FIFO is full, ASF will no longer function properly.
8123          *
8124          * Unintended resets have been reported on real time kernels
8125          * where the timer doesn't run on time.  Netpoll will also have
8126          * same problem.
8127          *
8128          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8129          * to check the ring condition when the heartbeat is expiring
8130          * before doing the reset.  This will prevent most unintended
8131          * resets.
8132          */
8133         if (!--tp->asf_counter) {
8134                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8135                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8136                         tg3_wait_for_event_ack(tp);
8137
8138                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8139                                       FWCMD_NICDRV_ALIVE3);
8140                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8141                         /* 5 seconds timeout */
8142                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8143
8144                         tg3_generate_fw_event(tp);
8145                 }
8146                 tp->asf_counter = tp->asf_multiplier;
8147         }
8148
8149         spin_unlock(&tp->lock);
8150
8151 restart_timer:
8152         tp->timer.expires = jiffies + tp->timer_offset;
8153         add_timer(&tp->timer);
8154 }
8155
8156 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8157 {
8158         irq_handler_t fn;
8159         unsigned long flags;
8160         char *name;
8161         struct tg3_napi *tnapi = &tp->napi[irq_num];
8162
8163         if (tp->irq_cnt == 1)
8164                 name = tp->dev->name;
8165         else {
8166                 name = &tnapi->irq_lbl[0];
8167                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8168                 name[IFNAMSIZ-1] = 0;
8169         }
8170
8171         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8172                 fn = tg3_msi;
8173                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8174                         fn = tg3_msi_1shot;
8175                 flags = IRQF_SAMPLE_RANDOM;
8176         } else {
8177                 fn = tg3_interrupt;
8178                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8179                         fn = tg3_interrupt_tagged;
8180                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8181         }
8182
8183         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8184 }
8185
8186 static int tg3_test_interrupt(struct tg3 *tp)
8187 {
8188         struct tg3_napi *tnapi = &tp->napi[0];
8189         struct net_device *dev = tp->dev;
8190         int err, i, intr_ok = 0;
8191         u32 val;
8192
8193         if (!netif_running(dev))
8194                 return -ENODEV;
8195
8196         tg3_disable_ints(tp);
8197
8198         free_irq(tnapi->irq_vec, tnapi);
8199
8200         /*
8201          * Turn off MSI one shot mode.  Otherwise this test has no
8202          * observable way to know whether the interrupt was delivered.
8203          */
8204         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8205             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8206                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8207                 tw32(MSGINT_MODE, val);
8208         }
8209
8210         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8211                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8212         if (err)
8213                 return err;
8214
8215         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8216         tg3_enable_ints(tp);
8217
8218         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8219                tnapi->coal_now);
8220
8221         for (i = 0; i < 5; i++) {
8222                 u32 int_mbox, misc_host_ctrl;
8223
8224                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8225                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8226
8227                 if ((int_mbox != 0) ||
8228                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8229                         intr_ok = 1;
8230                         break;
8231                 }
8232
8233                 msleep(10);
8234         }
8235
8236         tg3_disable_ints(tp);
8237
8238         free_irq(tnapi->irq_vec, tnapi);
8239
8240         err = tg3_request_irq(tp, 0);
8241
8242         if (err)
8243                 return err;
8244
8245         if (intr_ok) {
8246                 /* Reenable MSI one shot mode. */
8247                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8248                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8249                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8250                         tw32(MSGINT_MODE, val);
8251                 }
8252                 return 0;
8253         }
8254
8255         return -EIO;
8256 }
8257
8258 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8259  * successfully restored
8260  */
8261 static int tg3_test_msi(struct tg3 *tp)
8262 {
8263         int err;
8264         u16 pci_cmd;
8265
8266         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8267                 return 0;
8268
8269         /* Turn off SERR reporting in case MSI terminates with Master
8270          * Abort.
8271          */
8272         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8273         pci_write_config_word(tp->pdev, PCI_COMMAND,
8274                               pci_cmd & ~PCI_COMMAND_SERR);
8275
8276         err = tg3_test_interrupt(tp);
8277
8278         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8279
8280         if (!err)
8281                 return 0;
8282
8283         /* other failures */
8284         if (err != -EIO)
8285                 return err;
8286
8287         /* MSI test failed, go back to INTx mode */
8288         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8289                "switching to INTx mode. Please report this failure to "
8290                "the PCI maintainer and include system chipset information.\n",
8291                        tp->dev->name);
8292
8293         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8294
8295         pci_disable_msi(tp->pdev);
8296
8297         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8298
8299         err = tg3_request_irq(tp, 0);
8300         if (err)
8301                 return err;
8302
8303         /* Need to reset the chip because the MSI cycle may have terminated
8304          * with Master Abort.
8305          */
8306         tg3_full_lock(tp, 1);
8307
8308         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8309         err = tg3_init_hw(tp, 1);
8310
8311         tg3_full_unlock(tp);
8312
8313         if (err)
8314                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8315
8316         return err;
8317 }
8318
8319 static int tg3_request_firmware(struct tg3 *tp)
8320 {
8321         const __be32 *fw_data;
8322
8323         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8324                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8325                        tp->dev->name, tp->fw_needed);
8326                 return -ENOENT;
8327         }
8328
8329         fw_data = (void *)tp->fw->data;
8330
8331         /* Firmware blob starts with version numbers, followed by
8332          * start address and _full_ length including BSS sections
8333          * (which must be longer than the actual data, of course
8334          */
8335
8336         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8337         if (tp->fw_len < (tp->fw->size - 12)) {
8338                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8339                        tp->dev->name, tp->fw_len, tp->fw_needed);
8340                 release_firmware(tp->fw);
8341                 tp->fw = NULL;
8342                 return -EINVAL;
8343         }
8344
8345         /* We no longer need firmware; we have it. */
8346         tp->fw_needed = NULL;
8347         return 0;
8348 }
8349
8350 static bool tg3_enable_msix(struct tg3 *tp)
8351 {
8352         int i, rc, cpus = num_online_cpus();
8353         struct msix_entry msix_ent[tp->irq_max];
8354
8355         if (cpus == 1)
8356                 /* Just fallback to the simpler MSI mode. */
8357                 return false;
8358
8359         /*
8360          * We want as many rx rings enabled as there are cpus.
8361          * The first MSIX vector only deals with link interrupts, etc,
8362          * so we add one to the number of vectors we are requesting.
8363          */
8364         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8365
8366         for (i = 0; i < tp->irq_max; i++) {
8367                 msix_ent[i].entry  = i;
8368                 msix_ent[i].vector = 0;
8369         }
8370
8371         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8372         if (rc != 0) {
8373                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8374                         return false;
8375                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8376                         return false;
8377                 printk(KERN_NOTICE
8378                        "%s: Requested %d MSI-X vectors, received %d\n",
8379                        tp->dev->name, tp->irq_cnt, rc);
8380                 tp->irq_cnt = rc;
8381         }
8382
8383         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8384
8385         for (i = 0; i < tp->irq_max; i++)
8386                 tp->napi[i].irq_vec = msix_ent[i].vector;
8387
8388         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8389
8390         return true;
8391 }
8392
8393 static void tg3_ints_init(struct tg3 *tp)
8394 {
8395         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8396             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8397                 /* All MSI supporting chips should support tagged
8398                  * status.  Assert that this is the case.
8399                  */
8400                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8401                        "Not using MSI.\n", tp->dev->name);
8402                 goto defcfg;
8403         }
8404
8405         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8406                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8407         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8408                  pci_enable_msi(tp->pdev) == 0)
8409                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8410
8411         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8412                 u32 msi_mode = tr32(MSGINT_MODE);
8413                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8414                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8415                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8416         }
8417 defcfg:
8418         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8419                 tp->irq_cnt = 1;
8420                 tp->napi[0].irq_vec = tp->pdev->irq;
8421                 tp->dev->real_num_tx_queues = 1;
8422         }
8423 }
8424
8425 static void tg3_ints_fini(struct tg3 *tp)
8426 {
8427         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8428                 pci_disable_msix(tp->pdev);
8429         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8430                 pci_disable_msi(tp->pdev);
8431         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8432         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8433 }
8434
8435 static int tg3_open(struct net_device *dev)
8436 {
8437         struct tg3 *tp = netdev_priv(dev);
8438         int i, err;
8439
8440         if (tp->fw_needed) {
8441                 err = tg3_request_firmware(tp);
8442                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8443                         if (err)
8444                                 return err;
8445                 } else if (err) {
8446                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8447                                tp->dev->name);
8448                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8449                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8450                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8451                                tp->dev->name);
8452                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8453                 }
8454         }
8455
8456         netif_carrier_off(tp->dev);
8457
8458         err = tg3_set_power_state(tp, PCI_D0);
8459         if (err)
8460                 return err;
8461
8462         tg3_full_lock(tp, 0);
8463
8464         tg3_disable_ints(tp);
8465         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8466
8467         tg3_full_unlock(tp);
8468
8469         /*
8470          * Setup interrupts first so we know how
8471          * many NAPI resources to allocate
8472          */
8473         tg3_ints_init(tp);
8474
8475         /* The placement of this call is tied
8476          * to the setup and use of Host TX descriptors.
8477          */
8478         err = tg3_alloc_consistent(tp);
8479         if (err)
8480                 goto err_out1;
8481
8482         tg3_napi_enable(tp);
8483
8484         for (i = 0; i < tp->irq_cnt; i++) {
8485                 struct tg3_napi *tnapi = &tp->napi[i];
8486                 err = tg3_request_irq(tp, i);
8487                 if (err) {
8488                         for (i--; i >= 0; i--)
8489                                 free_irq(tnapi->irq_vec, tnapi);
8490                         break;
8491                 }
8492         }
8493
8494         if (err)
8495                 goto err_out2;
8496
8497         tg3_full_lock(tp, 0);
8498
8499         err = tg3_init_hw(tp, 1);
8500         if (err) {
8501                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8502                 tg3_free_rings(tp);
8503         } else {
8504                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8505                         tp->timer_offset = HZ;
8506                 else
8507                         tp->timer_offset = HZ / 10;
8508
8509                 BUG_ON(tp->timer_offset > HZ);
8510                 tp->timer_counter = tp->timer_multiplier =
8511                         (HZ / tp->timer_offset);
8512                 tp->asf_counter = tp->asf_multiplier =
8513                         ((HZ / tp->timer_offset) * 2);
8514
8515                 init_timer(&tp->timer);
8516                 tp->timer.expires = jiffies + tp->timer_offset;
8517                 tp->timer.data = (unsigned long) tp;
8518                 tp->timer.function = tg3_timer;
8519         }
8520
8521         tg3_full_unlock(tp);
8522
8523         if (err)
8524                 goto err_out3;
8525
8526         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8527                 err = tg3_test_msi(tp);
8528
8529                 if (err) {
8530                         tg3_full_lock(tp, 0);
8531                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8532                         tg3_free_rings(tp);
8533                         tg3_full_unlock(tp);
8534
8535                         goto err_out2;
8536                 }
8537
8538                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8539                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8540                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8541                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8542
8543                         tw32(PCIE_TRANSACTION_CFG,
8544                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8545                 }
8546         }
8547
8548         tg3_phy_start(tp);
8549
8550         tg3_full_lock(tp, 0);
8551
8552         add_timer(&tp->timer);
8553         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8554         tg3_enable_ints(tp);
8555
8556         tg3_full_unlock(tp);
8557
8558         netif_tx_start_all_queues(dev);
8559
8560         return 0;
8561
8562 err_out3:
8563         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8564                 struct tg3_napi *tnapi = &tp->napi[i];
8565                 free_irq(tnapi->irq_vec, tnapi);
8566         }
8567
8568 err_out2:
8569         tg3_napi_disable(tp);
8570         tg3_free_consistent(tp);
8571
8572 err_out1:
8573         tg3_ints_fini(tp);
8574         return err;
8575 }
8576
8577 #if 0
8578 /*static*/ void tg3_dump_state(struct tg3 *tp)
8579 {
8580         u32 val32, val32_2, val32_3, val32_4, val32_5;
8581         u16 val16;
8582         int i;
8583         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8584
8585         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8586         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8587         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8588                val16, val32);
8589
8590         /* MAC block */
8591         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8592                tr32(MAC_MODE), tr32(MAC_STATUS));
8593         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8594                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8595         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8596                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8597         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8598                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8599
8600         /* Send data initiator control block */
8601         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8602                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8603         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8604                tr32(SNDDATAI_STATSCTRL));
8605
8606         /* Send data completion control block */
8607         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8608
8609         /* Send BD ring selector block */
8610         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8611                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8612
8613         /* Send BD initiator control block */
8614         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8615                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8616
8617         /* Send BD completion control block */
8618         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8619
8620         /* Receive list placement control block */
8621         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8622                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8623         printk("       RCVLPC_STATSCTRL[%08x]\n",
8624                tr32(RCVLPC_STATSCTRL));
8625
8626         /* Receive data and receive BD initiator control block */
8627         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8628                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8629
8630         /* Receive data completion control block */
8631         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8632                tr32(RCVDCC_MODE));
8633
8634         /* Receive BD initiator control block */
8635         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8636                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8637
8638         /* Receive BD completion control block */
8639         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8640                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8641
8642         /* Receive list selector control block */
8643         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8644                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8645
8646         /* Mbuf cluster free block */
8647         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8648                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8649
8650         /* Host coalescing control block */
8651         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8652                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8653         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8654                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8655                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8656         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8657                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8658                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8659         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8660                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8661         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8662                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8663
8664         /* Memory arbiter control block */
8665         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8666                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8667
8668         /* Buffer manager control block */
8669         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8670                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8671         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8672                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8673         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8674                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8675                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8676                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8677
8678         /* Read DMA control block */
8679         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8680                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8681
8682         /* Write DMA control block */
8683         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8684                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8685
8686         /* DMA completion block */
8687         printk("DEBUG: DMAC_MODE[%08x]\n",
8688                tr32(DMAC_MODE));
8689
8690         /* GRC block */
8691         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8692                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8693         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8694                tr32(GRC_LOCAL_CTRL));
8695
8696         /* TG3_BDINFOs */
8697         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8698                tr32(RCVDBDI_JUMBO_BD + 0x0),
8699                tr32(RCVDBDI_JUMBO_BD + 0x4),
8700                tr32(RCVDBDI_JUMBO_BD + 0x8),
8701                tr32(RCVDBDI_JUMBO_BD + 0xc));
8702         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8703                tr32(RCVDBDI_STD_BD + 0x0),
8704                tr32(RCVDBDI_STD_BD + 0x4),
8705                tr32(RCVDBDI_STD_BD + 0x8),
8706                tr32(RCVDBDI_STD_BD + 0xc));
8707         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8708                tr32(RCVDBDI_MINI_BD + 0x0),
8709                tr32(RCVDBDI_MINI_BD + 0x4),
8710                tr32(RCVDBDI_MINI_BD + 0x8),
8711                tr32(RCVDBDI_MINI_BD + 0xc));
8712
8713         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8714         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8715         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8716         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8717         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8718                val32, val32_2, val32_3, val32_4);
8719
8720         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8721         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8722         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8723         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8724         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8725                val32, val32_2, val32_3, val32_4);
8726
8727         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8728         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8729         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8730         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8731         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8732         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8733                val32, val32_2, val32_3, val32_4, val32_5);
8734
8735         /* SW status block */
8736         printk(KERN_DEBUG
8737          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8738                sblk->status,
8739                sblk->status_tag,
8740                sblk->rx_jumbo_consumer,
8741                sblk->rx_consumer,
8742                sblk->rx_mini_consumer,
8743                sblk->idx[0].rx_producer,
8744                sblk->idx[0].tx_consumer);
8745
8746         /* SW statistics block */
8747         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8748                ((u32 *)tp->hw_stats)[0],
8749                ((u32 *)tp->hw_stats)[1],
8750                ((u32 *)tp->hw_stats)[2],
8751                ((u32 *)tp->hw_stats)[3]);
8752
8753         /* Mailboxes */
8754         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8755                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8756                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8757                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8758                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8759
8760         /* NIC side send descriptors. */
8761         for (i = 0; i < 6; i++) {
8762                 unsigned long txd;
8763
8764                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8765                         + (i * sizeof(struct tg3_tx_buffer_desc));
8766                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8767                        i,
8768                        readl(txd + 0x0), readl(txd + 0x4),
8769                        readl(txd + 0x8), readl(txd + 0xc));
8770         }
8771
8772         /* NIC side RX descriptors. */
8773         for (i = 0; i < 6; i++) {
8774                 unsigned long rxd;
8775
8776                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8777                         + (i * sizeof(struct tg3_rx_buffer_desc));
8778                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8779                        i,
8780                        readl(rxd + 0x0), readl(rxd + 0x4),
8781                        readl(rxd + 0x8), readl(rxd + 0xc));
8782                 rxd += (4 * sizeof(u32));
8783                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8784                        i,
8785                        readl(rxd + 0x0), readl(rxd + 0x4),
8786                        readl(rxd + 0x8), readl(rxd + 0xc));
8787         }
8788
8789         for (i = 0; i < 6; i++) {
8790                 unsigned long rxd;
8791
8792                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8793                         + (i * sizeof(struct tg3_rx_buffer_desc));
8794                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8795                        i,
8796                        readl(rxd + 0x0), readl(rxd + 0x4),
8797                        readl(rxd + 0x8), readl(rxd + 0xc));
8798                 rxd += (4 * sizeof(u32));
8799                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8800                        i,
8801                        readl(rxd + 0x0), readl(rxd + 0x4),
8802                        readl(rxd + 0x8), readl(rxd + 0xc));
8803         }
8804 }
8805 #endif
8806
8807 static struct net_device_stats *tg3_get_stats(struct net_device *);
8808 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8809
8810 static int tg3_close(struct net_device *dev)
8811 {
8812         int i;
8813         struct tg3 *tp = netdev_priv(dev);
8814
8815         tg3_napi_disable(tp);
8816         cancel_work_sync(&tp->reset_task);
8817
8818         netif_tx_stop_all_queues(dev);
8819
8820         del_timer_sync(&tp->timer);
8821
8822         tg3_phy_stop(tp);
8823
8824         tg3_full_lock(tp, 1);
8825 #if 0
8826         tg3_dump_state(tp);
8827 #endif
8828
8829         tg3_disable_ints(tp);
8830
8831         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8832         tg3_free_rings(tp);
8833         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8834
8835         tg3_full_unlock(tp);
8836
8837         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8838                 struct tg3_napi *tnapi = &tp->napi[i];
8839                 free_irq(tnapi->irq_vec, tnapi);
8840         }
8841
8842         tg3_ints_fini(tp);
8843
8844         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8845                sizeof(tp->net_stats_prev));
8846         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8847                sizeof(tp->estats_prev));
8848
8849         tg3_free_consistent(tp);
8850
8851         tg3_set_power_state(tp, PCI_D3hot);
8852
8853         netif_carrier_off(tp->dev);
8854
8855         return 0;
8856 }
8857
8858 static inline unsigned long get_stat64(tg3_stat64_t *val)
8859 {
8860         unsigned long ret;
8861
8862 #if (BITS_PER_LONG == 32)
8863         ret = val->low;
8864 #else
8865         ret = ((u64)val->high << 32) | ((u64)val->low);
8866 #endif
8867         return ret;
8868 }
8869
8870 static inline u64 get_estat64(tg3_stat64_t *val)
8871 {
8872        return ((u64)val->high << 32) | ((u64)val->low);
8873 }
8874
8875 static unsigned long calc_crc_errors(struct tg3 *tp)
8876 {
8877         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8878
8879         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8880             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8881              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8882                 u32 val;
8883
8884                 spin_lock_bh(&tp->lock);
8885                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8886                         tg3_writephy(tp, MII_TG3_TEST1,
8887                                      val | MII_TG3_TEST1_CRC_EN);
8888                         tg3_readphy(tp, 0x14, &val);
8889                 } else
8890                         val = 0;
8891                 spin_unlock_bh(&tp->lock);
8892
8893                 tp->phy_crc_errors += val;
8894
8895                 return tp->phy_crc_errors;
8896         }
8897
8898         return get_stat64(&hw_stats->rx_fcs_errors);
8899 }
8900
8901 #define ESTAT_ADD(member) \
8902         estats->member =        old_estats->member + \
8903                                 get_estat64(&hw_stats->member)
8904
8905 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8906 {
8907         struct tg3_ethtool_stats *estats = &tp->estats;
8908         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8909         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8910
8911         if (!hw_stats)
8912                 return old_estats;
8913
8914         ESTAT_ADD(rx_octets);
8915         ESTAT_ADD(rx_fragments);
8916         ESTAT_ADD(rx_ucast_packets);
8917         ESTAT_ADD(rx_mcast_packets);
8918         ESTAT_ADD(rx_bcast_packets);
8919         ESTAT_ADD(rx_fcs_errors);
8920         ESTAT_ADD(rx_align_errors);
8921         ESTAT_ADD(rx_xon_pause_rcvd);
8922         ESTAT_ADD(rx_xoff_pause_rcvd);
8923         ESTAT_ADD(rx_mac_ctrl_rcvd);
8924         ESTAT_ADD(rx_xoff_entered);
8925         ESTAT_ADD(rx_frame_too_long_errors);
8926         ESTAT_ADD(rx_jabbers);
8927         ESTAT_ADD(rx_undersize_packets);
8928         ESTAT_ADD(rx_in_length_errors);
8929         ESTAT_ADD(rx_out_length_errors);
8930         ESTAT_ADD(rx_64_or_less_octet_packets);
8931         ESTAT_ADD(rx_65_to_127_octet_packets);
8932         ESTAT_ADD(rx_128_to_255_octet_packets);
8933         ESTAT_ADD(rx_256_to_511_octet_packets);
8934         ESTAT_ADD(rx_512_to_1023_octet_packets);
8935         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8936         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8937         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8938         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8939         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8940
8941         ESTAT_ADD(tx_octets);
8942         ESTAT_ADD(tx_collisions);
8943         ESTAT_ADD(tx_xon_sent);
8944         ESTAT_ADD(tx_xoff_sent);
8945         ESTAT_ADD(tx_flow_control);
8946         ESTAT_ADD(tx_mac_errors);
8947         ESTAT_ADD(tx_single_collisions);
8948         ESTAT_ADD(tx_mult_collisions);
8949         ESTAT_ADD(tx_deferred);
8950         ESTAT_ADD(tx_excessive_collisions);
8951         ESTAT_ADD(tx_late_collisions);
8952         ESTAT_ADD(tx_collide_2times);
8953         ESTAT_ADD(tx_collide_3times);
8954         ESTAT_ADD(tx_collide_4times);
8955         ESTAT_ADD(tx_collide_5times);
8956         ESTAT_ADD(tx_collide_6times);
8957         ESTAT_ADD(tx_collide_7times);
8958         ESTAT_ADD(tx_collide_8times);
8959         ESTAT_ADD(tx_collide_9times);
8960         ESTAT_ADD(tx_collide_10times);
8961         ESTAT_ADD(tx_collide_11times);
8962         ESTAT_ADD(tx_collide_12times);
8963         ESTAT_ADD(tx_collide_13times);
8964         ESTAT_ADD(tx_collide_14times);
8965         ESTAT_ADD(tx_collide_15times);
8966         ESTAT_ADD(tx_ucast_packets);
8967         ESTAT_ADD(tx_mcast_packets);
8968         ESTAT_ADD(tx_bcast_packets);
8969         ESTAT_ADD(tx_carrier_sense_errors);
8970         ESTAT_ADD(tx_discards);
8971         ESTAT_ADD(tx_errors);
8972
8973         ESTAT_ADD(dma_writeq_full);
8974         ESTAT_ADD(dma_write_prioq_full);
8975         ESTAT_ADD(rxbds_empty);
8976         ESTAT_ADD(rx_discards);
8977         ESTAT_ADD(rx_errors);
8978         ESTAT_ADD(rx_threshold_hit);
8979
8980         ESTAT_ADD(dma_readq_full);
8981         ESTAT_ADD(dma_read_prioq_full);
8982         ESTAT_ADD(tx_comp_queue_full);
8983
8984         ESTAT_ADD(ring_set_send_prod_index);
8985         ESTAT_ADD(ring_status_update);
8986         ESTAT_ADD(nic_irqs);
8987         ESTAT_ADD(nic_avoided_irqs);
8988         ESTAT_ADD(nic_tx_threshold_hit);
8989
8990         return estats;
8991 }
8992
8993 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8994 {
8995         struct tg3 *tp = netdev_priv(dev);
8996         struct net_device_stats *stats = &tp->net_stats;
8997         struct net_device_stats *old_stats = &tp->net_stats_prev;
8998         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8999
9000         if (!hw_stats)
9001                 return old_stats;
9002
9003         stats->rx_packets = old_stats->rx_packets +
9004                 get_stat64(&hw_stats->rx_ucast_packets) +
9005                 get_stat64(&hw_stats->rx_mcast_packets) +
9006                 get_stat64(&hw_stats->rx_bcast_packets);
9007
9008         stats->tx_packets = old_stats->tx_packets +
9009                 get_stat64(&hw_stats->tx_ucast_packets) +
9010                 get_stat64(&hw_stats->tx_mcast_packets) +
9011                 get_stat64(&hw_stats->tx_bcast_packets);
9012
9013         stats->rx_bytes = old_stats->rx_bytes +
9014                 get_stat64(&hw_stats->rx_octets);
9015         stats->tx_bytes = old_stats->tx_bytes +
9016                 get_stat64(&hw_stats->tx_octets);
9017
9018         stats->rx_errors = old_stats->rx_errors +
9019                 get_stat64(&hw_stats->rx_errors);
9020         stats->tx_errors = old_stats->tx_errors +
9021                 get_stat64(&hw_stats->tx_errors) +
9022                 get_stat64(&hw_stats->tx_mac_errors) +
9023                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9024                 get_stat64(&hw_stats->tx_discards);
9025
9026         stats->multicast = old_stats->multicast +
9027                 get_stat64(&hw_stats->rx_mcast_packets);
9028         stats->collisions = old_stats->collisions +
9029                 get_stat64(&hw_stats->tx_collisions);
9030
9031         stats->rx_length_errors = old_stats->rx_length_errors +
9032                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9033                 get_stat64(&hw_stats->rx_undersize_packets);
9034
9035         stats->rx_over_errors = old_stats->rx_over_errors +
9036                 get_stat64(&hw_stats->rxbds_empty);
9037         stats->rx_frame_errors = old_stats->rx_frame_errors +
9038                 get_stat64(&hw_stats->rx_align_errors);
9039         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9040                 get_stat64(&hw_stats->tx_discards);
9041         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9042                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9043
9044         stats->rx_crc_errors = old_stats->rx_crc_errors +
9045                 calc_crc_errors(tp);
9046
9047         stats->rx_missed_errors = old_stats->rx_missed_errors +
9048                 get_stat64(&hw_stats->rx_discards);
9049
9050         return stats;
9051 }
9052
9053 static inline u32 calc_crc(unsigned char *buf, int len)
9054 {
9055         u32 reg;
9056         u32 tmp;
9057         int j, k;
9058
9059         reg = 0xffffffff;
9060
9061         for (j = 0; j < len; j++) {
9062                 reg ^= buf[j];
9063
9064                 for (k = 0; k < 8; k++) {
9065                         tmp = reg & 0x01;
9066
9067                         reg >>= 1;
9068
9069                         if (tmp) {
9070                                 reg ^= 0xedb88320;
9071                         }
9072                 }
9073         }
9074
9075         return ~reg;
9076 }
9077
9078 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9079 {
9080         /* accept or reject all multicast frames */
9081         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9082         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9083         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9084         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9085 }
9086
9087 static void __tg3_set_rx_mode(struct net_device *dev)
9088 {
9089         struct tg3 *tp = netdev_priv(dev);
9090         u32 rx_mode;
9091
9092         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9093                                   RX_MODE_KEEP_VLAN_TAG);
9094
9095         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9096          * flag clear.
9097          */
9098 #if TG3_VLAN_TAG_USED
9099         if (!tp->vlgrp &&
9100             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9101                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9102 #else
9103         /* By definition, VLAN is disabled always in this
9104          * case.
9105          */
9106         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9107                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9108 #endif
9109
9110         if (dev->flags & IFF_PROMISC) {
9111                 /* Promiscuous mode. */
9112                 rx_mode |= RX_MODE_PROMISC;
9113         } else if (dev->flags & IFF_ALLMULTI) {
9114                 /* Accept all multicast. */
9115                 tg3_set_multi (tp, 1);
9116         } else if (dev->mc_count < 1) {
9117                 /* Reject all multicast. */
9118                 tg3_set_multi (tp, 0);
9119         } else {
9120                 /* Accept one or more multicast(s). */
9121                 struct dev_mc_list *mclist;
9122                 unsigned int i;
9123                 u32 mc_filter[4] = { 0, };
9124                 u32 regidx;
9125                 u32 bit;
9126                 u32 crc;
9127
9128                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9129                      i++, mclist = mclist->next) {
9130
9131                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9132                         bit = ~crc & 0x7f;
9133                         regidx = (bit & 0x60) >> 5;
9134                         bit &= 0x1f;
9135                         mc_filter[regidx] |= (1 << bit);
9136                 }
9137
9138                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9139                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9140                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9141                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9142         }
9143
9144         if (rx_mode != tp->rx_mode) {
9145                 tp->rx_mode = rx_mode;
9146                 tw32_f(MAC_RX_MODE, rx_mode);
9147                 udelay(10);
9148         }
9149 }
9150
9151 static void tg3_set_rx_mode(struct net_device *dev)
9152 {
9153         struct tg3 *tp = netdev_priv(dev);
9154
9155         if (!netif_running(dev))
9156                 return;
9157
9158         tg3_full_lock(tp, 0);
9159         __tg3_set_rx_mode(dev);
9160         tg3_full_unlock(tp);
9161 }
9162
9163 #define TG3_REGDUMP_LEN         (32 * 1024)
9164
9165 static int tg3_get_regs_len(struct net_device *dev)
9166 {
9167         return TG3_REGDUMP_LEN;
9168 }
9169
9170 static void tg3_get_regs(struct net_device *dev,
9171                 struct ethtool_regs *regs, void *_p)
9172 {
9173         u32 *p = _p;
9174         struct tg3 *tp = netdev_priv(dev);
9175         u8 *orig_p = _p;
9176         int i;
9177
9178         regs->version = 0;
9179
9180         memset(p, 0, TG3_REGDUMP_LEN);
9181
9182         if (tp->link_config.phy_is_low_power)
9183                 return;
9184
9185         tg3_full_lock(tp, 0);
9186
9187 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9188 #define GET_REG32_LOOP(base,len)                \
9189 do {    p = (u32 *)(orig_p + (base));           \
9190         for (i = 0; i < len; i += 4)            \
9191                 __GET_REG32((base) + i);        \
9192 } while (0)
9193 #define GET_REG32_1(reg)                        \
9194 do {    p = (u32 *)(orig_p + (reg));            \
9195         __GET_REG32((reg));                     \
9196 } while (0)
9197
9198         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9199         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9200         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9201         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9202         GET_REG32_1(SNDDATAC_MODE);
9203         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9204         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9205         GET_REG32_1(SNDBDC_MODE);
9206         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9207         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9208         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9209         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9210         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9211         GET_REG32_1(RCVDCC_MODE);
9212         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9213         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9214         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9215         GET_REG32_1(MBFREE_MODE);
9216         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9217         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9218         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9219         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9220         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9221         GET_REG32_1(RX_CPU_MODE);
9222         GET_REG32_1(RX_CPU_STATE);
9223         GET_REG32_1(RX_CPU_PGMCTR);
9224         GET_REG32_1(RX_CPU_HWBKPT);
9225         GET_REG32_1(TX_CPU_MODE);
9226         GET_REG32_1(TX_CPU_STATE);
9227         GET_REG32_1(TX_CPU_PGMCTR);
9228         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9229         GET_REG32_LOOP(FTQ_RESET, 0x120);
9230         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9231         GET_REG32_1(DMAC_MODE);
9232         GET_REG32_LOOP(GRC_MODE, 0x4c);
9233         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9234                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9235
9236 #undef __GET_REG32
9237 #undef GET_REG32_LOOP
9238 #undef GET_REG32_1
9239
9240         tg3_full_unlock(tp);
9241 }
9242
9243 static int tg3_get_eeprom_len(struct net_device *dev)
9244 {
9245         struct tg3 *tp = netdev_priv(dev);
9246
9247         return tp->nvram_size;
9248 }
9249
9250 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9251 {
9252         struct tg3 *tp = netdev_priv(dev);
9253         int ret;
9254         u8  *pd;
9255         u32 i, offset, len, b_offset, b_count;
9256         __be32 val;
9257
9258         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9259                 return -EINVAL;
9260
9261         if (tp->link_config.phy_is_low_power)
9262                 return -EAGAIN;
9263
9264         offset = eeprom->offset;
9265         len = eeprom->len;
9266         eeprom->len = 0;
9267
9268         eeprom->magic = TG3_EEPROM_MAGIC;
9269
9270         if (offset & 3) {
9271                 /* adjustments to start on required 4 byte boundary */
9272                 b_offset = offset & 3;
9273                 b_count = 4 - b_offset;
9274                 if (b_count > len) {
9275                         /* i.e. offset=1 len=2 */
9276                         b_count = len;
9277                 }
9278                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9279                 if (ret)
9280                         return ret;
9281                 memcpy(data, ((char*)&val) + b_offset, b_count);
9282                 len -= b_count;
9283                 offset += b_count;
9284                 eeprom->len += b_count;
9285         }
9286
9287         /* read bytes upto the last 4 byte boundary */
9288         pd = &data[eeprom->len];
9289         for (i = 0; i < (len - (len & 3)); i += 4) {
9290                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9291                 if (ret) {
9292                         eeprom->len += i;
9293                         return ret;
9294                 }
9295                 memcpy(pd + i, &val, 4);
9296         }
9297         eeprom->len += i;
9298
9299         if (len & 3) {
9300                 /* read last bytes not ending on 4 byte boundary */
9301                 pd = &data[eeprom->len];
9302                 b_count = len & 3;
9303                 b_offset = offset + len - b_count;
9304                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9305                 if (ret)
9306                         return ret;
9307                 memcpy(pd, &val, b_count);
9308                 eeprom->len += b_count;
9309         }
9310         return 0;
9311 }
9312
9313 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9314
9315 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9316 {
9317         struct tg3 *tp = netdev_priv(dev);
9318         int ret;
9319         u32 offset, len, b_offset, odd_len;
9320         u8 *buf;
9321         __be32 start, end;
9322
9323         if (tp->link_config.phy_is_low_power)
9324                 return -EAGAIN;
9325
9326         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9327             eeprom->magic != TG3_EEPROM_MAGIC)
9328                 return -EINVAL;
9329
9330         offset = eeprom->offset;
9331         len = eeprom->len;
9332
9333         if ((b_offset = (offset & 3))) {
9334                 /* adjustments to start on required 4 byte boundary */
9335                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9336                 if (ret)
9337                         return ret;
9338                 len += b_offset;
9339                 offset &= ~3;
9340                 if (len < 4)
9341                         len = 4;
9342         }
9343
9344         odd_len = 0;
9345         if (len & 3) {
9346                 /* adjustments to end on required 4 byte boundary */
9347                 odd_len = 1;
9348                 len = (len + 3) & ~3;
9349                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9350                 if (ret)
9351                         return ret;
9352         }
9353
9354         buf = data;
9355         if (b_offset || odd_len) {
9356                 buf = kmalloc(len, GFP_KERNEL);
9357                 if (!buf)
9358                         return -ENOMEM;
9359                 if (b_offset)
9360                         memcpy(buf, &start, 4);
9361                 if (odd_len)
9362                         memcpy(buf+len-4, &end, 4);
9363                 memcpy(buf + b_offset, data, eeprom->len);
9364         }
9365
9366         ret = tg3_nvram_write_block(tp, offset, len, buf);
9367
9368         if (buf != data)
9369                 kfree(buf);
9370
9371         return ret;
9372 }
9373
9374 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9375 {
9376         struct tg3 *tp = netdev_priv(dev);
9377
9378         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9379                 struct phy_device *phydev;
9380                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9381                         return -EAGAIN;
9382                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9383                 return phy_ethtool_gset(phydev, cmd);
9384         }
9385
9386         cmd->supported = (SUPPORTED_Autoneg);
9387
9388         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9389                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9390                                    SUPPORTED_1000baseT_Full);
9391
9392         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9393                 cmd->supported |= (SUPPORTED_100baseT_Half |
9394                                   SUPPORTED_100baseT_Full |
9395                                   SUPPORTED_10baseT_Half |
9396                                   SUPPORTED_10baseT_Full |
9397                                   SUPPORTED_TP);
9398                 cmd->port = PORT_TP;
9399         } else {
9400                 cmd->supported |= SUPPORTED_FIBRE;
9401                 cmd->port = PORT_FIBRE;
9402         }
9403
9404         cmd->advertising = tp->link_config.advertising;
9405         if (netif_running(dev)) {
9406                 cmd->speed = tp->link_config.active_speed;
9407                 cmd->duplex = tp->link_config.active_duplex;
9408         }
9409         cmd->phy_address = tp->phy_addr;
9410         cmd->transceiver = XCVR_INTERNAL;
9411         cmd->autoneg = tp->link_config.autoneg;
9412         cmd->maxtxpkt = 0;
9413         cmd->maxrxpkt = 0;
9414         return 0;
9415 }
9416
9417 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9418 {
9419         struct tg3 *tp = netdev_priv(dev);
9420
9421         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9422                 struct phy_device *phydev;
9423                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9424                         return -EAGAIN;
9425                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9426                 return phy_ethtool_sset(phydev, cmd);
9427         }
9428
9429         if (cmd->autoneg != AUTONEG_ENABLE &&
9430             cmd->autoneg != AUTONEG_DISABLE)
9431                 return -EINVAL;
9432
9433         if (cmd->autoneg == AUTONEG_DISABLE &&
9434             cmd->duplex != DUPLEX_FULL &&
9435             cmd->duplex != DUPLEX_HALF)
9436                 return -EINVAL;
9437
9438         if (cmd->autoneg == AUTONEG_ENABLE) {
9439                 u32 mask = ADVERTISED_Autoneg |
9440                            ADVERTISED_Pause |
9441                            ADVERTISED_Asym_Pause;
9442
9443                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9444                         mask |= ADVERTISED_1000baseT_Half |
9445                                 ADVERTISED_1000baseT_Full;
9446
9447                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9448                         mask |= ADVERTISED_100baseT_Half |
9449                                 ADVERTISED_100baseT_Full |
9450                                 ADVERTISED_10baseT_Half |
9451                                 ADVERTISED_10baseT_Full |
9452                                 ADVERTISED_TP;
9453                 else
9454                         mask |= ADVERTISED_FIBRE;
9455
9456                 if (cmd->advertising & ~mask)
9457                         return -EINVAL;
9458
9459                 mask &= (ADVERTISED_1000baseT_Half |
9460                          ADVERTISED_1000baseT_Full |
9461                          ADVERTISED_100baseT_Half |
9462                          ADVERTISED_100baseT_Full |
9463                          ADVERTISED_10baseT_Half |
9464                          ADVERTISED_10baseT_Full);
9465
9466                 cmd->advertising &= mask;
9467         } else {
9468                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9469                         if (cmd->speed != SPEED_1000)
9470                                 return -EINVAL;
9471
9472                         if (cmd->duplex != DUPLEX_FULL)
9473                                 return -EINVAL;
9474                 } else {
9475                         if (cmd->speed != SPEED_100 &&
9476                             cmd->speed != SPEED_10)
9477                                 return -EINVAL;
9478                 }
9479         }
9480
9481         tg3_full_lock(tp, 0);
9482
9483         tp->link_config.autoneg = cmd->autoneg;
9484         if (cmd->autoneg == AUTONEG_ENABLE) {
9485                 tp->link_config.advertising = (cmd->advertising |
9486                                               ADVERTISED_Autoneg);
9487                 tp->link_config.speed = SPEED_INVALID;
9488                 tp->link_config.duplex = DUPLEX_INVALID;
9489         } else {
9490                 tp->link_config.advertising = 0;
9491                 tp->link_config.speed = cmd->speed;
9492                 tp->link_config.duplex = cmd->duplex;
9493         }
9494
9495         tp->link_config.orig_speed = tp->link_config.speed;
9496         tp->link_config.orig_duplex = tp->link_config.duplex;
9497         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9498
9499         if (netif_running(dev))
9500                 tg3_setup_phy(tp, 1);
9501
9502         tg3_full_unlock(tp);
9503
9504         return 0;
9505 }
9506
9507 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9508 {
9509         struct tg3 *tp = netdev_priv(dev);
9510
9511         strcpy(info->driver, DRV_MODULE_NAME);
9512         strcpy(info->version, DRV_MODULE_VERSION);
9513         strcpy(info->fw_version, tp->fw_ver);
9514         strcpy(info->bus_info, pci_name(tp->pdev));
9515 }
9516
9517 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9518 {
9519         struct tg3 *tp = netdev_priv(dev);
9520
9521         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9522             device_can_wakeup(&tp->pdev->dev))
9523                 wol->supported = WAKE_MAGIC;
9524         else
9525                 wol->supported = 0;
9526         wol->wolopts = 0;
9527         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9528             device_can_wakeup(&tp->pdev->dev))
9529                 wol->wolopts = WAKE_MAGIC;
9530         memset(&wol->sopass, 0, sizeof(wol->sopass));
9531 }
9532
9533 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9534 {
9535         struct tg3 *tp = netdev_priv(dev);
9536         struct device *dp = &tp->pdev->dev;
9537
9538         if (wol->wolopts & ~WAKE_MAGIC)
9539                 return -EINVAL;
9540         if ((wol->wolopts & WAKE_MAGIC) &&
9541             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9542                 return -EINVAL;
9543
9544         spin_lock_bh(&tp->lock);
9545         if (wol->wolopts & WAKE_MAGIC) {
9546                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9547                 device_set_wakeup_enable(dp, true);
9548         } else {
9549                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9550                 device_set_wakeup_enable(dp, false);
9551         }
9552         spin_unlock_bh(&tp->lock);
9553
9554         return 0;
9555 }
9556
9557 static u32 tg3_get_msglevel(struct net_device *dev)
9558 {
9559         struct tg3 *tp = netdev_priv(dev);
9560         return tp->msg_enable;
9561 }
9562
9563 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9564 {
9565         struct tg3 *tp = netdev_priv(dev);
9566         tp->msg_enable = value;
9567 }
9568
9569 static int tg3_set_tso(struct net_device *dev, u32 value)
9570 {
9571         struct tg3 *tp = netdev_priv(dev);
9572
9573         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9574                 if (value)
9575                         return -EINVAL;
9576                 return 0;
9577         }
9578         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9579             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9580              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9581                 if (value) {
9582                         dev->features |= NETIF_F_TSO6;
9583                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9584                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9585                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9586                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9587                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9588                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9589                                 dev->features |= NETIF_F_TSO_ECN;
9590                 } else
9591                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9592         }
9593         return ethtool_op_set_tso(dev, value);
9594 }
9595
9596 static int tg3_nway_reset(struct net_device *dev)
9597 {
9598         struct tg3 *tp = netdev_priv(dev);
9599         int r;
9600
9601         if (!netif_running(dev))
9602                 return -EAGAIN;
9603
9604         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9605                 return -EINVAL;
9606
9607         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9608                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9609                         return -EAGAIN;
9610                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9611         } else {
9612                 u32 bmcr;
9613
9614                 spin_lock_bh(&tp->lock);
9615                 r = -EINVAL;
9616                 tg3_readphy(tp, MII_BMCR, &bmcr);
9617                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9618                     ((bmcr & BMCR_ANENABLE) ||
9619                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9620                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9621                                                    BMCR_ANENABLE);
9622                         r = 0;
9623                 }
9624                 spin_unlock_bh(&tp->lock);
9625         }
9626
9627         return r;
9628 }
9629
9630 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9631 {
9632         struct tg3 *tp = netdev_priv(dev);
9633
9634         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9635         ering->rx_mini_max_pending = 0;
9636         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9637                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9638         else
9639                 ering->rx_jumbo_max_pending = 0;
9640
9641         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9642
9643         ering->rx_pending = tp->rx_pending;
9644         ering->rx_mini_pending = 0;
9645         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9646                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9647         else
9648                 ering->rx_jumbo_pending = 0;
9649
9650         ering->tx_pending = tp->napi[0].tx_pending;
9651 }
9652
9653 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9654 {
9655         struct tg3 *tp = netdev_priv(dev);
9656         int i, irq_sync = 0, err = 0;
9657
9658         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9659             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9660             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9661             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9662             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9663              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9664                 return -EINVAL;
9665
9666         if (netif_running(dev)) {
9667                 tg3_phy_stop(tp);
9668                 tg3_netif_stop(tp);
9669                 irq_sync = 1;
9670         }
9671
9672         tg3_full_lock(tp, irq_sync);
9673
9674         tp->rx_pending = ering->rx_pending;
9675
9676         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9677             tp->rx_pending > 63)
9678                 tp->rx_pending = 63;
9679         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9680
9681         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9682                 tp->napi[i].tx_pending = ering->tx_pending;
9683
9684         if (netif_running(dev)) {
9685                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9686                 err = tg3_restart_hw(tp, 1);
9687                 if (!err)
9688                         tg3_netif_start(tp);
9689         }
9690
9691         tg3_full_unlock(tp);
9692
9693         if (irq_sync && !err)
9694                 tg3_phy_start(tp);
9695
9696         return err;
9697 }
9698
9699 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9700 {
9701         struct tg3 *tp = netdev_priv(dev);
9702
9703         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9704
9705         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9706                 epause->rx_pause = 1;
9707         else
9708                 epause->rx_pause = 0;
9709
9710         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9711                 epause->tx_pause = 1;
9712         else
9713                 epause->tx_pause = 0;
9714 }
9715
9716 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9717 {
9718         struct tg3 *tp = netdev_priv(dev);
9719         int err = 0;
9720
9721         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9722                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9723                         return -EAGAIN;
9724
9725                 if (epause->autoneg) {
9726                         u32 newadv;
9727                         struct phy_device *phydev;
9728
9729                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9730
9731                         if (epause->rx_pause) {
9732                                 if (epause->tx_pause)
9733                                         newadv = ADVERTISED_Pause;
9734                                 else
9735                                         newadv = ADVERTISED_Pause |
9736                                                  ADVERTISED_Asym_Pause;
9737                         } else if (epause->tx_pause) {
9738                                 newadv = ADVERTISED_Asym_Pause;
9739                         } else
9740                                 newadv = 0;
9741
9742                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9743                                 u32 oldadv = phydev->advertising &
9744                                              (ADVERTISED_Pause |
9745                                               ADVERTISED_Asym_Pause);
9746                                 if (oldadv != newadv) {
9747                                         phydev->advertising &=
9748                                                 ~(ADVERTISED_Pause |
9749                                                   ADVERTISED_Asym_Pause);
9750                                         phydev->advertising |= newadv;
9751                                         err = phy_start_aneg(phydev);
9752                                 }
9753                         } else {
9754                                 tp->link_config.advertising &=
9755                                                 ~(ADVERTISED_Pause |
9756                                                   ADVERTISED_Asym_Pause);
9757                                 tp->link_config.advertising |= newadv;
9758                         }
9759                 } else {
9760                         if (epause->rx_pause)
9761                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9762                         else
9763                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9764
9765                         if (epause->tx_pause)
9766                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9767                         else
9768                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9769
9770                         if (netif_running(dev))
9771                                 tg3_setup_flow_control(tp, 0, 0);
9772                 }
9773         } else {
9774                 int irq_sync = 0;
9775
9776                 if (netif_running(dev)) {
9777                         tg3_netif_stop(tp);
9778                         irq_sync = 1;
9779                 }
9780
9781                 tg3_full_lock(tp, irq_sync);
9782
9783                 if (epause->autoneg)
9784                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9785                 else
9786                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9787                 if (epause->rx_pause)
9788                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9789                 else
9790                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9791                 if (epause->tx_pause)
9792                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9793                 else
9794                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9795
9796                 if (netif_running(dev)) {
9797                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9798                         err = tg3_restart_hw(tp, 1);
9799                         if (!err)
9800                                 tg3_netif_start(tp);
9801                 }
9802
9803                 tg3_full_unlock(tp);
9804         }
9805
9806         return err;
9807 }
9808
9809 static u32 tg3_get_rx_csum(struct net_device *dev)
9810 {
9811         struct tg3 *tp = netdev_priv(dev);
9812         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9813 }
9814
9815 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9816 {
9817         struct tg3 *tp = netdev_priv(dev);
9818
9819         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9820                 if (data != 0)
9821                         return -EINVAL;
9822                 return 0;
9823         }
9824
9825         spin_lock_bh(&tp->lock);
9826         if (data)
9827                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9828         else
9829                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9830         spin_unlock_bh(&tp->lock);
9831
9832         return 0;
9833 }
9834
9835 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9836 {
9837         struct tg3 *tp = netdev_priv(dev);
9838
9839         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9840                 if (data != 0)
9841                         return -EINVAL;
9842                 return 0;
9843         }
9844
9845         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9846                 ethtool_op_set_tx_ipv6_csum(dev, data);
9847         else
9848                 ethtool_op_set_tx_csum(dev, data);
9849
9850         return 0;
9851 }
9852
9853 static int tg3_get_sset_count (struct net_device *dev, int sset)
9854 {
9855         switch (sset) {
9856         case ETH_SS_TEST:
9857                 return TG3_NUM_TEST;
9858         case ETH_SS_STATS:
9859                 return TG3_NUM_STATS;
9860         default:
9861                 return -EOPNOTSUPP;
9862         }
9863 }
9864
9865 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9866 {
9867         switch (stringset) {
9868         case ETH_SS_STATS:
9869                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9870                 break;
9871         case ETH_SS_TEST:
9872                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9873                 break;
9874         default:
9875                 WARN_ON(1);     /* we need a WARN() */
9876                 break;
9877         }
9878 }
9879
9880 static int tg3_phys_id(struct net_device *dev, u32 data)
9881 {
9882         struct tg3 *tp = netdev_priv(dev);
9883         int i;
9884
9885         if (!netif_running(tp->dev))
9886                 return -EAGAIN;
9887
9888         if (data == 0)
9889                 data = UINT_MAX / 2;
9890
9891         for (i = 0; i < (data * 2); i++) {
9892                 if ((i % 2) == 0)
9893                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9894                                            LED_CTRL_1000MBPS_ON |
9895                                            LED_CTRL_100MBPS_ON |
9896                                            LED_CTRL_10MBPS_ON |
9897                                            LED_CTRL_TRAFFIC_OVERRIDE |
9898                                            LED_CTRL_TRAFFIC_BLINK |
9899                                            LED_CTRL_TRAFFIC_LED);
9900
9901                 else
9902                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9903                                            LED_CTRL_TRAFFIC_OVERRIDE);
9904
9905                 if (msleep_interruptible(500))
9906                         break;
9907         }
9908         tw32(MAC_LED_CTRL, tp->led_ctrl);
9909         return 0;
9910 }
9911
9912 static void tg3_get_ethtool_stats (struct net_device *dev,
9913                                    struct ethtool_stats *estats, u64 *tmp_stats)
9914 {
9915         struct tg3 *tp = netdev_priv(dev);
9916         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9917 }
9918
9919 #define NVRAM_TEST_SIZE 0x100
9920 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9921 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9922 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9923 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9924 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9925
9926 static int tg3_test_nvram(struct tg3 *tp)
9927 {
9928         u32 csum, magic;
9929         __be32 *buf;
9930         int i, j, k, err = 0, size;
9931
9932         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9933                 return 0;
9934
9935         if (tg3_nvram_read(tp, 0, &magic) != 0)
9936                 return -EIO;
9937
9938         if (magic == TG3_EEPROM_MAGIC)
9939                 size = NVRAM_TEST_SIZE;
9940         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9941                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9942                     TG3_EEPROM_SB_FORMAT_1) {
9943                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9944                         case TG3_EEPROM_SB_REVISION_0:
9945                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9946                                 break;
9947                         case TG3_EEPROM_SB_REVISION_2:
9948                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9949                                 break;
9950                         case TG3_EEPROM_SB_REVISION_3:
9951                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9952                                 break;
9953                         default:
9954                                 return 0;
9955                         }
9956                 } else
9957                         return 0;
9958         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9959                 size = NVRAM_SELFBOOT_HW_SIZE;
9960         else
9961                 return -EIO;
9962
9963         buf = kmalloc(size, GFP_KERNEL);
9964         if (buf == NULL)
9965                 return -ENOMEM;
9966
9967         err = -EIO;
9968         for (i = 0, j = 0; i < size; i += 4, j++) {
9969                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9970                 if (err)
9971                         break;
9972         }
9973         if (i < size)
9974                 goto out;
9975
9976         /* Selfboot format */
9977         magic = be32_to_cpu(buf[0]);
9978         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9979             TG3_EEPROM_MAGIC_FW) {
9980                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9981
9982                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9983                     TG3_EEPROM_SB_REVISION_2) {
9984                         /* For rev 2, the csum doesn't include the MBA. */
9985                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9986                                 csum8 += buf8[i];
9987                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9988                                 csum8 += buf8[i];
9989                 } else {
9990                         for (i = 0; i < size; i++)
9991                                 csum8 += buf8[i];
9992                 }
9993
9994                 if (csum8 == 0) {
9995                         err = 0;
9996                         goto out;
9997                 }
9998
9999                 err = -EIO;
10000                 goto out;
10001         }
10002
10003         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10004             TG3_EEPROM_MAGIC_HW) {
10005                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10006                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10007                 u8 *buf8 = (u8 *) buf;
10008
10009                 /* Separate the parity bits and the data bytes.  */
10010                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10011                         if ((i == 0) || (i == 8)) {
10012                                 int l;
10013                                 u8 msk;
10014
10015                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10016                                         parity[k++] = buf8[i] & msk;
10017                                 i++;
10018                         }
10019                         else if (i == 16) {
10020                                 int l;
10021                                 u8 msk;
10022
10023                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10024                                         parity[k++] = buf8[i] & msk;
10025                                 i++;
10026
10027                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10028                                         parity[k++] = buf8[i] & msk;
10029                                 i++;
10030                         }
10031                         data[j++] = buf8[i];
10032                 }
10033
10034                 err = -EIO;
10035                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10036                         u8 hw8 = hweight8(data[i]);
10037
10038                         if ((hw8 & 0x1) && parity[i])
10039                                 goto out;
10040                         else if (!(hw8 & 0x1) && !parity[i])
10041                                 goto out;
10042                 }
10043                 err = 0;
10044                 goto out;
10045         }
10046
10047         /* Bootstrap checksum at offset 0x10 */
10048         csum = calc_crc((unsigned char *) buf, 0x10);
10049         if (csum != be32_to_cpu(buf[0x10/4]))
10050                 goto out;
10051
10052         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10053         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10054         if (csum != be32_to_cpu(buf[0xfc/4]))
10055                 goto out;
10056
10057         err = 0;
10058
10059 out:
10060         kfree(buf);
10061         return err;
10062 }
10063
10064 #define TG3_SERDES_TIMEOUT_SEC  2
10065 #define TG3_COPPER_TIMEOUT_SEC  6
10066
10067 static int tg3_test_link(struct tg3 *tp)
10068 {
10069         int i, max;
10070
10071         if (!netif_running(tp->dev))
10072                 return -ENODEV;
10073
10074         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10075                 max = TG3_SERDES_TIMEOUT_SEC;
10076         else
10077                 max = TG3_COPPER_TIMEOUT_SEC;
10078
10079         for (i = 0; i < max; i++) {
10080                 if (netif_carrier_ok(tp->dev))
10081                         return 0;
10082
10083                 if (msleep_interruptible(1000))
10084                         break;
10085         }
10086
10087         return -EIO;
10088 }
10089
10090 /* Only test the commonly used registers */
10091 static int tg3_test_registers(struct tg3 *tp)
10092 {
10093         int i, is_5705, is_5750;
10094         u32 offset, read_mask, write_mask, val, save_val, read_val;
10095         static struct {
10096                 u16 offset;
10097                 u16 flags;
10098 #define TG3_FL_5705     0x1
10099 #define TG3_FL_NOT_5705 0x2
10100 #define TG3_FL_NOT_5788 0x4
10101 #define TG3_FL_NOT_5750 0x8
10102                 u32 read_mask;
10103                 u32 write_mask;
10104         } reg_tbl[] = {
10105                 /* MAC Control Registers */
10106                 { MAC_MODE, TG3_FL_NOT_5705,
10107                         0x00000000, 0x00ef6f8c },
10108                 { MAC_MODE, TG3_FL_5705,
10109                         0x00000000, 0x01ef6b8c },
10110                 { MAC_STATUS, TG3_FL_NOT_5705,
10111                         0x03800107, 0x00000000 },
10112                 { MAC_STATUS, TG3_FL_5705,
10113                         0x03800100, 0x00000000 },
10114                 { MAC_ADDR_0_HIGH, 0x0000,
10115                         0x00000000, 0x0000ffff },
10116                 { MAC_ADDR_0_LOW, 0x0000,
10117                         0x00000000, 0xffffffff },
10118                 { MAC_RX_MTU_SIZE, 0x0000,
10119                         0x00000000, 0x0000ffff },
10120                 { MAC_TX_MODE, 0x0000,
10121                         0x00000000, 0x00000070 },
10122                 { MAC_TX_LENGTHS, 0x0000,
10123                         0x00000000, 0x00003fff },
10124                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10125                         0x00000000, 0x000007fc },
10126                 { MAC_RX_MODE, TG3_FL_5705,
10127                         0x00000000, 0x000007dc },
10128                 { MAC_HASH_REG_0, 0x0000,
10129                         0x00000000, 0xffffffff },
10130                 { MAC_HASH_REG_1, 0x0000,
10131                         0x00000000, 0xffffffff },
10132                 { MAC_HASH_REG_2, 0x0000,
10133                         0x00000000, 0xffffffff },
10134                 { MAC_HASH_REG_3, 0x0000,
10135                         0x00000000, 0xffffffff },
10136
10137                 /* Receive Data and Receive BD Initiator Control Registers. */
10138                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10139                         0x00000000, 0xffffffff },
10140                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10141                         0x00000000, 0xffffffff },
10142                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10143                         0x00000000, 0x00000003 },
10144                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10145                         0x00000000, 0xffffffff },
10146                 { RCVDBDI_STD_BD+0, 0x0000,
10147                         0x00000000, 0xffffffff },
10148                 { RCVDBDI_STD_BD+4, 0x0000,
10149                         0x00000000, 0xffffffff },
10150                 { RCVDBDI_STD_BD+8, 0x0000,
10151                         0x00000000, 0xffff0002 },
10152                 { RCVDBDI_STD_BD+0xc, 0x0000,
10153                         0x00000000, 0xffffffff },
10154
10155                 /* Receive BD Initiator Control Registers. */
10156                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10157                         0x00000000, 0xffffffff },
10158                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10159                         0x00000000, 0x000003ff },
10160                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10161                         0x00000000, 0xffffffff },
10162
10163                 /* Host Coalescing Control Registers. */
10164                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10165                         0x00000000, 0x00000004 },
10166                 { HOSTCC_MODE, TG3_FL_5705,
10167                         0x00000000, 0x000000f6 },
10168                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10169                         0x00000000, 0xffffffff },
10170                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10171                         0x00000000, 0x000003ff },
10172                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10173                         0x00000000, 0xffffffff },
10174                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10175                         0x00000000, 0x000003ff },
10176                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10177                         0x00000000, 0xffffffff },
10178                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10179                         0x00000000, 0x000000ff },
10180                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10181                         0x00000000, 0xffffffff },
10182                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10183                         0x00000000, 0x000000ff },
10184                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10185                         0x00000000, 0xffffffff },
10186                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10187                         0x00000000, 0xffffffff },
10188                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10189                         0x00000000, 0xffffffff },
10190                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10191                         0x00000000, 0x000000ff },
10192                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10193                         0x00000000, 0xffffffff },
10194                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10195                         0x00000000, 0x000000ff },
10196                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10197                         0x00000000, 0xffffffff },
10198                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10199                         0x00000000, 0xffffffff },
10200                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10201                         0x00000000, 0xffffffff },
10202                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10203                         0x00000000, 0xffffffff },
10204                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10205                         0x00000000, 0xffffffff },
10206                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10207                         0xffffffff, 0x00000000 },
10208                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10209                         0xffffffff, 0x00000000 },
10210
10211                 /* Buffer Manager Control Registers. */
10212                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10213                         0x00000000, 0x007fff80 },
10214                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10215                         0x00000000, 0x007fffff },
10216                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10217                         0x00000000, 0x0000003f },
10218                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10219                         0x00000000, 0x000001ff },
10220                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10221                         0x00000000, 0x000001ff },
10222                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10223                         0xffffffff, 0x00000000 },
10224                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10225                         0xffffffff, 0x00000000 },
10226
10227                 /* Mailbox Registers */
10228                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10229                         0x00000000, 0x000001ff },
10230                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10231                         0x00000000, 0x000001ff },
10232                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10233                         0x00000000, 0x000007ff },
10234                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10235                         0x00000000, 0x000001ff },
10236
10237                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10238         };
10239
10240         is_5705 = is_5750 = 0;
10241         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10242                 is_5705 = 1;
10243                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10244                         is_5750 = 1;
10245         }
10246
10247         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10248                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10249                         continue;
10250
10251                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10252                         continue;
10253
10254                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10255                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10256                         continue;
10257
10258                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10259                         continue;
10260
10261                 offset = (u32) reg_tbl[i].offset;
10262                 read_mask = reg_tbl[i].read_mask;
10263                 write_mask = reg_tbl[i].write_mask;
10264
10265                 /* Save the original register content */
10266                 save_val = tr32(offset);
10267
10268                 /* Determine the read-only value. */
10269                 read_val = save_val & read_mask;
10270
10271                 /* Write zero to the register, then make sure the read-only bits
10272                  * are not changed and the read/write bits are all zeros.
10273                  */
10274                 tw32(offset, 0);
10275
10276                 val = tr32(offset);
10277
10278                 /* Test the read-only and read/write bits. */
10279                 if (((val & read_mask) != read_val) || (val & write_mask))
10280                         goto out;
10281
10282                 /* Write ones to all the bits defined by RdMask and WrMask, then
10283                  * make sure the read-only bits are not changed and the
10284                  * read/write bits are all ones.
10285                  */
10286                 tw32(offset, read_mask | write_mask);
10287
10288                 val = tr32(offset);
10289
10290                 /* Test the read-only bits. */
10291                 if ((val & read_mask) != read_val)
10292                         goto out;
10293
10294                 /* Test the read/write bits. */
10295                 if ((val & write_mask) != write_mask)
10296                         goto out;
10297
10298                 tw32(offset, save_val);
10299         }
10300
10301         return 0;
10302
10303 out:
10304         if (netif_msg_hw(tp))
10305                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10306                        offset);
10307         tw32(offset, save_val);
10308         return -EIO;
10309 }
10310
10311 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10312 {
10313         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10314         int i;
10315         u32 j;
10316
10317         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10318                 for (j = 0; j < len; j += 4) {
10319                         u32 val;
10320
10321                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10322                         tg3_read_mem(tp, offset + j, &val);
10323                         if (val != test_pattern[i])
10324                                 return -EIO;
10325                 }
10326         }
10327         return 0;
10328 }
10329
10330 static int tg3_test_memory(struct tg3 *tp)
10331 {
10332         static struct mem_entry {
10333                 u32 offset;
10334                 u32 len;
10335         } mem_tbl_570x[] = {
10336                 { 0x00000000, 0x00b50},
10337                 { 0x00002000, 0x1c000},
10338                 { 0xffffffff, 0x00000}
10339         }, mem_tbl_5705[] = {
10340                 { 0x00000100, 0x0000c},
10341                 { 0x00000200, 0x00008},
10342                 { 0x00004000, 0x00800},
10343                 { 0x00006000, 0x01000},
10344                 { 0x00008000, 0x02000},
10345                 { 0x00010000, 0x0e000},
10346                 { 0xffffffff, 0x00000}
10347         }, mem_tbl_5755[] = {
10348                 { 0x00000200, 0x00008},
10349                 { 0x00004000, 0x00800},
10350                 { 0x00006000, 0x00800},
10351                 { 0x00008000, 0x02000},
10352                 { 0x00010000, 0x0c000},
10353                 { 0xffffffff, 0x00000}
10354         }, mem_tbl_5906[] = {
10355                 { 0x00000200, 0x00008},
10356                 { 0x00004000, 0x00400},
10357                 { 0x00006000, 0x00400},
10358                 { 0x00008000, 0x01000},
10359                 { 0x00010000, 0x01000},
10360                 { 0xffffffff, 0x00000}
10361         };
10362         struct mem_entry *mem_tbl;
10363         int err = 0;
10364         int i;
10365
10366         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10367                 mem_tbl = mem_tbl_5755;
10368         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10369                 mem_tbl = mem_tbl_5906;
10370         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10371                 mem_tbl = mem_tbl_5705;
10372         else
10373                 mem_tbl = mem_tbl_570x;
10374
10375         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10376                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10377                     mem_tbl[i].len)) != 0)
10378                         break;
10379         }
10380
10381         return err;
10382 }
10383
10384 #define TG3_MAC_LOOPBACK        0
10385 #define TG3_PHY_LOOPBACK        1
10386
10387 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10388 {
10389         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10390         u32 desc_idx, coal_now;
10391         struct sk_buff *skb, *rx_skb;
10392         u8 *tx_data;
10393         dma_addr_t map;
10394         int num_pkts, tx_len, rx_len, i, err;
10395         struct tg3_rx_buffer_desc *desc;
10396         struct tg3_napi *tnapi, *rnapi;
10397         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10398
10399         if (tp->irq_cnt > 1) {
10400                 tnapi = &tp->napi[1];
10401                 rnapi = &tp->napi[1];
10402         } else {
10403                 tnapi = &tp->napi[0];
10404                 rnapi = &tp->napi[0];
10405         }
10406         coal_now = tnapi->coal_now | rnapi->coal_now;
10407
10408         if (loopback_mode == TG3_MAC_LOOPBACK) {
10409                 /* HW errata - mac loopback fails in some cases on 5780.
10410                  * Normal traffic and PHY loopback are not affected by
10411                  * errata.
10412                  */
10413                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10414                         return 0;
10415
10416                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10417                            MAC_MODE_PORT_INT_LPBACK;
10418                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10419                         mac_mode |= MAC_MODE_LINK_POLARITY;
10420                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10421                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10422                 else
10423                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10424                 tw32(MAC_MODE, mac_mode);
10425         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10426                 u32 val;
10427
10428                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10429                         tg3_phy_fet_toggle_apd(tp, false);
10430                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10431                 } else
10432                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10433
10434                 tg3_phy_toggle_automdix(tp, 0);
10435
10436                 tg3_writephy(tp, MII_BMCR, val);
10437                 udelay(40);
10438
10439                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10440                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10441                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10442                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10443                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10444                 } else
10445                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10446
10447                 /* reset to prevent losing 1st rx packet intermittently */
10448                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10449                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10450                         udelay(10);
10451                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10452                 }
10453                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10454                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10455                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10456                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10457                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10458                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10459                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10460                 }
10461                 tw32(MAC_MODE, mac_mode);
10462         }
10463         else
10464                 return -EINVAL;
10465
10466         err = -EIO;
10467
10468         tx_len = 1514;
10469         skb = netdev_alloc_skb(tp->dev, tx_len);
10470         if (!skb)
10471                 return -ENOMEM;
10472
10473         tx_data = skb_put(skb, tx_len);
10474         memcpy(tx_data, tp->dev->dev_addr, 6);
10475         memset(tx_data + 6, 0x0, 8);
10476
10477         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10478
10479         for (i = 14; i < tx_len; i++)
10480                 tx_data[i] = (u8) (i & 0xff);
10481
10482         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10483                 dev_kfree_skb(skb);
10484                 return -EIO;
10485         }
10486
10487         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10488                rnapi->coal_now);
10489
10490         udelay(10);
10491
10492         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10493
10494         num_pkts = 0;
10495
10496         tg3_set_txd(tnapi, tnapi->tx_prod,
10497                     skb_shinfo(skb)->dma_head, tx_len, 0, 1);
10498
10499         tnapi->tx_prod++;
10500         num_pkts++;
10501
10502         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10503         tr32_mailbox(tnapi->prodmbox);
10504
10505         udelay(10);
10506
10507         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10508         for (i = 0; i < 35; i++) {
10509                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10510                        coal_now);
10511
10512                 udelay(10);
10513
10514                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10515                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10516                 if ((tx_idx == tnapi->tx_prod) &&
10517                     (rx_idx == (rx_start_idx + num_pkts)))
10518                         break;
10519         }
10520
10521         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
10522         dev_kfree_skb(skb);
10523
10524         if (tx_idx != tnapi->tx_prod)
10525                 goto out;
10526
10527         if (rx_idx != rx_start_idx + num_pkts)
10528                 goto out;
10529
10530         desc = &rnapi->rx_rcb[rx_start_idx];
10531         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10532         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10533         if (opaque_key != RXD_OPAQUE_RING_STD)
10534                 goto out;
10535
10536         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10537             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10538                 goto out;
10539
10540         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10541         if (rx_len != tx_len)
10542                 goto out;
10543
10544         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10545
10546         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10547         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10548
10549         for (i = 14; i < tx_len; i++) {
10550                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10551                         goto out;
10552         }
10553         err = 0;
10554
10555         /* tg3_free_rings will unmap and free the rx_skb */
10556 out:
10557         return err;
10558 }
10559
10560 #define TG3_MAC_LOOPBACK_FAILED         1
10561 #define TG3_PHY_LOOPBACK_FAILED         2
10562 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10563                                          TG3_PHY_LOOPBACK_FAILED)
10564
10565 static int tg3_test_loopback(struct tg3 *tp)
10566 {
10567         int err = 0;
10568         u32 cpmuctrl = 0;
10569
10570         if (!netif_running(tp->dev))
10571                 return TG3_LOOPBACK_FAILED;
10572
10573         err = tg3_reset_hw(tp, 1);
10574         if (err)
10575                 return TG3_LOOPBACK_FAILED;
10576
10577         /* Turn off gphy autopowerdown. */
10578         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10579                 tg3_phy_toggle_apd(tp, false);
10580
10581         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10582                 int i;
10583                 u32 status;
10584
10585                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10586
10587                 /* Wait for up to 40 microseconds to acquire lock. */
10588                 for (i = 0; i < 4; i++) {
10589                         status = tr32(TG3_CPMU_MUTEX_GNT);
10590                         if (status == CPMU_MUTEX_GNT_DRIVER)
10591                                 break;
10592                         udelay(10);
10593                 }
10594
10595                 if (status != CPMU_MUTEX_GNT_DRIVER)
10596                         return TG3_LOOPBACK_FAILED;
10597
10598                 /* Turn off link-based power management. */
10599                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10600                 tw32(TG3_CPMU_CTRL,
10601                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10602                                   CPMU_CTRL_LINK_AWARE_MODE));
10603         }
10604
10605         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10606                 err |= TG3_MAC_LOOPBACK_FAILED;
10607
10608         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10609                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10610
10611                 /* Release the mutex */
10612                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10613         }
10614
10615         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10616             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10617                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10618                         err |= TG3_PHY_LOOPBACK_FAILED;
10619         }
10620
10621         /* Re-enable gphy autopowerdown. */
10622         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10623                 tg3_phy_toggle_apd(tp, true);
10624
10625         return err;
10626 }
10627
10628 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10629                           u64 *data)
10630 {
10631         struct tg3 *tp = netdev_priv(dev);
10632
10633         if (tp->link_config.phy_is_low_power)
10634                 tg3_set_power_state(tp, PCI_D0);
10635
10636         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10637
10638         if (tg3_test_nvram(tp) != 0) {
10639                 etest->flags |= ETH_TEST_FL_FAILED;
10640                 data[0] = 1;
10641         }
10642         if (tg3_test_link(tp) != 0) {
10643                 etest->flags |= ETH_TEST_FL_FAILED;
10644                 data[1] = 1;
10645         }
10646         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10647                 int err, err2 = 0, irq_sync = 0;
10648
10649                 if (netif_running(dev)) {
10650                         tg3_phy_stop(tp);
10651                         tg3_netif_stop(tp);
10652                         irq_sync = 1;
10653                 }
10654
10655                 tg3_full_lock(tp, irq_sync);
10656
10657                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10658                 err = tg3_nvram_lock(tp);
10659                 tg3_halt_cpu(tp, RX_CPU_BASE);
10660                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10661                         tg3_halt_cpu(tp, TX_CPU_BASE);
10662                 if (!err)
10663                         tg3_nvram_unlock(tp);
10664
10665                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10666                         tg3_phy_reset(tp);
10667
10668                 if (tg3_test_registers(tp) != 0) {
10669                         etest->flags |= ETH_TEST_FL_FAILED;
10670                         data[2] = 1;
10671                 }
10672                 if (tg3_test_memory(tp) != 0) {
10673                         etest->flags |= ETH_TEST_FL_FAILED;
10674                         data[3] = 1;
10675                 }
10676                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10677                         etest->flags |= ETH_TEST_FL_FAILED;
10678
10679                 tg3_full_unlock(tp);
10680
10681                 if (tg3_test_interrupt(tp) != 0) {
10682                         etest->flags |= ETH_TEST_FL_FAILED;
10683                         data[5] = 1;
10684                 }
10685
10686                 tg3_full_lock(tp, 0);
10687
10688                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10689                 if (netif_running(dev)) {
10690                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10691                         err2 = tg3_restart_hw(tp, 1);
10692                         if (!err2)
10693                                 tg3_netif_start(tp);
10694                 }
10695
10696                 tg3_full_unlock(tp);
10697
10698                 if (irq_sync && !err2)
10699                         tg3_phy_start(tp);
10700         }
10701         if (tp->link_config.phy_is_low_power)
10702                 tg3_set_power_state(tp, PCI_D3hot);
10703
10704 }
10705
10706 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10707 {
10708         struct mii_ioctl_data *data = if_mii(ifr);
10709         struct tg3 *tp = netdev_priv(dev);
10710         int err;
10711
10712         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10713                 struct phy_device *phydev;
10714                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10715                         return -EAGAIN;
10716                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10717                 return phy_mii_ioctl(phydev, data, cmd);
10718         }
10719
10720         switch(cmd) {
10721         case SIOCGMIIPHY:
10722                 data->phy_id = tp->phy_addr;
10723
10724                 /* fallthru */
10725         case SIOCGMIIREG: {
10726                 u32 mii_regval;
10727
10728                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10729                         break;                  /* We have no PHY */
10730
10731                 if (tp->link_config.phy_is_low_power)
10732                         return -EAGAIN;
10733
10734                 spin_lock_bh(&tp->lock);
10735                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10736                 spin_unlock_bh(&tp->lock);
10737
10738                 data->val_out = mii_regval;
10739
10740                 return err;
10741         }
10742
10743         case SIOCSMIIREG:
10744                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10745                         break;                  /* We have no PHY */
10746
10747                 if (tp->link_config.phy_is_low_power)
10748                         return -EAGAIN;
10749
10750                 spin_lock_bh(&tp->lock);
10751                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10752                 spin_unlock_bh(&tp->lock);
10753
10754                 return err;
10755
10756         default:
10757                 /* do nothing */
10758                 break;
10759         }
10760         return -EOPNOTSUPP;
10761 }
10762
10763 #if TG3_VLAN_TAG_USED
10764 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10765 {
10766         struct tg3 *tp = netdev_priv(dev);
10767
10768         if (!netif_running(dev)) {
10769                 tp->vlgrp = grp;
10770                 return;
10771         }
10772
10773         tg3_netif_stop(tp);
10774
10775         tg3_full_lock(tp, 0);
10776
10777         tp->vlgrp = grp;
10778
10779         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10780         __tg3_set_rx_mode(dev);
10781
10782         tg3_netif_start(tp);
10783
10784         tg3_full_unlock(tp);
10785 }
10786 #endif
10787
10788 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10789 {
10790         struct tg3 *tp = netdev_priv(dev);
10791
10792         memcpy(ec, &tp->coal, sizeof(*ec));
10793         return 0;
10794 }
10795
10796 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10797 {
10798         struct tg3 *tp = netdev_priv(dev);
10799         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10800         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10801
10802         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10803                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10804                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10805                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10806                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10807         }
10808
10809         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10810             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10811             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10812             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10813             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10814             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10815             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10816             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10817             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10818             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10819                 return -EINVAL;
10820
10821         /* No rx interrupts will be generated if both are zero */
10822         if ((ec->rx_coalesce_usecs == 0) &&
10823             (ec->rx_max_coalesced_frames == 0))
10824                 return -EINVAL;
10825
10826         /* No tx interrupts will be generated if both are zero */
10827         if ((ec->tx_coalesce_usecs == 0) &&
10828             (ec->tx_max_coalesced_frames == 0))
10829                 return -EINVAL;
10830
10831         /* Only copy relevant parameters, ignore all others. */
10832         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10833         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10834         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10835         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10836         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10837         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10838         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10839         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10840         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10841
10842         if (netif_running(dev)) {
10843                 tg3_full_lock(tp, 0);
10844                 __tg3_set_coalesce(tp, &tp->coal);
10845                 tg3_full_unlock(tp);
10846         }
10847         return 0;
10848 }
10849
10850 static const struct ethtool_ops tg3_ethtool_ops = {
10851         .get_settings           = tg3_get_settings,
10852         .set_settings           = tg3_set_settings,
10853         .get_drvinfo            = tg3_get_drvinfo,
10854         .get_regs_len           = tg3_get_regs_len,
10855         .get_regs               = tg3_get_regs,
10856         .get_wol                = tg3_get_wol,
10857         .set_wol                = tg3_set_wol,
10858         .get_msglevel           = tg3_get_msglevel,
10859         .set_msglevel           = tg3_set_msglevel,
10860         .nway_reset             = tg3_nway_reset,
10861         .get_link               = ethtool_op_get_link,
10862         .get_eeprom_len         = tg3_get_eeprom_len,
10863         .get_eeprom             = tg3_get_eeprom,
10864         .set_eeprom             = tg3_set_eeprom,
10865         .get_ringparam          = tg3_get_ringparam,
10866         .set_ringparam          = tg3_set_ringparam,
10867         .get_pauseparam         = tg3_get_pauseparam,
10868         .set_pauseparam         = tg3_set_pauseparam,
10869         .get_rx_csum            = tg3_get_rx_csum,
10870         .set_rx_csum            = tg3_set_rx_csum,
10871         .set_tx_csum            = tg3_set_tx_csum,
10872         .set_sg                 = ethtool_op_set_sg,
10873         .set_tso                = tg3_set_tso,
10874         .self_test              = tg3_self_test,
10875         .get_strings            = tg3_get_strings,
10876         .phys_id                = tg3_phys_id,
10877         .get_ethtool_stats      = tg3_get_ethtool_stats,
10878         .get_coalesce           = tg3_get_coalesce,
10879         .set_coalesce           = tg3_set_coalesce,
10880         .get_sset_count         = tg3_get_sset_count,
10881 };
10882
10883 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10884 {
10885         u32 cursize, val, magic;
10886
10887         tp->nvram_size = EEPROM_CHIP_SIZE;
10888
10889         if (tg3_nvram_read(tp, 0, &magic) != 0)
10890                 return;
10891
10892         if ((magic != TG3_EEPROM_MAGIC) &&
10893             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10894             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10895                 return;
10896
10897         /*
10898          * Size the chip by reading offsets at increasing powers of two.
10899          * When we encounter our validation signature, we know the addressing
10900          * has wrapped around, and thus have our chip size.
10901          */
10902         cursize = 0x10;
10903
10904         while (cursize < tp->nvram_size) {
10905                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10906                         return;
10907
10908                 if (val == magic)
10909                         break;
10910
10911                 cursize <<= 1;
10912         }
10913
10914         tp->nvram_size = cursize;
10915 }
10916
10917 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10918 {
10919         u32 val;
10920
10921         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10922             tg3_nvram_read(tp, 0, &val) != 0)
10923                 return;
10924
10925         /* Selfboot format */
10926         if (val != TG3_EEPROM_MAGIC) {
10927                 tg3_get_eeprom_size(tp);
10928                 return;
10929         }
10930
10931         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10932                 if (val != 0) {
10933                         /* This is confusing.  We want to operate on the
10934                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10935                          * call will read from NVRAM and byteswap the data
10936                          * according to the byteswapping settings for all
10937                          * other register accesses.  This ensures the data we
10938                          * want will always reside in the lower 16-bits.
10939                          * However, the data in NVRAM is in LE format, which
10940                          * means the data from the NVRAM read will always be
10941                          * opposite the endianness of the CPU.  The 16-bit
10942                          * byteswap then brings the data to CPU endianness.
10943                          */
10944                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10945                         return;
10946                 }
10947         }
10948         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10949 }
10950
10951 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10952 {
10953         u32 nvcfg1;
10954
10955         nvcfg1 = tr32(NVRAM_CFG1);
10956         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10957                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10958         } else {
10959                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10960                 tw32(NVRAM_CFG1, nvcfg1);
10961         }
10962
10963         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10964             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10965                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10966                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10967                         tp->nvram_jedecnum = JEDEC_ATMEL;
10968                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10969                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10970                         break;
10971                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10972                         tp->nvram_jedecnum = JEDEC_ATMEL;
10973                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10974                         break;
10975                 case FLASH_VENDOR_ATMEL_EEPROM:
10976                         tp->nvram_jedecnum = JEDEC_ATMEL;
10977                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10978                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10979                         break;
10980                 case FLASH_VENDOR_ST:
10981                         tp->nvram_jedecnum = JEDEC_ST;
10982                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10983                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10984                         break;
10985                 case FLASH_VENDOR_SAIFUN:
10986                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10987                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10988                         break;
10989                 case FLASH_VENDOR_SST_SMALL:
10990                 case FLASH_VENDOR_SST_LARGE:
10991                         tp->nvram_jedecnum = JEDEC_SST;
10992                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10993                         break;
10994                 }
10995         } else {
10996                 tp->nvram_jedecnum = JEDEC_ATMEL;
10997                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10998                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10999         }
11000 }
11001
11002 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11003 {
11004         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11005         case FLASH_5752PAGE_SIZE_256:
11006                 tp->nvram_pagesize = 256;
11007                 break;
11008         case FLASH_5752PAGE_SIZE_512:
11009                 tp->nvram_pagesize = 512;
11010                 break;
11011         case FLASH_5752PAGE_SIZE_1K:
11012                 tp->nvram_pagesize = 1024;
11013                 break;
11014         case FLASH_5752PAGE_SIZE_2K:
11015                 tp->nvram_pagesize = 2048;
11016                 break;
11017         case FLASH_5752PAGE_SIZE_4K:
11018                 tp->nvram_pagesize = 4096;
11019                 break;
11020         case FLASH_5752PAGE_SIZE_264:
11021                 tp->nvram_pagesize = 264;
11022                 break;
11023         case FLASH_5752PAGE_SIZE_528:
11024                 tp->nvram_pagesize = 528;
11025                 break;
11026         }
11027 }
11028
11029 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11030 {
11031         u32 nvcfg1;
11032
11033         nvcfg1 = tr32(NVRAM_CFG1);
11034
11035         /* NVRAM protection for TPM */
11036         if (nvcfg1 & (1 << 27))
11037                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11038
11039         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11040         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11041         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11042                 tp->nvram_jedecnum = JEDEC_ATMEL;
11043                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11044                 break;
11045         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11046                 tp->nvram_jedecnum = JEDEC_ATMEL;
11047                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11048                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11049                 break;
11050         case FLASH_5752VENDOR_ST_M45PE10:
11051         case FLASH_5752VENDOR_ST_M45PE20:
11052         case FLASH_5752VENDOR_ST_M45PE40:
11053                 tp->nvram_jedecnum = JEDEC_ST;
11054                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11055                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11056                 break;
11057         }
11058
11059         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11060                 tg3_nvram_get_pagesize(tp, nvcfg1);
11061         } else {
11062                 /* For eeprom, set pagesize to maximum eeprom size */
11063                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11064
11065                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11066                 tw32(NVRAM_CFG1, nvcfg1);
11067         }
11068 }
11069
11070 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11071 {
11072         u32 nvcfg1, protect = 0;
11073
11074         nvcfg1 = tr32(NVRAM_CFG1);
11075
11076         /* NVRAM protection for TPM */
11077         if (nvcfg1 & (1 << 27)) {
11078                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11079                 protect = 1;
11080         }
11081
11082         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11083         switch (nvcfg1) {
11084         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11085         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11086         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11087         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11088                 tp->nvram_jedecnum = JEDEC_ATMEL;
11089                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11090                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11091                 tp->nvram_pagesize = 264;
11092                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11093                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11094                         tp->nvram_size = (protect ? 0x3e200 :
11095                                           TG3_NVRAM_SIZE_512KB);
11096                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11097                         tp->nvram_size = (protect ? 0x1f200 :
11098                                           TG3_NVRAM_SIZE_256KB);
11099                 else
11100                         tp->nvram_size = (protect ? 0x1f200 :
11101                                           TG3_NVRAM_SIZE_128KB);
11102                 break;
11103         case FLASH_5752VENDOR_ST_M45PE10:
11104         case FLASH_5752VENDOR_ST_M45PE20:
11105         case FLASH_5752VENDOR_ST_M45PE40:
11106                 tp->nvram_jedecnum = JEDEC_ST;
11107                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11108                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11109                 tp->nvram_pagesize = 256;
11110                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11111                         tp->nvram_size = (protect ?
11112                                           TG3_NVRAM_SIZE_64KB :
11113                                           TG3_NVRAM_SIZE_128KB);
11114                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11115                         tp->nvram_size = (protect ?
11116                                           TG3_NVRAM_SIZE_64KB :
11117                                           TG3_NVRAM_SIZE_256KB);
11118                 else
11119                         tp->nvram_size = (protect ?
11120                                           TG3_NVRAM_SIZE_128KB :
11121                                           TG3_NVRAM_SIZE_512KB);
11122                 break;
11123         }
11124 }
11125
11126 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11127 {
11128         u32 nvcfg1;
11129
11130         nvcfg1 = tr32(NVRAM_CFG1);
11131
11132         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11133         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11134         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11135         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11136         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11137                 tp->nvram_jedecnum = JEDEC_ATMEL;
11138                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11139                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11140
11141                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11142                 tw32(NVRAM_CFG1, nvcfg1);
11143                 break;
11144         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11145         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11146         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11147         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11148                 tp->nvram_jedecnum = JEDEC_ATMEL;
11149                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11150                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11151                 tp->nvram_pagesize = 264;
11152                 break;
11153         case FLASH_5752VENDOR_ST_M45PE10:
11154         case FLASH_5752VENDOR_ST_M45PE20:
11155         case FLASH_5752VENDOR_ST_M45PE40:
11156                 tp->nvram_jedecnum = JEDEC_ST;
11157                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11158                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11159                 tp->nvram_pagesize = 256;
11160                 break;
11161         }
11162 }
11163
11164 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11165 {
11166         u32 nvcfg1, protect = 0;
11167
11168         nvcfg1 = tr32(NVRAM_CFG1);
11169
11170         /* NVRAM protection for TPM */
11171         if (nvcfg1 & (1 << 27)) {
11172                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11173                 protect = 1;
11174         }
11175
11176         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11177         switch (nvcfg1) {
11178         case FLASH_5761VENDOR_ATMEL_ADB021D:
11179         case FLASH_5761VENDOR_ATMEL_ADB041D:
11180         case FLASH_5761VENDOR_ATMEL_ADB081D:
11181         case FLASH_5761VENDOR_ATMEL_ADB161D:
11182         case FLASH_5761VENDOR_ATMEL_MDB021D:
11183         case FLASH_5761VENDOR_ATMEL_MDB041D:
11184         case FLASH_5761VENDOR_ATMEL_MDB081D:
11185         case FLASH_5761VENDOR_ATMEL_MDB161D:
11186                 tp->nvram_jedecnum = JEDEC_ATMEL;
11187                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11188                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11189                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11190                 tp->nvram_pagesize = 256;
11191                 break;
11192         case FLASH_5761VENDOR_ST_A_M45PE20:
11193         case FLASH_5761VENDOR_ST_A_M45PE40:
11194         case FLASH_5761VENDOR_ST_A_M45PE80:
11195         case FLASH_5761VENDOR_ST_A_M45PE16:
11196         case FLASH_5761VENDOR_ST_M_M45PE20:
11197         case FLASH_5761VENDOR_ST_M_M45PE40:
11198         case FLASH_5761VENDOR_ST_M_M45PE80:
11199         case FLASH_5761VENDOR_ST_M_M45PE16:
11200                 tp->nvram_jedecnum = JEDEC_ST;
11201                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11202                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11203                 tp->nvram_pagesize = 256;
11204                 break;
11205         }
11206
11207         if (protect) {
11208                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11209         } else {
11210                 switch (nvcfg1) {
11211                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11212                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11213                 case FLASH_5761VENDOR_ST_A_M45PE16:
11214                 case FLASH_5761VENDOR_ST_M_M45PE16:
11215                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11216                         break;
11217                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11218                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11219                 case FLASH_5761VENDOR_ST_A_M45PE80:
11220                 case FLASH_5761VENDOR_ST_M_M45PE80:
11221                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11222                         break;
11223                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11224                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11225                 case FLASH_5761VENDOR_ST_A_M45PE40:
11226                 case FLASH_5761VENDOR_ST_M_M45PE40:
11227                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11228                         break;
11229                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11230                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11231                 case FLASH_5761VENDOR_ST_A_M45PE20:
11232                 case FLASH_5761VENDOR_ST_M_M45PE20:
11233                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11234                         break;
11235                 }
11236         }
11237 }
11238
11239 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11240 {
11241         tp->nvram_jedecnum = JEDEC_ATMEL;
11242         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11243         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11244 }
11245
11246 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11247 {
11248         u32 nvcfg1;
11249
11250         nvcfg1 = tr32(NVRAM_CFG1);
11251
11252         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11253         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11254         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11255                 tp->nvram_jedecnum = JEDEC_ATMEL;
11256                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11257                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11258
11259                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11260                 tw32(NVRAM_CFG1, nvcfg1);
11261                 return;
11262         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11263         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11264         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11265         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11266         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11267         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11268         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11269                 tp->nvram_jedecnum = JEDEC_ATMEL;
11270                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11271                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11272
11273                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11274                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11275                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11276                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11277                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11278                         break;
11279                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11280                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11281                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11282                         break;
11283                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11284                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11285                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11286                         break;
11287                 }
11288                 break;
11289         case FLASH_5752VENDOR_ST_M45PE10:
11290         case FLASH_5752VENDOR_ST_M45PE20:
11291         case FLASH_5752VENDOR_ST_M45PE40:
11292                 tp->nvram_jedecnum = JEDEC_ST;
11293                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11294                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11295
11296                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11297                 case FLASH_5752VENDOR_ST_M45PE10:
11298                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11299                         break;
11300                 case FLASH_5752VENDOR_ST_M45PE20:
11301                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11302                         break;
11303                 case FLASH_5752VENDOR_ST_M45PE40:
11304                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11305                         break;
11306                 }
11307                 break;
11308         default:
11309                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11310                 return;
11311         }
11312
11313         tg3_nvram_get_pagesize(tp, nvcfg1);
11314         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11315                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11316 }
11317
11318
11319 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11320 {
11321         u32 nvcfg1;
11322
11323         nvcfg1 = tr32(NVRAM_CFG1);
11324
11325         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11326         case FLASH_5717VENDOR_ATMEL_EEPROM:
11327         case FLASH_5717VENDOR_MICRO_EEPROM:
11328                 tp->nvram_jedecnum = JEDEC_ATMEL;
11329                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11330                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11331
11332                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11333                 tw32(NVRAM_CFG1, nvcfg1);
11334                 return;
11335         case FLASH_5717VENDOR_ATMEL_MDB011D:
11336         case FLASH_5717VENDOR_ATMEL_ADB011B:
11337         case FLASH_5717VENDOR_ATMEL_ADB011D:
11338         case FLASH_5717VENDOR_ATMEL_MDB021D:
11339         case FLASH_5717VENDOR_ATMEL_ADB021B:
11340         case FLASH_5717VENDOR_ATMEL_ADB021D:
11341         case FLASH_5717VENDOR_ATMEL_45USPT:
11342                 tp->nvram_jedecnum = JEDEC_ATMEL;
11343                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11344                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11345
11346                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11347                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11348                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11349                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11350                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11351                         break;
11352                 default:
11353                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11354                         break;
11355                 }
11356                 break;
11357         case FLASH_5717VENDOR_ST_M_M25PE10:
11358         case FLASH_5717VENDOR_ST_A_M25PE10:
11359         case FLASH_5717VENDOR_ST_M_M45PE10:
11360         case FLASH_5717VENDOR_ST_A_M45PE10:
11361         case FLASH_5717VENDOR_ST_M_M25PE20:
11362         case FLASH_5717VENDOR_ST_A_M25PE20:
11363         case FLASH_5717VENDOR_ST_M_M45PE20:
11364         case FLASH_5717VENDOR_ST_A_M45PE20:
11365         case FLASH_5717VENDOR_ST_25USPT:
11366         case FLASH_5717VENDOR_ST_45USPT:
11367                 tp->nvram_jedecnum = JEDEC_ST;
11368                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11369                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11370
11371                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11372                 case FLASH_5717VENDOR_ST_M_M25PE20:
11373                 case FLASH_5717VENDOR_ST_A_M25PE20:
11374                 case FLASH_5717VENDOR_ST_M_M45PE20:
11375                 case FLASH_5717VENDOR_ST_A_M45PE20:
11376                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11377                         break;
11378                 default:
11379                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11380                         break;
11381                 }
11382                 break;
11383         default:
11384                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11385                 return;
11386         }
11387
11388         tg3_nvram_get_pagesize(tp, nvcfg1);
11389         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11390                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11391 }
11392
11393 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11394 static void __devinit tg3_nvram_init(struct tg3 *tp)
11395 {
11396         tw32_f(GRC_EEPROM_ADDR,
11397              (EEPROM_ADDR_FSM_RESET |
11398               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11399                EEPROM_ADDR_CLKPERD_SHIFT)));
11400
11401         msleep(1);
11402
11403         /* Enable seeprom accesses. */
11404         tw32_f(GRC_LOCAL_CTRL,
11405              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11406         udelay(100);
11407
11408         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11409             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11410                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11411
11412                 if (tg3_nvram_lock(tp)) {
11413                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11414                                "tg3_nvram_init failed.\n", tp->dev->name);
11415                         return;
11416                 }
11417                 tg3_enable_nvram_access(tp);
11418
11419                 tp->nvram_size = 0;
11420
11421                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11422                         tg3_get_5752_nvram_info(tp);
11423                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11424                         tg3_get_5755_nvram_info(tp);
11425                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11426                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11427                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11428                         tg3_get_5787_nvram_info(tp);
11429                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11430                         tg3_get_5761_nvram_info(tp);
11431                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11432                         tg3_get_5906_nvram_info(tp);
11433                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11434                         tg3_get_57780_nvram_info(tp);
11435                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11436                         tg3_get_5717_nvram_info(tp);
11437                 else
11438                         tg3_get_nvram_info(tp);
11439
11440                 if (tp->nvram_size == 0)
11441                         tg3_get_nvram_size(tp);
11442
11443                 tg3_disable_nvram_access(tp);
11444                 tg3_nvram_unlock(tp);
11445
11446         } else {
11447                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11448
11449                 tg3_get_eeprom_size(tp);
11450         }
11451 }
11452
11453 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11454                                     u32 offset, u32 len, u8 *buf)
11455 {
11456         int i, j, rc = 0;
11457         u32 val;
11458
11459         for (i = 0; i < len; i += 4) {
11460                 u32 addr;
11461                 __be32 data;
11462
11463                 addr = offset + i;
11464
11465                 memcpy(&data, buf + i, 4);
11466
11467                 /*
11468                  * The SEEPROM interface expects the data to always be opposite
11469                  * the native endian format.  We accomplish this by reversing
11470                  * all the operations that would have been performed on the
11471                  * data from a call to tg3_nvram_read_be32().
11472                  */
11473                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11474
11475                 val = tr32(GRC_EEPROM_ADDR);
11476                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11477
11478                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11479                         EEPROM_ADDR_READ);
11480                 tw32(GRC_EEPROM_ADDR, val |
11481                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11482                         (addr & EEPROM_ADDR_ADDR_MASK) |
11483                         EEPROM_ADDR_START |
11484                         EEPROM_ADDR_WRITE);
11485
11486                 for (j = 0; j < 1000; j++) {
11487                         val = tr32(GRC_EEPROM_ADDR);
11488
11489                         if (val & EEPROM_ADDR_COMPLETE)
11490                                 break;
11491                         msleep(1);
11492                 }
11493                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11494                         rc = -EBUSY;
11495                         break;
11496                 }
11497         }
11498
11499         return rc;
11500 }
11501
11502 /* offset and length are dword aligned */
11503 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11504                 u8 *buf)
11505 {
11506         int ret = 0;
11507         u32 pagesize = tp->nvram_pagesize;
11508         u32 pagemask = pagesize - 1;
11509         u32 nvram_cmd;
11510         u8 *tmp;
11511
11512         tmp = kmalloc(pagesize, GFP_KERNEL);
11513         if (tmp == NULL)
11514                 return -ENOMEM;
11515
11516         while (len) {
11517                 int j;
11518                 u32 phy_addr, page_off, size;
11519
11520                 phy_addr = offset & ~pagemask;
11521
11522                 for (j = 0; j < pagesize; j += 4) {
11523                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11524                                                   (__be32 *) (tmp + j));
11525                         if (ret)
11526                                 break;
11527                 }
11528                 if (ret)
11529                         break;
11530
11531                 page_off = offset & pagemask;
11532                 size = pagesize;
11533                 if (len < size)
11534                         size = len;
11535
11536                 len -= size;
11537
11538                 memcpy(tmp + page_off, buf, size);
11539
11540                 offset = offset + (pagesize - page_off);
11541
11542                 tg3_enable_nvram_access(tp);
11543
11544                 /*
11545                  * Before we can erase the flash page, we need
11546                  * to issue a special "write enable" command.
11547                  */
11548                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11549
11550                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11551                         break;
11552
11553                 /* Erase the target page */
11554                 tw32(NVRAM_ADDR, phy_addr);
11555
11556                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11557                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11558
11559                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11560                         break;
11561
11562                 /* Issue another write enable to start the write. */
11563                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11564
11565                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11566                         break;
11567
11568                 for (j = 0; j < pagesize; j += 4) {
11569                         __be32 data;
11570
11571                         data = *((__be32 *) (tmp + j));
11572
11573                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11574
11575                         tw32(NVRAM_ADDR, phy_addr + j);
11576
11577                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11578                                 NVRAM_CMD_WR;
11579
11580                         if (j == 0)
11581                                 nvram_cmd |= NVRAM_CMD_FIRST;
11582                         else if (j == (pagesize - 4))
11583                                 nvram_cmd |= NVRAM_CMD_LAST;
11584
11585                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11586                                 break;
11587                 }
11588                 if (ret)
11589                         break;
11590         }
11591
11592         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11593         tg3_nvram_exec_cmd(tp, nvram_cmd);
11594
11595         kfree(tmp);
11596
11597         return ret;
11598 }
11599
11600 /* offset and length are dword aligned */
11601 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11602                 u8 *buf)
11603 {
11604         int i, ret = 0;
11605
11606         for (i = 0; i < len; i += 4, offset += 4) {
11607                 u32 page_off, phy_addr, nvram_cmd;
11608                 __be32 data;
11609
11610                 memcpy(&data, buf + i, 4);
11611                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11612
11613                 page_off = offset % tp->nvram_pagesize;
11614
11615                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11616
11617                 tw32(NVRAM_ADDR, phy_addr);
11618
11619                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11620
11621                 if ((page_off == 0) || (i == 0))
11622                         nvram_cmd |= NVRAM_CMD_FIRST;
11623                 if (page_off == (tp->nvram_pagesize - 4))
11624                         nvram_cmd |= NVRAM_CMD_LAST;
11625
11626                 if (i == (len - 4))
11627                         nvram_cmd |= NVRAM_CMD_LAST;
11628
11629                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11630                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11631                     (tp->nvram_jedecnum == JEDEC_ST) &&
11632                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11633
11634                         if ((ret = tg3_nvram_exec_cmd(tp,
11635                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11636                                 NVRAM_CMD_DONE)))
11637
11638                                 break;
11639                 }
11640                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11641                         /* We always do complete word writes to eeprom. */
11642                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11643                 }
11644
11645                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11646                         break;
11647         }
11648         return ret;
11649 }
11650
11651 /* offset and length are dword aligned */
11652 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11653 {
11654         int ret;
11655
11656         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11657                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11658                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11659                 udelay(40);
11660         }
11661
11662         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11663                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11664         }
11665         else {
11666                 u32 grc_mode;
11667
11668                 ret = tg3_nvram_lock(tp);
11669                 if (ret)
11670                         return ret;
11671
11672                 tg3_enable_nvram_access(tp);
11673                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11674                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11675                         tw32(NVRAM_WRITE1, 0x406);
11676
11677                 grc_mode = tr32(GRC_MODE);
11678                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11679
11680                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11681                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11682
11683                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11684                                 buf);
11685                 }
11686                 else {
11687                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11688                                 buf);
11689                 }
11690
11691                 grc_mode = tr32(GRC_MODE);
11692                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11693
11694                 tg3_disable_nvram_access(tp);
11695                 tg3_nvram_unlock(tp);
11696         }
11697
11698         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11699                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11700                 udelay(40);
11701         }
11702
11703         return ret;
11704 }
11705
11706 struct subsys_tbl_ent {
11707         u16 subsys_vendor, subsys_devid;
11708         u32 phy_id;
11709 };
11710
11711 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11712         /* Broadcom boards. */
11713         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11714         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11715         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11716         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11717         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11718         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11719         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11720         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11721         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11722         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11723         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11724
11725         /* 3com boards. */
11726         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11727         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11728         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11729         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11730         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11731
11732         /* DELL boards. */
11733         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11734         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11735         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11736         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11737
11738         /* Compaq boards. */
11739         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11740         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11741         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11742         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11743         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11744
11745         /* IBM boards. */
11746         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11747 };
11748
11749 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11750 {
11751         int i;
11752
11753         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11754                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11755                      tp->pdev->subsystem_vendor) &&
11756                     (subsys_id_to_phy_id[i].subsys_devid ==
11757                      tp->pdev->subsystem_device))
11758                         return &subsys_id_to_phy_id[i];
11759         }
11760         return NULL;
11761 }
11762
11763 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11764 {
11765         u32 val;
11766         u16 pmcsr;
11767
11768         /* On some early chips the SRAM cannot be accessed in D3hot state,
11769          * so need make sure we're in D0.
11770          */
11771         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11772         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11773         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11774         msleep(1);
11775
11776         /* Make sure register accesses (indirect or otherwise)
11777          * will function correctly.
11778          */
11779         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11780                                tp->misc_host_ctrl);
11781
11782         /* The memory arbiter has to be enabled in order for SRAM accesses
11783          * to succeed.  Normally on powerup the tg3 chip firmware will make
11784          * sure it is enabled, but other entities such as system netboot
11785          * code might disable it.
11786          */
11787         val = tr32(MEMARB_MODE);
11788         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11789
11790         tp->phy_id = PHY_ID_INVALID;
11791         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11792
11793         /* Assume an onboard device and WOL capable by default.  */
11794         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11795
11796         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11797                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11798                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11799                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11800                 }
11801                 val = tr32(VCPU_CFGSHDW);
11802                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11803                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11804                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11805                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11806                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11807                 goto done;
11808         }
11809
11810         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11811         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11812                 u32 nic_cfg, led_cfg;
11813                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11814                 int eeprom_phy_serdes = 0;
11815
11816                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11817                 tp->nic_sram_data_cfg = nic_cfg;
11818
11819                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11820                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11821                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11822                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11823                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11824                     (ver > 0) && (ver < 0x100))
11825                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11826
11827                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11828                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11829
11830                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11831                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11832                         eeprom_phy_serdes = 1;
11833
11834                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11835                 if (nic_phy_id != 0) {
11836                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11837                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11838
11839                         eeprom_phy_id  = (id1 >> 16) << 10;
11840                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11841                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11842                 } else
11843                         eeprom_phy_id = 0;
11844
11845                 tp->phy_id = eeprom_phy_id;
11846                 if (eeprom_phy_serdes) {
11847                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11848                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11849                         else
11850                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11851                 }
11852
11853                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11854                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11855                                     SHASTA_EXT_LED_MODE_MASK);
11856                 else
11857                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11858
11859                 switch (led_cfg) {
11860                 default:
11861                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11862                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11863                         break;
11864
11865                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11866                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11867                         break;
11868
11869                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11870                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11871
11872                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11873                          * read on some older 5700/5701 bootcode.
11874                          */
11875                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11876                             ASIC_REV_5700 ||
11877                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11878                             ASIC_REV_5701)
11879                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11880
11881                         break;
11882
11883                 case SHASTA_EXT_LED_SHARED:
11884                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11885                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11886                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11887                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11888                                                  LED_CTRL_MODE_PHY_2);
11889                         break;
11890
11891                 case SHASTA_EXT_LED_MAC:
11892                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11893                         break;
11894
11895                 case SHASTA_EXT_LED_COMBO:
11896                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11897                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11898                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11899                                                  LED_CTRL_MODE_PHY_2);
11900                         break;
11901
11902                 }
11903
11904                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11905                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11906                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11907                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11908
11909                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11910                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11911
11912                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11913                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11914                         if ((tp->pdev->subsystem_vendor ==
11915                              PCI_VENDOR_ID_ARIMA) &&
11916                             (tp->pdev->subsystem_device == 0x205a ||
11917                              tp->pdev->subsystem_device == 0x2063))
11918                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11919                 } else {
11920                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11921                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11922                 }
11923
11924                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11925                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11926                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11927                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11928                 }
11929
11930                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11931                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11932                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11933
11934                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11935                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11936                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11937
11938                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11939                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11940                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11941
11942                 if (cfg2 & (1 << 17))
11943                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11944
11945                 /* serdes signal pre-emphasis in register 0x590 set by */
11946                 /* bootcode if bit 18 is set */
11947                 if (cfg2 & (1 << 18))
11948                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11949
11950                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11951                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11952                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11953                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11954
11955                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11956                         u32 cfg3;
11957
11958                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11959                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11960                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11961                 }
11962
11963                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11964                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11965                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11966                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11967                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11968                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11969         }
11970 done:
11971         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11972         device_set_wakeup_enable(&tp->pdev->dev,
11973                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11974 }
11975
11976 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11977 {
11978         int i;
11979         u32 val;
11980
11981         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11982         tw32(OTP_CTRL, cmd);
11983
11984         /* Wait for up to 1 ms for command to execute. */
11985         for (i = 0; i < 100; i++) {
11986                 val = tr32(OTP_STATUS);
11987                 if (val & OTP_STATUS_CMD_DONE)
11988                         break;
11989                 udelay(10);
11990         }
11991
11992         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11993 }
11994
11995 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11996  * configuration is a 32-bit value that straddles the alignment boundary.
11997  * We do two 32-bit reads and then shift and merge the results.
11998  */
11999 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12000 {
12001         u32 bhalf_otp, thalf_otp;
12002
12003         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12004
12005         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12006                 return 0;
12007
12008         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12009
12010         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12011                 return 0;
12012
12013         thalf_otp = tr32(OTP_READ_DATA);
12014
12015         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12016
12017         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12018                 return 0;
12019
12020         bhalf_otp = tr32(OTP_READ_DATA);
12021
12022         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12023 }
12024
12025 static int __devinit tg3_phy_probe(struct tg3 *tp)
12026 {
12027         u32 hw_phy_id_1, hw_phy_id_2;
12028         u32 hw_phy_id, hw_phy_id_masked;
12029         int err;
12030
12031         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12032                 return tg3_phy_init(tp);
12033
12034         /* Reading the PHY ID register can conflict with ASF
12035          * firmware access to the PHY hardware.
12036          */
12037         err = 0;
12038         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12039             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12040                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12041         } else {
12042                 /* Now read the physical PHY_ID from the chip and verify
12043                  * that it is sane.  If it doesn't look good, we fall back
12044                  * to either the hard-coded table based PHY_ID and failing
12045                  * that the value found in the eeprom area.
12046                  */
12047                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12048                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12049
12050                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12051                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12052                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12053
12054                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12055         }
12056
12057         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12058                 tp->phy_id = hw_phy_id;
12059                 if (hw_phy_id_masked == PHY_ID_BCM8002)
12060                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12061                 else
12062                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12063         } else {
12064                 if (tp->phy_id != PHY_ID_INVALID) {
12065                         /* Do nothing, phy ID already set up in
12066                          * tg3_get_eeprom_hw_cfg().
12067                          */
12068                 } else {
12069                         struct subsys_tbl_ent *p;
12070
12071                         /* No eeprom signature?  Try the hardcoded
12072                          * subsys device table.
12073                          */
12074                         p = lookup_by_subsys(tp);
12075                         if (!p)
12076                                 return -ENODEV;
12077
12078                         tp->phy_id = p->phy_id;
12079                         if (!tp->phy_id ||
12080                             tp->phy_id == PHY_ID_BCM8002)
12081                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12082                 }
12083         }
12084
12085         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12086             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12087             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12088                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12089
12090                 tg3_readphy(tp, MII_BMSR, &bmsr);
12091                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12092                     (bmsr & BMSR_LSTATUS))
12093                         goto skip_phy_reset;
12094
12095                 err = tg3_phy_reset(tp);
12096                 if (err)
12097                         return err;
12098
12099                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12100                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12101                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12102                 tg3_ctrl = 0;
12103                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12104                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12105                                     MII_TG3_CTRL_ADV_1000_FULL);
12106                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12107                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12108                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12109                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12110                 }
12111
12112                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12113                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12114                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12115                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12116                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12117
12118                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12119                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12120
12121                         tg3_writephy(tp, MII_BMCR,
12122                                      BMCR_ANENABLE | BMCR_ANRESTART);
12123                 }
12124                 tg3_phy_set_wirespeed(tp);
12125
12126                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12127                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12128                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12129         }
12130
12131 skip_phy_reset:
12132         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12133                 err = tg3_init_5401phy_dsp(tp);
12134                 if (err)
12135                         return err;
12136         }
12137
12138         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12139                 err = tg3_init_5401phy_dsp(tp);
12140         }
12141
12142         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12143                 tp->link_config.advertising =
12144                         (ADVERTISED_1000baseT_Half |
12145                          ADVERTISED_1000baseT_Full |
12146                          ADVERTISED_Autoneg |
12147                          ADVERTISED_FIBRE);
12148         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12149                 tp->link_config.advertising &=
12150                         ~(ADVERTISED_1000baseT_Half |
12151                           ADVERTISED_1000baseT_Full);
12152
12153         return err;
12154 }
12155
12156 static void __devinit tg3_read_partno(struct tg3 *tp)
12157 {
12158         unsigned char vpd_data[256];   /* in little-endian format */
12159         unsigned int i;
12160         u32 magic;
12161
12162         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12163             tg3_nvram_read(tp, 0x0, &magic))
12164                 goto out_not_found;
12165
12166         if (magic == TG3_EEPROM_MAGIC) {
12167                 for (i = 0; i < 256; i += 4) {
12168                         u32 tmp;
12169
12170                         /* The data is in little-endian format in NVRAM.
12171                          * Use the big-endian read routines to preserve
12172                          * the byte order as it exists in NVRAM.
12173                          */
12174                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12175                                 goto out_not_found;
12176
12177                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12178                 }
12179         } else {
12180                 int vpd_cap;
12181
12182                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12183                 for (i = 0; i < 256; i += 4) {
12184                         u32 tmp, j = 0;
12185                         __le32 v;
12186                         u16 tmp16;
12187
12188                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12189                                               i);
12190                         while (j++ < 100) {
12191                                 pci_read_config_word(tp->pdev, vpd_cap +
12192                                                      PCI_VPD_ADDR, &tmp16);
12193                                 if (tmp16 & 0x8000)
12194                                         break;
12195                                 msleep(1);
12196                         }
12197                         if (!(tmp16 & 0x8000))
12198                                 goto out_not_found;
12199
12200                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12201                                               &tmp);
12202                         v = cpu_to_le32(tmp);
12203                         memcpy(&vpd_data[i], &v, sizeof(v));
12204                 }
12205         }
12206
12207         /* Now parse and find the part number. */
12208         for (i = 0; i < 254; ) {
12209                 unsigned char val = vpd_data[i];
12210                 unsigned int block_end;
12211
12212                 if (val == 0x82 || val == 0x91) {
12213                         i = (i + 3 +
12214                              (vpd_data[i + 1] +
12215                               (vpd_data[i + 2] << 8)));
12216                         continue;
12217                 }
12218
12219                 if (val != 0x90)
12220                         goto out_not_found;
12221
12222                 block_end = (i + 3 +
12223                              (vpd_data[i + 1] +
12224                               (vpd_data[i + 2] << 8)));
12225                 i += 3;
12226
12227                 if (block_end > 256)
12228                         goto out_not_found;
12229
12230                 while (i < (block_end - 2)) {
12231                         if (vpd_data[i + 0] == 'P' &&
12232                             vpd_data[i + 1] == 'N') {
12233                                 int partno_len = vpd_data[i + 2];
12234
12235                                 i += 3;
12236                                 if (partno_len > 24 || (partno_len + i) > 256)
12237                                         goto out_not_found;
12238
12239                                 memcpy(tp->board_part_number,
12240                                        &vpd_data[i], partno_len);
12241
12242                                 /* Success. */
12243                                 return;
12244                         }
12245                         i += 3 + vpd_data[i + 2];
12246                 }
12247
12248                 /* Part number not found. */
12249                 goto out_not_found;
12250         }
12251
12252 out_not_found:
12253         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12254                 strcpy(tp->board_part_number, "BCM95906");
12255         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12256                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12257                 strcpy(tp->board_part_number, "BCM57780");
12258         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12259                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12260                 strcpy(tp->board_part_number, "BCM57760");
12261         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12262                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12263                 strcpy(tp->board_part_number, "BCM57790");
12264         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12265                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12266                 strcpy(tp->board_part_number, "BCM57788");
12267         else
12268                 strcpy(tp->board_part_number, "none");
12269 }
12270
12271 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12272 {
12273         u32 val;
12274
12275         if (tg3_nvram_read(tp, offset, &val) ||
12276             (val & 0xfc000000) != 0x0c000000 ||
12277             tg3_nvram_read(tp, offset + 4, &val) ||
12278             val != 0)
12279                 return 0;
12280
12281         return 1;
12282 }
12283
12284 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12285 {
12286         u32 val, offset, start, ver_offset;
12287         int i;
12288         bool newver = false;
12289
12290         if (tg3_nvram_read(tp, 0xc, &offset) ||
12291             tg3_nvram_read(tp, 0x4, &start))
12292                 return;
12293
12294         offset = tg3_nvram_logical_addr(tp, offset);
12295
12296         if (tg3_nvram_read(tp, offset, &val))
12297                 return;
12298
12299         if ((val & 0xfc000000) == 0x0c000000) {
12300                 if (tg3_nvram_read(tp, offset + 4, &val))
12301                         return;
12302
12303                 if (val == 0)
12304                         newver = true;
12305         }
12306
12307         if (newver) {
12308                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12309                         return;
12310
12311                 offset = offset + ver_offset - start;
12312                 for (i = 0; i < 16; i += 4) {
12313                         __be32 v;
12314                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12315                                 return;
12316
12317                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12318                 }
12319         } else {
12320                 u32 major, minor;
12321
12322                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12323                         return;
12324
12325                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12326                         TG3_NVM_BCVER_MAJSFT;
12327                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12328                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12329         }
12330 }
12331
12332 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12333 {
12334         u32 val, major, minor;
12335
12336         /* Use native endian representation */
12337         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12338                 return;
12339
12340         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12341                 TG3_NVM_HWSB_CFG1_MAJSFT;
12342         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12343                 TG3_NVM_HWSB_CFG1_MINSFT;
12344
12345         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12346 }
12347
12348 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12349 {
12350         u32 offset, major, minor, build;
12351
12352         tp->fw_ver[0] = 's';
12353         tp->fw_ver[1] = 'b';
12354         tp->fw_ver[2] = '\0';
12355
12356         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12357                 return;
12358
12359         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12360         case TG3_EEPROM_SB_REVISION_0:
12361                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12362                 break;
12363         case TG3_EEPROM_SB_REVISION_2:
12364                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12365                 break;
12366         case TG3_EEPROM_SB_REVISION_3:
12367                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12368                 break;
12369         default:
12370                 return;
12371         }
12372
12373         if (tg3_nvram_read(tp, offset, &val))
12374                 return;
12375
12376         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12377                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12378         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12379                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12380         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12381
12382         if (minor > 99 || build > 26)
12383                 return;
12384
12385         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12386
12387         if (build > 0) {
12388                 tp->fw_ver[8] = 'a' + build - 1;
12389                 tp->fw_ver[9] = '\0';
12390         }
12391 }
12392
12393 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12394 {
12395         u32 val, offset, start;
12396         int i, vlen;
12397
12398         for (offset = TG3_NVM_DIR_START;
12399              offset < TG3_NVM_DIR_END;
12400              offset += TG3_NVM_DIRENT_SIZE) {
12401                 if (tg3_nvram_read(tp, offset, &val))
12402                         return;
12403
12404                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12405                         break;
12406         }
12407
12408         if (offset == TG3_NVM_DIR_END)
12409                 return;
12410
12411         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12412                 start = 0x08000000;
12413         else if (tg3_nvram_read(tp, offset - 4, &start))
12414                 return;
12415
12416         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12417             !tg3_fw_img_is_valid(tp, offset) ||
12418             tg3_nvram_read(tp, offset + 8, &val))
12419                 return;
12420
12421         offset += val - start;
12422
12423         vlen = strlen(tp->fw_ver);
12424
12425         tp->fw_ver[vlen++] = ',';
12426         tp->fw_ver[vlen++] = ' ';
12427
12428         for (i = 0; i < 4; i++) {
12429                 __be32 v;
12430                 if (tg3_nvram_read_be32(tp, offset, &v))
12431                         return;
12432
12433                 offset += sizeof(v);
12434
12435                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12436                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12437                         break;
12438                 }
12439
12440                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12441                 vlen += sizeof(v);
12442         }
12443 }
12444
12445 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12446 {
12447         int vlen;
12448         u32 apedata;
12449
12450         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12451             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12452                 return;
12453
12454         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12455         if (apedata != APE_SEG_SIG_MAGIC)
12456                 return;
12457
12458         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12459         if (!(apedata & APE_FW_STATUS_READY))
12460                 return;
12461
12462         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12463
12464         vlen = strlen(tp->fw_ver);
12465
12466         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12467                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12468                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12469                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12470                  (apedata & APE_FW_VERSION_BLDMSK));
12471 }
12472
12473 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12474 {
12475         u32 val;
12476
12477         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12478                 tp->fw_ver[0] = 's';
12479                 tp->fw_ver[1] = 'b';
12480                 tp->fw_ver[2] = '\0';
12481
12482                 return;
12483         }
12484
12485         if (tg3_nvram_read(tp, 0, &val))
12486                 return;
12487
12488         if (val == TG3_EEPROM_MAGIC)
12489                 tg3_read_bc_ver(tp);
12490         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12491                 tg3_read_sb_ver(tp, val);
12492         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12493                 tg3_read_hwsb_ver(tp);
12494         else
12495                 return;
12496
12497         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12498              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12499                 return;
12500
12501         tg3_read_mgmtfw_ver(tp);
12502
12503         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12504 }
12505
12506 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12507
12508 static int __devinit tg3_get_invariants(struct tg3 *tp)
12509 {
12510         static struct pci_device_id write_reorder_chipsets[] = {
12511                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12512                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12513                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12514                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12515                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12516                              PCI_DEVICE_ID_VIA_8385_0) },
12517                 { },
12518         };
12519         u32 misc_ctrl_reg;
12520         u32 pci_state_reg, grc_misc_cfg;
12521         u32 val;
12522         u16 pci_cmd;
12523         int err;
12524
12525         /* Force memory write invalidate off.  If we leave it on,
12526          * then on 5700_BX chips we have to enable a workaround.
12527          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12528          * to match the cacheline size.  The Broadcom driver have this
12529          * workaround but turns MWI off all the times so never uses
12530          * it.  This seems to suggest that the workaround is insufficient.
12531          */
12532         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12533         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12534         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12535
12536         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12537          * has the register indirect write enable bit set before
12538          * we try to access any of the MMIO registers.  It is also
12539          * critical that the PCI-X hw workaround situation is decided
12540          * before that as well.
12541          */
12542         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12543                               &misc_ctrl_reg);
12544
12545         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12546                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12547         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12548                 u32 prod_id_asic_rev;
12549
12550                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12551                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12552                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12553                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12554                         pci_read_config_dword(tp->pdev,
12555                                               TG3PCI_GEN2_PRODID_ASICREV,
12556                                               &prod_id_asic_rev);
12557                 else
12558                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12559                                               &prod_id_asic_rev);
12560
12561                 tp->pci_chip_rev_id = prod_id_asic_rev;
12562         }
12563
12564         /* Wrong chip ID in 5752 A0. This code can be removed later
12565          * as A0 is not in production.
12566          */
12567         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12568                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12569
12570         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12571          * we need to disable memory and use config. cycles
12572          * only to access all registers. The 5702/03 chips
12573          * can mistakenly decode the special cycles from the
12574          * ICH chipsets as memory write cycles, causing corruption
12575          * of register and memory space. Only certain ICH bridges
12576          * will drive special cycles with non-zero data during the
12577          * address phase which can fall within the 5703's address
12578          * range. This is not an ICH bug as the PCI spec allows
12579          * non-zero address during special cycles. However, only
12580          * these ICH bridges are known to drive non-zero addresses
12581          * during special cycles.
12582          *
12583          * Since special cycles do not cross PCI bridges, we only
12584          * enable this workaround if the 5703 is on the secondary
12585          * bus of these ICH bridges.
12586          */
12587         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12588             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12589                 static struct tg3_dev_id {
12590                         u32     vendor;
12591                         u32     device;
12592                         u32     rev;
12593                 } ich_chipsets[] = {
12594                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12595                           PCI_ANY_ID },
12596                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12597                           PCI_ANY_ID },
12598                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12599                           0xa },
12600                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12601                           PCI_ANY_ID },
12602                         { },
12603                 };
12604                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12605                 struct pci_dev *bridge = NULL;
12606
12607                 while (pci_id->vendor != 0) {
12608                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12609                                                 bridge);
12610                         if (!bridge) {
12611                                 pci_id++;
12612                                 continue;
12613                         }
12614                         if (pci_id->rev != PCI_ANY_ID) {
12615                                 if (bridge->revision > pci_id->rev)
12616                                         continue;
12617                         }
12618                         if (bridge->subordinate &&
12619                             (bridge->subordinate->number ==
12620                              tp->pdev->bus->number)) {
12621
12622                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12623                                 pci_dev_put(bridge);
12624                                 break;
12625                         }
12626                 }
12627         }
12628
12629         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12630                 static struct tg3_dev_id {
12631                         u32     vendor;
12632                         u32     device;
12633                 } bridge_chipsets[] = {
12634                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12635                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12636                         { },
12637                 };
12638                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12639                 struct pci_dev *bridge = NULL;
12640
12641                 while (pci_id->vendor != 0) {
12642                         bridge = pci_get_device(pci_id->vendor,
12643                                                 pci_id->device,
12644                                                 bridge);
12645                         if (!bridge) {
12646                                 pci_id++;
12647                                 continue;
12648                         }
12649                         if (bridge->subordinate &&
12650                             (bridge->subordinate->number <=
12651                              tp->pdev->bus->number) &&
12652                             (bridge->subordinate->subordinate >=
12653                              tp->pdev->bus->number)) {
12654                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12655                                 pci_dev_put(bridge);
12656                                 break;
12657                         }
12658                 }
12659         }
12660
12661         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12662          * DMA addresses > 40-bit. This bridge may have other additional
12663          * 57xx devices behind it in some 4-port NIC designs for example.
12664          * Any tg3 device found behind the bridge will also need the 40-bit
12665          * DMA workaround.
12666          */
12667         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12668             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12669                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12670                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12671                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12672         }
12673         else {
12674                 struct pci_dev *bridge = NULL;
12675
12676                 do {
12677                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12678                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12679                                                 bridge);
12680                         if (bridge && bridge->subordinate &&
12681                             (bridge->subordinate->number <=
12682                              tp->pdev->bus->number) &&
12683                             (bridge->subordinate->subordinate >=
12684                              tp->pdev->bus->number)) {
12685                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12686                                 pci_dev_put(bridge);
12687                                 break;
12688                         }
12689                 } while (bridge);
12690         }
12691
12692         /* Initialize misc host control in PCI block. */
12693         tp->misc_host_ctrl |= (misc_ctrl_reg &
12694                                MISC_HOST_CTRL_CHIPREV);
12695         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12696                                tp->misc_host_ctrl);
12697
12698         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12699             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12700             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12701                 tp->pdev_peer = tg3_find_peer(tp);
12702
12703         /* Intentionally exclude ASIC_REV_5906 */
12704         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12705             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12706             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12707             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12708             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12709             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12710             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12711                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12712
12713         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12714             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12715             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12716             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12717             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12718                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12719
12720         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12721             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12722                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12723
12724         /* 5700 B0 chips do not support checksumming correctly due
12725          * to hardware bugs.
12726          */
12727         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12728                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12729         else {
12730                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12731                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12732                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12733                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12734         }
12735
12736         /* Determine TSO capabilities */
12737         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12738                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12739         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12740                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12741                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12742         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12743                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12744                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12745                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12746                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12747         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12748                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12749                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12750                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12751                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12752                         tp->fw_needed = FIRMWARE_TG3TSO5;
12753                 else
12754                         tp->fw_needed = FIRMWARE_TG3TSO;
12755         }
12756
12757         tp->irq_max = 1;
12758
12759         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12760                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12761                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12762                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12763                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12764                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12765                      tp->pdev_peer == tp->pdev))
12766                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12767
12768                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12769                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12770                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12771                 }
12772
12773                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12774                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12775                         tp->irq_max = TG3_IRQ_MAX_VECS;
12776                 }
12777         }
12778
12779         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12780             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12781                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12782         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12783                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12784                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12785         }
12786
12787         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12788              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12789             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12790                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12791
12792         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12793                               &pci_state_reg);
12794
12795         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12796         if (tp->pcie_cap != 0) {
12797                 u16 lnkctl;
12798
12799                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12800
12801                 pcie_set_readrq(tp->pdev, 4096);
12802
12803                 pci_read_config_word(tp->pdev,
12804                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12805                                      &lnkctl);
12806                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12807                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12808                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12809                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12810                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12811                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12812                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12813                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12814                 }
12815         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12816                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12817         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12818                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12819                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12820                 if (!tp->pcix_cap) {
12821                         printk(KERN_ERR PFX "Cannot find PCI-X "
12822                                             "capability, aborting.\n");
12823                         return -EIO;
12824                 }
12825
12826                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12827                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12828         }
12829
12830         /* If we have an AMD 762 or VIA K8T800 chipset, write
12831          * reordering to the mailbox registers done by the host
12832          * controller can cause major troubles.  We read back from
12833          * every mailbox register write to force the writes to be
12834          * posted to the chip in order.
12835          */
12836         if (pci_dev_present(write_reorder_chipsets) &&
12837             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12838                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12839
12840         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12841                              &tp->pci_cacheline_sz);
12842         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12843                              &tp->pci_lat_timer);
12844         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12845             tp->pci_lat_timer < 64) {
12846                 tp->pci_lat_timer = 64;
12847                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12848                                       tp->pci_lat_timer);
12849         }
12850
12851         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12852                 /* 5700 BX chips need to have their TX producer index
12853                  * mailboxes written twice to workaround a bug.
12854                  */
12855                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12856
12857                 /* If we are in PCI-X mode, enable register write workaround.
12858                  *
12859                  * The workaround is to use indirect register accesses
12860                  * for all chip writes not to mailbox registers.
12861                  */
12862                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12863                         u32 pm_reg;
12864
12865                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12866
12867                         /* The chip can have it's power management PCI config
12868                          * space registers clobbered due to this bug.
12869                          * So explicitly force the chip into D0 here.
12870                          */
12871                         pci_read_config_dword(tp->pdev,
12872                                               tp->pm_cap + PCI_PM_CTRL,
12873                                               &pm_reg);
12874                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12875                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12876                         pci_write_config_dword(tp->pdev,
12877                                                tp->pm_cap + PCI_PM_CTRL,
12878                                                pm_reg);
12879
12880                         /* Also, force SERR#/PERR# in PCI command. */
12881                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12882                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12883                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12884                 }
12885         }
12886
12887         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12888                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12889         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12890                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12891
12892         /* Chip-specific fixup from Broadcom driver */
12893         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12894             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12895                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12896                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12897         }
12898
12899         /* Default fast path register access methods */
12900         tp->read32 = tg3_read32;
12901         tp->write32 = tg3_write32;
12902         tp->read32_mbox = tg3_read32;
12903         tp->write32_mbox = tg3_write32;
12904         tp->write32_tx_mbox = tg3_write32;
12905         tp->write32_rx_mbox = tg3_write32;
12906
12907         /* Various workaround register access methods */
12908         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12909                 tp->write32 = tg3_write_indirect_reg32;
12910         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12911                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12912                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12913                 /*
12914                  * Back to back register writes can cause problems on these
12915                  * chips, the workaround is to read back all reg writes
12916                  * except those to mailbox regs.
12917                  *
12918                  * See tg3_write_indirect_reg32().
12919                  */
12920                 tp->write32 = tg3_write_flush_reg32;
12921         }
12922
12923         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12924             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12925                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12926                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12927                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12928         }
12929
12930         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12931                 tp->read32 = tg3_read_indirect_reg32;
12932                 tp->write32 = tg3_write_indirect_reg32;
12933                 tp->read32_mbox = tg3_read_indirect_mbox;
12934                 tp->write32_mbox = tg3_write_indirect_mbox;
12935                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12936                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12937
12938                 iounmap(tp->regs);
12939                 tp->regs = NULL;
12940
12941                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12942                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12943                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12944         }
12945         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12946                 tp->read32_mbox = tg3_read32_mbox_5906;
12947                 tp->write32_mbox = tg3_write32_mbox_5906;
12948                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12949                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12950         }
12951
12952         if (tp->write32 == tg3_write_indirect_reg32 ||
12953             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12954              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12955               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12956                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12957
12958         /* Get eeprom hw config before calling tg3_set_power_state().
12959          * In particular, the TG3_FLG2_IS_NIC flag must be
12960          * determined before calling tg3_set_power_state() so that
12961          * we know whether or not to switch out of Vaux power.
12962          * When the flag is set, it means that GPIO1 is used for eeprom
12963          * write protect and also implies that it is a LOM where GPIOs
12964          * are not used to switch power.
12965          */
12966         tg3_get_eeprom_hw_cfg(tp);
12967
12968         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12969                 /* Allow reads and writes to the
12970                  * APE register and memory space.
12971                  */
12972                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12973                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12974                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12975                                        pci_state_reg);
12976         }
12977
12978         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12979             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12980             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12981             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12982             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12983                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12984
12985         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12986          * GPIO1 driven high will bring 5700's external PHY out of reset.
12987          * It is also used as eeprom write protect on LOMs.
12988          */
12989         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12990         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12991             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12992                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12993                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12994         /* Unused GPIO3 must be driven as output on 5752 because there
12995          * are no pull-up resistors on unused GPIO pins.
12996          */
12997         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12998                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12999
13000         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13002                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13003
13004         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13005             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13006                 /* Turn off the debug UART. */
13007                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13008                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13009                         /* Keep VMain power. */
13010                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13011                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13012         }
13013
13014         /* Force the chip into D0. */
13015         err = tg3_set_power_state(tp, PCI_D0);
13016         if (err) {
13017                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13018                        pci_name(tp->pdev));
13019                 return err;
13020         }
13021
13022         /* Derive initial jumbo mode from MTU assigned in
13023          * ether_setup() via the alloc_etherdev() call
13024          */
13025         if (tp->dev->mtu > ETH_DATA_LEN &&
13026             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13027                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13028
13029         /* Determine WakeOnLan speed to use. */
13030         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13031             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13032             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13033             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13034                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13035         } else {
13036                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13037         }
13038
13039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13040                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13041
13042         /* A few boards don't want Ethernet@WireSpeed phy feature */
13043         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13044             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13045              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13046              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13047             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13048             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13049                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13050
13051         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13052             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13053                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13054         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13055                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13056
13057         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13058             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13059             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13060             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13061             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13062                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13063                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13064                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13065                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13066                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13067                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13068                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13069                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13070                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13071                 } else
13072                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13073         }
13074
13075         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13076             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13077                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13078                 if (tp->phy_otp == 0)
13079                         tp->phy_otp = TG3_OTP_DEFAULT;
13080         }
13081
13082         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13083                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13084         else
13085                 tp->mi_mode = MAC_MI_MODE_BASE;
13086
13087         tp->coalesce_mode = 0;
13088         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13089             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13090                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13091
13092         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13093             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13094                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13095
13096         err = tg3_mdio_init(tp);
13097         if (err)
13098                 return err;
13099
13100         /* Initialize data/descriptor byte/word swapping. */
13101         val = tr32(GRC_MODE);
13102         val &= GRC_MODE_HOST_STACKUP;
13103         tw32(GRC_MODE, val | tp->grc_mode);
13104
13105         tg3_switch_clocks(tp);
13106
13107         /* Clear this out for sanity. */
13108         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13109
13110         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13111                               &pci_state_reg);
13112         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13113             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13114                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13115
13116                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13117                     chiprevid == CHIPREV_ID_5701_B0 ||
13118                     chiprevid == CHIPREV_ID_5701_B2 ||
13119                     chiprevid == CHIPREV_ID_5701_B5) {
13120                         void __iomem *sram_base;
13121
13122                         /* Write some dummy words into the SRAM status block
13123                          * area, see if it reads back correctly.  If the return
13124                          * value is bad, force enable the PCIX workaround.
13125                          */
13126                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13127
13128                         writel(0x00000000, sram_base);
13129                         writel(0x00000000, sram_base + 4);
13130                         writel(0xffffffff, sram_base + 4);
13131                         if (readl(sram_base) != 0x00000000)
13132                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13133                 }
13134         }
13135
13136         udelay(50);
13137         tg3_nvram_init(tp);
13138
13139         grc_misc_cfg = tr32(GRC_MISC_CFG);
13140         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13141
13142         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13143             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13144              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13145                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13146
13147         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13148             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13149                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13150         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13151                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13152                                       HOSTCC_MODE_CLRTICK_TXBD);
13153
13154                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13155                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13156                                        tp->misc_host_ctrl);
13157         }
13158
13159         /* Preserve the APE MAC_MODE bits */
13160         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13161                 tp->mac_mode = tr32(MAC_MODE) |
13162                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13163         else
13164                 tp->mac_mode = TG3_DEF_MAC_MODE;
13165
13166         /* these are limited to 10/100 only */
13167         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13168              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13169             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13170              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13171              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13172               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13173               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13174             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13175              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13176               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13177               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13178             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13179             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13180                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13181
13182         err = tg3_phy_probe(tp);
13183         if (err) {
13184                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13185                        pci_name(tp->pdev), err);
13186                 /* ... but do not return immediately ... */
13187                 tg3_mdio_fini(tp);
13188         }
13189
13190         tg3_read_partno(tp);
13191         tg3_read_fw_ver(tp);
13192
13193         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13194                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13195         } else {
13196                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13197                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13198                 else
13199                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13200         }
13201
13202         /* 5700 {AX,BX} chips have a broken status block link
13203          * change bit implementation, so we must use the
13204          * status register in those cases.
13205          */
13206         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13207                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13208         else
13209                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13210
13211         /* The led_ctrl is set during tg3_phy_probe, here we might
13212          * have to force the link status polling mechanism based
13213          * upon subsystem IDs.
13214          */
13215         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13216             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13217             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13218                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13219                                   TG3_FLAG_USE_LINKCHG_REG);
13220         }
13221
13222         /* For all SERDES we poll the MAC status register. */
13223         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13224                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13225         else
13226                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13227
13228         tp->rx_offset = NET_IP_ALIGN;
13229         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13230             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13231                 tp->rx_offset = 0;
13232
13233         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13234
13235         /* Increment the rx prod index on the rx std ring by at most
13236          * 8 for these chips to workaround hw errata.
13237          */
13238         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13239             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13240             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13241                 tp->rx_std_max_post = 8;
13242
13243         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13244                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13245                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13246
13247         return err;
13248 }
13249
13250 #ifdef CONFIG_SPARC
13251 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13252 {
13253         struct net_device *dev = tp->dev;
13254         struct pci_dev *pdev = tp->pdev;
13255         struct device_node *dp = pci_device_to_OF_node(pdev);
13256         const unsigned char *addr;
13257         int len;
13258
13259         addr = of_get_property(dp, "local-mac-address", &len);
13260         if (addr && len == 6) {
13261                 memcpy(dev->dev_addr, addr, 6);
13262                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13263                 return 0;
13264         }
13265         return -ENODEV;
13266 }
13267
13268 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13269 {
13270         struct net_device *dev = tp->dev;
13271
13272         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13273         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13274         return 0;
13275 }
13276 #endif
13277
13278 static int __devinit tg3_get_device_address(struct tg3 *tp)
13279 {
13280         struct net_device *dev = tp->dev;
13281         u32 hi, lo, mac_offset;
13282         int addr_ok = 0;
13283
13284 #ifdef CONFIG_SPARC
13285         if (!tg3_get_macaddr_sparc(tp))
13286                 return 0;
13287 #endif
13288
13289         mac_offset = 0x7c;
13290         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13291             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13292                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13293                         mac_offset = 0xcc;
13294                 if (tg3_nvram_lock(tp))
13295                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13296                 else
13297                         tg3_nvram_unlock(tp);
13298         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13299                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13300                         mac_offset = 0xcc;
13301         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13302                 mac_offset = 0x10;
13303
13304         /* First try to get it from MAC address mailbox. */
13305         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13306         if ((hi >> 16) == 0x484b) {
13307                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13308                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13309
13310                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13311                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13312                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13313                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13314                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13315
13316                 /* Some old bootcode may report a 0 MAC address in SRAM */
13317                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13318         }
13319         if (!addr_ok) {
13320                 /* Next, try NVRAM. */
13321                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13322                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13323                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13324                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13325                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13326                 }
13327                 /* Finally just fetch it out of the MAC control regs. */
13328                 else {
13329                         hi = tr32(MAC_ADDR_0_HIGH);
13330                         lo = tr32(MAC_ADDR_0_LOW);
13331
13332                         dev->dev_addr[5] = lo & 0xff;
13333                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13334                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13335                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13336                         dev->dev_addr[1] = hi & 0xff;
13337                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13338                 }
13339         }
13340
13341         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13342 #ifdef CONFIG_SPARC
13343                 if (!tg3_get_default_macaddr_sparc(tp))
13344                         return 0;
13345 #endif
13346                 return -EINVAL;
13347         }
13348         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13349         return 0;
13350 }
13351
13352 #define BOUNDARY_SINGLE_CACHELINE       1
13353 #define BOUNDARY_MULTI_CACHELINE        2
13354
13355 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13356 {
13357         int cacheline_size;
13358         u8 byte;
13359         int goal;
13360
13361         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13362         if (byte == 0)
13363                 cacheline_size = 1024;
13364         else
13365                 cacheline_size = (int) byte * 4;
13366
13367         /* On 5703 and later chips, the boundary bits have no
13368          * effect.
13369          */
13370         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13371             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13372             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13373                 goto out;
13374
13375 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13376         goal = BOUNDARY_MULTI_CACHELINE;
13377 #else
13378 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13379         goal = BOUNDARY_SINGLE_CACHELINE;
13380 #else
13381         goal = 0;
13382 #endif
13383 #endif
13384
13385         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13386                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13387                 goto out;
13388         }
13389
13390         if (!goal)
13391                 goto out;
13392
13393         /* PCI controllers on most RISC systems tend to disconnect
13394          * when a device tries to burst across a cache-line boundary.
13395          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13396          *
13397          * Unfortunately, for PCI-E there are only limited
13398          * write-side controls for this, and thus for reads
13399          * we will still get the disconnects.  We'll also waste
13400          * these PCI cycles for both read and write for chips
13401          * other than 5700 and 5701 which do not implement the
13402          * boundary bits.
13403          */
13404         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13405             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13406                 switch (cacheline_size) {
13407                 case 16:
13408                 case 32:
13409                 case 64:
13410                 case 128:
13411                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13412                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13413                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13414                         } else {
13415                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13416                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13417                         }
13418                         break;
13419
13420                 case 256:
13421                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13422                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13423                         break;
13424
13425                 default:
13426                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13427                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13428                         break;
13429                 }
13430         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13431                 switch (cacheline_size) {
13432                 case 16:
13433                 case 32:
13434                 case 64:
13435                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13436                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13437                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13438                                 break;
13439                         }
13440                         /* fallthrough */
13441                 case 128:
13442                 default:
13443                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13444                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13445                         break;
13446                 }
13447         } else {
13448                 switch (cacheline_size) {
13449                 case 16:
13450                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13451                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13452                                         DMA_RWCTRL_WRITE_BNDRY_16);
13453                                 break;
13454                         }
13455                         /* fallthrough */
13456                 case 32:
13457                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13458                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13459                                         DMA_RWCTRL_WRITE_BNDRY_32);
13460                                 break;
13461                         }
13462                         /* fallthrough */
13463                 case 64:
13464                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13465                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13466                                         DMA_RWCTRL_WRITE_BNDRY_64);
13467                                 break;
13468                         }
13469                         /* fallthrough */
13470                 case 128:
13471                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13472                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13473                                         DMA_RWCTRL_WRITE_BNDRY_128);
13474                                 break;
13475                         }
13476                         /* fallthrough */
13477                 case 256:
13478                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13479                                 DMA_RWCTRL_WRITE_BNDRY_256);
13480                         break;
13481                 case 512:
13482                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13483                                 DMA_RWCTRL_WRITE_BNDRY_512);
13484                         break;
13485                 case 1024:
13486                 default:
13487                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13488                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13489                         break;
13490                 }
13491         }
13492
13493 out:
13494         return val;
13495 }
13496
13497 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13498 {
13499         struct tg3_internal_buffer_desc test_desc;
13500         u32 sram_dma_descs;
13501         int i, ret;
13502
13503         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13504
13505         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13506         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13507         tw32(RDMAC_STATUS, 0);
13508         tw32(WDMAC_STATUS, 0);
13509
13510         tw32(BUFMGR_MODE, 0);
13511         tw32(FTQ_RESET, 0);
13512
13513         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13514         test_desc.addr_lo = buf_dma & 0xffffffff;
13515         test_desc.nic_mbuf = 0x00002100;
13516         test_desc.len = size;
13517
13518         /*
13519          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13520          * the *second* time the tg3 driver was getting loaded after an
13521          * initial scan.
13522          *
13523          * Broadcom tells me:
13524          *   ...the DMA engine is connected to the GRC block and a DMA
13525          *   reset may affect the GRC block in some unpredictable way...
13526          *   The behavior of resets to individual blocks has not been tested.
13527          *
13528          * Broadcom noted the GRC reset will also reset all sub-components.
13529          */
13530         if (to_device) {
13531                 test_desc.cqid_sqid = (13 << 8) | 2;
13532
13533                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13534                 udelay(40);
13535         } else {
13536                 test_desc.cqid_sqid = (16 << 8) | 7;
13537
13538                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13539                 udelay(40);
13540         }
13541         test_desc.flags = 0x00000005;
13542
13543         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13544                 u32 val;
13545
13546                 val = *(((u32 *)&test_desc) + i);
13547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13548                                        sram_dma_descs + (i * sizeof(u32)));
13549                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13550         }
13551         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13552
13553         if (to_device) {
13554                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13555         } else {
13556                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13557         }
13558
13559         ret = -ENODEV;
13560         for (i = 0; i < 40; i++) {
13561                 u32 val;
13562
13563                 if (to_device)
13564                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13565                 else
13566                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13567                 if ((val & 0xffff) == sram_dma_descs) {
13568                         ret = 0;
13569                         break;
13570                 }
13571
13572                 udelay(100);
13573         }
13574
13575         return ret;
13576 }
13577
13578 #define TEST_BUFFER_SIZE        0x2000
13579
13580 static int __devinit tg3_test_dma(struct tg3 *tp)
13581 {
13582         dma_addr_t buf_dma;
13583         u32 *buf, saved_dma_rwctrl;
13584         int ret = 0;
13585
13586         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13587         if (!buf) {
13588                 ret = -ENOMEM;
13589                 goto out_nofree;
13590         }
13591
13592         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13593                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13594
13595         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13596
13597         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13598                 goto out;
13599
13600         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13601                 /* DMA read watermark not used on PCIE */
13602                 tp->dma_rwctrl |= 0x00180000;
13603         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13604                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13605                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13606                         tp->dma_rwctrl |= 0x003f0000;
13607                 else
13608                         tp->dma_rwctrl |= 0x003f000f;
13609         } else {
13610                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13611                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13612                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13613                         u32 read_water = 0x7;
13614
13615                         /* If the 5704 is behind the EPB bridge, we can
13616                          * do the less restrictive ONE_DMA workaround for
13617                          * better performance.
13618                          */
13619                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13620                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13621                                 tp->dma_rwctrl |= 0x8000;
13622                         else if (ccval == 0x6 || ccval == 0x7)
13623                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13624
13625                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13626                                 read_water = 4;
13627                         /* Set bit 23 to enable PCIX hw bug fix */
13628                         tp->dma_rwctrl |=
13629                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13630                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13631                                 (1 << 23);
13632                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13633                         /* 5780 always in PCIX mode */
13634                         tp->dma_rwctrl |= 0x00144000;
13635                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13636                         /* 5714 always in PCIX mode */
13637                         tp->dma_rwctrl |= 0x00148000;
13638                 } else {
13639                         tp->dma_rwctrl |= 0x001b000f;
13640                 }
13641         }
13642
13643         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13644             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13645                 tp->dma_rwctrl &= 0xfffffff0;
13646
13647         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13648             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13649                 /* Remove this if it causes problems for some boards. */
13650                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13651
13652                 /* On 5700/5701 chips, we need to set this bit.
13653                  * Otherwise the chip will issue cacheline transactions
13654                  * to streamable DMA memory with not all the byte
13655                  * enables turned on.  This is an error on several
13656                  * RISC PCI controllers, in particular sparc64.
13657                  *
13658                  * On 5703/5704 chips, this bit has been reassigned
13659                  * a different meaning.  In particular, it is used
13660                  * on those chips to enable a PCI-X workaround.
13661                  */
13662                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13663         }
13664
13665         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13666
13667 #if 0
13668         /* Unneeded, already done by tg3_get_invariants.  */
13669         tg3_switch_clocks(tp);
13670 #endif
13671
13672         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13673             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13674                 goto out;
13675
13676         /* It is best to perform DMA test with maximum write burst size
13677          * to expose the 5700/5701 write DMA bug.
13678          */
13679         saved_dma_rwctrl = tp->dma_rwctrl;
13680         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13681         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13682
13683         while (1) {
13684                 u32 *p = buf, i;
13685
13686                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13687                         p[i] = i;
13688
13689                 /* Send the buffer to the chip. */
13690                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13691                 if (ret) {
13692                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13693                         break;
13694                 }
13695
13696 #if 0
13697                 /* validate data reached card RAM correctly. */
13698                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13699                         u32 val;
13700                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13701                         if (le32_to_cpu(val) != p[i]) {
13702                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13703                                 /* ret = -ENODEV here? */
13704                         }
13705                         p[i] = 0;
13706                 }
13707 #endif
13708                 /* Now read it back. */
13709                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13710                 if (ret) {
13711                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13712
13713                         break;
13714                 }
13715
13716                 /* Verify it. */
13717                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13718                         if (p[i] == i)
13719                                 continue;
13720
13721                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13722                             DMA_RWCTRL_WRITE_BNDRY_16) {
13723                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13724                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13725                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13726                                 break;
13727                         } else {
13728                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13729                                 ret = -ENODEV;
13730                                 goto out;
13731                         }
13732                 }
13733
13734                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13735                         /* Success. */
13736                         ret = 0;
13737                         break;
13738                 }
13739         }
13740         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13741             DMA_RWCTRL_WRITE_BNDRY_16) {
13742                 static struct pci_device_id dma_wait_state_chipsets[] = {
13743                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13744                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13745                         { },
13746                 };
13747
13748                 /* DMA test passed without adjusting DMA boundary,
13749                  * now look for chipsets that are known to expose the
13750                  * DMA bug without failing the test.
13751                  */
13752                 if (pci_dev_present(dma_wait_state_chipsets)) {
13753                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13754                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13755                 }
13756                 else
13757                         /* Safe to use the calculated DMA boundary. */
13758                         tp->dma_rwctrl = saved_dma_rwctrl;
13759
13760                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13761         }
13762
13763 out:
13764         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13765 out_nofree:
13766         return ret;
13767 }
13768
13769 static void __devinit tg3_init_link_config(struct tg3 *tp)
13770 {
13771         tp->link_config.advertising =
13772                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13773                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13774                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13775                  ADVERTISED_Autoneg | ADVERTISED_MII);
13776         tp->link_config.speed = SPEED_INVALID;
13777         tp->link_config.duplex = DUPLEX_INVALID;
13778         tp->link_config.autoneg = AUTONEG_ENABLE;
13779         tp->link_config.active_speed = SPEED_INVALID;
13780         tp->link_config.active_duplex = DUPLEX_INVALID;
13781         tp->link_config.phy_is_low_power = 0;
13782         tp->link_config.orig_speed = SPEED_INVALID;
13783         tp->link_config.orig_duplex = DUPLEX_INVALID;
13784         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13785 }
13786
13787 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13788 {
13789         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13790             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13791                 tp->bufmgr_config.mbuf_read_dma_low_water =
13792                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13793                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13794                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13795                 tp->bufmgr_config.mbuf_high_water =
13796                         DEFAULT_MB_HIGH_WATER_5705;
13797                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13798                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13799                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13800                         tp->bufmgr_config.mbuf_high_water =
13801                                 DEFAULT_MB_HIGH_WATER_5906;
13802                 }
13803
13804                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13805                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13806                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13807                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13808                 tp->bufmgr_config.mbuf_high_water_jumbo =
13809                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13810         } else {
13811                 tp->bufmgr_config.mbuf_read_dma_low_water =
13812                         DEFAULT_MB_RDMA_LOW_WATER;
13813                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13814                         DEFAULT_MB_MACRX_LOW_WATER;
13815                 tp->bufmgr_config.mbuf_high_water =
13816                         DEFAULT_MB_HIGH_WATER;
13817
13818                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13819                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13820                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13821                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13822                 tp->bufmgr_config.mbuf_high_water_jumbo =
13823                         DEFAULT_MB_HIGH_WATER_JUMBO;
13824         }
13825
13826         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13827         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13828 }
13829
13830 static char * __devinit tg3_phy_string(struct tg3 *tp)
13831 {
13832         switch (tp->phy_id & PHY_ID_MASK) {
13833         case PHY_ID_BCM5400:    return "5400";
13834         case PHY_ID_BCM5401:    return "5401";
13835         case PHY_ID_BCM5411:    return "5411";
13836         case PHY_ID_BCM5701:    return "5701";
13837         case PHY_ID_BCM5703:    return "5703";
13838         case PHY_ID_BCM5704:    return "5704";
13839         case PHY_ID_BCM5705:    return "5705";
13840         case PHY_ID_BCM5750:    return "5750";
13841         case PHY_ID_BCM5752:    return "5752";
13842         case PHY_ID_BCM5714:    return "5714";
13843         case PHY_ID_BCM5780:    return "5780";
13844         case PHY_ID_BCM5755:    return "5755";
13845         case PHY_ID_BCM5787:    return "5787";
13846         case PHY_ID_BCM5784:    return "5784";
13847         case PHY_ID_BCM5756:    return "5722/5756";
13848         case PHY_ID_BCM5906:    return "5906";
13849         case PHY_ID_BCM5761:    return "5761";
13850         case PHY_ID_BCM5717:    return "5717";
13851         case PHY_ID_BCM8002:    return "8002/serdes";
13852         case 0:                 return "serdes";
13853         default:                return "unknown";
13854         }
13855 }
13856
13857 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13858 {
13859         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13860                 strcpy(str, "PCI Express");
13861                 return str;
13862         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13863                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13864
13865                 strcpy(str, "PCIX:");
13866
13867                 if ((clock_ctrl == 7) ||
13868                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13869                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13870                         strcat(str, "133MHz");
13871                 else if (clock_ctrl == 0)
13872                         strcat(str, "33MHz");
13873                 else if (clock_ctrl == 2)
13874                         strcat(str, "50MHz");
13875                 else if (clock_ctrl == 4)
13876                         strcat(str, "66MHz");
13877                 else if (clock_ctrl == 6)
13878                         strcat(str, "100MHz");
13879         } else {
13880                 strcpy(str, "PCI:");
13881                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13882                         strcat(str, "66MHz");
13883                 else
13884                         strcat(str, "33MHz");
13885         }
13886         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13887                 strcat(str, ":32-bit");
13888         else
13889                 strcat(str, ":64-bit");
13890         return str;
13891 }
13892
13893 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13894 {
13895         struct pci_dev *peer;
13896         unsigned int func, devnr = tp->pdev->devfn & ~7;
13897
13898         for (func = 0; func < 8; func++) {
13899                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13900                 if (peer && peer != tp->pdev)
13901                         break;
13902                 pci_dev_put(peer);
13903         }
13904         /* 5704 can be configured in single-port mode, set peer to
13905          * tp->pdev in that case.
13906          */
13907         if (!peer) {
13908                 peer = tp->pdev;
13909                 return peer;
13910         }
13911
13912         /*
13913          * We don't need to keep the refcount elevated; there's no way
13914          * to remove one half of this device without removing the other
13915          */
13916         pci_dev_put(peer);
13917
13918         return peer;
13919 }
13920
13921 static void __devinit tg3_init_coal(struct tg3 *tp)
13922 {
13923         struct ethtool_coalesce *ec = &tp->coal;
13924
13925         memset(ec, 0, sizeof(*ec));
13926         ec->cmd = ETHTOOL_GCOALESCE;
13927         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13928         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13929         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13930         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13931         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13932         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13933         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13934         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13935         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13936
13937         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13938                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13939                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13940                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13941                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13942                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13943         }
13944
13945         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13946                 ec->rx_coalesce_usecs_irq = 0;
13947                 ec->tx_coalesce_usecs_irq = 0;
13948                 ec->stats_block_coalesce_usecs = 0;
13949         }
13950 }
13951
13952 static const struct net_device_ops tg3_netdev_ops = {
13953         .ndo_open               = tg3_open,
13954         .ndo_stop               = tg3_close,
13955         .ndo_start_xmit         = tg3_start_xmit,
13956         .ndo_get_stats          = tg3_get_stats,
13957         .ndo_validate_addr      = eth_validate_addr,
13958         .ndo_set_multicast_list = tg3_set_rx_mode,
13959         .ndo_set_mac_address    = tg3_set_mac_addr,
13960         .ndo_do_ioctl           = tg3_ioctl,
13961         .ndo_tx_timeout         = tg3_tx_timeout,
13962         .ndo_change_mtu         = tg3_change_mtu,
13963 #if TG3_VLAN_TAG_USED
13964         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13965 #endif
13966 #ifdef CONFIG_NET_POLL_CONTROLLER
13967         .ndo_poll_controller    = tg3_poll_controller,
13968 #endif
13969 };
13970
13971 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13972         .ndo_open               = tg3_open,
13973         .ndo_stop               = tg3_close,
13974         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13975         .ndo_get_stats          = tg3_get_stats,
13976         .ndo_validate_addr      = eth_validate_addr,
13977         .ndo_set_multicast_list = tg3_set_rx_mode,
13978         .ndo_set_mac_address    = tg3_set_mac_addr,
13979         .ndo_do_ioctl           = tg3_ioctl,
13980         .ndo_tx_timeout         = tg3_tx_timeout,
13981         .ndo_change_mtu         = tg3_change_mtu,
13982 #if TG3_VLAN_TAG_USED
13983         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13984 #endif
13985 #ifdef CONFIG_NET_POLL_CONTROLLER
13986         .ndo_poll_controller    = tg3_poll_controller,
13987 #endif
13988 };
13989
13990 static int __devinit tg3_init_one(struct pci_dev *pdev,
13991                                   const struct pci_device_id *ent)
13992 {
13993         static int tg3_version_printed = 0;
13994         struct net_device *dev;
13995         struct tg3 *tp;
13996         int i, err, pm_cap;
13997         u32 sndmbx, rcvmbx, intmbx;
13998         char str[40];
13999         u64 dma_mask, persist_dma_mask;
14000
14001         if (tg3_version_printed++ == 0)
14002                 printk(KERN_INFO "%s", version);
14003
14004         err = pci_enable_device(pdev);
14005         if (err) {
14006                 printk(KERN_ERR PFX "Cannot enable PCI device, "
14007                        "aborting.\n");
14008                 return err;
14009         }
14010
14011         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14012         if (err) {
14013                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14014                        "aborting.\n");
14015                 goto err_out_disable_pdev;
14016         }
14017
14018         pci_set_master(pdev);
14019
14020         /* Find power-management capability. */
14021         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14022         if (pm_cap == 0) {
14023                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14024                        "aborting.\n");
14025                 err = -EIO;
14026                 goto err_out_free_res;
14027         }
14028
14029         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14030         if (!dev) {
14031                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14032                 err = -ENOMEM;
14033                 goto err_out_free_res;
14034         }
14035
14036         SET_NETDEV_DEV(dev, &pdev->dev);
14037
14038 #if TG3_VLAN_TAG_USED
14039         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14040 #endif
14041
14042         tp = netdev_priv(dev);
14043         tp->pdev = pdev;
14044         tp->dev = dev;
14045         tp->pm_cap = pm_cap;
14046         tp->rx_mode = TG3_DEF_RX_MODE;
14047         tp->tx_mode = TG3_DEF_TX_MODE;
14048
14049         if (tg3_debug > 0)
14050                 tp->msg_enable = tg3_debug;
14051         else
14052                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14053
14054         /* The word/byte swap controls here control register access byte
14055          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14056          * setting below.
14057          */
14058         tp->misc_host_ctrl =
14059                 MISC_HOST_CTRL_MASK_PCI_INT |
14060                 MISC_HOST_CTRL_WORD_SWAP |
14061                 MISC_HOST_CTRL_INDIR_ACCESS |
14062                 MISC_HOST_CTRL_PCISTATE_RW;
14063
14064         /* The NONFRM (non-frame) byte/word swap controls take effect
14065          * on descriptor entries, anything which isn't packet data.
14066          *
14067          * The StrongARM chips on the board (one for tx, one for rx)
14068          * are running in big-endian mode.
14069          */
14070         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14071                         GRC_MODE_WSWAP_NONFRM_DATA);
14072 #ifdef __BIG_ENDIAN
14073         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14074 #endif
14075         spin_lock_init(&tp->lock);
14076         spin_lock_init(&tp->indirect_lock);
14077         INIT_WORK(&tp->reset_task, tg3_reset_task);
14078
14079         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14080         if (!tp->regs) {
14081                 printk(KERN_ERR PFX "Cannot map device registers, "
14082                        "aborting.\n");
14083                 err = -ENOMEM;
14084                 goto err_out_free_dev;
14085         }
14086
14087         tg3_init_link_config(tp);
14088
14089         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14090         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14091
14092         dev->ethtool_ops = &tg3_ethtool_ops;
14093         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14094         dev->irq = pdev->irq;
14095
14096         err = tg3_get_invariants(tp);
14097         if (err) {
14098                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14099                        "aborting.\n");
14100                 goto err_out_iounmap;
14101         }
14102
14103         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14104             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14105                 dev->netdev_ops = &tg3_netdev_ops;
14106         else
14107                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14108
14109
14110         /* The EPB bridge inside 5714, 5715, and 5780 and any
14111          * device behind the EPB cannot support DMA addresses > 40-bit.
14112          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14113          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14114          * do DMA address check in tg3_start_xmit().
14115          */
14116         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14117                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14118         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14119                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14120 #ifdef CONFIG_HIGHMEM
14121                 dma_mask = DMA_BIT_MASK(64);
14122 #endif
14123         } else
14124                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14125
14126         /* Configure DMA attributes. */
14127         if (dma_mask > DMA_BIT_MASK(32)) {
14128                 err = pci_set_dma_mask(pdev, dma_mask);
14129                 if (!err) {
14130                         dev->features |= NETIF_F_HIGHDMA;
14131                         err = pci_set_consistent_dma_mask(pdev,
14132                                                           persist_dma_mask);
14133                         if (err < 0) {
14134                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14135                                        "DMA for consistent allocations\n");
14136                                 goto err_out_iounmap;
14137                         }
14138                 }
14139         }
14140         if (err || dma_mask == DMA_BIT_MASK(32)) {
14141                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14142                 if (err) {
14143                         printk(KERN_ERR PFX "No usable DMA configuration, "
14144                                "aborting.\n");
14145                         goto err_out_iounmap;
14146                 }
14147         }
14148
14149         tg3_init_bufmgr_config(tp);
14150
14151         /* Selectively allow TSO based on operating conditions */
14152         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14153             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14154                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14155         else {
14156                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14157                 tp->fw_needed = NULL;
14158         }
14159
14160         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14161                 tp->fw_needed = FIRMWARE_TG3;
14162
14163         /* TSO is on by default on chips that support hardware TSO.
14164          * Firmware TSO on older chips gives lower performance, so it
14165          * is off by default, but can be enabled using ethtool.
14166          */
14167         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14168             (dev->features & NETIF_F_IP_CSUM))
14169                 dev->features |= NETIF_F_TSO;
14170
14171         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14172             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14173                 if (dev->features & NETIF_F_IPV6_CSUM)
14174                         dev->features |= NETIF_F_TSO6;
14175                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14176                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14177                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14178                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14179                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14180                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14181                         dev->features |= NETIF_F_TSO_ECN;
14182         }
14183
14184         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14185             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14186             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14187                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14188                 tp->rx_pending = 63;
14189         }
14190
14191         err = tg3_get_device_address(tp);
14192         if (err) {
14193                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14194                        "aborting.\n");
14195                 goto err_out_fw;
14196         }
14197
14198         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14199                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14200                 if (!tp->aperegs) {
14201                         printk(KERN_ERR PFX "Cannot map APE registers, "
14202                                "aborting.\n");
14203                         err = -ENOMEM;
14204                         goto err_out_fw;
14205                 }
14206
14207                 tg3_ape_lock_init(tp);
14208
14209                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14210                         tg3_read_dash_ver(tp);
14211         }
14212
14213         /*
14214          * Reset chip in case UNDI or EFI driver did not shutdown
14215          * DMA self test will enable WDMAC and we'll see (spurious)
14216          * pending DMA on the PCI bus at that point.
14217          */
14218         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14219             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14220                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14221                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14222         }
14223
14224         err = tg3_test_dma(tp);
14225         if (err) {
14226                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14227                 goto err_out_apeunmap;
14228         }
14229
14230         /* flow control autonegotiation is default behavior */
14231         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14232         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14233
14234         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14235         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14236         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14237         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14238                 struct tg3_napi *tnapi = &tp->napi[i];
14239
14240                 tnapi->tp = tp;
14241                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14242
14243                 tnapi->int_mbox = intmbx;
14244                 if (i < 4)
14245                         intmbx += 0x8;
14246                 else
14247                         intmbx += 0x4;
14248
14249                 tnapi->consmbox = rcvmbx;
14250                 tnapi->prodmbox = sndmbx;
14251
14252                 if (i) {
14253                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14254                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14255                 } else {
14256                         tnapi->coal_now = HOSTCC_MODE_NOW;
14257                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14258                 }
14259
14260                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14261                         break;
14262
14263                 /*
14264                  * If we support MSIX, we'll be using RSS.  If we're using
14265                  * RSS, the first vector only handles link interrupts and the
14266                  * remaining vectors handle rx and tx interrupts.  Reuse the
14267                  * mailbox values for the next iteration.  The values we setup
14268                  * above are still useful for the single vectored mode.
14269                  */
14270                 if (!i)
14271                         continue;
14272
14273                 rcvmbx += 0x8;
14274
14275                 if (sndmbx & 0x4)
14276                         sndmbx -= 0x4;
14277                 else
14278                         sndmbx += 0xc;
14279         }
14280
14281         tg3_init_coal(tp);
14282
14283         pci_set_drvdata(pdev, dev);
14284
14285         err = register_netdev(dev);
14286         if (err) {
14287                 printk(KERN_ERR PFX "Cannot register net device, "
14288                        "aborting.\n");
14289                 goto err_out_apeunmap;
14290         }
14291
14292         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14293                dev->name,
14294                tp->board_part_number,
14295                tp->pci_chip_rev_id,
14296                tg3_bus_string(tp, str),
14297                dev->dev_addr);
14298
14299         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14300                 struct phy_device *phydev;
14301                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14302                 printk(KERN_INFO
14303                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14304                        tp->dev->name, phydev->drv->name,
14305                        dev_name(&phydev->dev));
14306         } else
14307                 printk(KERN_INFO
14308                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14309                        tp->dev->name, tg3_phy_string(tp),
14310                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14311                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14312                          "10/100/1000Base-T")),
14313                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14314
14315         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14316                dev->name,
14317                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14318                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14319                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14320                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14321                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14322         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14323                dev->name, tp->dma_rwctrl,
14324                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14325                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14326
14327         return 0;
14328
14329 err_out_apeunmap:
14330         if (tp->aperegs) {
14331                 iounmap(tp->aperegs);
14332                 tp->aperegs = NULL;
14333         }
14334
14335 err_out_fw:
14336         if (tp->fw)
14337                 release_firmware(tp->fw);
14338
14339 err_out_iounmap:
14340         if (tp->regs) {
14341                 iounmap(tp->regs);
14342                 tp->regs = NULL;
14343         }
14344
14345 err_out_free_dev:
14346         free_netdev(dev);
14347
14348 err_out_free_res:
14349         pci_release_regions(pdev);
14350
14351 err_out_disable_pdev:
14352         pci_disable_device(pdev);
14353         pci_set_drvdata(pdev, NULL);
14354         return err;
14355 }
14356
14357 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14358 {
14359         struct net_device *dev = pci_get_drvdata(pdev);
14360
14361         if (dev) {
14362                 struct tg3 *tp = netdev_priv(dev);
14363
14364                 if (tp->fw)
14365                         release_firmware(tp->fw);
14366
14367                 flush_scheduled_work();
14368
14369                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14370                         tg3_phy_fini(tp);
14371                         tg3_mdio_fini(tp);
14372                 }
14373
14374                 unregister_netdev(dev);
14375                 if (tp->aperegs) {
14376                         iounmap(tp->aperegs);
14377                         tp->aperegs = NULL;
14378                 }
14379                 if (tp->regs) {
14380                         iounmap(tp->regs);
14381                         tp->regs = NULL;
14382                 }
14383                 free_netdev(dev);
14384                 pci_release_regions(pdev);
14385                 pci_disable_device(pdev);
14386                 pci_set_drvdata(pdev, NULL);
14387         }
14388 }
14389
14390 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14391 {
14392         struct net_device *dev = pci_get_drvdata(pdev);
14393         struct tg3 *tp = netdev_priv(dev);
14394         pci_power_t target_state;
14395         int err;
14396
14397         /* PCI register 4 needs to be saved whether netif_running() or not.
14398          * MSI address and data need to be saved if using MSI and
14399          * netif_running().
14400          */
14401         pci_save_state(pdev);
14402
14403         if (!netif_running(dev))
14404                 return 0;
14405
14406         flush_scheduled_work();
14407         tg3_phy_stop(tp);
14408         tg3_netif_stop(tp);
14409
14410         del_timer_sync(&tp->timer);
14411
14412         tg3_full_lock(tp, 1);
14413         tg3_disable_ints(tp);
14414         tg3_full_unlock(tp);
14415
14416         netif_device_detach(dev);
14417
14418         tg3_full_lock(tp, 0);
14419         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14420         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14421         tg3_full_unlock(tp);
14422
14423         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14424
14425         err = tg3_set_power_state(tp, target_state);
14426         if (err) {
14427                 int err2;
14428
14429                 tg3_full_lock(tp, 0);
14430
14431                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14432                 err2 = tg3_restart_hw(tp, 1);
14433                 if (err2)
14434                         goto out;
14435
14436                 tp->timer.expires = jiffies + tp->timer_offset;
14437                 add_timer(&tp->timer);
14438
14439                 netif_device_attach(dev);
14440                 tg3_netif_start(tp);
14441
14442 out:
14443                 tg3_full_unlock(tp);
14444
14445                 if (!err2)
14446                         tg3_phy_start(tp);
14447         }
14448
14449         return err;
14450 }
14451
14452 static int tg3_resume(struct pci_dev *pdev)
14453 {
14454         struct net_device *dev = pci_get_drvdata(pdev);
14455         struct tg3 *tp = netdev_priv(dev);
14456         int err;
14457
14458         pci_restore_state(tp->pdev);
14459
14460         if (!netif_running(dev))
14461                 return 0;
14462
14463         err = tg3_set_power_state(tp, PCI_D0);
14464         if (err)
14465                 return err;
14466
14467         netif_device_attach(dev);
14468
14469         tg3_full_lock(tp, 0);
14470
14471         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14472         err = tg3_restart_hw(tp, 1);
14473         if (err)
14474                 goto out;
14475
14476         tp->timer.expires = jiffies + tp->timer_offset;
14477         add_timer(&tp->timer);
14478
14479         tg3_netif_start(tp);
14480
14481 out:
14482         tg3_full_unlock(tp);
14483
14484         if (!err)
14485                 tg3_phy_start(tp);
14486
14487         return err;
14488 }
14489
14490 static struct pci_driver tg3_driver = {
14491         .name           = DRV_MODULE_NAME,
14492         .id_table       = tg3_pci_tbl,
14493         .probe          = tg3_init_one,
14494         .remove         = __devexit_p(tg3_remove_one),
14495         .suspend        = tg3_suspend,
14496         .resume         = tg3_resume
14497 };
14498
14499 static int __init tg3_init(void)
14500 {
14501         return pci_register_driver(&tg3_driver);
14502 }
14503
14504 static void __exit tg3_cleanup(void)
14505 {
14506         pci_unregister_driver(&tg3_driver);
14507 }
14508
14509 module_init(tg3_init);
14510 module_exit(tg3_cleanup);