drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.102"
  72 #define DRV_MODULE_RELDATE      "September 1, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 /* minimum number of free TX descriptors required to wake up TX process */
 141 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 142
 143 #define TG3_RAW_IP_ALIGN 2
 144
 145 /* number of ETHTOOL_GSTATS u64's */
 146 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 147
 148 #define TG3_NUM_TEST            6
 149
 150 #define FIRMWARE_TG3            "tigon/tg3.bin"
 151 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 152 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 153
 154 static char version[] __devinitdata =
 155         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 156
 157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_MODULE_VERSION);
 161 MODULE_FIRMWARE(FIRMWARE_TG3);
 162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 164
 165 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 166
 167 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 168 module_param(tg3_debug, int, 0);
 169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 170
 171 static struct pci_device_id tg3_pci_tbl[] = {
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 245         {}
 246 };
 247
 248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 249
 250 static const struct {
 251         const char string[ETH_GSTRING_LEN];
 252 } ethtool_stats_keys[TG3_NUM_STATS] = {
 253         { "rx_octets" },
 254         { "rx_fragments" },
 255         { "rx_ucast_packets" },
 256         { "rx_mcast_packets" },
 257         { "rx_bcast_packets" },
 258         { "rx_fcs_errors" },
 259         { "rx_align_errors" },
 260         { "rx_xon_pause_rcvd" },
 261         { "rx_xoff_pause_rcvd" },
 262         { "rx_mac_ctrl_rcvd" },
 263         { "rx_xoff_entered" },
 264         { "rx_frame_too_long_errors" },
 265         { "rx_jabbers" },
 266         { "rx_undersize_packets" },
 267         { "rx_in_length_errors" },
 268         { "rx_out_length_errors" },
 269         { "rx_64_or_less_octet_packets" },
 270         { "rx_65_to_127_octet_packets" },
 271         { "rx_128_to_255_octet_packets" },
 272         { "rx_256_to_511_octet_packets" },
 273         { "rx_512_to_1023_octet_packets" },
 274         { "rx_1024_to_1522_octet_packets" },
 275         { "rx_1523_to_2047_octet_packets" },
 276         { "rx_2048_to_4095_octet_packets" },
 277         { "rx_4096_to_8191_octet_packets" },
 278         { "rx_8192_to_9022_octet_packets" },
 279
 280         { "tx_octets" },
 281         { "tx_collisions" },
 282
 283         { "tx_xon_sent" },
 284         { "tx_xoff_sent" },
 285         { "tx_flow_control" },
 286         { "tx_mac_errors" },
 287         { "tx_single_collisions" },
 288         { "tx_mult_collisions" },
 289         { "tx_deferred" },
 290         { "tx_excessive_collisions" },
 291         { "tx_late_collisions" },
 292         { "tx_collide_2times" },
 293         { "tx_collide_3times" },
 294         { "tx_collide_4times" },
 295         { "tx_collide_5times" },
 296         { "tx_collide_6times" },
 297         { "tx_collide_7times" },
 298         { "tx_collide_8times" },
 299         { "tx_collide_9times" },
 300         { "tx_collide_10times" },
 301         { "tx_collide_11times" },
 302         { "tx_collide_12times" },
 303         { "tx_collide_13times" },
 304         { "tx_collide_14times" },
 305         { "tx_collide_15times" },
 306         { "tx_ucast_packets" },
 307         { "tx_mcast_packets" },
 308         { "tx_bcast_packets" },
 309         { "tx_carrier_sense_errors" },
 310         { "tx_discards" },
 311         { "tx_errors" },
 312
 313         { "dma_writeq_full" },
 314         { "dma_write_prioq_full" },
 315         { "rxbds_empty" },
 316         { "rx_discards" },
 317         { "rx_errors" },
 318         { "rx_threshold_hit" },
 319
 320         { "dma_readq_full" },
 321         { "dma_read_prioq_full" },
 322         { "tx_comp_queue_full" },
 323
 324         { "ring_set_send_prod_index" },
 325         { "ring_status_update" },
 326         { "nic_irqs" },
 327         { "nic_avoided_irqs" },
 328         { "nic_tx_threshold_hit" }
 329 };
 330
 331 static const struct {
 332         const char string[ETH_GSTRING_LEN];
 333 } ethtool_test_keys[TG3_NUM_TEST] = {
 334         { "nvram test     (online) " },
 335         { "link test      (online) " },
 336         { "register test  (offline)" },
 337         { "memory test    (offline)" },
 338         { "loopback test  (offline)" },
 339         { "interrupt test (offline)" },
 340 };
 341
 342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 343 {
 344         writel(val, tp->regs + off);
 345 }
 346
 347 static u32 tg3_read32(struct tg3 *tp, u32 off)
 348 {
 349         return (readl(tp->regs + off));
 350 }
 351
 352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 353 {
 354         writel(val, tp->aperegs + off);
 355 }
 356
 357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 358 {
 359         return (readl(tp->aperegs + off));
 360 }
 361
 362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 363 {
 364         unsigned long flags;
 365
 366         spin_lock_irqsave(&tp->indirect_lock, flags);
 367         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 368         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 369         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 370 }
 371
 372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         writel(val, tp->regs + off);
 375         readl(tp->regs + off);
 376 }
 377
 378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 379 {
 380         unsigned long flags;
 381         u32 val;
 382
 383         spin_lock_irqsave(&tp->indirect_lock, flags);
 384         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 385         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 386         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 387         return val;
 388 }
 389
 390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 391 {
 392         unsigned long flags;
 393
 394         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 395                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 396                                        TG3_64BIT_REG_LOW, val);
 397                 return;
 398         }
 399         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 400                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 401                                        TG3_64BIT_REG_LOW, val);
 402                 return;
 403         }
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409
 410         /* In indirect mode when disabling interrupts, we also need
 411          * to clear the interrupt bit in the GRC local ctrl register.
 412          */
 413         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 414             (val == 0x1)) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 416                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 417         }
 418 }
 419
 420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 421 {
 422         unsigned long flags;
 423         u32 val;
 424
 425         spin_lock_irqsave(&tp->indirect_lock, flags);
 426         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 427         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 428         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 429         return val;
 430 }
 431
 432 /* usec_wait specifies the wait time in usec when writing to certain registers
 433  * where it is unsafe to read back the register without some delay.
 434  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 435  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 436  */
 437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 438 {
 439         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 440             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 441                 /* Non-posted methods */
 442                 tp->write32(tp, off, val);
 443         else {
 444                 /* Posted method */
 445                 tg3_write32(tp, off, val);
 446                 if (usec_wait)
 447                         udelay(usec_wait);
 448                 tp->read32(tp, off);
 449         }
 450         /* Wait again after the read for the posted method to guarantee that
 451          * the wait time is met.
 452          */
 453         if (usec_wait)
 454                 udelay(usec_wait);
 455 }
 456
 457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 458 {
 459         tp->write32_mbox(tp, off, val);
 460         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 461             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 462                 tp->read32_mbox(tp, off);
 463 }
 464
 465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 466 {
 467         void __iomem *mbox = tp->regs + off;
 468         writel(val, mbox);
 469         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 470                 writel(val, mbox);
 471         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 472                 readl(mbox);
 473 }
 474
 475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 476 {
 477         return (readl(tp->regs + off + GRCMBOX_BASE));
 478 }
 479
 480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         writel(val, tp->regs + off + GRCMBOX_BASE);
 483 }
 484
 485 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 486 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 487 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 488 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 489 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 490
 491 #define tw32(reg,val)           tp->write32(tp, reg, val)
 492 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 494 #define tr32(reg)               tp->read32(tp, reg)
 495
 496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         unsigned long flags;
 499
 500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 501             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 502                 return;
 503
 504         spin_lock_irqsave(&tp->indirect_lock, flags);
 505         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 508
 509                 /* Always leave this as zero. */
 510                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 511         } else {
 512                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 513                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 514
 515                 /* Always leave this as zero. */
 516                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 517         }
 518         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 519 }
 520
 521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 522 {
 523         unsigned long flags;
 524
 525         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 526             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 527                 *val = 0;
 528                 return;
 529         }
 530
 531         spin_lock_irqsave(&tp->indirect_lock, flags);
 532         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 533                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 534                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 535
 536                 /* Always leave this as zero. */
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 538         } else {
 539                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 540                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 541
 542                 /* Always leave this as zero. */
 543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 544         }
 545         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 546 }
 547
 548 static void tg3_ape_lock_init(struct tg3 *tp)
 549 {
 550         int i;
 551
 552         /* Make sure the driver hasn't any stale locks. */
 553         for (i = 0; i < 8; i++)
 554                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 555                                 APE_LOCK_GRANT_DRIVER);
 556 }
 557
 558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 559 {
 560         int i, off;
 561         int ret = 0;
 562         u32 status;
 563
 564         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 565                 return 0;
 566
 567         switch (locknum) {
 568                 case TG3_APE_LOCK_GRC:
 569                 case TG3_APE_LOCK_MEM:
 570                         break;
 571                 default:
 572                         return -EINVAL;
 573         }
 574
 575         off = 4 * locknum;
 576
 577         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 578
 579         /* Wait for up to 1 millisecond to acquire lock. */
 580         for (i = 0; i < 100; i++) {
 581                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 582                 if (status == APE_LOCK_GRANT_DRIVER)
 583                         break;
 584                 udelay(10);
 585         }
 586
 587         if (status != APE_LOCK_GRANT_DRIVER) {
 588                 /* Revoke the lock request. */
 589                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 590                                 APE_LOCK_GRANT_DRIVER);
 591
 592                 ret = -EBUSY;
 593         }
 594
 595         return ret;
 596 }
 597
 598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 599 {
 600         int off;
 601
 602         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 603                 return;
 604
 605         switch (locknum) {
 606                 case TG3_APE_LOCK_GRC:
 607                 case TG3_APE_LOCK_MEM:
 608                         break;
 609                 default:
 610                         return;
 611         }
 612
 613         off = 4 * locknum;
 614         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 615 }
 616
 617 static void tg3_disable_ints(struct tg3 *tp)
 618 {
 619         int i;
 620
 621         tw32(TG3PCI_MISC_HOST_CTRL,
 622              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 623         for (i = 0; i < tp->irq_max; i++)
 624                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 625 }
 626
 627 static void tg3_enable_ints(struct tg3 *tp)
 628 {
 629         int i;
 630         u32 coal_now = 0;
 631
 632         tp->irq_sync = 0;
 633         wmb();
 634
 635         tw32(TG3PCI_MISC_HOST_CTRL,
 636              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 637
 638         for (i = 0; i < tp->irq_cnt; i++) {
 639                 struct tg3_napi *tnapi = &tp->napi[i];
 640                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 641                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 642                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 643
 644                 coal_now |= tnapi->coal_now;
 645         }
 646
 647         /* Force an initial interrupt */
 648         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 649             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 650                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 651         else
 652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 653                      HOSTCC_MODE_ENABLE | coal_now);
 654 }
 655
 656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 657 {
 658         struct tg3 *tp = tnapi->tp;
 659         struct tg3_hw_status *sblk = tnapi->hw_status;
 660         unsigned int work_exists = 0;
 661
 662         /* check for phy events */
 663         if (!(tp->tg3_flags &
 664               (TG3_FLAG_USE_LINKCHG_REG |
 665                TG3_FLAG_POLL_SERDES))) {
 666                 if (sblk->status & SD_STATUS_LINK_CHG)
 667                         work_exists = 1;
 668         }
 669         /* check for RX/TX work to do */
 670         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 671             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 672                 work_exists = 1;
 673
 674         return work_exists;
 675 }
 676
 677 /* tg3_int_reenable
 678  *  similar to tg3_enable_ints, but it accurately determines whether there
 679  *  is new work pending and can return without flushing the PIO write
 680  *  which reenables interrupts
 681  */
 682 static void tg3_int_reenable(struct tg3_napi *tnapi)
 683 {
 684         struct tg3 *tp = tnapi->tp;
 685
 686         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 687         mmiowb();
 688
 689         /* When doing tagged status, this work check is unnecessary.
 690          * The last_tag we write above tells the chip which piece of
 691          * work we've completed.
 692          */
 693         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 694             tg3_has_work(tnapi))
 695                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 696                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 697 }
 698
 699 static void tg3_napi_disable(struct tg3 *tp)
 700 {
 701         int i;
 702
 703         for (i = tp->irq_cnt - 1; i >= 0; i--)
 704                 napi_disable(&tp->napi[i].napi);
 705 }
 706
 707 static void tg3_napi_enable(struct tg3 *tp)
 708 {
 709         int i;
 710
 711         for (i = 0; i < tp->irq_cnt; i++)
 712                 napi_enable(&tp->napi[i].napi);
 713 }
 714
 715 static inline void tg3_netif_stop(struct tg3 *tp)
 716 {
 717         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 718         tg3_napi_disable(tp);
 719         netif_tx_disable(tp->dev);
 720 }
 721
 722 static inline void tg3_netif_start(struct tg3 *tp)
 723 {
 724         /* NOTE: unconditional netif_tx_wake_all_queues is only
 725          * appropriate so long as all callers are assured to
 726          * have free tx slots (such as after tg3_init_hw)
 727          */
 728         netif_tx_wake_all_queues(tp->dev);
 729
 730         tg3_napi_enable(tp);
 731         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 732         tg3_enable_ints(tp);
 733 }
 734
 735 static void tg3_switch_clocks(struct tg3 *tp)
 736 {
 737         u32 clock_ctrl;
 738         u32 orig_clock_ctrl;
 739
 740         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 741             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 742                 return;
 743
 744         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 745
 746         orig_clock_ctrl = clock_ctrl;
 747         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 748                        CLOCK_CTRL_CLKRUN_OENABLE |
 749                        0x1f);
 750         tp->pci_clock_ctrl = clock_ctrl;
 751
 752         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 753                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 754                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 755                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 756                 }
 757         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 758                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 759                             clock_ctrl |
 760                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 761                             40);
 762                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 763                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 764                             40);
 765         }
 766         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 767 }
 768
 769 #define PHY_BUSY_LOOPS  5000
 770
 771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 772 {
 773         u32 frame_val;
 774         unsigned int loops;
 775         int ret;
 776
 777         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 778                 tw32_f(MAC_MI_MODE,
 779                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 780                 udelay(80);
 781         }
 782
 783         *val = 0x0;
 784
 785         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 786                       MI_COM_PHY_ADDR_MASK);
 787         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 788                       MI_COM_REG_ADDR_MASK);
 789         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 790
 791         tw32_f(MAC_MI_COM, frame_val);
 792
 793         loops = PHY_BUSY_LOOPS;
 794         while (loops != 0) {
 795                 udelay(10);
 796                 frame_val = tr32(MAC_MI_COM);
 797
 798                 if ((frame_val & MI_COM_BUSY) == 0) {
 799                         udelay(5);
 800                         frame_val = tr32(MAC_MI_COM);
 801                         break;
 802                 }
 803                 loops -= 1;
 804         }
 805
 806         ret = -EBUSY;
 807         if (loops != 0) {
 808                 *val = frame_val & MI_COM_DATA_MASK;
 809                 ret = 0;
 810         }
 811
 812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 813                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 814                 udelay(80);
 815         }
 816
 817         return ret;
 818 }
 819
 820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 821 {
 822         u32 frame_val;
 823         unsigned int loops;
 824         int ret;
 825
 826         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 827             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 828                 return 0;
 829
 830         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 831                 tw32_f(MAC_MI_MODE,
 832                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 833                 udelay(80);
 834         }
 835
 836         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 837                       MI_COM_PHY_ADDR_MASK);
 838         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 839                       MI_COM_REG_ADDR_MASK);
 840         frame_val |= (val & MI_COM_DATA_MASK);
 841         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 842
 843         tw32_f(MAC_MI_COM, frame_val);
 844
 845         loops = PHY_BUSY_LOOPS;
 846         while (loops != 0) {
 847                 udelay(10);
 848                 frame_val = tr32(MAC_MI_COM);
 849                 if ((frame_val & MI_COM_BUSY) == 0) {
 850                         udelay(5);
 851                         frame_val = tr32(MAC_MI_COM);
 852                         break;
 853                 }
 854                 loops -= 1;
 855         }
 856
 857         ret = -EBUSY;
 858         if (loops != 0)
 859                 ret = 0;
 860
 861         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 862                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 863                 udelay(80);
 864         }
 865
 866         return ret;
 867 }
 868
 869 static int tg3_bmcr_reset(struct tg3 *tp)
 870 {
 871         u32 phy_control;
 872         int limit, err;
 873
 874         /* OK, reset it, and poll the BMCR_RESET bit until it
 875          * clears or we time out.
 876          */
 877         phy_control = BMCR_RESET;
 878         err = tg3_writephy(tp, MII_BMCR, phy_control);
 879         if (err != 0)
 880                 return -EBUSY;
 881
 882         limit = 5000;
 883         while (limit--) {
 884                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 885                 if (err != 0)
 886                         return -EBUSY;
 887
 888                 if ((phy_control & BMCR_RESET) == 0) {
 889                         udelay(40);
 890                         break;
 891                 }
 892                 udelay(10);
 893         }
 894         if (limit < 0)
 895                 return -EBUSY;
 896
 897         return 0;
 898 }
 899
 900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 901 {
 902         struct tg3 *tp = bp->priv;
 903         u32 val;
 904
 905         spin_lock_bh(&tp->lock);
 906
 907         if (tg3_readphy(tp, reg, &val))
 908                 val = -EIO;
 909
 910         spin_unlock_bh(&tp->lock);
 911
 912         return val;
 913 }
 914
 915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 ret = 0;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_writephy(tp, reg, val))
 923                 ret = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return ret;
 928 }
 929
 930 static int tg3_mdio_reset(struct mii_bus *bp)
 931 {
 932         return 0;
 933 }
 934
 935 static void tg3_mdio_config_5785(struct tg3 *tp)
 936 {
 937         u32 val;
 938         struct phy_device *phydev;
 939
 940         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 941         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 942         case TG3_PHY_ID_BCM50610:
 943         case TG3_PHY_ID_BCM50610M:
 944                 val = MAC_PHYCFG2_50610_LED_MODES;
 945                 break;
 946         case TG3_PHY_ID_BCMAC131:
 947                 val = MAC_PHYCFG2_AC131_LED_MODES;
 948                 break;
 949         case TG3_PHY_ID_RTL8211C:
 950                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 951                 break;
 952         case TG3_PHY_ID_RTL8201E:
 953                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 954                 break;
 955         default:
 956                 return;
 957         }
 958
 959         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 960                 tw32(MAC_PHYCFG2, val);
 961
 962                 val = tr32(MAC_PHYCFG1);
 963                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 964                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 965                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 966                 tw32(MAC_PHYCFG1, val);
 967
 968                 return;
 969         }
 970
 971         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 972                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 973                        MAC_PHYCFG2_FMODE_MASK_MASK |
 974                        MAC_PHYCFG2_GMODE_MASK_MASK |
 975                        MAC_PHYCFG2_ACT_MASK_MASK   |
 976                        MAC_PHYCFG2_QUAL_MASK_MASK |
 977                        MAC_PHYCFG2_INBAND_ENABLE;
 978
 979         tw32(MAC_PHYCFG2, val);
 980
 981         val = tr32(MAC_PHYCFG1);
 982         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 983                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 984         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 985                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 986                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 987                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 988                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 989         }
 990         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 991                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 992         tw32(MAC_PHYCFG1, val);
 993
 994         val = tr32(MAC_EXT_RGMII_MODE);
 995         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 996                  MAC_RGMII_MODE_RX_QUALITY |
 997                  MAC_RGMII_MODE_RX_ACTIVITY |
 998                  MAC_RGMII_MODE_RX_ENG_DET |
 999                  MAC_RGMII_MODE_TX_ENABLE |
1000                  MAC_RGMII_MODE_TX_LOWPWR |
1001                  MAC_RGMII_MODE_TX_RESET);
1002         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1003                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004                         val |= MAC_RGMII_MODE_RX_INT_B |
1005                                MAC_RGMII_MODE_RX_QUALITY |
1006                                MAC_RGMII_MODE_RX_ACTIVITY |
1007                                MAC_RGMII_MODE_RX_ENG_DET;
1008                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009                         val |= MAC_RGMII_MODE_TX_ENABLE |
1010                                MAC_RGMII_MODE_TX_LOWPWR |
1011                                MAC_RGMII_MODE_TX_RESET;
1012         }
1013         tw32(MAC_EXT_RGMII_MODE, val);
1014 }
1015
1016 static void tg3_mdio_start(struct tg3 *tp)
1017 {
1018         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019         tw32_f(MAC_MI_MODE, tp->mi_mode);
1020         udelay(80);
1021
1022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023                 u32 funcnum, is_serdes;
1024
1025                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026                 if (funcnum)
1027                         tp->phy_addr = 2;
1028                 else
1029                         tp->phy_addr = 1;
1030
1031                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032                 if (is_serdes)
1033                         tp->phy_addr += 7;
1034         } else
1035                 tp->phy_addr = TG3_PHY_MII_ADDR;
1036
1037         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039                 tg3_mdio_config_5785(tp);
1040 }
1041
1042 static int tg3_mdio_init(struct tg3 *tp)
1043 {
1044         int i;
1045         u32 reg;
1046         struct phy_device *phydev;
1047
1048         tg3_mdio_start(tp);
1049
1050         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052                 return 0;
1053
1054         tp->mdio_bus = mdiobus_alloc();
1055         if (tp->mdio_bus == NULL)
1056                 return -ENOMEM;
1057
1058         tp->mdio_bus->name     = "tg3 mdio bus";
1059         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1060                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1061         tp->mdio_bus->priv     = tp;
1062         tp->mdio_bus->parent   = &tp->pdev->dev;
1063         tp->mdio_bus->read     = &tg3_mdio_read;
1064         tp->mdio_bus->write    = &tg3_mdio_write;
1065         tp->mdio_bus->reset    = &tg3_mdio_reset;
1066         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1067         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1068
1069         for (i = 0; i < PHY_MAX_ADDR; i++)
1070                 tp->mdio_bus->irq[i] = PHY_POLL;
1071
1072         /* The bus registration will look for all the PHYs on the mdio bus.
1073          * Unfortunately, it does not ensure the PHY is powered up before
1074          * accessing the PHY ID registers.  A chip reset is the
1075          * quickest way to bring the device back to an operational state..
1076          */
1077         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078                 tg3_bmcr_reset(tp);
1079
1080         i = mdiobus_register(tp->mdio_bus);
1081         if (i) {
1082                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083                         tp->dev->name, i);
1084                 mdiobus_free(tp->mdio_bus);
1085                 return i;
1086         }
1087
1088         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1089
1090         if (!phydev || !phydev->drv) {
1091                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092                 mdiobus_unregister(tp->mdio_bus);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return -ENODEV;
1095         }
1096
1097         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1098         case TG3_PHY_ID_BCM57780:
1099                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1100                 break;
1101         case TG3_PHY_ID_BCM50610:
1102         case TG3_PHY_ID_BCM50610M:
1103                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE;
1104                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1105                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1106                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1107                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1108                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1109                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1110                 /* fallthru */
1111         case TG3_PHY_ID_RTL8211C:
1112                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1113                 break;
1114         case TG3_PHY_ID_RTL8201E:
1115         case TG3_PHY_ID_BCMAC131:
1116                 phydev->interface = PHY_INTERFACE_MODE_MII;
1117                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1118                 break;
1119         }
1120
1121         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1122
1123         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1124                 tg3_mdio_config_5785(tp);
1125
1126         return 0;
1127 }
1128
1129 static void tg3_mdio_fini(struct tg3 *tp)
1130 {
1131         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1132                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1133                 mdiobus_unregister(tp->mdio_bus);
1134                 mdiobus_free(tp->mdio_bus);
1135         }
1136 }
1137
1138 /* tp->lock is held. */
1139 static inline void tg3_generate_fw_event(struct tg3 *tp)
1140 {
1141         u32 val;
1142
1143         val = tr32(GRC_RX_CPU_EVENT);
1144         val |= GRC_RX_CPU_DRIVER_EVENT;
1145         tw32_f(GRC_RX_CPU_EVENT, val);
1146
1147         tp->last_event_jiffies = jiffies;
1148 }
1149
1150 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1151
1152 /* tp->lock is held. */
1153 static void tg3_wait_for_event_ack(struct tg3 *tp)
1154 {
1155         int i;
1156         unsigned int delay_cnt;
1157         long time_remain;
1158
1159         /* If enough time has passed, no wait is necessary. */
1160         time_remain = (long)(tp->last_event_jiffies + 1 +
1161                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1162                       (long)jiffies;
1163         if (time_remain < 0)
1164                 return;
1165
1166         /* Check if we can shorten the wait time. */
1167         delay_cnt = jiffies_to_usecs(time_remain);
1168         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1169                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1170         delay_cnt = (delay_cnt >> 3) + 1;
1171
1172         for (i = 0; i < delay_cnt; i++) {
1173                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1174                         break;
1175                 udelay(8);
1176         }
1177 }
1178
1179 /* tp->lock is held. */
1180 static void tg3_ump_link_report(struct tg3 *tp)
1181 {
1182         u32 reg;
1183         u32 val;
1184
1185         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1186             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1187                 return;
1188
1189         tg3_wait_for_event_ack(tp);
1190
1191         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1192
1193         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1194
1195         val = 0;
1196         if (!tg3_readphy(tp, MII_BMCR, &reg))
1197                 val = reg << 16;
1198         if (!tg3_readphy(tp, MII_BMSR, &reg))
1199                 val |= (reg & 0xffff);
1200         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1201
1202         val = 0;
1203         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1204                 val = reg << 16;
1205         if (!tg3_readphy(tp, MII_LPA, &reg))
1206                 val |= (reg & 0xffff);
1207         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1208
1209         val = 0;
1210         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1211                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1212                         val = reg << 16;
1213                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1214                         val |= (reg & 0xffff);
1215         }
1216         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1217
1218         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1219                 val = reg << 16;
1220         else
1221                 val = 0;
1222         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1223
1224         tg3_generate_fw_event(tp);
1225 }
1226
1227 static void tg3_link_report(struct tg3 *tp)
1228 {
1229         if (!netif_carrier_ok(tp->dev)) {
1230                 if (netif_msg_link(tp))
1231                         printk(KERN_INFO PFX "%s: Link is down.\n",
1232                                tp->dev->name);
1233                 tg3_ump_link_report(tp);
1234         } else if (netif_msg_link(tp)) {
1235                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1236                        tp->dev->name,
1237                        (tp->link_config.active_speed == SPEED_1000 ?
1238                         1000 :
1239                         (tp->link_config.active_speed == SPEED_100 ?
1240                          100 : 10)),
1241                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1242                         "full" : "half"));
1243
1244                 printk(KERN_INFO PFX
1245                        "%s: Flow control is %s for TX and %s for RX.\n",
1246                        tp->dev->name,
1247                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1248                        "on" : "off",
1249                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1250                        "on" : "off");
1251                 tg3_ump_link_report(tp);
1252         }
1253 }
1254
1255 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1256 {
1257         u16 miireg;
1258
1259         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1260                 miireg = ADVERTISE_PAUSE_CAP;
1261         else if (flow_ctrl & FLOW_CTRL_TX)
1262                 miireg = ADVERTISE_PAUSE_ASYM;
1263         else if (flow_ctrl & FLOW_CTRL_RX)
1264                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1265         else
1266                 miireg = 0;
1267
1268         return miireg;
1269 }
1270
1271 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1272 {
1273         u16 miireg;
1274
1275         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1276                 miireg = ADVERTISE_1000XPAUSE;
1277         else if (flow_ctrl & FLOW_CTRL_TX)
1278                 miireg = ADVERTISE_1000XPSE_ASYM;
1279         else if (flow_ctrl & FLOW_CTRL_RX)
1280                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1281         else
1282                 miireg = 0;
1283
1284         return miireg;
1285 }
1286
1287 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1288 {
1289         u8 cap = 0;
1290
1291         if (lcladv & ADVERTISE_1000XPAUSE) {
1292                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1293                         if (rmtadv & LPA_1000XPAUSE)
1294                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1295                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1296                                 cap = FLOW_CTRL_RX;
1297                 } else {
1298                         if (rmtadv & LPA_1000XPAUSE)
1299                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1300                 }
1301         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1302                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1303                         cap = FLOW_CTRL_TX;
1304         }
1305
1306         return cap;
1307 }
1308
1309 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1310 {
1311         u8 autoneg;
1312         u8 flowctrl = 0;
1313         u32 old_rx_mode = tp->rx_mode;
1314         u32 old_tx_mode = tp->tx_mode;
1315
1316         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1317                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1318         else
1319                 autoneg = tp->link_config.autoneg;
1320
1321         if (autoneg == AUTONEG_ENABLE &&
1322             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1323                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1324                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1325                 else
1326                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1327         } else
1328                 flowctrl = tp->link_config.flowctrl;
1329
1330         tp->link_config.active_flowctrl = flowctrl;
1331
1332         if (flowctrl & FLOW_CTRL_RX)
1333                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1334         else
1335                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1336
1337         if (old_rx_mode != tp->rx_mode)
1338                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1339
1340         if (flowctrl & FLOW_CTRL_TX)
1341                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1342         else
1343                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1344
1345         if (old_tx_mode != tp->tx_mode)
1346                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1347 }
1348
1349 static void tg3_adjust_link(struct net_device *dev)
1350 {
1351         u8 oldflowctrl, linkmesg = 0;
1352         u32 mac_mode, lcl_adv, rmt_adv;
1353         struct tg3 *tp = netdev_priv(dev);
1354         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1355
1356         spin_lock_bh(&tp->lock);
1357
1358         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1359                                     MAC_MODE_HALF_DUPLEX);
1360
1361         oldflowctrl = tp->link_config.active_flowctrl;
1362
1363         if (phydev->link) {
1364                 lcl_adv = 0;
1365                 rmt_adv = 0;
1366
1367                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1368                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1369                 else if (phydev->speed == SPEED_1000 ||
1370                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1371                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1372                 else
1373                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1374
1375                 if (phydev->duplex == DUPLEX_HALF)
1376                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1377                 else {
1378                         lcl_adv = tg3_advert_flowctrl_1000T(
1379                                   tp->link_config.flowctrl);
1380
1381                         if (phydev->pause)
1382                                 rmt_adv = LPA_PAUSE_CAP;
1383                         if (phydev->asym_pause)
1384                                 rmt_adv |= LPA_PAUSE_ASYM;
1385                 }
1386
1387                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1388         } else
1389                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1390
1391         if (mac_mode != tp->mac_mode) {
1392                 tp->mac_mode = mac_mode;
1393                 tw32_f(MAC_MODE, tp->mac_mode);
1394                 udelay(40);
1395         }
1396
1397         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1398                 if (phydev->speed == SPEED_10)
1399                         tw32(MAC_MI_STAT,
1400                              MAC_MI_STAT_10MBPS_MODE |
1401                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1402                 else
1403                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1404         }
1405
1406         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1407                 tw32(MAC_TX_LENGTHS,
1408                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1409                       (6 << TX_LENGTHS_IPG_SHIFT) |
1410                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1411         else
1412                 tw32(MAC_TX_LENGTHS,
1413                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1414                       (6 << TX_LENGTHS_IPG_SHIFT) |
1415                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1416
1417         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1418             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1419             phydev->speed != tp->link_config.active_speed ||
1420             phydev->duplex != tp->link_config.active_duplex ||
1421             oldflowctrl != tp->link_config.active_flowctrl)
1422             linkmesg = 1;
1423
1424         tp->link_config.active_speed = phydev->speed;
1425         tp->link_config.active_duplex = phydev->duplex;
1426
1427         spin_unlock_bh(&tp->lock);
1428
1429         if (linkmesg)
1430                 tg3_link_report(tp);
1431 }
1432
1433 static int tg3_phy_init(struct tg3 *tp)
1434 {
1435         struct phy_device *phydev;
1436
1437         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1438                 return 0;
1439
1440         /* Bring the PHY back to a known state. */
1441         tg3_bmcr_reset(tp);
1442
1443         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1444
1445         /* Attach the MAC to the PHY. */
1446         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1447                              phydev->dev_flags, phydev->interface);
1448         if (IS_ERR(phydev)) {
1449                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1450                 return PTR_ERR(phydev);
1451         }
1452
1453         /* Mask with MAC supported features. */
1454         switch (phydev->interface) {
1455         case PHY_INTERFACE_MODE_GMII:
1456         case PHY_INTERFACE_MODE_RGMII:
1457                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1458                         phydev->supported &= (PHY_GBIT_FEATURES |
1459                                               SUPPORTED_Pause |
1460                                               SUPPORTED_Asym_Pause);
1461                         break;
1462                 }
1463                 /* fallthru */
1464         case PHY_INTERFACE_MODE_MII:
1465                 phydev->supported &= (PHY_BASIC_FEATURES |
1466                                       SUPPORTED_Pause |
1467                                       SUPPORTED_Asym_Pause);
1468                 break;
1469         default:
1470                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1471                 return -EINVAL;
1472         }
1473
1474         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1475
1476         phydev->advertising = phydev->supported;
1477
1478         return 0;
1479 }
1480
1481 static void tg3_phy_start(struct tg3 *tp)
1482 {
1483         struct phy_device *phydev;
1484
1485         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1486                 return;
1487
1488         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1489
1490         if (tp->link_config.phy_is_low_power) {
1491                 tp->link_config.phy_is_low_power = 0;
1492                 phydev->speed = tp->link_config.orig_speed;
1493                 phydev->duplex = tp->link_config.orig_duplex;
1494                 phydev->autoneg = tp->link_config.orig_autoneg;
1495                 phydev->advertising = tp->link_config.orig_advertising;
1496         }
1497
1498         phy_start(phydev);
1499
1500         phy_start_aneg(phydev);
1501 }
1502
1503 static void tg3_phy_stop(struct tg3 *tp)
1504 {
1505         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1506                 return;
1507
1508         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1509 }
1510
1511 static void tg3_phy_fini(struct tg3 *tp)
1512 {
1513         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1514                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1515                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1516         }
1517 }
1518
1519 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1520 {
1521         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1522         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1523 }
1524
1525 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1526 {
1527         u32 phytest;
1528
1529         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1530                 u32 phy;
1531
1532                 tg3_writephy(tp, MII_TG3_FET_TEST,
1533                              phytest | MII_TG3_FET_SHADOW_EN);
1534                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1535                         if (enable)
1536                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1537                         else
1538                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1539                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1540                 }
1541                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1542         }
1543 }
1544
1545 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1546 {
1547         u32 reg;
1548
1549         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1550                 return;
1551
1552         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1553                 tg3_phy_fet_toggle_apd(tp, enable);
1554                 return;
1555         }
1556
1557         reg = MII_TG3_MISC_SHDW_WREN |
1558               MII_TG3_MISC_SHDW_SCR5_SEL |
1559               MII_TG3_MISC_SHDW_SCR5_LPED |
1560               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1561               MII_TG3_MISC_SHDW_SCR5_SDTL |
1562               MII_TG3_MISC_SHDW_SCR5_C125OE;
1563         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1564                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1565
1566         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1567
1568
1569         reg = MII_TG3_MISC_SHDW_WREN |
1570               MII_TG3_MISC_SHDW_APD_SEL |
1571               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1572         if (enable)
1573                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1574
1575         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1576 }
1577
1578 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1579 {
1580         u32 phy;
1581
1582         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1583             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1584                 return;
1585
1586         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1587                 u32 ephy;
1588
1589                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1590                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1591
1592                         tg3_writephy(tp, MII_TG3_FET_TEST,
1593                                      ephy | MII_TG3_FET_SHADOW_EN);
1594                         if (!tg3_readphy(tp, reg, &phy)) {
1595                                 if (enable)
1596                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1597                                 else
1598                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1599                                 tg3_writephy(tp, reg, phy);
1600                         }
1601                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1602                 }
1603         } else {
1604                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1605                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1606                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1607                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1608                         if (enable)
1609                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1610                         else
1611                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1612                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1613                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1614                 }
1615         }
1616 }
1617
1618 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1619 {
1620         u32 val;
1621
1622         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1623                 return;
1624
1625         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1626             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1627                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1628                              (val | (1 << 15) | (1 << 4)));
1629 }
1630
1631 static void tg3_phy_apply_otp(struct tg3 *tp)
1632 {
1633         u32 otp, phy;
1634
1635         if (!tp->phy_otp)
1636                 return;
1637
1638         otp = tp->phy_otp;
1639
1640         /* Enable SM_DSP clock and tx 6dB coding. */
1641         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1642               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1643               MII_TG3_AUXCTL_ACTL_TX_6DB;
1644         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1645
1646         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1647         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1648         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1649
1650         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1651               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1652         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1653
1654         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1655         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1656         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1657
1658         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1659         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1660
1661         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1662         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1663
1664         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1665               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1666         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1667
1668         /* Turn off SM_DSP clock. */
1669         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1670               MII_TG3_AUXCTL_ACTL_TX_6DB;
1671         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1672 }
1673
1674 static int tg3_wait_macro_done(struct tg3 *tp)
1675 {
1676         int limit = 100;
1677
1678         while (limit--) {
1679                 u32 tmp32;
1680
1681                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1682                         if ((tmp32 & 0x1000) == 0)
1683                                 break;
1684                 }
1685         }
1686         if (limit < 0)
1687                 return -EBUSY;
1688
1689         return 0;
1690 }
1691
1692 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1693 {
1694         static const u32 test_pat[4][6] = {
1695         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1696         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1697         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1698         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1699         };
1700         int chan;
1701
1702         for (chan = 0; chan < 4; chan++) {
1703                 int i;
1704
1705                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1706                              (chan * 0x2000) | 0x0200);
1707                 tg3_writephy(tp, 0x16, 0x0002);
1708
1709                 for (i = 0; i < 6; i++)
1710                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1711                                      test_pat[chan][i]);
1712
1713                 tg3_writephy(tp, 0x16, 0x0202);
1714                 if (tg3_wait_macro_done(tp)) {
1715                         *resetp = 1;
1716                         return -EBUSY;
1717                 }
1718
1719                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720                              (chan * 0x2000) | 0x0200);
1721                 tg3_writephy(tp, 0x16, 0x0082);
1722                 if (tg3_wait_macro_done(tp)) {
1723                         *resetp = 1;
1724                         return -EBUSY;
1725                 }
1726
1727                 tg3_writephy(tp, 0x16, 0x0802);
1728                 if (tg3_wait_macro_done(tp)) {
1729                         *resetp = 1;
1730                         return -EBUSY;
1731                 }
1732
1733                 for (i = 0; i < 6; i += 2) {
1734                         u32 low, high;
1735
1736                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1737                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1738                             tg3_wait_macro_done(tp)) {
1739                                 *resetp = 1;
1740                                 return -EBUSY;
1741                         }
1742                         low &= 0x7fff;
1743                         high &= 0x000f;
1744                         if (low != test_pat[chan][i] ||
1745                             high != test_pat[chan][i+1]) {
1746                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1747                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1748                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1749
1750                                 return -EBUSY;
1751                         }
1752                 }
1753         }
1754
1755         return 0;
1756 }
1757
1758 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1759 {
1760         int chan;
1761
1762         for (chan = 0; chan < 4; chan++) {
1763                 int i;
1764
1765                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1766                              (chan * 0x2000) | 0x0200);
1767                 tg3_writephy(tp, 0x16, 0x0002);
1768                 for (i = 0; i < 6; i++)
1769                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1770                 tg3_writephy(tp, 0x16, 0x0202);
1771                 if (tg3_wait_macro_done(tp))
1772                         return -EBUSY;
1773         }
1774
1775         return 0;
1776 }
1777
1778 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1779 {
1780         u32 reg32, phy9_orig;
1781         int retries, do_phy_reset, err;
1782
1783         retries = 10;
1784         do_phy_reset = 1;
1785         do {
1786                 if (do_phy_reset) {
1787                         err = tg3_bmcr_reset(tp);
1788                         if (err)
1789                                 return err;
1790                         do_phy_reset = 0;
1791                 }
1792
1793                 /* Disable transmitter and interrupt.  */
1794                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1795                         continue;
1796
1797                 reg32 |= 0x3000;
1798                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1799
1800                 /* Set full-duplex, 1000 mbps.  */
1801                 tg3_writephy(tp, MII_BMCR,
1802                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1803
1804                 /* Set to master mode.  */
1805                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1806                         continue;
1807
1808                 tg3_writephy(tp, MII_TG3_CTRL,
1809                              (MII_TG3_CTRL_AS_MASTER |
1810                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1811
1812                 /* Enable SM_DSP_CLOCK and 6dB.  */
1813                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1814
1815                 /* Block the PHY control access.  */
1816                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1817                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1818
1819                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1820                 if (!err)
1821                         break;
1822         } while (--retries);
1823
1824         err = tg3_phy_reset_chanpat(tp);
1825         if (err)
1826                 return err;
1827
1828         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1829         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1830
1831         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1832         tg3_writephy(tp, 0x16, 0x0000);
1833
1834         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1835             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1836                 /* Set Extended packet length bit for jumbo frames */
1837                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1838         }
1839         else {
1840                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1841         }
1842
1843         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1844
1845         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1846                 reg32 &= ~0x3000;
1847                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1848         } else if (!err)
1849                 err = -EBUSY;
1850
1851         return err;
1852 }
1853
1854 /* This will reset the tigon3 PHY if there is no valid
1855  * link unless the FORCE argument is non-zero.
1856  */
1857 static int tg3_phy_reset(struct tg3 *tp)
1858 {
1859         u32 cpmuctrl;
1860         u32 phy_status;
1861         int err;
1862
1863         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1864                 u32 val;
1865
1866                 val = tr32(GRC_MISC_CFG);
1867                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1868                 udelay(40);
1869         }
1870         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1871         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1872         if (err != 0)
1873                 return -EBUSY;
1874
1875         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1876                 netif_carrier_off(tp->dev);
1877                 tg3_link_report(tp);
1878         }
1879
1880         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1881             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1882             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1883                 err = tg3_phy_reset_5703_4_5(tp);
1884                 if (err)
1885                         return err;
1886                 goto out;
1887         }
1888
1889         cpmuctrl = 0;
1890         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1891             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1892                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1893                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1894                         tw32(TG3_CPMU_CTRL,
1895                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1896         }
1897
1898         err = tg3_bmcr_reset(tp);
1899         if (err)
1900                 return err;
1901
1902         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1903                 u32 phy;
1904
1905                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1906                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1907
1908                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1909         }
1910
1911         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1912             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1913                 u32 val;
1914
1915                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1916                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1917                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1918                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1919                         udelay(40);
1920                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1921                 }
1922         }
1923
1924         tg3_phy_apply_otp(tp);
1925
1926         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1927                 tg3_phy_toggle_apd(tp, true);
1928         else
1929                 tg3_phy_toggle_apd(tp, false);
1930
1931 out:
1932         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1933                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1934                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1935                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1936                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1937                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1939         }
1940         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1941                 tg3_writephy(tp, 0x1c, 0x8d68);
1942                 tg3_writephy(tp, 0x1c, 0x8d68);
1943         }
1944         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1945                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1946                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1947                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1948                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1949                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1950                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1951                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1952                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1953         }
1954         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1955                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1956                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1957                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1958                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1959                         tg3_writephy(tp, MII_TG3_TEST1,
1960                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1961                 } else
1962                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1963                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1964         }
1965         /* Set Extended packet length bit (bit 14) on all chips that */
1966         /* support jumbo frames */
1967         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1968                 /* Cannot do read-modify-write on 5401 */
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1970         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1971                 u32 phy_reg;
1972
1973                 /* Set bit 14 with read-modify-write to preserve other bits */
1974                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1975                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1976                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1977         }
1978
1979         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1980          * jumbo frames transmission.
1981          */
1982         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1983                 u32 phy_reg;
1984
1985                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1986                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1987                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1988         }
1989
1990         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1991                 /* adjust output voltage */
1992                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1993         }
1994
1995         tg3_phy_toggle_automdix(tp, 1);
1996         tg3_phy_set_wirespeed(tp);
1997         return 0;
1998 }
1999
2000 static void tg3_frob_aux_power(struct tg3 *tp)
2001 {
2002         struct tg3 *tp_peer = tp;
2003
2004         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2005                 return;
2006
2007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2008             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2010                 struct net_device *dev_peer;
2011
2012                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2013                 /* remove_one() may have been run on the peer. */
2014                 if (!dev_peer)
2015                         tp_peer = tp;
2016                 else
2017                         tp_peer = netdev_priv(dev_peer);
2018         }
2019
2020         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2021             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2022             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2023             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2024                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2025                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2026                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2027                                     (GRC_LCLCTRL_GPIO_OE0 |
2028                                      GRC_LCLCTRL_GPIO_OE1 |
2029                                      GRC_LCLCTRL_GPIO_OE2 |
2030                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2031                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2032                                     100);
2033                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2034                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2035                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2036                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2037                                              GRC_LCLCTRL_GPIO_OE1 |
2038                                              GRC_LCLCTRL_GPIO_OE2 |
2039                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2040                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2041                                              tp->grc_local_ctrl;
2042                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2043
2044                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2045                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2046
2047                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2048                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2049                 } else {
2050                         u32 no_gpio2;
2051                         u32 grc_local_ctrl = 0;
2052
2053                         if (tp_peer != tp &&
2054                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2055                                 return;
2056
2057                         /* Workaround to prevent overdrawing Amps. */
2058                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2059                             ASIC_REV_5714) {
2060                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2061                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2062                                             grc_local_ctrl, 100);
2063                         }
2064
2065                         /* On 5753 and variants, GPIO2 cannot be used. */
2066                         no_gpio2 = tp->nic_sram_data_cfg &
2067                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2068
2069                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2070                                          GRC_LCLCTRL_GPIO_OE1 |
2071                                          GRC_LCLCTRL_GPIO_OE2 |
2072                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2073                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2074                         if (no_gpio2) {
2075                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2076                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2077                         }
2078                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2079                                                     grc_local_ctrl, 100);
2080
2081                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2082
2083                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2084                                                     grc_local_ctrl, 100);
2085
2086                         if (!no_gpio2) {
2087                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2088                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089                                             grc_local_ctrl, 100);
2090                         }
2091                 }
2092         } else {
2093                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2094                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2095                         if (tp_peer != tp &&
2096                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2097                                 return;
2098
2099                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2100                                     (GRC_LCLCTRL_GPIO_OE1 |
2101                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2102
2103                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104                                     GRC_LCLCTRL_GPIO_OE1, 100);
2105
2106                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2107                                     (GRC_LCLCTRL_GPIO_OE1 |
2108                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2109                 }
2110         }
2111 }
2112
2113 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2114 {
2115         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2116                 return 1;
2117         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2118                 if (speed != SPEED_10)
2119                         return 1;
2120         } else if (speed == SPEED_10)
2121                 return 1;
2122
2123         return 0;
2124 }
2125
2126 static int tg3_setup_phy(struct tg3 *, int);
2127
2128 #define RESET_KIND_SHUTDOWN     0
2129 #define RESET_KIND_INIT         1
2130 #define RESET_KIND_SUSPEND      2
2131
2132 static void tg3_write_sig_post_reset(struct tg3 *, int);
2133 static int tg3_halt_cpu(struct tg3 *, u32);
2134
2135 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2136 {
2137         u32 val;
2138
2139         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2140                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2141                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2142                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2143
2144                         sg_dig_ctrl |=
2145                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2146                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2147                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2148                 }
2149                 return;
2150         }
2151
2152         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2153                 tg3_bmcr_reset(tp);
2154                 val = tr32(GRC_MISC_CFG);
2155                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2156                 udelay(40);
2157                 return;
2158         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2159                 u32 phytest;
2160                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2161                         u32 phy;
2162
2163                         tg3_writephy(tp, MII_ADVERTISE, 0);
2164                         tg3_writephy(tp, MII_BMCR,
2165                                      BMCR_ANENABLE | BMCR_ANRESTART);
2166
2167                         tg3_writephy(tp, MII_TG3_FET_TEST,
2168                                      phytest | MII_TG3_FET_SHADOW_EN);
2169                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2170                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2171                                 tg3_writephy(tp,
2172                                              MII_TG3_FET_SHDW_AUXMODE4,
2173                                              phy);
2174                         }
2175                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2176                 }
2177                 return;
2178         } else if (do_low_power) {
2179                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2180                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2181
2182                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2183                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2184                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2185                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2186                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2187         }
2188
2189         /* The PHY should not be powered down on some chips because
2190          * of bugs.
2191          */
2192         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2193             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2194             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2195              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2196                 return;
2197
2198         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2199             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2200                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2201                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2202                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2203                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2204         }
2205
2206         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2207 }
2208
2209 /* tp->lock is held. */
2210 static int tg3_nvram_lock(struct tg3 *tp)
2211 {
2212         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2213                 int i;
2214
2215                 if (tp->nvram_lock_cnt == 0) {
2216                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2217                         for (i = 0; i < 8000; i++) {
2218                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2219                                         break;
2220                                 udelay(20);
2221                         }
2222                         if (i == 8000) {
2223                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2224                                 return -ENODEV;
2225                         }
2226                 }
2227                 tp->nvram_lock_cnt++;
2228         }
2229         return 0;
2230 }
2231
2232 /* tp->lock is held. */
2233 static void tg3_nvram_unlock(struct tg3 *tp)
2234 {
2235         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2236                 if (tp->nvram_lock_cnt > 0)
2237                         tp->nvram_lock_cnt--;
2238                 if (tp->nvram_lock_cnt == 0)
2239                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2240         }
2241 }
2242
2243 /* tp->lock is held. */
2244 static void tg3_enable_nvram_access(struct tg3 *tp)
2245 {
2246         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2247             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2248                 u32 nvaccess = tr32(NVRAM_ACCESS);
2249
2250                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2251         }
2252 }
2253
2254 /* tp->lock is held. */
2255 static void tg3_disable_nvram_access(struct tg3 *tp)
2256 {
2257         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2258             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2259                 u32 nvaccess = tr32(NVRAM_ACCESS);
2260
2261                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2262         }
2263 }
2264
2265 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2266                                         u32 offset, u32 *val)
2267 {
2268         u32 tmp;
2269         int i;
2270
2271         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2272                 return -EINVAL;
2273
2274         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2275                                         EEPROM_ADDR_DEVID_MASK |
2276                                         EEPROM_ADDR_READ);
2277         tw32(GRC_EEPROM_ADDR,
2278              tmp |
2279              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2280              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2281               EEPROM_ADDR_ADDR_MASK) |
2282              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2283
2284         for (i = 0; i < 1000; i++) {
2285                 tmp = tr32(GRC_EEPROM_ADDR);
2286
2287                 if (tmp & EEPROM_ADDR_COMPLETE)
2288                         break;
2289                 msleep(1);
2290         }
2291         if (!(tmp & EEPROM_ADDR_COMPLETE))
2292                 return -EBUSY;
2293
2294         tmp = tr32(GRC_EEPROM_DATA);
2295
2296         /*
2297          * The data will always be opposite the native endian
2298          * format.  Perform a blind byteswap to compensate.
2299          */
2300         *val = swab32(tmp);
2301
2302         return 0;
2303 }
2304
2305 #define NVRAM_CMD_TIMEOUT 10000
2306
2307 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2308 {
2309         int i;
2310
2311         tw32(NVRAM_CMD, nvram_cmd);
2312         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2313                 udelay(10);
2314                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2315                         udelay(10);
2316                         break;
2317                 }
2318         }
2319
2320         if (i == NVRAM_CMD_TIMEOUT)
2321                 return -EBUSY;
2322
2323         return 0;
2324 }
2325
2326 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2327 {
2328         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2329             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2330             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2331            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2332             (tp->nvram_jedecnum == JEDEC_ATMEL))
2333
2334                 addr = ((addr / tp->nvram_pagesize) <<
2335                         ATMEL_AT45DB0X1B_PAGE_POS) +
2336                        (addr % tp->nvram_pagesize);
2337
2338         return addr;
2339 }
2340
2341 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2342 {
2343         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2344             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2345             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2346            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2347             (tp->nvram_jedecnum == JEDEC_ATMEL))
2348
2349                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2350                         tp->nvram_pagesize) +
2351                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2352
2353         return addr;
2354 }
2355
2356 /* NOTE: Data read in from NVRAM is byteswapped according to
2357  * the byteswapping settings for all other register accesses.
2358  * tg3 devices are BE devices, so on a BE machine, the data
2359  * returned will be exactly as it is seen in NVRAM.  On a LE
2360  * machine, the 32-bit value will be byteswapped.
2361  */
2362 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2363 {
2364         int ret;
2365
2366         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2367                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2368
2369         offset = tg3_nvram_phys_addr(tp, offset);
2370
2371         if (offset > NVRAM_ADDR_MSK)
2372                 return -EINVAL;
2373
2374         ret = tg3_nvram_lock(tp);
2375         if (ret)
2376                 return ret;
2377
2378         tg3_enable_nvram_access(tp);
2379
2380         tw32(NVRAM_ADDR, offset);
2381         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2382                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2383
2384         if (ret == 0)
2385                 *val = tr32(NVRAM_RDDATA);
2386
2387         tg3_disable_nvram_access(tp);
2388
2389         tg3_nvram_unlock(tp);
2390
2391         return ret;
2392 }
2393
2394 /* Ensures NVRAM data is in bytestream format. */
2395 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2396 {
2397         u32 v;
2398         int res = tg3_nvram_read(tp, offset, &v);
2399         if (!res)
2400                 *val = cpu_to_be32(v);
2401         return res;
2402 }
2403
2404 /* tp->lock is held. */
2405 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2406 {
2407         u32 addr_high, addr_low;
2408         int i;
2409
2410         addr_high = ((tp->dev->dev_addr[0] << 8) |
2411                      tp->dev->dev_addr[1]);
2412         addr_low = ((tp->dev->dev_addr[2] << 24) |
2413                     (tp->dev->dev_addr[3] << 16) |
2414                     (tp->dev->dev_addr[4] <<  8) |
2415                     (tp->dev->dev_addr[5] <<  0));
2416         for (i = 0; i < 4; i++) {
2417                 if (i == 1 && skip_mac_1)
2418                         continue;
2419                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2420                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2421         }
2422
2423         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2424             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2425                 for (i = 0; i < 12; i++) {
2426                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2427                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2428                 }
2429         }
2430
2431         addr_high = (tp->dev->dev_addr[0] +
2432                      tp->dev->dev_addr[1] +
2433                      tp->dev->dev_addr[2] +
2434                      tp->dev->dev_addr[3] +
2435                      tp->dev->dev_addr[4] +
2436                      tp->dev->dev_addr[5]) &
2437                 TX_BACKOFF_SEED_MASK;
2438         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2439 }
2440
2441 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2442 {
2443         u32 misc_host_ctrl;
2444         bool device_should_wake, do_low_power;
2445
2446         /* Make sure register accesses (indirect or otherwise)
2447          * will function correctly.
2448          */
2449         pci_write_config_dword(tp->pdev,
2450                                TG3PCI_MISC_HOST_CTRL,
2451                                tp->misc_host_ctrl);
2452
2453         switch (state) {
2454         case PCI_D0:
2455                 pci_enable_wake(tp->pdev, state, false);
2456                 pci_set_power_state(tp->pdev, PCI_D0);
2457
2458                 /* Switch out of Vaux if it is a NIC */
2459                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2460                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2461
2462                 return 0;
2463
2464         case PCI_D1:
2465         case PCI_D2:
2466         case PCI_D3hot:
2467                 break;
2468
2469         default:
2470                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2471                         tp->dev->name, state);
2472                 return -EINVAL;
2473         }
2474
2475         /* Restore the CLKREQ setting. */
2476         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2477                 u16 lnkctl;
2478
2479                 pci_read_config_word(tp->pdev,
2480                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2481                                      &lnkctl);
2482                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2483                 pci_write_config_word(tp->pdev,
2484                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2485                                       lnkctl);
2486         }
2487
2488         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2489         tw32(TG3PCI_MISC_HOST_CTRL,
2490              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2491
2492         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2493                              device_may_wakeup(&tp->pdev->dev) &&
2494                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2495
2496         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2497                 do_low_power = false;
2498                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2499                     !tp->link_config.phy_is_low_power) {
2500                         struct phy_device *phydev;
2501                         u32 phyid, advertising;
2502
2503                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2504
2505                         tp->link_config.phy_is_low_power = 1;
2506
2507                         tp->link_config.orig_speed = phydev->speed;
2508                         tp->link_config.orig_duplex = phydev->duplex;
2509                         tp->link_config.orig_autoneg = phydev->autoneg;
2510                         tp->link_config.orig_advertising = phydev->advertising;
2511
2512                         advertising = ADVERTISED_TP |
2513                                       ADVERTISED_Pause |
2514                                       ADVERTISED_Autoneg |
2515                                       ADVERTISED_10baseT_Half;
2516
2517                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2518                             device_should_wake) {
2519                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2520                                         advertising |=
2521                                                 ADVERTISED_100baseT_Half |
2522                                                 ADVERTISED_100baseT_Full |
2523                                                 ADVERTISED_10baseT_Full;
2524                                 else
2525                                         advertising |= ADVERTISED_10baseT_Full;
2526                         }
2527
2528                         phydev->advertising = advertising;
2529
2530                         phy_start_aneg(phydev);
2531
2532                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2533                         if (phyid != TG3_PHY_ID_BCMAC131) {
2534                                 phyid &= TG3_PHY_OUI_MASK;
2535                                 if (phyid == TG3_PHY_OUI_1 ||
2536                                     phyid == TG3_PHY_OUI_2 ||
2537                                     phyid == TG3_PHY_OUI_3)
2538                                         do_low_power = true;
2539                         }
2540                 }
2541         } else {
2542                 do_low_power = true;
2543
2544                 if (tp->link_config.phy_is_low_power == 0) {
2545                         tp->link_config.phy_is_low_power = 1;
2546                         tp->link_config.orig_speed = tp->link_config.speed;
2547                         tp->link_config.orig_duplex = tp->link_config.duplex;
2548                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2549                 }
2550
2551                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2552                         tp->link_config.speed = SPEED_10;
2553                         tp->link_config.duplex = DUPLEX_HALF;
2554                         tp->link_config.autoneg = AUTONEG_ENABLE;
2555                         tg3_setup_phy(tp, 0);
2556                 }
2557         }
2558
2559         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2560                 u32 val;
2561
2562                 val = tr32(GRC_VCPU_EXT_CTRL);
2563                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2564         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2565                 int i;
2566                 u32 val;
2567
2568                 for (i = 0; i < 200; i++) {
2569                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2570                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2571                                 break;
2572                         msleep(1);
2573                 }
2574         }
2575         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2576                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2577                                                      WOL_DRV_STATE_SHUTDOWN |
2578                                                      WOL_DRV_WOL |
2579                                                      WOL_SET_MAGIC_PKT);
2580
2581         if (device_should_wake) {
2582                 u32 mac_mode;
2583
2584                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2585                         if (do_low_power) {
2586                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2587                                 udelay(40);
2588                         }
2589
2590                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2591                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2592                         else
2593                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2594
2595                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2596                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2597                             ASIC_REV_5700) {
2598                                 u32 speed = (tp->tg3_flags &
2599                                              TG3_FLAG_WOL_SPEED_100MB) ?
2600                                              SPEED_100 : SPEED_10;
2601                                 if (tg3_5700_link_polarity(tp, speed))
2602                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2603                                 else
2604                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2605                         }
2606                 } else {
2607                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2608                 }
2609
2610                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2611                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2612
2613                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2614                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2615                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2616                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2617                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2618                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2619
2620                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2621                         mac_mode |= tp->mac_mode &
2622                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2623                         if (mac_mode & MAC_MODE_APE_TX_EN)
2624                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2625                 }
2626
2627                 tw32_f(MAC_MODE, mac_mode);
2628                 udelay(100);
2629
2630                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2631                 udelay(10);
2632         }
2633
2634         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2635             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2636              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2637                 u32 base_val;
2638
2639                 base_val = tp->pci_clock_ctrl;
2640                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2641                              CLOCK_CTRL_TXCLK_DISABLE);
2642
2643                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2644                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2645         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2646                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2647                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2648                 /* do nothing */
2649         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2650                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2651                 u32 newbits1, newbits2;
2652
2653                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2654                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2655                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2656                                     CLOCK_CTRL_TXCLK_DISABLE |
2657                                     CLOCK_CTRL_ALTCLK);
2658                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2659                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2660                         newbits1 = CLOCK_CTRL_625_CORE;
2661                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2662                 } else {
2663                         newbits1 = CLOCK_CTRL_ALTCLK;
2664                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2665                 }
2666
2667                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2668                             40);
2669
2670                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2671                             40);
2672
2673                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2674                         u32 newbits3;
2675
2676                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2677                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2678                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2679                                             CLOCK_CTRL_TXCLK_DISABLE |
2680                                             CLOCK_CTRL_44MHZ_CORE);
2681                         } else {
2682                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2683                         }
2684
2685                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2686                                     tp->pci_clock_ctrl | newbits3, 40);
2687                 }
2688         }
2689
2690         if (!(device_should_wake) &&
2691             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2692                 tg3_power_down_phy(tp, do_low_power);
2693
2694         tg3_frob_aux_power(tp);
2695
2696         /* Workaround for unstable PLL clock */
2697         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2698             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2699                 u32 val = tr32(0x7d00);
2700
2701                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2702                 tw32(0x7d00, val);
2703                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2704                         int err;
2705
2706                         err = tg3_nvram_lock(tp);
2707                         tg3_halt_cpu(tp, RX_CPU_BASE);
2708                         if (!err)
2709                                 tg3_nvram_unlock(tp);
2710                 }
2711         }
2712
2713         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2714
2715         if (device_should_wake)
2716                 pci_enable_wake(tp->pdev, state, true);
2717
2718         /* Finally, set the new power state. */
2719         pci_set_power_state(tp->pdev, state);
2720
2721         return 0;
2722 }
2723
2724 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2725 {
2726         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2727         case MII_TG3_AUX_STAT_10HALF:
2728                 *speed = SPEED_10;
2729                 *duplex = DUPLEX_HALF;
2730                 break;
2731
2732         case MII_TG3_AUX_STAT_10FULL:
2733                 *speed = SPEED_10;
2734                 *duplex = DUPLEX_FULL;
2735                 break;
2736
2737         case MII_TG3_AUX_STAT_100HALF:
2738                 *speed = SPEED_100;
2739                 *duplex = DUPLEX_HALF;
2740                 break;
2741
2742         case MII_TG3_AUX_STAT_100FULL:
2743                 *speed = SPEED_100;
2744                 *duplex = DUPLEX_FULL;
2745                 break;
2746
2747         case MII_TG3_AUX_STAT_1000HALF:
2748                 *speed = SPEED_1000;
2749                 *duplex = DUPLEX_HALF;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_1000FULL:
2753                 *speed = SPEED_1000;
2754                 *duplex = DUPLEX_FULL;
2755                 break;
2756
2757         default:
2758                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2759                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2760                                  SPEED_10;
2761                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2762                                   DUPLEX_HALF;
2763                         break;
2764                 }
2765                 *speed = SPEED_INVALID;
2766                 *duplex = DUPLEX_INVALID;
2767                 break;
2768         }
2769 }
2770
2771 static void tg3_phy_copper_begin(struct tg3 *tp)
2772 {
2773         u32 new_adv;
2774         int i;
2775
2776         if (tp->link_config.phy_is_low_power) {
2777                 /* Entering low power mode.  Disable gigabit and
2778                  * 100baseT advertisements.
2779                  */
2780                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2781
2782                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2783                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2784                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2785                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2786
2787                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2788         } else if (tp->link_config.speed == SPEED_INVALID) {
2789                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2790                         tp->link_config.advertising &=
2791                                 ~(ADVERTISED_1000baseT_Half |
2792                                   ADVERTISED_1000baseT_Full);
2793
2794                 new_adv = ADVERTISE_CSMA;
2795                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2796                         new_adv |= ADVERTISE_10HALF;
2797                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2798                         new_adv |= ADVERTISE_10FULL;
2799                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2800                         new_adv |= ADVERTISE_100HALF;
2801                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2802                         new_adv |= ADVERTISE_100FULL;
2803
2804                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2805
2806                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2807
2808                 if (tp->link_config.advertising &
2809                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2810                         new_adv = 0;
2811                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2812                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2813                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2814                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2815                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2816                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2817                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2818                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2819                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2820                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2821                 } else {
2822                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2823                 }
2824         } else {
2825                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2826                 new_adv |= ADVERTISE_CSMA;
2827
2828                 /* Asking for a specific link mode. */
2829                 if (tp->link_config.speed == SPEED_1000) {
2830                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2831
2832                         if (tp->link_config.duplex == DUPLEX_FULL)
2833                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2834                         else
2835                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2836                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2837                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2838                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2839                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2840                 } else {
2841                         if (tp->link_config.speed == SPEED_100) {
2842                                 if (tp->link_config.duplex == DUPLEX_FULL)
2843                                         new_adv |= ADVERTISE_100FULL;
2844                                 else
2845                                         new_adv |= ADVERTISE_100HALF;
2846                         } else {
2847                                 if (tp->link_config.duplex == DUPLEX_FULL)
2848                                         new_adv |= ADVERTISE_10FULL;
2849                                 else
2850                                         new_adv |= ADVERTISE_10HALF;
2851                         }
2852                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2853
2854                         new_adv = 0;
2855                 }
2856
2857                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2858         }
2859
2860         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2861             tp->link_config.speed != SPEED_INVALID) {
2862                 u32 bmcr, orig_bmcr;
2863
2864                 tp->link_config.active_speed = tp->link_config.speed;
2865                 tp->link_config.active_duplex = tp->link_config.duplex;
2866
2867                 bmcr = 0;
2868                 switch (tp->link_config.speed) {
2869                 default:
2870                 case SPEED_10:
2871                         break;
2872
2873                 case SPEED_100:
2874                         bmcr |= BMCR_SPEED100;
2875                         break;
2876
2877                 case SPEED_1000:
2878                         bmcr |= TG3_BMCR_SPEED1000;
2879                         break;
2880                 }
2881
2882                 if (tp->link_config.duplex == DUPLEX_FULL)
2883                         bmcr |= BMCR_FULLDPLX;
2884
2885                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2886                     (bmcr != orig_bmcr)) {
2887                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2888                         for (i = 0; i < 1500; i++) {
2889                                 u32 tmp;
2890
2891                                 udelay(10);
2892                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2893                                     tg3_readphy(tp, MII_BMSR, &tmp))
2894                                         continue;
2895                                 if (!(tmp & BMSR_LSTATUS)) {
2896                                         udelay(40);
2897                                         break;
2898                                 }
2899                         }
2900                         tg3_writephy(tp, MII_BMCR, bmcr);
2901                         udelay(40);
2902                 }
2903         } else {
2904                 tg3_writephy(tp, MII_BMCR,
2905                              BMCR_ANENABLE | BMCR_ANRESTART);
2906         }
2907 }
2908
2909 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2910 {
2911         int err;
2912
2913         /* Turn off tap power management. */
2914         /* Set Extended packet length bit */
2915         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2916
2917         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2918         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2919
2920         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2921         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2922
2923         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2924         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2925
2926         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2927         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2928
2929         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2930         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2931
2932         udelay(40);
2933
2934         return err;
2935 }
2936
2937 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2938 {
2939         u32 adv_reg, all_mask = 0;
2940
2941         if (mask & ADVERTISED_10baseT_Half)
2942                 all_mask |= ADVERTISE_10HALF;
2943         if (mask & ADVERTISED_10baseT_Full)
2944                 all_mask |= ADVERTISE_10FULL;
2945         if (mask & ADVERTISED_100baseT_Half)
2946                 all_mask |= ADVERTISE_100HALF;
2947         if (mask & ADVERTISED_100baseT_Full)
2948                 all_mask |= ADVERTISE_100FULL;
2949
2950         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2951                 return 0;
2952
2953         if ((adv_reg & all_mask) != all_mask)
2954                 return 0;
2955         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2956                 u32 tg3_ctrl;
2957
2958                 all_mask = 0;
2959                 if (mask & ADVERTISED_1000baseT_Half)
2960                         all_mask |= ADVERTISE_1000HALF;
2961                 if (mask & ADVERTISED_1000baseT_Full)
2962                         all_mask |= ADVERTISE_1000FULL;
2963
2964                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2965                         return 0;
2966
2967                 if ((tg3_ctrl & all_mask) != all_mask)
2968                         return 0;
2969         }
2970         return 1;
2971 }
2972
2973 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2974 {
2975         u32 curadv, reqadv;
2976
2977         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2978                 return 1;
2979
2980         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2981         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2982
2983         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2984                 if (curadv != reqadv)
2985                         return 0;
2986
2987                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2988                         tg3_readphy(tp, MII_LPA, rmtadv);
2989         } else {
2990                 /* Reprogram the advertisement register, even if it
2991                  * does not affect the current link.  If the link
2992                  * gets renegotiated in the future, we can save an
2993                  * additional renegotiation cycle by advertising
2994                  * it correctly in the first place.
2995                  */
2996                 if (curadv != reqadv) {
2997                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2998                                      ADVERTISE_PAUSE_ASYM);
2999                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3000                 }
3001         }
3002
3003         return 1;
3004 }
3005
3006 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3007 {
3008         int current_link_up;
3009         u32 bmsr, dummy;
3010         u32 lcl_adv, rmt_adv;
3011         u16 current_speed;
3012         u8 current_duplex;
3013         int i, err;
3014
3015         tw32(MAC_EVENT, 0);
3016
3017         tw32_f(MAC_STATUS,
3018              (MAC_STATUS_SYNC_CHANGED |
3019               MAC_STATUS_CFG_CHANGED |
3020               MAC_STATUS_MI_COMPLETION |
3021               MAC_STATUS_LNKSTATE_CHANGED));
3022         udelay(40);
3023
3024         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3025                 tw32_f(MAC_MI_MODE,
3026                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3027                 udelay(80);
3028         }
3029
3030         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3031
3032         /* Some third-party PHYs need to be reset on link going
3033          * down.
3034          */
3035         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3036              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3037              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3038             netif_carrier_ok(tp->dev)) {
3039                 tg3_readphy(tp, MII_BMSR, &bmsr);
3040                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3041                     !(bmsr & BMSR_LSTATUS))
3042                         force_reset = 1;
3043         }
3044         if (force_reset)
3045                 tg3_phy_reset(tp);
3046
3047         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3048                 tg3_readphy(tp, MII_BMSR, &bmsr);
3049                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3050                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3051                         bmsr = 0;
3052
3053                 if (!(bmsr & BMSR_LSTATUS)) {
3054                         err = tg3_init_5401phy_dsp(tp);
3055                         if (err)
3056                                 return err;
3057
3058                         tg3_readphy(tp, MII_BMSR, &bmsr);
3059                         for (i = 0; i < 1000; i++) {
3060                                 udelay(10);
3061                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3062                                     (bmsr & BMSR_LSTATUS)) {
3063                                         udelay(40);
3064                                         break;
3065                                 }
3066                         }
3067
3068                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3069                             !(bmsr & BMSR_LSTATUS) &&
3070                             tp->link_config.active_speed == SPEED_1000) {
3071                                 err = tg3_phy_reset(tp);
3072                                 if (!err)
3073                                         err = tg3_init_5401phy_dsp(tp);
3074                                 if (err)
3075                                         return err;
3076                         }
3077                 }
3078         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3079                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3080                 /* 5701 {A0,B0} CRC bug workaround */
3081                 tg3_writephy(tp, 0x15, 0x0a75);
3082                 tg3_writephy(tp, 0x1c, 0x8c68);
3083                 tg3_writephy(tp, 0x1c, 0x8d68);
3084                 tg3_writephy(tp, 0x1c, 0x8c68);
3085         }
3086
3087         /* Clear pending interrupts... */
3088         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3089         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3090
3091         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3092                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3093         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3094                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3095
3096         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3097             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3098                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3099                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3100                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3101                 else
3102                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3103         }
3104
3105         current_link_up = 0;
3106         current_speed = SPEED_INVALID;
3107         current_duplex = DUPLEX_INVALID;
3108
3109         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3110                 u32 val;
3111
3112                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3113                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3114                 if (!(val & (1 << 10))) {
3115                         val |= (1 << 10);
3116                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3117                         goto relink;
3118                 }
3119         }
3120
3121         bmsr = 0;
3122         for (i = 0; i < 100; i++) {
3123                 tg3_readphy(tp, MII_BMSR, &bmsr);
3124                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3125                     (bmsr & BMSR_LSTATUS))
3126                         break;
3127                 udelay(40);
3128         }
3129
3130         if (bmsr & BMSR_LSTATUS) {
3131                 u32 aux_stat, bmcr;
3132
3133                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3134                 for (i = 0; i < 2000; i++) {
3135                         udelay(10);
3136                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3137                             aux_stat)
3138                                 break;
3139                 }
3140
3141                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3142                                              &current_speed,
3143                                              &current_duplex);
3144
3145                 bmcr = 0;
3146                 for (i = 0; i < 200; i++) {
3147                         tg3_readphy(tp, MII_BMCR, &bmcr);
3148                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3149                                 continue;
3150                         if (bmcr && bmcr != 0x7fff)
3151                                 break;
3152                         udelay(10);
3153                 }
3154
3155                 lcl_adv = 0;
3156                 rmt_adv = 0;
3157
3158                 tp->link_config.active_speed = current_speed;
3159                 tp->link_config.active_duplex = current_duplex;
3160
3161                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3162                         if ((bmcr & BMCR_ANENABLE) &&
3163                             tg3_copper_is_advertising_all(tp,
3164                                                 tp->link_config.advertising)) {
3165                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3166                                                                   &rmt_adv))
3167                                         current_link_up = 1;
3168                         }
3169                 } else {
3170                         if (!(bmcr & BMCR_ANENABLE) &&
3171                             tp->link_config.speed == current_speed &&
3172                             tp->link_config.duplex == current_duplex &&
3173                             tp->link_config.flowctrl ==
3174                             tp->link_config.active_flowctrl) {
3175                                 current_link_up = 1;
3176                         }
3177                 }
3178
3179                 if (current_link_up == 1 &&
3180                     tp->link_config.active_duplex == DUPLEX_FULL)
3181                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3182         }
3183
3184 relink:
3185         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3186                 u32 tmp;
3187
3188                 tg3_phy_copper_begin(tp);
3189
3190                 tg3_readphy(tp, MII_BMSR, &tmp);
3191                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3192                     (tmp & BMSR_LSTATUS))
3193                         current_link_up = 1;
3194         }
3195
3196         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3197         if (current_link_up == 1) {
3198                 if (tp->link_config.active_speed == SPEED_100 ||
3199                     tp->link_config.active_speed == SPEED_10)
3200                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3201                 else
3202                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3203         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3204                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3205         else
3206                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3207
3208         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3209         if (tp->link_config.active_duplex == DUPLEX_HALF)
3210                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3211
3212         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3213                 if (current_link_up == 1 &&
3214                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3215                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3216                 else
3217                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3218         }
3219
3220         /* ??? Without this setting Netgear GA302T PHY does not
3221          * ??? send/receive packets...
3222          */
3223         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3224             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3225                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3226                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3227                 udelay(80);
3228         }
3229
3230         tw32_f(MAC_MODE, tp->mac_mode);
3231         udelay(40);
3232
3233         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3234                 /* Polled via timer. */
3235                 tw32_f(MAC_EVENT, 0);
3236         } else {
3237                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3238         }
3239         udelay(40);
3240
3241         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3242             current_link_up == 1 &&
3243             tp->link_config.active_speed == SPEED_1000 &&
3244             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3245              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3246                 udelay(120);
3247                 tw32_f(MAC_STATUS,
3248                      (MAC_STATUS_SYNC_CHANGED |
3249                       MAC_STATUS_CFG_CHANGED));
3250                 udelay(40);
3251                 tg3_write_mem(tp,
3252                               NIC_SRAM_FIRMWARE_MBOX,
3253                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3254         }
3255
3256         /* Prevent send BD corruption. */
3257         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3258                 u16 oldlnkctl, newlnkctl;
3259
3260                 pci_read_config_word(tp->pdev,
3261                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3262                                      &oldlnkctl);
3263                 if (tp->link_config.active_speed == SPEED_100 ||
3264                     tp->link_config.active_speed == SPEED_10)
3265                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3266                 else
3267                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3268                 if (newlnkctl != oldlnkctl)
3269                         pci_write_config_word(tp->pdev,
3270                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3271                                               newlnkctl);
3272         }
3273
3274         if (current_link_up != netif_carrier_ok(tp->dev)) {
3275                 if (current_link_up)
3276                         netif_carrier_on(tp->dev);
3277                 else
3278                         netif_carrier_off(tp->dev);
3279                 tg3_link_report(tp);
3280         }
3281
3282         return 0;
3283 }
3284
3285 struct tg3_fiber_aneginfo {
3286         int state;
3287 #define ANEG_STATE_UNKNOWN              0
3288 #define ANEG_STATE_AN_ENABLE            1
3289 #define ANEG_STATE_RESTART_INIT         2
3290 #define ANEG_STATE_RESTART              3
3291 #define ANEG_STATE_DISABLE_LINK_OK      4
3292 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3293 #define ANEG_STATE_ABILITY_DETECT       6
3294 #define ANEG_STATE_ACK_DETECT_INIT      7
3295 #define ANEG_STATE_ACK_DETECT           8
3296 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3297 #define ANEG_STATE_COMPLETE_ACK         10
3298 #define ANEG_STATE_IDLE_DETECT_INIT     11
3299 #define ANEG_STATE_IDLE_DETECT          12
3300 #define ANEG_STATE_LINK_OK              13
3301 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3302 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3303
3304         u32 flags;
3305 #define MR_AN_ENABLE            0x00000001
3306 #define MR_RESTART_AN           0x00000002
3307 #define MR_AN_COMPLETE          0x00000004
3308 #define MR_PAGE_RX              0x00000008
3309 #define MR_NP_LOADED            0x00000010
3310 #define MR_TOGGLE_TX            0x00000020
3311 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3312 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3313 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3314 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3315 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3316 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3317 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3318 #define MR_TOGGLE_RX            0x00002000
3319 #define MR_NP_RX                0x00004000
3320
3321 #define MR_LINK_OK              0x80000000
3322
3323         unsigned long link_time, cur_time;
3324
3325         u32 ability_match_cfg;
3326         int ability_match_count;
3327
3328         char ability_match, idle_match, ack_match;
3329
3330         u32 txconfig, rxconfig;
3331 #define ANEG_CFG_NP             0x00000080
3332 #define ANEG_CFG_ACK            0x00000040
3333 #define ANEG_CFG_RF2            0x00000020
3334 #define ANEG_CFG_RF1            0x00000010
3335 #define ANEG_CFG_PS2            0x00000001
3336 #define ANEG_CFG_PS1            0x00008000
3337 #define ANEG_CFG_HD             0x00004000
3338 #define ANEG_CFG_FD             0x00002000
3339 #define ANEG_CFG_INVAL          0x00001f06
3340
3341 };
3342 #define ANEG_OK         0
3343 #define ANEG_DONE       1
3344 #define ANEG_TIMER_ENAB 2
3345 #define ANEG_FAILED     -1
3346
3347 #define ANEG_STATE_SETTLE_TIME  10000
3348
3349 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3350                                    struct tg3_fiber_aneginfo *ap)
3351 {
3352         u16 flowctrl;
3353         unsigned long delta;
3354         u32 rx_cfg_reg;
3355         int ret;
3356
3357         if (ap->state == ANEG_STATE_UNKNOWN) {
3358                 ap->rxconfig = 0;
3359                 ap->link_time = 0;
3360                 ap->cur_time = 0;
3361                 ap->ability_match_cfg = 0;
3362                 ap->ability_match_count = 0;
3363                 ap->ability_match = 0;
3364                 ap->idle_match = 0;
3365                 ap->ack_match = 0;
3366         }
3367         ap->cur_time++;
3368
3369         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3370                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3371
3372                 if (rx_cfg_reg != ap->ability_match_cfg) {
3373                         ap->ability_match_cfg = rx_cfg_reg;
3374                         ap->ability_match = 0;
3375                         ap->ability_match_count = 0;
3376                 } else {
3377                         if (++ap->ability_match_count > 1) {
3378                                 ap->ability_match = 1;
3379                                 ap->ability_match_cfg = rx_cfg_reg;
3380                         }
3381                 }
3382                 if (rx_cfg_reg & ANEG_CFG_ACK)
3383                         ap->ack_match = 1;
3384                 else
3385                         ap->ack_match = 0;
3386
3387                 ap->idle_match = 0;
3388         } else {
3389                 ap->idle_match = 1;
3390                 ap->ability_match_cfg = 0;
3391                 ap->ability_match_count = 0;
3392                 ap->ability_match = 0;
3393                 ap->ack_match = 0;
3394
3395                 rx_cfg_reg = 0;
3396         }
3397
3398         ap->rxconfig = rx_cfg_reg;
3399         ret = ANEG_OK;
3400
3401         switch(ap->state) {
3402         case ANEG_STATE_UNKNOWN:
3403                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3404                         ap->state = ANEG_STATE_AN_ENABLE;
3405
3406                 /* fallthru */
3407         case ANEG_STATE_AN_ENABLE:
3408                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3409                 if (ap->flags & MR_AN_ENABLE) {
3410                         ap->link_time = 0;
3411                         ap->cur_time = 0;
3412                         ap->ability_match_cfg = 0;
3413                         ap->ability_match_count = 0;
3414                         ap->ability_match = 0;
3415                         ap->idle_match = 0;
3416                         ap->ack_match = 0;
3417
3418                         ap->state = ANEG_STATE_RESTART_INIT;
3419                 } else {
3420                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3421                 }
3422                 break;
3423
3424         case ANEG_STATE_RESTART_INIT:
3425                 ap->link_time = ap->cur_time;
3426                 ap->flags &= ~(MR_NP_LOADED);
3427                 ap->txconfig = 0;
3428                 tw32(MAC_TX_AUTO_NEG, 0);
3429                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3430                 tw32_f(MAC_MODE, tp->mac_mode);
3431                 udelay(40);
3432
3433                 ret = ANEG_TIMER_ENAB;
3434                 ap->state = ANEG_STATE_RESTART;
3435
3436                 /* fallthru */
3437         case ANEG_STATE_RESTART:
3438                 delta = ap->cur_time - ap->link_time;
3439                 if (delta > ANEG_STATE_SETTLE_TIME) {
3440                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3441                 } else {
3442                         ret = ANEG_TIMER_ENAB;
3443                 }
3444                 break;
3445
3446         case ANEG_STATE_DISABLE_LINK_OK:
3447                 ret = ANEG_DONE;
3448                 break;
3449
3450         case ANEG_STATE_ABILITY_DETECT_INIT:
3451                 ap->flags &= ~(MR_TOGGLE_TX);
3452                 ap->txconfig = ANEG_CFG_FD;
3453                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3454                 if (flowctrl & ADVERTISE_1000XPAUSE)
3455                         ap->txconfig |= ANEG_CFG_PS1;
3456                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3457                         ap->txconfig |= ANEG_CFG_PS2;
3458                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3459                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3460                 tw32_f(MAC_MODE, tp->mac_mode);
3461                 udelay(40);
3462
3463                 ap->state = ANEG_STATE_ABILITY_DETECT;
3464                 break;
3465
3466         case ANEG_STATE_ABILITY_DETECT:
3467                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3468                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3469                 }
3470                 break;
3471
3472         case ANEG_STATE_ACK_DETECT_INIT:
3473                 ap->txconfig |= ANEG_CFG_ACK;
3474                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3475                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3476                 tw32_f(MAC_MODE, tp->mac_mode);
3477                 udelay(40);
3478
3479                 ap->state = ANEG_STATE_ACK_DETECT;
3480
3481                 /* fallthru */
3482         case ANEG_STATE_ACK_DETECT:
3483                 if (ap->ack_match != 0) {
3484                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3485                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3486                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3487                         } else {
3488                                 ap->state = ANEG_STATE_AN_ENABLE;
3489                         }
3490                 } else if (ap->ability_match != 0 &&
3491                            ap->rxconfig == 0) {
3492                         ap->state = ANEG_STATE_AN_ENABLE;
3493                 }
3494                 break;
3495
3496         case ANEG_STATE_COMPLETE_ACK_INIT:
3497                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3498                         ret = ANEG_FAILED;
3499                         break;
3500                 }
3501                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3502                                MR_LP_ADV_HALF_DUPLEX |
3503                                MR_LP_ADV_SYM_PAUSE |
3504                                MR_LP_ADV_ASYM_PAUSE |
3505                                MR_LP_ADV_REMOTE_FAULT1 |
3506                                MR_LP_ADV_REMOTE_FAULT2 |
3507                                MR_LP_ADV_NEXT_PAGE |
3508                                MR_TOGGLE_RX |
3509                                MR_NP_RX);
3510                 if (ap->rxconfig & ANEG_CFG_FD)
3511                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3512                 if (ap->rxconfig & ANEG_CFG_HD)
3513                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3514                 if (ap->rxconfig & ANEG_CFG_PS1)
3515                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3516                 if (ap->rxconfig & ANEG_CFG_PS2)
3517                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3518                 if (ap->rxconfig & ANEG_CFG_RF1)
3519                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3520                 if (ap->rxconfig & ANEG_CFG_RF2)
3521                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3522                 if (ap->rxconfig & ANEG_CFG_NP)
3523                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3524
3525                 ap->link_time = ap->cur_time;
3526
3527                 ap->flags ^= (MR_TOGGLE_TX);
3528                 if (ap->rxconfig & 0x0008)
3529                         ap->flags |= MR_TOGGLE_RX;
3530                 if (ap->rxconfig & ANEG_CFG_NP)
3531                         ap->flags |= MR_NP_RX;
3532                 ap->flags |= MR_PAGE_RX;
3533
3534                 ap->state = ANEG_STATE_COMPLETE_ACK;
3535                 ret = ANEG_TIMER_ENAB;
3536                 break;
3537
3538         case ANEG_STATE_COMPLETE_ACK:
3539                 if (ap->ability_match != 0 &&
3540                     ap->rxconfig == 0) {
3541                         ap->state = ANEG_STATE_AN_ENABLE;
3542                         break;
3543                 }
3544                 delta = ap->cur_time - ap->link_time;
3545                 if (delta > ANEG_STATE_SETTLE_TIME) {
3546                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3547                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3548                         } else {
3549                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3550                                     !(ap->flags & MR_NP_RX)) {
3551                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3552                                 } else {
3553                                         ret = ANEG_FAILED;
3554                                 }
3555                         }
3556                 }
3557                 break;
3558
3559         case ANEG_STATE_IDLE_DETECT_INIT:
3560                 ap->link_time = ap->cur_time;
3561                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3562                 tw32_f(MAC_MODE, tp->mac_mode);
3563                 udelay(40);
3564
3565                 ap->state = ANEG_STATE_IDLE_DETECT;
3566                 ret = ANEG_TIMER_ENAB;
3567                 break;
3568
3569         case ANEG_STATE_IDLE_DETECT:
3570                 if (ap->ability_match != 0 &&
3571                     ap->rxconfig == 0) {
3572                         ap->state = ANEG_STATE_AN_ENABLE;
3573                         break;
3574                 }
3575                 delta = ap->cur_time - ap->link_time;
3576                 if (delta > ANEG_STATE_SETTLE_TIME) {
3577                         /* XXX another gem from the Broadcom driver :( */
3578                         ap->state = ANEG_STATE_LINK_OK;
3579                 }
3580                 break;
3581
3582         case ANEG_STATE_LINK_OK:
3583                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3584                 ret = ANEG_DONE;
3585                 break;
3586
3587         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3588                 /* ??? unimplemented */
3589                 break;
3590
3591         case ANEG_STATE_NEXT_PAGE_WAIT:
3592                 /* ??? unimplemented */
3593                 break;
3594
3595         default:
3596                 ret = ANEG_FAILED;
3597                 break;
3598         }
3599
3600         return ret;
3601 }
3602
3603 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3604 {
3605         int res = 0;
3606         struct tg3_fiber_aneginfo aninfo;
3607         int status = ANEG_FAILED;
3608         unsigned int tick;
3609         u32 tmp;
3610
3611         tw32_f(MAC_TX_AUTO_NEG, 0);
3612
3613         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3614         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3615         udelay(40);
3616
3617         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3618         udelay(40);
3619
3620         memset(&aninfo, 0, sizeof(aninfo));
3621         aninfo.flags |= MR_AN_ENABLE;
3622         aninfo.state = ANEG_STATE_UNKNOWN;
3623         aninfo.cur_time = 0;
3624         tick = 0;
3625         while (++tick < 195000) {
3626                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3627                 if (status == ANEG_DONE || status == ANEG_FAILED)
3628                         break;
3629
3630                 udelay(1);
3631         }
3632
3633         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3634         tw32_f(MAC_MODE, tp->mac_mode);
3635         udelay(40);
3636
3637         *txflags = aninfo.txconfig;
3638         *rxflags = aninfo.flags;
3639
3640         if (status == ANEG_DONE &&
3641             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3642                              MR_LP_ADV_FULL_DUPLEX)))
3643                 res = 1;
3644
3645         return res;
3646 }
3647
3648 static void tg3_init_bcm8002(struct tg3 *tp)
3649 {
3650         u32 mac_status = tr32(MAC_STATUS);
3651         int i;
3652
3653         /* Reset when initting first time or we have a link. */
3654         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3655             !(mac_status & MAC_STATUS_PCS_SYNCED))
3656                 return;
3657
3658         /* Set PLL lock range. */
3659         tg3_writephy(tp, 0x16, 0x8007);
3660
3661         /* SW reset */
3662         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3663
3664         /* Wait for reset to complete. */
3665         /* XXX schedule_timeout() ... */
3666         for (i = 0; i < 500; i++)
3667                 udelay(10);
3668
3669         /* Config mode; select PMA/Ch 1 regs. */
3670         tg3_writephy(tp, 0x10, 0x8411);
3671
3672         /* Enable auto-lock and comdet, select txclk for tx. */
3673         tg3_writephy(tp, 0x11, 0x0a10);
3674
3675         tg3_writephy(tp, 0x18, 0x00a0);
3676         tg3_writephy(tp, 0x16, 0x41ff);
3677
3678         /* Assert and deassert POR. */
3679         tg3_writephy(tp, 0x13, 0x0400);
3680         udelay(40);
3681         tg3_writephy(tp, 0x13, 0x0000);
3682
3683         tg3_writephy(tp, 0x11, 0x0a50);
3684         udelay(40);
3685         tg3_writephy(tp, 0x11, 0x0a10);
3686
3687         /* Wait for signal to stabilize */
3688         /* XXX schedule_timeout() ... */
3689         for (i = 0; i < 15000; i++)
3690                 udelay(10);
3691
3692         /* Deselect the channel register so we can read the PHYID
3693          * later.
3694          */
3695         tg3_writephy(tp, 0x10, 0x8011);
3696 }
3697
3698 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3699 {
3700         u16 flowctrl;
3701         u32 sg_dig_ctrl, sg_dig_status;
3702         u32 serdes_cfg, expected_sg_dig_ctrl;
3703         int workaround, port_a;
3704         int current_link_up;
3705
3706         serdes_cfg = 0;
3707         expected_sg_dig_ctrl = 0;
3708         workaround = 0;
3709         port_a = 1;
3710         current_link_up = 0;
3711
3712         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3713             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3714                 workaround = 1;
3715                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3716                         port_a = 0;
3717
3718                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3719                 /* preserve bits 20-23 for voltage regulator */
3720                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3721         }
3722
3723         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3724
3725         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3726                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3727                         if (workaround) {
3728                                 u32 val = serdes_cfg;
3729
3730                                 if (port_a)
3731                                         val |= 0xc010000;
3732                                 else
3733                                         val |= 0x4010000;
3734                                 tw32_f(MAC_SERDES_CFG, val);
3735                         }
3736
3737                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3738                 }
3739                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3740                         tg3_setup_flow_control(tp, 0, 0);
3741                         current_link_up = 1;
3742                 }
3743                 goto out;
3744         }
3745
3746         /* Want auto-negotiation.  */
3747         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3748
3749         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3750         if (flowctrl & ADVERTISE_1000XPAUSE)
3751                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3752         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3753                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3754
3755         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3756                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3757                     tp->serdes_counter &&
3758                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3759                                     MAC_STATUS_RCVD_CFG)) ==
3760                      MAC_STATUS_PCS_SYNCED)) {
3761                         tp->serdes_counter--;
3762                         current_link_up = 1;
3763                         goto out;
3764                 }
3765 restart_autoneg:
3766                 if (workaround)
3767                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3768                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3769                 udelay(5);
3770                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3771
3772                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3773                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3774         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3775                                  MAC_STATUS_SIGNAL_DET)) {
3776                 sg_dig_status = tr32(SG_DIG_STATUS);
3777                 mac_status = tr32(MAC_STATUS);
3778
3779                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3780                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3781                         u32 local_adv = 0, remote_adv = 0;
3782
3783                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3784                                 local_adv |= ADVERTISE_1000XPAUSE;
3785                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3786                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3787
3788                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3789                                 remote_adv |= LPA_1000XPAUSE;
3790                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3791                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3792
3793                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3794                         current_link_up = 1;
3795                         tp->serdes_counter = 0;
3796                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3797                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3798                         if (tp->serdes_counter)
3799                                 tp->serdes_counter--;
3800                         else {
3801                                 if (workaround) {
3802                                         u32 val = serdes_cfg;
3803
3804                                         if (port_a)
3805                                                 val |= 0xc010000;
3806                                         else
3807                                                 val |= 0x4010000;
3808
3809                                         tw32_f(MAC_SERDES_CFG, val);
3810                                 }
3811
3812                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3813                                 udelay(40);
3814
3815                                 /* Link parallel detection - link is up */
3816                                 /* only if we have PCS_SYNC and not */
3817                                 /* receiving config code words */
3818                                 mac_status = tr32(MAC_STATUS);
3819                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3820                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3821                                         tg3_setup_flow_control(tp, 0, 0);
3822                                         current_link_up = 1;
3823                                         tp->tg3_flags2 |=
3824                                                 TG3_FLG2_PARALLEL_DETECT;
3825                                         tp->serdes_counter =
3826                                                 SERDES_PARALLEL_DET_TIMEOUT;
3827                                 } else
3828                                         goto restart_autoneg;
3829                         }
3830                 }
3831         } else {
3832                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3833                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3834         }
3835
3836 out:
3837         return current_link_up;
3838 }
3839
3840 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3841 {
3842         int current_link_up = 0;
3843
3844         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3845                 goto out;
3846
3847         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3848                 u32 txflags, rxflags;
3849                 int i;
3850
3851                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3852                         u32 local_adv = 0, remote_adv = 0;
3853
3854                         if (txflags & ANEG_CFG_PS1)
3855                                 local_adv |= ADVERTISE_1000XPAUSE;
3856                         if (txflags & ANEG_CFG_PS2)
3857                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3858
3859                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3860                                 remote_adv |= LPA_1000XPAUSE;
3861                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3862                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3863
3864                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3865
3866                         current_link_up = 1;
3867                 }
3868                 for (i = 0; i < 30; i++) {
3869                         udelay(20);
3870                         tw32_f(MAC_STATUS,
3871                                (MAC_STATUS_SYNC_CHANGED |
3872                                 MAC_STATUS_CFG_CHANGED));
3873                         udelay(40);
3874                         if ((tr32(MAC_STATUS) &
3875                              (MAC_STATUS_SYNC_CHANGED |
3876                               MAC_STATUS_CFG_CHANGED)) == 0)
3877                                 break;
3878                 }
3879
3880                 mac_status = tr32(MAC_STATUS);
3881                 if (current_link_up == 0 &&
3882                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3883                     !(mac_status & MAC_STATUS_RCVD_CFG))
3884                         current_link_up = 1;
3885         } else {
3886                 tg3_setup_flow_control(tp, 0, 0);
3887
3888                 /* Forcing 1000FD link up. */
3889                 current_link_up = 1;
3890
3891                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3892                 udelay(40);
3893
3894                 tw32_f(MAC_MODE, tp->mac_mode);
3895                 udelay(40);
3896         }
3897
3898 out:
3899         return current_link_up;
3900 }
3901
3902 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3903 {
3904         u32 orig_pause_cfg;
3905         u16 orig_active_speed;
3906         u8 orig_active_duplex;
3907         u32 mac_status;
3908         int current_link_up;
3909         int i;
3910
3911         orig_pause_cfg = tp->link_config.active_flowctrl;
3912         orig_active_speed = tp->link_config.active_speed;
3913         orig_active_duplex = tp->link_config.active_duplex;
3914
3915         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3916             netif_carrier_ok(tp->dev) &&
3917             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3918                 mac_status = tr32(MAC_STATUS);
3919                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3920                                MAC_STATUS_SIGNAL_DET |
3921                                MAC_STATUS_CFG_CHANGED |
3922                                MAC_STATUS_RCVD_CFG);
3923                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3924                                    MAC_STATUS_SIGNAL_DET)) {
3925                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3926                                             MAC_STATUS_CFG_CHANGED));
3927                         return 0;
3928                 }
3929         }
3930
3931         tw32_f(MAC_TX_AUTO_NEG, 0);
3932
3933         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3934         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3935         tw32_f(MAC_MODE, tp->mac_mode);
3936         udelay(40);
3937
3938         if (tp->phy_id == PHY_ID_BCM8002)
3939                 tg3_init_bcm8002(tp);
3940
3941         /* Enable link change event even when serdes polling.  */
3942         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3943         udelay(40);
3944
3945         current_link_up = 0;
3946         mac_status = tr32(MAC_STATUS);
3947
3948         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3949                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3950         else
3951                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3952
3953         tp->napi[0].hw_status->status =
3954                 (SD_STATUS_UPDATED |
3955                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3956
3957         for (i = 0; i < 100; i++) {
3958                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3959                                     MAC_STATUS_CFG_CHANGED));
3960                 udelay(5);
3961                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3962                                          MAC_STATUS_CFG_CHANGED |
3963                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3964                         break;
3965         }
3966
3967         mac_status = tr32(MAC_STATUS);
3968         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3969                 current_link_up = 0;
3970                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3971                     tp->serdes_counter == 0) {
3972                         tw32_f(MAC_MODE, (tp->mac_mode |
3973                                           MAC_MODE_SEND_CONFIGS));
3974                         udelay(1);
3975                         tw32_f(MAC_MODE, tp->mac_mode);
3976                 }
3977         }
3978
3979         if (current_link_up == 1) {
3980                 tp->link_config.active_speed = SPEED_1000;
3981                 tp->link_config.active_duplex = DUPLEX_FULL;
3982                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3983                                     LED_CTRL_LNKLED_OVERRIDE |
3984                                     LED_CTRL_1000MBPS_ON));
3985         } else {
3986                 tp->link_config.active_speed = SPEED_INVALID;
3987                 tp->link_config.active_duplex = DUPLEX_INVALID;
3988                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3989                                     LED_CTRL_LNKLED_OVERRIDE |
3990                                     LED_CTRL_TRAFFIC_OVERRIDE));
3991         }
3992
3993         if (current_link_up != netif_carrier_ok(tp->dev)) {
3994                 if (current_link_up)
3995                         netif_carrier_on(tp->dev);
3996                 else
3997                         netif_carrier_off(tp->dev);
3998                 tg3_link_report(tp);
3999         } else {
4000                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4001                 if (orig_pause_cfg != now_pause_cfg ||
4002                     orig_active_speed != tp->link_config.active_speed ||
4003                     orig_active_duplex != tp->link_config.active_duplex)
4004                         tg3_link_report(tp);
4005         }
4006
4007         return 0;
4008 }
4009
4010 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4011 {
4012         int current_link_up, err = 0;
4013         u32 bmsr, bmcr;
4014         u16 current_speed;
4015         u8 current_duplex;
4016         u32 local_adv, remote_adv;
4017
4018         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4019         tw32_f(MAC_MODE, tp->mac_mode);
4020         udelay(40);
4021
4022         tw32(MAC_EVENT, 0);
4023
4024         tw32_f(MAC_STATUS,
4025              (MAC_STATUS_SYNC_CHANGED |
4026               MAC_STATUS_CFG_CHANGED |
4027               MAC_STATUS_MI_COMPLETION |
4028               MAC_STATUS_LNKSTATE_CHANGED));
4029         udelay(40);
4030
4031         if (force_reset)
4032                 tg3_phy_reset(tp);
4033
4034         current_link_up = 0;
4035         current_speed = SPEED_INVALID;
4036         current_duplex = DUPLEX_INVALID;
4037
4038         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4039         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4040         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4041                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4042                         bmsr |= BMSR_LSTATUS;
4043                 else
4044                         bmsr &= ~BMSR_LSTATUS;
4045         }
4046
4047         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4048
4049         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4050             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4051                 /* do nothing, just check for link up at the end */
4052         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4053                 u32 adv, new_adv;
4054
4055                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4056                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4057                                   ADVERTISE_1000XPAUSE |
4058                                   ADVERTISE_1000XPSE_ASYM |
4059                                   ADVERTISE_SLCT);
4060
4061                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4062
4063                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4064                         new_adv |= ADVERTISE_1000XHALF;
4065                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4066                         new_adv |= ADVERTISE_1000XFULL;
4067
4068                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4069                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4070                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4071                         tg3_writephy(tp, MII_BMCR, bmcr);
4072
4073                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4074                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4075                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4076
4077                         return err;
4078                 }
4079         } else {
4080                 u32 new_bmcr;
4081
4082                 bmcr &= ~BMCR_SPEED1000;
4083                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4084
4085                 if (tp->link_config.duplex == DUPLEX_FULL)
4086                         new_bmcr |= BMCR_FULLDPLX;
4087
4088                 if (new_bmcr != bmcr) {
4089                         /* BMCR_SPEED1000 is a reserved bit that needs
4090                          * to be set on write.
4091                          */
4092                         new_bmcr |= BMCR_SPEED1000;
4093
4094                         /* Force a linkdown */
4095                         if (netif_carrier_ok(tp->dev)) {
4096                                 u32 adv;
4097
4098                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4099                                 adv &= ~(ADVERTISE_1000XFULL |
4100                                          ADVERTISE_1000XHALF |
4101                                          ADVERTISE_SLCT);
4102                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4103                                 tg3_writephy(tp, MII_BMCR, bmcr |
4104                                                            BMCR_ANRESTART |
4105                                                            BMCR_ANENABLE);
4106                                 udelay(10);
4107                                 netif_carrier_off(tp->dev);
4108                         }
4109                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4110                         bmcr = new_bmcr;
4111                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4112                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4113                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4114                             ASIC_REV_5714) {
4115                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4116                                         bmsr |= BMSR_LSTATUS;
4117                                 else
4118                                         bmsr &= ~BMSR_LSTATUS;
4119                         }
4120                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4121                 }
4122         }
4123
4124         if (bmsr & BMSR_LSTATUS) {
4125                 current_speed = SPEED_1000;
4126                 current_link_up = 1;
4127                 if (bmcr & BMCR_FULLDPLX)
4128                         current_duplex = DUPLEX_FULL;
4129                 else
4130                         current_duplex = DUPLEX_HALF;
4131
4132                 local_adv = 0;
4133                 remote_adv = 0;
4134
4135                 if (bmcr & BMCR_ANENABLE) {
4136                         u32 common;
4137
4138                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4139                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4140                         common = local_adv & remote_adv;
4141                         if (common & (ADVERTISE_1000XHALF |
4142                                       ADVERTISE_1000XFULL)) {
4143                                 if (common & ADVERTISE_1000XFULL)
4144                                         current_duplex = DUPLEX_FULL;
4145                                 else
4146                                         current_duplex = DUPLEX_HALF;
4147                         }
4148                         else
4149                                 current_link_up = 0;
4150                 }
4151         }
4152
4153         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4154                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4155
4156         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4157         if (tp->link_config.active_duplex == DUPLEX_HALF)
4158                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4159
4160         tw32_f(MAC_MODE, tp->mac_mode);
4161         udelay(40);
4162
4163         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4164
4165         tp->link_config.active_speed = current_speed;
4166         tp->link_config.active_duplex = current_duplex;
4167
4168         if (current_link_up != netif_carrier_ok(tp->dev)) {
4169                 if (current_link_up)
4170                         netif_carrier_on(tp->dev);
4171                 else {
4172                         netif_carrier_off(tp->dev);
4173                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4174                 }
4175                 tg3_link_report(tp);
4176         }
4177         return err;
4178 }
4179
4180 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4181 {
4182         if (tp->serdes_counter) {
4183                 /* Give autoneg time to complete. */
4184                 tp->serdes_counter--;
4185                 return;
4186         }
4187         if (!netif_carrier_ok(tp->dev) &&
4188             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4189                 u32 bmcr;
4190
4191                 tg3_readphy(tp, MII_BMCR, &bmcr);
4192                 if (bmcr & BMCR_ANENABLE) {
4193                         u32 phy1, phy2;
4194
4195                         /* Select shadow register 0x1f */
4196                         tg3_writephy(tp, 0x1c, 0x7c00);
4197                         tg3_readphy(tp, 0x1c, &phy1);
4198
4199                         /* Select expansion interrupt status register */
4200                         tg3_writephy(tp, 0x17, 0x0f01);
4201                         tg3_readphy(tp, 0x15, &phy2);
4202                         tg3_readphy(tp, 0x15, &phy2);
4203
4204                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4205                                 /* We have signal detect and not receiving
4206                                  * config code words, link is up by parallel
4207                                  * detection.
4208                                  */
4209
4210                                 bmcr &= ~BMCR_ANENABLE;
4211                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4212                                 tg3_writephy(tp, MII_BMCR, bmcr);
4213                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4214                         }
4215                 }
4216         }
4217         else if (netif_carrier_ok(tp->dev) &&
4218                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4219                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4220                 u32 phy2;
4221
4222                 /* Select expansion interrupt status register */
4223                 tg3_writephy(tp, 0x17, 0x0f01);
4224                 tg3_readphy(tp, 0x15, &phy2);
4225                 if (phy2 & 0x20) {
4226                         u32 bmcr;
4227
4228                         /* Config code words received, turn on autoneg. */
4229                         tg3_readphy(tp, MII_BMCR, &bmcr);
4230                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4231
4232                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4233
4234                 }
4235         }
4236 }
4237
4238 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4239 {
4240         int err;
4241
4242         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4243                 err = tg3_setup_fiber_phy(tp, force_reset);
4244         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4245                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4246         } else {
4247                 err = tg3_setup_copper_phy(tp, force_reset);
4248         }
4249
4250         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4251                 u32 val, scale;
4252
4253                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4254                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4255                         scale = 65;
4256                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4257                         scale = 6;
4258                 else
4259                         scale = 12;
4260
4261                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4262                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4263                 tw32(GRC_MISC_CFG, val);
4264         }
4265
4266         if (tp->link_config.active_speed == SPEED_1000 &&
4267             tp->link_config.active_duplex == DUPLEX_HALF)
4268                 tw32(MAC_TX_LENGTHS,
4269                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4270                       (6 << TX_LENGTHS_IPG_SHIFT) |
4271                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4272         else
4273                 tw32(MAC_TX_LENGTHS,
4274                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275                       (6 << TX_LENGTHS_IPG_SHIFT) |
4276                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277
4278         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4279                 if (netif_carrier_ok(tp->dev)) {
4280                         tw32(HOSTCC_STAT_COAL_TICKS,
4281                              tp->coal.stats_block_coalesce_usecs);
4282                 } else {
4283                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4284                 }
4285         }
4286
4287         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4288                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4289                 if (!netif_carrier_ok(tp->dev))
4290                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4291                               tp->pwrmgmt_thresh;
4292                 else
4293                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4294                 tw32(PCIE_PWR_MGMT_THRESH, val);
4295         }
4296
4297         return err;
4298 }
4299
4300 /* This is called whenever we suspect that the system chipset is re-
4301  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4302  * is bogus tx completions. We try to recover by setting the
4303  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4304  * in the workqueue.
4305  */
4306 static void tg3_tx_recover(struct tg3 *tp)
4307 {
4308         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4309                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4310
4311         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4312                "mapped I/O cycles to the network device, attempting to "
4313                "recover. Please report the problem to the driver maintainer "
4314                "and include system chipset information.\n", tp->dev->name);
4315
4316         spin_lock(&tp->lock);
4317         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4318         spin_unlock(&tp->lock);
4319 }
4320
4321 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4322 {
4323         smp_mb();
4324         return tnapi->tx_pending -
4325                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4326 }
4327
4328 /* Tigon3 never reports partial packet sends.  So we do not
4329  * need special logic to handle SKBs that have not had all
4330  * of their frags sent yet, like SunGEM does.
4331  */
4332 static void tg3_tx(struct tg3_napi *tnapi)
4333 {
4334         struct tg3 *tp = tnapi->tp;
4335         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4336         u32 sw_idx = tnapi->tx_cons;
4337         struct netdev_queue *txq;
4338         int index = tnapi - tp->napi;
4339
4340         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4341                 index--;
4342
4343         txq = netdev_get_tx_queue(tp->dev, index);
4344
4345         while (sw_idx != hw_idx) {
4346                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4347                 struct sk_buff *skb = ri->skb;
4348                 int i, tx_bug = 0;
4349
4350                 if (unlikely(skb == NULL)) {
4351                         tg3_tx_recover(tp);
4352                         return;
4353                 }
4354
4355                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4356
4357                 ri->skb = NULL;
4358
4359                 sw_idx = NEXT_TX(sw_idx);
4360
4361                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4362                         ri = &tnapi->tx_buffers[sw_idx];
4363                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4364                                 tx_bug = 1;
4365                         sw_idx = NEXT_TX(sw_idx);
4366                 }
4367
4368                 dev_kfree_skb(skb);
4369
4370                 if (unlikely(tx_bug)) {
4371                         tg3_tx_recover(tp);
4372                         return;
4373                 }
4374         }
4375
4376         tnapi->tx_cons = sw_idx;
4377
4378         /* Need to make the tx_cons update visible to tg3_start_xmit()
4379          * before checking for netif_queue_stopped().  Without the
4380          * memory barrier, there is a small possibility that tg3_start_xmit()
4381          * will miss it and cause the queue to be stopped forever.
4382          */
4383         smp_mb();
4384
4385         if (unlikely(netif_tx_queue_stopped(txq) &&
4386                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4387                 __netif_tx_lock(txq, smp_processor_id());
4388                 if (netif_tx_queue_stopped(txq) &&
4389                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4390                         netif_tx_wake_queue(txq);
4391                 __netif_tx_unlock(txq);
4392         }
4393 }
4394
4395 /* Returns size of skb allocated or < 0 on error.
4396  *
4397  * We only need to fill in the address because the other members
4398  * of the RX descriptor are invariant, see tg3_init_rings.
4399  *
4400  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4401  * posting buffers we only dirty the first cache line of the RX
4402  * descriptor (containing the address).  Whereas for the RX status
4403  * buffers the cpu only reads the last cacheline of the RX descriptor
4404  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4405  */
4406 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4407                             int src_idx, u32 dest_idx_unmasked)
4408 {
4409         struct tg3 *tp = tnapi->tp;
4410         struct tg3_rx_buffer_desc *desc;
4411         struct ring_info *map, *src_map;
4412         struct sk_buff *skb;
4413         dma_addr_t mapping;
4414         int skb_size, dest_idx;
4415         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4416
4417         src_map = NULL;
4418         switch (opaque_key) {
4419         case RXD_OPAQUE_RING_STD:
4420                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4421                 desc = &tpr->rx_std[dest_idx];
4422                 map = &tpr->rx_std_buffers[dest_idx];
4423                 if (src_idx >= 0)
4424                         src_map = &tpr->rx_std_buffers[src_idx];
4425                 skb_size = tp->rx_pkt_map_sz;
4426                 break;
4427
4428         case RXD_OPAQUE_RING_JUMBO:
4429                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4430                 desc = &tpr->rx_jmb[dest_idx].std;
4431                 map = &tpr->rx_jmb_buffers[dest_idx];
4432                 if (src_idx >= 0)
4433                         src_map = &tpr->rx_jmb_buffers[src_idx];
4434                 skb_size = TG3_RX_JMB_MAP_SZ;
4435                 break;
4436
4437         default:
4438                 return -EINVAL;
4439         }
4440
4441         /* Do not overwrite any of the map or rp information
4442          * until we are sure we can commit to a new buffer.
4443          *
4444          * Callers depend upon this behavior and assume that
4445          * we leave everything unchanged if we fail.
4446          */
4447         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4448         if (skb == NULL)
4449                 return -ENOMEM;
4450
4451         skb_reserve(skb, tp->rx_offset);
4452
4453         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4454                                  PCI_DMA_FROMDEVICE);
4455         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4456                 dev_kfree_skb(skb);
4457                 return -EIO;
4458         }
4459
4460         map->skb = skb;
4461         pci_unmap_addr_set(map, mapping, mapping);
4462
4463         if (src_map != NULL)
4464                 src_map->skb = NULL;
4465
4466         desc->addr_hi = ((u64)mapping >> 32);
4467         desc->addr_lo = ((u64)mapping & 0xffffffff);
4468
4469         return skb_size;
4470 }
4471
4472 /* We only need to move over in the address because the other
4473  * members of the RX descriptor are invariant.  See notes above
4474  * tg3_alloc_rx_skb for full details.
4475  */
4476 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4477                            int src_idx, u32 dest_idx_unmasked)
4478 {
4479         struct tg3 *tp = tnapi->tp;
4480         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4481         struct ring_info *src_map, *dest_map;
4482         int dest_idx;
4483         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4484
4485         switch (opaque_key) {
4486         case RXD_OPAQUE_RING_STD:
4487                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4488                 dest_desc = &tpr->rx_std[dest_idx];
4489                 dest_map = &tpr->rx_std_buffers[dest_idx];
4490                 src_desc = &tpr->rx_std[src_idx];
4491                 src_map = &tpr->rx_std_buffers[src_idx];
4492                 break;
4493
4494         case RXD_OPAQUE_RING_JUMBO:
4495                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4496                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4497                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4498                 src_desc = &tpr->rx_jmb[src_idx].std;
4499                 src_map = &tpr->rx_jmb_buffers[src_idx];
4500                 break;
4501
4502         default:
4503                 return;
4504         }
4505
4506         dest_map->skb = src_map->skb;
4507         pci_unmap_addr_set(dest_map, mapping,
4508                            pci_unmap_addr(src_map, mapping));
4509         dest_desc->addr_hi = src_desc->addr_hi;
4510         dest_desc->addr_lo = src_desc->addr_lo;
4511
4512         src_map->skb = NULL;
4513 }
4514
4515 /* The RX ring scheme is composed of multiple rings which post fresh
4516  * buffers to the chip, and one special ring the chip uses to report
4517  * status back to the host.
4518  *
4519  * The special ring reports the status of received packets to the
4520  * host.  The chip does not write into the original descriptor the
4521  * RX buffer was obtained from.  The chip simply takes the original
4522  * descriptor as provided by the host, updates the status and length
4523  * field, then writes this into the next status ring entry.
4524  *
4525  * Each ring the host uses to post buffers to the chip is described
4526  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4527  * it is first placed into the on-chip ram.  When the packet's length
4528  * is known, it walks down the TG3_BDINFO entries to select the ring.
4529  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4530  * which is within the range of the new packet's length is chosen.
4531  *
4532  * The "separate ring for rx status" scheme may sound queer, but it makes
4533  * sense from a cache coherency perspective.  If only the host writes
4534  * to the buffer post rings, and only the chip writes to the rx status
4535  * rings, then cache lines never move beyond shared-modified state.
4536  * If both the host and chip were to write into the same ring, cache line
4537  * eviction could occur since both entities want it in an exclusive state.
4538  */
4539 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4540 {
4541         struct tg3 *tp = tnapi->tp;
4542         u32 work_mask, rx_std_posted = 0;
4543         u32 sw_idx = tnapi->rx_rcb_ptr;
4544         u16 hw_idx;
4545         int received;
4546         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4547
4548         hw_idx = *(tnapi->rx_rcb_prod_idx);
4549         /*
4550          * We need to order the read of hw_idx and the read of
4551          * the opaque cookie.
4552          */
4553         rmb();
4554         work_mask = 0;
4555         received = 0;
4556         while (sw_idx != hw_idx && budget > 0) {
4557                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4558                 unsigned int len;
4559                 struct sk_buff *skb;
4560                 dma_addr_t dma_addr;
4561                 u32 opaque_key, desc_idx, *post_ptr;
4562
4563                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4564                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4565                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4566                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4567                         dma_addr = pci_unmap_addr(ri, mapping);
4568                         skb = ri->skb;
4569                         post_ptr = &tpr->rx_std_ptr;
4570                         rx_std_posted++;
4571                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4572                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4573                         dma_addr = pci_unmap_addr(ri, mapping);
4574                         skb = ri->skb;
4575                         post_ptr = &tpr->rx_jmb_ptr;
4576                 } else
4577                         goto next_pkt_nopost;
4578
4579                 work_mask |= opaque_key;
4580
4581                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4582                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4583                 drop_it:
4584                         tg3_recycle_rx(tnapi, opaque_key,
4585                                        desc_idx, *post_ptr);
4586                 drop_it_no_recycle:
4587                         /* Other statistics kept track of by card. */
4588                         tp->net_stats.rx_dropped++;
4589                         goto next_pkt;
4590                 }
4591
4592                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4593                       ETH_FCS_LEN;
4594
4595                 if (len > RX_COPY_THRESHOLD
4596                         && tp->rx_offset == NET_IP_ALIGN
4597                         /* rx_offset will likely not equal NET_IP_ALIGN
4598                          * if this is a 5701 card running in PCI-X mode
4599                          * [see tg3_get_invariants()]
4600                          */
4601                 ) {
4602                         int skb_size;
4603
4604                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4605                                                     desc_idx, *post_ptr);
4606                         if (skb_size < 0)
4607                                 goto drop_it;
4608
4609                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4610                                          PCI_DMA_FROMDEVICE);
4611
4612                         skb_put(skb, len);
4613                 } else {
4614                         struct sk_buff *copy_skb;
4615
4616                         tg3_recycle_rx(tnapi, opaque_key,
4617                                        desc_idx, *post_ptr);
4618
4619                         copy_skb = netdev_alloc_skb(tp->dev,
4620                                                     len + TG3_RAW_IP_ALIGN);
4621                         if (copy_skb == NULL)
4622                                 goto drop_it_no_recycle;
4623
4624                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4625                         skb_put(copy_skb, len);
4626                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4627                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4628                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4629
4630                         /* We'll reuse the original ring buffer. */
4631                         skb = copy_skb;
4632                 }
4633
4634                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4635                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4636                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4637                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4638                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4639                 else
4640                         skb->ip_summed = CHECKSUM_NONE;
4641
4642                 skb->protocol = eth_type_trans(skb, tp->dev);
4643
4644                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4645                     skb->protocol != htons(ETH_P_8021Q)) {
4646                         dev_kfree_skb(skb);
4647                         goto next_pkt;
4648                 }
4649
4650 #if TG3_VLAN_TAG_USED
4651                 if (tp->vlgrp != NULL &&
4652                     desc->type_flags & RXD_FLAG_VLAN) {
4653                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4654                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4655                 } else
4656 #endif
4657                         napi_gro_receive(&tnapi->napi, skb);
4658
4659                 received++;
4660                 budget--;
4661
4662 next_pkt:
4663                 (*post_ptr)++;
4664
4665                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4666                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4667
4668                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4669                                      TG3_64BIT_REG_LOW, idx);
4670                         work_mask &= ~RXD_OPAQUE_RING_STD;
4671                         rx_std_posted = 0;
4672                 }
4673 next_pkt_nopost:
4674                 sw_idx++;
4675                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4676
4677                 /* Refresh hw_idx to see if there is new work */
4678                 if (sw_idx == hw_idx) {
4679                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4680                         rmb();
4681                 }
4682         }
4683
4684         /* ACK the status ring. */
4685         tnapi->rx_rcb_ptr = sw_idx;
4686         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4687
4688         /* Refill RX ring(s). */
4689         if (work_mask & RXD_OPAQUE_RING_STD) {
4690                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4691                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4692                              sw_idx);
4693         }
4694         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4695                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4696                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4697                              sw_idx);
4698         }
4699         mmiowb();
4700
4701         return received;
4702 }
4703
4704 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4705 {
4706         struct tg3 *tp = tnapi->tp;
4707         struct tg3_hw_status *sblk = tnapi->hw_status;
4708
4709         /* handle link change and other phy events */
4710         if (!(tp->tg3_flags &
4711               (TG3_FLAG_USE_LINKCHG_REG |
4712                TG3_FLAG_POLL_SERDES))) {
4713                 if (sblk->status & SD_STATUS_LINK_CHG) {
4714                         sblk->status = SD_STATUS_UPDATED |
4715                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4716                         spin_lock(&tp->lock);
4717                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4718                                 tw32_f(MAC_STATUS,
4719                                      (MAC_STATUS_SYNC_CHANGED |
4720                                       MAC_STATUS_CFG_CHANGED |
4721                                       MAC_STATUS_MI_COMPLETION |
4722                                       MAC_STATUS_LNKSTATE_CHANGED));
4723                                 udelay(40);
4724                         } else
4725                                 tg3_setup_phy(tp, 0);
4726                         spin_unlock(&tp->lock);
4727                 }
4728         }
4729
4730         /* run TX completion thread */
4731         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4732                 tg3_tx(tnapi);
4733                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4734                         return work_done;
4735         }
4736
4737         /* run RX thread, within the bounds set by NAPI.
4738          * All RX "locking" is done by ensuring outside
4739          * code synchronizes with tg3->napi.poll()
4740          */
4741         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4742                 work_done += tg3_rx(tnapi, budget - work_done);
4743
4744         return work_done;
4745 }
4746
4747 static int tg3_poll(struct napi_struct *napi, int budget)
4748 {
4749         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4750         struct tg3 *tp = tnapi->tp;
4751         int work_done = 0;
4752         struct tg3_hw_status *sblk = tnapi->hw_status;
4753
4754         while (1) {
4755                 work_done = tg3_poll_work(tnapi, work_done, budget);
4756
4757                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4758                         goto tx_recovery;
4759
4760                 if (unlikely(work_done >= budget))
4761                         break;
4762
4763                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4764                         /* tp->last_tag is used in tg3_int_reenable() below
4765                          * to tell the hw how much work has been processed,
4766                          * so we must read it before checking for more work.
4767                          */
4768                         tnapi->last_tag = sblk->status_tag;
4769                         tnapi->last_irq_tag = tnapi->last_tag;
4770                         rmb();
4771                 } else
4772                         sblk->status &= ~SD_STATUS_UPDATED;
4773
4774                 if (likely(!tg3_has_work(tnapi))) {
4775                         napi_complete(napi);
4776                         tg3_int_reenable(tnapi);
4777                         break;
4778                 }
4779         }
4780
4781         return work_done;
4782
4783 tx_recovery:
4784         /* work_done is guaranteed to be less than budget. */
4785         napi_complete(napi);
4786         schedule_work(&tp->reset_task);
4787         return work_done;
4788 }
4789
4790 static void tg3_irq_quiesce(struct tg3 *tp)
4791 {
4792         int i;
4793
4794         BUG_ON(tp->irq_sync);
4795
4796         tp->irq_sync = 1;
4797         smp_mb();
4798
4799         for (i = 0; i < tp->irq_cnt; i++)
4800                 synchronize_irq(tp->napi[i].irq_vec);
4801 }
4802
4803 static inline int tg3_irq_sync(struct tg3 *tp)
4804 {
4805         return tp->irq_sync;
4806 }
4807
4808 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4809  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4810  * with as well.  Most of the time, this is not necessary except when
4811  * shutting down the device.
4812  */
4813 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4814 {
4815         spin_lock_bh(&tp->lock);
4816         if (irq_sync)
4817                 tg3_irq_quiesce(tp);
4818 }
4819
4820 static inline void tg3_full_unlock(struct tg3 *tp)
4821 {
4822         spin_unlock_bh(&tp->lock);
4823 }
4824
4825 /* One-shot MSI handler - Chip automatically disables interrupt
4826  * after sending MSI so driver doesn't have to do it.
4827  */
4828 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4829 {
4830         struct tg3_napi *tnapi = dev_id;
4831         struct tg3 *tp = tnapi->tp;
4832
4833         prefetch(tnapi->hw_status);
4834         if (tnapi->rx_rcb)
4835                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4836
4837         if (likely(!tg3_irq_sync(tp)))
4838                 napi_schedule(&tnapi->napi);
4839
4840         return IRQ_HANDLED;
4841 }
4842
4843 /* MSI ISR - No need to check for interrupt sharing and no need to
4844  * flush status block and interrupt mailbox. PCI ordering rules
4845  * guarantee that MSI will arrive after the status block.
4846  */
4847 static irqreturn_t tg3_msi(int irq, void *dev_id)
4848 {
4849         struct tg3_napi *tnapi = dev_id;
4850         struct tg3 *tp = tnapi->tp;
4851
4852         prefetch(tnapi->hw_status);
4853         if (tnapi->rx_rcb)
4854                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4855         /*
4856          * Writing any value to intr-mbox-0 clears PCI INTA# and
4857          * chip-internal interrupt pending events.
4858          * Writing non-zero to intr-mbox-0 additional tells the
4859          * NIC to stop sending us irqs, engaging "in-intr-handler"
4860          * event coalescing.
4861          */
4862         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4863         if (likely(!tg3_irq_sync(tp)))
4864                 napi_schedule(&tnapi->napi);
4865
4866         return IRQ_RETVAL(1);
4867 }
4868
4869 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4870 {
4871         struct tg3_napi *tnapi = dev_id;
4872         struct tg3 *tp = tnapi->tp;
4873         struct tg3_hw_status *sblk = tnapi->hw_status;
4874         unsigned int handled = 1;
4875
4876         /* In INTx mode, it is possible for the interrupt to arrive at
4877          * the CPU before the status block posted prior to the interrupt.
4878          * Reading the PCI State register will confirm whether the
4879          * interrupt is ours and will flush the status block.
4880          */
4881         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4882                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4883                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4884                         handled = 0;
4885                         goto out;
4886                 }
4887         }
4888
4889         /*
4890          * Writing any value to intr-mbox-0 clears PCI INTA# and
4891          * chip-internal interrupt pending events.
4892          * Writing non-zero to intr-mbox-0 additional tells the
4893          * NIC to stop sending us irqs, engaging "in-intr-handler"
4894          * event coalescing.
4895          *
4896          * Flush the mailbox to de-assert the IRQ immediately to prevent
4897          * spurious interrupts.  The flush impacts performance but
4898          * excessive spurious interrupts can be worse in some cases.
4899          */
4900         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4901         if (tg3_irq_sync(tp))
4902                 goto out;
4903         sblk->status &= ~SD_STATUS_UPDATED;
4904         if (likely(tg3_has_work(tnapi))) {
4905                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4906                 napi_schedule(&tnapi->napi);
4907         } else {
4908                 /* No work, shared interrupt perhaps?  re-enable
4909                  * interrupts, and flush that PCI write
4910                  */
4911                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4912                                0x00000000);
4913         }
4914 out:
4915         return IRQ_RETVAL(handled);
4916 }
4917
4918 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4919 {
4920         struct tg3_napi *tnapi = dev_id;
4921         struct tg3 *tp = tnapi->tp;
4922         struct tg3_hw_status *sblk = tnapi->hw_status;
4923         unsigned int handled = 1;
4924
4925         /* In INTx mode, it is possible for the interrupt to arrive at
4926          * the CPU before the status block posted prior to the interrupt.
4927          * Reading the PCI State register will confirm whether the
4928          * interrupt is ours and will flush the status block.
4929          */
4930         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4931                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4932                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4933                         handled = 0;
4934                         goto out;
4935                 }
4936         }
4937
4938         /*
4939          * writing any value to intr-mbox-0 clears PCI INTA# and
4940          * chip-internal interrupt pending events.
4941          * writing non-zero to intr-mbox-0 additional tells the
4942          * NIC to stop sending us irqs, engaging "in-intr-handler"
4943          * event coalescing.
4944          *
4945          * Flush the mailbox to de-assert the IRQ immediately to prevent
4946          * spurious interrupts.  The flush impacts performance but
4947          * excessive spurious interrupts can be worse in some cases.
4948          */
4949         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4950
4951         /*
4952          * In a shared interrupt configuration, sometimes other devices'
4953          * interrupts will scream.  We record the current status tag here
4954          * so that the above check can report that the screaming interrupts
4955          * are unhandled.  Eventually they will be silenced.
4956          */
4957         tnapi->last_irq_tag = sblk->status_tag;
4958
4959         if (tg3_irq_sync(tp))
4960                 goto out;
4961
4962         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4963
4964         napi_schedule(&tnapi->napi);
4965
4966 out:
4967         return IRQ_RETVAL(handled);
4968 }
4969
4970 /* ISR for interrupt test */
4971 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4972 {
4973         struct tg3_napi *tnapi = dev_id;
4974         struct tg3 *tp = tnapi->tp;
4975         struct tg3_hw_status *sblk = tnapi->hw_status;
4976
4977         if ((sblk->status & SD_STATUS_UPDATED) ||
4978             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4979                 tg3_disable_ints(tp);
4980                 return IRQ_RETVAL(1);
4981         }
4982         return IRQ_RETVAL(0);
4983 }
4984
4985 static int tg3_init_hw(struct tg3 *, int);
4986 static int tg3_halt(struct tg3 *, int, int);
4987
4988 /* Restart hardware after configuration changes, self-test, etc.
4989  * Invoked with tp->lock held.
4990  */
4991 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4992         __releases(tp->lock)
4993         __acquires(tp->lock)
4994 {
4995         int err;
4996
4997         err = tg3_init_hw(tp, reset_phy);
4998         if (err) {
4999                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5000                        "aborting.\n", tp->dev->name);
5001                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5002                 tg3_full_unlock(tp);
5003                 del_timer_sync(&tp->timer);
5004                 tp->irq_sync = 0;
5005                 tg3_napi_enable(tp);
5006                 dev_close(tp->dev);
5007                 tg3_full_lock(tp, 0);
5008         }
5009         return err;
5010 }
5011
5012 #ifdef CONFIG_NET_POLL_CONTROLLER
5013 static void tg3_poll_controller(struct net_device *dev)
5014 {
5015         int i;
5016         struct tg3 *tp = netdev_priv(dev);
5017
5018         for (i = 0; i < tp->irq_cnt; i++)
5019                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5020 }
5021 #endif
5022
5023 static void tg3_reset_task(struct work_struct *work)
5024 {
5025         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5026         int err;
5027         unsigned int restart_timer;
5028
5029         tg3_full_lock(tp, 0);
5030
5031         if (!netif_running(tp->dev)) {
5032                 tg3_full_unlock(tp);
5033                 return;
5034         }
5035
5036         tg3_full_unlock(tp);
5037
5038         tg3_phy_stop(tp);
5039
5040         tg3_netif_stop(tp);
5041
5042         tg3_full_lock(tp, 1);
5043
5044         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5045         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5046
5047         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5048                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5049                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5050                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5051                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5052         }
5053
5054         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5055         err = tg3_init_hw(tp, 1);
5056         if (err)
5057                 goto out;
5058
5059         tg3_netif_start(tp);
5060
5061         if (restart_timer)
5062                 mod_timer(&tp->timer, jiffies + 1);
5063
5064 out:
5065         tg3_full_unlock(tp);
5066
5067         if (!err)
5068                 tg3_phy_start(tp);
5069 }
5070
5071 static void tg3_dump_short_state(struct tg3 *tp)
5072 {
5073         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5074                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5075         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5076                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5077 }
5078
5079 static void tg3_tx_timeout(struct net_device *dev)
5080 {
5081         struct tg3 *tp = netdev_priv(dev);
5082
5083         if (netif_msg_tx_err(tp)) {
5084                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5085                        dev->name);
5086                 tg3_dump_short_state(tp);
5087         }
5088
5089         schedule_work(&tp->reset_task);
5090 }
5091
5092 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5093 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5094 {
5095         u32 base = (u32) mapping & 0xffffffff;
5096
5097         return ((base > 0xffffdcc0) &&
5098                 (base + len + 8 < base));
5099 }
5100
5101 /* Test for DMA addresses > 40-bit */
5102 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5103                                           int len)
5104 {
5105 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5106         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5107                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5108         return 0;
5109 #else
5110         return 0;
5111 #endif
5112 }
5113
5114 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5115
5116 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5117 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5118                                        u32 last_plus_one, u32 *start,
5119                                        u32 base_flags, u32 mss)
5120 {
5121         struct tg3_napi *tnapi = &tp->napi[0];
5122         struct sk_buff *new_skb;
5123         dma_addr_t new_addr = 0;
5124         u32 entry = *start;
5125         int i, ret = 0;
5126
5127         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5128                 new_skb = skb_copy(skb, GFP_ATOMIC);
5129         else {
5130                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5131
5132                 new_skb = skb_copy_expand(skb,
5133                                           skb_headroom(skb) + more_headroom,
5134                                           skb_tailroom(skb), GFP_ATOMIC);
5135         }
5136
5137         if (!new_skb) {
5138                 ret = -1;
5139         } else {
5140                 /* New SKB is guaranteed to be linear. */
5141                 entry = *start;
5142                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5143                 new_addr = skb_shinfo(new_skb)->dma_head;
5144
5145                 /* Make sure new skb does not cross any 4G boundaries.
5146                  * Drop the packet if it does.
5147                  */
5148                 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5149                             tg3_4g_overflow_test(new_addr, new_skb->len))) {
5150                         if (!ret)
5151                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5152                                               DMA_TO_DEVICE);
5153                         ret = -1;
5154                         dev_kfree_skb(new_skb);
5155                         new_skb = NULL;
5156                 } else {
5157                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5158                                     base_flags, 1 | (mss << 1));
5159                         *start = NEXT_TX(entry);
5160                 }
5161         }
5162
5163         /* Now clean up the sw ring entries. */
5164         i = 0;
5165         while (entry != last_plus_one) {
5166                 if (i == 0)
5167                         tnapi->tx_buffers[entry].skb = new_skb;
5168                 else
5169                         tnapi->tx_buffers[entry].skb = NULL;
5170                 entry = NEXT_TX(entry);
5171                 i++;
5172         }
5173
5174         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5175         dev_kfree_skb(skb);
5176
5177         return ret;
5178 }
5179
5180 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5181                         dma_addr_t mapping, int len, u32 flags,
5182                         u32 mss_and_is_end)
5183 {
5184         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5185         int is_end = (mss_and_is_end & 0x1);
5186         u32 mss = (mss_and_is_end >> 1);
5187         u32 vlan_tag = 0;
5188
5189         if (is_end)
5190                 flags |= TXD_FLAG_END;
5191         if (flags & TXD_FLAG_VLAN) {
5192                 vlan_tag = flags >> 16;
5193                 flags &= 0xffff;
5194         }
5195         vlan_tag |= (mss << TXD_MSS_SHIFT);
5196
5197         txd->addr_hi = ((u64) mapping >> 32);
5198         txd->addr_lo = ((u64) mapping & 0xffffffff);
5199         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5200         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5201 }
5202
5203 /* hard_start_xmit for devices that don't have any bugs and
5204  * support TG3_FLG2_HW_TSO_2 only.
5205  */
5206 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5207                                   struct net_device *dev)
5208 {
5209         struct tg3 *tp = netdev_priv(dev);
5210         u32 len, entry, base_flags, mss;
5211         struct skb_shared_info *sp;
5212         dma_addr_t mapping;
5213         struct tg3_napi *tnapi;
5214         struct netdev_queue *txq;
5215
5216         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5217         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5218         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5219                 tnapi++;
5220
5221         /* We are running in BH disabled context with netif_tx_lock
5222          * and TX reclaim runs via tp->napi.poll inside of a software
5223          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5224          * no IRQ context deadlocks to worry about either.  Rejoice!
5225          */
5226         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5227                 if (!netif_tx_queue_stopped(txq)) {
5228                         netif_tx_stop_queue(txq);
5229
5230                         /* This is a hard error, log it. */
5231                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5232                                "queue awake!\n", dev->name);
5233                 }
5234                 return NETDEV_TX_BUSY;
5235         }
5236
5237         entry = tnapi->tx_prod;
5238         base_flags = 0;
5239         mss = 0;
5240         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5241                 int tcp_opt_len, ip_tcp_len;
5242                 u32 hdrlen;
5243
5244                 if (skb_header_cloned(skb) &&
5245                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5246                         dev_kfree_skb(skb);
5247                         goto out_unlock;
5248                 }
5249
5250                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5251                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5252                 else {
5253                         struct iphdr *iph = ip_hdr(skb);
5254
5255                         tcp_opt_len = tcp_optlen(skb);
5256                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5257
5258                         iph->check = 0;
5259                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5260                         hdrlen = ip_tcp_len + tcp_opt_len;
5261                 }
5262
5263                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5264                         mss |= (hdrlen & 0xc) << 12;
5265                         if (hdrlen & 0x10)
5266                                 base_flags |= 0x00000010;
5267                         base_flags |= (hdrlen & 0x3e0) << 5;
5268                 } else
5269                         mss |= hdrlen << 9;
5270
5271                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5272                                TXD_FLAG_CPU_POST_DMA);
5273
5274                 tcp_hdr(skb)->check = 0;
5275
5276         }
5277         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5278                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5279 #if TG3_VLAN_TAG_USED
5280         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5281                 base_flags |= (TXD_FLAG_VLAN |
5282                                (vlan_tx_tag_get(skb) << 16));
5283 #endif
5284
5285         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5286                 dev_kfree_skb(skb);
5287                 goto out_unlock;
5288         }
5289
5290         sp = skb_shinfo(skb);
5291
5292         mapping = sp->dma_head;
5293
5294         tnapi->tx_buffers[entry].skb = skb;
5295
5296         len = skb_headlen(skb);
5297
5298         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5299             !mss && skb->len > ETH_DATA_LEN)
5300                 base_flags |= TXD_FLAG_JMB_PKT;
5301
5302         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5303                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5304
5305         entry = NEXT_TX(entry);
5306
5307         /* Now loop through additional data fragments, and queue them. */
5308         if (skb_shinfo(skb)->nr_frags > 0) {
5309                 unsigned int i, last;
5310
5311                 last = skb_shinfo(skb)->nr_frags - 1;
5312                 for (i = 0; i <= last; i++) {
5313                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5314
5315                         len = frag->size;
5316                         mapping = sp->dma_maps[i];
5317                         tnapi->tx_buffers[entry].skb = NULL;
5318
5319                         tg3_set_txd(tnapi, entry, mapping, len,
5320                                     base_flags, (i == last) | (mss << 1));
5321
5322                         entry = NEXT_TX(entry);
5323                 }
5324         }
5325
5326         /* Packets are ready, update Tx producer idx local and on card. */
5327         tw32_tx_mbox(tnapi->prodmbox, entry);
5328
5329         tnapi->tx_prod = entry;
5330         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5331                 netif_tx_stop_queue(txq);
5332                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5333                         netif_tx_wake_queue(txq);
5334         }
5335
5336 out_unlock:
5337         mmiowb();
5338
5339         return NETDEV_TX_OK;
5340 }
5341
5342 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5343                                           struct net_device *);
5344
5345 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5346  * TSO header is greater than 80 bytes.
5347  */
5348 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5349 {
5350         struct sk_buff *segs, *nskb;
5351         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5352
5353         /* Estimate the number of fragments in the worst case */
5354         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5355                 netif_stop_queue(tp->dev);
5356                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5357                         return NETDEV_TX_BUSY;
5358
5359                 netif_wake_queue(tp->dev);
5360         }
5361
5362         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5363         if (IS_ERR(segs))
5364                 goto tg3_tso_bug_end;
5365
5366         do {
5367                 nskb = segs;
5368                 segs = segs->next;
5369                 nskb->next = NULL;
5370                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5371         } while (segs);
5372
5373 tg3_tso_bug_end:
5374         dev_kfree_skb(skb);
5375
5376         return NETDEV_TX_OK;
5377 }
5378
5379 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5380  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5381  */
5382 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5383                                           struct net_device *dev)
5384 {
5385         struct tg3 *tp = netdev_priv(dev);
5386         u32 len, entry, base_flags, mss;
5387         struct skb_shared_info *sp;
5388         int would_hit_hwbug;
5389         dma_addr_t mapping;
5390         struct tg3_napi *tnapi = &tp->napi[0];
5391
5392         len = skb_headlen(skb);
5393
5394         /* We are running in BH disabled context with netif_tx_lock
5395          * and TX reclaim runs via tp->napi.poll inside of a software
5396          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5397          * no IRQ context deadlocks to worry about either.  Rejoice!
5398          */
5399         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5400                 if (!netif_queue_stopped(dev)) {
5401                         netif_stop_queue(dev);
5402
5403                         /* This is a hard error, log it. */
5404                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5405                                "queue awake!\n", dev->name);
5406                 }
5407                 return NETDEV_TX_BUSY;
5408         }
5409
5410         entry = tnapi->tx_prod;
5411         base_flags = 0;
5412         if (skb->ip_summed == CHECKSUM_PARTIAL)
5413                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5414         mss = 0;
5415         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5416                 struct iphdr *iph;
5417                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5418
5419                 if (skb_header_cloned(skb) &&
5420                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5421                         dev_kfree_skb(skb);
5422                         goto out_unlock;
5423                 }
5424
5425                 tcp_opt_len = tcp_optlen(skb);
5426                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5427
5428                 hdr_len = ip_tcp_len + tcp_opt_len;
5429                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5430                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5431                         return (tg3_tso_bug(tp, skb));
5432
5433                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5434                                TXD_FLAG_CPU_POST_DMA);
5435
5436                 iph = ip_hdr(skb);
5437                 iph->check = 0;
5438                 iph->tot_len = htons(mss + hdr_len);
5439                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5440                         tcp_hdr(skb)->check = 0;
5441                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5442                 } else
5443                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5444                                                                  iph->daddr, 0,
5445                                                                  IPPROTO_TCP,
5446                                                                  0);
5447
5448                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5449                         mss |= hdr_len << 9;
5450                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5451                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5452                         if (tcp_opt_len || iph->ihl > 5) {
5453                                 int tsflags;
5454
5455                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5456                                 mss |= (tsflags << 11);
5457                         }
5458                 } else {
5459                         if (tcp_opt_len || iph->ihl > 5) {
5460                                 int tsflags;
5461
5462                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5463                                 base_flags |= tsflags << 12;
5464                         }
5465                 }
5466         }
5467 #if TG3_VLAN_TAG_USED
5468         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5469                 base_flags |= (TXD_FLAG_VLAN |
5470                                (vlan_tx_tag_get(skb) << 16));
5471 #endif
5472
5473         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5474                 dev_kfree_skb(skb);
5475                 goto out_unlock;
5476         }
5477
5478         sp = skb_shinfo(skb);
5479
5480         mapping = sp->dma_head;
5481
5482         tnapi->tx_buffers[entry].skb = skb;
5483
5484         would_hit_hwbug = 0;
5485
5486         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5487                 would_hit_hwbug = 1;
5488
5489         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5490             tg3_4g_overflow_test(mapping, len))
5491                 would_hit_hwbug = 1;
5492
5493         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5494             tg3_40bit_overflow_test(tp, mapping, len))
5495                 would_hit_hwbug = 1;
5496
5497         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5498                 would_hit_hwbug = 1;
5499
5500         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5501                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5502
5503         entry = NEXT_TX(entry);
5504
5505         /* Now loop through additional data fragments, and queue them. */
5506         if (skb_shinfo(skb)->nr_frags > 0) {
5507                 unsigned int i, last;
5508
5509                 last = skb_shinfo(skb)->nr_frags - 1;
5510                 for (i = 0; i <= last; i++) {
5511                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5512
5513                         len = frag->size;
5514                         mapping = sp->dma_maps[i];
5515
5516                         tnapi->tx_buffers[entry].skb = NULL;
5517
5518                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5519                             len <= 8)
5520                                 would_hit_hwbug = 1;
5521
5522                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5523                             tg3_4g_overflow_test(mapping, len))
5524                                 would_hit_hwbug = 1;
5525
5526                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5527                             tg3_40bit_overflow_test(tp, mapping, len))
5528                                 would_hit_hwbug = 1;
5529
5530                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5531                                 tg3_set_txd(tnapi, entry, mapping, len,
5532                                             base_flags, (i == last)|(mss << 1));
5533                         else
5534                                 tg3_set_txd(tnapi, entry, mapping, len,
5535                                             base_flags, (i == last));
5536
5537                         entry = NEXT_TX(entry);
5538                 }
5539         }
5540
5541         if (would_hit_hwbug) {
5542                 u32 last_plus_one = entry;
5543                 u32 start;
5544
5545                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5546                 start &= (TG3_TX_RING_SIZE - 1);
5547
5548                 /* If the workaround fails due to memory/mapping
5549                  * failure, silently drop this packet.
5550                  */
5551                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5552                                                 &start, base_flags, mss))
5553                         goto out_unlock;
5554
5555                 entry = start;
5556         }
5557
5558         /* Packets are ready, update Tx producer idx local and on card. */
5559         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5560
5561         tnapi->tx_prod = entry;
5562         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5563                 netif_stop_queue(dev);
5564                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5565                         netif_wake_queue(tp->dev);
5566         }
5567
5568 out_unlock:
5569         mmiowb();
5570
5571         return NETDEV_TX_OK;
5572 }
5573
5574 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5575                                int new_mtu)
5576 {
5577         dev->mtu = new_mtu;
5578
5579         if (new_mtu > ETH_DATA_LEN) {
5580                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5581                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5582                         ethtool_op_set_tso(dev, 0);
5583                 }
5584                 else
5585                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5586         } else {
5587                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5588                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5589                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5590         }
5591 }
5592
5593 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5594 {
5595         struct tg3 *tp = netdev_priv(dev);
5596         int err;
5597
5598         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5599                 return -EINVAL;
5600
5601         if (!netif_running(dev)) {
5602                 /* We'll just catch it later when the
5603                  * device is up'd.
5604                  */
5605                 tg3_set_mtu(dev, tp, new_mtu);
5606                 return 0;
5607         }
5608
5609         tg3_phy_stop(tp);
5610
5611         tg3_netif_stop(tp);
5612
5613         tg3_full_lock(tp, 1);
5614
5615         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5616
5617         tg3_set_mtu(dev, tp, new_mtu);
5618
5619         err = tg3_restart_hw(tp, 0);
5620
5621         if (!err)
5622                 tg3_netif_start(tp);
5623
5624         tg3_full_unlock(tp);
5625
5626         if (!err)
5627                 tg3_phy_start(tp);
5628
5629         return err;
5630 }
5631
5632 static void tg3_rx_prodring_free(struct tg3 *tp,
5633                                  struct tg3_rx_prodring_set *tpr)
5634 {
5635         int i;
5636         struct ring_info *rxp;
5637
5638         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5639                 rxp = &tpr->rx_std_buffers[i];
5640
5641                 if (rxp->skb == NULL)
5642                         continue;
5643
5644                 pci_unmap_single(tp->pdev,
5645                                  pci_unmap_addr(rxp, mapping),
5646                                  tp->rx_pkt_map_sz,
5647                                  PCI_DMA_FROMDEVICE);
5648                 dev_kfree_skb_any(rxp->skb);
5649                 rxp->skb = NULL;
5650         }
5651
5652         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5653                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5654                         rxp = &tpr->rx_jmb_buffers[i];
5655
5656                         if (rxp->skb == NULL)
5657                                 continue;
5658
5659                         pci_unmap_single(tp->pdev,
5660                                          pci_unmap_addr(rxp, mapping),
5661                                          TG3_RX_JMB_MAP_SZ,
5662                                          PCI_DMA_FROMDEVICE);
5663                         dev_kfree_skb_any(rxp->skb);
5664                         rxp->skb = NULL;
5665                 }
5666         }
5667 }
5668
5669 /* Initialize tx/rx rings for packet processing.
5670  *
5671  * The chip has been shut down and the driver detached from
5672  * the networking, so no interrupts or new tx packets will
5673  * end up in the driver.  tp->{tx,}lock are held and thus
5674  * we may not sleep.
5675  */
5676 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5677                                  struct tg3_rx_prodring_set *tpr)
5678 {
5679         u32 i, rx_pkt_dma_sz;
5680         struct tg3_napi *tnapi = &tp->napi[0];
5681
5682         /* Zero out all descriptors. */
5683         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5684
5685         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5686         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5687             tp->dev->mtu > ETH_DATA_LEN)
5688                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5689         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5690
5691         /* Initialize invariants of the rings, we only set this
5692          * stuff once.  This works because the card does not
5693          * write into the rx buffer posting rings.
5694          */
5695         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5696                 struct tg3_rx_buffer_desc *rxd;
5697
5698                 rxd = &tpr->rx_std[i];
5699                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5700                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5701                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5702                                (i << RXD_OPAQUE_INDEX_SHIFT));
5703         }
5704
5705         /* Now allocate fresh SKBs for each rx ring. */
5706         for (i = 0; i < tp->rx_pending; i++) {
5707                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5708                         printk(KERN_WARNING PFX
5709                                "%s: Using a smaller RX standard ring, "
5710                                "only %d out of %d buffers were allocated "
5711                                "successfully.\n",
5712                                tp->dev->name, i, tp->rx_pending);
5713                         if (i == 0)
5714                                 goto initfail;
5715                         tp->rx_pending = i;
5716                         break;
5717                 }
5718         }
5719
5720         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5721                 goto done;
5722
5723         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5724
5725         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5726                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5727                         struct tg3_rx_buffer_desc *rxd;
5728
5729                         rxd = &tpr->rx_jmb[i].std;
5730                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5731                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5732                                 RXD_FLAG_JUMBO;
5733                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5734                                (i << RXD_OPAQUE_INDEX_SHIFT));
5735                 }
5736
5737                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5738                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5739                                              -1, i) < 0) {
5740                                 printk(KERN_WARNING PFX
5741                                        "%s: Using a smaller RX jumbo ring, "
5742                                        "only %d out of %d buffers were "
5743                                        "allocated successfully.\n",
5744                                        tp->dev->name, i, tp->rx_jumbo_pending);
5745                                 if (i == 0)
5746                                         goto initfail;
5747                                 tp->rx_jumbo_pending = i;
5748                                 break;
5749                         }
5750                 }
5751         }
5752
5753 done:
5754         return 0;
5755
5756 initfail:
5757         tg3_rx_prodring_free(tp, tpr);
5758         return -ENOMEM;
5759 }
5760
5761 static void tg3_rx_prodring_fini(struct tg3 *tp,
5762                                  struct tg3_rx_prodring_set *tpr)
5763 {
5764         kfree(tpr->rx_std_buffers);
5765         tpr->rx_std_buffers = NULL;
5766         kfree(tpr->rx_jmb_buffers);
5767         tpr->rx_jmb_buffers = NULL;
5768         if (tpr->rx_std) {
5769                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5770                                     tpr->rx_std, tpr->rx_std_mapping);
5771                 tpr->rx_std = NULL;
5772         }
5773         if (tpr->rx_jmb) {
5774                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5775                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5776                 tpr->rx_jmb = NULL;
5777         }
5778 }
5779
5780 static int tg3_rx_prodring_init(struct tg3 *tp,
5781                                 struct tg3_rx_prodring_set *tpr)
5782 {
5783         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5784                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5785         if (!tpr->rx_std_buffers)
5786                 return -ENOMEM;
5787
5788         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5789                                            &tpr->rx_std_mapping);
5790         if (!tpr->rx_std)
5791                 goto err_out;
5792
5793         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5794                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5795                                               TG3_RX_JUMBO_RING_SIZE,
5796                                               GFP_KERNEL);
5797                 if (!tpr->rx_jmb_buffers)
5798                         goto err_out;
5799
5800                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5801                                                    TG3_RX_JUMBO_RING_BYTES,
5802                                                    &tpr->rx_jmb_mapping);
5803                 if (!tpr->rx_jmb)
5804                         goto err_out;
5805         }
5806
5807         return 0;
5808
5809 err_out:
5810         tg3_rx_prodring_fini(tp, tpr);
5811         return -ENOMEM;
5812 }
5813
5814 /* Free up pending packets in all rx/tx rings.
5815  *
5816  * The chip has been shut down and the driver detached from
5817  * the networking, so no interrupts or new tx packets will
5818  * end up in the driver.  tp->{tx,}lock is not held and we are not
5819  * in an interrupt context and thus may sleep.
5820  */
5821 static void tg3_free_rings(struct tg3 *tp)
5822 {
5823         int i, j;
5824
5825         for (j = 0; j < tp->irq_cnt; j++) {
5826                 struct tg3_napi *tnapi = &tp->napi[j];
5827
5828                 if (!tnapi->tx_buffers)
5829                         continue;
5830
5831                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5832                         struct tx_ring_info *txp;
5833                         struct sk_buff *skb;
5834
5835                         txp = &tnapi->tx_buffers[i];
5836                         skb = txp->skb;
5837
5838                         if (skb == NULL) {
5839                                 i++;
5840                                 continue;
5841                         }
5842
5843                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5844
5845                         txp->skb = NULL;
5846
5847                         i += skb_shinfo(skb)->nr_frags + 1;
5848
5849                         dev_kfree_skb_any(skb);
5850                 }
5851         }
5852
5853         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5854 }
5855
5856 /* Initialize tx/rx rings for packet processing.
5857  *
5858  * The chip has been shut down and the driver detached from
5859  * the networking, so no interrupts or new tx packets will
5860  * end up in the driver.  tp->{tx,}lock are held and thus
5861  * we may not sleep.
5862  */
5863 static int tg3_init_rings(struct tg3 *tp)
5864 {
5865         int i;
5866
5867         /* Free up all the SKBs. */
5868         tg3_free_rings(tp);
5869
5870         for (i = 0; i < tp->irq_cnt; i++) {
5871                 struct tg3_napi *tnapi = &tp->napi[i];
5872
5873                 tnapi->last_tag = 0;
5874                 tnapi->last_irq_tag = 0;
5875                 tnapi->hw_status->status = 0;
5876                 tnapi->hw_status->status_tag = 0;
5877                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5878
5879                 tnapi->tx_prod = 0;
5880                 tnapi->tx_cons = 0;
5881                 if (tnapi->tx_ring)
5882                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5883
5884                 tnapi->rx_rcb_ptr = 0;
5885                 if (tnapi->rx_rcb)
5886                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5887         }
5888
5889         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5890 }
5891
5892 /*
5893  * Must not be invoked with interrupt sources disabled and
5894  * the hardware shutdown down.
5895  */
5896 static void tg3_free_consistent(struct tg3 *tp)
5897 {
5898         int i;
5899
5900         for (i = 0; i < tp->irq_cnt; i++) {
5901                 struct tg3_napi *tnapi = &tp->napi[i];
5902
5903                 if (tnapi->tx_ring) {
5904                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5905                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5906                         tnapi->tx_ring = NULL;
5907                 }
5908
5909                 kfree(tnapi->tx_buffers);
5910                 tnapi->tx_buffers = NULL;
5911
5912                 if (tnapi->rx_rcb) {
5913                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5914                                             tnapi->rx_rcb,
5915                                             tnapi->rx_rcb_mapping);
5916                         tnapi->rx_rcb = NULL;
5917                 }
5918
5919                 if (tnapi->hw_status) {
5920                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5921                                             tnapi->hw_status,
5922                                             tnapi->status_mapping);
5923                         tnapi->hw_status = NULL;
5924                 }
5925         }
5926
5927         if (tp->hw_stats) {
5928                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5929                                     tp->hw_stats, tp->stats_mapping);
5930                 tp->hw_stats = NULL;
5931         }
5932
5933         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5934 }
5935
5936 /*
5937  * Must not be invoked with interrupt sources disabled and
5938  * the hardware shutdown down.  Can sleep.
5939  */
5940 static int tg3_alloc_consistent(struct tg3 *tp)
5941 {
5942         int i;
5943
5944         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5945                 return -ENOMEM;
5946
5947         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5948                                             sizeof(struct tg3_hw_stats),
5949                                             &tp->stats_mapping);
5950         if (!tp->hw_stats)
5951                 goto err_out;
5952
5953         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5954
5955         for (i = 0; i < tp->irq_cnt; i++) {
5956                 struct tg3_napi *tnapi = &tp->napi[i];
5957                 struct tg3_hw_status *sblk;
5958
5959                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5960                                                         TG3_HW_STATUS_SIZE,
5961                                                         &tnapi->status_mapping);
5962                 if (!tnapi->hw_status)
5963                         goto err_out;
5964
5965                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5966                 sblk = tnapi->hw_status;
5967
5968                 /*
5969                  * When RSS is enabled, the status block format changes
5970                  * slightly.  The "rx_jumbo_consumer", "reserved",
5971                  * and "rx_mini_consumer" members get mapped to the
5972                  * other three rx return ring producer indexes.
5973                  */
5974                 switch (i) {
5975                 default:
5976                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5977                         break;
5978                 case 2:
5979                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5980                         break;
5981                 case 3:
5982                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
5983                         break;
5984                 case 4:
5985                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5986                         break;
5987                 }
5988
5989                 /*
5990                  * If multivector RSS is enabled, vector 0 does not handle
5991                  * rx or tx interrupts.  Don't allocate any resources for it.
5992                  */
5993                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5994                         continue;
5995
5996                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5997                                                      TG3_RX_RCB_RING_BYTES(tp),
5998                                                      &tnapi->rx_rcb_mapping);
5999                 if (!tnapi->rx_rcb)
6000                         goto err_out;
6001
6002                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6003
6004                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6005                                             TG3_TX_RING_SIZE, GFP_KERNEL);
6006                 if (!tnapi->tx_buffers)
6007                         goto err_out;
6008
6009                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6010                                                       TG3_TX_RING_BYTES,
6011                                                       &tnapi->tx_desc_mapping);
6012                 if (!tnapi->tx_ring)
6013                         goto err_out;
6014         }
6015
6016         return 0;
6017
6018 err_out:
6019         tg3_free_consistent(tp);
6020         return -ENOMEM;
6021 }
6022
6023 #define MAX_WAIT_CNT 1000
6024
6025 /* To stop a block, clear the enable bit and poll till it
6026  * clears.  tp->lock is held.
6027  */
6028 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6029 {
6030         unsigned int i;
6031         u32 val;
6032
6033         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6034                 switch (ofs) {
6035                 case RCVLSC_MODE:
6036                 case DMAC_MODE:
6037                 case MBFREE_MODE:
6038                 case BUFMGR_MODE:
6039                 case MEMARB_MODE:
6040                         /* We can't enable/disable these bits of the
6041                          * 5705/5750, just say success.
6042                          */
6043                         return 0;
6044
6045                 default:
6046                         break;
6047                 }
6048         }
6049
6050         val = tr32(ofs);
6051         val &= ~enable_bit;
6052         tw32_f(ofs, val);
6053
6054         for (i = 0; i < MAX_WAIT_CNT; i++) {
6055                 udelay(100);
6056                 val = tr32(ofs);
6057                 if ((val & enable_bit) == 0)
6058                         break;
6059         }
6060
6061         if (i == MAX_WAIT_CNT && !silent) {
6062                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6063                        "ofs=%lx enable_bit=%x\n",
6064                        ofs, enable_bit);
6065                 return -ENODEV;
6066         }
6067
6068         return 0;
6069 }
6070
6071 /* tp->lock is held. */
6072 static int tg3_abort_hw(struct tg3 *tp, int silent)
6073 {
6074         int i, err;
6075
6076         tg3_disable_ints(tp);
6077
6078         tp->rx_mode &= ~RX_MODE_ENABLE;
6079         tw32_f(MAC_RX_MODE, tp->rx_mode);
6080         udelay(10);
6081
6082         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6083         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6084         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6085         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6086         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6087         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6088
6089         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6090         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6091         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6092         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6093         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6094         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6095         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6096
6097         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6098         tw32_f(MAC_MODE, tp->mac_mode);
6099         udelay(40);
6100
6101         tp->tx_mode &= ~TX_MODE_ENABLE;
6102         tw32_f(MAC_TX_MODE, tp->tx_mode);
6103
6104         for (i = 0; i < MAX_WAIT_CNT; i++) {
6105                 udelay(100);
6106                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6107                         break;
6108         }
6109         if (i >= MAX_WAIT_CNT) {
6110                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6111                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6112                        tp->dev->name, tr32(MAC_TX_MODE));
6113                 err |= -ENODEV;
6114         }
6115
6116         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6117         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6118         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6119
6120         tw32(FTQ_RESET, 0xffffffff);
6121         tw32(FTQ_RESET, 0x00000000);
6122
6123         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6124         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6125
6126         for (i = 0; i < tp->irq_cnt; i++) {
6127                 struct tg3_napi *tnapi = &tp->napi[i];
6128                 if (tnapi->hw_status)
6129                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6130         }
6131         if (tp->hw_stats)
6132                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6133
6134         return err;
6135 }
6136
6137 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6138 {
6139         int i;
6140         u32 apedata;
6141
6142         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6143         if (apedata != APE_SEG_SIG_MAGIC)
6144                 return;
6145
6146         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6147         if (!(apedata & APE_FW_STATUS_READY))
6148                 return;
6149
6150         /* Wait for up to 1 millisecond for APE to service previous event. */
6151         for (i = 0; i < 10; i++) {
6152                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6153                         return;
6154
6155                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6156
6157                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6158                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6159                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6160
6161                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6162
6163                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6164                         break;
6165
6166                 udelay(100);
6167         }
6168
6169         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6170                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6171 }
6172
6173 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6174 {
6175         u32 event;
6176         u32 apedata;
6177
6178         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6179                 return;
6180
6181         switch (kind) {
6182                 case RESET_KIND_INIT:
6183                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6184                                         APE_HOST_SEG_SIG_MAGIC);
6185                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6186                                         APE_HOST_SEG_LEN_MAGIC);
6187                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6188                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6189                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6190                                         APE_HOST_DRIVER_ID_MAGIC);
6191                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6192                                         APE_HOST_BEHAV_NO_PHYLOCK);
6193
6194                         event = APE_EVENT_STATUS_STATE_START;
6195                         break;
6196                 case RESET_KIND_SHUTDOWN:
6197                         /* With the interface we are currently using,
6198                          * APE does not track driver state.  Wiping
6199                          * out the HOST SEGMENT SIGNATURE forces
6200                          * the APE to assume OS absent status.
6201                          */
6202                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6203
6204                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6205                         break;
6206                 case RESET_KIND_SUSPEND:
6207                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6208                         break;
6209                 default:
6210                         return;
6211         }
6212
6213         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6214
6215         tg3_ape_send_event(tp, event);
6216 }
6217
6218 /* tp->lock is held. */
6219 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6220 {
6221         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6222                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6223
6224         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6225                 switch (kind) {
6226                 case RESET_KIND_INIT:
6227                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6228                                       DRV_STATE_START);
6229                         break;
6230
6231                 case RESET_KIND_SHUTDOWN:
6232                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6233                                       DRV_STATE_UNLOAD);
6234                         break;
6235
6236                 case RESET_KIND_SUSPEND:
6237                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6238                                       DRV_STATE_SUSPEND);
6239                         break;
6240
6241                 default:
6242                         break;
6243                 }
6244         }
6245
6246         if (kind == RESET_KIND_INIT ||
6247             kind == RESET_KIND_SUSPEND)
6248                 tg3_ape_driver_state_change(tp, kind);
6249 }
6250
6251 /* tp->lock is held. */
6252 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6253 {
6254         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6255                 switch (kind) {
6256                 case RESET_KIND_INIT:
6257                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6258                                       DRV_STATE_START_DONE);
6259                         break;
6260
6261                 case RESET_KIND_SHUTDOWN:
6262                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6263                                       DRV_STATE_UNLOAD_DONE);
6264                         break;
6265
6266                 default:
6267                         break;
6268                 }
6269         }
6270
6271         if (kind == RESET_KIND_SHUTDOWN)
6272                 tg3_ape_driver_state_change(tp, kind);
6273 }
6274
6275 /* tp->lock is held. */
6276 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6277 {
6278         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6279                 switch (kind) {
6280                 case RESET_KIND_INIT:
6281                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6282                                       DRV_STATE_START);
6283                         break;
6284
6285                 case RESET_KIND_SHUTDOWN:
6286                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6287                                       DRV_STATE_UNLOAD);
6288                         break;
6289
6290                 case RESET_KIND_SUSPEND:
6291                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6292                                       DRV_STATE_SUSPEND);
6293                         break;
6294
6295                 default:
6296                         break;
6297                 }
6298         }
6299 }
6300
6301 static int tg3_poll_fw(struct tg3 *tp)
6302 {
6303         int i;
6304         u32 val;
6305
6306         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6307                 /* Wait up to 20ms for init done. */
6308                 for (i = 0; i < 200; i++) {
6309                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6310                                 return 0;
6311                         udelay(100);
6312                 }
6313                 return -ENODEV;
6314         }
6315
6316         /* Wait for firmware initialization to complete. */
6317         for (i = 0; i < 100000; i++) {
6318                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6319                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6320                         break;
6321                 udelay(10);
6322         }
6323
6324         /* Chip might not be fitted with firmware.  Some Sun onboard
6325          * parts are configured like that.  So don't signal the timeout
6326          * of the above loop as an error, but do report the lack of
6327          * running firmware once.
6328          */
6329         if (i >= 100000 &&
6330             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6331                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6332
6333                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6334                        tp->dev->name);
6335         }
6336
6337         return 0;
6338 }
6339
6340 /* Save PCI command register before chip reset */
6341 static void tg3_save_pci_state(struct tg3 *tp)
6342 {
6343         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6344 }
6345
6346 /* Restore PCI state after chip reset */
6347 static void tg3_restore_pci_state(struct tg3 *tp)
6348 {
6349         u32 val;
6350
6351         /* Re-enable indirect register accesses. */
6352         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6353                                tp->misc_host_ctrl);
6354
6355         /* Set MAX PCI retry to zero. */
6356         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6357         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6358             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6359                 val |= PCISTATE_RETRY_SAME_DMA;
6360         /* Allow reads and writes to the APE register and memory space. */
6361         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6362                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6363                        PCISTATE_ALLOW_APE_SHMEM_WR;
6364         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6365
6366         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6367
6368         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6369                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6370                         pcie_set_readrq(tp->pdev, 4096);
6371                 else {
6372                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6373                                               tp->pci_cacheline_sz);
6374                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6375                                               tp->pci_lat_timer);
6376                 }
6377         }
6378
6379         /* Make sure PCI-X relaxed ordering bit is clear. */
6380         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6381                 u16 pcix_cmd;
6382
6383                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6384                                      &pcix_cmd);
6385                 pcix_cmd &= ~PCI_X_CMD_ERO;
6386                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6387                                       pcix_cmd);
6388         }
6389
6390         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6391
6392                 /* Chip reset on 5780 will reset MSI enable bit,
6393                  * so need to restore it.
6394                  */
6395                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6396                         u16 ctrl;
6397
6398                         pci_read_config_word(tp->pdev,
6399                                              tp->msi_cap + PCI_MSI_FLAGS,
6400                                              &ctrl);
6401                         pci_write_config_word(tp->pdev,
6402                                               tp->msi_cap + PCI_MSI_FLAGS,
6403                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6404                         val = tr32(MSGINT_MODE);
6405                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6406                 }
6407         }
6408 }
6409
6410 static void tg3_stop_fw(struct tg3 *);
6411
6412 /* tp->lock is held. */
6413 static int tg3_chip_reset(struct tg3 *tp)
6414 {
6415         u32 val;
6416         void (*write_op)(struct tg3 *, u32, u32);
6417         int i, err;
6418
6419         tg3_nvram_lock(tp);
6420
6421         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6422
6423         /* No matching tg3_nvram_unlock() after this because
6424          * chip reset below will undo the nvram lock.
6425          */
6426         tp->nvram_lock_cnt = 0;
6427
6428         /* GRC_MISC_CFG core clock reset will clear the memory
6429          * enable bit in PCI register 4 and the MSI enable bit
6430          * on some chips, so we save relevant registers here.
6431          */
6432         tg3_save_pci_state(tp);
6433
6434         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6435             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6436                 tw32(GRC_FASTBOOT_PC, 0);
6437
6438         /*
6439          * We must avoid the readl() that normally takes place.
6440          * It locks machines, causes machine checks, and other
6441          * fun things.  So, temporarily disable the 5701
6442          * hardware workaround, while we do the reset.
6443          */
6444         write_op = tp->write32;
6445         if (write_op == tg3_write_flush_reg32)
6446                 tp->write32 = tg3_write32;
6447
6448         /* Prevent the irq handler from reading or writing PCI registers
6449          * during chip reset when the memory enable bit in the PCI command
6450          * register may be cleared.  The chip does not generate interrupt
6451          * at this time, but the irq handler may still be called due to irq
6452          * sharing or irqpoll.
6453          */
6454         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6455         for (i = 0; i < tp->irq_cnt; i++) {
6456                 struct tg3_napi *tnapi = &tp->napi[i];
6457                 if (tnapi->hw_status) {
6458                         tnapi->hw_status->status = 0;
6459                         tnapi->hw_status->status_tag = 0;
6460                 }
6461                 tnapi->last_tag = 0;
6462                 tnapi->last_irq_tag = 0;
6463         }
6464         smp_mb();
6465
6466         for (i = 0; i < tp->irq_cnt; i++)
6467                 synchronize_irq(tp->napi[i].irq_vec);
6468
6469         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6470                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6471                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6472         }
6473
6474         /* do the reset */
6475         val = GRC_MISC_CFG_CORECLK_RESET;
6476
6477         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6478                 if (tr32(0x7e2c) == 0x60) {
6479                         tw32(0x7e2c, 0x20);
6480                 }
6481                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6482                         tw32(GRC_MISC_CFG, (1 << 29));
6483                         val |= (1 << 29);
6484                 }
6485         }
6486
6487         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6488                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6489                 tw32(GRC_VCPU_EXT_CTRL,
6490                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6491         }
6492
6493         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6494                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6495         tw32(GRC_MISC_CFG, val);
6496
6497         /* restore 5701 hardware bug workaround write method */
6498         tp->write32 = write_op;
6499
6500         /* Unfortunately, we have to delay before the PCI read back.
6501          * Some 575X chips even will not respond to a PCI cfg access
6502          * when the reset command is given to the chip.
6503          *
6504          * How do these hardware designers expect things to work
6505          * properly if the PCI write is posted for a long period
6506          * of time?  It is always necessary to have some method by
6507          * which a register read back can occur to push the write
6508          * out which does the reset.
6509          *
6510          * For most tg3 variants the trick below was working.
6511          * Ho hum...
6512          */
6513         udelay(120);
6514
6515         /* Flush PCI posted writes.  The normal MMIO registers
6516          * are inaccessible at this time so this is the only
6517          * way to make this reliably (actually, this is no longer
6518          * the case, see above).  I tried to use indirect
6519          * register read/write but this upset some 5701 variants.
6520          */
6521         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6522
6523         udelay(120);
6524
6525         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6526                 u16 val16;
6527
6528                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6529                         int i;
6530                         u32 cfg_val;
6531
6532                         /* Wait for link training to complete.  */
6533                         for (i = 0; i < 5000; i++)
6534                                 udelay(100);
6535
6536                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6537                         pci_write_config_dword(tp->pdev, 0xc4,
6538                                                cfg_val | (1 << 15));
6539                 }
6540
6541                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6542                 pci_read_config_word(tp->pdev,
6543                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6544                                      &val16);
6545                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6546                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6547                 /*
6548                  * Older PCIe devices only support the 128 byte
6549                  * MPS setting.  Enforce the restriction.
6550                  */
6551                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6552                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6553                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6554                 pci_write_config_word(tp->pdev,
6555                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6556                                       val16);
6557
6558                 pcie_set_readrq(tp->pdev, 4096);
6559
6560                 /* Clear error status */
6561                 pci_write_config_word(tp->pdev,
6562                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6563                                       PCI_EXP_DEVSTA_CED |
6564                                       PCI_EXP_DEVSTA_NFED |
6565                                       PCI_EXP_DEVSTA_FED |
6566                                       PCI_EXP_DEVSTA_URD);
6567         }
6568
6569         tg3_restore_pci_state(tp);
6570
6571         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6572
6573         val = 0;
6574         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6575                 val = tr32(MEMARB_MODE);
6576         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6577
6578         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6579                 tg3_stop_fw(tp);
6580                 tw32(0x5000, 0x400);
6581         }
6582
6583         tw32(GRC_MODE, tp->grc_mode);
6584
6585         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6586                 val = tr32(0xc4);
6587
6588                 tw32(0xc4, val | (1 << 15));
6589         }
6590
6591         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6592             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6593                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6594                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6595                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6596                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6597         }
6598
6599         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6600                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6601                 tw32_f(MAC_MODE, tp->mac_mode);
6602         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6603                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6604                 tw32_f(MAC_MODE, tp->mac_mode);
6605         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6606                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6607                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6608                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6609                 tw32_f(MAC_MODE, tp->mac_mode);
6610         } else
6611                 tw32_f(MAC_MODE, 0);
6612         udelay(40);
6613
6614         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6615
6616         err = tg3_poll_fw(tp);
6617         if (err)
6618                 return err;
6619
6620         tg3_mdio_start(tp);
6621
6622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6623                 u8 phy_addr;
6624
6625                 phy_addr = tp->phy_addr;
6626                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6627
6628                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6629                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6630                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6631                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6632                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6633                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6634                 udelay(10);
6635
6636                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6637                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6638                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6639                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6640                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6641                 udelay(10);
6642
6643                 tp->phy_addr = phy_addr;
6644         }
6645
6646         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6647             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6648             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6649             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6650                 val = tr32(0x7c00);
6651
6652                 tw32(0x7c00, val | (1 << 25));
6653         }
6654
6655         /* Reprobe ASF enable state.  */
6656         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6657         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6658         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6659         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6660                 u32 nic_cfg;
6661
6662                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6663                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6664                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6665                         tp->last_event_jiffies = jiffies;
6666                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6667                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6668                 }
6669         }
6670
6671         return 0;
6672 }
6673
6674 /* tp->lock is held. */
6675 static void tg3_stop_fw(struct tg3 *tp)
6676 {
6677         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6678            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6679                 /* Wait for RX cpu to ACK the previous event. */
6680                 tg3_wait_for_event_ack(tp);
6681
6682                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6683
6684                 tg3_generate_fw_event(tp);
6685
6686                 /* Wait for RX cpu to ACK this event. */
6687                 tg3_wait_for_event_ack(tp);
6688         }
6689 }
6690
6691 /* tp->lock is held. */
6692 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6693 {
6694         int err;
6695
6696         tg3_stop_fw(tp);
6697
6698         tg3_write_sig_pre_reset(tp, kind);
6699
6700         tg3_abort_hw(tp, silent);
6701         err = tg3_chip_reset(tp);
6702
6703         __tg3_set_mac_addr(tp, 0);
6704
6705         tg3_write_sig_legacy(tp, kind);
6706         tg3_write_sig_post_reset(tp, kind);
6707
6708         if (err)
6709                 return err;
6710
6711         return 0;
6712 }
6713
6714 #define RX_CPU_SCRATCH_BASE     0x30000
6715 #define RX_CPU_SCRATCH_SIZE     0x04000
6716 #define TX_CPU_SCRATCH_BASE     0x34000
6717 #define TX_CPU_SCRATCH_SIZE     0x04000
6718
6719 /* tp->lock is held. */
6720 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6721 {
6722         int i;
6723
6724         BUG_ON(offset == TX_CPU_BASE &&
6725             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6726
6727         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6728                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6729
6730                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6731                 return 0;
6732         }
6733         if (offset == RX_CPU_BASE) {
6734                 for (i = 0; i < 10000; i++) {
6735                         tw32(offset + CPU_STATE, 0xffffffff);
6736                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6737                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6738                                 break;
6739                 }
6740
6741                 tw32(offset + CPU_STATE, 0xffffffff);
6742                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6743                 udelay(10);
6744         } else {
6745                 for (i = 0; i < 10000; i++) {
6746                         tw32(offset + CPU_STATE, 0xffffffff);
6747                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6748                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6749                                 break;
6750                 }
6751         }
6752
6753         if (i >= 10000) {
6754                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6755                        "and %s CPU\n",
6756                        tp->dev->name,
6757                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6758                 return -ENODEV;
6759         }
6760
6761         /* Clear firmware's nvram arbitration. */
6762         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6763                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6764         return 0;
6765 }
6766
6767 struct fw_info {
6768         unsigned int fw_base;
6769         unsigned int fw_len;
6770         const __be32 *fw_data;
6771 };
6772
6773 /* tp->lock is held. */
6774 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6775                                  int cpu_scratch_size, struct fw_info *info)
6776 {
6777         int err, lock_err, i;
6778         void (*write_op)(struct tg3 *, u32, u32);
6779
6780         if (cpu_base == TX_CPU_BASE &&
6781             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6782                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6783                        "TX cpu firmware on %s which is 5705.\n",
6784                        tp->dev->name);
6785                 return -EINVAL;
6786         }
6787
6788         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6789                 write_op = tg3_write_mem;
6790         else
6791                 write_op = tg3_write_indirect_reg32;
6792
6793         /* It is possible that bootcode is still loading at this point.
6794          * Get the nvram lock first before halting the cpu.
6795          */
6796         lock_err = tg3_nvram_lock(tp);
6797         err = tg3_halt_cpu(tp, cpu_base);
6798         if (!lock_err)
6799                 tg3_nvram_unlock(tp);
6800         if (err)
6801                 goto out;
6802
6803         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6804                 write_op(tp, cpu_scratch_base + i, 0);
6805         tw32(cpu_base + CPU_STATE, 0xffffffff);
6806         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6807         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6808                 write_op(tp, (cpu_scratch_base +
6809                               (info->fw_base & 0xffff) +
6810                               (i * sizeof(u32))),
6811                               be32_to_cpu(info->fw_data[i]));
6812
6813         err = 0;
6814
6815 out:
6816         return err;
6817 }
6818
6819 /* tp->lock is held. */
6820 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6821 {
6822         struct fw_info info;
6823         const __be32 *fw_data;
6824         int err, i;
6825
6826         fw_data = (void *)tp->fw->data;
6827
6828         /* Firmware blob starts with version numbers, followed by
6829            start address and length. We are setting complete length.
6830            length = end_address_of_bss - start_address_of_text.
6831            Remainder is the blob to be loaded contiguously
6832            from start address. */
6833
6834         info.fw_base = be32_to_cpu(fw_data[1]);
6835         info.fw_len = tp->fw->size - 12;
6836         info.fw_data = &fw_data[3];
6837
6838         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6839                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6840                                     &info);
6841         if (err)
6842                 return err;
6843
6844         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6845                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6846                                     &info);
6847         if (err)
6848                 return err;
6849
6850         /* Now startup only the RX cpu. */
6851         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6852         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6853
6854         for (i = 0; i < 5; i++) {
6855                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6856                         break;
6857                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6858                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6859                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6860                 udelay(1000);
6861         }
6862         if (i >= 5) {
6863                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6864                        "to set RX CPU PC, is %08x should be %08x\n",
6865                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6866                        info.fw_base);
6867                 return -ENODEV;
6868         }
6869         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6870         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6871
6872         return 0;
6873 }
6874
6875 /* 5705 needs a special version of the TSO firmware.  */
6876
6877 /* tp->lock is held. */
6878 static int tg3_load_tso_firmware(struct tg3 *tp)
6879 {
6880         struct fw_info info;
6881         const __be32 *fw_data;
6882         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6883         int err, i;
6884
6885         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6886                 return 0;
6887
6888         fw_data = (void *)tp->fw->data;
6889
6890         /* Firmware blob starts with version numbers, followed by
6891            start address and length. We are setting complete length.
6892            length = end_address_of_bss - start_address_of_text.
6893            Remainder is the blob to be loaded contiguously
6894            from start address. */
6895
6896         info.fw_base = be32_to_cpu(fw_data[1]);
6897         cpu_scratch_size = tp->fw_len;
6898         info.fw_len = tp->fw->size - 12;
6899         info.fw_data = &fw_data[3];
6900
6901         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6902                 cpu_base = RX_CPU_BASE;
6903                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6904         } else {
6905                 cpu_base = TX_CPU_BASE;
6906                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6907                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6908         }
6909
6910         err = tg3_load_firmware_cpu(tp, cpu_base,
6911                                     cpu_scratch_base, cpu_scratch_size,
6912                                     &info);
6913         if (err)
6914                 return err;
6915
6916         /* Now startup the cpu. */
6917         tw32(cpu_base + CPU_STATE, 0xffffffff);
6918         tw32_f(cpu_base + CPU_PC, info.fw_base);
6919
6920         for (i = 0; i < 5; i++) {
6921                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6922                         break;
6923                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6924                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6925                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6926                 udelay(1000);
6927         }
6928         if (i >= 5) {
6929                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6930                        "to set CPU PC, is %08x should be %08x\n",
6931                        tp->dev->name, tr32(cpu_base + CPU_PC),
6932                        info.fw_base);
6933                 return -ENODEV;
6934         }
6935         tw32(cpu_base + CPU_STATE, 0xffffffff);
6936         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6937         return 0;
6938 }
6939
6940
6941 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6942 {
6943         struct tg3 *tp = netdev_priv(dev);
6944         struct sockaddr *addr = p;
6945         int err = 0, skip_mac_1 = 0;
6946
6947         if (!is_valid_ether_addr(addr->sa_data))
6948                 return -EINVAL;
6949
6950         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6951
6952         if (!netif_running(dev))
6953                 return 0;
6954
6955         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6956                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6957
6958                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6959                 addr0_low = tr32(MAC_ADDR_0_LOW);
6960                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6961                 addr1_low = tr32(MAC_ADDR_1_LOW);
6962
6963                 /* Skip MAC addr 1 if ASF is using it. */
6964                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6965                     !(addr1_high == 0 && addr1_low == 0))
6966                         skip_mac_1 = 1;
6967         }
6968         spin_lock_bh(&tp->lock);
6969         __tg3_set_mac_addr(tp, skip_mac_1);
6970         spin_unlock_bh(&tp->lock);
6971
6972         return err;
6973 }
6974
6975 /* tp->lock is held. */
6976 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6977                            dma_addr_t mapping, u32 maxlen_flags,
6978                            u32 nic_addr)
6979 {
6980         tg3_write_mem(tp,
6981                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6982                       ((u64) mapping >> 32));
6983         tg3_write_mem(tp,
6984                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6985                       ((u64) mapping & 0xffffffff));
6986         tg3_write_mem(tp,
6987                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6988                        maxlen_flags);
6989
6990         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6991                 tg3_write_mem(tp,
6992                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6993                               nic_addr);
6994 }
6995
6996 static void __tg3_set_rx_mode(struct net_device *);
6997 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6998 {
6999         int i;
7000
7001         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7002                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7003                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7004                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7005
7006                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7007                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7008                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7009         } else {
7010                 tw32(HOSTCC_TXCOL_TICKS, 0);
7011                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7012                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7013
7014                 tw32(HOSTCC_RXCOL_TICKS, 0);
7015                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7016                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7017         }
7018
7019         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7020                 u32 val = ec->stats_block_coalesce_usecs;
7021
7022                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7023                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7024
7025                 if (!netif_carrier_ok(tp->dev))
7026                         val = 0;
7027
7028                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7029         }
7030
7031         for (i = 0; i < tp->irq_cnt - 1; i++) {
7032                 u32 reg;
7033
7034                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7035                 tw32(reg, ec->rx_coalesce_usecs);
7036                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7037                 tw32(reg, ec->tx_coalesce_usecs);
7038                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7039                 tw32(reg, ec->rx_max_coalesced_frames);
7040                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7041                 tw32(reg, ec->tx_max_coalesced_frames);
7042                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7043                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7044                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7045                 tw32(reg, ec->tx_max_coalesced_frames_irq);
7046         }
7047
7048         for (; i < tp->irq_max - 1; i++) {
7049                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7050                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7051                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7052                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7053                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7054                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7055         }
7056 }
7057
7058 /* tp->lock is held. */
7059 static void tg3_rings_reset(struct tg3 *tp)
7060 {
7061         int i;
7062         u32 stblk, txrcb, rxrcb, limit;
7063         struct tg3_napi *tnapi = &tp->napi[0];
7064
7065         /* Disable all transmit rings but the first. */
7066         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7067                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7068         else
7069                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7070
7071         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7072              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7073                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7074                               BDINFO_FLAGS_DISABLED);
7075
7076
7077         /* Disable all receive return rings but the first. */
7078         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7079                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7080         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7081                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7082         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7083                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7084         else
7085                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7086
7087         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7088              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7089                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7090                               BDINFO_FLAGS_DISABLED);
7091
7092         /* Disable interrupts */
7093         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7094
7095         /* Zero mailbox registers. */
7096         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7097                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7098                         tp->napi[i].tx_prod = 0;
7099                         tp->napi[i].tx_cons = 0;
7100                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7101                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7102                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7103                 }
7104         } else {
7105                 tp->napi[0].tx_prod = 0;
7106                 tp->napi[0].tx_cons = 0;
7107                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7108                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7109         }
7110
7111         /* Make sure the NIC-based send BD rings are disabled. */
7112         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7113                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7114                 for (i = 0; i < 16; i++)
7115                         tw32_tx_mbox(mbox + i * 8, 0);
7116         }
7117
7118         txrcb = NIC_SRAM_SEND_RCB;
7119         rxrcb = NIC_SRAM_RCV_RET_RCB;
7120
7121         /* Clear status block in ram. */
7122         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7123
7124         /* Set status block DMA address */
7125         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7126              ((u64) tnapi->status_mapping >> 32));
7127         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7128              ((u64) tnapi->status_mapping & 0xffffffff));
7129
7130         if (tnapi->tx_ring) {
7131                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7132                                (TG3_TX_RING_SIZE <<
7133                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7134                                NIC_SRAM_TX_BUFFER_DESC);
7135                 txrcb += TG3_BDINFO_SIZE;
7136         }
7137
7138         if (tnapi->rx_rcb) {
7139                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7140                                (TG3_RX_RCB_RING_SIZE(tp) <<
7141                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7142                 rxrcb += TG3_BDINFO_SIZE;
7143         }
7144
7145         stblk = HOSTCC_STATBLCK_RING1;
7146
7147         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7148                 u64 mapping = (u64)tnapi->status_mapping;
7149                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7150                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7151
7152                 /* Clear status block in ram. */
7153                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7154
7155                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7156                                (TG3_TX_RING_SIZE <<
7157                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7158                                NIC_SRAM_TX_BUFFER_DESC);
7159
7160                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7161                                (TG3_RX_RCB_RING_SIZE(tp) <<
7162                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7163
7164                 stblk += 8;
7165                 txrcb += TG3_BDINFO_SIZE;
7166                 rxrcb += TG3_BDINFO_SIZE;
7167         }
7168 }
7169
7170 /* tp->lock is held. */
7171 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7172 {
7173         u32 val, rdmac_mode;
7174         int i, err, limit;
7175         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7176
7177         tg3_disable_ints(tp);
7178
7179         tg3_stop_fw(tp);
7180
7181         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7182
7183         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7184                 tg3_abort_hw(tp, 1);
7185         }
7186
7187         if (reset_phy &&
7188             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7189                 tg3_phy_reset(tp);
7190
7191         err = tg3_chip_reset(tp);
7192         if (err)
7193                 return err;
7194
7195         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7196
7197         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7198                 val = tr32(TG3_CPMU_CTRL);
7199                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7200                 tw32(TG3_CPMU_CTRL, val);
7201
7202                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7203                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7204                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7205                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7206
7207                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7208                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7209                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7210                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7211
7212                 val = tr32(TG3_CPMU_HST_ACC);
7213                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7214                 val |= CPMU_HST_ACC_MACCLK_6_25;
7215                 tw32(TG3_CPMU_HST_ACC, val);
7216         }
7217
7218         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7219                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7220                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7221                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7222                 tw32(PCIE_PWR_MGMT_THRESH, val);
7223
7224                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7225                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7226
7227                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7228
7229                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7230                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7231         }
7232
7233         /* This works around an issue with Athlon chipsets on
7234          * B3 tigon3 silicon.  This bit has no effect on any
7235          * other revision.  But do not set this on PCI Express
7236          * chips and don't even touch the clocks if the CPMU is present.
7237          */
7238         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7239                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7240                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7241                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7242         }
7243
7244         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7245             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7246                 val = tr32(TG3PCI_PCISTATE);
7247                 val |= PCISTATE_RETRY_SAME_DMA;
7248                 tw32(TG3PCI_PCISTATE, val);
7249         }
7250
7251         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7252                 /* Allow reads and writes to the
7253                  * APE register and memory space.
7254                  */
7255                 val = tr32(TG3PCI_PCISTATE);
7256                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7257                        PCISTATE_ALLOW_APE_SHMEM_WR;
7258                 tw32(TG3PCI_PCISTATE, val);
7259         }
7260
7261         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7262                 /* Enable some hw fixes.  */
7263                 val = tr32(TG3PCI_MSI_DATA);
7264                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7265                 tw32(TG3PCI_MSI_DATA, val);
7266         }
7267
7268         /* Descriptor ring init may make accesses to the
7269          * NIC SRAM area to setup the TX descriptors, so we
7270          * can only do this after the hardware has been
7271          * successfully reset.
7272          */
7273         err = tg3_init_rings(tp);
7274         if (err)
7275                 return err;
7276
7277         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7278             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7279             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
7280                 /* This value is determined during the probe time DMA
7281                  * engine test, tg3_test_dma.
7282                  */
7283                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7284         }
7285
7286         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7287                           GRC_MODE_4X_NIC_SEND_RINGS |
7288                           GRC_MODE_NO_TX_PHDR_CSUM |
7289                           GRC_MODE_NO_RX_PHDR_CSUM);
7290         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7291
7292         /* Pseudo-header checksum is done by hardware logic and not
7293          * the offload processers, so make the chip do the pseudo-
7294          * header checksums on receive.  For transmit it is more
7295          * convenient to do the pseudo-header checksum in software
7296          * as Linux does that on transmit for us in all cases.
7297          */
7298         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7299
7300         tw32(GRC_MODE,
7301              tp->grc_mode |
7302              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7303
7304         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7305         val = tr32(GRC_MISC_CFG);
7306         val &= ~0xff;
7307         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7308         tw32(GRC_MISC_CFG, val);
7309
7310         /* Initialize MBUF/DESC pool. */
7311         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7312                 /* Do nothing.  */
7313         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7314                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7315                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7316                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7317                 else
7318                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7319                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7320                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7321         }
7322         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7323                 int fw_len;
7324
7325                 fw_len = tp->fw_len;
7326                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7327                 tw32(BUFMGR_MB_POOL_ADDR,
7328                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7329                 tw32(BUFMGR_MB_POOL_SIZE,
7330                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7331         }
7332
7333         if (tp->dev->mtu <= ETH_DATA_LEN) {
7334                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7335                      tp->bufmgr_config.mbuf_read_dma_low_water);
7336                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7337                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7338                 tw32(BUFMGR_MB_HIGH_WATER,
7339                      tp->bufmgr_config.mbuf_high_water);
7340         } else {
7341                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7342                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7343                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7344                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7345                 tw32(BUFMGR_MB_HIGH_WATER,
7346                      tp->bufmgr_config.mbuf_high_water_jumbo);
7347         }
7348         tw32(BUFMGR_DMA_LOW_WATER,
7349              tp->bufmgr_config.dma_low_water);
7350         tw32(BUFMGR_DMA_HIGH_WATER,
7351              tp->bufmgr_config.dma_high_water);
7352
7353         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7354         for (i = 0; i < 2000; i++) {
7355                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7356                         break;
7357                 udelay(10);
7358         }
7359         if (i >= 2000) {
7360                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7361                        tp->dev->name);
7362                 return -ENODEV;
7363         }
7364
7365         /* Setup replenish threshold. */
7366         val = tp->rx_pending / 8;
7367         if (val == 0)
7368                 val = 1;
7369         else if (val > tp->rx_std_max_post)
7370                 val = tp->rx_std_max_post;
7371         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7372                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7373                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7374
7375                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7376                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7377         }
7378
7379         tw32(RCVBDI_STD_THRESH, val);
7380
7381         /* Initialize TG3_BDINFO's at:
7382          *  RCVDBDI_STD_BD:     standard eth size rx ring
7383          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7384          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7385          *
7386          * like so:
7387          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7388          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7389          *                              ring attribute flags
7390          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7391          *
7392          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7393          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7394          *
7395          * The size of each ring is fixed in the firmware, but the location is
7396          * configurable.
7397          */
7398         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7399              ((u64) tpr->rx_std_mapping >> 32));
7400         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7401              ((u64) tpr->rx_std_mapping & 0xffffffff));
7402         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7403              NIC_SRAM_RX_BUFFER_DESC);
7404
7405         /* Disable the mini ring */
7406         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7407                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7408                      BDINFO_FLAGS_DISABLED);
7409
7410         /* Program the jumbo buffer descriptor ring control
7411          * blocks on those devices that have them.
7412          */
7413         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7414             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7415                 /* Setup replenish threshold. */
7416                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7417
7418                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7419                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7420                              ((u64) tpr->rx_jmb_mapping >> 32));
7421                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7422                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7423                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7424                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7425                              BDINFO_FLAGS_USE_EXT_RECV);
7426                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7427                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7428                 } else {
7429                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7430                              BDINFO_FLAGS_DISABLED);
7431                 }
7432
7433                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7434                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7435                               (RX_STD_MAX_SIZE << 2);
7436                 else
7437                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7438         } else
7439                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7440
7441         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7442
7443         tpr->rx_std_ptr = tp->rx_pending;
7444         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7445                      tpr->rx_std_ptr);
7446
7447         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7448                           tp->rx_jumbo_pending : 0;
7449         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7450                      tpr->rx_jmb_ptr);
7451
7452         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7453                 tw32(STD_REPLENISH_LWM, 32);
7454                 tw32(JMB_REPLENISH_LWM, 16);
7455         }
7456
7457         tg3_rings_reset(tp);
7458
7459         /* Initialize MAC address and backoff seed. */
7460         __tg3_set_mac_addr(tp, 0);
7461
7462         /* MTU + ethernet header + FCS + optional VLAN tag */
7463         tw32(MAC_RX_MTU_SIZE,
7464              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7465
7466         /* The slot time is changed by tg3_setup_phy if we
7467          * run at gigabit with half duplex.
7468          */
7469         tw32(MAC_TX_LENGTHS,
7470              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7471              (6 << TX_LENGTHS_IPG_SHIFT) |
7472              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7473
7474         /* Receive rules. */
7475         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7476         tw32(RCVLPC_CONFIG, 0x0181);
7477
7478         /* Calculate RDMAC_MODE setting early, we need it to determine
7479          * the RCVLPC_STATE_ENABLE mask.
7480          */
7481         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7482                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7483                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7484                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7485                       RDMAC_MODE_LNGREAD_ENAB);
7486
7487         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7488             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7489             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7490                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7491                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7492                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7493
7494         /* If statement applies to 5705 and 5750 PCI devices only */
7495         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7496              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7497             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7498                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7499                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7500                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7501                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7502                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7503                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7504                 }
7505         }
7506
7507         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7508                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7509
7510         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7511                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7512
7513         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7514             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7515                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7516
7517         /* Receive/send statistics. */
7518         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7519                 val = tr32(RCVLPC_STATS_ENABLE);
7520                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7521                 tw32(RCVLPC_STATS_ENABLE, val);
7522         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7523                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7524                 val = tr32(RCVLPC_STATS_ENABLE);
7525                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7526                 tw32(RCVLPC_STATS_ENABLE, val);
7527         } else {
7528                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7529         }
7530         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7531         tw32(SNDDATAI_STATSENAB, 0xffffff);
7532         tw32(SNDDATAI_STATSCTRL,
7533              (SNDDATAI_SCTRL_ENABLE |
7534               SNDDATAI_SCTRL_FASTUPD));
7535
7536         /* Setup host coalescing engine. */
7537         tw32(HOSTCC_MODE, 0);
7538         for (i = 0; i < 2000; i++) {
7539                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7540                         break;
7541                 udelay(10);
7542         }
7543
7544         __tg3_set_coalesce(tp, &tp->coal);
7545
7546         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7547                 /* Status/statistics block address.  See tg3_timer,
7548                  * the tg3_periodic_fetch_stats call there, and
7549                  * tg3_get_stats to see how this works for 5705/5750 chips.
7550                  */
7551                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7552                      ((u64) tp->stats_mapping >> 32));
7553                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7554                      ((u64) tp->stats_mapping & 0xffffffff));
7555                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7556
7557                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7558
7559                 /* Clear statistics and status block memory areas */
7560                 for (i = NIC_SRAM_STATS_BLK;
7561                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7562                      i += sizeof(u32)) {
7563                         tg3_write_mem(tp, i, 0);
7564                         udelay(40);
7565                 }
7566         }
7567
7568         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7569
7570         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7571         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7572         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7573                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7574
7575         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7576                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7577                 /* reset to prevent losing 1st rx packet intermittently */
7578                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7579                 udelay(10);
7580         }
7581
7582         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7583                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7584         else
7585                 tp->mac_mode = 0;
7586         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7587                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7588         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7589             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7590             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7591                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7592         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7593         udelay(40);
7594
7595         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7596          * If TG3_FLG2_IS_NIC is zero, we should read the
7597          * register to preserve the GPIO settings for LOMs. The GPIOs,
7598          * whether used as inputs or outputs, are set by boot code after
7599          * reset.
7600          */
7601         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7602                 u32 gpio_mask;
7603
7604                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7605                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7606                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7607
7608                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7609                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7610                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7611
7612                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7613                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7614
7615                 tp->grc_local_ctrl &= ~gpio_mask;
7616                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7617
7618                 /* GPIO1 must be driven high for eeprom write protect */
7619                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7620                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7621                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7622         }
7623         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7624         udelay(100);
7625
7626         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7627                 val = tr32(MSGINT_MODE);
7628                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7629                 tw32(MSGINT_MODE, val);
7630         }
7631
7632         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7633                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7634                 udelay(40);
7635         }
7636
7637         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7638                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7639                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7640                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7641                WDMAC_MODE_LNGREAD_ENAB);
7642
7643         /* If statement applies to 5705 and 5750 PCI devices only */
7644         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7645              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7646             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7647                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7648                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7649                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7650                         /* nothing */
7651                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7652                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7653                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7654                         val |= WDMAC_MODE_RX_ACCEL;
7655                 }
7656         }
7657
7658         /* Enable host coalescing bug fix */
7659         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7660                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7661
7662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7663                 val |= WDMAC_MODE_BURST_ALL_DATA;
7664
7665         tw32_f(WDMAC_MODE, val);
7666         udelay(40);
7667
7668         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7669                 u16 pcix_cmd;
7670
7671                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7672                                      &pcix_cmd);
7673                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7674                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7675                         pcix_cmd |= PCI_X_CMD_READ_2K;
7676                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7677                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7678                         pcix_cmd |= PCI_X_CMD_READ_2K;
7679                 }
7680                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7681                                       pcix_cmd);
7682         }
7683
7684         tw32_f(RDMAC_MODE, rdmac_mode);
7685         udelay(40);
7686
7687         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7688         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7689                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7690
7691         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7692                 tw32(SNDDATAC_MODE,
7693                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7694         else
7695                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7696
7697         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7698         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7699         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7700         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7701         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7702                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7703         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7704         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7705                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7706         tw32(SNDBDI_MODE, val);
7707         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7708
7709         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7710                 err = tg3_load_5701_a0_firmware_fix(tp);
7711                 if (err)
7712                         return err;
7713         }
7714
7715         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7716                 err = tg3_load_tso_firmware(tp);
7717                 if (err)
7718                         return err;
7719         }
7720
7721         tp->tx_mode = TX_MODE_ENABLE;
7722         tw32_f(MAC_TX_MODE, tp->tx_mode);
7723         udelay(100);
7724
7725         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7726                 u32 reg = MAC_RSS_INDIR_TBL_0;
7727                 u8 *ent = (u8 *)&val;
7728
7729                 /* Setup the indirection table */
7730                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7731                         int idx = i % sizeof(val);
7732
7733                         ent[idx] = i % (tp->irq_cnt - 1);
7734                         if (idx == sizeof(val) - 1) {
7735                                 tw32(reg, val);
7736                                 reg += 4;
7737                         }
7738                 }
7739
7740                 /* Setup the "secret" hash key. */
7741                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7742                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7743                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7744                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7745                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7746                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7747                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7748                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7749                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7750                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7751         }
7752
7753         tp->rx_mode = RX_MODE_ENABLE;
7754         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7755                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7756
7757         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7758                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7759                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7760                                RX_MODE_RSS_IPV6_HASH_EN |
7761                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7762                                RX_MODE_RSS_IPV4_HASH_EN |
7763                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7764
7765         tw32_f(MAC_RX_MODE, tp->rx_mode);
7766         udelay(10);
7767
7768         tw32(MAC_LED_CTRL, tp->led_ctrl);
7769
7770         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7771         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7772                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7773                 udelay(10);
7774         }
7775         tw32_f(MAC_RX_MODE, tp->rx_mode);
7776         udelay(10);
7777
7778         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7779                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7780                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7781                         /* Set drive transmission level to 1.2V  */
7782                         /* only if the signal pre-emphasis bit is not set  */
7783                         val = tr32(MAC_SERDES_CFG);
7784                         val &= 0xfffff000;
7785                         val |= 0x880;
7786                         tw32(MAC_SERDES_CFG, val);
7787                 }
7788                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7789                         tw32(MAC_SERDES_CFG, 0x616000);
7790         }
7791
7792         /* Prevent chip from dropping frames when flow control
7793          * is enabled.
7794          */
7795         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7796
7797         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7798             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7799                 /* Use hardware link auto-negotiation */
7800                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7801         }
7802
7803         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7804             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7805                 u32 tmp;
7806
7807                 tmp = tr32(SERDES_RX_CTRL);
7808                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7809                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7810                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7811                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7812         }
7813
7814         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7815                 if (tp->link_config.phy_is_low_power) {
7816                         tp->link_config.phy_is_low_power = 0;
7817                         tp->link_config.speed = tp->link_config.orig_speed;
7818                         tp->link_config.duplex = tp->link_config.orig_duplex;
7819                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7820                 }
7821
7822                 err = tg3_setup_phy(tp, 0);
7823                 if (err)
7824                         return err;
7825
7826                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7827                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7828                         u32 tmp;
7829
7830                         /* Clear CRC stats. */
7831                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7832                                 tg3_writephy(tp, MII_TG3_TEST1,
7833                                              tmp | MII_TG3_TEST1_CRC_EN);
7834                                 tg3_readphy(tp, 0x14, &tmp);
7835                         }
7836                 }
7837         }
7838
7839         __tg3_set_rx_mode(tp->dev);
7840
7841         /* Initialize receive rules. */
7842         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7843         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7844         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7845         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7846
7847         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7848             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7849                 limit = 8;
7850         else
7851                 limit = 16;
7852         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7853                 limit -= 4;
7854         switch (limit) {
7855         case 16:
7856                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7857         case 15:
7858                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7859         case 14:
7860                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7861         case 13:
7862                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7863         case 12:
7864                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7865         case 11:
7866                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7867         case 10:
7868                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7869         case 9:
7870                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7871         case 8:
7872                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7873         case 7:
7874                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7875         case 6:
7876                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7877         case 5:
7878                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7879         case 4:
7880                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7881         case 3:
7882                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7883         case 2:
7884         case 1:
7885
7886         default:
7887                 break;
7888         }
7889
7890         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7891                 /* Write our heartbeat update interval to APE. */
7892                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7893                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7894
7895         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7896
7897         return 0;
7898 }
7899
7900 /* Called at device open time to get the chip ready for
7901  * packet processing.  Invoked with tp->lock held.
7902  */
7903 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7904 {
7905         tg3_switch_clocks(tp);
7906
7907         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7908
7909         return tg3_reset_hw(tp, reset_phy);
7910 }
7911
7912 #define TG3_STAT_ADD32(PSTAT, REG) \
7913 do {    u32 __val = tr32(REG); \
7914         (PSTAT)->low += __val; \
7915         if ((PSTAT)->low < __val) \
7916                 (PSTAT)->high += 1; \
7917 } while (0)
7918
7919 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7920 {
7921         struct tg3_hw_stats *sp = tp->hw_stats;
7922
7923         if (!netif_carrier_ok(tp->dev))
7924                 return;
7925
7926         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7927         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7928         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7929         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7930         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7931         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7932         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7933         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7934         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7935         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7936         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7937         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7938         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7939
7940         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7941         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7942         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7943         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7944         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7945         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7946         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7947         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7948         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7949         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7950         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7951         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7952         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7953         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7954
7955         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7956         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7957         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7958 }
7959
7960 static void tg3_timer(unsigned long __opaque)
7961 {
7962         struct tg3 *tp = (struct tg3 *) __opaque;
7963
7964         if (tp->irq_sync)
7965                 goto restart_timer;
7966
7967         spin_lock(&tp->lock);
7968
7969         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7970                 /* All of this garbage is because when using non-tagged
7971                  * IRQ status the mailbox/status_block protocol the chip
7972                  * uses with the cpu is race prone.
7973                  */
7974                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7975                         tw32(GRC_LOCAL_CTRL,
7976                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7977                 } else {
7978                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7979                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7980                 }
7981
7982                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7983                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7984                         spin_unlock(&tp->lock);
7985                         schedule_work(&tp->reset_task);
7986                         return;
7987                 }
7988         }
7989
7990         /* This part only runs once per second. */
7991         if (!--tp->timer_counter) {
7992                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7993                         tg3_periodic_fetch_stats(tp);
7994
7995                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7996                         u32 mac_stat;
7997                         int phy_event;
7998
7999                         mac_stat = tr32(MAC_STATUS);
8000
8001                         phy_event = 0;
8002                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8003                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8004                                         phy_event = 1;
8005                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8006                                 phy_event = 1;
8007
8008                         if (phy_event)
8009                                 tg3_setup_phy(tp, 0);
8010                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8011                         u32 mac_stat = tr32(MAC_STATUS);
8012                         int need_setup = 0;
8013
8014                         if (netif_carrier_ok(tp->dev) &&
8015                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8016                                 need_setup = 1;
8017                         }
8018                         if (! netif_carrier_ok(tp->dev) &&
8019                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8020                                          MAC_STATUS_SIGNAL_DET))) {
8021                                 need_setup = 1;
8022                         }
8023                         if (need_setup) {
8024                                 if (!tp->serdes_counter) {
8025                                         tw32_f(MAC_MODE,
8026                                              (tp->mac_mode &
8027                                               ~MAC_MODE_PORT_MODE_MASK));
8028                                         udelay(40);
8029                                         tw32_f(MAC_MODE, tp->mac_mode);
8030                                         udelay(40);
8031                                 }
8032                                 tg3_setup_phy(tp, 0);
8033                         }
8034                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8035                         tg3_serdes_parallel_detect(tp);
8036
8037                 tp->timer_counter = tp->timer_multiplier;
8038         }
8039
8040         /* Heartbeat is only sent once every 2 seconds.
8041          *
8042          * The heartbeat is to tell the ASF firmware that the host
8043          * driver is still alive.  In the event that the OS crashes,
8044          * ASF needs to reset the hardware to free up the FIFO space
8045          * that may be filled with rx packets destined for the host.
8046          * If the FIFO is full, ASF will no longer function properly.
8047          *
8048          * Unintended resets have been reported on real time kernels
8049          * where the timer doesn't run on time.  Netpoll will also have
8050          * same problem.
8051          *
8052          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8053          * to check the ring condition when the heartbeat is expiring
8054          * before doing the reset.  This will prevent most unintended
8055          * resets.
8056          */
8057         if (!--tp->asf_counter) {
8058                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8059                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8060                         tg3_wait_for_event_ack(tp);
8061
8062                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8063                                       FWCMD_NICDRV_ALIVE3);
8064                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8065                         /* 5 seconds timeout */
8066                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8067
8068                         tg3_generate_fw_event(tp);
8069                 }
8070                 tp->asf_counter = tp->asf_multiplier;
8071         }
8072
8073         spin_unlock(&tp->lock);
8074
8075 restart_timer:
8076         tp->timer.expires = jiffies + tp->timer_offset;
8077         add_timer(&tp->timer);
8078 }
8079
8080 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8081 {
8082         irq_handler_t fn;
8083         unsigned long flags;
8084         char *name;
8085         struct tg3_napi *tnapi = &tp->napi[irq_num];
8086
8087         if (tp->irq_cnt == 1)
8088                 name = tp->dev->name;
8089         else {
8090                 name = &tnapi->irq_lbl[0];
8091                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8092                 name[IFNAMSIZ-1] = 0;
8093         }
8094
8095         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8096                 fn = tg3_msi;
8097                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8098                         fn = tg3_msi_1shot;
8099                 flags = IRQF_SAMPLE_RANDOM;
8100         } else {
8101                 fn = tg3_interrupt;
8102                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8103                         fn = tg3_interrupt_tagged;
8104                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8105         }
8106
8107         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8108 }
8109
8110 static int tg3_test_interrupt(struct tg3 *tp)
8111 {
8112         struct tg3_napi *tnapi = &tp->napi[0];
8113         struct net_device *dev = tp->dev;
8114         int err, i, intr_ok = 0;
8115         u32 val;
8116
8117         if (!netif_running(dev))
8118                 return -ENODEV;
8119
8120         tg3_disable_ints(tp);
8121
8122         free_irq(tnapi->irq_vec, tnapi);
8123
8124         /*
8125          * Turn off MSI one shot mode.  Otherwise this test has no
8126          * observable way to know whether the interrupt was delivered.
8127          */
8128         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8129             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8130                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8131                 tw32(MSGINT_MODE, val);
8132         }
8133
8134         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8135                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8136         if (err)
8137                 return err;
8138
8139         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8140         tg3_enable_ints(tp);
8141
8142         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8143                tnapi->coal_now);
8144
8145         for (i = 0; i < 5; i++) {
8146                 u32 int_mbox, misc_host_ctrl;
8147
8148                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8149                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8150
8151                 if ((int_mbox != 0) ||
8152                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8153                         intr_ok = 1;
8154                         break;
8155                 }
8156
8157                 msleep(10);
8158         }
8159
8160         tg3_disable_ints(tp);
8161
8162         free_irq(tnapi->irq_vec, tnapi);
8163
8164         err = tg3_request_irq(tp, 0);
8165
8166         if (err)
8167                 return err;
8168
8169         if (intr_ok) {
8170                 /* Reenable MSI one shot mode. */
8171                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8172                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8173                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8174                         tw32(MSGINT_MODE, val);
8175                 }
8176                 return 0;
8177         }
8178
8179         return -EIO;
8180 }
8181
8182 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8183  * successfully restored
8184  */
8185 static int tg3_test_msi(struct tg3 *tp)
8186 {
8187         int err;
8188         u16 pci_cmd;
8189
8190         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8191                 return 0;
8192
8193         /* Turn off SERR reporting in case MSI terminates with Master
8194          * Abort.
8195          */
8196         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8197         pci_write_config_word(tp->pdev, PCI_COMMAND,
8198                               pci_cmd & ~PCI_COMMAND_SERR);
8199
8200         err = tg3_test_interrupt(tp);
8201
8202         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8203
8204         if (!err)
8205                 return 0;
8206
8207         /* other failures */
8208         if (err != -EIO)
8209                 return err;
8210
8211         /* MSI test failed, go back to INTx mode */
8212         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8213                "switching to INTx mode. Please report this failure to "
8214                "the PCI maintainer and include system chipset information.\n",
8215                        tp->dev->name);
8216
8217         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8218
8219         pci_disable_msi(tp->pdev);
8220
8221         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8222
8223         err = tg3_request_irq(tp, 0);
8224         if (err)
8225                 return err;
8226
8227         /* Need to reset the chip because the MSI cycle may have terminated
8228          * with Master Abort.
8229          */
8230         tg3_full_lock(tp, 1);
8231
8232         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8233         err = tg3_init_hw(tp, 1);
8234
8235         tg3_full_unlock(tp);
8236
8237         if (err)
8238                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8239
8240         return err;
8241 }
8242
8243 static int tg3_request_firmware(struct tg3 *tp)
8244 {
8245         const __be32 *fw_data;
8246
8247         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8248                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8249                        tp->dev->name, tp->fw_needed);
8250                 return -ENOENT;
8251         }
8252
8253         fw_data = (void *)tp->fw->data;
8254
8255         /* Firmware blob starts with version numbers, followed by
8256          * start address and _full_ length including BSS sections
8257          * (which must be longer than the actual data, of course
8258          */
8259
8260         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8261         if (tp->fw_len < (tp->fw->size - 12)) {
8262                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8263                        tp->dev->name, tp->fw_len, tp->fw_needed);
8264                 release_firmware(tp->fw);
8265                 tp->fw = NULL;
8266                 return -EINVAL;
8267         }
8268
8269         /* We no longer need firmware; we have it. */
8270         tp->fw_needed = NULL;
8271         return 0;
8272 }
8273
8274 static bool tg3_enable_msix(struct tg3 *tp)
8275 {
8276         int i, rc, cpus = num_online_cpus();
8277         struct msix_entry msix_ent[tp->irq_max];
8278
8279         if (cpus == 1)
8280                 /* Just fallback to the simpler MSI mode. */
8281                 return false;
8282
8283         /*
8284          * We want as many rx rings enabled as there are cpus.
8285          * The first MSIX vector only deals with link interrupts, etc,
8286          * so we add one to the number of vectors we are requesting.
8287          */
8288         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8289
8290         for (i = 0; i < tp->irq_max; i++) {
8291                 msix_ent[i].entry  = i;
8292                 msix_ent[i].vector = 0;
8293         }
8294
8295         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8296         if (rc != 0) {
8297                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8298                         return false;
8299                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8300                         return false;
8301                 printk(KERN_NOTICE
8302                        "%s: Requested %d MSI-X vectors, received %d\n",
8303                        tp->dev->name, tp->irq_cnt, rc);
8304                 tp->irq_cnt = rc;
8305         }
8306
8307         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8308
8309         for (i = 0; i < tp->irq_max; i++)
8310                 tp->napi[i].irq_vec = msix_ent[i].vector;
8311
8312         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8313
8314         return true;
8315 }
8316
8317 static void tg3_ints_init(struct tg3 *tp)
8318 {
8319         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8320             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8321                 /* All MSI supporting chips should support tagged
8322                  * status.  Assert that this is the case.
8323                  */
8324                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8325                        "Not using MSI.\n", tp->dev->name);
8326                 goto defcfg;
8327         }
8328
8329         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8330                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8331         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8332                  pci_enable_msi(tp->pdev) == 0)
8333                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8334
8335         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8336                 u32 msi_mode = tr32(MSGINT_MODE);
8337                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8338                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8339                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8340         }
8341 defcfg:
8342         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8343                 tp->irq_cnt = 1;
8344                 tp->napi[0].irq_vec = tp->pdev->irq;
8345                 tp->dev->real_num_tx_queues = 1;
8346         }
8347 }
8348
8349 static void tg3_ints_fini(struct tg3 *tp)
8350 {
8351         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8352                 pci_disable_msix(tp->pdev);
8353         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8354                 pci_disable_msi(tp->pdev);
8355         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8356         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8357 }
8358
8359 static int tg3_open(struct net_device *dev)
8360 {
8361         struct tg3 *tp = netdev_priv(dev);
8362         int i, err;
8363
8364         if (tp->fw_needed) {
8365                 err = tg3_request_firmware(tp);
8366                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8367                         if (err)
8368                                 return err;
8369                 } else if (err) {
8370                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8371                                tp->dev->name);
8372                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8373                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8374                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8375                                tp->dev->name);
8376                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8377                 }
8378         }
8379
8380         netif_carrier_off(tp->dev);
8381
8382         err = tg3_set_power_state(tp, PCI_D0);
8383         if (err)
8384                 return err;
8385
8386         tg3_full_lock(tp, 0);
8387
8388         tg3_disable_ints(tp);
8389         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8390
8391         tg3_full_unlock(tp);
8392
8393         /*
8394          * Setup interrupts first so we know how
8395          * many NAPI resources to allocate
8396          */
8397         tg3_ints_init(tp);
8398
8399         /* The placement of this call is tied
8400          * to the setup and use of Host TX descriptors.
8401          */
8402         err = tg3_alloc_consistent(tp);
8403         if (err)
8404                 goto err_out1;
8405
8406         tg3_napi_enable(tp);
8407
8408         for (i = 0; i < tp->irq_cnt; i++) {
8409                 struct tg3_napi *tnapi = &tp->napi[i];
8410                 err = tg3_request_irq(tp, i);
8411                 if (err) {
8412                         for (i--; i >= 0; i--)
8413                                 free_irq(tnapi->irq_vec, tnapi);
8414                         break;
8415                 }
8416         }
8417
8418         if (err)
8419                 goto err_out2;
8420
8421         tg3_full_lock(tp, 0);
8422
8423         err = tg3_init_hw(tp, 1);
8424         if (err) {
8425                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8426                 tg3_free_rings(tp);
8427         } else {
8428                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8429                         tp->timer_offset = HZ;
8430                 else
8431                         tp->timer_offset = HZ / 10;
8432
8433                 BUG_ON(tp->timer_offset > HZ);
8434                 tp->timer_counter = tp->timer_multiplier =
8435                         (HZ / tp->timer_offset);
8436                 tp->asf_counter = tp->asf_multiplier =
8437                         ((HZ / tp->timer_offset) * 2);
8438
8439                 init_timer(&tp->timer);
8440                 tp->timer.expires = jiffies + tp->timer_offset;
8441                 tp->timer.data = (unsigned long) tp;
8442                 tp->timer.function = tg3_timer;
8443         }
8444
8445         tg3_full_unlock(tp);
8446
8447         if (err)
8448                 goto err_out3;
8449
8450         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8451                 err = tg3_test_msi(tp);
8452
8453                 if (err) {
8454                         tg3_full_lock(tp, 0);
8455                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8456                         tg3_free_rings(tp);
8457                         tg3_full_unlock(tp);
8458
8459                         goto err_out2;
8460                 }
8461
8462                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8463                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8464                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8465                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8466
8467                         tw32(PCIE_TRANSACTION_CFG,
8468                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8469                 }
8470         }
8471
8472         tg3_phy_start(tp);
8473
8474         tg3_full_lock(tp, 0);
8475
8476         add_timer(&tp->timer);
8477         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8478         tg3_enable_ints(tp);
8479
8480         tg3_full_unlock(tp);
8481
8482         netif_tx_start_all_queues(dev);
8483
8484         return 0;
8485
8486 err_out3:
8487         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8488                 struct tg3_napi *tnapi = &tp->napi[i];
8489                 free_irq(tnapi->irq_vec, tnapi);
8490         }
8491
8492 err_out2:
8493         tg3_napi_disable(tp);
8494         tg3_free_consistent(tp);
8495
8496 err_out1:
8497         tg3_ints_fini(tp);
8498         return err;
8499 }
8500
8501 #if 0
8502 /*static*/ void tg3_dump_state(struct tg3 *tp)
8503 {
8504         u32 val32, val32_2, val32_3, val32_4, val32_5;
8505         u16 val16;
8506         int i;
8507         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8508
8509         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8510         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8511         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8512                val16, val32);
8513
8514         /* MAC block */
8515         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8516                tr32(MAC_MODE), tr32(MAC_STATUS));
8517         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8518                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8519         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8520                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8521         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8522                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8523
8524         /* Send data initiator control block */
8525         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8526                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8527         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8528                tr32(SNDDATAI_STATSCTRL));
8529
8530         /* Send data completion control block */
8531         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8532
8533         /* Send BD ring selector block */
8534         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8535                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8536
8537         /* Send BD initiator control block */
8538         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8539                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8540
8541         /* Send BD completion control block */
8542         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8543
8544         /* Receive list placement control block */
8545         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8546                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8547         printk("       RCVLPC_STATSCTRL[%08x]\n",
8548                tr32(RCVLPC_STATSCTRL));
8549
8550         /* Receive data and receive BD initiator control block */
8551         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8552                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8553
8554         /* Receive data completion control block */
8555         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8556                tr32(RCVDCC_MODE));
8557
8558         /* Receive BD initiator control block */
8559         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8560                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8561
8562         /* Receive BD completion control block */
8563         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8564                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8565
8566         /* Receive list selector control block */
8567         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8568                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8569
8570         /* Mbuf cluster free block */
8571         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8572                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8573
8574         /* Host coalescing control block */
8575         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8576                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8577         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8578                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8579                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8580         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8581                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8582                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8583         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8584                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8585         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8586                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8587
8588         /* Memory arbiter control block */
8589         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8590                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8591
8592         /* Buffer manager control block */
8593         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8594                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8595         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8596                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8597         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8598                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8599                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8600                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8601
8602         /* Read DMA control block */
8603         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8604                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8605
8606         /* Write DMA control block */
8607         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8608                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8609
8610         /* DMA completion block */
8611         printk("DEBUG: DMAC_MODE[%08x]\n",
8612                tr32(DMAC_MODE));
8613
8614         /* GRC block */
8615         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8616                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8617         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8618                tr32(GRC_LOCAL_CTRL));
8619
8620         /* TG3_BDINFOs */
8621         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8622                tr32(RCVDBDI_JUMBO_BD + 0x0),
8623                tr32(RCVDBDI_JUMBO_BD + 0x4),
8624                tr32(RCVDBDI_JUMBO_BD + 0x8),
8625                tr32(RCVDBDI_JUMBO_BD + 0xc));
8626         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8627                tr32(RCVDBDI_STD_BD + 0x0),
8628                tr32(RCVDBDI_STD_BD + 0x4),
8629                tr32(RCVDBDI_STD_BD + 0x8),
8630                tr32(RCVDBDI_STD_BD + 0xc));
8631         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8632                tr32(RCVDBDI_MINI_BD + 0x0),
8633                tr32(RCVDBDI_MINI_BD + 0x4),
8634                tr32(RCVDBDI_MINI_BD + 0x8),
8635                tr32(RCVDBDI_MINI_BD + 0xc));
8636
8637         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8638         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8639         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8640         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8641         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8642                val32, val32_2, val32_3, val32_4);
8643
8644         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8645         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8646         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8647         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8648         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8649                val32, val32_2, val32_3, val32_4);
8650
8651         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8652         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8653         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8654         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8655         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8656         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8657                val32, val32_2, val32_3, val32_4, val32_5);
8658
8659         /* SW status block */
8660         printk(KERN_DEBUG
8661          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8662                sblk->status,
8663                sblk->status_tag,
8664                sblk->rx_jumbo_consumer,
8665                sblk->rx_consumer,
8666                sblk->rx_mini_consumer,
8667                sblk->idx[0].rx_producer,
8668                sblk->idx[0].tx_consumer);
8669
8670         /* SW statistics block */
8671         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8672                ((u32 *)tp->hw_stats)[0],
8673                ((u32 *)tp->hw_stats)[1],
8674                ((u32 *)tp->hw_stats)[2],
8675                ((u32 *)tp->hw_stats)[3]);
8676
8677         /* Mailboxes */
8678         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8679                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8680                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8681                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8682                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8683
8684         /* NIC side send descriptors. */
8685         for (i = 0; i < 6; i++) {
8686                 unsigned long txd;
8687
8688                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8689                         + (i * sizeof(struct tg3_tx_buffer_desc));
8690                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8691                        i,
8692                        readl(txd + 0x0), readl(txd + 0x4),
8693                        readl(txd + 0x8), readl(txd + 0xc));
8694         }
8695
8696         /* NIC side RX descriptors. */
8697         for (i = 0; i < 6; i++) {
8698                 unsigned long rxd;
8699
8700                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8701                         + (i * sizeof(struct tg3_rx_buffer_desc));
8702                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8703                        i,
8704                        readl(rxd + 0x0), readl(rxd + 0x4),
8705                        readl(rxd + 0x8), readl(rxd + 0xc));
8706                 rxd += (4 * sizeof(u32));
8707                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8708                        i,
8709                        readl(rxd + 0x0), readl(rxd + 0x4),
8710                        readl(rxd + 0x8), readl(rxd + 0xc));
8711         }
8712
8713         for (i = 0; i < 6; i++) {
8714                 unsigned long rxd;
8715
8716                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8717                         + (i * sizeof(struct tg3_rx_buffer_desc));
8718                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8719                        i,
8720                        readl(rxd + 0x0), readl(rxd + 0x4),
8721                        readl(rxd + 0x8), readl(rxd + 0xc));
8722                 rxd += (4 * sizeof(u32));
8723                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8724                        i,
8725                        readl(rxd + 0x0), readl(rxd + 0x4),
8726                        readl(rxd + 0x8), readl(rxd + 0xc));
8727         }
8728 }
8729 #endif
8730
8731 static struct net_device_stats *tg3_get_stats(struct net_device *);
8732 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8733
8734 static int tg3_close(struct net_device *dev)
8735 {
8736         int i;
8737         struct tg3 *tp = netdev_priv(dev);
8738
8739         tg3_napi_disable(tp);
8740         cancel_work_sync(&tp->reset_task);
8741
8742         netif_tx_stop_all_queues(dev);
8743
8744         del_timer_sync(&tp->timer);
8745
8746         tg3_phy_stop(tp);
8747
8748         tg3_full_lock(tp, 1);
8749 #if 0
8750         tg3_dump_state(tp);
8751 #endif
8752
8753         tg3_disable_ints(tp);
8754
8755         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8756         tg3_free_rings(tp);
8757         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8758
8759         tg3_full_unlock(tp);
8760
8761         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8762                 struct tg3_napi *tnapi = &tp->napi[i];
8763                 free_irq(tnapi->irq_vec, tnapi);
8764         }
8765
8766         tg3_ints_fini(tp);
8767
8768         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8769                sizeof(tp->net_stats_prev));
8770         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8771                sizeof(tp->estats_prev));
8772
8773         tg3_free_consistent(tp);
8774
8775         tg3_set_power_state(tp, PCI_D3hot);
8776
8777         netif_carrier_off(tp->dev);
8778
8779         return 0;
8780 }
8781
8782 static inline unsigned long get_stat64(tg3_stat64_t *val)
8783 {
8784         unsigned long ret;
8785
8786 #if (BITS_PER_LONG == 32)
8787         ret = val->low;
8788 #else
8789         ret = ((u64)val->high << 32) | ((u64)val->low);
8790 #endif
8791         return ret;
8792 }
8793
8794 static inline u64 get_estat64(tg3_stat64_t *val)
8795 {
8796        return ((u64)val->high << 32) | ((u64)val->low);
8797 }
8798
8799 static unsigned long calc_crc_errors(struct tg3 *tp)
8800 {
8801         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8802
8803         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8804             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8805              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8806                 u32 val;
8807
8808                 spin_lock_bh(&tp->lock);
8809                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8810                         tg3_writephy(tp, MII_TG3_TEST1,
8811                                      val | MII_TG3_TEST1_CRC_EN);
8812                         tg3_readphy(tp, 0x14, &val);
8813                 } else
8814                         val = 0;
8815                 spin_unlock_bh(&tp->lock);
8816
8817                 tp->phy_crc_errors += val;
8818
8819                 return tp->phy_crc_errors;
8820         }
8821
8822         return get_stat64(&hw_stats->rx_fcs_errors);
8823 }
8824
8825 #define ESTAT_ADD(member) \
8826         estats->member =        old_estats->member + \
8827                                 get_estat64(&hw_stats->member)
8828
8829 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8830 {
8831         struct tg3_ethtool_stats *estats = &tp->estats;
8832         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8833         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8834
8835         if (!hw_stats)
8836                 return old_estats;
8837
8838         ESTAT_ADD(rx_octets);
8839         ESTAT_ADD(rx_fragments);
8840         ESTAT_ADD(rx_ucast_packets);
8841         ESTAT_ADD(rx_mcast_packets);
8842         ESTAT_ADD(rx_bcast_packets);
8843         ESTAT_ADD(rx_fcs_errors);
8844         ESTAT_ADD(rx_align_errors);
8845         ESTAT_ADD(rx_xon_pause_rcvd);
8846         ESTAT_ADD(rx_xoff_pause_rcvd);
8847         ESTAT_ADD(rx_mac_ctrl_rcvd);
8848         ESTAT_ADD(rx_xoff_entered);
8849         ESTAT_ADD(rx_frame_too_long_errors);
8850         ESTAT_ADD(rx_jabbers);
8851         ESTAT_ADD(rx_undersize_packets);
8852         ESTAT_ADD(rx_in_length_errors);
8853         ESTAT_ADD(rx_out_length_errors);
8854         ESTAT_ADD(rx_64_or_less_octet_packets);
8855         ESTAT_ADD(rx_65_to_127_octet_packets);
8856         ESTAT_ADD(rx_128_to_255_octet_packets);
8857         ESTAT_ADD(rx_256_to_511_octet_packets);
8858         ESTAT_ADD(rx_512_to_1023_octet_packets);
8859         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8860         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8861         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8862         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8863         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8864
8865         ESTAT_ADD(tx_octets);
8866         ESTAT_ADD(tx_collisions);
8867         ESTAT_ADD(tx_xon_sent);
8868         ESTAT_ADD(tx_xoff_sent);
8869         ESTAT_ADD(tx_flow_control);
8870         ESTAT_ADD(tx_mac_errors);
8871         ESTAT_ADD(tx_single_collisions);
8872         ESTAT_ADD(tx_mult_collisions);
8873         ESTAT_ADD(tx_deferred);
8874         ESTAT_ADD(tx_excessive_collisions);
8875         ESTAT_ADD(tx_late_collisions);
8876         ESTAT_ADD(tx_collide_2times);
8877         ESTAT_ADD(tx_collide_3times);
8878         ESTAT_ADD(tx_collide_4times);
8879         ESTAT_ADD(tx_collide_5times);
8880         ESTAT_ADD(tx_collide_6times);
8881         ESTAT_ADD(tx_collide_7times);
8882         ESTAT_ADD(tx_collide_8times);
8883         ESTAT_ADD(tx_collide_9times);
8884         ESTAT_ADD(tx_collide_10times);
8885         ESTAT_ADD(tx_collide_11times);
8886         ESTAT_ADD(tx_collide_12times);
8887         ESTAT_ADD(tx_collide_13times);
8888         ESTAT_ADD(tx_collide_14times);
8889         ESTAT_ADD(tx_collide_15times);
8890         ESTAT_ADD(tx_ucast_packets);
8891         ESTAT_ADD(tx_mcast_packets);
8892         ESTAT_ADD(tx_bcast_packets);
8893         ESTAT_ADD(tx_carrier_sense_errors);
8894         ESTAT_ADD(tx_discards);
8895         ESTAT_ADD(tx_errors);
8896
8897         ESTAT_ADD(dma_writeq_full);
8898         ESTAT_ADD(dma_write_prioq_full);
8899         ESTAT_ADD(rxbds_empty);
8900         ESTAT_ADD(rx_discards);
8901         ESTAT_ADD(rx_errors);
8902         ESTAT_ADD(rx_threshold_hit);
8903
8904         ESTAT_ADD(dma_readq_full);
8905         ESTAT_ADD(dma_read_prioq_full);
8906         ESTAT_ADD(tx_comp_queue_full);
8907
8908         ESTAT_ADD(ring_set_send_prod_index);
8909         ESTAT_ADD(ring_status_update);
8910         ESTAT_ADD(nic_irqs);
8911         ESTAT_ADD(nic_avoided_irqs);
8912         ESTAT_ADD(nic_tx_threshold_hit);
8913
8914         return estats;
8915 }
8916
8917 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8918 {
8919         struct tg3 *tp = netdev_priv(dev);
8920         struct net_device_stats *stats = &tp->net_stats;
8921         struct net_device_stats *old_stats = &tp->net_stats_prev;
8922         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8923
8924         if (!hw_stats)
8925                 return old_stats;
8926
8927         stats->rx_packets = old_stats->rx_packets +
8928                 get_stat64(&hw_stats->rx_ucast_packets) +
8929                 get_stat64(&hw_stats->rx_mcast_packets) +
8930                 get_stat64(&hw_stats->rx_bcast_packets);
8931
8932         stats->tx_packets = old_stats->tx_packets +
8933                 get_stat64(&hw_stats->tx_ucast_packets) +
8934                 get_stat64(&hw_stats->tx_mcast_packets) +
8935                 get_stat64(&hw_stats->tx_bcast_packets);
8936
8937         stats->rx_bytes = old_stats->rx_bytes +
8938                 get_stat64(&hw_stats->rx_octets);
8939         stats->tx_bytes = old_stats->tx_bytes +
8940                 get_stat64(&hw_stats->tx_octets);
8941
8942         stats->rx_errors = old_stats->rx_errors +
8943                 get_stat64(&hw_stats->rx_errors);
8944         stats->tx_errors = old_stats->tx_errors +
8945                 get_stat64(&hw_stats->tx_errors) +
8946                 get_stat64(&hw_stats->tx_mac_errors) +
8947                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8948                 get_stat64(&hw_stats->tx_discards);
8949
8950         stats->multicast = old_stats->multicast +
8951                 get_stat64(&hw_stats->rx_mcast_packets);
8952         stats->collisions = old_stats->collisions +
8953                 get_stat64(&hw_stats->tx_collisions);
8954
8955         stats->rx_length_errors = old_stats->rx_length_errors +
8956                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8957                 get_stat64(&hw_stats->rx_undersize_packets);
8958
8959         stats->rx_over_errors = old_stats->rx_over_errors +
8960                 get_stat64(&hw_stats->rxbds_empty);
8961         stats->rx_frame_errors = old_stats->rx_frame_errors +
8962                 get_stat64(&hw_stats->rx_align_errors);
8963         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8964                 get_stat64(&hw_stats->tx_discards);
8965         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8966                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8967
8968         stats->rx_crc_errors = old_stats->rx_crc_errors +
8969                 calc_crc_errors(tp);
8970
8971         stats->rx_missed_errors = old_stats->rx_missed_errors +
8972                 get_stat64(&hw_stats->rx_discards);
8973
8974         return stats;
8975 }
8976
8977 static inline u32 calc_crc(unsigned char *buf, int len)
8978 {
8979         u32 reg;
8980         u32 tmp;
8981         int j, k;
8982
8983         reg = 0xffffffff;
8984
8985         for (j = 0; j < len; j++) {
8986                 reg ^= buf[j];
8987
8988                 for (k = 0; k < 8; k++) {
8989                         tmp = reg & 0x01;
8990
8991                         reg >>= 1;
8992
8993                         if (tmp) {
8994                                 reg ^= 0xedb88320;
8995                         }
8996                 }
8997         }
8998
8999         return ~reg;
9000 }
9001
9002 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9003 {
9004         /* accept or reject all multicast frames */
9005         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9006         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9007         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9008         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9009 }
9010
9011 static void __tg3_set_rx_mode(struct net_device *dev)
9012 {
9013         struct tg3 *tp = netdev_priv(dev);
9014         u32 rx_mode;
9015
9016         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9017                                   RX_MODE_KEEP_VLAN_TAG);
9018
9019         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9020          * flag clear.
9021          */
9022 #if TG3_VLAN_TAG_USED
9023         if (!tp->vlgrp &&
9024             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9025                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9026 #else
9027         /* By definition, VLAN is disabled always in this
9028          * case.
9029          */
9030         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9031                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9032 #endif
9033
9034         if (dev->flags & IFF_PROMISC) {
9035                 /* Promiscuous mode. */
9036                 rx_mode |= RX_MODE_PROMISC;
9037         } else if (dev->flags & IFF_ALLMULTI) {
9038                 /* Accept all multicast. */
9039                 tg3_set_multi (tp, 1);
9040         } else if (dev->mc_count < 1) {
9041                 /* Reject all multicast. */
9042                 tg3_set_multi (tp, 0);
9043         } else {
9044                 /* Accept one or more multicast(s). */
9045                 struct dev_mc_list *mclist;
9046                 unsigned int i;
9047                 u32 mc_filter[4] = { 0, };
9048                 u32 regidx;
9049                 u32 bit;
9050                 u32 crc;
9051
9052                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9053                      i++, mclist = mclist->next) {
9054
9055                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9056                         bit = ~crc & 0x7f;
9057                         regidx = (bit & 0x60) >> 5;
9058                         bit &= 0x1f;
9059                         mc_filter[regidx] |= (1 << bit);
9060                 }
9061
9062                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9063                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9064                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9065                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9066         }
9067
9068         if (rx_mode != tp->rx_mode) {
9069                 tp->rx_mode = rx_mode;
9070                 tw32_f(MAC_RX_MODE, rx_mode);
9071                 udelay(10);
9072         }
9073 }
9074
9075 static void tg3_set_rx_mode(struct net_device *dev)
9076 {
9077         struct tg3 *tp = netdev_priv(dev);
9078
9079         if (!netif_running(dev))
9080                 return;
9081
9082         tg3_full_lock(tp, 0);
9083         __tg3_set_rx_mode(dev);
9084         tg3_full_unlock(tp);
9085 }
9086
9087 #define TG3_REGDUMP_LEN         (32 * 1024)
9088
9089 static int tg3_get_regs_len(struct net_device *dev)
9090 {
9091         return TG3_REGDUMP_LEN;
9092 }
9093
9094 static void tg3_get_regs(struct net_device *dev,
9095                 struct ethtool_regs *regs, void *_p)
9096 {
9097         u32 *p = _p;
9098         struct tg3 *tp = netdev_priv(dev);
9099         u8 *orig_p = _p;
9100         int i;
9101
9102         regs->version = 0;
9103
9104         memset(p, 0, TG3_REGDUMP_LEN);
9105
9106         if (tp->link_config.phy_is_low_power)
9107                 return;
9108
9109         tg3_full_lock(tp, 0);
9110
9111 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9112 #define GET_REG32_LOOP(base,len)                \
9113 do {    p = (u32 *)(orig_p + (base));           \
9114         for (i = 0; i < len; i += 4)            \
9115                 __GET_REG32((base) + i);        \
9116 } while (0)
9117 #define GET_REG32_1(reg)                        \
9118 do {    p = (u32 *)(orig_p + (reg));            \
9119         __GET_REG32((reg));                     \
9120 } while (0)
9121
9122         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9123         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9124         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9125         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9126         GET_REG32_1(SNDDATAC_MODE);
9127         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9128         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9129         GET_REG32_1(SNDBDC_MODE);
9130         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9131         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9132         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9133         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9134         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9135         GET_REG32_1(RCVDCC_MODE);
9136         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9137         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9138         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9139         GET_REG32_1(MBFREE_MODE);
9140         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9141         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9142         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9143         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9144         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9145         GET_REG32_1(RX_CPU_MODE);
9146         GET_REG32_1(RX_CPU_STATE);
9147         GET_REG32_1(RX_CPU_PGMCTR);
9148         GET_REG32_1(RX_CPU_HWBKPT);
9149         GET_REG32_1(TX_CPU_MODE);
9150         GET_REG32_1(TX_CPU_STATE);
9151         GET_REG32_1(TX_CPU_PGMCTR);
9152         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9153         GET_REG32_LOOP(FTQ_RESET, 0x120);
9154         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9155         GET_REG32_1(DMAC_MODE);
9156         GET_REG32_LOOP(GRC_MODE, 0x4c);
9157         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9158                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9159
9160 #undef __GET_REG32
9161 #undef GET_REG32_LOOP
9162 #undef GET_REG32_1
9163
9164         tg3_full_unlock(tp);
9165 }
9166
9167 static int tg3_get_eeprom_len(struct net_device *dev)
9168 {
9169         struct tg3 *tp = netdev_priv(dev);
9170
9171         return tp->nvram_size;
9172 }
9173
9174 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9175 {
9176         struct tg3 *tp = netdev_priv(dev);
9177         int ret;
9178         u8  *pd;
9179         u32 i, offset, len, b_offset, b_count;
9180         __be32 val;
9181
9182         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9183                 return -EINVAL;
9184
9185         if (tp->link_config.phy_is_low_power)
9186                 return -EAGAIN;
9187
9188         offset = eeprom->offset;
9189         len = eeprom->len;
9190         eeprom->len = 0;
9191
9192         eeprom->magic = TG3_EEPROM_MAGIC;
9193
9194         if (offset & 3) {
9195                 /* adjustments to start on required 4 byte boundary */
9196                 b_offset = offset & 3;
9197                 b_count = 4 - b_offset;
9198                 if (b_count > len) {
9199                         /* i.e. offset=1 len=2 */
9200                         b_count = len;
9201                 }
9202                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9203                 if (ret)
9204                         return ret;
9205                 memcpy(data, ((char*)&val) + b_offset, b_count);
9206                 len -= b_count;
9207                 offset += b_count;
9208                 eeprom->len += b_count;
9209         }
9210
9211         /* read bytes upto the last 4 byte boundary */
9212         pd = &data[eeprom->len];
9213         for (i = 0; i < (len - (len & 3)); i += 4) {
9214                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9215                 if (ret) {
9216                         eeprom->len += i;
9217                         return ret;
9218                 }
9219                 memcpy(pd + i, &val, 4);
9220         }
9221         eeprom->len += i;
9222
9223         if (len & 3) {
9224                 /* read last bytes not ending on 4 byte boundary */
9225                 pd = &data[eeprom->len];
9226                 b_count = len & 3;
9227                 b_offset = offset + len - b_count;
9228                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9229                 if (ret)
9230                         return ret;
9231                 memcpy(pd, &val, b_count);
9232                 eeprom->len += b_count;
9233         }
9234         return 0;
9235 }
9236
9237 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9238
9239 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9240 {
9241         struct tg3 *tp = netdev_priv(dev);
9242         int ret;
9243         u32 offset, len, b_offset, odd_len;
9244         u8 *buf;
9245         __be32 start, end;
9246
9247         if (tp->link_config.phy_is_low_power)
9248                 return -EAGAIN;
9249
9250         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9251             eeprom->magic != TG3_EEPROM_MAGIC)
9252                 return -EINVAL;
9253
9254         offset = eeprom->offset;
9255         len = eeprom->len;
9256
9257         if ((b_offset = (offset & 3))) {
9258                 /* adjustments to start on required 4 byte boundary */
9259                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9260                 if (ret)
9261                         return ret;
9262                 len += b_offset;
9263                 offset &= ~3;
9264                 if (len < 4)
9265                         len = 4;
9266         }
9267
9268         odd_len = 0;
9269         if (len & 3) {
9270                 /* adjustments to end on required 4 byte boundary */
9271                 odd_len = 1;
9272                 len = (len + 3) & ~3;
9273                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9274                 if (ret)
9275                         return ret;
9276         }
9277
9278         buf = data;
9279         if (b_offset || odd_len) {
9280                 buf = kmalloc(len, GFP_KERNEL);
9281                 if (!buf)
9282                         return -ENOMEM;
9283                 if (b_offset)
9284                         memcpy(buf, &start, 4);
9285                 if (odd_len)
9286                         memcpy(buf+len-4, &end, 4);
9287                 memcpy(buf + b_offset, data, eeprom->len);
9288         }
9289
9290         ret = tg3_nvram_write_block(tp, offset, len, buf);
9291
9292         if (buf != data)
9293                 kfree(buf);
9294
9295         return ret;
9296 }
9297
9298 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9299 {
9300         struct tg3 *tp = netdev_priv(dev);
9301
9302         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9303                 struct phy_device *phydev;
9304                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9305                         return -EAGAIN;
9306                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9307                 return phy_ethtool_gset(phydev, cmd);
9308         }
9309
9310         cmd->supported = (SUPPORTED_Autoneg);
9311
9312         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9313                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9314                                    SUPPORTED_1000baseT_Full);
9315
9316         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9317                 cmd->supported |= (SUPPORTED_100baseT_Half |
9318                                   SUPPORTED_100baseT_Full |
9319                                   SUPPORTED_10baseT_Half |
9320                                   SUPPORTED_10baseT_Full |
9321                                   SUPPORTED_TP);
9322                 cmd->port = PORT_TP;
9323         } else {
9324                 cmd->supported |= SUPPORTED_FIBRE;
9325                 cmd->port = PORT_FIBRE;
9326         }
9327
9328         cmd->advertising = tp->link_config.advertising;
9329         if (netif_running(dev)) {
9330                 cmd->speed = tp->link_config.active_speed;
9331                 cmd->duplex = tp->link_config.active_duplex;
9332         }
9333         cmd->phy_address = tp->phy_addr;
9334         cmd->transceiver = XCVR_INTERNAL;
9335         cmd->autoneg = tp->link_config.autoneg;
9336         cmd->maxtxpkt = 0;
9337         cmd->maxrxpkt = 0;
9338         return 0;
9339 }
9340
9341 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9342 {
9343         struct tg3 *tp = netdev_priv(dev);
9344
9345         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9346                 struct phy_device *phydev;
9347                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9348                         return -EAGAIN;
9349                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9350                 return phy_ethtool_sset(phydev, cmd);
9351         }
9352
9353         if (cmd->autoneg != AUTONEG_ENABLE &&
9354             cmd->autoneg != AUTONEG_DISABLE)
9355                 return -EINVAL;
9356
9357         if (cmd->autoneg == AUTONEG_DISABLE &&
9358             cmd->duplex != DUPLEX_FULL &&
9359             cmd->duplex != DUPLEX_HALF)
9360                 return -EINVAL;
9361
9362         if (cmd->autoneg == AUTONEG_ENABLE) {
9363                 u32 mask = ADVERTISED_Autoneg |
9364                            ADVERTISED_Pause |
9365                            ADVERTISED_Asym_Pause;
9366
9367                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9368                         mask |= ADVERTISED_1000baseT_Half |
9369                                 ADVERTISED_1000baseT_Full;
9370
9371                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9372                         mask |= ADVERTISED_100baseT_Half |
9373                                 ADVERTISED_100baseT_Full |
9374                                 ADVERTISED_10baseT_Half |
9375                                 ADVERTISED_10baseT_Full |
9376                                 ADVERTISED_TP;
9377                 else
9378                         mask |= ADVERTISED_FIBRE;
9379
9380                 if (cmd->advertising & ~mask)
9381                         return -EINVAL;
9382
9383                 mask &= (ADVERTISED_1000baseT_Half |
9384                          ADVERTISED_1000baseT_Full |
9385                          ADVERTISED_100baseT_Half |
9386                          ADVERTISED_100baseT_Full |
9387                          ADVERTISED_10baseT_Half |
9388                          ADVERTISED_10baseT_Full);
9389
9390                 cmd->advertising &= mask;
9391         } else {
9392                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9393                         if (cmd->speed != SPEED_1000)
9394                                 return -EINVAL;
9395
9396                         if (cmd->duplex != DUPLEX_FULL)
9397                                 return -EINVAL;
9398                 } else {
9399                         if (cmd->speed != SPEED_100 &&
9400                             cmd->speed != SPEED_10)
9401                                 return -EINVAL;
9402                 }
9403         }
9404
9405         tg3_full_lock(tp, 0);
9406
9407         tp->link_config.autoneg = cmd->autoneg;
9408         if (cmd->autoneg == AUTONEG_ENABLE) {
9409                 tp->link_config.advertising = (cmd->advertising |
9410                                               ADVERTISED_Autoneg);
9411                 tp->link_config.speed = SPEED_INVALID;
9412                 tp->link_config.duplex = DUPLEX_INVALID;
9413         } else {
9414                 tp->link_config.advertising = 0;
9415                 tp->link_config.speed = cmd->speed;
9416                 tp->link_config.duplex = cmd->duplex;
9417         }
9418
9419         tp->link_config.orig_speed = tp->link_config.speed;
9420         tp->link_config.orig_duplex = tp->link_config.duplex;
9421         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9422
9423         if (netif_running(dev))
9424                 tg3_setup_phy(tp, 1);
9425
9426         tg3_full_unlock(tp);
9427
9428         return 0;
9429 }
9430
9431 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9432 {
9433         struct tg3 *tp = netdev_priv(dev);
9434
9435         strcpy(info->driver, DRV_MODULE_NAME);
9436         strcpy(info->version, DRV_MODULE_VERSION);
9437         strcpy(info->fw_version, tp->fw_ver);
9438         strcpy(info->bus_info, pci_name(tp->pdev));
9439 }
9440
9441 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9442 {
9443         struct tg3 *tp = netdev_priv(dev);
9444
9445         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9446             device_can_wakeup(&tp->pdev->dev))
9447                 wol->supported = WAKE_MAGIC;
9448         else
9449                 wol->supported = 0;
9450         wol->wolopts = 0;
9451         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9452             device_can_wakeup(&tp->pdev->dev))
9453                 wol->wolopts = WAKE_MAGIC;
9454         memset(&wol->sopass, 0, sizeof(wol->sopass));
9455 }
9456
9457 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9458 {
9459         struct tg3 *tp = netdev_priv(dev);
9460         struct device *dp = &tp->pdev->dev;
9461
9462         if (wol->wolopts & ~WAKE_MAGIC)
9463                 return -EINVAL;
9464         if ((wol->wolopts & WAKE_MAGIC) &&
9465             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9466                 return -EINVAL;
9467
9468         spin_lock_bh(&tp->lock);
9469         if (wol->wolopts & WAKE_MAGIC) {
9470                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9471                 device_set_wakeup_enable(dp, true);
9472         } else {
9473                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9474                 device_set_wakeup_enable(dp, false);
9475         }
9476         spin_unlock_bh(&tp->lock);
9477
9478         return 0;
9479 }
9480
9481 static u32 tg3_get_msglevel(struct net_device *dev)
9482 {
9483         struct tg3 *tp = netdev_priv(dev);
9484         return tp->msg_enable;
9485 }
9486
9487 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9488 {
9489         struct tg3 *tp = netdev_priv(dev);
9490         tp->msg_enable = value;
9491 }
9492
9493 static int tg3_set_tso(struct net_device *dev, u32 value)
9494 {
9495         struct tg3 *tp = netdev_priv(dev);
9496
9497         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9498                 if (value)
9499                         return -EINVAL;
9500                 return 0;
9501         }
9502         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9503             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9504                 if (value) {
9505                         dev->features |= NETIF_F_TSO6;
9506                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9507                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9508                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9509                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9510                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9511                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9512                                 dev->features |= NETIF_F_TSO_ECN;
9513                 } else
9514                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9515         }
9516         return ethtool_op_set_tso(dev, value);
9517 }
9518
9519 static int tg3_nway_reset(struct net_device *dev)
9520 {
9521         struct tg3 *tp = netdev_priv(dev);
9522         int r;
9523
9524         if (!netif_running(dev))
9525                 return -EAGAIN;
9526
9527         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9528                 return -EINVAL;
9529
9530         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9531                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9532                         return -EAGAIN;
9533                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9534         } else {
9535                 u32 bmcr;
9536
9537                 spin_lock_bh(&tp->lock);
9538                 r = -EINVAL;
9539                 tg3_readphy(tp, MII_BMCR, &bmcr);
9540                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9541                     ((bmcr & BMCR_ANENABLE) ||
9542                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9543                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9544                                                    BMCR_ANENABLE);
9545                         r = 0;
9546                 }
9547                 spin_unlock_bh(&tp->lock);
9548         }
9549
9550         return r;
9551 }
9552
9553 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9554 {
9555         struct tg3 *tp = netdev_priv(dev);
9556
9557         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9558         ering->rx_mini_max_pending = 0;
9559         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9560                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9561         else
9562                 ering->rx_jumbo_max_pending = 0;
9563
9564         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9565
9566         ering->rx_pending = tp->rx_pending;
9567         ering->rx_mini_pending = 0;
9568         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9569                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9570         else
9571                 ering->rx_jumbo_pending = 0;
9572
9573         ering->tx_pending = tp->napi[0].tx_pending;
9574 }
9575
9576 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9577 {
9578         struct tg3 *tp = netdev_priv(dev);
9579         int i, irq_sync = 0, err = 0;
9580
9581         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9582             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9583             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9584             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9585             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9586              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9587                 return -EINVAL;
9588
9589         if (netif_running(dev)) {
9590                 tg3_phy_stop(tp);
9591                 tg3_netif_stop(tp);
9592                 irq_sync = 1;
9593         }
9594
9595         tg3_full_lock(tp, irq_sync);
9596
9597         tp->rx_pending = ering->rx_pending;
9598
9599         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9600             tp->rx_pending > 63)
9601                 tp->rx_pending = 63;
9602         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9603
9604         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9605                 tp->napi[i].tx_pending = ering->tx_pending;
9606
9607         if (netif_running(dev)) {
9608                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9609                 err = tg3_restart_hw(tp, 1);
9610                 if (!err)
9611                         tg3_netif_start(tp);
9612         }
9613
9614         tg3_full_unlock(tp);
9615
9616         if (irq_sync && !err)
9617                 tg3_phy_start(tp);
9618
9619         return err;
9620 }
9621
9622 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9623 {
9624         struct tg3 *tp = netdev_priv(dev);
9625
9626         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9627
9628         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9629                 epause->rx_pause = 1;
9630         else
9631                 epause->rx_pause = 0;
9632
9633         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9634                 epause->tx_pause = 1;
9635         else
9636                 epause->tx_pause = 0;
9637 }
9638
9639 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9640 {
9641         struct tg3 *tp = netdev_priv(dev);
9642         int err = 0;
9643
9644         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9645                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9646                         return -EAGAIN;
9647
9648                 if (epause->autoneg) {
9649                         u32 newadv;
9650                         struct phy_device *phydev;
9651
9652                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9653
9654                         if (epause->rx_pause) {
9655                                 if (epause->tx_pause)
9656                                         newadv = ADVERTISED_Pause;
9657                                 else
9658                                         newadv = ADVERTISED_Pause |
9659                                                  ADVERTISED_Asym_Pause;
9660                         } else if (epause->tx_pause) {
9661                                 newadv = ADVERTISED_Asym_Pause;
9662                         } else
9663                                 newadv = 0;
9664
9665                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9666                                 u32 oldadv = phydev->advertising &
9667                                              (ADVERTISED_Pause |
9668                                               ADVERTISED_Asym_Pause);
9669                                 if (oldadv != newadv) {
9670                                         phydev->advertising &=
9671                                                 ~(ADVERTISED_Pause |
9672                                                   ADVERTISED_Asym_Pause);
9673                                         phydev->advertising |= newadv;
9674                                         err = phy_start_aneg(phydev);
9675                                 }
9676                         } else {
9677                                 tp->link_config.advertising &=
9678                                                 ~(ADVERTISED_Pause |
9679                                                   ADVERTISED_Asym_Pause);
9680                                 tp->link_config.advertising |= newadv;
9681                         }
9682                 } else {
9683                         if (epause->rx_pause)
9684                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9685                         else
9686                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9687
9688                         if (epause->tx_pause)
9689                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9690                         else
9691                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9692
9693                         if (netif_running(dev))
9694                                 tg3_setup_flow_control(tp, 0, 0);
9695                 }
9696         } else {
9697                 int irq_sync = 0;
9698
9699                 if (netif_running(dev)) {
9700                         tg3_netif_stop(tp);
9701                         irq_sync = 1;
9702                 }
9703
9704                 tg3_full_lock(tp, irq_sync);
9705
9706                 if (epause->autoneg)
9707                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9708                 else
9709                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9710                 if (epause->rx_pause)
9711                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9712                 else
9713                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9714                 if (epause->tx_pause)
9715                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9716                 else
9717                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9718
9719                 if (netif_running(dev)) {
9720                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9721                         err = tg3_restart_hw(tp, 1);
9722                         if (!err)
9723                                 tg3_netif_start(tp);
9724                 }
9725
9726                 tg3_full_unlock(tp);
9727         }
9728
9729         return err;
9730 }
9731
9732 static u32 tg3_get_rx_csum(struct net_device *dev)
9733 {
9734         struct tg3 *tp = netdev_priv(dev);
9735         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9736 }
9737
9738 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9739 {
9740         struct tg3 *tp = netdev_priv(dev);
9741
9742         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9743                 if (data != 0)
9744                         return -EINVAL;
9745                 return 0;
9746         }
9747
9748         spin_lock_bh(&tp->lock);
9749         if (data)
9750                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9751         else
9752                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9753         spin_unlock_bh(&tp->lock);
9754
9755         return 0;
9756 }
9757
9758 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9759 {
9760         struct tg3 *tp = netdev_priv(dev);
9761
9762         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9763                 if (data != 0)
9764                         return -EINVAL;
9765                 return 0;
9766         }
9767
9768         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9769                 ethtool_op_set_tx_ipv6_csum(dev, data);
9770         else
9771                 ethtool_op_set_tx_csum(dev, data);
9772
9773         return 0;
9774 }
9775
9776 static int tg3_get_sset_count (struct net_device *dev, int sset)
9777 {
9778         switch (sset) {
9779         case ETH_SS_TEST:
9780                 return TG3_NUM_TEST;
9781         case ETH_SS_STATS:
9782                 return TG3_NUM_STATS;
9783         default:
9784                 return -EOPNOTSUPP;
9785         }
9786 }
9787
9788 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9789 {
9790         switch (stringset) {
9791         case ETH_SS_STATS:
9792                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9793                 break;
9794         case ETH_SS_TEST:
9795                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9796                 break;
9797         default:
9798                 WARN_ON(1);     /* we need a WARN() */
9799                 break;
9800         }
9801 }
9802
9803 static int tg3_phys_id(struct net_device *dev, u32 data)
9804 {
9805         struct tg3 *tp = netdev_priv(dev);
9806         int i;
9807
9808         if (!netif_running(tp->dev))
9809                 return -EAGAIN;
9810
9811         if (data == 0)
9812                 data = UINT_MAX / 2;
9813
9814         for (i = 0; i < (data * 2); i++) {
9815                 if ((i % 2) == 0)
9816                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9817                                            LED_CTRL_1000MBPS_ON |
9818                                            LED_CTRL_100MBPS_ON |
9819                                            LED_CTRL_10MBPS_ON |
9820                                            LED_CTRL_TRAFFIC_OVERRIDE |
9821                                            LED_CTRL_TRAFFIC_BLINK |
9822                                            LED_CTRL_TRAFFIC_LED);
9823
9824                 else
9825                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9826                                            LED_CTRL_TRAFFIC_OVERRIDE);
9827
9828                 if (msleep_interruptible(500))
9829                         break;
9830         }
9831         tw32(MAC_LED_CTRL, tp->led_ctrl);
9832         return 0;
9833 }
9834
9835 static void tg3_get_ethtool_stats (struct net_device *dev,
9836                                    struct ethtool_stats *estats, u64 *tmp_stats)
9837 {
9838         struct tg3 *tp = netdev_priv(dev);
9839         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9840 }
9841
9842 #define NVRAM_TEST_SIZE 0x100
9843 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9844 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9845 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9846 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9847 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9848
9849 static int tg3_test_nvram(struct tg3 *tp)
9850 {
9851         u32 csum, magic;
9852         __be32 *buf;
9853         int i, j, k, err = 0, size;
9854
9855         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9856                 return 0;
9857
9858         if (tg3_nvram_read(tp, 0, &magic) != 0)
9859                 return -EIO;
9860
9861         if (magic == TG3_EEPROM_MAGIC)
9862                 size = NVRAM_TEST_SIZE;
9863         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9864                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9865                     TG3_EEPROM_SB_FORMAT_1) {
9866                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9867                         case TG3_EEPROM_SB_REVISION_0:
9868                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9869                                 break;
9870                         case TG3_EEPROM_SB_REVISION_2:
9871                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9872                                 break;
9873                         case TG3_EEPROM_SB_REVISION_3:
9874                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9875                                 break;
9876                         default:
9877                                 return 0;
9878                         }
9879                 } else
9880                         return 0;
9881         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9882                 size = NVRAM_SELFBOOT_HW_SIZE;
9883         else
9884                 return -EIO;
9885
9886         buf = kmalloc(size, GFP_KERNEL);
9887         if (buf == NULL)
9888                 return -ENOMEM;
9889
9890         err = -EIO;
9891         for (i = 0, j = 0; i < size; i += 4, j++) {
9892                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9893                 if (err)
9894                         break;
9895         }
9896         if (i < size)
9897                 goto out;
9898
9899         /* Selfboot format */
9900         magic = be32_to_cpu(buf[0]);
9901         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9902             TG3_EEPROM_MAGIC_FW) {
9903                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9904
9905                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9906                     TG3_EEPROM_SB_REVISION_2) {
9907                         /* For rev 2, the csum doesn't include the MBA. */
9908                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9909                                 csum8 += buf8[i];
9910                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9911                                 csum8 += buf8[i];
9912                 } else {
9913                         for (i = 0; i < size; i++)
9914                                 csum8 += buf8[i];
9915                 }
9916
9917                 if (csum8 == 0) {
9918                         err = 0;
9919                         goto out;
9920                 }
9921
9922                 err = -EIO;
9923                 goto out;
9924         }
9925
9926         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9927             TG3_EEPROM_MAGIC_HW) {
9928                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9929                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9930                 u8 *buf8 = (u8 *) buf;
9931
9932                 /* Separate the parity bits and the data bytes.  */
9933                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9934                         if ((i == 0) || (i == 8)) {
9935                                 int l;
9936                                 u8 msk;
9937
9938                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9939                                         parity[k++] = buf8[i] & msk;
9940                                 i++;
9941                         }
9942                         else if (i == 16) {
9943                                 int l;
9944                                 u8 msk;
9945
9946                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9947                                         parity[k++] = buf8[i] & msk;
9948                                 i++;
9949
9950                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9951                                         parity[k++] = buf8[i] & msk;
9952                                 i++;
9953                         }
9954                         data[j++] = buf8[i];
9955                 }
9956
9957                 err = -EIO;
9958                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9959                         u8 hw8 = hweight8(data[i]);
9960
9961                         if ((hw8 & 0x1) && parity[i])
9962                                 goto out;
9963                         else if (!(hw8 & 0x1) && !parity[i])
9964                                 goto out;
9965                 }
9966                 err = 0;
9967                 goto out;
9968         }
9969
9970         /* Bootstrap checksum at offset 0x10 */
9971         csum = calc_crc((unsigned char *) buf, 0x10);
9972         if (csum != be32_to_cpu(buf[0x10/4]))
9973                 goto out;
9974
9975         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9976         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9977         if (csum != be32_to_cpu(buf[0xfc/4]))
9978                 goto out;
9979
9980         err = 0;
9981
9982 out:
9983         kfree(buf);
9984         return err;
9985 }
9986
9987 #define TG3_SERDES_TIMEOUT_SEC  2
9988 #define TG3_COPPER_TIMEOUT_SEC  6
9989
9990 static int tg3_test_link(struct tg3 *tp)
9991 {
9992         int i, max;
9993
9994         if (!netif_running(tp->dev))
9995                 return -ENODEV;
9996
9997         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9998                 max = TG3_SERDES_TIMEOUT_SEC;
9999         else
10000                 max = TG3_COPPER_TIMEOUT_SEC;
10001
10002         for (i = 0; i < max; i++) {
10003                 if (netif_carrier_ok(tp->dev))
10004                         return 0;
10005
10006                 if (msleep_interruptible(1000))
10007                         break;
10008         }
10009
10010         return -EIO;
10011 }
10012
10013 /* Only test the commonly used registers */
10014 static int tg3_test_registers(struct tg3 *tp)
10015 {
10016         int i, is_5705, is_5750;
10017         u32 offset, read_mask, write_mask, val, save_val, read_val;
10018         static struct {
10019                 u16 offset;
10020                 u16 flags;
10021 #define TG3_FL_5705     0x1
10022 #define TG3_FL_NOT_5705 0x2
10023 #define TG3_FL_NOT_5788 0x4
10024 #define TG3_FL_NOT_5750 0x8
10025                 u32 read_mask;
10026                 u32 write_mask;
10027         } reg_tbl[] = {
10028                 /* MAC Control Registers */
10029                 { MAC_MODE, TG3_FL_NOT_5705,
10030                         0x00000000, 0x00ef6f8c },
10031                 { MAC_MODE, TG3_FL_5705,
10032                         0x00000000, 0x01ef6b8c },
10033                 { MAC_STATUS, TG3_FL_NOT_5705,
10034                         0x03800107, 0x00000000 },
10035                 { MAC_STATUS, TG3_FL_5705,
10036                         0x03800100, 0x00000000 },
10037                 { MAC_ADDR_0_HIGH, 0x0000,
10038                         0x00000000, 0x0000ffff },
10039                 { MAC_ADDR_0_LOW, 0x0000,
10040                         0x00000000, 0xffffffff },
10041                 { MAC_RX_MTU_SIZE, 0x0000,
10042                         0x00000000, 0x0000ffff },
10043                 { MAC_TX_MODE, 0x0000,
10044                         0x00000000, 0x00000070 },
10045                 { MAC_TX_LENGTHS, 0x0000,
10046                         0x00000000, 0x00003fff },
10047                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10048                         0x00000000, 0x000007fc },
10049                 { MAC_RX_MODE, TG3_FL_5705,
10050                         0x00000000, 0x000007dc },
10051                 { MAC_HASH_REG_0, 0x0000,
10052                         0x00000000, 0xffffffff },
10053                 { MAC_HASH_REG_1, 0x0000,
10054                         0x00000000, 0xffffffff },
10055                 { MAC_HASH_REG_2, 0x0000,
10056                         0x00000000, 0xffffffff },
10057                 { MAC_HASH_REG_3, 0x0000,
10058                         0x00000000, 0xffffffff },
10059
10060                 /* Receive Data and Receive BD Initiator Control Registers. */
10061                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10062                         0x00000000, 0xffffffff },
10063                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10064                         0x00000000, 0xffffffff },
10065                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10066                         0x00000000, 0x00000003 },
10067                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10068                         0x00000000, 0xffffffff },
10069                 { RCVDBDI_STD_BD+0, 0x0000,
10070                         0x00000000, 0xffffffff },
10071                 { RCVDBDI_STD_BD+4, 0x0000,
10072                         0x00000000, 0xffffffff },
10073                 { RCVDBDI_STD_BD+8, 0x0000,
10074                         0x00000000, 0xffff0002 },
10075                 { RCVDBDI_STD_BD+0xc, 0x0000,
10076                         0x00000000, 0xffffffff },
10077
10078                 /* Receive BD Initiator Control Registers. */
10079                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10080                         0x00000000, 0xffffffff },
10081                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10082                         0x00000000, 0x000003ff },
10083                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10084                         0x00000000, 0xffffffff },
10085
10086                 /* Host Coalescing Control Registers. */
10087                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10088                         0x00000000, 0x00000004 },
10089                 { HOSTCC_MODE, TG3_FL_5705,
10090                         0x00000000, 0x000000f6 },
10091                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10092                         0x00000000, 0xffffffff },
10093                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10094                         0x00000000, 0x000003ff },
10095                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10096                         0x00000000, 0xffffffff },
10097                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10098                         0x00000000, 0x000003ff },
10099                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10100                         0x00000000, 0xffffffff },
10101                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10102                         0x00000000, 0x000000ff },
10103                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10104                         0x00000000, 0xffffffff },
10105                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10106                         0x00000000, 0x000000ff },
10107                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10108                         0x00000000, 0xffffffff },
10109                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10110                         0x00000000, 0xffffffff },
10111                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10112                         0x00000000, 0xffffffff },
10113                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10114                         0x00000000, 0x000000ff },
10115                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10116                         0x00000000, 0xffffffff },
10117                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10118                         0x00000000, 0x000000ff },
10119                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10120                         0x00000000, 0xffffffff },
10121                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10122                         0x00000000, 0xffffffff },
10123                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10124                         0x00000000, 0xffffffff },
10125                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10126                         0x00000000, 0xffffffff },
10127                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10128                         0x00000000, 0xffffffff },
10129                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10130                         0xffffffff, 0x00000000 },
10131                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10132                         0xffffffff, 0x00000000 },
10133
10134                 /* Buffer Manager Control Registers. */
10135                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10136                         0x00000000, 0x007fff80 },
10137                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10138                         0x00000000, 0x007fffff },
10139                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10140                         0x00000000, 0x0000003f },
10141                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10142                         0x00000000, 0x000001ff },
10143                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10144                         0x00000000, 0x000001ff },
10145                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10146                         0xffffffff, 0x00000000 },
10147                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10148                         0xffffffff, 0x00000000 },
10149
10150                 /* Mailbox Registers */
10151                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10152                         0x00000000, 0x000001ff },
10153                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10154                         0x00000000, 0x000001ff },
10155                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10156                         0x00000000, 0x000007ff },
10157                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10158                         0x00000000, 0x000001ff },
10159
10160                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10161         };
10162
10163         is_5705 = is_5750 = 0;
10164         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10165                 is_5705 = 1;
10166                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10167                         is_5750 = 1;
10168         }
10169
10170         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10171                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10172                         continue;
10173
10174                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10175                         continue;
10176
10177                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10178                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10179                         continue;
10180
10181                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10182                         continue;
10183
10184                 offset = (u32) reg_tbl[i].offset;
10185                 read_mask = reg_tbl[i].read_mask;
10186                 write_mask = reg_tbl[i].write_mask;
10187
10188                 /* Save the original register content */
10189                 save_val = tr32(offset);
10190
10191                 /* Determine the read-only value. */
10192                 read_val = save_val & read_mask;
10193
10194                 /* Write zero to the register, then make sure the read-only bits
10195                  * are not changed and the read/write bits are all zeros.
10196                  */
10197                 tw32(offset, 0);
10198
10199                 val = tr32(offset);
10200
10201                 /* Test the read-only and read/write bits. */
10202                 if (((val & read_mask) != read_val) || (val & write_mask))
10203                         goto out;
10204
10205                 /* Write ones to all the bits defined by RdMask and WrMask, then
10206                  * make sure the read-only bits are not changed and the
10207                  * read/write bits are all ones.
10208                  */
10209                 tw32(offset, read_mask | write_mask);
10210
10211                 val = tr32(offset);
10212
10213                 /* Test the read-only bits. */
10214                 if ((val & read_mask) != read_val)
10215                         goto out;
10216
10217                 /* Test the read/write bits. */
10218                 if ((val & write_mask) != write_mask)
10219                         goto out;
10220
10221                 tw32(offset, save_val);
10222         }
10223
10224         return 0;
10225
10226 out:
10227         if (netif_msg_hw(tp))
10228                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10229                        offset);
10230         tw32(offset, save_val);
10231         return -EIO;
10232 }
10233
10234 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10235 {
10236         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10237         int i;
10238         u32 j;
10239
10240         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10241                 for (j = 0; j < len; j += 4) {
10242                         u32 val;
10243
10244                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10245                         tg3_read_mem(tp, offset + j, &val);
10246                         if (val != test_pattern[i])
10247                                 return -EIO;
10248                 }
10249         }
10250         return 0;
10251 }
10252
10253 static int tg3_test_memory(struct tg3 *tp)
10254 {
10255         static struct mem_entry {
10256                 u32 offset;
10257                 u32 len;
10258         } mem_tbl_570x[] = {
10259                 { 0x00000000, 0x00b50},
10260                 { 0x00002000, 0x1c000},
10261                 { 0xffffffff, 0x00000}
10262         }, mem_tbl_5705[] = {
10263                 { 0x00000100, 0x0000c},
10264                 { 0x00000200, 0x00008},
10265                 { 0x00004000, 0x00800},
10266                 { 0x00006000, 0x01000},
10267                 { 0x00008000, 0x02000},
10268                 { 0x00010000, 0x0e000},
10269                 { 0xffffffff, 0x00000}
10270         }, mem_tbl_5755[] = {
10271                 { 0x00000200, 0x00008},
10272                 { 0x00004000, 0x00800},
10273                 { 0x00006000, 0x00800},
10274                 { 0x00008000, 0x02000},
10275                 { 0x00010000, 0x0c000},
10276                 { 0xffffffff, 0x00000}
10277         }, mem_tbl_5906[] = {
10278                 { 0x00000200, 0x00008},
10279                 { 0x00004000, 0x00400},
10280                 { 0x00006000, 0x00400},
10281                 { 0x00008000, 0x01000},
10282                 { 0x00010000, 0x01000},
10283                 { 0xffffffff, 0x00000}
10284         };
10285         struct mem_entry *mem_tbl;
10286         int err = 0;
10287         int i;
10288
10289         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10290                 mem_tbl = mem_tbl_5755;
10291         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10292                 mem_tbl = mem_tbl_5906;
10293         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10294                 mem_tbl = mem_tbl_5705;
10295         else
10296                 mem_tbl = mem_tbl_570x;
10297
10298         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10299                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10300                     mem_tbl[i].len)) != 0)
10301                         break;
10302         }
10303
10304         return err;
10305 }
10306
10307 #define TG3_MAC_LOOPBACK        0
10308 #define TG3_PHY_LOOPBACK        1
10309
10310 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10311 {
10312         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10313         u32 desc_idx, coal_now;
10314         struct sk_buff *skb, *rx_skb;
10315         u8 *tx_data;
10316         dma_addr_t map;
10317         int num_pkts, tx_len, rx_len, i, err;
10318         struct tg3_rx_buffer_desc *desc;
10319         struct tg3_napi *tnapi, *rnapi;
10320         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10321
10322         if (tp->irq_cnt > 1) {
10323                 tnapi = &tp->napi[1];
10324                 rnapi = &tp->napi[1];
10325         } else {
10326                 tnapi = &tp->napi[0];
10327                 rnapi = &tp->napi[0];
10328         }
10329         coal_now = tnapi->coal_now | rnapi->coal_now;
10330
10331         if (loopback_mode == TG3_MAC_LOOPBACK) {
10332                 /* HW errata - mac loopback fails in some cases on 5780.
10333                  * Normal traffic and PHY loopback are not affected by
10334                  * errata.
10335                  */
10336                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10337                         return 0;
10338
10339                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10340                            MAC_MODE_PORT_INT_LPBACK;
10341                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10342                         mac_mode |= MAC_MODE_LINK_POLARITY;
10343                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10344                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10345                 else
10346                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10347                 tw32(MAC_MODE, mac_mode);
10348         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10349                 u32 val;
10350
10351                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10352                         tg3_phy_fet_toggle_apd(tp, false);
10353                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10354                 } else
10355                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10356
10357                 tg3_phy_toggle_automdix(tp, 0);
10358
10359                 tg3_writephy(tp, MII_BMCR, val);
10360                 udelay(40);
10361
10362                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10363                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10364                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10365                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10366                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10367                 } else
10368                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10369
10370                 /* reset to prevent losing 1st rx packet intermittently */
10371                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10372                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10373                         udelay(10);
10374                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10375                 }
10376                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10377                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10378                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10379                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10380                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10381                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10382                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10383                 }
10384                 tw32(MAC_MODE, mac_mode);
10385         }
10386         else
10387                 return -EINVAL;
10388
10389         err = -EIO;
10390
10391         tx_len = 1514;
10392         skb = netdev_alloc_skb(tp->dev, tx_len);
10393         if (!skb)
10394                 return -ENOMEM;
10395
10396         tx_data = skb_put(skb, tx_len);
10397         memcpy(tx_data, tp->dev->dev_addr, 6);
10398         memset(tx_data + 6, 0x0, 8);
10399
10400         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10401
10402         for (i = 14; i < tx_len; i++)
10403                 tx_data[i] = (u8) (i & 0xff);
10404
10405         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10406                 dev_kfree_skb(skb);
10407                 return -EIO;
10408         }
10409
10410         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10411                rnapi->coal_now);
10412
10413         udelay(10);
10414
10415         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10416
10417         num_pkts = 0;
10418
10419         tg3_set_txd(tnapi, tnapi->tx_prod,
10420                     skb_shinfo(skb)->dma_head, tx_len, 0, 1);
10421
10422         tnapi->tx_prod++;
10423         num_pkts++;
10424
10425         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10426         tr32_mailbox(tnapi->prodmbox);
10427
10428         udelay(10);
10429
10430         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10431         for (i = 0; i < 35; i++) {
10432                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10433                        coal_now);
10434
10435                 udelay(10);
10436
10437                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10438                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10439                 if ((tx_idx == tnapi->tx_prod) &&
10440                     (rx_idx == (rx_start_idx + num_pkts)))
10441                         break;
10442         }
10443
10444         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
10445         dev_kfree_skb(skb);
10446
10447         if (tx_idx != tnapi->tx_prod)
10448                 goto out;
10449
10450         if (rx_idx != rx_start_idx + num_pkts)
10451                 goto out;
10452
10453         desc = &rnapi->rx_rcb[rx_start_idx];
10454         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10455         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10456         if (opaque_key != RXD_OPAQUE_RING_STD)
10457                 goto out;
10458
10459         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10460             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10461                 goto out;
10462
10463         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10464         if (rx_len != tx_len)
10465                 goto out;
10466
10467         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10468
10469         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10470         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10471
10472         for (i = 14; i < tx_len; i++) {
10473                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10474                         goto out;
10475         }
10476         err = 0;
10477
10478         /* tg3_free_rings will unmap and free the rx_skb */
10479 out:
10480         return err;
10481 }
10482
10483 #define TG3_MAC_LOOPBACK_FAILED         1
10484 #define TG3_PHY_LOOPBACK_FAILED         2
10485 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10486                                          TG3_PHY_LOOPBACK_FAILED)
10487
10488 static int tg3_test_loopback(struct tg3 *tp)
10489 {
10490         int err = 0;
10491         u32 cpmuctrl = 0;
10492
10493         if (!netif_running(tp->dev))
10494                 return TG3_LOOPBACK_FAILED;
10495
10496         err = tg3_reset_hw(tp, 1);
10497         if (err)
10498                 return TG3_LOOPBACK_FAILED;
10499
10500         /* Turn off gphy autopowerdown. */
10501         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10502                 tg3_phy_toggle_apd(tp, false);
10503
10504         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10505                 int i;
10506                 u32 status;
10507
10508                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10509
10510                 /* Wait for up to 40 microseconds to acquire lock. */
10511                 for (i = 0; i < 4; i++) {
10512                         status = tr32(TG3_CPMU_MUTEX_GNT);
10513                         if (status == CPMU_MUTEX_GNT_DRIVER)
10514                                 break;
10515                         udelay(10);
10516                 }
10517
10518                 if (status != CPMU_MUTEX_GNT_DRIVER)
10519                         return TG3_LOOPBACK_FAILED;
10520
10521                 /* Turn off link-based power management. */
10522                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10523                 tw32(TG3_CPMU_CTRL,
10524                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10525                                   CPMU_CTRL_LINK_AWARE_MODE));
10526         }
10527
10528         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10529                 err |= TG3_MAC_LOOPBACK_FAILED;
10530
10531         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10532                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10533
10534                 /* Release the mutex */
10535                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10536         }
10537
10538         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10539             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10540                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10541                         err |= TG3_PHY_LOOPBACK_FAILED;
10542         }
10543
10544         /* Re-enable gphy autopowerdown. */
10545         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10546                 tg3_phy_toggle_apd(tp, true);
10547
10548         return err;
10549 }
10550
10551 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10552                           u64 *data)
10553 {
10554         struct tg3 *tp = netdev_priv(dev);
10555
10556         if (tp->link_config.phy_is_low_power)
10557                 tg3_set_power_state(tp, PCI_D0);
10558
10559         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10560
10561         if (tg3_test_nvram(tp) != 0) {
10562                 etest->flags |= ETH_TEST_FL_FAILED;
10563                 data[0] = 1;
10564         }
10565         if (tg3_test_link(tp) != 0) {
10566                 etest->flags |= ETH_TEST_FL_FAILED;
10567                 data[1] = 1;
10568         }
10569         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10570                 int err, err2 = 0, irq_sync = 0;
10571
10572                 if (netif_running(dev)) {
10573                         tg3_phy_stop(tp);
10574                         tg3_netif_stop(tp);
10575                         irq_sync = 1;
10576                 }
10577
10578                 tg3_full_lock(tp, irq_sync);
10579
10580                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10581                 err = tg3_nvram_lock(tp);
10582                 tg3_halt_cpu(tp, RX_CPU_BASE);
10583                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10584                         tg3_halt_cpu(tp, TX_CPU_BASE);
10585                 if (!err)
10586                         tg3_nvram_unlock(tp);
10587
10588                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10589                         tg3_phy_reset(tp);
10590
10591                 if (tg3_test_registers(tp) != 0) {
10592                         etest->flags |= ETH_TEST_FL_FAILED;
10593                         data[2] = 1;
10594                 }
10595                 if (tg3_test_memory(tp) != 0) {
10596                         etest->flags |= ETH_TEST_FL_FAILED;
10597                         data[3] = 1;
10598                 }
10599                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10600                         etest->flags |= ETH_TEST_FL_FAILED;
10601
10602                 tg3_full_unlock(tp);
10603
10604                 if (tg3_test_interrupt(tp) != 0) {
10605                         etest->flags |= ETH_TEST_FL_FAILED;
10606                         data[5] = 1;
10607                 }
10608
10609                 tg3_full_lock(tp, 0);
10610
10611                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10612                 if (netif_running(dev)) {
10613                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10614                         err2 = tg3_restart_hw(tp, 1);
10615                         if (!err2)
10616                                 tg3_netif_start(tp);
10617                 }
10618
10619                 tg3_full_unlock(tp);
10620
10621                 if (irq_sync && !err2)
10622                         tg3_phy_start(tp);
10623         }
10624         if (tp->link_config.phy_is_low_power)
10625                 tg3_set_power_state(tp, PCI_D3hot);
10626
10627 }
10628
10629 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10630 {
10631         struct mii_ioctl_data *data = if_mii(ifr);
10632         struct tg3 *tp = netdev_priv(dev);
10633         int err;
10634
10635         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10636                 struct phy_device *phydev;
10637                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10638                         return -EAGAIN;
10639                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10640                 return phy_mii_ioctl(phydev, data, cmd);
10641         }
10642
10643         switch(cmd) {
10644         case SIOCGMIIPHY:
10645                 data->phy_id = tp->phy_addr;
10646
10647                 /* fallthru */
10648         case SIOCGMIIREG: {
10649                 u32 mii_regval;
10650
10651                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10652                         break;                  /* We have no PHY */
10653
10654                 if (tp->link_config.phy_is_low_power)
10655                         return -EAGAIN;
10656
10657                 spin_lock_bh(&tp->lock);
10658                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10659                 spin_unlock_bh(&tp->lock);
10660
10661                 data->val_out = mii_regval;
10662
10663                 return err;
10664         }
10665
10666         case SIOCSMIIREG:
10667                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10668                         break;                  /* We have no PHY */
10669
10670                 if (tp->link_config.phy_is_low_power)
10671                         return -EAGAIN;
10672
10673                 spin_lock_bh(&tp->lock);
10674                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10675                 spin_unlock_bh(&tp->lock);
10676
10677                 return err;
10678
10679         default:
10680                 /* do nothing */
10681                 break;
10682         }
10683         return -EOPNOTSUPP;
10684 }
10685
10686 #if TG3_VLAN_TAG_USED
10687 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10688 {
10689         struct tg3 *tp = netdev_priv(dev);
10690
10691         if (!netif_running(dev)) {
10692                 tp->vlgrp = grp;
10693                 return;
10694         }
10695
10696         tg3_netif_stop(tp);
10697
10698         tg3_full_lock(tp, 0);
10699
10700         tp->vlgrp = grp;
10701
10702         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10703         __tg3_set_rx_mode(dev);
10704
10705         tg3_netif_start(tp);
10706
10707         tg3_full_unlock(tp);
10708 }
10709 #endif
10710
10711 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10712 {
10713         struct tg3 *tp = netdev_priv(dev);
10714
10715         memcpy(ec, &tp->coal, sizeof(*ec));
10716         return 0;
10717 }
10718
10719 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10720 {
10721         struct tg3 *tp = netdev_priv(dev);
10722         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10723         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10724
10725         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10726                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10727                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10728                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10729                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10730         }
10731
10732         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10733             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10734             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10735             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10736             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10737             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10738             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10739             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10740             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10741             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10742                 return -EINVAL;
10743
10744         /* No rx interrupts will be generated if both are zero */
10745         if ((ec->rx_coalesce_usecs == 0) &&
10746             (ec->rx_max_coalesced_frames == 0))
10747                 return -EINVAL;
10748
10749         /* No tx interrupts will be generated if both are zero */
10750         if ((ec->tx_coalesce_usecs == 0) &&
10751             (ec->tx_max_coalesced_frames == 0))
10752                 return -EINVAL;
10753
10754         /* Only copy relevant parameters, ignore all others. */
10755         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10756         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10757         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10758         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10759         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10760         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10761         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10762         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10763         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10764
10765         if (netif_running(dev)) {
10766                 tg3_full_lock(tp, 0);
10767                 __tg3_set_coalesce(tp, &tp->coal);
10768                 tg3_full_unlock(tp);
10769         }
10770         return 0;
10771 }
10772
10773 static const struct ethtool_ops tg3_ethtool_ops = {
10774         .get_settings           = tg3_get_settings,
10775         .set_settings           = tg3_set_settings,
10776         .get_drvinfo            = tg3_get_drvinfo,
10777         .get_regs_len           = tg3_get_regs_len,
10778         .get_regs               = tg3_get_regs,
10779         .get_wol                = tg3_get_wol,
10780         .set_wol                = tg3_set_wol,
10781         .get_msglevel           = tg3_get_msglevel,
10782         .set_msglevel           = tg3_set_msglevel,
10783         .nway_reset             = tg3_nway_reset,
10784         .get_link               = ethtool_op_get_link,
10785         .get_eeprom_len         = tg3_get_eeprom_len,
10786         .get_eeprom             = tg3_get_eeprom,
10787         .set_eeprom             = tg3_set_eeprom,
10788         .get_ringparam          = tg3_get_ringparam,
10789         .set_ringparam          = tg3_set_ringparam,
10790         .get_pauseparam         = tg3_get_pauseparam,
10791         .set_pauseparam         = tg3_set_pauseparam,
10792         .get_rx_csum            = tg3_get_rx_csum,
10793         .set_rx_csum            = tg3_set_rx_csum,
10794         .set_tx_csum            = tg3_set_tx_csum,
10795         .set_sg                 = ethtool_op_set_sg,
10796         .set_tso                = tg3_set_tso,
10797         .self_test              = tg3_self_test,
10798         .get_strings            = tg3_get_strings,
10799         .phys_id                = tg3_phys_id,
10800         .get_ethtool_stats      = tg3_get_ethtool_stats,
10801         .get_coalesce           = tg3_get_coalesce,
10802         .set_coalesce           = tg3_set_coalesce,
10803         .get_sset_count         = tg3_get_sset_count,
10804 };
10805
10806 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10807 {
10808         u32 cursize, val, magic;
10809
10810         tp->nvram_size = EEPROM_CHIP_SIZE;
10811
10812         if (tg3_nvram_read(tp, 0, &magic) != 0)
10813                 return;
10814
10815         if ((magic != TG3_EEPROM_MAGIC) &&
10816             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10817             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10818                 return;
10819
10820         /*
10821          * Size the chip by reading offsets at increasing powers of two.
10822          * When we encounter our validation signature, we know the addressing
10823          * has wrapped around, and thus have our chip size.
10824          */
10825         cursize = 0x10;
10826
10827         while (cursize < tp->nvram_size) {
10828                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10829                         return;
10830
10831                 if (val == magic)
10832                         break;
10833
10834                 cursize <<= 1;
10835         }
10836
10837         tp->nvram_size = cursize;
10838 }
10839
10840 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10841 {
10842         u32 val;
10843
10844         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10845             tg3_nvram_read(tp, 0, &val) != 0)
10846                 return;
10847
10848         /* Selfboot format */
10849         if (val != TG3_EEPROM_MAGIC) {
10850                 tg3_get_eeprom_size(tp);
10851                 return;
10852         }
10853
10854         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10855                 if (val != 0) {
10856                         /* This is confusing.  We want to operate on the
10857                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10858                          * call will read from NVRAM and byteswap the data
10859                          * according to the byteswapping settings for all
10860                          * other register accesses.  This ensures the data we
10861                          * want will always reside in the lower 16-bits.
10862                          * However, the data in NVRAM is in LE format, which
10863                          * means the data from the NVRAM read will always be
10864                          * opposite the endianness of the CPU.  The 16-bit
10865                          * byteswap then brings the data to CPU endianness.
10866                          */
10867                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10868                         return;
10869                 }
10870         }
10871         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10872 }
10873
10874 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10875 {
10876         u32 nvcfg1;
10877
10878         nvcfg1 = tr32(NVRAM_CFG1);
10879         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10880                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10881         } else {
10882                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10883                 tw32(NVRAM_CFG1, nvcfg1);
10884         }
10885
10886         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10887             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10888                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10889                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10890                         tp->nvram_jedecnum = JEDEC_ATMEL;
10891                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10892                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10893                         break;
10894                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10895                         tp->nvram_jedecnum = JEDEC_ATMEL;
10896                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10897                         break;
10898                 case FLASH_VENDOR_ATMEL_EEPROM:
10899                         tp->nvram_jedecnum = JEDEC_ATMEL;
10900                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10901                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10902                         break;
10903                 case FLASH_VENDOR_ST:
10904                         tp->nvram_jedecnum = JEDEC_ST;
10905                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10906                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10907                         break;
10908                 case FLASH_VENDOR_SAIFUN:
10909                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10910                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10911                         break;
10912                 case FLASH_VENDOR_SST_SMALL:
10913                 case FLASH_VENDOR_SST_LARGE:
10914                         tp->nvram_jedecnum = JEDEC_SST;
10915                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10916                         break;
10917                 }
10918         } else {
10919                 tp->nvram_jedecnum = JEDEC_ATMEL;
10920                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10921                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10922         }
10923 }
10924
10925 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10926 {
10927         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10928         case FLASH_5752PAGE_SIZE_256:
10929                 tp->nvram_pagesize = 256;
10930                 break;
10931         case FLASH_5752PAGE_SIZE_512:
10932                 tp->nvram_pagesize = 512;
10933                 break;
10934         case FLASH_5752PAGE_SIZE_1K:
10935                 tp->nvram_pagesize = 1024;
10936                 break;
10937         case FLASH_5752PAGE_SIZE_2K:
10938                 tp->nvram_pagesize = 2048;
10939                 break;
10940         case FLASH_5752PAGE_SIZE_4K:
10941                 tp->nvram_pagesize = 4096;
10942                 break;
10943         case FLASH_5752PAGE_SIZE_264:
10944                 tp->nvram_pagesize = 264;
10945                 break;
10946         case FLASH_5752PAGE_SIZE_528:
10947                 tp->nvram_pagesize = 528;
10948                 break;
10949         }
10950 }
10951
10952 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10953 {
10954         u32 nvcfg1;
10955
10956         nvcfg1 = tr32(NVRAM_CFG1);
10957
10958         /* NVRAM protection for TPM */
10959         if (nvcfg1 & (1 << 27))
10960                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10961
10962         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10963         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10964         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10965                 tp->nvram_jedecnum = JEDEC_ATMEL;
10966                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10967                 break;
10968         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10969                 tp->nvram_jedecnum = JEDEC_ATMEL;
10970                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10971                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10972                 break;
10973         case FLASH_5752VENDOR_ST_M45PE10:
10974         case FLASH_5752VENDOR_ST_M45PE20:
10975         case FLASH_5752VENDOR_ST_M45PE40:
10976                 tp->nvram_jedecnum = JEDEC_ST;
10977                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10978                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10979                 break;
10980         }
10981
10982         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10983                 tg3_nvram_get_pagesize(tp, nvcfg1);
10984         } else {
10985                 /* For eeprom, set pagesize to maximum eeprom size */
10986                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10987
10988                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10989                 tw32(NVRAM_CFG1, nvcfg1);
10990         }
10991 }
10992
10993 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10994 {
10995         u32 nvcfg1, protect = 0;
10996
10997         nvcfg1 = tr32(NVRAM_CFG1);
10998
10999         /* NVRAM protection for TPM */
11000         if (nvcfg1 & (1 << 27)) {
11001                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11002                 protect = 1;
11003         }
11004
11005         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11006         switch (nvcfg1) {
11007         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11008         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11009         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11010         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11011                 tp->nvram_jedecnum = JEDEC_ATMEL;
11012                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11013                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11014                 tp->nvram_pagesize = 264;
11015                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11016                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11017                         tp->nvram_size = (protect ? 0x3e200 :
11018                                           TG3_NVRAM_SIZE_512KB);
11019                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11020                         tp->nvram_size = (protect ? 0x1f200 :
11021                                           TG3_NVRAM_SIZE_256KB);
11022                 else
11023                         tp->nvram_size = (protect ? 0x1f200 :
11024                                           TG3_NVRAM_SIZE_128KB);
11025                 break;
11026         case FLASH_5752VENDOR_ST_M45PE10:
11027         case FLASH_5752VENDOR_ST_M45PE20:
11028         case FLASH_5752VENDOR_ST_M45PE40:
11029                 tp->nvram_jedecnum = JEDEC_ST;
11030                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11031                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11032                 tp->nvram_pagesize = 256;
11033                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11034                         tp->nvram_size = (protect ?
11035                                           TG3_NVRAM_SIZE_64KB :
11036                                           TG3_NVRAM_SIZE_128KB);
11037                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11038                         tp->nvram_size = (protect ?
11039                                           TG3_NVRAM_SIZE_64KB :
11040                                           TG3_NVRAM_SIZE_256KB);
11041                 else
11042                         tp->nvram_size = (protect ?
11043                                           TG3_NVRAM_SIZE_128KB :
11044                                           TG3_NVRAM_SIZE_512KB);
11045                 break;
11046         }
11047 }
11048
11049 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11050 {
11051         u32 nvcfg1;
11052
11053         nvcfg1 = tr32(NVRAM_CFG1);
11054
11055         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11056         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11057         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11058         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11059         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11060                 tp->nvram_jedecnum = JEDEC_ATMEL;
11061                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11062                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11063
11064                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11065                 tw32(NVRAM_CFG1, nvcfg1);
11066                 break;
11067         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11068         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11069         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11070         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11071                 tp->nvram_jedecnum = JEDEC_ATMEL;
11072                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11073                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11074                 tp->nvram_pagesize = 264;
11075                 break;
11076         case FLASH_5752VENDOR_ST_M45PE10:
11077         case FLASH_5752VENDOR_ST_M45PE20:
11078         case FLASH_5752VENDOR_ST_M45PE40:
11079                 tp->nvram_jedecnum = JEDEC_ST;
11080                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11081                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11082                 tp->nvram_pagesize = 256;
11083                 break;
11084         }
11085 }
11086
11087 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11088 {
11089         u32 nvcfg1, protect = 0;
11090
11091         nvcfg1 = tr32(NVRAM_CFG1);
11092
11093         /* NVRAM protection for TPM */
11094         if (nvcfg1 & (1 << 27)) {
11095                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11096                 protect = 1;
11097         }
11098
11099         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11100         switch (nvcfg1) {
11101         case FLASH_5761VENDOR_ATMEL_ADB021D:
11102         case FLASH_5761VENDOR_ATMEL_ADB041D:
11103         case FLASH_5761VENDOR_ATMEL_ADB081D:
11104         case FLASH_5761VENDOR_ATMEL_ADB161D:
11105         case FLASH_5761VENDOR_ATMEL_MDB021D:
11106         case FLASH_5761VENDOR_ATMEL_MDB041D:
11107         case FLASH_5761VENDOR_ATMEL_MDB081D:
11108         case FLASH_5761VENDOR_ATMEL_MDB161D:
11109                 tp->nvram_jedecnum = JEDEC_ATMEL;
11110                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11111                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11112                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11113                 tp->nvram_pagesize = 256;
11114                 break;
11115         case FLASH_5761VENDOR_ST_A_M45PE20:
11116         case FLASH_5761VENDOR_ST_A_M45PE40:
11117         case FLASH_5761VENDOR_ST_A_M45PE80:
11118         case FLASH_5761VENDOR_ST_A_M45PE16:
11119         case FLASH_5761VENDOR_ST_M_M45PE20:
11120         case FLASH_5761VENDOR_ST_M_M45PE40:
11121         case FLASH_5761VENDOR_ST_M_M45PE80:
11122         case FLASH_5761VENDOR_ST_M_M45PE16:
11123                 tp->nvram_jedecnum = JEDEC_ST;
11124                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11125                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11126                 tp->nvram_pagesize = 256;
11127                 break;
11128         }
11129
11130         if (protect) {
11131                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11132         } else {
11133                 switch (nvcfg1) {
11134                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11135                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11136                 case FLASH_5761VENDOR_ST_A_M45PE16:
11137                 case FLASH_5761VENDOR_ST_M_M45PE16:
11138                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11139                         break;
11140                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11141                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11142                 case FLASH_5761VENDOR_ST_A_M45PE80:
11143                 case FLASH_5761VENDOR_ST_M_M45PE80:
11144                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11145                         break;
11146                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11147                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11148                 case FLASH_5761VENDOR_ST_A_M45PE40:
11149                 case FLASH_5761VENDOR_ST_M_M45PE40:
11150                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11151                         break;
11152                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11153                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11154                 case FLASH_5761VENDOR_ST_A_M45PE20:
11155                 case FLASH_5761VENDOR_ST_M_M45PE20:
11156                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11157                         break;
11158                 }
11159         }
11160 }
11161
11162 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11163 {
11164         tp->nvram_jedecnum = JEDEC_ATMEL;
11165         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11166         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11167 }
11168
11169 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11170 {
11171         u32 nvcfg1;
11172
11173         nvcfg1 = tr32(NVRAM_CFG1);
11174
11175         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11176         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11177         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11178                 tp->nvram_jedecnum = JEDEC_ATMEL;
11179                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11180                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11181
11182                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11183                 tw32(NVRAM_CFG1, nvcfg1);
11184                 return;
11185         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11186         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11187         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11188         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11189         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11190         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11191         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11192                 tp->nvram_jedecnum = JEDEC_ATMEL;
11193                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11194                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11195
11196                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11197                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11198                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11199                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11200                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11201                         break;
11202                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11203                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11204                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11205                         break;
11206                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11207                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11208                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11209                         break;
11210                 }
11211                 break;
11212         case FLASH_5752VENDOR_ST_M45PE10:
11213         case FLASH_5752VENDOR_ST_M45PE20:
11214         case FLASH_5752VENDOR_ST_M45PE40:
11215                 tp->nvram_jedecnum = JEDEC_ST;
11216                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11217                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11218
11219                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11220                 case FLASH_5752VENDOR_ST_M45PE10:
11221                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11222                         break;
11223                 case FLASH_5752VENDOR_ST_M45PE20:
11224                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11225                         break;
11226                 case FLASH_5752VENDOR_ST_M45PE40:
11227                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11228                         break;
11229                 }
11230                 break;
11231         default:
11232                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11233                 return;
11234         }
11235
11236         tg3_nvram_get_pagesize(tp, nvcfg1);
11237         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11238                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11239 }
11240
11241
11242 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11243 {
11244         u32 nvcfg1;
11245
11246         nvcfg1 = tr32(NVRAM_CFG1);
11247
11248         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11249         case FLASH_5717VENDOR_ATMEL_EEPROM:
11250         case FLASH_5717VENDOR_MICRO_EEPROM:
11251                 tp->nvram_jedecnum = JEDEC_ATMEL;
11252                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11253                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11254
11255                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11256                 tw32(NVRAM_CFG1, nvcfg1);
11257                 return;
11258         case FLASH_5717VENDOR_ATMEL_MDB011D:
11259         case FLASH_5717VENDOR_ATMEL_ADB011B:
11260         case FLASH_5717VENDOR_ATMEL_ADB011D:
11261         case FLASH_5717VENDOR_ATMEL_MDB021D:
11262         case FLASH_5717VENDOR_ATMEL_ADB021B:
11263         case FLASH_5717VENDOR_ATMEL_ADB021D:
11264         case FLASH_5717VENDOR_ATMEL_45USPT:
11265                 tp->nvram_jedecnum = JEDEC_ATMEL;
11266                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11267                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11268
11269                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11270                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11271                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11272                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11273                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11274                         break;
11275                 default:
11276                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11277                         break;
11278                 }
11279                 break;
11280         case FLASH_5717VENDOR_ST_M_M25PE10:
11281         case FLASH_5717VENDOR_ST_A_M25PE10:
11282         case FLASH_5717VENDOR_ST_M_M45PE10:
11283         case FLASH_5717VENDOR_ST_A_M45PE10:
11284         case FLASH_5717VENDOR_ST_M_M25PE20:
11285         case FLASH_5717VENDOR_ST_A_M25PE20:
11286         case FLASH_5717VENDOR_ST_M_M45PE20:
11287         case FLASH_5717VENDOR_ST_A_M45PE20:
11288         case FLASH_5717VENDOR_ST_25USPT:
11289         case FLASH_5717VENDOR_ST_45USPT:
11290                 tp->nvram_jedecnum = JEDEC_ST;
11291                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11292                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11293
11294                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11295                 case FLASH_5717VENDOR_ST_M_M25PE20:
11296                 case FLASH_5717VENDOR_ST_A_M25PE20:
11297                 case FLASH_5717VENDOR_ST_M_M45PE20:
11298                 case FLASH_5717VENDOR_ST_A_M45PE20:
11299                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11300                         break;
11301                 default:
11302                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11303                         break;
11304                 }
11305                 break;
11306         default:
11307                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11308                 return;
11309         }
11310
11311         tg3_nvram_get_pagesize(tp, nvcfg1);
11312         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11313                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11314 }
11315
11316 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11317 static void __devinit tg3_nvram_init(struct tg3 *tp)
11318 {
11319         tw32_f(GRC_EEPROM_ADDR,
11320              (EEPROM_ADDR_FSM_RESET |
11321               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11322                EEPROM_ADDR_CLKPERD_SHIFT)));
11323
11324         msleep(1);
11325
11326         /* Enable seeprom accesses. */
11327         tw32_f(GRC_LOCAL_CTRL,
11328              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11329         udelay(100);
11330
11331         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11332             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11333                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11334
11335                 if (tg3_nvram_lock(tp)) {
11336                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11337                                "tg3_nvram_init failed.\n", tp->dev->name);
11338                         return;
11339                 }
11340                 tg3_enable_nvram_access(tp);
11341
11342                 tp->nvram_size = 0;
11343
11344                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11345                         tg3_get_5752_nvram_info(tp);
11346                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11347                         tg3_get_5755_nvram_info(tp);
11348                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11349                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11350                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11351                         tg3_get_5787_nvram_info(tp);
11352                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11353                         tg3_get_5761_nvram_info(tp);
11354                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11355                         tg3_get_5906_nvram_info(tp);
11356                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11357                         tg3_get_57780_nvram_info(tp);
11358                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11359                         tg3_get_5717_nvram_info(tp);
11360                 else
11361                         tg3_get_nvram_info(tp);
11362
11363                 if (tp->nvram_size == 0)
11364                         tg3_get_nvram_size(tp);
11365
11366                 tg3_disable_nvram_access(tp);
11367                 tg3_nvram_unlock(tp);
11368
11369         } else {
11370                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11371
11372                 tg3_get_eeprom_size(tp);
11373         }
11374 }
11375
11376 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11377                                     u32 offset, u32 len, u8 *buf)
11378 {
11379         int i, j, rc = 0;
11380         u32 val;
11381
11382         for (i = 0; i < len; i += 4) {
11383                 u32 addr;
11384                 __be32 data;
11385
11386                 addr = offset + i;
11387
11388                 memcpy(&data, buf + i, 4);
11389
11390                 /*
11391                  * The SEEPROM interface expects the data to always be opposite
11392                  * the native endian format.  We accomplish this by reversing
11393                  * all the operations that would have been performed on the
11394                  * data from a call to tg3_nvram_read_be32().
11395                  */
11396                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11397
11398                 val = tr32(GRC_EEPROM_ADDR);
11399                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11400
11401                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11402                         EEPROM_ADDR_READ);
11403                 tw32(GRC_EEPROM_ADDR, val |
11404                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11405                         (addr & EEPROM_ADDR_ADDR_MASK) |
11406                         EEPROM_ADDR_START |
11407                         EEPROM_ADDR_WRITE);
11408
11409                 for (j = 0; j < 1000; j++) {
11410                         val = tr32(GRC_EEPROM_ADDR);
11411
11412                         if (val & EEPROM_ADDR_COMPLETE)
11413                                 break;
11414                         msleep(1);
11415                 }
11416                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11417                         rc = -EBUSY;
11418                         break;
11419                 }
11420         }
11421
11422         return rc;
11423 }
11424
11425 /* offset and length are dword aligned */
11426 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11427                 u8 *buf)
11428 {
11429         int ret = 0;
11430         u32 pagesize = tp->nvram_pagesize;
11431         u32 pagemask = pagesize - 1;
11432         u32 nvram_cmd;
11433         u8 *tmp;
11434
11435         tmp = kmalloc(pagesize, GFP_KERNEL);
11436         if (tmp == NULL)
11437                 return -ENOMEM;
11438
11439         while (len) {
11440                 int j;
11441                 u32 phy_addr, page_off, size;
11442
11443                 phy_addr = offset & ~pagemask;
11444
11445                 for (j = 0; j < pagesize; j += 4) {
11446                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11447                                                   (__be32 *) (tmp + j));
11448                         if (ret)
11449                                 break;
11450                 }
11451                 if (ret)
11452                         break;
11453
11454                 page_off = offset & pagemask;
11455                 size = pagesize;
11456                 if (len < size)
11457                         size = len;
11458
11459                 len -= size;
11460
11461                 memcpy(tmp + page_off, buf, size);
11462
11463                 offset = offset + (pagesize - page_off);
11464
11465                 tg3_enable_nvram_access(tp);
11466
11467                 /*
11468                  * Before we can erase the flash page, we need
11469                  * to issue a special "write enable" command.
11470                  */
11471                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11472
11473                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11474                         break;
11475
11476                 /* Erase the target page */
11477                 tw32(NVRAM_ADDR, phy_addr);
11478
11479                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11480                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11481
11482                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11483                         break;
11484
11485                 /* Issue another write enable to start the write. */
11486                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11487
11488                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11489                         break;
11490
11491                 for (j = 0; j < pagesize; j += 4) {
11492                         __be32 data;
11493
11494                         data = *((__be32 *) (tmp + j));
11495
11496                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11497
11498                         tw32(NVRAM_ADDR, phy_addr + j);
11499
11500                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11501                                 NVRAM_CMD_WR;
11502
11503                         if (j == 0)
11504                                 nvram_cmd |= NVRAM_CMD_FIRST;
11505                         else if (j == (pagesize - 4))
11506                                 nvram_cmd |= NVRAM_CMD_LAST;
11507
11508                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11509                                 break;
11510                 }
11511                 if (ret)
11512                         break;
11513         }
11514
11515         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11516         tg3_nvram_exec_cmd(tp, nvram_cmd);
11517
11518         kfree(tmp);
11519
11520         return ret;
11521 }
11522
11523 /* offset and length are dword aligned */
11524 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11525                 u8 *buf)
11526 {
11527         int i, ret = 0;
11528
11529         for (i = 0; i < len; i += 4, offset += 4) {
11530                 u32 page_off, phy_addr, nvram_cmd;
11531                 __be32 data;
11532
11533                 memcpy(&data, buf + i, 4);
11534                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11535
11536                 page_off = offset % tp->nvram_pagesize;
11537
11538                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11539
11540                 tw32(NVRAM_ADDR, phy_addr);
11541
11542                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11543
11544                 if ((page_off == 0) || (i == 0))
11545                         nvram_cmd |= NVRAM_CMD_FIRST;
11546                 if (page_off == (tp->nvram_pagesize - 4))
11547                         nvram_cmd |= NVRAM_CMD_LAST;
11548
11549                 if (i == (len - 4))
11550                         nvram_cmd |= NVRAM_CMD_LAST;
11551
11552                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11553                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11554                     (tp->nvram_jedecnum == JEDEC_ST) &&
11555                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11556
11557                         if ((ret = tg3_nvram_exec_cmd(tp,
11558                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11559                                 NVRAM_CMD_DONE)))
11560
11561                                 break;
11562                 }
11563                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11564                         /* We always do complete word writes to eeprom. */
11565                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11566                 }
11567
11568                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11569                         break;
11570         }
11571         return ret;
11572 }
11573
11574 /* offset and length are dword aligned */
11575 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11576 {
11577         int ret;
11578
11579         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11580                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11581                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11582                 udelay(40);
11583         }
11584
11585         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11586                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11587         }
11588         else {
11589                 u32 grc_mode;
11590
11591                 ret = tg3_nvram_lock(tp);
11592                 if (ret)
11593                         return ret;
11594
11595                 tg3_enable_nvram_access(tp);
11596                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11597                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11598                         tw32(NVRAM_WRITE1, 0x406);
11599
11600                 grc_mode = tr32(GRC_MODE);
11601                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11602
11603                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11604                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11605
11606                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11607                                 buf);
11608                 }
11609                 else {
11610                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11611                                 buf);
11612                 }
11613
11614                 grc_mode = tr32(GRC_MODE);
11615                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11616
11617                 tg3_disable_nvram_access(tp);
11618                 tg3_nvram_unlock(tp);
11619         }
11620
11621         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11622                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11623                 udelay(40);
11624         }
11625
11626         return ret;
11627 }
11628
11629 struct subsys_tbl_ent {
11630         u16 subsys_vendor, subsys_devid;
11631         u32 phy_id;
11632 };
11633
11634 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11635         /* Broadcom boards. */
11636         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11637         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11638         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11639         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11640         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11641         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11642         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11643         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11644         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11645         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11646         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11647
11648         /* 3com boards. */
11649         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11650         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11651         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11652         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11653         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11654
11655         /* DELL boards. */
11656         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11657         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11658         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11659         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11660
11661         /* Compaq boards. */
11662         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11663         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11664         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11665         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11666         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11667
11668         /* IBM boards. */
11669         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11670 };
11671
11672 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11673 {
11674         int i;
11675
11676         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11677                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11678                      tp->pdev->subsystem_vendor) &&
11679                     (subsys_id_to_phy_id[i].subsys_devid ==
11680                      tp->pdev->subsystem_device))
11681                         return &subsys_id_to_phy_id[i];
11682         }
11683         return NULL;
11684 }
11685
11686 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11687 {
11688         u32 val;
11689         u16 pmcsr;
11690
11691         /* On some early chips the SRAM cannot be accessed in D3hot state,
11692          * so need make sure we're in D0.
11693          */
11694         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11695         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11696         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11697         msleep(1);
11698
11699         /* Make sure register accesses (indirect or otherwise)
11700          * will function correctly.
11701          */
11702         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11703                                tp->misc_host_ctrl);
11704
11705         /* The memory arbiter has to be enabled in order for SRAM accesses
11706          * to succeed.  Normally on powerup the tg3 chip firmware will make
11707          * sure it is enabled, but other entities such as system netboot
11708          * code might disable it.
11709          */
11710         val = tr32(MEMARB_MODE);
11711         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11712
11713         tp->phy_id = PHY_ID_INVALID;
11714         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11715
11716         /* Assume an onboard device and WOL capable by default.  */
11717         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11718
11719         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11720                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11721                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11722                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11723                 }
11724                 val = tr32(VCPU_CFGSHDW);
11725                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11726                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11727                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11728                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11729                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11730                 goto done;
11731         }
11732
11733         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11734         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11735                 u32 nic_cfg, led_cfg;
11736                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11737                 int eeprom_phy_serdes = 0;
11738
11739                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11740                 tp->nic_sram_data_cfg = nic_cfg;
11741
11742                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11743                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11744                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11745                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11746                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11747                     (ver > 0) && (ver < 0x100))
11748                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11749
11750                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11751                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11752
11753                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11754                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11755                         eeprom_phy_serdes = 1;
11756
11757                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11758                 if (nic_phy_id != 0) {
11759                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11760                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11761
11762                         eeprom_phy_id  = (id1 >> 16) << 10;
11763                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11764                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11765                 } else
11766                         eeprom_phy_id = 0;
11767
11768                 tp->phy_id = eeprom_phy_id;
11769                 if (eeprom_phy_serdes) {
11770                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11771                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11772                         else
11773                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11774                 }
11775
11776                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11777                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11778                                     SHASTA_EXT_LED_MODE_MASK);
11779                 else
11780                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11781
11782                 switch (led_cfg) {
11783                 default:
11784                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11785                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11786                         break;
11787
11788                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11789                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11790                         break;
11791
11792                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11793                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11794
11795                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11796                          * read on some older 5700/5701 bootcode.
11797                          */
11798                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11799                             ASIC_REV_5700 ||
11800                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11801                             ASIC_REV_5701)
11802                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11803
11804                         break;
11805
11806                 case SHASTA_EXT_LED_SHARED:
11807                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11808                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11809                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11810                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11811                                                  LED_CTRL_MODE_PHY_2);
11812                         break;
11813
11814                 case SHASTA_EXT_LED_MAC:
11815                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11816                         break;
11817
11818                 case SHASTA_EXT_LED_COMBO:
11819                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11820                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11821                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11822                                                  LED_CTRL_MODE_PHY_2);
11823                         break;
11824
11825                 }
11826
11827                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11828                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11829                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11830                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11831
11832                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11833                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11834
11835                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11836                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11837                         if ((tp->pdev->subsystem_vendor ==
11838                              PCI_VENDOR_ID_ARIMA) &&
11839                             (tp->pdev->subsystem_device == 0x205a ||
11840                              tp->pdev->subsystem_device == 0x2063))
11841                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11842                 } else {
11843                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11844                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11845                 }
11846
11847                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11848                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11849                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11850                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11851                 }
11852
11853                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11854                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11855                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11856
11857                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11858                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11859                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11860
11861                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11862                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11863                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11864
11865                 if (cfg2 & (1 << 17))
11866                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11867
11868                 /* serdes signal pre-emphasis in register 0x590 set by */
11869                 /* bootcode if bit 18 is set */
11870                 if (cfg2 & (1 << 18))
11871                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11872
11873                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11874                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11875                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11876                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11877
11878                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11879                         u32 cfg3;
11880
11881                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11882                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11883                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11884                 }
11885
11886                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11887                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11888                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11889                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11890                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11891                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11892         }
11893 done:
11894         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11895         device_set_wakeup_enable(&tp->pdev->dev,
11896                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11897 }
11898
11899 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11900 {
11901         int i;
11902         u32 val;
11903
11904         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11905         tw32(OTP_CTRL, cmd);
11906
11907         /* Wait for up to 1 ms for command to execute. */
11908         for (i = 0; i < 100; i++) {
11909                 val = tr32(OTP_STATUS);
11910                 if (val & OTP_STATUS_CMD_DONE)
11911                         break;
11912                 udelay(10);
11913         }
11914
11915         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11916 }
11917
11918 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11919  * configuration is a 32-bit value that straddles the alignment boundary.
11920  * We do two 32-bit reads and then shift and merge the results.
11921  */
11922 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11923 {
11924         u32 bhalf_otp, thalf_otp;
11925
11926         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11927
11928         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11929                 return 0;
11930
11931         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11932
11933         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11934                 return 0;
11935
11936         thalf_otp = tr32(OTP_READ_DATA);
11937
11938         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11939
11940         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11941                 return 0;
11942
11943         bhalf_otp = tr32(OTP_READ_DATA);
11944
11945         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11946 }
11947
11948 static int __devinit tg3_phy_probe(struct tg3 *tp)
11949 {
11950         u32 hw_phy_id_1, hw_phy_id_2;
11951         u32 hw_phy_id, hw_phy_id_masked;
11952         int err;
11953
11954         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11955                 return tg3_phy_init(tp);
11956
11957         /* Reading the PHY ID register can conflict with ASF
11958          * firmware access to the PHY hardware.
11959          */
11960         err = 0;
11961         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11962             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11963                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11964         } else {
11965                 /* Now read the physical PHY_ID from the chip and verify
11966                  * that it is sane.  If it doesn't look good, we fall back
11967                  * to either the hard-coded table based PHY_ID and failing
11968                  * that the value found in the eeprom area.
11969                  */
11970                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11971                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11972
11973                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11974                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11975                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11976
11977                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11978         }
11979
11980         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11981                 tp->phy_id = hw_phy_id;
11982                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11983                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11984                 else
11985                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11986         } else {
11987                 if (tp->phy_id != PHY_ID_INVALID) {
11988                         /* Do nothing, phy ID already set up in
11989                          * tg3_get_eeprom_hw_cfg().
11990                          */
11991                 } else {
11992                         struct subsys_tbl_ent *p;
11993
11994                         /* No eeprom signature?  Try the hardcoded
11995                          * subsys device table.
11996                          */
11997                         p = lookup_by_subsys(tp);
11998                         if (!p)
11999                                 return -ENODEV;
12000
12001                         tp->phy_id = p->phy_id;
12002                         if (!tp->phy_id ||
12003                             tp->phy_id == PHY_ID_BCM8002)
12004                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12005                 }
12006         }
12007
12008         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12009             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12010             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12011                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12012
12013                 tg3_readphy(tp, MII_BMSR, &bmsr);
12014                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12015                     (bmsr & BMSR_LSTATUS))
12016                         goto skip_phy_reset;
12017
12018                 err = tg3_phy_reset(tp);
12019                 if (err)
12020                         return err;
12021
12022                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12023                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12024                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12025                 tg3_ctrl = 0;
12026                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12027                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12028                                     MII_TG3_CTRL_ADV_1000_FULL);
12029                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12030                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12031                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12032                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12033                 }
12034
12035                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12036                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12037                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12038                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12039                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12040
12041                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12042                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12043
12044                         tg3_writephy(tp, MII_BMCR,
12045                                      BMCR_ANENABLE | BMCR_ANRESTART);
12046                 }
12047                 tg3_phy_set_wirespeed(tp);
12048
12049                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12050                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12051                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12052         }
12053
12054 skip_phy_reset:
12055         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12056                 err = tg3_init_5401phy_dsp(tp);
12057                 if (err)
12058                         return err;
12059         }
12060
12061         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12062                 err = tg3_init_5401phy_dsp(tp);
12063         }
12064
12065         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12066                 tp->link_config.advertising =
12067                         (ADVERTISED_1000baseT_Half |
12068                          ADVERTISED_1000baseT_Full |
12069                          ADVERTISED_Autoneg |
12070                          ADVERTISED_FIBRE);
12071         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12072                 tp->link_config.advertising &=
12073                         ~(ADVERTISED_1000baseT_Half |
12074                           ADVERTISED_1000baseT_Full);
12075
12076         return err;
12077 }
12078
12079 static void __devinit tg3_read_partno(struct tg3 *tp)
12080 {
12081         unsigned char vpd_data[256];   /* in little-endian format */
12082         unsigned int i;
12083         u32 magic;
12084
12085         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12086             tg3_nvram_read(tp, 0x0, &magic))
12087                 goto out_not_found;
12088
12089         if (magic == TG3_EEPROM_MAGIC) {
12090                 for (i = 0; i < 256; i += 4) {
12091                         u32 tmp;
12092
12093                         /* The data is in little-endian format in NVRAM.
12094                          * Use the big-endian read routines to preserve
12095                          * the byte order as it exists in NVRAM.
12096                          */
12097                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12098                                 goto out_not_found;
12099
12100                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12101                 }
12102         } else {
12103                 int vpd_cap;
12104
12105                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12106                 for (i = 0; i < 256; i += 4) {
12107                         u32 tmp, j = 0;
12108                         __le32 v;
12109                         u16 tmp16;
12110
12111                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12112                                               i);
12113                         while (j++ < 100) {
12114                                 pci_read_config_word(tp->pdev, vpd_cap +
12115                                                      PCI_VPD_ADDR, &tmp16);
12116                                 if (tmp16 & 0x8000)
12117                                         break;
12118                                 msleep(1);
12119                         }
12120                         if (!(tmp16 & 0x8000))
12121                                 goto out_not_found;
12122
12123                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12124                                               &tmp);
12125                         v = cpu_to_le32(tmp);
12126                         memcpy(&vpd_data[i], &v, sizeof(v));
12127                 }
12128         }
12129
12130         /* Now parse and find the part number. */
12131         for (i = 0; i < 254; ) {
12132                 unsigned char val = vpd_data[i];
12133                 unsigned int block_end;
12134
12135                 if (val == 0x82 || val == 0x91) {
12136                         i = (i + 3 +
12137                              (vpd_data[i + 1] +
12138                               (vpd_data[i + 2] << 8)));
12139                         continue;
12140                 }
12141
12142                 if (val != 0x90)
12143                         goto out_not_found;
12144
12145                 block_end = (i + 3 +
12146                              (vpd_data[i + 1] +
12147                               (vpd_data[i + 2] << 8)));
12148                 i += 3;
12149
12150                 if (block_end > 256)
12151                         goto out_not_found;
12152
12153                 while (i < (block_end - 2)) {
12154                         if (vpd_data[i + 0] == 'P' &&
12155                             vpd_data[i + 1] == 'N') {
12156                                 int partno_len = vpd_data[i + 2];
12157
12158                                 i += 3;
12159                                 if (partno_len > 24 || (partno_len + i) > 256)
12160                                         goto out_not_found;
12161
12162                                 memcpy(tp->board_part_number,
12163                                        &vpd_data[i], partno_len);
12164
12165                                 /* Success. */
12166                                 return;
12167                         }
12168                         i += 3 + vpd_data[i + 2];
12169                 }
12170
12171                 /* Part number not found. */
12172                 goto out_not_found;
12173         }
12174
12175 out_not_found:
12176         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12177                 strcpy(tp->board_part_number, "BCM95906");
12178         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12179                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12180                 strcpy(tp->board_part_number, "BCM57780");
12181         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12182                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12183                 strcpy(tp->board_part_number, "BCM57760");
12184         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12185                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12186                 strcpy(tp->board_part_number, "BCM57790");
12187         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12188                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12189                 strcpy(tp->board_part_number, "BCM57788");
12190         else
12191                 strcpy(tp->board_part_number, "none");
12192 }
12193
12194 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12195 {
12196         u32 val;
12197
12198         if (tg3_nvram_read(tp, offset, &val) ||
12199             (val & 0xfc000000) != 0x0c000000 ||
12200             tg3_nvram_read(tp, offset + 4, &val) ||
12201             val != 0)
12202                 return 0;
12203
12204         return 1;
12205 }
12206
12207 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12208 {
12209         u32 val, offset, start, ver_offset;
12210         int i;
12211         bool newver = false;
12212
12213         if (tg3_nvram_read(tp, 0xc, &offset) ||
12214             tg3_nvram_read(tp, 0x4, &start))
12215                 return;
12216
12217         offset = tg3_nvram_logical_addr(tp, offset);
12218
12219         if (tg3_nvram_read(tp, offset, &val))
12220                 return;
12221
12222         if ((val & 0xfc000000) == 0x0c000000) {
12223                 if (tg3_nvram_read(tp, offset + 4, &val))
12224                         return;
12225
12226                 if (val == 0)
12227                         newver = true;
12228         }
12229
12230         if (newver) {
12231                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12232                         return;
12233
12234                 offset = offset + ver_offset - start;
12235                 for (i = 0; i < 16; i += 4) {
12236                         __be32 v;
12237                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12238                                 return;
12239
12240                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12241                 }
12242         } else {
12243                 u32 major, minor;
12244
12245                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12246                         return;
12247
12248                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12249                         TG3_NVM_BCVER_MAJSFT;
12250                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12251                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12252         }
12253 }
12254
12255 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12256 {
12257         u32 val, major, minor;
12258
12259         /* Use native endian representation */
12260         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12261                 return;
12262
12263         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12264                 TG3_NVM_HWSB_CFG1_MAJSFT;
12265         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12266                 TG3_NVM_HWSB_CFG1_MINSFT;
12267
12268         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12269 }
12270
12271 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12272 {
12273         u32 offset, major, minor, build;
12274
12275         tp->fw_ver[0] = 's';
12276         tp->fw_ver[1] = 'b';
12277         tp->fw_ver[2] = '\0';
12278
12279         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12280                 return;
12281
12282         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12283         case TG3_EEPROM_SB_REVISION_0:
12284                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12285                 break;
12286         case TG3_EEPROM_SB_REVISION_2:
12287                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12288                 break;
12289         case TG3_EEPROM_SB_REVISION_3:
12290                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12291                 break;
12292         default:
12293                 return;
12294         }
12295
12296         if (tg3_nvram_read(tp, offset, &val))
12297                 return;
12298
12299         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12300                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12301         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12302                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12303         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12304
12305         if (minor > 99 || build > 26)
12306                 return;
12307
12308         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12309
12310         if (build > 0) {
12311                 tp->fw_ver[8] = 'a' + build - 1;
12312                 tp->fw_ver[9] = '\0';
12313         }
12314 }
12315
12316 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12317 {
12318         u32 val, offset, start;
12319         int i, vlen;
12320
12321         for (offset = TG3_NVM_DIR_START;
12322              offset < TG3_NVM_DIR_END;
12323              offset += TG3_NVM_DIRENT_SIZE) {
12324                 if (tg3_nvram_read(tp, offset, &val))
12325                         return;
12326
12327                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12328                         break;
12329         }
12330
12331         if (offset == TG3_NVM_DIR_END)
12332                 return;
12333
12334         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12335                 start = 0x08000000;
12336         else if (tg3_nvram_read(tp, offset - 4, &start))
12337                 return;
12338
12339         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12340             !tg3_fw_img_is_valid(tp, offset) ||
12341             tg3_nvram_read(tp, offset + 8, &val))
12342                 return;
12343
12344         offset += val - start;
12345
12346         vlen = strlen(tp->fw_ver);
12347
12348         tp->fw_ver[vlen++] = ',';
12349         tp->fw_ver[vlen++] = ' ';
12350
12351         for (i = 0; i < 4; i++) {
12352                 __be32 v;
12353                 if (tg3_nvram_read_be32(tp, offset, &v))
12354                         return;
12355
12356                 offset += sizeof(v);
12357
12358                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12359                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12360                         break;
12361                 }
12362
12363                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12364                 vlen += sizeof(v);
12365         }
12366 }
12367
12368 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12369 {
12370         int vlen;
12371         u32 apedata;
12372
12373         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12374             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12375                 return;
12376
12377         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12378         if (apedata != APE_SEG_SIG_MAGIC)
12379                 return;
12380
12381         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12382         if (!(apedata & APE_FW_STATUS_READY))
12383                 return;
12384
12385         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12386
12387         vlen = strlen(tp->fw_ver);
12388
12389         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12390                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12391                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12392                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12393                  (apedata & APE_FW_VERSION_BLDMSK));
12394 }
12395
12396 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12397 {
12398         u32 val;
12399
12400         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12401                 tp->fw_ver[0] = 's';
12402                 tp->fw_ver[1] = 'b';
12403                 tp->fw_ver[2] = '\0';
12404
12405                 return;
12406         }
12407
12408         if (tg3_nvram_read(tp, 0, &val))
12409                 return;
12410
12411         if (val == TG3_EEPROM_MAGIC)
12412                 tg3_read_bc_ver(tp);
12413         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12414                 tg3_read_sb_ver(tp, val);
12415         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12416                 tg3_read_hwsb_ver(tp);
12417         else
12418                 return;
12419
12420         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12421              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12422                 return;
12423
12424         tg3_read_mgmtfw_ver(tp);
12425
12426         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12427 }
12428
12429 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12430
12431 static int __devinit tg3_get_invariants(struct tg3 *tp)
12432 {
12433         static struct pci_device_id write_reorder_chipsets[] = {
12434                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12435                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12436                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12437                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12438                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12439                              PCI_DEVICE_ID_VIA_8385_0) },
12440                 { },
12441         };
12442         u32 misc_ctrl_reg;
12443         u32 pci_state_reg, grc_misc_cfg;
12444         u32 val;
12445         u16 pci_cmd;
12446         int err;
12447
12448         /* Force memory write invalidate off.  If we leave it on,
12449          * then on 5700_BX chips we have to enable a workaround.
12450          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12451          * to match the cacheline size.  The Broadcom driver have this
12452          * workaround but turns MWI off all the times so never uses
12453          * it.  This seems to suggest that the workaround is insufficient.
12454          */
12455         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12456         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12457         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12458
12459         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12460          * has the register indirect write enable bit set before
12461          * we try to access any of the MMIO registers.  It is also
12462          * critical that the PCI-X hw workaround situation is decided
12463          * before that as well.
12464          */
12465         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12466                               &misc_ctrl_reg);
12467
12468         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12469                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12470         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12471                 u32 prod_id_asic_rev;
12472
12473                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12474                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12475                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12476                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12477                         pci_read_config_dword(tp->pdev,
12478                                               TG3PCI_GEN2_PRODID_ASICREV,
12479                                               &prod_id_asic_rev);
12480                 else
12481                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12482                                               &prod_id_asic_rev);
12483
12484                 tp->pci_chip_rev_id = prod_id_asic_rev;
12485         }
12486
12487         /* Wrong chip ID in 5752 A0. This code can be removed later
12488          * as A0 is not in production.
12489          */
12490         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12491                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12492
12493         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12494          * we need to disable memory and use config. cycles
12495          * only to access all registers. The 5702/03 chips
12496          * can mistakenly decode the special cycles from the
12497          * ICH chipsets as memory write cycles, causing corruption
12498          * of register and memory space. Only certain ICH bridges
12499          * will drive special cycles with non-zero data during the
12500          * address phase which can fall within the 5703's address
12501          * range. This is not an ICH bug as the PCI spec allows
12502          * non-zero address during special cycles. However, only
12503          * these ICH bridges are known to drive non-zero addresses
12504          * during special cycles.
12505          *
12506          * Since special cycles do not cross PCI bridges, we only
12507          * enable this workaround if the 5703 is on the secondary
12508          * bus of these ICH bridges.
12509          */
12510         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12511             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12512                 static struct tg3_dev_id {
12513                         u32     vendor;
12514                         u32     device;
12515                         u32     rev;
12516                 } ich_chipsets[] = {
12517                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12518                           PCI_ANY_ID },
12519                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12520                           PCI_ANY_ID },
12521                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12522                           0xa },
12523                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12524                           PCI_ANY_ID },
12525                         { },
12526                 };
12527                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12528                 struct pci_dev *bridge = NULL;
12529
12530                 while (pci_id->vendor != 0) {
12531                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12532                                                 bridge);
12533                         if (!bridge) {
12534                                 pci_id++;
12535                                 continue;
12536                         }
12537                         if (pci_id->rev != PCI_ANY_ID) {
12538                                 if (bridge->revision > pci_id->rev)
12539                                         continue;
12540                         }
12541                         if (bridge->subordinate &&
12542                             (bridge->subordinate->number ==
12543                              tp->pdev->bus->number)) {
12544
12545                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12546                                 pci_dev_put(bridge);
12547                                 break;
12548                         }
12549                 }
12550         }
12551
12552         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12553                 static struct tg3_dev_id {
12554                         u32     vendor;
12555                         u32     device;
12556                 } bridge_chipsets[] = {
12557                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12558                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12559                         { },
12560                 };
12561                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12562                 struct pci_dev *bridge = NULL;
12563
12564                 while (pci_id->vendor != 0) {
12565                         bridge = pci_get_device(pci_id->vendor,
12566                                                 pci_id->device,
12567                                                 bridge);
12568                         if (!bridge) {
12569                                 pci_id++;
12570                                 continue;
12571                         }
12572                         if (bridge->subordinate &&
12573                             (bridge->subordinate->number <=
12574                              tp->pdev->bus->number) &&
12575                             (bridge->subordinate->subordinate >=
12576                              tp->pdev->bus->number)) {
12577                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12578                                 pci_dev_put(bridge);
12579                                 break;
12580                         }
12581                 }
12582         }
12583
12584         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12585          * DMA addresses > 40-bit. This bridge may have other additional
12586          * 57xx devices behind it in some 4-port NIC designs for example.
12587          * Any tg3 device found behind the bridge will also need the 40-bit
12588          * DMA workaround.
12589          */
12590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12591             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12592                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12593                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12594                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12595         }
12596         else {
12597                 struct pci_dev *bridge = NULL;
12598
12599                 do {
12600                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12601                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12602                                                 bridge);
12603                         if (bridge && bridge->subordinate &&
12604                             (bridge->subordinate->number <=
12605                              tp->pdev->bus->number) &&
12606                             (bridge->subordinate->subordinate >=
12607                              tp->pdev->bus->number)) {
12608                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12609                                 pci_dev_put(bridge);
12610                                 break;
12611                         }
12612                 } while (bridge);
12613         }
12614
12615         /* Initialize misc host control in PCI block. */
12616         tp->misc_host_ctrl |= (misc_ctrl_reg &
12617                                MISC_HOST_CTRL_CHIPREV);
12618         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12619                                tp->misc_host_ctrl);
12620
12621         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12622             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12623             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12624                 tp->pdev_peer = tg3_find_peer(tp);
12625
12626         /* Intentionally exclude ASIC_REV_5906 */
12627         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12628             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12629             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12630             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12631             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12632             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12633             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12634                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12635
12636         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12637             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12638             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12639             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12640             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12641                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12642
12643         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12644             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12645                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12646
12647         /* 5700 B0 chips do not support checksumming correctly due
12648          * to hardware bugs.
12649          */
12650         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12651                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12652         else {
12653                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12654                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12655                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12656                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12657         }
12658
12659         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12660                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12661                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12662                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12663                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12664                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12665                      tp->pdev_peer == tp->pdev))
12666                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12667
12668                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12669                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12670                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12671                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12672                 } else {
12673                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12674                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12675                                 ASIC_REV_5750 &&
12676                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12677                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12678                 }
12679         }
12680
12681         tp->irq_max = 1;
12682
12683         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12684                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12685                 tp->irq_max = TG3_IRQ_MAX_VECS;
12686         }
12687
12688         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12689                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12690                         tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12691                 else {
12692                         tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12693                         tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12694                 }
12695         }
12696
12697         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12698              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12699             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12700                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12701
12702         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12703                               &pci_state_reg);
12704
12705         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12706         if (tp->pcie_cap != 0) {
12707                 u16 lnkctl;
12708
12709                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12710
12711                 pcie_set_readrq(tp->pdev, 4096);
12712
12713                 pci_read_config_word(tp->pdev,
12714                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12715                                      &lnkctl);
12716                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12717                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12718                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12719                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12720                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12721                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12722                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12723                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12724                 }
12725         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12726                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12727         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12728                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12729                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12730                 if (!tp->pcix_cap) {
12731                         printk(KERN_ERR PFX "Cannot find PCI-X "
12732                                             "capability, aborting.\n");
12733                         return -EIO;
12734                 }
12735
12736                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12737                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12738         }
12739
12740         /* If we have an AMD 762 or VIA K8T800 chipset, write
12741          * reordering to the mailbox registers done by the host
12742          * controller can cause major troubles.  We read back from
12743          * every mailbox register write to force the writes to be
12744          * posted to the chip in order.
12745          */
12746         if (pci_dev_present(write_reorder_chipsets) &&
12747             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12748                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12749
12750         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12751                              &tp->pci_cacheline_sz);
12752         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12753                              &tp->pci_lat_timer);
12754         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12755             tp->pci_lat_timer < 64) {
12756                 tp->pci_lat_timer = 64;
12757                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12758                                       tp->pci_lat_timer);
12759         }
12760
12761         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12762                 /* 5700 BX chips need to have their TX producer index
12763                  * mailboxes written twice to workaround a bug.
12764                  */
12765                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12766
12767                 /* If we are in PCI-X mode, enable register write workaround.
12768                  *
12769                  * The workaround is to use indirect register accesses
12770                  * for all chip writes not to mailbox registers.
12771                  */
12772                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12773                         u32 pm_reg;
12774
12775                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12776
12777                         /* The chip can have it's power management PCI config
12778                          * space registers clobbered due to this bug.
12779                          * So explicitly force the chip into D0 here.
12780                          */
12781                         pci_read_config_dword(tp->pdev,
12782                                               tp->pm_cap + PCI_PM_CTRL,
12783                                               &pm_reg);
12784                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12785                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12786                         pci_write_config_dword(tp->pdev,
12787                                                tp->pm_cap + PCI_PM_CTRL,
12788                                                pm_reg);
12789
12790                         /* Also, force SERR#/PERR# in PCI command. */
12791                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12792                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12793                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12794                 }
12795         }
12796
12797         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12798                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12799         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12800                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12801
12802         /* Chip-specific fixup from Broadcom driver */
12803         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12804             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12805                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12806                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12807         }
12808
12809         /* Default fast path register access methods */
12810         tp->read32 = tg3_read32;
12811         tp->write32 = tg3_write32;
12812         tp->read32_mbox = tg3_read32;
12813         tp->write32_mbox = tg3_write32;
12814         tp->write32_tx_mbox = tg3_write32;
12815         tp->write32_rx_mbox = tg3_write32;
12816
12817         /* Various workaround register access methods */
12818         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12819                 tp->write32 = tg3_write_indirect_reg32;
12820         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12821                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12822                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12823                 /*
12824                  * Back to back register writes can cause problems on these
12825                  * chips, the workaround is to read back all reg writes
12826                  * except those to mailbox regs.
12827                  *
12828                  * See tg3_write_indirect_reg32().
12829                  */
12830                 tp->write32 = tg3_write_flush_reg32;
12831         }
12832
12833         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12834             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12835                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12836                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12837                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12838         }
12839
12840         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12841                 tp->read32 = tg3_read_indirect_reg32;
12842                 tp->write32 = tg3_write_indirect_reg32;
12843                 tp->read32_mbox = tg3_read_indirect_mbox;
12844                 tp->write32_mbox = tg3_write_indirect_mbox;
12845                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12846                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12847
12848                 iounmap(tp->regs);
12849                 tp->regs = NULL;
12850
12851                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12852                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12853                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12854         }
12855         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12856                 tp->read32_mbox = tg3_read32_mbox_5906;
12857                 tp->write32_mbox = tg3_write32_mbox_5906;
12858                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12859                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12860         }
12861
12862         if (tp->write32 == tg3_write_indirect_reg32 ||
12863             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12864              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12865               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12866                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12867
12868         /* Get eeprom hw config before calling tg3_set_power_state().
12869          * In particular, the TG3_FLG2_IS_NIC flag must be
12870          * determined before calling tg3_set_power_state() so that
12871          * we know whether or not to switch out of Vaux power.
12872          * When the flag is set, it means that GPIO1 is used for eeprom
12873          * write protect and also implies that it is a LOM where GPIOs
12874          * are not used to switch power.
12875          */
12876         tg3_get_eeprom_hw_cfg(tp);
12877
12878         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12879                 /* Allow reads and writes to the
12880                  * APE register and memory space.
12881                  */
12882                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12883                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12884                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12885                                        pci_state_reg);
12886         }
12887
12888         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12889             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12890             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12891             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12892             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12893                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12894
12895         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12896          * GPIO1 driven high will bring 5700's external PHY out of reset.
12897          * It is also used as eeprom write protect on LOMs.
12898          */
12899         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12900         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12901             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12902                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12903                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12904         /* Unused GPIO3 must be driven as output on 5752 because there
12905          * are no pull-up resistors on unused GPIO pins.
12906          */
12907         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12908                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12909
12910         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12911             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12912                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12913
12914         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12915             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12916                 /* Turn off the debug UART. */
12917                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12918                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12919                         /* Keep VMain power. */
12920                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12921                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12922         }
12923
12924         /* Force the chip into D0. */
12925         err = tg3_set_power_state(tp, PCI_D0);
12926         if (err) {
12927                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12928                        pci_name(tp->pdev));
12929                 return err;
12930         }
12931
12932         /* Derive initial jumbo mode from MTU assigned in
12933          * ether_setup() via the alloc_etherdev() call
12934          */
12935         if (tp->dev->mtu > ETH_DATA_LEN &&
12936             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12937                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12938
12939         /* Determine WakeOnLan speed to use. */
12940         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12941             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12942             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12943             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12944                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12945         } else {
12946                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12947         }
12948
12949         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12950                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12951
12952         /* A few boards don't want Ethernet@WireSpeed phy feature */
12953         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12954             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12955              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12956              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12957             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12958             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12959                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12960
12961         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12962             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12963                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12964         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12965                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12966
12967         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12968             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12969             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12970             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12971             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
12972                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12973                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12974                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12975                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12976                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12977                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12978                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12979                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12980                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12981                 } else
12982                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12983         }
12984
12985         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12986             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12987                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12988                 if (tp->phy_otp == 0)
12989                         tp->phy_otp = TG3_OTP_DEFAULT;
12990         }
12991
12992         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12993                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12994         else
12995                 tp->mi_mode = MAC_MI_MODE_BASE;
12996
12997         tp->coalesce_mode = 0;
12998         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12999             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13000                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13001
13002         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13003             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13004                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13005
13006         err = tg3_mdio_init(tp);
13007         if (err)
13008                 return err;
13009
13010         /* Initialize data/descriptor byte/word swapping. */
13011         val = tr32(GRC_MODE);
13012         val &= GRC_MODE_HOST_STACKUP;
13013         tw32(GRC_MODE, val | tp->grc_mode);
13014
13015         tg3_switch_clocks(tp);
13016
13017         /* Clear this out for sanity. */
13018         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13019
13020         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13021                               &pci_state_reg);
13022         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13023             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13024                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13025
13026                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13027                     chiprevid == CHIPREV_ID_5701_B0 ||
13028                     chiprevid == CHIPREV_ID_5701_B2 ||
13029                     chiprevid == CHIPREV_ID_5701_B5) {
13030                         void __iomem *sram_base;
13031
13032                         /* Write some dummy words into the SRAM status block
13033                          * area, see if it reads back correctly.  If the return
13034                          * value is bad, force enable the PCIX workaround.
13035                          */
13036                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13037
13038                         writel(0x00000000, sram_base);
13039                         writel(0x00000000, sram_base + 4);
13040                         writel(0xffffffff, sram_base + 4);
13041                         if (readl(sram_base) != 0x00000000)
13042                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13043                 }
13044         }
13045
13046         udelay(50);
13047         tg3_nvram_init(tp);
13048
13049         grc_misc_cfg = tr32(GRC_MISC_CFG);
13050         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13051
13052         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13053             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13054              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13055                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13056
13057         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13058             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13059                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13060         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13061                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13062                                       HOSTCC_MODE_CLRTICK_TXBD);
13063
13064                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13065                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13066                                        tp->misc_host_ctrl);
13067         }
13068
13069         /* Preserve the APE MAC_MODE bits */
13070         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13071                 tp->mac_mode = tr32(MAC_MODE) |
13072                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13073         else
13074                 tp->mac_mode = TG3_DEF_MAC_MODE;
13075
13076         /* these are limited to 10/100 only */
13077         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13078              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13079             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13080              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13081              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13082               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13083               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13084             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13085              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13086               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13087               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13088             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13089             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13090                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13091
13092         err = tg3_phy_probe(tp);
13093         if (err) {
13094                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13095                        pci_name(tp->pdev), err);
13096                 /* ... but do not return immediately ... */
13097                 tg3_mdio_fini(tp);
13098         }
13099
13100         tg3_read_partno(tp);
13101         tg3_read_fw_ver(tp);
13102
13103         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13104                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13105         } else {
13106                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13107                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13108                 else
13109                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13110         }
13111
13112         /* 5700 {AX,BX} chips have a broken status block link
13113          * change bit implementation, so we must use the
13114          * status register in those cases.
13115          */
13116         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13117                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13118         else
13119                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13120
13121         /* The led_ctrl is set during tg3_phy_probe, here we might
13122          * have to force the link status polling mechanism based
13123          * upon subsystem IDs.
13124          */
13125         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13126             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13127             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13128                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13129                                   TG3_FLAG_USE_LINKCHG_REG);
13130         }
13131
13132         /* For all SERDES we poll the MAC status register. */
13133         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13134                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13135         else
13136                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13137
13138         tp->rx_offset = NET_IP_ALIGN;
13139         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13140             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13141                 tp->rx_offset = 0;
13142
13143         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13144
13145         /* Increment the rx prod index on the rx std ring by at most
13146          * 8 for these chips to workaround hw errata.
13147          */
13148         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13149             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13150             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13151                 tp->rx_std_max_post = 8;
13152
13153         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13154                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13155                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13156
13157         return err;
13158 }
13159
13160 #ifdef CONFIG_SPARC
13161 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13162 {
13163         struct net_device *dev = tp->dev;
13164         struct pci_dev *pdev = tp->pdev;
13165         struct device_node *dp = pci_device_to_OF_node(pdev);
13166         const unsigned char *addr;
13167         int len;
13168
13169         addr = of_get_property(dp, "local-mac-address", &len);
13170         if (addr && len == 6) {
13171                 memcpy(dev->dev_addr, addr, 6);
13172                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13173                 return 0;
13174         }
13175         return -ENODEV;
13176 }
13177
13178 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13179 {
13180         struct net_device *dev = tp->dev;
13181
13182         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13183         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13184         return 0;
13185 }
13186 #endif
13187
13188 static int __devinit tg3_get_device_address(struct tg3 *tp)
13189 {
13190         struct net_device *dev = tp->dev;
13191         u32 hi, lo, mac_offset;
13192         int addr_ok = 0;
13193
13194 #ifdef CONFIG_SPARC
13195         if (!tg3_get_macaddr_sparc(tp))
13196                 return 0;
13197 #endif
13198
13199         mac_offset = 0x7c;
13200         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13201             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13202                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13203                         mac_offset = 0xcc;
13204                 if (tg3_nvram_lock(tp))
13205                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13206                 else
13207                         tg3_nvram_unlock(tp);
13208         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13209                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13210                         mac_offset = 0xcc;
13211         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13212                 mac_offset = 0x10;
13213
13214         /* First try to get it from MAC address mailbox. */
13215         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13216         if ((hi >> 16) == 0x484b) {
13217                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13218                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13219
13220                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13221                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13222                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13223                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13224                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13225
13226                 /* Some old bootcode may report a 0 MAC address in SRAM */
13227                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13228         }
13229         if (!addr_ok) {
13230                 /* Next, try NVRAM. */
13231                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13232                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13233                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13234                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13235                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13236                 }
13237                 /* Finally just fetch it out of the MAC control regs. */
13238                 else {
13239                         hi = tr32(MAC_ADDR_0_HIGH);
13240                         lo = tr32(MAC_ADDR_0_LOW);
13241
13242                         dev->dev_addr[5] = lo & 0xff;
13243                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13244                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13245                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13246                         dev->dev_addr[1] = hi & 0xff;
13247                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13248                 }
13249         }
13250
13251         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13252 #ifdef CONFIG_SPARC
13253                 if (!tg3_get_default_macaddr_sparc(tp))
13254                         return 0;
13255 #endif
13256                 return -EINVAL;
13257         }
13258         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13259         return 0;
13260 }
13261
13262 #define BOUNDARY_SINGLE_CACHELINE       1
13263 #define BOUNDARY_MULTI_CACHELINE        2
13264
13265 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13266 {
13267         int cacheline_size;
13268         u8 byte;
13269         int goal;
13270
13271         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13272         if (byte == 0)
13273                 cacheline_size = 1024;
13274         else
13275                 cacheline_size = (int) byte * 4;
13276
13277         /* On 5703 and later chips, the boundary bits have no
13278          * effect.
13279          */
13280         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13281             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13282             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13283                 goto out;
13284
13285 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13286         goal = BOUNDARY_MULTI_CACHELINE;
13287 #else
13288 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13289         goal = BOUNDARY_SINGLE_CACHELINE;
13290 #else
13291         goal = 0;
13292 #endif
13293 #endif
13294
13295         if (!goal)
13296                 goto out;
13297
13298         /* PCI controllers on most RISC systems tend to disconnect
13299          * when a device tries to burst across a cache-line boundary.
13300          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13301          *
13302          * Unfortunately, for PCI-E there are only limited
13303          * write-side controls for this, and thus for reads
13304          * we will still get the disconnects.  We'll also waste
13305          * these PCI cycles for both read and write for chips
13306          * other than 5700 and 5701 which do not implement the
13307          * boundary bits.
13308          */
13309         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13310             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13311                 switch (cacheline_size) {
13312                 case 16:
13313                 case 32:
13314                 case 64:
13315                 case 128:
13316                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13317                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13318                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13319                         } else {
13320                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13321                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13322                         }
13323                         break;
13324
13325                 case 256:
13326                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13327                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13328                         break;
13329
13330                 default:
13331                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13332                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13333                         break;
13334                 }
13335         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13336                 switch (cacheline_size) {
13337                 case 16:
13338                 case 32:
13339                 case 64:
13340                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13341                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13342                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13343                                 break;
13344                         }
13345                         /* fallthrough */
13346                 case 128:
13347                 default:
13348                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13349                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13350                         break;
13351                 }
13352         } else {
13353                 switch (cacheline_size) {
13354                 case 16:
13355                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13356                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13357                                         DMA_RWCTRL_WRITE_BNDRY_16);
13358                                 break;
13359                         }
13360                         /* fallthrough */
13361                 case 32:
13362                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13363                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13364                                         DMA_RWCTRL_WRITE_BNDRY_32);
13365                                 break;
13366                         }
13367                         /* fallthrough */
13368                 case 64:
13369                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13370                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13371                                         DMA_RWCTRL_WRITE_BNDRY_64);
13372                                 break;
13373                         }
13374                         /* fallthrough */
13375                 case 128:
13376                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13377                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13378                                         DMA_RWCTRL_WRITE_BNDRY_128);
13379                                 break;
13380                         }
13381                         /* fallthrough */
13382                 case 256:
13383                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13384                                 DMA_RWCTRL_WRITE_BNDRY_256);
13385                         break;
13386                 case 512:
13387                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13388                                 DMA_RWCTRL_WRITE_BNDRY_512);
13389                         break;
13390                 case 1024:
13391                 default:
13392                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13393                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13394                         break;
13395                 }
13396         }
13397
13398 out:
13399         return val;
13400 }
13401
13402 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13403 {
13404         struct tg3_internal_buffer_desc test_desc;
13405         u32 sram_dma_descs;
13406         int i, ret;
13407
13408         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13409
13410         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13411         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13412         tw32(RDMAC_STATUS, 0);
13413         tw32(WDMAC_STATUS, 0);
13414
13415         tw32(BUFMGR_MODE, 0);
13416         tw32(FTQ_RESET, 0);
13417
13418         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13419         test_desc.addr_lo = buf_dma & 0xffffffff;
13420         test_desc.nic_mbuf = 0x00002100;
13421         test_desc.len = size;
13422
13423         /*
13424          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13425          * the *second* time the tg3 driver was getting loaded after an
13426          * initial scan.
13427          *
13428          * Broadcom tells me:
13429          *   ...the DMA engine is connected to the GRC block and a DMA
13430          *   reset may affect the GRC block in some unpredictable way...
13431          *   The behavior of resets to individual blocks has not been tested.
13432          *
13433          * Broadcom noted the GRC reset will also reset all sub-components.
13434          */
13435         if (to_device) {
13436                 test_desc.cqid_sqid = (13 << 8) | 2;
13437
13438                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13439                 udelay(40);
13440         } else {
13441                 test_desc.cqid_sqid = (16 << 8) | 7;
13442
13443                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13444                 udelay(40);
13445         }
13446         test_desc.flags = 0x00000005;
13447
13448         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13449                 u32 val;
13450
13451                 val = *(((u32 *)&test_desc) + i);
13452                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13453                                        sram_dma_descs + (i * sizeof(u32)));
13454                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13455         }
13456         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13457
13458         if (to_device) {
13459                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13460         } else {
13461                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13462         }
13463
13464         ret = -ENODEV;
13465         for (i = 0; i < 40; i++) {
13466                 u32 val;
13467
13468                 if (to_device)
13469                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13470                 else
13471                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13472                 if ((val & 0xffff) == sram_dma_descs) {
13473                         ret = 0;
13474                         break;
13475                 }
13476
13477                 udelay(100);
13478         }
13479
13480         return ret;
13481 }
13482
13483 #define TEST_BUFFER_SIZE        0x2000
13484
13485 static int __devinit tg3_test_dma(struct tg3 *tp)
13486 {
13487         dma_addr_t buf_dma;
13488         u32 *buf, saved_dma_rwctrl;
13489         int ret;
13490
13491         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13492         if (!buf) {
13493                 ret = -ENOMEM;
13494                 goto out_nofree;
13495         }
13496
13497         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13498                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13499
13500         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13501
13502         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13503                 /* DMA read watermark not used on PCIE */
13504                 tp->dma_rwctrl |= 0x00180000;
13505         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13506                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13507                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13508                         tp->dma_rwctrl |= 0x003f0000;
13509                 else
13510                         tp->dma_rwctrl |= 0x003f000f;
13511         } else {
13512                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13513                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13514                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13515                         u32 read_water = 0x7;
13516
13517                         /* If the 5704 is behind the EPB bridge, we can
13518                          * do the less restrictive ONE_DMA workaround for
13519                          * better performance.
13520                          */
13521                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13522                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13523                                 tp->dma_rwctrl |= 0x8000;
13524                         else if (ccval == 0x6 || ccval == 0x7)
13525                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13526
13527                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13528                                 read_water = 4;
13529                         /* Set bit 23 to enable PCIX hw bug fix */
13530                         tp->dma_rwctrl |=
13531                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13532                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13533                                 (1 << 23);
13534                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13535                         /* 5780 always in PCIX mode */
13536                         tp->dma_rwctrl |= 0x00144000;
13537                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13538                         /* 5714 always in PCIX mode */
13539                         tp->dma_rwctrl |= 0x00148000;
13540                 } else {
13541                         tp->dma_rwctrl |= 0x001b000f;
13542                 }
13543         }
13544
13545         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13546             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13547                 tp->dma_rwctrl &= 0xfffffff0;
13548
13549         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13550             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13551                 /* Remove this if it causes problems for some boards. */
13552                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13553
13554                 /* On 5700/5701 chips, we need to set this bit.
13555                  * Otherwise the chip will issue cacheline transactions
13556                  * to streamable DMA memory with not all the byte
13557                  * enables turned on.  This is an error on several
13558                  * RISC PCI controllers, in particular sparc64.
13559                  *
13560                  * On 5703/5704 chips, this bit has been reassigned
13561                  * a different meaning.  In particular, it is used
13562                  * on those chips to enable a PCI-X workaround.
13563                  */
13564                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13565         }
13566
13567         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13568
13569 #if 0
13570         /* Unneeded, already done by tg3_get_invariants.  */
13571         tg3_switch_clocks(tp);
13572 #endif
13573
13574         ret = 0;
13575         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13576             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13577                 goto out;
13578
13579         /* It is best to perform DMA test with maximum write burst size
13580          * to expose the 5700/5701 write DMA bug.
13581          */
13582         saved_dma_rwctrl = tp->dma_rwctrl;
13583         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13584         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13585
13586         while (1) {
13587                 u32 *p = buf, i;
13588
13589                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13590                         p[i] = i;
13591
13592                 /* Send the buffer to the chip. */
13593                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13594                 if (ret) {
13595                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13596                         break;
13597                 }
13598
13599 #if 0
13600                 /* validate data reached card RAM correctly. */
13601                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13602                         u32 val;
13603                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13604                         if (le32_to_cpu(val) != p[i]) {
13605                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13606                                 /* ret = -ENODEV here? */
13607                         }
13608                         p[i] = 0;
13609                 }
13610 #endif
13611                 /* Now read it back. */
13612                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13613                 if (ret) {
13614                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13615
13616                         break;
13617                 }
13618
13619                 /* Verify it. */
13620                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13621                         if (p[i] == i)
13622                                 continue;
13623
13624                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13625                             DMA_RWCTRL_WRITE_BNDRY_16) {
13626                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13627                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13628                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13629                                 break;
13630                         } else {
13631                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13632                                 ret = -ENODEV;
13633                                 goto out;
13634                         }
13635                 }
13636
13637                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13638                         /* Success. */
13639                         ret = 0;
13640                         break;
13641                 }
13642         }
13643         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13644             DMA_RWCTRL_WRITE_BNDRY_16) {
13645                 static struct pci_device_id dma_wait_state_chipsets[] = {
13646                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13647                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13648                         { },
13649                 };
13650
13651                 /* DMA test passed without adjusting DMA boundary,
13652                  * now look for chipsets that are known to expose the
13653                  * DMA bug without failing the test.
13654                  */
13655                 if (pci_dev_present(dma_wait_state_chipsets)) {
13656                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13657                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13658                 }
13659                 else
13660                         /* Safe to use the calculated DMA boundary. */
13661                         tp->dma_rwctrl = saved_dma_rwctrl;
13662
13663                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13664         }
13665
13666 out:
13667         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13668 out_nofree:
13669         return ret;
13670 }
13671
13672 static void __devinit tg3_init_link_config(struct tg3 *tp)
13673 {
13674         tp->link_config.advertising =
13675                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13676                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13677                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13678                  ADVERTISED_Autoneg | ADVERTISED_MII);
13679         tp->link_config.speed = SPEED_INVALID;
13680         tp->link_config.duplex = DUPLEX_INVALID;
13681         tp->link_config.autoneg = AUTONEG_ENABLE;
13682         tp->link_config.active_speed = SPEED_INVALID;
13683         tp->link_config.active_duplex = DUPLEX_INVALID;
13684         tp->link_config.phy_is_low_power = 0;
13685         tp->link_config.orig_speed = SPEED_INVALID;
13686         tp->link_config.orig_duplex = DUPLEX_INVALID;
13687         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13688 }
13689
13690 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13691 {
13692         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13693             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13694                 tp->bufmgr_config.mbuf_read_dma_low_water =
13695                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13696                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13697                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13698                 tp->bufmgr_config.mbuf_high_water =
13699                         DEFAULT_MB_HIGH_WATER_5705;
13700                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13701                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13702                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13703                         tp->bufmgr_config.mbuf_high_water =
13704                                 DEFAULT_MB_HIGH_WATER_5906;
13705                 }
13706
13707                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13708                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13709                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13710                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13711                 tp->bufmgr_config.mbuf_high_water_jumbo =
13712                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13713         } else {
13714                 tp->bufmgr_config.mbuf_read_dma_low_water =
13715                         DEFAULT_MB_RDMA_LOW_WATER;
13716                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13717                         DEFAULT_MB_MACRX_LOW_WATER;
13718                 tp->bufmgr_config.mbuf_high_water =
13719                         DEFAULT_MB_HIGH_WATER;
13720
13721                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13722                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13723                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13724                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13725                 tp->bufmgr_config.mbuf_high_water_jumbo =
13726                         DEFAULT_MB_HIGH_WATER_JUMBO;
13727         }
13728
13729         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13730         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13731 }
13732
13733 static char * __devinit tg3_phy_string(struct tg3 *tp)
13734 {
13735         switch (tp->phy_id & PHY_ID_MASK) {
13736         case PHY_ID_BCM5400:    return "5400";
13737         case PHY_ID_BCM5401:    return "5401";
13738         case PHY_ID_BCM5411:    return "5411";
13739         case PHY_ID_BCM5701:    return "5701";
13740         case PHY_ID_BCM5703:    return "5703";
13741         case PHY_ID_BCM5704:    return "5704";
13742         case PHY_ID_BCM5705:    return "5705";
13743         case PHY_ID_BCM5750:    return "5750";
13744         case PHY_ID_BCM5752:    return "5752";
13745         case PHY_ID_BCM5714:    return "5714";
13746         case PHY_ID_BCM5780:    return "5780";
13747         case PHY_ID_BCM5755:    return "5755";
13748         case PHY_ID_BCM5787:    return "5787";
13749         case PHY_ID_BCM5784:    return "5784";
13750         case PHY_ID_BCM5756:    return "5722/5756";
13751         case PHY_ID_BCM5906:    return "5906";
13752         case PHY_ID_BCM5761:    return "5761";
13753         case PHY_ID_BCM8002:    return "8002/serdes";
13754         case 0:                 return "serdes";
13755         default:                return "unknown";
13756         }
13757 }
13758
13759 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13760 {
13761         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13762                 strcpy(str, "PCI Express");
13763                 return str;
13764         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13765                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13766
13767                 strcpy(str, "PCIX:");
13768
13769                 if ((clock_ctrl == 7) ||
13770                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13771                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13772                         strcat(str, "133MHz");
13773                 else if (clock_ctrl == 0)
13774                         strcat(str, "33MHz");
13775                 else if (clock_ctrl == 2)
13776                         strcat(str, "50MHz");
13777                 else if (clock_ctrl == 4)
13778                         strcat(str, "66MHz");
13779                 else if (clock_ctrl == 6)
13780                         strcat(str, "100MHz");
13781         } else {
13782                 strcpy(str, "PCI:");
13783                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13784                         strcat(str, "66MHz");
13785                 else
13786                         strcat(str, "33MHz");
13787         }
13788         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13789                 strcat(str, ":32-bit");
13790         else
13791                 strcat(str, ":64-bit");
13792         return str;
13793 }
13794
13795 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13796 {
13797         struct pci_dev *peer;
13798         unsigned int func, devnr = tp->pdev->devfn & ~7;
13799
13800         for (func = 0; func < 8; func++) {
13801                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13802                 if (peer && peer != tp->pdev)
13803                         break;
13804                 pci_dev_put(peer);
13805         }
13806         /* 5704 can be configured in single-port mode, set peer to
13807          * tp->pdev in that case.
13808          */
13809         if (!peer) {
13810                 peer = tp->pdev;
13811                 return peer;
13812         }
13813
13814         /*
13815          * We don't need to keep the refcount elevated; there's no way
13816          * to remove one half of this device without removing the other
13817          */
13818         pci_dev_put(peer);
13819
13820         return peer;
13821 }
13822
13823 static void __devinit tg3_init_coal(struct tg3 *tp)
13824 {
13825         struct ethtool_coalesce *ec = &tp->coal;
13826
13827         memset(ec, 0, sizeof(*ec));
13828         ec->cmd = ETHTOOL_GCOALESCE;
13829         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13830         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13831         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13832         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13833         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13834         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13835         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13836         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13837         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13838
13839         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13840                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13841                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13842                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13843                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13844                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13845         }
13846
13847         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13848                 ec->rx_coalesce_usecs_irq = 0;
13849                 ec->tx_coalesce_usecs_irq = 0;
13850                 ec->stats_block_coalesce_usecs = 0;
13851         }
13852 }
13853
13854 static const struct net_device_ops tg3_netdev_ops = {
13855         .ndo_open               = tg3_open,
13856         .ndo_stop               = tg3_close,
13857         .ndo_start_xmit         = tg3_start_xmit,
13858         .ndo_get_stats          = tg3_get_stats,
13859         .ndo_validate_addr      = eth_validate_addr,
13860         .ndo_set_multicast_list = tg3_set_rx_mode,
13861         .ndo_set_mac_address    = tg3_set_mac_addr,
13862         .ndo_do_ioctl           = tg3_ioctl,
13863         .ndo_tx_timeout         = tg3_tx_timeout,
13864         .ndo_change_mtu         = tg3_change_mtu,
13865 #if TG3_VLAN_TAG_USED
13866         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13867 #endif
13868 #ifdef CONFIG_NET_POLL_CONTROLLER
13869         .ndo_poll_controller    = tg3_poll_controller,
13870 #endif
13871 };
13872
13873 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13874         .ndo_open               = tg3_open,
13875         .ndo_stop               = tg3_close,
13876         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13877         .ndo_get_stats          = tg3_get_stats,
13878         .ndo_validate_addr      = eth_validate_addr,
13879         .ndo_set_multicast_list = tg3_set_rx_mode,
13880         .ndo_set_mac_address    = tg3_set_mac_addr,
13881         .ndo_do_ioctl           = tg3_ioctl,
13882         .ndo_tx_timeout         = tg3_tx_timeout,
13883         .ndo_change_mtu         = tg3_change_mtu,
13884 #if TG3_VLAN_TAG_USED
13885         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13886 #endif
13887 #ifdef CONFIG_NET_POLL_CONTROLLER
13888         .ndo_poll_controller    = tg3_poll_controller,
13889 #endif
13890 };
13891
13892 static int __devinit tg3_init_one(struct pci_dev *pdev,
13893                                   const struct pci_device_id *ent)
13894 {
13895         static int tg3_version_printed = 0;
13896         struct net_device *dev;
13897         struct tg3 *tp;
13898         int i, err, pm_cap;
13899         u32 sndmbx, rcvmbx, intmbx;
13900         char str[40];
13901         u64 dma_mask, persist_dma_mask;
13902
13903         if (tg3_version_printed++ == 0)
13904                 printk(KERN_INFO "%s", version);
13905
13906         err = pci_enable_device(pdev);
13907         if (err) {
13908                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13909                        "aborting.\n");
13910                 return err;
13911         }
13912
13913         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13914         if (err) {
13915                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13916                        "aborting.\n");
13917                 goto err_out_disable_pdev;
13918         }
13919
13920         pci_set_master(pdev);
13921
13922         /* Find power-management capability. */
13923         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13924         if (pm_cap == 0) {
13925                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13926                        "aborting.\n");
13927                 err = -EIO;
13928                 goto err_out_free_res;
13929         }
13930
13931         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13932         if (!dev) {
13933                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13934                 err = -ENOMEM;
13935                 goto err_out_free_res;
13936         }
13937
13938         SET_NETDEV_DEV(dev, &pdev->dev);
13939
13940 #if TG3_VLAN_TAG_USED
13941         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13942 #endif
13943
13944         tp = netdev_priv(dev);
13945         tp->pdev = pdev;
13946         tp->dev = dev;
13947         tp->pm_cap = pm_cap;
13948         tp->rx_mode = TG3_DEF_RX_MODE;
13949         tp->tx_mode = TG3_DEF_TX_MODE;
13950
13951         if (tg3_debug > 0)
13952                 tp->msg_enable = tg3_debug;
13953         else
13954                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13955
13956         /* The word/byte swap controls here control register access byte
13957          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13958          * setting below.
13959          */
13960         tp->misc_host_ctrl =
13961                 MISC_HOST_CTRL_MASK_PCI_INT |
13962                 MISC_HOST_CTRL_WORD_SWAP |
13963                 MISC_HOST_CTRL_INDIR_ACCESS |
13964                 MISC_HOST_CTRL_PCISTATE_RW;
13965
13966         /* The NONFRM (non-frame) byte/word swap controls take effect
13967          * on descriptor entries, anything which isn't packet data.
13968          *
13969          * The StrongARM chips on the board (one for tx, one for rx)
13970          * are running in big-endian mode.
13971          */
13972         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13973                         GRC_MODE_WSWAP_NONFRM_DATA);
13974 #ifdef __BIG_ENDIAN
13975         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13976 #endif
13977         spin_lock_init(&tp->lock);
13978         spin_lock_init(&tp->indirect_lock);
13979         INIT_WORK(&tp->reset_task, tg3_reset_task);
13980
13981         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13982         if (!tp->regs) {
13983                 printk(KERN_ERR PFX "Cannot map device registers, "
13984                        "aborting.\n");
13985                 err = -ENOMEM;
13986                 goto err_out_free_dev;
13987         }
13988
13989         tg3_init_link_config(tp);
13990
13991         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13992         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13993
13994         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13995         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13996         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13997         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13998                 struct tg3_napi *tnapi = &tp->napi[i];
13999
14000                 tnapi->tp = tp;
14001                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14002
14003                 tnapi->int_mbox = intmbx;
14004                 if (i < 4)
14005                         intmbx += 0x8;
14006                 else
14007                         intmbx += 0x4;
14008
14009                 tnapi->consmbox = rcvmbx;
14010                 tnapi->prodmbox = sndmbx;
14011
14012                 if (i)
14013                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14014                 else
14015                         tnapi->coal_now = HOSTCC_MODE_NOW;
14016
14017                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14018                         break;
14019
14020                 /*
14021                  * If we support MSIX, we'll be using RSS.  If we're using
14022                  * RSS, the first vector only handles link interrupts and the
14023                  * remaining vectors handle rx and tx interrupts.  Reuse the
14024                  * mailbox values for the next iteration.  The values we setup
14025                  * above are still useful for the single vectored mode.
14026                  */
14027                 if (!i)
14028                         continue;
14029
14030                 rcvmbx += 0x8;
14031
14032                 if (sndmbx & 0x4)
14033                         sndmbx -= 0x4;
14034                 else
14035                         sndmbx += 0xc;
14036         }
14037
14038         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
14039         dev->ethtool_ops = &tg3_ethtool_ops;
14040         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14041         dev->irq = pdev->irq;
14042
14043         err = tg3_get_invariants(tp);
14044         if (err) {
14045                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14046                        "aborting.\n");
14047                 goto err_out_iounmap;
14048         }
14049
14050         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
14051                 dev->netdev_ops = &tg3_netdev_ops;
14052         else
14053                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14054
14055
14056         /* The EPB bridge inside 5714, 5715, and 5780 and any
14057          * device behind the EPB cannot support DMA addresses > 40-bit.
14058          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14059          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14060          * do DMA address check in tg3_start_xmit().
14061          */
14062         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14063                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14064         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14065                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14066 #ifdef CONFIG_HIGHMEM
14067                 dma_mask = DMA_BIT_MASK(64);
14068 #endif
14069         } else
14070                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14071
14072         /* Configure DMA attributes. */
14073         if (dma_mask > DMA_BIT_MASK(32)) {
14074                 err = pci_set_dma_mask(pdev, dma_mask);
14075                 if (!err) {
14076                         dev->features |= NETIF_F_HIGHDMA;
14077                         err = pci_set_consistent_dma_mask(pdev,
14078                                                           persist_dma_mask);
14079                         if (err < 0) {
14080                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14081                                        "DMA for consistent allocations\n");
14082                                 goto err_out_iounmap;
14083                         }
14084                 }
14085         }
14086         if (err || dma_mask == DMA_BIT_MASK(32)) {
14087                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14088                 if (err) {
14089                         printk(KERN_ERR PFX "No usable DMA configuration, "
14090                                "aborting.\n");
14091                         goto err_out_iounmap;
14092                 }
14093         }
14094
14095         tg3_init_bufmgr_config(tp);
14096
14097         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14098                 tp->fw_needed = FIRMWARE_TG3;
14099
14100         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14101                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14102         }
14103         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14104             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14105             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
14106             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14107             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14108                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14109         } else {
14110                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
14111                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14112                         tp->fw_needed = FIRMWARE_TG3TSO5;
14113                 else
14114                         tp->fw_needed = FIRMWARE_TG3TSO;
14115         }
14116
14117         /* TSO is on by default on chips that support hardware TSO.
14118          * Firmware TSO on older chips gives lower performance, so it
14119          * is off by default, but can be enabled using ethtool.
14120          */
14121         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14122                 if (dev->features & NETIF_F_IP_CSUM)
14123                         dev->features |= NETIF_F_TSO;
14124                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14125                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
14126                         dev->features |= NETIF_F_TSO6;
14127                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14128                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14129                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14130                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14131                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14132                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
14133                         dev->features |= NETIF_F_TSO_ECN;
14134         }
14135
14136
14137         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14138             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14139             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14140                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14141                 tp->rx_pending = 63;
14142         }
14143
14144         err = tg3_get_device_address(tp);
14145         if (err) {
14146                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14147                        "aborting.\n");
14148                 goto err_out_fw;
14149         }
14150
14151         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14152                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14153                 if (!tp->aperegs) {
14154                         printk(KERN_ERR PFX "Cannot map APE registers, "
14155                                "aborting.\n");
14156                         err = -ENOMEM;
14157                         goto err_out_fw;
14158                 }
14159
14160                 tg3_ape_lock_init(tp);
14161
14162                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14163                         tg3_read_dash_ver(tp);
14164         }
14165
14166         /*
14167          * Reset chip in case UNDI or EFI driver did not shutdown
14168          * DMA self test will enable WDMAC and we'll see (spurious)
14169          * pending DMA on the PCI bus at that point.
14170          */
14171         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14172             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14173                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14174                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14175         }
14176
14177         err = tg3_test_dma(tp);
14178         if (err) {
14179                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14180                 goto err_out_apeunmap;
14181         }
14182
14183         /* flow control autonegotiation is default behavior */
14184         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14185         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14186
14187         tg3_init_coal(tp);
14188
14189         pci_set_drvdata(pdev, dev);
14190
14191         err = register_netdev(dev);
14192         if (err) {
14193                 printk(KERN_ERR PFX "Cannot register net device, "
14194                        "aborting.\n");
14195                 goto err_out_apeunmap;
14196         }
14197
14198         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14199                dev->name,
14200                tp->board_part_number,
14201                tp->pci_chip_rev_id,
14202                tg3_bus_string(tp, str),
14203                dev->dev_addr);
14204
14205         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14206                 struct phy_device *phydev;
14207                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14208                 printk(KERN_INFO
14209                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14210                        tp->dev->name, phydev->drv->name,
14211                        dev_name(&phydev->dev));
14212         } else
14213                 printk(KERN_INFO
14214                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14215                        tp->dev->name, tg3_phy_string(tp),
14216                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14217                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14218                          "10/100/1000Base-T")),
14219                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14220
14221         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14222                dev->name,
14223                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14224                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14225                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14226                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14227                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14228         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14229                dev->name, tp->dma_rwctrl,
14230                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14231                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14232
14233         return 0;
14234
14235 err_out_apeunmap:
14236         if (tp->aperegs) {
14237                 iounmap(tp->aperegs);
14238                 tp->aperegs = NULL;
14239         }
14240
14241 err_out_fw:
14242         if (tp->fw)
14243                 release_firmware(tp->fw);
14244
14245 err_out_iounmap:
14246         if (tp->regs) {
14247                 iounmap(tp->regs);
14248                 tp->regs = NULL;
14249         }
14250
14251 err_out_free_dev:
14252         free_netdev(dev);
14253
14254 err_out_free_res:
14255         pci_release_regions(pdev);
14256
14257 err_out_disable_pdev:
14258         pci_disable_device(pdev);
14259         pci_set_drvdata(pdev, NULL);
14260         return err;
14261 }
14262
14263 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14264 {
14265         struct net_device *dev = pci_get_drvdata(pdev);
14266
14267         if (dev) {
14268                 struct tg3 *tp = netdev_priv(dev);
14269
14270                 if (tp->fw)
14271                         release_firmware(tp->fw);
14272
14273                 flush_scheduled_work();
14274
14275                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14276                         tg3_phy_fini(tp);
14277                         tg3_mdio_fini(tp);
14278                 }
14279
14280                 unregister_netdev(dev);
14281                 if (tp->aperegs) {
14282                         iounmap(tp->aperegs);
14283                         tp->aperegs = NULL;
14284                 }
14285                 if (tp->regs) {
14286                         iounmap(tp->regs);
14287                         tp->regs = NULL;
14288                 }
14289                 free_netdev(dev);
14290                 pci_release_regions(pdev);
14291                 pci_disable_device(pdev);
14292                 pci_set_drvdata(pdev, NULL);
14293         }
14294 }
14295
14296 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14297 {
14298         struct net_device *dev = pci_get_drvdata(pdev);
14299         struct tg3 *tp = netdev_priv(dev);
14300         pci_power_t target_state;
14301         int err;
14302
14303         /* PCI register 4 needs to be saved whether netif_running() or not.
14304          * MSI address and data need to be saved if using MSI and
14305          * netif_running().
14306          */
14307         pci_save_state(pdev);
14308
14309         if (!netif_running(dev))
14310                 return 0;
14311
14312         flush_scheduled_work();
14313         tg3_phy_stop(tp);
14314         tg3_netif_stop(tp);
14315
14316         del_timer_sync(&tp->timer);
14317
14318         tg3_full_lock(tp, 1);
14319         tg3_disable_ints(tp);
14320         tg3_full_unlock(tp);
14321
14322         netif_device_detach(dev);
14323
14324         tg3_full_lock(tp, 0);
14325         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14326         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14327         tg3_full_unlock(tp);
14328
14329         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14330
14331         err = tg3_set_power_state(tp, target_state);
14332         if (err) {
14333                 int err2;
14334
14335                 tg3_full_lock(tp, 0);
14336
14337                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14338                 err2 = tg3_restart_hw(tp, 1);
14339                 if (err2)
14340                         goto out;
14341
14342                 tp->timer.expires = jiffies + tp->timer_offset;
14343                 add_timer(&tp->timer);
14344
14345                 netif_device_attach(dev);
14346                 tg3_netif_start(tp);
14347
14348 out:
14349                 tg3_full_unlock(tp);
14350
14351                 if (!err2)
14352                         tg3_phy_start(tp);
14353         }
14354
14355         return err;
14356 }
14357
14358 static int tg3_resume(struct pci_dev *pdev)
14359 {
14360         struct net_device *dev = pci_get_drvdata(pdev);
14361         struct tg3 *tp = netdev_priv(dev);
14362         int err;
14363
14364         pci_restore_state(tp->pdev);
14365
14366         if (!netif_running(dev))
14367                 return 0;
14368
14369         err = tg3_set_power_state(tp, PCI_D0);
14370         if (err)
14371                 return err;
14372
14373         netif_device_attach(dev);
14374
14375         tg3_full_lock(tp, 0);
14376
14377         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14378         err = tg3_restart_hw(tp, 1);
14379         if (err)
14380                 goto out;
14381
14382         tp->timer.expires = jiffies + tp->timer_offset;
14383         add_timer(&tp->timer);
14384
14385         tg3_netif_start(tp);
14386
14387 out:
14388         tg3_full_unlock(tp);
14389
14390         if (!err)
14391                 tg3_phy_start(tp);
14392
14393         return err;
14394 }
14395
14396 static struct pci_driver tg3_driver = {
14397         .name           = DRV_MODULE_NAME,
14398         .id_table       = tg3_pci_tbl,
14399         .probe          = tg3_init_one,
14400         .remove         = __devexit_p(tg3_remove_one),
14401         .suspend        = tg3_suspend,
14402         .resume         = tg3_resume
14403 };
14404
14405 static int __init tg3_init(void)
14406 {
14407         return pci_register_driver(&tg3_driver);
14408 }
14409
14410 static void __exit tg3_cleanup(void)
14411 {
14412         pci_unregister_driver(&tg3_driver);
14413 }
14414
14415 module_init(tg3_init);
14416 module_exit(tg3_cleanup);