drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.103"
  72 #define DRV_MODULE_RELDATE      "November 2, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 #define TG3_RX_STD_BUFF_RING_SIZE \
 141         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 142
 143 #define TG3_RX_JMB_BUFF_RING_SIZE \
 144         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 145
 146 /* minimum number of free TX descriptors required to wake up TX process */
 147 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 148
 149 #define TG3_RAW_IP_ALIGN 2
 150
 151 /* number of ETHTOOL_GSTATS u64's */
 152 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 153
 154 #define TG3_NUM_TEST            6
 155
 156 #define FIRMWARE_TG3            "tigon/tg3.bin"
 157 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 158 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 159
 160 static char version[] __devinitdata =
 161         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 162
 163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 165 MODULE_LICENSE("GPL");
 166 MODULE_VERSION(DRV_MODULE_VERSION);
 167 MODULE_FIRMWARE(FIRMWARE_TG3);
 168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 170
 171 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 172
 173 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 174 module_param(tg3_debug, int, 0);
 175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 176
 177 static struct pci_device_id tg3_pci_tbl[] = {
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 254         {}
 255 };
 256
 257 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 258
 259 static const struct {
 260         const char string[ETH_GSTRING_LEN];
 261 } ethtool_stats_keys[TG3_NUM_STATS] = {
 262         { "rx_octets" },
 263         { "rx_fragments" },
 264         { "rx_ucast_packets" },
 265         { "rx_mcast_packets" },
 266         { "rx_bcast_packets" },
 267         { "rx_fcs_errors" },
 268         { "rx_align_errors" },
 269         { "rx_xon_pause_rcvd" },
 270         { "rx_xoff_pause_rcvd" },
 271         { "rx_mac_ctrl_rcvd" },
 272         { "rx_xoff_entered" },
 273         { "rx_frame_too_long_errors" },
 274         { "rx_jabbers" },
 275         { "rx_undersize_packets" },
 276         { "rx_in_length_errors" },
 277         { "rx_out_length_errors" },
 278         { "rx_64_or_less_octet_packets" },
 279         { "rx_65_to_127_octet_packets" },
 280         { "rx_128_to_255_octet_packets" },
 281         { "rx_256_to_511_octet_packets" },
 282         { "rx_512_to_1023_octet_packets" },
 283         { "rx_1024_to_1522_octet_packets" },
 284         { "rx_1523_to_2047_octet_packets" },
 285         { "rx_2048_to_4095_octet_packets" },
 286         { "rx_4096_to_8191_octet_packets" },
 287         { "rx_8192_to_9022_octet_packets" },
 288
 289         { "tx_octets" },
 290         { "tx_collisions" },
 291
 292         { "tx_xon_sent" },
 293         { "tx_xoff_sent" },
 294         { "tx_flow_control" },
 295         { "tx_mac_errors" },
 296         { "tx_single_collisions" },
 297         { "tx_mult_collisions" },
 298         { "tx_deferred" },
 299         { "tx_excessive_collisions" },
 300         { "tx_late_collisions" },
 301         { "tx_collide_2times" },
 302         { "tx_collide_3times" },
 303         { "tx_collide_4times" },
 304         { "tx_collide_5times" },
 305         { "tx_collide_6times" },
 306         { "tx_collide_7times" },
 307         { "tx_collide_8times" },
 308         { "tx_collide_9times" },
 309         { "tx_collide_10times" },
 310         { "tx_collide_11times" },
 311         { "tx_collide_12times" },
 312         { "tx_collide_13times" },
 313         { "tx_collide_14times" },
 314         { "tx_collide_15times" },
 315         { "tx_ucast_packets" },
 316         { "tx_mcast_packets" },
 317         { "tx_bcast_packets" },
 318         { "tx_carrier_sense_errors" },
 319         { "tx_discards" },
 320         { "tx_errors" },
 321
 322         { "dma_writeq_full" },
 323         { "dma_write_prioq_full" },
 324         { "rxbds_empty" },
 325         { "rx_discards" },
 326         { "rx_errors" },
 327         { "rx_threshold_hit" },
 328
 329         { "dma_readq_full" },
 330         { "dma_read_prioq_full" },
 331         { "tx_comp_queue_full" },
 332
 333         { "ring_set_send_prod_index" },
 334         { "ring_status_update" },
 335         { "nic_irqs" },
 336         { "nic_avoided_irqs" },
 337         { "nic_tx_threshold_hit" }
 338 };
 339
 340 static const struct {
 341         const char string[ETH_GSTRING_LEN];
 342 } ethtool_test_keys[TG3_NUM_TEST] = {
 343         { "nvram test     (online) " },
 344         { "link test      (online) " },
 345         { "register test  (offline)" },
 346         { "memory test    (offline)" },
 347         { "loopback test  (offline)" },
 348         { "interrupt test (offline)" },
 349 };
 350
 351 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         writel(val, tp->regs + off);
 354 }
 355
 356 static u32 tg3_read32(struct tg3 *tp, u32 off)
 357 {
 358         return (readl(tp->regs + off));
 359 }
 360
 361 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         writel(val, tp->aperegs + off);
 364 }
 365
 366 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 367 {
 368         return (readl(tp->aperegs + off));
 369 }
 370
 371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 372 {
 373         unsigned long flags;
 374
 375         spin_lock_irqsave(&tp->indirect_lock, flags);
 376         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 377         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 378         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 379 }
 380
 381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->regs + off);
 384         readl(tp->regs + off);
 385 }
 386
 387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 388 {
 389         unsigned long flags;
 390         u32 val;
 391
 392         spin_lock_irqsave(&tp->indirect_lock, flags);
 393         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 394         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 395         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 396         return val;
 397 }
 398
 399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 404                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 405                                        TG3_64BIT_REG_LOW, val);
 406                 return;
 407         }
 408         if (off == TG3_RX_STD_PROD_IDX_REG) {
 409                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 410                                        TG3_64BIT_REG_LOW, val);
 411                 return;
 412         }
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 416         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418
 419         /* In indirect mode when disabling interrupts, we also need
 420          * to clear the interrupt bit in the GRC local ctrl register.
 421          */
 422         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 423             (val == 0x1)) {
 424                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 425                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 426         }
 427 }
 428
 429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 430 {
 431         unsigned long flags;
 432         u32 val;
 433
 434         spin_lock_irqsave(&tp->indirect_lock, flags);
 435         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 436         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 437         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 438         return val;
 439 }
 440
 441 /* usec_wait specifies the wait time in usec when writing to certain registers
 442  * where it is unsafe to read back the register without some delay.
 443  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 444  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 445  */
 446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 447 {
 448         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 449             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 450                 /* Non-posted methods */
 451                 tp->write32(tp, off, val);
 452         else {
 453                 /* Posted method */
 454                 tg3_write32(tp, off, val);
 455                 if (usec_wait)
 456                         udelay(usec_wait);
 457                 tp->read32(tp, off);
 458         }
 459         /* Wait again after the read for the posted method to guarantee that
 460          * the wait time is met.
 461          */
 462         if (usec_wait)
 463                 udelay(usec_wait);
 464 }
 465
 466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 467 {
 468         tp->write32_mbox(tp, off, val);
 469         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 470             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 471                 tp->read32_mbox(tp, off);
 472 }
 473
 474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 475 {
 476         void __iomem *mbox = tp->regs + off;
 477         writel(val, mbox);
 478         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 479                 writel(val, mbox);
 480         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 481                 readl(mbox);
 482 }
 483
 484 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 485 {
 486         return (readl(tp->regs + off + GRCMBOX_BASE));
 487 }
 488
 489 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 490 {
 491         writel(val, tp->regs + off + GRCMBOX_BASE);
 492 }
 493
 494 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 495 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 496 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 497 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 498 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 499
 500 #define tw32(reg,val)           tp->write32(tp, reg, val)
 501 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 502 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 503 #define tr32(reg)               tp->read32(tp, reg)
 504
 505 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 506 {
 507         unsigned long flags;
 508
 509         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 510             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 511                 return;
 512
 513         spin_lock_irqsave(&tp->indirect_lock, flags);
 514         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 515                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 516                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 517
 518                 /* Always leave this as zero. */
 519                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 520         } else {
 521                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 522                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 523
 524                 /* Always leave this as zero. */
 525                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 526         }
 527         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 528 }
 529
 530 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 531 {
 532         unsigned long flags;
 533
 534         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 535             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 536                 *val = 0;
 537                 return;
 538         }
 539
 540         spin_lock_irqsave(&tp->indirect_lock, flags);
 541         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 543                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 544
 545                 /* Always leave this as zero. */
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 547         } else {
 548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 549                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 550
 551                 /* Always leave this as zero. */
 552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 553         }
 554         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 555 }
 556
 557 static void tg3_ape_lock_init(struct tg3 *tp)
 558 {
 559         int i;
 560
 561         /* Make sure the driver hasn't any stale locks. */
 562         for (i = 0; i < 8; i++)
 563                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 564                                 APE_LOCK_GRANT_DRIVER);
 565 }
 566
 567 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 568 {
 569         int i, off;
 570         int ret = 0;
 571         u32 status;
 572
 573         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 574                 return 0;
 575
 576         switch (locknum) {
 577                 case TG3_APE_LOCK_GRC:
 578                 case TG3_APE_LOCK_MEM:
 579                         break;
 580                 default:
 581                         return -EINVAL;
 582         }
 583
 584         off = 4 * locknum;
 585
 586         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 587
 588         /* Wait for up to 1 millisecond to acquire lock. */
 589         for (i = 0; i < 100; i++) {
 590                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 591                 if (status == APE_LOCK_GRANT_DRIVER)
 592                         break;
 593                 udelay(10);
 594         }
 595
 596         if (status != APE_LOCK_GRANT_DRIVER) {
 597                 /* Revoke the lock request. */
 598                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 599                                 APE_LOCK_GRANT_DRIVER);
 600
 601                 ret = -EBUSY;
 602         }
 603
 604         return ret;
 605 }
 606
 607 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 608 {
 609         int off;
 610
 611         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 612                 return;
 613
 614         switch (locknum) {
 615                 case TG3_APE_LOCK_GRC:
 616                 case TG3_APE_LOCK_MEM:
 617                         break;
 618                 default:
 619                         return;
 620         }
 621
 622         off = 4 * locknum;
 623         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 624 }
 625
 626 static void tg3_disable_ints(struct tg3 *tp)
 627 {
 628         int i;
 629
 630         tw32(TG3PCI_MISC_HOST_CTRL,
 631              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 632         for (i = 0; i < tp->irq_max; i++)
 633                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 634 }
 635
 636 static void tg3_enable_ints(struct tg3 *tp)
 637 {
 638         int i;
 639         u32 coal_now = 0;
 640
 641         tp->irq_sync = 0;
 642         wmb();
 643
 644         tw32(TG3PCI_MISC_HOST_CTRL,
 645              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 646
 647         for (i = 0; i < tp->irq_cnt; i++) {
 648                 struct tg3_napi *tnapi = &tp->napi[i];
 649                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 650                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 651                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 652
 653                 coal_now |= tnapi->coal_now;
 654         }
 655
 656         /* Force an initial interrupt */
 657         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 658             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 659                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 660         else
 661                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 662                      HOSTCC_MODE_ENABLE | coal_now);
 663 }
 664
 665 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 666 {
 667         struct tg3 *tp = tnapi->tp;
 668         struct tg3_hw_status *sblk = tnapi->hw_status;
 669         unsigned int work_exists = 0;
 670
 671         /* check for phy events */
 672         if (!(tp->tg3_flags &
 673               (TG3_FLAG_USE_LINKCHG_REG |
 674                TG3_FLAG_POLL_SERDES))) {
 675                 if (sblk->status & SD_STATUS_LINK_CHG)
 676                         work_exists = 1;
 677         }
 678         /* check for RX/TX work to do */
 679         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 680             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 681                 work_exists = 1;
 682
 683         return work_exists;
 684 }
 685
 686 /* tg3_int_reenable
 687  *  similar to tg3_enable_ints, but it accurately determines whether there
 688  *  is new work pending and can return without flushing the PIO write
 689  *  which reenables interrupts
 690  */
 691 static void tg3_int_reenable(struct tg3_napi *tnapi)
 692 {
 693         struct tg3 *tp = tnapi->tp;
 694
 695         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 696         mmiowb();
 697
 698         /* When doing tagged status, this work check is unnecessary.
 699          * The last_tag we write above tells the chip which piece of
 700          * work we've completed.
 701          */
 702         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 703             tg3_has_work(tnapi))
 704                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 705                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 706 }
 707
 708 static void tg3_napi_disable(struct tg3 *tp)
 709 {
 710         int i;
 711
 712         for (i = tp->irq_cnt - 1; i >= 0; i--)
 713                 napi_disable(&tp->napi[i].napi);
 714 }
 715
 716 static void tg3_napi_enable(struct tg3 *tp)
 717 {
 718         int i;
 719
 720         for (i = 0; i < tp->irq_cnt; i++)
 721                 napi_enable(&tp->napi[i].napi);
 722 }
 723
 724 static inline void tg3_netif_stop(struct tg3 *tp)
 725 {
 726         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 727         tg3_napi_disable(tp);
 728         netif_tx_disable(tp->dev);
 729 }
 730
 731 static inline void tg3_netif_start(struct tg3 *tp)
 732 {
 733         /* NOTE: unconditional netif_tx_wake_all_queues is only
 734          * appropriate so long as all callers are assured to
 735          * have free tx slots (such as after tg3_init_hw)
 736          */
 737         netif_tx_wake_all_queues(tp->dev);
 738
 739         tg3_napi_enable(tp);
 740         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 741         tg3_enable_ints(tp);
 742 }
 743
 744 static void tg3_switch_clocks(struct tg3 *tp)
 745 {
 746         u32 clock_ctrl;
 747         u32 orig_clock_ctrl;
 748
 749         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 750             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 751                 return;
 752
 753         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 754
 755         orig_clock_ctrl = clock_ctrl;
 756         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 757                        CLOCK_CTRL_CLKRUN_OENABLE |
 758                        0x1f);
 759         tp->pci_clock_ctrl = clock_ctrl;
 760
 761         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 762                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 763                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 764                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 765                 }
 766         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 767                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 768                             clock_ctrl |
 769                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 770                             40);
 771                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 772                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 773                             40);
 774         }
 775         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 776 }
 777
 778 #define PHY_BUSY_LOOPS  5000
 779
 780 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 781 {
 782         u32 frame_val;
 783         unsigned int loops;
 784         int ret;
 785
 786         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 787                 tw32_f(MAC_MI_MODE,
 788                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 789                 udelay(80);
 790         }
 791
 792         *val = 0x0;
 793
 794         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 795                       MI_COM_PHY_ADDR_MASK);
 796         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 797                       MI_COM_REG_ADDR_MASK);
 798         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 799
 800         tw32_f(MAC_MI_COM, frame_val);
 801
 802         loops = PHY_BUSY_LOOPS;
 803         while (loops != 0) {
 804                 udelay(10);
 805                 frame_val = tr32(MAC_MI_COM);
 806
 807                 if ((frame_val & MI_COM_BUSY) == 0) {
 808                         udelay(5);
 809                         frame_val = tr32(MAC_MI_COM);
 810                         break;
 811                 }
 812                 loops -= 1;
 813         }
 814
 815         ret = -EBUSY;
 816         if (loops != 0) {
 817                 *val = frame_val & MI_COM_DATA_MASK;
 818                 ret = 0;
 819         }
 820
 821         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 822                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 823                 udelay(80);
 824         }
 825
 826         return ret;
 827 }
 828
 829 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 830 {
 831         u32 frame_val;
 832         unsigned int loops;
 833         int ret;
 834
 835         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 836             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 837                 return 0;
 838
 839         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 840                 tw32_f(MAC_MI_MODE,
 841                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 842                 udelay(80);
 843         }
 844
 845         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 846                       MI_COM_PHY_ADDR_MASK);
 847         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 848                       MI_COM_REG_ADDR_MASK);
 849         frame_val |= (val & MI_COM_DATA_MASK);
 850         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 851
 852         tw32_f(MAC_MI_COM, frame_val);
 853
 854         loops = PHY_BUSY_LOOPS;
 855         while (loops != 0) {
 856                 udelay(10);
 857                 frame_val = tr32(MAC_MI_COM);
 858                 if ((frame_val & MI_COM_BUSY) == 0) {
 859                         udelay(5);
 860                         frame_val = tr32(MAC_MI_COM);
 861                         break;
 862                 }
 863                 loops -= 1;
 864         }
 865
 866         ret = -EBUSY;
 867         if (loops != 0)
 868                 ret = 0;
 869
 870         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 871                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 872                 udelay(80);
 873         }
 874
 875         return ret;
 876 }
 877
 878 static int tg3_bmcr_reset(struct tg3 *tp)
 879 {
 880         u32 phy_control;
 881         int limit, err;
 882
 883         /* OK, reset it, and poll the BMCR_RESET bit until it
 884          * clears or we time out.
 885          */
 886         phy_control = BMCR_RESET;
 887         err = tg3_writephy(tp, MII_BMCR, phy_control);
 888         if (err != 0)
 889                 return -EBUSY;
 890
 891         limit = 5000;
 892         while (limit--) {
 893                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 894                 if (err != 0)
 895                         return -EBUSY;
 896
 897                 if ((phy_control & BMCR_RESET) == 0) {
 898                         udelay(40);
 899                         break;
 900                 }
 901                 udelay(10);
 902         }
 903         if (limit < 0)
 904                 return -EBUSY;
 905
 906         return 0;
 907 }
 908
 909 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 910 {
 911         struct tg3 *tp = bp->priv;
 912         u32 val;
 913
 914         spin_lock_bh(&tp->lock);
 915
 916         if (tg3_readphy(tp, reg, &val))
 917                 val = -EIO;
 918
 919         spin_unlock_bh(&tp->lock);
 920
 921         return val;
 922 }
 923
 924 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 925 {
 926         struct tg3 *tp = bp->priv;
 927         u32 ret = 0;
 928
 929         spin_lock_bh(&tp->lock);
 930
 931         if (tg3_writephy(tp, reg, val))
 932                 ret = -EIO;
 933
 934         spin_unlock_bh(&tp->lock);
 935
 936         return ret;
 937 }
 938
 939 static int tg3_mdio_reset(struct mii_bus *bp)
 940 {
 941         return 0;
 942 }
 943
 944 static void tg3_mdio_config_5785(struct tg3 *tp)
 945 {
 946         u32 val;
 947         struct phy_device *phydev;
 948
 949         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 950         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 951         case TG3_PHY_ID_BCM50610:
 952         case TG3_PHY_ID_BCM50610M:
 953                 val = MAC_PHYCFG2_50610_LED_MODES;
 954                 break;
 955         case TG3_PHY_ID_BCMAC131:
 956                 val = MAC_PHYCFG2_AC131_LED_MODES;
 957                 break;
 958         case TG3_PHY_ID_RTL8211C:
 959                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 960                 break;
 961         case TG3_PHY_ID_RTL8201E:
 962                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 963                 break;
 964         default:
 965                 return;
 966         }
 967
 968         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 969                 tw32(MAC_PHYCFG2, val);
 970
 971                 val = tr32(MAC_PHYCFG1);
 972                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 973                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 974                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 975                 tw32(MAC_PHYCFG1, val);
 976
 977                 return;
 978         }
 979
 980         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 981                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 982                        MAC_PHYCFG2_FMODE_MASK_MASK |
 983                        MAC_PHYCFG2_GMODE_MASK_MASK |
 984                        MAC_PHYCFG2_ACT_MASK_MASK   |
 985                        MAC_PHYCFG2_QUAL_MASK_MASK |
 986                        MAC_PHYCFG2_INBAND_ENABLE;
 987
 988         tw32(MAC_PHYCFG2, val);
 989
 990         val = tr32(MAC_PHYCFG1);
 991         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 992                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 994                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 995                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 996                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 997                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 998         }
 999         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001         tw32(MAC_PHYCFG1, val);
1002
1003         val = tr32(MAC_EXT_RGMII_MODE);
1004         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005                  MAC_RGMII_MODE_RX_QUALITY |
1006                  MAC_RGMII_MODE_RX_ACTIVITY |
1007                  MAC_RGMII_MODE_RX_ENG_DET |
1008                  MAC_RGMII_MODE_TX_ENABLE |
1009                  MAC_RGMII_MODE_TX_LOWPWR |
1010                  MAC_RGMII_MODE_TX_RESET);
1011         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1012                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013                         val |= MAC_RGMII_MODE_RX_INT_B |
1014                                MAC_RGMII_MODE_RX_QUALITY |
1015                                MAC_RGMII_MODE_RX_ACTIVITY |
1016                                MAC_RGMII_MODE_RX_ENG_DET;
1017                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018                         val |= MAC_RGMII_MODE_TX_ENABLE |
1019                                MAC_RGMII_MODE_TX_LOWPWR |
1020                                MAC_RGMII_MODE_TX_RESET;
1021         }
1022         tw32(MAC_EXT_RGMII_MODE, val);
1023 }
1024
1025 static void tg3_mdio_start(struct tg3 *tp)
1026 {
1027         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028         tw32_f(MAC_MI_MODE, tp->mi_mode);
1029         udelay(80);
1030
1031         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032                 u32 funcnum, is_serdes;
1033
1034                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1035                 if (funcnum)
1036                         tp->phy_addr = 2;
1037                 else
1038                         tp->phy_addr = 1;
1039
1040                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1041                 if (is_serdes)
1042                         tp->phy_addr += 7;
1043         } else
1044                 tp->phy_addr = TG3_PHY_MII_ADDR;
1045
1046         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048                 tg3_mdio_config_5785(tp);
1049 }
1050
1051 static int tg3_mdio_init(struct tg3 *tp)
1052 {
1053         int i;
1054         u32 reg;
1055         struct phy_device *phydev;
1056
1057         tg3_mdio_start(tp);
1058
1059         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1061                 return 0;
1062
1063         tp->mdio_bus = mdiobus_alloc();
1064         if (tp->mdio_bus == NULL)
1065                 return -ENOMEM;
1066
1067         tp->mdio_bus->name     = "tg3 mdio bus";
1068         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1069                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1070         tp->mdio_bus->priv     = tp;
1071         tp->mdio_bus->parent   = &tp->pdev->dev;
1072         tp->mdio_bus->read     = &tg3_mdio_read;
1073         tp->mdio_bus->write    = &tg3_mdio_write;
1074         tp->mdio_bus->reset    = &tg3_mdio_reset;
1075         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1076         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1077
1078         for (i = 0; i < PHY_MAX_ADDR; i++)
1079                 tp->mdio_bus->irq[i] = PHY_POLL;
1080
1081         /* The bus registration will look for all the PHYs on the mdio bus.
1082          * Unfortunately, it does not ensure the PHY is powered up before
1083          * accessing the PHY ID registers.  A chip reset is the
1084          * quickest way to bring the device back to an operational state..
1085          */
1086         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1087                 tg3_bmcr_reset(tp);
1088
1089         i = mdiobus_register(tp->mdio_bus);
1090         if (i) {
1091                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1092                         tp->dev->name, i);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return i;
1095         }
1096
1097         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1098
1099         if (!phydev || !phydev->drv) {
1100                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101                 mdiobus_unregister(tp->mdio_bus);
1102                 mdiobus_free(tp->mdio_bus);
1103                 return -ENODEV;
1104         }
1105
1106         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1107         case TG3_PHY_ID_BCM57780:
1108                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1109                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1110                 break;
1111         case TG3_PHY_ID_BCM50610:
1112         case TG3_PHY_ID_BCM50610M:
1113                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1114                                      PHY_BRCM_RX_REFCLK_UNUSED |
1115                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1116                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1117                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1123                 /* fallthru */
1124         case TG3_PHY_ID_RTL8211C:
1125                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1126                 break;
1127         case TG3_PHY_ID_RTL8201E:
1128         case TG3_PHY_ID_BCMAC131:
1129                 phydev->interface = PHY_INTERFACE_MODE_MII;
1130                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1131                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1132                 break;
1133         }
1134
1135         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1136
1137         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138                 tg3_mdio_config_5785(tp);
1139
1140         return 0;
1141 }
1142
1143 static void tg3_mdio_fini(struct tg3 *tp)
1144 {
1145         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1147                 mdiobus_unregister(tp->mdio_bus);
1148                 mdiobus_free(tp->mdio_bus);
1149         }
1150 }
1151
1152 /* tp->lock is held. */
1153 static inline void tg3_generate_fw_event(struct tg3 *tp)
1154 {
1155         u32 val;
1156
1157         val = tr32(GRC_RX_CPU_EVENT);
1158         val |= GRC_RX_CPU_DRIVER_EVENT;
1159         tw32_f(GRC_RX_CPU_EVENT, val);
1160
1161         tp->last_event_jiffies = jiffies;
1162 }
1163
1164 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1165
1166 /* tp->lock is held. */
1167 static void tg3_wait_for_event_ack(struct tg3 *tp)
1168 {
1169         int i;
1170         unsigned int delay_cnt;
1171         long time_remain;
1172
1173         /* If enough time has passed, no wait is necessary. */
1174         time_remain = (long)(tp->last_event_jiffies + 1 +
1175                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1176                       (long)jiffies;
1177         if (time_remain < 0)
1178                 return;
1179
1180         /* Check if we can shorten the wait time. */
1181         delay_cnt = jiffies_to_usecs(time_remain);
1182         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184         delay_cnt = (delay_cnt >> 3) + 1;
1185
1186         for (i = 0; i < delay_cnt; i++) {
1187                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1188                         break;
1189                 udelay(8);
1190         }
1191 }
1192
1193 /* tp->lock is held. */
1194 static void tg3_ump_link_report(struct tg3 *tp)
1195 {
1196         u32 reg;
1197         u32 val;
1198
1199         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1201                 return;
1202
1203         tg3_wait_for_event_ack(tp);
1204
1205         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1206
1207         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1208
1209         val = 0;
1210         if (!tg3_readphy(tp, MII_BMCR, &reg))
1211                 val = reg << 16;
1212         if (!tg3_readphy(tp, MII_BMSR, &reg))
1213                 val |= (reg & 0xffff);
1214         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1215
1216         val = 0;
1217         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1218                 val = reg << 16;
1219         if (!tg3_readphy(tp, MII_LPA, &reg))
1220                 val |= (reg & 0xffff);
1221         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1222
1223         val = 0;
1224         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1226                         val = reg << 16;
1227                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1228                         val |= (reg & 0xffff);
1229         }
1230         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1231
1232         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1233                 val = reg << 16;
1234         else
1235                 val = 0;
1236         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1237
1238         tg3_generate_fw_event(tp);
1239 }
1240
1241 static void tg3_link_report(struct tg3 *tp)
1242 {
1243         if (!netif_carrier_ok(tp->dev)) {
1244                 if (netif_msg_link(tp))
1245                         printk(KERN_INFO PFX "%s: Link is down.\n",
1246                                tp->dev->name);
1247                 tg3_ump_link_report(tp);
1248         } else if (netif_msg_link(tp)) {
1249                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1250                        tp->dev->name,
1251                        (tp->link_config.active_speed == SPEED_1000 ?
1252                         1000 :
1253                         (tp->link_config.active_speed == SPEED_100 ?
1254                          100 : 10)),
1255                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1256                         "full" : "half"));
1257
1258                 printk(KERN_INFO PFX
1259                        "%s: Flow control is %s for TX and %s for RX.\n",
1260                        tp->dev->name,
1261                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1262                        "on" : "off",
1263                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1264                        "on" : "off");
1265                 tg3_ump_link_report(tp);
1266         }
1267 }
1268
1269 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1270 {
1271         u16 miireg;
1272
1273         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1274                 miireg = ADVERTISE_PAUSE_CAP;
1275         else if (flow_ctrl & FLOW_CTRL_TX)
1276                 miireg = ADVERTISE_PAUSE_ASYM;
1277         else if (flow_ctrl & FLOW_CTRL_RX)
1278                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1279         else
1280                 miireg = 0;
1281
1282         return miireg;
1283 }
1284
1285 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1286 {
1287         u16 miireg;
1288
1289         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1290                 miireg = ADVERTISE_1000XPAUSE;
1291         else if (flow_ctrl & FLOW_CTRL_TX)
1292                 miireg = ADVERTISE_1000XPSE_ASYM;
1293         else if (flow_ctrl & FLOW_CTRL_RX)
1294                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1295         else
1296                 miireg = 0;
1297
1298         return miireg;
1299 }
1300
1301 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1302 {
1303         u8 cap = 0;
1304
1305         if (lcladv & ADVERTISE_1000XPAUSE) {
1306                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307                         if (rmtadv & LPA_1000XPAUSE)
1308                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1309                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1310                                 cap = FLOW_CTRL_RX;
1311                 } else {
1312                         if (rmtadv & LPA_1000XPAUSE)
1313                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1314                 }
1315         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1317                         cap = FLOW_CTRL_TX;
1318         }
1319
1320         return cap;
1321 }
1322
1323 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1324 {
1325         u8 autoneg;
1326         u8 flowctrl = 0;
1327         u32 old_rx_mode = tp->rx_mode;
1328         u32 old_tx_mode = tp->tx_mode;
1329
1330         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1331                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1332         else
1333                 autoneg = tp->link_config.autoneg;
1334
1335         if (autoneg == AUTONEG_ENABLE &&
1336             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1338                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1339                 else
1340                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1341         } else
1342                 flowctrl = tp->link_config.flowctrl;
1343
1344         tp->link_config.active_flowctrl = flowctrl;
1345
1346         if (flowctrl & FLOW_CTRL_RX)
1347                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1348         else
1349                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1350
1351         if (old_rx_mode != tp->rx_mode)
1352                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1353
1354         if (flowctrl & FLOW_CTRL_TX)
1355                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1356         else
1357                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1358
1359         if (old_tx_mode != tp->tx_mode)
1360                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1361 }
1362
1363 static void tg3_adjust_link(struct net_device *dev)
1364 {
1365         u8 oldflowctrl, linkmesg = 0;
1366         u32 mac_mode, lcl_adv, rmt_adv;
1367         struct tg3 *tp = netdev_priv(dev);
1368         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1369
1370         spin_lock_bh(&tp->lock);
1371
1372         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373                                     MAC_MODE_HALF_DUPLEX);
1374
1375         oldflowctrl = tp->link_config.active_flowctrl;
1376
1377         if (phydev->link) {
1378                 lcl_adv = 0;
1379                 rmt_adv = 0;
1380
1381                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1383                 else if (phydev->speed == SPEED_1000 ||
1384                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1385                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1386                 else
1387                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1388
1389                 if (phydev->duplex == DUPLEX_HALF)
1390                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1391                 else {
1392                         lcl_adv = tg3_advert_flowctrl_1000T(
1393                                   tp->link_config.flowctrl);
1394
1395                         if (phydev->pause)
1396                                 rmt_adv = LPA_PAUSE_CAP;
1397                         if (phydev->asym_pause)
1398                                 rmt_adv |= LPA_PAUSE_ASYM;
1399                 }
1400
1401                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1402         } else
1403                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1404
1405         if (mac_mode != tp->mac_mode) {
1406                 tp->mac_mode = mac_mode;
1407                 tw32_f(MAC_MODE, tp->mac_mode);
1408                 udelay(40);
1409         }
1410
1411         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412                 if (phydev->speed == SPEED_10)
1413                         tw32(MAC_MI_STAT,
1414                              MAC_MI_STAT_10MBPS_MODE |
1415                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1416                 else
1417                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1418         }
1419
1420         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421                 tw32(MAC_TX_LENGTHS,
1422                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423                       (6 << TX_LENGTHS_IPG_SHIFT) |
1424                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1425         else
1426                 tw32(MAC_TX_LENGTHS,
1427                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428                       (6 << TX_LENGTHS_IPG_SHIFT) |
1429                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430
1431         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433             phydev->speed != tp->link_config.active_speed ||
1434             phydev->duplex != tp->link_config.active_duplex ||
1435             oldflowctrl != tp->link_config.active_flowctrl)
1436             linkmesg = 1;
1437
1438         tp->link_config.active_speed = phydev->speed;
1439         tp->link_config.active_duplex = phydev->duplex;
1440
1441         spin_unlock_bh(&tp->lock);
1442
1443         if (linkmesg)
1444                 tg3_link_report(tp);
1445 }
1446
1447 static int tg3_phy_init(struct tg3 *tp)
1448 {
1449         struct phy_device *phydev;
1450
1451         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1452                 return 0;
1453
1454         /* Bring the PHY back to a known state. */
1455         tg3_bmcr_reset(tp);
1456
1457         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1458
1459         /* Attach the MAC to the PHY. */
1460         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1461                              phydev->dev_flags, phydev->interface);
1462         if (IS_ERR(phydev)) {
1463                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464                 return PTR_ERR(phydev);
1465         }
1466
1467         /* Mask with MAC supported features. */
1468         switch (phydev->interface) {
1469         case PHY_INTERFACE_MODE_GMII:
1470         case PHY_INTERFACE_MODE_RGMII:
1471                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472                         phydev->supported &= (PHY_GBIT_FEATURES |
1473                                               SUPPORTED_Pause |
1474                                               SUPPORTED_Asym_Pause);
1475                         break;
1476                 }
1477                 /* fallthru */
1478         case PHY_INTERFACE_MODE_MII:
1479                 phydev->supported &= (PHY_BASIC_FEATURES |
1480                                       SUPPORTED_Pause |
1481                                       SUPPORTED_Asym_Pause);
1482                 break;
1483         default:
1484                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1485                 return -EINVAL;
1486         }
1487
1488         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1489
1490         phydev->advertising = phydev->supported;
1491
1492         return 0;
1493 }
1494
1495 static void tg3_phy_start(struct tg3 *tp)
1496 {
1497         struct phy_device *phydev;
1498
1499         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500                 return;
1501
1502         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1503
1504         if (tp->link_config.phy_is_low_power) {
1505                 tp->link_config.phy_is_low_power = 0;
1506                 phydev->speed = tp->link_config.orig_speed;
1507                 phydev->duplex = tp->link_config.orig_duplex;
1508                 phydev->autoneg = tp->link_config.orig_autoneg;
1509                 phydev->advertising = tp->link_config.orig_advertising;
1510         }
1511
1512         phy_start(phydev);
1513
1514         phy_start_aneg(phydev);
1515 }
1516
1517 static void tg3_phy_stop(struct tg3 *tp)
1518 {
1519         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1520                 return;
1521
1522         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1523 }
1524
1525 static void tg3_phy_fini(struct tg3 *tp)
1526 {
1527         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1528                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1530         }
1531 }
1532
1533 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1534 {
1535         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1537 }
1538
1539 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1540 {
1541         u32 phytest;
1542
1543         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1544                 u32 phy;
1545
1546                 tg3_writephy(tp, MII_TG3_FET_TEST,
1547                              phytest | MII_TG3_FET_SHADOW_EN);
1548                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1549                         if (enable)
1550                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1551                         else
1552                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1554                 }
1555                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1556         }
1557 }
1558
1559 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1560 {
1561         u32 reg;
1562
1563         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1564                 return;
1565
1566         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1567                 tg3_phy_fet_toggle_apd(tp, enable);
1568                 return;
1569         }
1570
1571         reg = MII_TG3_MISC_SHDW_WREN |
1572               MII_TG3_MISC_SHDW_SCR5_SEL |
1573               MII_TG3_MISC_SHDW_SCR5_LPED |
1574               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1575               MII_TG3_MISC_SHDW_SCR5_SDTL |
1576               MII_TG3_MISC_SHDW_SCR5_C125OE;
1577         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1578                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1579
1580         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581
1582
1583         reg = MII_TG3_MISC_SHDW_WREN |
1584               MII_TG3_MISC_SHDW_APD_SEL |
1585               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1586         if (enable)
1587                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1588
1589         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1590 }
1591
1592 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1593 {
1594         u32 phy;
1595
1596         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1597             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1598                 return;
1599
1600         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1601                 u32 ephy;
1602
1603                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1604                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1605
1606                         tg3_writephy(tp, MII_TG3_FET_TEST,
1607                                      ephy | MII_TG3_FET_SHADOW_EN);
1608                         if (!tg3_readphy(tp, reg, &phy)) {
1609                                 if (enable)
1610                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1611                                 else
1612                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1613                                 tg3_writephy(tp, reg, phy);
1614                         }
1615                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1616                 }
1617         } else {
1618                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1619                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1620                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1621                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1622                         if (enable)
1623                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1624                         else
1625                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1627                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1628                 }
1629         }
1630 }
1631
1632 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1633 {
1634         u32 val;
1635
1636         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1637                 return;
1638
1639         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1640             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1641                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1642                              (val | (1 << 15) | (1 << 4)));
1643 }
1644
1645 static void tg3_phy_apply_otp(struct tg3 *tp)
1646 {
1647         u32 otp, phy;
1648
1649         if (!tp->phy_otp)
1650                 return;
1651
1652         otp = tp->phy_otp;
1653
1654         /* Enable SM_DSP clock and tx 6dB coding. */
1655         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1656               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1657               MII_TG3_AUXCTL_ACTL_TX_6DB;
1658         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1659
1660         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1661         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1662         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1663
1664         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1665               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1666         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1667
1668         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1669         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1670         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1671
1672         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1673         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1674
1675         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1676         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1677
1678         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1679               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1680         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1681
1682         /* Turn off SM_DSP clock. */
1683         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1684               MII_TG3_AUXCTL_ACTL_TX_6DB;
1685         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1686 }
1687
1688 static int tg3_wait_macro_done(struct tg3 *tp)
1689 {
1690         int limit = 100;
1691
1692         while (limit--) {
1693                 u32 tmp32;
1694
1695                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1696                         if ((tmp32 & 0x1000) == 0)
1697                                 break;
1698                 }
1699         }
1700         if (limit < 0)
1701                 return -EBUSY;
1702
1703         return 0;
1704 }
1705
1706 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1707 {
1708         static const u32 test_pat[4][6] = {
1709         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1710         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1711         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1712         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1713         };
1714         int chan;
1715
1716         for (chan = 0; chan < 4; chan++) {
1717                 int i;
1718
1719                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720                              (chan * 0x2000) | 0x0200);
1721                 tg3_writephy(tp, 0x16, 0x0002);
1722
1723                 for (i = 0; i < 6; i++)
1724                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1725                                      test_pat[chan][i]);
1726
1727                 tg3_writephy(tp, 0x16, 0x0202);
1728                 if (tg3_wait_macro_done(tp)) {
1729                         *resetp = 1;
1730                         return -EBUSY;
1731                 }
1732
1733                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1734                              (chan * 0x2000) | 0x0200);
1735                 tg3_writephy(tp, 0x16, 0x0082);
1736                 if (tg3_wait_macro_done(tp)) {
1737                         *resetp = 1;
1738                         return -EBUSY;
1739                 }
1740
1741                 tg3_writephy(tp, 0x16, 0x0802);
1742                 if (tg3_wait_macro_done(tp)) {
1743                         *resetp = 1;
1744                         return -EBUSY;
1745                 }
1746
1747                 for (i = 0; i < 6; i += 2) {
1748                         u32 low, high;
1749
1750                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1751                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1752                             tg3_wait_macro_done(tp)) {
1753                                 *resetp = 1;
1754                                 return -EBUSY;
1755                         }
1756                         low &= 0x7fff;
1757                         high &= 0x000f;
1758                         if (low != test_pat[chan][i] ||
1759                             high != test_pat[chan][i+1]) {
1760                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1761                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1762                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1763
1764                                 return -EBUSY;
1765                         }
1766                 }
1767         }
1768
1769         return 0;
1770 }
1771
1772 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1773 {
1774         int chan;
1775
1776         for (chan = 0; chan < 4; chan++) {
1777                 int i;
1778
1779                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1780                              (chan * 0x2000) | 0x0200);
1781                 tg3_writephy(tp, 0x16, 0x0002);
1782                 for (i = 0; i < 6; i++)
1783                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1784                 tg3_writephy(tp, 0x16, 0x0202);
1785                 if (tg3_wait_macro_done(tp))
1786                         return -EBUSY;
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1793 {
1794         u32 reg32, phy9_orig;
1795         int retries, do_phy_reset, err;
1796
1797         retries = 10;
1798         do_phy_reset = 1;
1799         do {
1800                 if (do_phy_reset) {
1801                         err = tg3_bmcr_reset(tp);
1802                         if (err)
1803                                 return err;
1804                         do_phy_reset = 0;
1805                 }
1806
1807                 /* Disable transmitter and interrupt.  */
1808                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1809                         continue;
1810
1811                 reg32 |= 0x3000;
1812                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1813
1814                 /* Set full-duplex, 1000 mbps.  */
1815                 tg3_writephy(tp, MII_BMCR,
1816                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1817
1818                 /* Set to master mode.  */
1819                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1820                         continue;
1821
1822                 tg3_writephy(tp, MII_TG3_CTRL,
1823                              (MII_TG3_CTRL_AS_MASTER |
1824                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1825
1826                 /* Enable SM_DSP_CLOCK and 6dB.  */
1827                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1828
1829                 /* Block the PHY control access.  */
1830                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1831                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1832
1833                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1834                 if (!err)
1835                         break;
1836         } while (--retries);
1837
1838         err = tg3_phy_reset_chanpat(tp);
1839         if (err)
1840                 return err;
1841
1842         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1843         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1844
1845         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1846         tg3_writephy(tp, 0x16, 0x0000);
1847
1848         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1849             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1850                 /* Set Extended packet length bit for jumbo frames */
1851                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1852         }
1853         else {
1854                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1855         }
1856
1857         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1858
1859         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1860                 reg32 &= ~0x3000;
1861                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1862         } else if (!err)
1863                 err = -EBUSY;
1864
1865         return err;
1866 }
1867
1868 /* This will reset the tigon3 PHY if there is no valid
1869  * link unless the FORCE argument is non-zero.
1870  */
1871 static int tg3_phy_reset(struct tg3 *tp)
1872 {
1873         u32 cpmuctrl;
1874         u32 phy_status;
1875         int err;
1876
1877         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1878                 u32 val;
1879
1880                 val = tr32(GRC_MISC_CFG);
1881                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1882                 udelay(40);
1883         }
1884         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1885         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1886         if (err != 0)
1887                 return -EBUSY;
1888
1889         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1890                 netif_carrier_off(tp->dev);
1891                 tg3_link_report(tp);
1892         }
1893
1894         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1895             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1896             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1897                 err = tg3_phy_reset_5703_4_5(tp);
1898                 if (err)
1899                         return err;
1900                 goto out;
1901         }
1902
1903         cpmuctrl = 0;
1904         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1905             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1906                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1907                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1908                         tw32(TG3_CPMU_CTRL,
1909                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1910         }
1911
1912         err = tg3_bmcr_reset(tp);
1913         if (err)
1914                 return err;
1915
1916         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1917                 u32 phy;
1918
1919                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1920                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1921
1922                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1923         }
1924
1925         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1926             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1927                 u32 val;
1928
1929                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1930                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1931                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1932                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1933                         udelay(40);
1934                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1935                 }
1936         }
1937
1938         tg3_phy_apply_otp(tp);
1939
1940         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1941                 tg3_phy_toggle_apd(tp, true);
1942         else
1943                 tg3_phy_toggle_apd(tp, false);
1944
1945 out:
1946         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1947                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1949                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1950                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1951                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1952                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1953         }
1954         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1955                 tg3_writephy(tp, 0x1c, 0x8d68);
1956                 tg3_writephy(tp, 0x1c, 0x8d68);
1957         }
1958         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1959                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1961                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1962                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1963                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1964                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1965                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1966                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1967         }
1968         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1970                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1971                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1972                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1973                         tg3_writephy(tp, MII_TG3_TEST1,
1974                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1975                 } else
1976                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1977                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1978         }
1979         /* Set Extended packet length bit (bit 14) on all chips that */
1980         /* support jumbo frames */
1981         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1982                 /* Cannot do read-modify-write on 5401 */
1983                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1984         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1985                 u32 phy_reg;
1986
1987                 /* Set bit 14 with read-modify-write to preserve other bits */
1988                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1990                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1991         }
1992
1993         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994          * jumbo frames transmission.
1995          */
1996         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1997                 u32 phy_reg;
1998
1999                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2000                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
2001                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2002         }
2003
2004         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2005                 /* adjust output voltage */
2006                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2007         }
2008
2009         tg3_phy_toggle_automdix(tp, 1);
2010         tg3_phy_set_wirespeed(tp);
2011         return 0;
2012 }
2013
2014 static void tg3_frob_aux_power(struct tg3 *tp)
2015 {
2016         struct tg3 *tp_peer = tp;
2017
2018         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2019                 return;
2020
2021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2022             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2023             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2024                 struct net_device *dev_peer;
2025
2026                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2027                 /* remove_one() may have been run on the peer. */
2028                 if (!dev_peer)
2029                         tp_peer = tp;
2030                 else
2031                         tp_peer = netdev_priv(dev_peer);
2032         }
2033
2034         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2035             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2036             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2037             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2038                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2039                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2040                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041                                     (GRC_LCLCTRL_GPIO_OE0 |
2042                                      GRC_LCLCTRL_GPIO_OE1 |
2043                                      GRC_LCLCTRL_GPIO_OE2 |
2044                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2045                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2046                                     100);
2047                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2048                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2049                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2050                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2051                                              GRC_LCLCTRL_GPIO_OE1 |
2052                                              GRC_LCLCTRL_GPIO_OE2 |
2053                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2054                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2055                                              tp->grc_local_ctrl;
2056                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2057
2058                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2059                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2060
2061                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2062                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2063                 } else {
2064                         u32 no_gpio2;
2065                         u32 grc_local_ctrl = 0;
2066
2067                         if (tp_peer != tp &&
2068                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2069                                 return;
2070
2071                         /* Workaround to prevent overdrawing Amps. */
2072                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2073                             ASIC_REV_5714) {
2074                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2075                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2076                                             grc_local_ctrl, 100);
2077                         }
2078
2079                         /* On 5753 and variants, GPIO2 cannot be used. */
2080                         no_gpio2 = tp->nic_sram_data_cfg &
2081                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2082
2083                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2084                                          GRC_LCLCTRL_GPIO_OE1 |
2085                                          GRC_LCLCTRL_GPIO_OE2 |
2086                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2087                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2088                         if (no_gpio2) {
2089                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2090                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2091                         }
2092                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2093                                                     grc_local_ctrl, 100);
2094
2095                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2096
2097                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098                                                     grc_local_ctrl, 100);
2099
2100                         if (!no_gpio2) {
2101                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2102                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2103                                             grc_local_ctrl, 100);
2104                         }
2105                 }
2106         } else {
2107                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2108                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2109                         if (tp_peer != tp &&
2110                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2111                                 return;
2112
2113                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2114                                     (GRC_LCLCTRL_GPIO_OE1 |
2115                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2116
2117                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118                                     GRC_LCLCTRL_GPIO_OE1, 100);
2119
2120                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121                                     (GRC_LCLCTRL_GPIO_OE1 |
2122                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2123                 }
2124         }
2125 }
2126
2127 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2128 {
2129         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2130                 return 1;
2131         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2132                 if (speed != SPEED_10)
2133                         return 1;
2134         } else if (speed == SPEED_10)
2135                 return 1;
2136
2137         return 0;
2138 }
2139
2140 static int tg3_setup_phy(struct tg3 *, int);
2141
2142 #define RESET_KIND_SHUTDOWN     0
2143 #define RESET_KIND_INIT         1
2144 #define RESET_KIND_SUSPEND      2
2145
2146 static void tg3_write_sig_post_reset(struct tg3 *, int);
2147 static int tg3_halt_cpu(struct tg3 *, u32);
2148
2149 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2150 {
2151         u32 val;
2152
2153         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2154                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2155                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2156                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2157
2158                         sg_dig_ctrl |=
2159                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2160                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2161                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2162                 }
2163                 return;
2164         }
2165
2166         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2167                 tg3_bmcr_reset(tp);
2168                 val = tr32(GRC_MISC_CFG);
2169                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2170                 udelay(40);
2171                 return;
2172         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2173                 u32 phytest;
2174                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2175                         u32 phy;
2176
2177                         tg3_writephy(tp, MII_ADVERTISE, 0);
2178                         tg3_writephy(tp, MII_BMCR,
2179                                      BMCR_ANENABLE | BMCR_ANRESTART);
2180
2181                         tg3_writephy(tp, MII_TG3_FET_TEST,
2182                                      phytest | MII_TG3_FET_SHADOW_EN);
2183                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2184                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2185                                 tg3_writephy(tp,
2186                                              MII_TG3_FET_SHDW_AUXMODE4,
2187                                              phy);
2188                         }
2189                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2190                 }
2191                 return;
2192         } else if (do_low_power) {
2193                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2194                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2195
2196                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2197                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2198                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2199                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2200                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2201         }
2202
2203         /* The PHY should not be powered down on some chips because
2204          * of bugs.
2205          */
2206         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2207             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2208             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2209              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2210                 return;
2211
2212         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2213             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2214                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2215                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2216                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2217                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2218         }
2219
2220         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2221 }
2222
2223 /* tp->lock is held. */
2224 static int tg3_nvram_lock(struct tg3 *tp)
2225 {
2226         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2227                 int i;
2228
2229                 if (tp->nvram_lock_cnt == 0) {
2230                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2231                         for (i = 0; i < 8000; i++) {
2232                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2233                                         break;
2234                                 udelay(20);
2235                         }
2236                         if (i == 8000) {
2237                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2238                                 return -ENODEV;
2239                         }
2240                 }
2241                 tp->nvram_lock_cnt++;
2242         }
2243         return 0;
2244 }
2245
2246 /* tp->lock is held. */
2247 static void tg3_nvram_unlock(struct tg3 *tp)
2248 {
2249         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2250                 if (tp->nvram_lock_cnt > 0)
2251                         tp->nvram_lock_cnt--;
2252                 if (tp->nvram_lock_cnt == 0)
2253                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2254         }
2255 }
2256
2257 /* tp->lock is held. */
2258 static void tg3_enable_nvram_access(struct tg3 *tp)
2259 {
2260         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2261             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2262                 u32 nvaccess = tr32(NVRAM_ACCESS);
2263
2264                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2265         }
2266 }
2267
2268 /* tp->lock is held. */
2269 static void tg3_disable_nvram_access(struct tg3 *tp)
2270 {
2271         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2272             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2273                 u32 nvaccess = tr32(NVRAM_ACCESS);
2274
2275                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2276         }
2277 }
2278
2279 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2280                                         u32 offset, u32 *val)
2281 {
2282         u32 tmp;
2283         int i;
2284
2285         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2286                 return -EINVAL;
2287
2288         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2289                                         EEPROM_ADDR_DEVID_MASK |
2290                                         EEPROM_ADDR_READ);
2291         tw32(GRC_EEPROM_ADDR,
2292              tmp |
2293              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2294              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2295               EEPROM_ADDR_ADDR_MASK) |
2296              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2297
2298         for (i = 0; i < 1000; i++) {
2299                 tmp = tr32(GRC_EEPROM_ADDR);
2300
2301                 if (tmp & EEPROM_ADDR_COMPLETE)
2302                         break;
2303                 msleep(1);
2304         }
2305         if (!(tmp & EEPROM_ADDR_COMPLETE))
2306                 return -EBUSY;
2307
2308         tmp = tr32(GRC_EEPROM_DATA);
2309
2310         /*
2311          * The data will always be opposite the native endian
2312          * format.  Perform a blind byteswap to compensate.
2313          */
2314         *val = swab32(tmp);
2315
2316         return 0;
2317 }
2318
2319 #define NVRAM_CMD_TIMEOUT 10000
2320
2321 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2322 {
2323         int i;
2324
2325         tw32(NVRAM_CMD, nvram_cmd);
2326         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2327                 udelay(10);
2328                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2329                         udelay(10);
2330                         break;
2331                 }
2332         }
2333
2334         if (i == NVRAM_CMD_TIMEOUT)
2335                 return -EBUSY;
2336
2337         return 0;
2338 }
2339
2340 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2341 {
2342         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2343             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2344             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2345            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2346             (tp->nvram_jedecnum == JEDEC_ATMEL))
2347
2348                 addr = ((addr / tp->nvram_pagesize) <<
2349                         ATMEL_AT45DB0X1B_PAGE_POS) +
2350                        (addr % tp->nvram_pagesize);
2351
2352         return addr;
2353 }
2354
2355 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2356 {
2357         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2358             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2359             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2360            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2361             (tp->nvram_jedecnum == JEDEC_ATMEL))
2362
2363                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2364                         tp->nvram_pagesize) +
2365                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2366
2367         return addr;
2368 }
2369
2370 /* NOTE: Data read in from NVRAM is byteswapped according to
2371  * the byteswapping settings for all other register accesses.
2372  * tg3 devices are BE devices, so on a BE machine, the data
2373  * returned will be exactly as it is seen in NVRAM.  On a LE
2374  * machine, the 32-bit value will be byteswapped.
2375  */
2376 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2377 {
2378         int ret;
2379
2380         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2381                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2382
2383         offset = tg3_nvram_phys_addr(tp, offset);
2384
2385         if (offset > NVRAM_ADDR_MSK)
2386                 return -EINVAL;
2387
2388         ret = tg3_nvram_lock(tp);
2389         if (ret)
2390                 return ret;
2391
2392         tg3_enable_nvram_access(tp);
2393
2394         tw32(NVRAM_ADDR, offset);
2395         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2396                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2397
2398         if (ret == 0)
2399                 *val = tr32(NVRAM_RDDATA);
2400
2401         tg3_disable_nvram_access(tp);
2402
2403         tg3_nvram_unlock(tp);
2404
2405         return ret;
2406 }
2407
2408 /* Ensures NVRAM data is in bytestream format. */
2409 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2410 {
2411         u32 v;
2412         int res = tg3_nvram_read(tp, offset, &v);
2413         if (!res)
2414                 *val = cpu_to_be32(v);
2415         return res;
2416 }
2417
2418 /* tp->lock is held. */
2419 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2420 {
2421         u32 addr_high, addr_low;
2422         int i;
2423
2424         addr_high = ((tp->dev->dev_addr[0] << 8) |
2425                      tp->dev->dev_addr[1]);
2426         addr_low = ((tp->dev->dev_addr[2] << 24) |
2427                     (tp->dev->dev_addr[3] << 16) |
2428                     (tp->dev->dev_addr[4] <<  8) |
2429                     (tp->dev->dev_addr[5] <<  0));
2430         for (i = 0; i < 4; i++) {
2431                 if (i == 1 && skip_mac_1)
2432                         continue;
2433                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2434                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2435         }
2436
2437         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2438             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2439                 for (i = 0; i < 12; i++) {
2440                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2441                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2442                 }
2443         }
2444
2445         addr_high = (tp->dev->dev_addr[0] +
2446                      tp->dev->dev_addr[1] +
2447                      tp->dev->dev_addr[2] +
2448                      tp->dev->dev_addr[3] +
2449                      tp->dev->dev_addr[4] +
2450                      tp->dev->dev_addr[5]) &
2451                 TX_BACKOFF_SEED_MASK;
2452         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2453 }
2454
2455 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2456 {
2457         u32 misc_host_ctrl;
2458         bool device_should_wake, do_low_power;
2459
2460         /* Make sure register accesses (indirect or otherwise)
2461          * will function correctly.
2462          */
2463         pci_write_config_dword(tp->pdev,
2464                                TG3PCI_MISC_HOST_CTRL,
2465                                tp->misc_host_ctrl);
2466
2467         switch (state) {
2468         case PCI_D0:
2469                 pci_enable_wake(tp->pdev, state, false);
2470                 pci_set_power_state(tp->pdev, PCI_D0);
2471
2472                 /* Switch out of Vaux if it is a NIC */
2473                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2474                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2475
2476                 return 0;
2477
2478         case PCI_D1:
2479         case PCI_D2:
2480         case PCI_D3hot:
2481                 break;
2482
2483         default:
2484                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2485                         tp->dev->name, state);
2486                 return -EINVAL;
2487         }
2488
2489         /* Restore the CLKREQ setting. */
2490         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2491                 u16 lnkctl;
2492
2493                 pci_read_config_word(tp->pdev,
2494                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2495                                      &lnkctl);
2496                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2497                 pci_write_config_word(tp->pdev,
2498                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2499                                       lnkctl);
2500         }
2501
2502         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2503         tw32(TG3PCI_MISC_HOST_CTRL,
2504              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2505
2506         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2507                              device_may_wakeup(&tp->pdev->dev) &&
2508                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2509
2510         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2511                 do_low_power = false;
2512                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2513                     !tp->link_config.phy_is_low_power) {
2514                         struct phy_device *phydev;
2515                         u32 phyid, advertising;
2516
2517                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2518
2519                         tp->link_config.phy_is_low_power = 1;
2520
2521                         tp->link_config.orig_speed = phydev->speed;
2522                         tp->link_config.orig_duplex = phydev->duplex;
2523                         tp->link_config.orig_autoneg = phydev->autoneg;
2524                         tp->link_config.orig_advertising = phydev->advertising;
2525
2526                         advertising = ADVERTISED_TP |
2527                                       ADVERTISED_Pause |
2528                                       ADVERTISED_Autoneg |
2529                                       ADVERTISED_10baseT_Half;
2530
2531                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2532                             device_should_wake) {
2533                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2534                                         advertising |=
2535                                                 ADVERTISED_100baseT_Half |
2536                                                 ADVERTISED_100baseT_Full |
2537                                                 ADVERTISED_10baseT_Full;
2538                                 else
2539                                         advertising |= ADVERTISED_10baseT_Full;
2540                         }
2541
2542                         phydev->advertising = advertising;
2543
2544                         phy_start_aneg(phydev);
2545
2546                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2547                         if (phyid != TG3_PHY_ID_BCMAC131) {
2548                                 phyid &= TG3_PHY_OUI_MASK;
2549                                 if (phyid == TG3_PHY_OUI_1 ||
2550                                     phyid == TG3_PHY_OUI_2 ||
2551                                     phyid == TG3_PHY_OUI_3)
2552                                         do_low_power = true;
2553                         }
2554                 }
2555         } else {
2556                 do_low_power = true;
2557
2558                 if (tp->link_config.phy_is_low_power == 0) {
2559                         tp->link_config.phy_is_low_power = 1;
2560                         tp->link_config.orig_speed = tp->link_config.speed;
2561                         tp->link_config.orig_duplex = tp->link_config.duplex;
2562                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2563                 }
2564
2565                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2566                         tp->link_config.speed = SPEED_10;
2567                         tp->link_config.duplex = DUPLEX_HALF;
2568                         tp->link_config.autoneg = AUTONEG_ENABLE;
2569                         tg3_setup_phy(tp, 0);
2570                 }
2571         }
2572
2573         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2574                 u32 val;
2575
2576                 val = tr32(GRC_VCPU_EXT_CTRL);
2577                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2578         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2579                 int i;
2580                 u32 val;
2581
2582                 for (i = 0; i < 200; i++) {
2583                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2584                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2585                                 break;
2586                         msleep(1);
2587                 }
2588         }
2589         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2590                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2591                                                      WOL_DRV_STATE_SHUTDOWN |
2592                                                      WOL_DRV_WOL |
2593                                                      WOL_SET_MAGIC_PKT);
2594
2595         if (device_should_wake) {
2596                 u32 mac_mode;
2597
2598                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2599                         if (do_low_power) {
2600                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2601                                 udelay(40);
2602                         }
2603
2604                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2605                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2606                         else
2607                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2608
2609                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2610                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2611                             ASIC_REV_5700) {
2612                                 u32 speed = (tp->tg3_flags &
2613                                              TG3_FLAG_WOL_SPEED_100MB) ?
2614                                              SPEED_100 : SPEED_10;
2615                                 if (tg3_5700_link_polarity(tp, speed))
2616                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2617                                 else
2618                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2619                         }
2620                 } else {
2621                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2622                 }
2623
2624                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2625                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2626
2627                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2628                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2629                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2630                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2631                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2632                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2633
2634                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2635                         mac_mode |= tp->mac_mode &
2636                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2637                         if (mac_mode & MAC_MODE_APE_TX_EN)
2638                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2639                 }
2640
2641                 tw32_f(MAC_MODE, mac_mode);
2642                 udelay(100);
2643
2644                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2645                 udelay(10);
2646         }
2647
2648         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2649             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2650              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2651                 u32 base_val;
2652
2653                 base_val = tp->pci_clock_ctrl;
2654                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2655                              CLOCK_CTRL_TXCLK_DISABLE);
2656
2657                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2658                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2659         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2660                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2661                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2662                 /* do nothing */
2663         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2664                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2665                 u32 newbits1, newbits2;
2666
2667                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2668                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2669                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2670                                     CLOCK_CTRL_TXCLK_DISABLE |
2671                                     CLOCK_CTRL_ALTCLK);
2672                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2673                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2674                         newbits1 = CLOCK_CTRL_625_CORE;
2675                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2676                 } else {
2677                         newbits1 = CLOCK_CTRL_ALTCLK;
2678                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2679                 }
2680
2681                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2682                             40);
2683
2684                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2685                             40);
2686
2687                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2688                         u32 newbits3;
2689
2690                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2691                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2692                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2693                                             CLOCK_CTRL_TXCLK_DISABLE |
2694                                             CLOCK_CTRL_44MHZ_CORE);
2695                         } else {
2696                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2697                         }
2698
2699                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2700                                     tp->pci_clock_ctrl | newbits3, 40);
2701                 }
2702         }
2703
2704         if (!(device_should_wake) &&
2705             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2706                 tg3_power_down_phy(tp, do_low_power);
2707
2708         tg3_frob_aux_power(tp);
2709
2710         /* Workaround for unstable PLL clock */
2711         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2712             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2713                 u32 val = tr32(0x7d00);
2714
2715                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2716                 tw32(0x7d00, val);
2717                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2718                         int err;
2719
2720                         err = tg3_nvram_lock(tp);
2721                         tg3_halt_cpu(tp, RX_CPU_BASE);
2722                         if (!err)
2723                                 tg3_nvram_unlock(tp);
2724                 }
2725         }
2726
2727         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2728
2729         if (device_should_wake)
2730                 pci_enable_wake(tp->pdev, state, true);
2731
2732         /* Finally, set the new power state. */
2733         pci_set_power_state(tp->pdev, state);
2734
2735         return 0;
2736 }
2737
2738 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2739 {
2740         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2741         case MII_TG3_AUX_STAT_10HALF:
2742                 *speed = SPEED_10;
2743                 *duplex = DUPLEX_HALF;
2744                 break;
2745
2746         case MII_TG3_AUX_STAT_10FULL:
2747                 *speed = SPEED_10;
2748                 *duplex = DUPLEX_FULL;
2749                 break;
2750
2751         case MII_TG3_AUX_STAT_100HALF:
2752                 *speed = SPEED_100;
2753                 *duplex = DUPLEX_HALF;
2754                 break;
2755
2756         case MII_TG3_AUX_STAT_100FULL:
2757                 *speed = SPEED_100;
2758                 *duplex = DUPLEX_FULL;
2759                 break;
2760
2761         case MII_TG3_AUX_STAT_1000HALF:
2762                 *speed = SPEED_1000;
2763                 *duplex = DUPLEX_HALF;
2764                 break;
2765
2766         case MII_TG3_AUX_STAT_1000FULL:
2767                 *speed = SPEED_1000;
2768                 *duplex = DUPLEX_FULL;
2769                 break;
2770
2771         default:
2772                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2773                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2774                                  SPEED_10;
2775                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2776                                   DUPLEX_HALF;
2777                         break;
2778                 }
2779                 *speed = SPEED_INVALID;
2780                 *duplex = DUPLEX_INVALID;
2781                 break;
2782         }
2783 }
2784
2785 static void tg3_phy_copper_begin(struct tg3 *tp)
2786 {
2787         u32 new_adv;
2788         int i;
2789
2790         if (tp->link_config.phy_is_low_power) {
2791                 /* Entering low power mode.  Disable gigabit and
2792                  * 100baseT advertisements.
2793                  */
2794                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2795
2796                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2797                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2798                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2799                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2800
2801                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2802         } else if (tp->link_config.speed == SPEED_INVALID) {
2803                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2804                         tp->link_config.advertising &=
2805                                 ~(ADVERTISED_1000baseT_Half |
2806                                   ADVERTISED_1000baseT_Full);
2807
2808                 new_adv = ADVERTISE_CSMA;
2809                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2810                         new_adv |= ADVERTISE_10HALF;
2811                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2812                         new_adv |= ADVERTISE_10FULL;
2813                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2814                         new_adv |= ADVERTISE_100HALF;
2815                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2816                         new_adv |= ADVERTISE_100FULL;
2817
2818                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2819
2820                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821
2822                 if (tp->link_config.advertising &
2823                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2824                         new_adv = 0;
2825                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2826                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2827                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2828                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2829                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2830                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2831                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2832                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2833                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2834                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2835                 } else {
2836                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2837                 }
2838         } else {
2839                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2840                 new_adv |= ADVERTISE_CSMA;
2841
2842                 /* Asking for a specific link mode. */
2843                 if (tp->link_config.speed == SPEED_1000) {
2844                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2845
2846                         if (tp->link_config.duplex == DUPLEX_FULL)
2847                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2848                         else
2849                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2850                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2851                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2852                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2853                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2854                 } else {
2855                         if (tp->link_config.speed == SPEED_100) {
2856                                 if (tp->link_config.duplex == DUPLEX_FULL)
2857                                         new_adv |= ADVERTISE_100FULL;
2858                                 else
2859                                         new_adv |= ADVERTISE_100HALF;
2860                         } else {
2861                                 if (tp->link_config.duplex == DUPLEX_FULL)
2862                                         new_adv |= ADVERTISE_10FULL;
2863                                 else
2864                                         new_adv |= ADVERTISE_10HALF;
2865                         }
2866                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2867
2868                         new_adv = 0;
2869                 }
2870
2871                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2872         }
2873
2874         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2875             tp->link_config.speed != SPEED_INVALID) {
2876                 u32 bmcr, orig_bmcr;
2877
2878                 tp->link_config.active_speed = tp->link_config.speed;
2879                 tp->link_config.active_duplex = tp->link_config.duplex;
2880
2881                 bmcr = 0;
2882                 switch (tp->link_config.speed) {
2883                 default:
2884                 case SPEED_10:
2885                         break;
2886
2887                 case SPEED_100:
2888                         bmcr |= BMCR_SPEED100;
2889                         break;
2890
2891                 case SPEED_1000:
2892                         bmcr |= TG3_BMCR_SPEED1000;
2893                         break;
2894                 }
2895
2896                 if (tp->link_config.duplex == DUPLEX_FULL)
2897                         bmcr |= BMCR_FULLDPLX;
2898
2899                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2900                     (bmcr != orig_bmcr)) {
2901                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2902                         for (i = 0; i < 1500; i++) {
2903                                 u32 tmp;
2904
2905                                 udelay(10);
2906                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2907                                     tg3_readphy(tp, MII_BMSR, &tmp))
2908                                         continue;
2909                                 if (!(tmp & BMSR_LSTATUS)) {
2910                                         udelay(40);
2911                                         break;
2912                                 }
2913                         }
2914                         tg3_writephy(tp, MII_BMCR, bmcr);
2915                         udelay(40);
2916                 }
2917         } else {
2918                 tg3_writephy(tp, MII_BMCR,
2919                              BMCR_ANENABLE | BMCR_ANRESTART);
2920         }
2921 }
2922
2923 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2924 {
2925         int err;
2926
2927         /* Turn off tap power management. */
2928         /* Set Extended packet length bit */
2929         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2930
2931         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2932         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2933
2934         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2935         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2936
2937         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2938         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2939
2940         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2941         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2942
2943         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2944         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2945
2946         udelay(40);
2947
2948         return err;
2949 }
2950
2951 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2952 {
2953         u32 adv_reg, all_mask = 0;
2954
2955         if (mask & ADVERTISED_10baseT_Half)
2956                 all_mask |= ADVERTISE_10HALF;
2957         if (mask & ADVERTISED_10baseT_Full)
2958                 all_mask |= ADVERTISE_10FULL;
2959         if (mask & ADVERTISED_100baseT_Half)
2960                 all_mask |= ADVERTISE_100HALF;
2961         if (mask & ADVERTISED_100baseT_Full)
2962                 all_mask |= ADVERTISE_100FULL;
2963
2964         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2965                 return 0;
2966
2967         if ((adv_reg & all_mask) != all_mask)
2968                 return 0;
2969         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2970                 u32 tg3_ctrl;
2971
2972                 all_mask = 0;
2973                 if (mask & ADVERTISED_1000baseT_Half)
2974                         all_mask |= ADVERTISE_1000HALF;
2975                 if (mask & ADVERTISED_1000baseT_Full)
2976                         all_mask |= ADVERTISE_1000FULL;
2977
2978                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2979                         return 0;
2980
2981                 if ((tg3_ctrl & all_mask) != all_mask)
2982                         return 0;
2983         }
2984         return 1;
2985 }
2986
2987 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2988 {
2989         u32 curadv, reqadv;
2990
2991         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2992                 return 1;
2993
2994         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2995         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2996
2997         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2998                 if (curadv != reqadv)
2999                         return 0;
3000
3001                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3002                         tg3_readphy(tp, MII_LPA, rmtadv);
3003         } else {
3004                 /* Reprogram the advertisement register, even if it
3005                  * does not affect the current link.  If the link
3006                  * gets renegotiated in the future, we can save an
3007                  * additional renegotiation cycle by advertising
3008                  * it correctly in the first place.
3009                  */
3010                 if (curadv != reqadv) {
3011                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3012                                      ADVERTISE_PAUSE_ASYM);
3013                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3014                 }
3015         }
3016
3017         return 1;
3018 }
3019
3020 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3021 {
3022         int current_link_up;
3023         u32 bmsr, dummy;
3024         u32 lcl_adv, rmt_adv;
3025         u16 current_speed;
3026         u8 current_duplex;
3027         int i, err;
3028
3029         tw32(MAC_EVENT, 0);
3030
3031         tw32_f(MAC_STATUS,
3032              (MAC_STATUS_SYNC_CHANGED |
3033               MAC_STATUS_CFG_CHANGED |
3034               MAC_STATUS_MI_COMPLETION |
3035               MAC_STATUS_LNKSTATE_CHANGED));
3036         udelay(40);
3037
3038         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3039                 tw32_f(MAC_MI_MODE,
3040                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3041                 udelay(80);
3042         }
3043
3044         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3045
3046         /* Some third-party PHYs need to be reset on link going
3047          * down.
3048          */
3049         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3050              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3051              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3052             netif_carrier_ok(tp->dev)) {
3053                 tg3_readphy(tp, MII_BMSR, &bmsr);
3054                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3055                     !(bmsr & BMSR_LSTATUS))
3056                         force_reset = 1;
3057         }
3058         if (force_reset)
3059                 tg3_phy_reset(tp);
3060
3061         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3062                 tg3_readphy(tp, MII_BMSR, &bmsr);
3063                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3064                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3065                         bmsr = 0;
3066
3067                 if (!(bmsr & BMSR_LSTATUS)) {
3068                         err = tg3_init_5401phy_dsp(tp);
3069                         if (err)
3070                                 return err;
3071
3072                         tg3_readphy(tp, MII_BMSR, &bmsr);
3073                         for (i = 0; i < 1000; i++) {
3074                                 udelay(10);
3075                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3076                                     (bmsr & BMSR_LSTATUS)) {
3077                                         udelay(40);
3078                                         break;
3079                                 }
3080                         }
3081
3082                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3083                             !(bmsr & BMSR_LSTATUS) &&
3084                             tp->link_config.active_speed == SPEED_1000) {
3085                                 err = tg3_phy_reset(tp);
3086                                 if (!err)
3087                                         err = tg3_init_5401phy_dsp(tp);
3088                                 if (err)
3089                                         return err;
3090                         }
3091                 }
3092         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3093                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3094                 /* 5701 {A0,B0} CRC bug workaround */
3095                 tg3_writephy(tp, 0x15, 0x0a75);
3096                 tg3_writephy(tp, 0x1c, 0x8c68);
3097                 tg3_writephy(tp, 0x1c, 0x8d68);
3098                 tg3_writephy(tp, 0x1c, 0x8c68);
3099         }
3100
3101         /* Clear pending interrupts... */
3102         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3103         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3104
3105         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3106                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3107         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3108                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3109
3110         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3111             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3112                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3113                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3115                 else
3116                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3117         }
3118
3119         current_link_up = 0;
3120         current_speed = SPEED_INVALID;
3121         current_duplex = DUPLEX_INVALID;
3122
3123         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3124                 u32 val;
3125
3126                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3127                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3128                 if (!(val & (1 << 10))) {
3129                         val |= (1 << 10);
3130                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3131                         goto relink;
3132                 }
3133         }
3134
3135         bmsr = 0;
3136         for (i = 0; i < 100; i++) {
3137                 tg3_readphy(tp, MII_BMSR, &bmsr);
3138                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3139                     (bmsr & BMSR_LSTATUS))
3140                         break;
3141                 udelay(40);
3142         }
3143
3144         if (bmsr & BMSR_LSTATUS) {
3145                 u32 aux_stat, bmcr;
3146
3147                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3148                 for (i = 0; i < 2000; i++) {
3149                         udelay(10);
3150                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3151                             aux_stat)
3152                                 break;
3153                 }
3154
3155                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3156                                              &current_speed,
3157                                              &current_duplex);
3158
3159                 bmcr = 0;
3160                 for (i = 0; i < 200; i++) {
3161                         tg3_readphy(tp, MII_BMCR, &bmcr);
3162                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3163                                 continue;
3164                         if (bmcr && bmcr != 0x7fff)
3165                                 break;
3166                         udelay(10);
3167                 }
3168
3169                 lcl_adv = 0;
3170                 rmt_adv = 0;
3171
3172                 tp->link_config.active_speed = current_speed;
3173                 tp->link_config.active_duplex = current_duplex;
3174
3175                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3176                         if ((bmcr & BMCR_ANENABLE) &&
3177                             tg3_copper_is_advertising_all(tp,
3178                                                 tp->link_config.advertising)) {
3179                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3180                                                                   &rmt_adv))
3181                                         current_link_up = 1;
3182                         }
3183                 } else {
3184                         if (!(bmcr & BMCR_ANENABLE) &&
3185                             tp->link_config.speed == current_speed &&
3186                             tp->link_config.duplex == current_duplex &&
3187                             tp->link_config.flowctrl ==
3188                             tp->link_config.active_flowctrl) {
3189                                 current_link_up = 1;
3190                         }
3191                 }
3192
3193                 if (current_link_up == 1 &&
3194                     tp->link_config.active_duplex == DUPLEX_FULL)
3195                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3196         }
3197
3198 relink:
3199         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3200                 u32 tmp;
3201
3202                 tg3_phy_copper_begin(tp);
3203
3204                 tg3_readphy(tp, MII_BMSR, &tmp);
3205                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3206                     (tmp & BMSR_LSTATUS))
3207                         current_link_up = 1;
3208         }
3209
3210         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3211         if (current_link_up == 1) {
3212                 if (tp->link_config.active_speed == SPEED_100 ||
3213                     tp->link_config.active_speed == SPEED_10)
3214                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3215                 else
3216                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3217         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3218                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3219         else
3220                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3221
3222         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3223         if (tp->link_config.active_duplex == DUPLEX_HALF)
3224                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3225
3226         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3227                 if (current_link_up == 1 &&
3228                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3229                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3230                 else
3231                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3232         }
3233
3234         /* ??? Without this setting Netgear GA302T PHY does not
3235          * ??? send/receive packets...
3236          */
3237         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3238             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3239                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3240                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3241                 udelay(80);
3242         }
3243
3244         tw32_f(MAC_MODE, tp->mac_mode);
3245         udelay(40);
3246
3247         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3248                 /* Polled via timer. */
3249                 tw32_f(MAC_EVENT, 0);
3250         } else {
3251                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3252         }
3253         udelay(40);
3254
3255         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3256             current_link_up == 1 &&
3257             tp->link_config.active_speed == SPEED_1000 &&
3258             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3259              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3260                 udelay(120);
3261                 tw32_f(MAC_STATUS,
3262                      (MAC_STATUS_SYNC_CHANGED |
3263                       MAC_STATUS_CFG_CHANGED));
3264                 udelay(40);
3265                 tg3_write_mem(tp,
3266                               NIC_SRAM_FIRMWARE_MBOX,
3267                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3268         }
3269
3270         /* Prevent send BD corruption. */
3271         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3272                 u16 oldlnkctl, newlnkctl;
3273
3274                 pci_read_config_word(tp->pdev,
3275                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3276                                      &oldlnkctl);
3277                 if (tp->link_config.active_speed == SPEED_100 ||
3278                     tp->link_config.active_speed == SPEED_10)
3279                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3280                 else
3281                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3282                 if (newlnkctl != oldlnkctl)
3283                         pci_write_config_word(tp->pdev,
3284                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3285                                               newlnkctl);
3286         }
3287
3288         if (current_link_up != netif_carrier_ok(tp->dev)) {
3289                 if (current_link_up)
3290                         netif_carrier_on(tp->dev);
3291                 else
3292                         netif_carrier_off(tp->dev);
3293                 tg3_link_report(tp);
3294         }
3295
3296         return 0;
3297 }
3298
3299 struct tg3_fiber_aneginfo {
3300         int state;
3301 #define ANEG_STATE_UNKNOWN              0
3302 #define ANEG_STATE_AN_ENABLE            1
3303 #define ANEG_STATE_RESTART_INIT         2
3304 #define ANEG_STATE_RESTART              3
3305 #define ANEG_STATE_DISABLE_LINK_OK      4
3306 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3307 #define ANEG_STATE_ABILITY_DETECT       6
3308 #define ANEG_STATE_ACK_DETECT_INIT      7
3309 #define ANEG_STATE_ACK_DETECT           8
3310 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3311 #define ANEG_STATE_COMPLETE_ACK         10
3312 #define ANEG_STATE_IDLE_DETECT_INIT     11
3313 #define ANEG_STATE_IDLE_DETECT          12
3314 #define ANEG_STATE_LINK_OK              13
3315 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3316 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3317
3318         u32 flags;
3319 #define MR_AN_ENABLE            0x00000001
3320 #define MR_RESTART_AN           0x00000002
3321 #define MR_AN_COMPLETE          0x00000004
3322 #define MR_PAGE_RX              0x00000008
3323 #define MR_NP_LOADED            0x00000010
3324 #define MR_TOGGLE_TX            0x00000020
3325 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3326 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3327 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3328 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3329 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3330 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3331 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3332 #define MR_TOGGLE_RX            0x00002000
3333 #define MR_NP_RX                0x00004000
3334
3335 #define MR_LINK_OK              0x80000000
3336
3337         unsigned long link_time, cur_time;
3338
3339         u32 ability_match_cfg;
3340         int ability_match_count;
3341
3342         char ability_match, idle_match, ack_match;
3343
3344         u32 txconfig, rxconfig;
3345 #define ANEG_CFG_NP             0x00000080
3346 #define ANEG_CFG_ACK            0x00000040
3347 #define ANEG_CFG_RF2            0x00000020
3348 #define ANEG_CFG_RF1            0x00000010
3349 #define ANEG_CFG_PS2            0x00000001
3350 #define ANEG_CFG_PS1            0x00008000
3351 #define ANEG_CFG_HD             0x00004000
3352 #define ANEG_CFG_FD             0x00002000
3353 #define ANEG_CFG_INVAL          0x00001f06
3354
3355 };
3356 #define ANEG_OK         0
3357 #define ANEG_DONE       1
3358 #define ANEG_TIMER_ENAB 2
3359 #define ANEG_FAILED     -1
3360
3361 #define ANEG_STATE_SETTLE_TIME  10000
3362
3363 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3364                                    struct tg3_fiber_aneginfo *ap)
3365 {
3366         u16 flowctrl;
3367         unsigned long delta;
3368         u32 rx_cfg_reg;
3369         int ret;
3370
3371         if (ap->state == ANEG_STATE_UNKNOWN) {
3372                 ap->rxconfig = 0;
3373                 ap->link_time = 0;
3374                 ap->cur_time = 0;
3375                 ap->ability_match_cfg = 0;
3376                 ap->ability_match_count = 0;
3377                 ap->ability_match = 0;
3378                 ap->idle_match = 0;
3379                 ap->ack_match = 0;
3380         }
3381         ap->cur_time++;
3382
3383         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3384                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3385
3386                 if (rx_cfg_reg != ap->ability_match_cfg) {
3387                         ap->ability_match_cfg = rx_cfg_reg;
3388                         ap->ability_match = 0;
3389                         ap->ability_match_count = 0;
3390                 } else {
3391                         if (++ap->ability_match_count > 1) {
3392                                 ap->ability_match = 1;
3393                                 ap->ability_match_cfg = rx_cfg_reg;
3394                         }
3395                 }
3396                 if (rx_cfg_reg & ANEG_CFG_ACK)
3397                         ap->ack_match = 1;
3398                 else
3399                         ap->ack_match = 0;
3400
3401                 ap->idle_match = 0;
3402         } else {
3403                 ap->idle_match = 1;
3404                 ap->ability_match_cfg = 0;
3405                 ap->ability_match_count = 0;
3406                 ap->ability_match = 0;
3407                 ap->ack_match = 0;
3408
3409                 rx_cfg_reg = 0;
3410         }
3411
3412         ap->rxconfig = rx_cfg_reg;
3413         ret = ANEG_OK;
3414
3415         switch(ap->state) {
3416         case ANEG_STATE_UNKNOWN:
3417                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3418                         ap->state = ANEG_STATE_AN_ENABLE;
3419
3420                 /* fallthru */
3421         case ANEG_STATE_AN_ENABLE:
3422                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3423                 if (ap->flags & MR_AN_ENABLE) {
3424                         ap->link_time = 0;
3425                         ap->cur_time = 0;
3426                         ap->ability_match_cfg = 0;
3427                         ap->ability_match_count = 0;
3428                         ap->ability_match = 0;
3429                         ap->idle_match = 0;
3430                         ap->ack_match = 0;
3431
3432                         ap->state = ANEG_STATE_RESTART_INIT;
3433                 } else {
3434                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3435                 }
3436                 break;
3437
3438         case ANEG_STATE_RESTART_INIT:
3439                 ap->link_time = ap->cur_time;
3440                 ap->flags &= ~(MR_NP_LOADED);
3441                 ap->txconfig = 0;
3442                 tw32(MAC_TX_AUTO_NEG, 0);
3443                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3444                 tw32_f(MAC_MODE, tp->mac_mode);
3445                 udelay(40);
3446
3447                 ret = ANEG_TIMER_ENAB;
3448                 ap->state = ANEG_STATE_RESTART;
3449
3450                 /* fallthru */
3451         case ANEG_STATE_RESTART:
3452                 delta = ap->cur_time - ap->link_time;
3453                 if (delta > ANEG_STATE_SETTLE_TIME) {
3454                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3455                 } else {
3456                         ret = ANEG_TIMER_ENAB;
3457                 }
3458                 break;
3459
3460         case ANEG_STATE_DISABLE_LINK_OK:
3461                 ret = ANEG_DONE;
3462                 break;
3463
3464         case ANEG_STATE_ABILITY_DETECT_INIT:
3465                 ap->flags &= ~(MR_TOGGLE_TX);
3466                 ap->txconfig = ANEG_CFG_FD;
3467                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3468                 if (flowctrl & ADVERTISE_1000XPAUSE)
3469                         ap->txconfig |= ANEG_CFG_PS1;
3470                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3471                         ap->txconfig |= ANEG_CFG_PS2;
3472                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3473                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3474                 tw32_f(MAC_MODE, tp->mac_mode);
3475                 udelay(40);
3476
3477                 ap->state = ANEG_STATE_ABILITY_DETECT;
3478                 break;
3479
3480         case ANEG_STATE_ABILITY_DETECT:
3481                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3482                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3483                 }
3484                 break;
3485
3486         case ANEG_STATE_ACK_DETECT_INIT:
3487                 ap->txconfig |= ANEG_CFG_ACK;
3488                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3489                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3490                 tw32_f(MAC_MODE, tp->mac_mode);
3491                 udelay(40);
3492
3493                 ap->state = ANEG_STATE_ACK_DETECT;
3494
3495                 /* fallthru */
3496         case ANEG_STATE_ACK_DETECT:
3497                 if (ap->ack_match != 0) {
3498                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3499                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3500                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3501                         } else {
3502                                 ap->state = ANEG_STATE_AN_ENABLE;
3503                         }
3504                 } else if (ap->ability_match != 0 &&
3505                            ap->rxconfig == 0) {
3506                         ap->state = ANEG_STATE_AN_ENABLE;
3507                 }
3508                 break;
3509
3510         case ANEG_STATE_COMPLETE_ACK_INIT:
3511                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3512                         ret = ANEG_FAILED;
3513                         break;
3514                 }
3515                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3516                                MR_LP_ADV_HALF_DUPLEX |
3517                                MR_LP_ADV_SYM_PAUSE |
3518                                MR_LP_ADV_ASYM_PAUSE |
3519                                MR_LP_ADV_REMOTE_FAULT1 |
3520                                MR_LP_ADV_REMOTE_FAULT2 |
3521                                MR_LP_ADV_NEXT_PAGE |
3522                                MR_TOGGLE_RX |
3523                                MR_NP_RX);
3524                 if (ap->rxconfig & ANEG_CFG_FD)
3525                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3526                 if (ap->rxconfig & ANEG_CFG_HD)
3527                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3528                 if (ap->rxconfig & ANEG_CFG_PS1)
3529                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3530                 if (ap->rxconfig & ANEG_CFG_PS2)
3531                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3532                 if (ap->rxconfig & ANEG_CFG_RF1)
3533                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3534                 if (ap->rxconfig & ANEG_CFG_RF2)
3535                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3536                 if (ap->rxconfig & ANEG_CFG_NP)
3537                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3538
3539                 ap->link_time = ap->cur_time;
3540
3541                 ap->flags ^= (MR_TOGGLE_TX);
3542                 if (ap->rxconfig & 0x0008)
3543                         ap->flags |= MR_TOGGLE_RX;
3544                 if (ap->rxconfig & ANEG_CFG_NP)
3545                         ap->flags |= MR_NP_RX;
3546                 ap->flags |= MR_PAGE_RX;
3547
3548                 ap->state = ANEG_STATE_COMPLETE_ACK;
3549                 ret = ANEG_TIMER_ENAB;
3550                 break;
3551
3552         case ANEG_STATE_COMPLETE_ACK:
3553                 if (ap->ability_match != 0 &&
3554                     ap->rxconfig == 0) {
3555                         ap->state = ANEG_STATE_AN_ENABLE;
3556                         break;
3557                 }
3558                 delta = ap->cur_time - ap->link_time;
3559                 if (delta > ANEG_STATE_SETTLE_TIME) {
3560                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3561                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3562                         } else {
3563                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3564                                     !(ap->flags & MR_NP_RX)) {
3565                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3566                                 } else {
3567                                         ret = ANEG_FAILED;
3568                                 }
3569                         }
3570                 }
3571                 break;
3572
3573         case ANEG_STATE_IDLE_DETECT_INIT:
3574                 ap->link_time = ap->cur_time;
3575                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3576                 tw32_f(MAC_MODE, tp->mac_mode);
3577                 udelay(40);
3578
3579                 ap->state = ANEG_STATE_IDLE_DETECT;
3580                 ret = ANEG_TIMER_ENAB;
3581                 break;
3582
3583         case ANEG_STATE_IDLE_DETECT:
3584                 if (ap->ability_match != 0 &&
3585                     ap->rxconfig == 0) {
3586                         ap->state = ANEG_STATE_AN_ENABLE;
3587                         break;
3588                 }
3589                 delta = ap->cur_time - ap->link_time;
3590                 if (delta > ANEG_STATE_SETTLE_TIME) {
3591                         /* XXX another gem from the Broadcom driver :( */
3592                         ap->state = ANEG_STATE_LINK_OK;
3593                 }
3594                 break;
3595
3596         case ANEG_STATE_LINK_OK:
3597                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3598                 ret = ANEG_DONE;
3599                 break;
3600
3601         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3602                 /* ??? unimplemented */
3603                 break;
3604
3605         case ANEG_STATE_NEXT_PAGE_WAIT:
3606                 /* ??? unimplemented */
3607                 break;
3608
3609         default:
3610                 ret = ANEG_FAILED;
3611                 break;
3612         }
3613
3614         return ret;
3615 }
3616
3617 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3618 {
3619         int res = 0;
3620         struct tg3_fiber_aneginfo aninfo;
3621         int status = ANEG_FAILED;
3622         unsigned int tick;
3623         u32 tmp;
3624
3625         tw32_f(MAC_TX_AUTO_NEG, 0);
3626
3627         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3628         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3629         udelay(40);
3630
3631         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3632         udelay(40);
3633
3634         memset(&aninfo, 0, sizeof(aninfo));
3635         aninfo.flags |= MR_AN_ENABLE;
3636         aninfo.state = ANEG_STATE_UNKNOWN;
3637         aninfo.cur_time = 0;
3638         tick = 0;
3639         while (++tick < 195000) {
3640                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3641                 if (status == ANEG_DONE || status == ANEG_FAILED)
3642                         break;
3643
3644                 udelay(1);
3645         }
3646
3647         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3648         tw32_f(MAC_MODE, tp->mac_mode);
3649         udelay(40);
3650
3651         *txflags = aninfo.txconfig;
3652         *rxflags = aninfo.flags;
3653
3654         if (status == ANEG_DONE &&
3655             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3656                              MR_LP_ADV_FULL_DUPLEX)))
3657                 res = 1;
3658
3659         return res;
3660 }
3661
3662 static void tg3_init_bcm8002(struct tg3 *tp)
3663 {
3664         u32 mac_status = tr32(MAC_STATUS);
3665         int i;
3666
3667         /* Reset when initting first time or we have a link. */
3668         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3669             !(mac_status & MAC_STATUS_PCS_SYNCED))
3670                 return;
3671
3672         /* Set PLL lock range. */
3673         tg3_writephy(tp, 0x16, 0x8007);
3674
3675         /* SW reset */
3676         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3677
3678         /* Wait for reset to complete. */
3679         /* XXX schedule_timeout() ... */
3680         for (i = 0; i < 500; i++)
3681                 udelay(10);
3682
3683         /* Config mode; select PMA/Ch 1 regs. */
3684         tg3_writephy(tp, 0x10, 0x8411);
3685
3686         /* Enable auto-lock and comdet, select txclk for tx. */
3687         tg3_writephy(tp, 0x11, 0x0a10);
3688
3689         tg3_writephy(tp, 0x18, 0x00a0);
3690         tg3_writephy(tp, 0x16, 0x41ff);
3691
3692         /* Assert and deassert POR. */
3693         tg3_writephy(tp, 0x13, 0x0400);
3694         udelay(40);
3695         tg3_writephy(tp, 0x13, 0x0000);
3696
3697         tg3_writephy(tp, 0x11, 0x0a50);
3698         udelay(40);
3699         tg3_writephy(tp, 0x11, 0x0a10);
3700
3701         /* Wait for signal to stabilize */
3702         /* XXX schedule_timeout() ... */
3703         for (i = 0; i < 15000; i++)
3704                 udelay(10);
3705
3706         /* Deselect the channel register so we can read the PHYID
3707          * later.
3708          */
3709         tg3_writephy(tp, 0x10, 0x8011);
3710 }
3711
3712 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3713 {
3714         u16 flowctrl;
3715         u32 sg_dig_ctrl, sg_dig_status;
3716         u32 serdes_cfg, expected_sg_dig_ctrl;
3717         int workaround, port_a;
3718         int current_link_up;
3719
3720         serdes_cfg = 0;
3721         expected_sg_dig_ctrl = 0;
3722         workaround = 0;
3723         port_a = 1;
3724         current_link_up = 0;
3725
3726         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3727             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3728                 workaround = 1;
3729                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3730                         port_a = 0;
3731
3732                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3733                 /* preserve bits 20-23 for voltage regulator */
3734                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3735         }
3736
3737         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3738
3739         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3740                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3741                         if (workaround) {
3742                                 u32 val = serdes_cfg;
3743
3744                                 if (port_a)
3745                                         val |= 0xc010000;
3746                                 else
3747                                         val |= 0x4010000;
3748                                 tw32_f(MAC_SERDES_CFG, val);
3749                         }
3750
3751                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3752                 }
3753                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3754                         tg3_setup_flow_control(tp, 0, 0);
3755                         current_link_up = 1;
3756                 }
3757                 goto out;
3758         }
3759
3760         /* Want auto-negotiation.  */
3761         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3762
3763         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3764         if (flowctrl & ADVERTISE_1000XPAUSE)
3765                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3766         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3767                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3768
3769         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3770                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3771                     tp->serdes_counter &&
3772                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3773                                     MAC_STATUS_RCVD_CFG)) ==
3774                      MAC_STATUS_PCS_SYNCED)) {
3775                         tp->serdes_counter--;
3776                         current_link_up = 1;
3777                         goto out;
3778                 }
3779 restart_autoneg:
3780                 if (workaround)
3781                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3782                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3783                 udelay(5);
3784                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3785
3786                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3787                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3788         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3789                                  MAC_STATUS_SIGNAL_DET)) {
3790                 sg_dig_status = tr32(SG_DIG_STATUS);
3791                 mac_status = tr32(MAC_STATUS);
3792
3793                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3794                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3795                         u32 local_adv = 0, remote_adv = 0;
3796
3797                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3798                                 local_adv |= ADVERTISE_1000XPAUSE;
3799                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3800                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3801
3802                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3803                                 remote_adv |= LPA_1000XPAUSE;
3804                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3805                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3806
3807                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3808                         current_link_up = 1;
3809                         tp->serdes_counter = 0;
3810                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3811                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3812                         if (tp->serdes_counter)
3813                                 tp->serdes_counter--;
3814                         else {
3815                                 if (workaround) {
3816                                         u32 val = serdes_cfg;
3817
3818                                         if (port_a)
3819                                                 val |= 0xc010000;
3820                                         else
3821                                                 val |= 0x4010000;
3822
3823                                         tw32_f(MAC_SERDES_CFG, val);
3824                                 }
3825
3826                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3827                                 udelay(40);
3828
3829                                 /* Link parallel detection - link is up */
3830                                 /* only if we have PCS_SYNC and not */
3831                                 /* receiving config code words */
3832                                 mac_status = tr32(MAC_STATUS);
3833                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3834                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3835                                         tg3_setup_flow_control(tp, 0, 0);
3836                                         current_link_up = 1;
3837                                         tp->tg3_flags2 |=
3838                                                 TG3_FLG2_PARALLEL_DETECT;
3839                                         tp->serdes_counter =
3840                                                 SERDES_PARALLEL_DET_TIMEOUT;
3841                                 } else
3842                                         goto restart_autoneg;
3843                         }
3844                 }
3845         } else {
3846                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3847                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3848         }
3849
3850 out:
3851         return current_link_up;
3852 }
3853
3854 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3855 {
3856         int current_link_up = 0;
3857
3858         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3859                 goto out;
3860
3861         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3862                 u32 txflags, rxflags;
3863                 int i;
3864
3865                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3866                         u32 local_adv = 0, remote_adv = 0;
3867
3868                         if (txflags & ANEG_CFG_PS1)
3869                                 local_adv |= ADVERTISE_1000XPAUSE;
3870                         if (txflags & ANEG_CFG_PS2)
3871                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3872
3873                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3874                                 remote_adv |= LPA_1000XPAUSE;
3875                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3876                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3877
3878                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3879
3880                         current_link_up = 1;
3881                 }
3882                 for (i = 0; i < 30; i++) {
3883                         udelay(20);
3884                         tw32_f(MAC_STATUS,
3885                                (MAC_STATUS_SYNC_CHANGED |
3886                                 MAC_STATUS_CFG_CHANGED));
3887                         udelay(40);
3888                         if ((tr32(MAC_STATUS) &
3889                              (MAC_STATUS_SYNC_CHANGED |
3890                               MAC_STATUS_CFG_CHANGED)) == 0)
3891                                 break;
3892                 }
3893
3894                 mac_status = tr32(MAC_STATUS);
3895                 if (current_link_up == 0 &&
3896                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3897                     !(mac_status & MAC_STATUS_RCVD_CFG))
3898                         current_link_up = 1;
3899         } else {
3900                 tg3_setup_flow_control(tp, 0, 0);
3901
3902                 /* Forcing 1000FD link up. */
3903                 current_link_up = 1;
3904
3905                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3906                 udelay(40);
3907
3908                 tw32_f(MAC_MODE, tp->mac_mode);
3909                 udelay(40);
3910         }
3911
3912 out:
3913         return current_link_up;
3914 }
3915
3916 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3917 {
3918         u32 orig_pause_cfg;
3919         u16 orig_active_speed;
3920         u8 orig_active_duplex;
3921         u32 mac_status;
3922         int current_link_up;
3923         int i;
3924
3925         orig_pause_cfg = tp->link_config.active_flowctrl;
3926         orig_active_speed = tp->link_config.active_speed;
3927         orig_active_duplex = tp->link_config.active_duplex;
3928
3929         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3930             netif_carrier_ok(tp->dev) &&
3931             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3932                 mac_status = tr32(MAC_STATUS);
3933                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3934                                MAC_STATUS_SIGNAL_DET |
3935                                MAC_STATUS_CFG_CHANGED |
3936                                MAC_STATUS_RCVD_CFG);
3937                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3938                                    MAC_STATUS_SIGNAL_DET)) {
3939                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3940                                             MAC_STATUS_CFG_CHANGED));
3941                         return 0;
3942                 }
3943         }
3944
3945         tw32_f(MAC_TX_AUTO_NEG, 0);
3946
3947         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3948         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3949         tw32_f(MAC_MODE, tp->mac_mode);
3950         udelay(40);
3951
3952         if (tp->phy_id == PHY_ID_BCM8002)
3953                 tg3_init_bcm8002(tp);
3954
3955         /* Enable link change event even when serdes polling.  */
3956         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3957         udelay(40);
3958
3959         current_link_up = 0;
3960         mac_status = tr32(MAC_STATUS);
3961
3962         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3963                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3964         else
3965                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3966
3967         tp->napi[0].hw_status->status =
3968                 (SD_STATUS_UPDATED |
3969                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3970
3971         for (i = 0; i < 100; i++) {
3972                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3973                                     MAC_STATUS_CFG_CHANGED));
3974                 udelay(5);
3975                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3976                                          MAC_STATUS_CFG_CHANGED |
3977                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3978                         break;
3979         }
3980
3981         mac_status = tr32(MAC_STATUS);
3982         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3983                 current_link_up = 0;
3984                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3985                     tp->serdes_counter == 0) {
3986                         tw32_f(MAC_MODE, (tp->mac_mode |
3987                                           MAC_MODE_SEND_CONFIGS));
3988                         udelay(1);
3989                         tw32_f(MAC_MODE, tp->mac_mode);
3990                 }
3991         }
3992
3993         if (current_link_up == 1) {
3994                 tp->link_config.active_speed = SPEED_1000;
3995                 tp->link_config.active_duplex = DUPLEX_FULL;
3996                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3997                                     LED_CTRL_LNKLED_OVERRIDE |
3998                                     LED_CTRL_1000MBPS_ON));
3999         } else {
4000                 tp->link_config.active_speed = SPEED_INVALID;
4001                 tp->link_config.active_duplex = DUPLEX_INVALID;
4002                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003                                     LED_CTRL_LNKLED_OVERRIDE |
4004                                     LED_CTRL_TRAFFIC_OVERRIDE));
4005         }
4006
4007         if (current_link_up != netif_carrier_ok(tp->dev)) {
4008                 if (current_link_up)
4009                         netif_carrier_on(tp->dev);
4010                 else
4011                         netif_carrier_off(tp->dev);
4012                 tg3_link_report(tp);
4013         } else {
4014                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4015                 if (orig_pause_cfg != now_pause_cfg ||
4016                     orig_active_speed != tp->link_config.active_speed ||
4017                     orig_active_duplex != tp->link_config.active_duplex)
4018                         tg3_link_report(tp);
4019         }
4020
4021         return 0;
4022 }
4023
4024 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4025 {
4026         int current_link_up, err = 0;
4027         u32 bmsr, bmcr;
4028         u16 current_speed;
4029         u8 current_duplex;
4030         u32 local_adv, remote_adv;
4031
4032         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4033         tw32_f(MAC_MODE, tp->mac_mode);
4034         udelay(40);
4035
4036         tw32(MAC_EVENT, 0);
4037
4038         tw32_f(MAC_STATUS,
4039              (MAC_STATUS_SYNC_CHANGED |
4040               MAC_STATUS_CFG_CHANGED |
4041               MAC_STATUS_MI_COMPLETION |
4042               MAC_STATUS_LNKSTATE_CHANGED));
4043         udelay(40);
4044
4045         if (force_reset)
4046                 tg3_phy_reset(tp);
4047
4048         current_link_up = 0;
4049         current_speed = SPEED_INVALID;
4050         current_duplex = DUPLEX_INVALID;
4051
4052         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4053         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4054         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4055                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4056                         bmsr |= BMSR_LSTATUS;
4057                 else
4058                         bmsr &= ~BMSR_LSTATUS;
4059         }
4060
4061         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4062
4063         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4064             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4065                 /* do nothing, just check for link up at the end */
4066         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4067                 u32 adv, new_adv;
4068
4069                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4070                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4071                                   ADVERTISE_1000XPAUSE |
4072                                   ADVERTISE_1000XPSE_ASYM |
4073                                   ADVERTISE_SLCT);
4074
4075                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4076
4077                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4078                         new_adv |= ADVERTISE_1000XHALF;
4079                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4080                         new_adv |= ADVERTISE_1000XFULL;
4081
4082                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4083                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4084                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4085                         tg3_writephy(tp, MII_BMCR, bmcr);
4086
4087                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4088                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4089                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4090
4091                         return err;
4092                 }
4093         } else {
4094                 u32 new_bmcr;
4095
4096                 bmcr &= ~BMCR_SPEED1000;
4097                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4098
4099                 if (tp->link_config.duplex == DUPLEX_FULL)
4100                         new_bmcr |= BMCR_FULLDPLX;
4101
4102                 if (new_bmcr != bmcr) {
4103                         /* BMCR_SPEED1000 is a reserved bit that needs
4104                          * to be set on write.
4105                          */
4106                         new_bmcr |= BMCR_SPEED1000;
4107
4108                         /* Force a linkdown */
4109                         if (netif_carrier_ok(tp->dev)) {
4110                                 u32 adv;
4111
4112                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4113                                 adv &= ~(ADVERTISE_1000XFULL |
4114                                          ADVERTISE_1000XHALF |
4115                                          ADVERTISE_SLCT);
4116                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4117                                 tg3_writephy(tp, MII_BMCR, bmcr |
4118                                                            BMCR_ANRESTART |
4119                                                            BMCR_ANENABLE);
4120                                 udelay(10);
4121                                 netif_carrier_off(tp->dev);
4122                         }
4123                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4124                         bmcr = new_bmcr;
4125                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4126                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4127                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4128                             ASIC_REV_5714) {
4129                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4130                                         bmsr |= BMSR_LSTATUS;
4131                                 else
4132                                         bmsr &= ~BMSR_LSTATUS;
4133                         }
4134                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4135                 }
4136         }
4137
4138         if (bmsr & BMSR_LSTATUS) {
4139                 current_speed = SPEED_1000;
4140                 current_link_up = 1;
4141                 if (bmcr & BMCR_FULLDPLX)
4142                         current_duplex = DUPLEX_FULL;
4143                 else
4144                         current_duplex = DUPLEX_HALF;
4145
4146                 local_adv = 0;
4147                 remote_adv = 0;
4148
4149                 if (bmcr & BMCR_ANENABLE) {
4150                         u32 common;
4151
4152                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4153                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4154                         common = local_adv & remote_adv;
4155                         if (common & (ADVERTISE_1000XHALF |
4156                                       ADVERTISE_1000XFULL)) {
4157                                 if (common & ADVERTISE_1000XFULL)
4158                                         current_duplex = DUPLEX_FULL;
4159                                 else
4160                                         current_duplex = DUPLEX_HALF;
4161                         }
4162                         else
4163                                 current_link_up = 0;
4164                 }
4165         }
4166
4167         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4168                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4169
4170         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4171         if (tp->link_config.active_duplex == DUPLEX_HALF)
4172                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4173
4174         tw32_f(MAC_MODE, tp->mac_mode);
4175         udelay(40);
4176
4177         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4178
4179         tp->link_config.active_speed = current_speed;
4180         tp->link_config.active_duplex = current_duplex;
4181
4182         if (current_link_up != netif_carrier_ok(tp->dev)) {
4183                 if (current_link_up)
4184                         netif_carrier_on(tp->dev);
4185                 else {
4186                         netif_carrier_off(tp->dev);
4187                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4188                 }
4189                 tg3_link_report(tp);
4190         }
4191         return err;
4192 }
4193
4194 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4195 {
4196         if (tp->serdes_counter) {
4197                 /* Give autoneg time to complete. */
4198                 tp->serdes_counter--;
4199                 return;
4200         }
4201         if (!netif_carrier_ok(tp->dev) &&
4202             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4203                 u32 bmcr;
4204
4205                 tg3_readphy(tp, MII_BMCR, &bmcr);
4206                 if (bmcr & BMCR_ANENABLE) {
4207                         u32 phy1, phy2;
4208
4209                         /* Select shadow register 0x1f */
4210                         tg3_writephy(tp, 0x1c, 0x7c00);
4211                         tg3_readphy(tp, 0x1c, &phy1);
4212
4213                         /* Select expansion interrupt status register */
4214                         tg3_writephy(tp, 0x17, 0x0f01);
4215                         tg3_readphy(tp, 0x15, &phy2);
4216                         tg3_readphy(tp, 0x15, &phy2);
4217
4218                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4219                                 /* We have signal detect and not receiving
4220                                  * config code words, link is up by parallel
4221                                  * detection.
4222                                  */
4223
4224                                 bmcr &= ~BMCR_ANENABLE;
4225                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4226                                 tg3_writephy(tp, MII_BMCR, bmcr);
4227                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4228                         }
4229                 }
4230         }
4231         else if (netif_carrier_ok(tp->dev) &&
4232                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4233                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4234                 u32 phy2;
4235
4236                 /* Select expansion interrupt status register */
4237                 tg3_writephy(tp, 0x17, 0x0f01);
4238                 tg3_readphy(tp, 0x15, &phy2);
4239                 if (phy2 & 0x20) {
4240                         u32 bmcr;
4241
4242                         /* Config code words received, turn on autoneg. */
4243                         tg3_readphy(tp, MII_BMCR, &bmcr);
4244                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4245
4246                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4247
4248                 }
4249         }
4250 }
4251
4252 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4253 {
4254         int err;
4255
4256         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4257                 err = tg3_setup_fiber_phy(tp, force_reset);
4258         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4259                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4260         } else {
4261                 err = tg3_setup_copper_phy(tp, force_reset);
4262         }
4263
4264         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4265                 u32 val, scale;
4266
4267                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4268                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4269                         scale = 65;
4270                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4271                         scale = 6;
4272                 else
4273                         scale = 12;
4274
4275                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4276                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4277                 tw32(GRC_MISC_CFG, val);
4278         }
4279
4280         if (tp->link_config.active_speed == SPEED_1000 &&
4281             tp->link_config.active_duplex == DUPLEX_HALF)
4282                 tw32(MAC_TX_LENGTHS,
4283                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4284                       (6 << TX_LENGTHS_IPG_SHIFT) |
4285                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4286         else
4287                 tw32(MAC_TX_LENGTHS,
4288                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4289                       (6 << TX_LENGTHS_IPG_SHIFT) |
4290                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4291
4292         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4293                 if (netif_carrier_ok(tp->dev)) {
4294                         tw32(HOSTCC_STAT_COAL_TICKS,
4295                              tp->coal.stats_block_coalesce_usecs);
4296                 } else {
4297                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4298                 }
4299         }
4300
4301         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4302                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4303                 if (!netif_carrier_ok(tp->dev))
4304                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4305                               tp->pwrmgmt_thresh;
4306                 else
4307                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4308                 tw32(PCIE_PWR_MGMT_THRESH, val);
4309         }
4310
4311         return err;
4312 }
4313
4314 /* This is called whenever we suspect that the system chipset is re-
4315  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4316  * is bogus tx completions. We try to recover by setting the
4317  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4318  * in the workqueue.
4319  */
4320 static void tg3_tx_recover(struct tg3 *tp)
4321 {
4322         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4323                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4324
4325         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4326                "mapped I/O cycles to the network device, attempting to "
4327                "recover. Please report the problem to the driver maintainer "
4328                "and include system chipset information.\n", tp->dev->name);
4329
4330         spin_lock(&tp->lock);
4331         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4332         spin_unlock(&tp->lock);
4333 }
4334
4335 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4336 {
4337         smp_mb();
4338         return tnapi->tx_pending -
4339                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4340 }
4341
4342 /* Tigon3 never reports partial packet sends.  So we do not
4343  * need special logic to handle SKBs that have not had all
4344  * of their frags sent yet, like SunGEM does.
4345  */
4346 static void tg3_tx(struct tg3_napi *tnapi)
4347 {
4348         struct tg3 *tp = tnapi->tp;
4349         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4350         u32 sw_idx = tnapi->tx_cons;
4351         struct netdev_queue *txq;
4352         int index = tnapi - tp->napi;
4353
4354         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4355                 index--;
4356
4357         txq = netdev_get_tx_queue(tp->dev, index);
4358
4359         while (sw_idx != hw_idx) {
4360                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4361                 struct sk_buff *skb = ri->skb;
4362                 int i, tx_bug = 0;
4363
4364                 if (unlikely(skb == NULL)) {
4365                         tg3_tx_recover(tp);
4366                         return;
4367                 }
4368
4369                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4370
4371                 ri->skb = NULL;
4372
4373                 sw_idx = NEXT_TX(sw_idx);
4374
4375                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4376                         ri = &tnapi->tx_buffers[sw_idx];
4377                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4378                                 tx_bug = 1;
4379                         sw_idx = NEXT_TX(sw_idx);
4380                 }
4381
4382                 dev_kfree_skb(skb);
4383
4384                 if (unlikely(tx_bug)) {
4385                         tg3_tx_recover(tp);
4386                         return;
4387                 }
4388         }
4389
4390         tnapi->tx_cons = sw_idx;
4391
4392         /* Need to make the tx_cons update visible to tg3_start_xmit()
4393          * before checking for netif_queue_stopped().  Without the
4394          * memory barrier, there is a small possibility that tg3_start_xmit()
4395          * will miss it and cause the queue to be stopped forever.
4396          */
4397         smp_mb();
4398
4399         if (unlikely(netif_tx_queue_stopped(txq) &&
4400                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4401                 __netif_tx_lock(txq, smp_processor_id());
4402                 if (netif_tx_queue_stopped(txq) &&
4403                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4404                         netif_tx_wake_queue(txq);
4405                 __netif_tx_unlock(txq);
4406         }
4407 }
4408
4409 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4410 {
4411         if (!ri->skb)
4412                 return;
4413
4414         pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4415                          map_sz, PCI_DMA_FROMDEVICE);
4416         dev_kfree_skb_any(ri->skb);
4417         ri->skb = NULL;
4418 }
4419
4420 /* Returns size of skb allocated or < 0 on error.
4421  *
4422  * We only need to fill in the address because the other members
4423  * of the RX descriptor are invariant, see tg3_init_rings.
4424  *
4425  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4426  * posting buffers we only dirty the first cache line of the RX
4427  * descriptor (containing the address).  Whereas for the RX status
4428  * buffers the cpu only reads the last cacheline of the RX descriptor
4429  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4430  */
4431 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4432                             u32 opaque_key, u32 dest_idx_unmasked)
4433 {
4434         struct tg3_rx_buffer_desc *desc;
4435         struct ring_info *map, *src_map;
4436         struct sk_buff *skb;
4437         dma_addr_t mapping;
4438         int skb_size, dest_idx;
4439
4440         src_map = NULL;
4441         switch (opaque_key) {
4442         case RXD_OPAQUE_RING_STD:
4443                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4444                 desc = &tpr->rx_std[dest_idx];
4445                 map = &tpr->rx_std_buffers[dest_idx];
4446                 skb_size = tp->rx_pkt_map_sz;
4447                 break;
4448
4449         case RXD_OPAQUE_RING_JUMBO:
4450                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4451                 desc = &tpr->rx_jmb[dest_idx].std;
4452                 map = &tpr->rx_jmb_buffers[dest_idx];
4453                 skb_size = TG3_RX_JMB_MAP_SZ;
4454                 break;
4455
4456         default:
4457                 return -EINVAL;
4458         }
4459
4460         /* Do not overwrite any of the map or rp information
4461          * until we are sure we can commit to a new buffer.
4462          *
4463          * Callers depend upon this behavior and assume that
4464          * we leave everything unchanged if we fail.
4465          */
4466         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4467         if (skb == NULL)
4468                 return -ENOMEM;
4469
4470         skb_reserve(skb, tp->rx_offset);
4471
4472         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4473                                  PCI_DMA_FROMDEVICE);
4474         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4475                 dev_kfree_skb(skb);
4476                 return -EIO;
4477         }
4478
4479         map->skb = skb;
4480         pci_unmap_addr_set(map, mapping, mapping);
4481
4482         desc->addr_hi = ((u64)mapping >> 32);
4483         desc->addr_lo = ((u64)mapping & 0xffffffff);
4484
4485         return skb_size;
4486 }
4487
4488 /* We only need to move over in the address because the other
4489  * members of the RX descriptor are invariant.  See notes above
4490  * tg3_alloc_rx_skb for full details.
4491  */
4492 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4493                            struct tg3_rx_prodring_set *dpr,
4494                            u32 opaque_key, int src_idx,
4495                            u32 dest_idx_unmasked)
4496 {
4497         struct tg3 *tp = tnapi->tp;
4498         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4499         struct ring_info *src_map, *dest_map;
4500         int dest_idx;
4501         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4502
4503         switch (opaque_key) {
4504         case RXD_OPAQUE_RING_STD:
4505                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4506                 dest_desc = &dpr->rx_std[dest_idx];
4507                 dest_map = &dpr->rx_std_buffers[dest_idx];
4508                 src_desc = &spr->rx_std[src_idx];
4509                 src_map = &spr->rx_std_buffers[src_idx];
4510                 break;
4511
4512         case RXD_OPAQUE_RING_JUMBO:
4513                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4514                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4515                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4516                 src_desc = &spr->rx_jmb[src_idx].std;
4517                 src_map = &spr->rx_jmb_buffers[src_idx];
4518                 break;
4519
4520         default:
4521                 return;
4522         }
4523
4524         dest_map->skb = src_map->skb;
4525         pci_unmap_addr_set(dest_map, mapping,
4526                            pci_unmap_addr(src_map, mapping));
4527         dest_desc->addr_hi = src_desc->addr_hi;
4528         dest_desc->addr_lo = src_desc->addr_lo;
4529         src_map->skb = NULL;
4530 }
4531
4532 /* The RX ring scheme is composed of multiple rings which post fresh
4533  * buffers to the chip, and one special ring the chip uses to report
4534  * status back to the host.
4535  *
4536  * The special ring reports the status of received packets to the
4537  * host.  The chip does not write into the original descriptor the
4538  * RX buffer was obtained from.  The chip simply takes the original
4539  * descriptor as provided by the host, updates the status and length
4540  * field, then writes this into the next status ring entry.
4541  *
4542  * Each ring the host uses to post buffers to the chip is described
4543  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4544  * it is first placed into the on-chip ram.  When the packet's length
4545  * is known, it walks down the TG3_BDINFO entries to select the ring.
4546  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4547  * which is within the range of the new packet's length is chosen.
4548  *
4549  * The "separate ring for rx status" scheme may sound queer, but it makes
4550  * sense from a cache coherency perspective.  If only the host writes
4551  * to the buffer post rings, and only the chip writes to the rx status
4552  * rings, then cache lines never move beyond shared-modified state.
4553  * If both the host and chip were to write into the same ring, cache line
4554  * eviction could occur since both entities want it in an exclusive state.
4555  */
4556 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4557 {
4558         struct tg3 *tp = tnapi->tp;
4559         u32 work_mask, rx_std_posted = 0;
4560         u32 std_prod_idx, jmb_prod_idx;
4561         u32 sw_idx = tnapi->rx_rcb_ptr;
4562         u16 hw_idx;
4563         int received;
4564         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4565
4566         hw_idx = *(tnapi->rx_rcb_prod_idx);
4567         /*
4568          * We need to order the read of hw_idx and the read of
4569          * the opaque cookie.
4570          */
4571         rmb();
4572         work_mask = 0;
4573         received = 0;
4574         std_prod_idx = tpr->rx_std_prod_idx;
4575         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4576         while (sw_idx != hw_idx && budget > 0) {
4577                 struct ring_info *ri;
4578                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4579                 unsigned int len;
4580                 struct sk_buff *skb;
4581                 dma_addr_t dma_addr;
4582                 u32 opaque_key, desc_idx, *post_ptr;
4583
4584                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4585                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4586                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4587                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4588                         dma_addr = pci_unmap_addr(ri, mapping);
4589                         skb = ri->skb;
4590                         post_ptr = &std_prod_idx;
4591                         rx_std_posted++;
4592                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4593                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4594                         dma_addr = pci_unmap_addr(ri, mapping);
4595                         skb = ri->skb;
4596                         post_ptr = &jmb_prod_idx;
4597                 } else
4598                         goto next_pkt_nopost;
4599
4600                 work_mask |= opaque_key;
4601
4602                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4603                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4604                 drop_it:
4605                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4606                                        desc_idx, *post_ptr);
4607                 drop_it_no_recycle:
4608                         /* Other statistics kept track of by card. */
4609                         tp->net_stats.rx_dropped++;
4610                         goto next_pkt;
4611                 }
4612
4613                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4614                       ETH_FCS_LEN;
4615
4616                 if (len > RX_COPY_THRESHOLD
4617                         && tp->rx_offset == NET_IP_ALIGN
4618                         /* rx_offset will likely not equal NET_IP_ALIGN
4619                          * if this is a 5701 card running in PCI-X mode
4620                          * [see tg3_get_invariants()]
4621                          */
4622                 ) {
4623                         int skb_size;
4624
4625                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4626                                                     *post_ptr);
4627                         if (skb_size < 0)
4628                                 goto drop_it;
4629
4630                         ri->skb = NULL;
4631
4632                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4633                                          PCI_DMA_FROMDEVICE);
4634
4635                         skb_put(skb, len);
4636                 } else {
4637                         struct sk_buff *copy_skb;
4638
4639                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4640                                        desc_idx, *post_ptr);
4641
4642                         copy_skb = netdev_alloc_skb(tp->dev,
4643                                                     len + TG3_RAW_IP_ALIGN);
4644                         if (copy_skb == NULL)
4645                                 goto drop_it_no_recycle;
4646
4647                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4648                         skb_put(copy_skb, len);
4649                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4650                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4651                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4652
4653                         /* We'll reuse the original ring buffer. */
4654                         skb = copy_skb;
4655                 }
4656
4657                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4658                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4659                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4660                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4661                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4662                 else
4663                         skb->ip_summed = CHECKSUM_NONE;
4664
4665                 skb->protocol = eth_type_trans(skb, tp->dev);
4666
4667                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4668                     skb->protocol != htons(ETH_P_8021Q)) {
4669                         dev_kfree_skb(skb);
4670                         goto next_pkt;
4671                 }
4672
4673 #if TG3_VLAN_TAG_USED
4674                 if (tp->vlgrp != NULL &&
4675                     desc->type_flags & RXD_FLAG_VLAN) {
4676                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4677                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4678                 } else
4679 #endif
4680                         napi_gro_receive(&tnapi->napi, skb);
4681
4682                 received++;
4683                 budget--;
4684
4685 next_pkt:
4686                 (*post_ptr)++;
4687
4688                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4689                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4690                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
4691                         work_mask &= ~RXD_OPAQUE_RING_STD;
4692                         rx_std_posted = 0;
4693                 }
4694 next_pkt_nopost:
4695                 sw_idx++;
4696                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4697
4698                 /* Refresh hw_idx to see if there is new work */
4699                 if (sw_idx == hw_idx) {
4700                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4701                         rmb();
4702                 }
4703         }
4704
4705         /* ACK the status ring. */
4706         tnapi->rx_rcb_ptr = sw_idx;
4707         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4708
4709         /* Refill RX ring(s). */
4710         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4711                 if (work_mask & RXD_OPAQUE_RING_STD) {
4712                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4713                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4714                                      tpr->rx_std_prod_idx);
4715                 }
4716                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4717                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4718                                                TG3_RX_JUMBO_RING_SIZE;
4719                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4720                                      tpr->rx_jmb_prod_idx);
4721                 }
4722                 mmiowb();
4723         } else if (work_mask) {
4724                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4725                  * updated before the producer indices can be updated.
4726                  */
4727                 smp_wmb();
4728
4729                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4730                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4731
4732                 napi_schedule(&tp->napi[1].napi);
4733         }
4734
4735         return received;
4736 }
4737
4738 static void tg3_poll_link(struct tg3 *tp)
4739 {
4740         /* handle link change and other phy events */
4741         if (!(tp->tg3_flags &
4742               (TG3_FLAG_USE_LINKCHG_REG |
4743                TG3_FLAG_POLL_SERDES))) {
4744                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4745
4746                 if (sblk->status & SD_STATUS_LINK_CHG) {
4747                         sblk->status = SD_STATUS_UPDATED |
4748                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4749                         spin_lock(&tp->lock);
4750                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4751                                 tw32_f(MAC_STATUS,
4752                                      (MAC_STATUS_SYNC_CHANGED |
4753                                       MAC_STATUS_CFG_CHANGED |
4754                                       MAC_STATUS_MI_COMPLETION |
4755                                       MAC_STATUS_LNKSTATE_CHANGED));
4756                                 udelay(40);
4757                         } else
4758                                 tg3_setup_phy(tp, 0);
4759                         spin_unlock(&tp->lock);
4760                 }
4761         }
4762 }
4763
4764 static void tg3_rx_prodring_xfer(struct tg3 *tp,
4765                                  struct tg3_rx_prodring_set *dpr,
4766                                  struct tg3_rx_prodring_set *spr)
4767 {
4768         u32 si, di, cpycnt, src_prod_idx;
4769         int i;
4770
4771         while (1) {
4772                 src_prod_idx = spr->rx_std_prod_idx;
4773
4774                 /* Make sure updates to the rx_std_buffers[] entries and the
4775                  * standard producer index are seen in the correct order.
4776                  */
4777                 smp_rmb();
4778
4779                 if (spr->rx_std_cons_idx == src_prod_idx)
4780                         break;
4781
4782                 if (spr->rx_std_cons_idx < src_prod_idx)
4783                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4784                 else
4785                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4786
4787                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4788
4789                 si = spr->rx_std_cons_idx;
4790                 di = dpr->rx_std_prod_idx;
4791
4792                 memcpy(&dpr->rx_std_buffers[di],
4793                        &spr->rx_std_buffers[si],
4794                        cpycnt * sizeof(struct ring_info));
4795
4796                 for (i = 0; i < cpycnt; i++, di++, si++) {
4797                         struct tg3_rx_buffer_desc *sbd, *dbd;
4798                         sbd = &spr->rx_std[si];
4799                         dbd = &dpr->rx_std[di];
4800                         dbd->addr_hi = sbd->addr_hi;
4801                         dbd->addr_lo = sbd->addr_lo;
4802                 }
4803
4804                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4805                                        TG3_RX_RING_SIZE;
4806                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4807                                        TG3_RX_RING_SIZE;
4808         }
4809
4810         while (1) {
4811                 src_prod_idx = spr->rx_jmb_prod_idx;
4812
4813                 /* Make sure updates to the rx_jmb_buffers[] entries and
4814                  * the jumbo producer index are seen in the correct order.
4815                  */
4816                 smp_rmb();
4817
4818                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4819                         break;
4820
4821                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4822                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4823                 else
4824                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4825
4826                 cpycnt = min(cpycnt,
4827                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4828
4829                 si = spr->rx_jmb_cons_idx;
4830                 di = dpr->rx_jmb_prod_idx;
4831
4832                 memcpy(&dpr->rx_jmb_buffers[di],
4833                        &spr->rx_jmb_buffers[si],
4834                        cpycnt * sizeof(struct ring_info));
4835
4836                 for (i = 0; i < cpycnt; i++, di++, si++) {
4837                         struct tg3_rx_buffer_desc *sbd, *dbd;
4838                         sbd = &spr->rx_jmb[si].std;
4839                         dbd = &dpr->rx_jmb[di].std;
4840                         dbd->addr_hi = sbd->addr_hi;
4841                         dbd->addr_lo = sbd->addr_lo;
4842                 }
4843
4844                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4845                                        TG3_RX_JUMBO_RING_SIZE;
4846                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4847                                        TG3_RX_JUMBO_RING_SIZE;
4848         }
4849 }
4850
4851 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4852 {
4853         struct tg3 *tp = tnapi->tp;
4854
4855         /* run TX completion thread */
4856         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4857                 tg3_tx(tnapi);
4858                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4859                         return work_done;
4860         }
4861
4862         /* run RX thread, within the bounds set by NAPI.
4863          * All RX "locking" is done by ensuring outside
4864          * code synchronizes with tg3->napi.poll()
4865          */
4866         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4867                 work_done += tg3_rx(tnapi, budget - work_done);
4868
4869         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4870                 int i;
4871                 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4872                 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4873
4874                 for (i = 2; i < tp->irq_cnt; i++)
4875                         tg3_rx_prodring_xfer(tp, tnapi->prodring,
4876                                              tp->napi[i].prodring);
4877
4878                 wmb();
4879
4880                 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4881                         u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4882                         tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4883                 }
4884
4885                 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4886                         u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4887                         tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4888                 }
4889
4890                 mmiowb();
4891         }
4892
4893         return work_done;
4894 }
4895
4896 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4897 {
4898         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4899         struct tg3 *tp = tnapi->tp;
4900         int work_done = 0;
4901         struct tg3_hw_status *sblk = tnapi->hw_status;
4902
4903         while (1) {
4904                 work_done = tg3_poll_work(tnapi, work_done, budget);
4905
4906                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4907                         goto tx_recovery;
4908
4909                 if (unlikely(work_done >= budget))
4910                         break;
4911
4912                 /* tp->last_tag is used in tg3_restart_ints() below
4913                  * to tell the hw how much work has been processed,
4914                  * so we must read it before checking for more work.
4915                  */
4916                 tnapi->last_tag = sblk->status_tag;
4917                 tnapi->last_irq_tag = tnapi->last_tag;
4918                 rmb();
4919
4920                 /* check for RX/TX work to do */
4921                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4922                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4923                         napi_complete(napi);
4924                         /* Reenable interrupts. */
4925                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4926                         mmiowb();
4927                         break;
4928                 }
4929         }
4930
4931         return work_done;
4932
4933 tx_recovery:
4934         /* work_done is guaranteed to be less than budget. */
4935         napi_complete(napi);
4936         schedule_work(&tp->reset_task);
4937         return work_done;
4938 }
4939
4940 static int tg3_poll(struct napi_struct *napi, int budget)
4941 {
4942         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4943         struct tg3 *tp = tnapi->tp;
4944         int work_done = 0;
4945         struct tg3_hw_status *sblk = tnapi->hw_status;
4946
4947         while (1) {
4948                 tg3_poll_link(tp);
4949
4950                 work_done = tg3_poll_work(tnapi, work_done, budget);
4951
4952                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4953                         goto tx_recovery;
4954
4955                 if (unlikely(work_done >= budget))
4956                         break;
4957
4958                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4959                         /* tp->last_tag is used in tg3_int_reenable() below
4960                          * to tell the hw how much work has been processed,
4961                          * so we must read it before checking for more work.
4962                          */
4963                         tnapi->last_tag = sblk->status_tag;
4964                         tnapi->last_irq_tag = tnapi->last_tag;
4965                         rmb();
4966                 } else
4967                         sblk->status &= ~SD_STATUS_UPDATED;
4968
4969                 if (likely(!tg3_has_work(tnapi))) {
4970                         napi_complete(napi);
4971                         tg3_int_reenable(tnapi);
4972                         break;
4973                 }
4974         }
4975
4976         return work_done;
4977
4978 tx_recovery:
4979         /* work_done is guaranteed to be less than budget. */
4980         napi_complete(napi);
4981         schedule_work(&tp->reset_task);
4982         return work_done;
4983 }
4984
4985 static void tg3_irq_quiesce(struct tg3 *tp)
4986 {
4987         int i;
4988
4989         BUG_ON(tp->irq_sync);
4990
4991         tp->irq_sync = 1;
4992         smp_mb();
4993
4994         for (i = 0; i < tp->irq_cnt; i++)
4995                 synchronize_irq(tp->napi[i].irq_vec);
4996 }
4997
4998 static inline int tg3_irq_sync(struct tg3 *tp)
4999 {
5000         return tp->irq_sync;
5001 }
5002
5003 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5004  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5005  * with as well.  Most of the time, this is not necessary except when
5006  * shutting down the device.
5007  */
5008 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5009 {
5010         spin_lock_bh(&tp->lock);
5011         if (irq_sync)
5012                 tg3_irq_quiesce(tp);
5013 }
5014
5015 static inline void tg3_full_unlock(struct tg3 *tp)
5016 {
5017         spin_unlock_bh(&tp->lock);
5018 }
5019
5020 /* One-shot MSI handler - Chip automatically disables interrupt
5021  * after sending MSI so driver doesn't have to do it.
5022  */
5023 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5024 {
5025         struct tg3_napi *tnapi = dev_id;
5026         struct tg3 *tp = tnapi->tp;
5027
5028         prefetch(tnapi->hw_status);
5029         if (tnapi->rx_rcb)
5030                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5031
5032         if (likely(!tg3_irq_sync(tp)))
5033                 napi_schedule(&tnapi->napi);
5034
5035         return IRQ_HANDLED;
5036 }
5037
5038 /* MSI ISR - No need to check for interrupt sharing and no need to
5039  * flush status block and interrupt mailbox. PCI ordering rules
5040  * guarantee that MSI will arrive after the status block.
5041  */
5042 static irqreturn_t tg3_msi(int irq, void *dev_id)
5043 {
5044         struct tg3_napi *tnapi = dev_id;
5045         struct tg3 *tp = tnapi->tp;
5046
5047         prefetch(tnapi->hw_status);
5048         if (tnapi->rx_rcb)
5049                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5050         /*
5051          * Writing any value to intr-mbox-0 clears PCI INTA# and
5052          * chip-internal interrupt pending events.
5053          * Writing non-zero to intr-mbox-0 additional tells the
5054          * NIC to stop sending us irqs, engaging "in-intr-handler"
5055          * event coalescing.
5056          */
5057         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5058         if (likely(!tg3_irq_sync(tp)))
5059                 napi_schedule(&tnapi->napi);
5060
5061         return IRQ_RETVAL(1);
5062 }
5063
5064 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5065 {
5066         struct tg3_napi *tnapi = dev_id;
5067         struct tg3 *tp = tnapi->tp;
5068         struct tg3_hw_status *sblk = tnapi->hw_status;
5069         unsigned int handled = 1;
5070
5071         /* In INTx mode, it is possible for the interrupt to arrive at
5072          * the CPU before the status block posted prior to the interrupt.
5073          * Reading the PCI State register will confirm whether the
5074          * interrupt is ours and will flush the status block.
5075          */
5076         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5077                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5078                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5079                         handled = 0;
5080                         goto out;
5081                 }
5082         }
5083
5084         /*
5085          * Writing any value to intr-mbox-0 clears PCI INTA# and
5086          * chip-internal interrupt pending events.
5087          * Writing non-zero to intr-mbox-0 additional tells the
5088          * NIC to stop sending us irqs, engaging "in-intr-handler"
5089          * event coalescing.
5090          *
5091          * Flush the mailbox to de-assert the IRQ immediately to prevent
5092          * spurious interrupts.  The flush impacts performance but
5093          * excessive spurious interrupts can be worse in some cases.
5094          */
5095         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5096         if (tg3_irq_sync(tp))
5097                 goto out;
5098         sblk->status &= ~SD_STATUS_UPDATED;
5099         if (likely(tg3_has_work(tnapi))) {
5100                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5101                 napi_schedule(&tnapi->napi);
5102         } else {
5103                 /* No work, shared interrupt perhaps?  re-enable
5104                  * interrupts, and flush that PCI write
5105                  */
5106                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5107                                0x00000000);
5108         }
5109 out:
5110         return IRQ_RETVAL(handled);
5111 }
5112
5113 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5114 {
5115         struct tg3_napi *tnapi = dev_id;
5116         struct tg3 *tp = tnapi->tp;
5117         struct tg3_hw_status *sblk = tnapi->hw_status;
5118         unsigned int handled = 1;
5119
5120         /* In INTx mode, it is possible for the interrupt to arrive at
5121          * the CPU before the status block posted prior to the interrupt.
5122          * Reading the PCI State register will confirm whether the
5123          * interrupt is ours and will flush the status block.
5124          */
5125         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5126                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5127                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5128                         handled = 0;
5129                         goto out;
5130                 }
5131         }
5132
5133         /*
5134          * writing any value to intr-mbox-0 clears PCI INTA# and
5135          * chip-internal interrupt pending events.
5136          * writing non-zero to intr-mbox-0 additional tells the
5137          * NIC to stop sending us irqs, engaging "in-intr-handler"
5138          * event coalescing.
5139          *
5140          * Flush the mailbox to de-assert the IRQ immediately to prevent
5141          * spurious interrupts.  The flush impacts performance but
5142          * excessive spurious interrupts can be worse in some cases.
5143          */
5144         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5145
5146         /*
5147          * In a shared interrupt configuration, sometimes other devices'
5148          * interrupts will scream.  We record the current status tag here
5149          * so that the above check can report that the screaming interrupts
5150          * are unhandled.  Eventually they will be silenced.
5151          */
5152         tnapi->last_irq_tag = sblk->status_tag;
5153
5154         if (tg3_irq_sync(tp))
5155                 goto out;
5156
5157         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5158
5159         napi_schedule(&tnapi->napi);
5160
5161 out:
5162         return IRQ_RETVAL(handled);
5163 }
5164
5165 /* ISR for interrupt test */
5166 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5167 {
5168         struct tg3_napi *tnapi = dev_id;
5169         struct tg3 *tp = tnapi->tp;
5170         struct tg3_hw_status *sblk = tnapi->hw_status;
5171
5172         if ((sblk->status & SD_STATUS_UPDATED) ||
5173             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5174                 tg3_disable_ints(tp);
5175                 return IRQ_RETVAL(1);
5176         }
5177         return IRQ_RETVAL(0);
5178 }
5179
5180 static int tg3_init_hw(struct tg3 *, int);
5181 static int tg3_halt(struct tg3 *, int, int);
5182
5183 /* Restart hardware after configuration changes, self-test, etc.
5184  * Invoked with tp->lock held.
5185  */
5186 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5187         __releases(tp->lock)
5188         __acquires(tp->lock)
5189 {
5190         int err;
5191
5192         err = tg3_init_hw(tp, reset_phy);
5193         if (err) {
5194                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5195                        "aborting.\n", tp->dev->name);
5196                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5197                 tg3_full_unlock(tp);
5198                 del_timer_sync(&tp->timer);
5199                 tp->irq_sync = 0;
5200                 tg3_napi_enable(tp);
5201                 dev_close(tp->dev);
5202                 tg3_full_lock(tp, 0);
5203         }
5204         return err;
5205 }
5206
5207 #ifdef CONFIG_NET_POLL_CONTROLLER
5208 static void tg3_poll_controller(struct net_device *dev)
5209 {
5210         int i;
5211         struct tg3 *tp = netdev_priv(dev);
5212
5213         for (i = 0; i < tp->irq_cnt; i++)
5214                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5215 }
5216 #endif
5217
5218 static void tg3_reset_task(struct work_struct *work)
5219 {
5220         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5221         int err;
5222         unsigned int restart_timer;
5223
5224         tg3_full_lock(tp, 0);
5225
5226         if (!netif_running(tp->dev)) {
5227                 tg3_full_unlock(tp);
5228                 return;
5229         }
5230
5231         tg3_full_unlock(tp);
5232
5233         tg3_phy_stop(tp);
5234
5235         tg3_netif_stop(tp);
5236
5237         tg3_full_lock(tp, 1);
5238
5239         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5240         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5241
5242         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5243                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5244                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5245                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5246                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5247         }
5248
5249         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5250         err = tg3_init_hw(tp, 1);
5251         if (err)
5252                 goto out;
5253
5254         tg3_netif_start(tp);
5255
5256         if (restart_timer)
5257                 mod_timer(&tp->timer, jiffies + 1);
5258
5259 out:
5260         tg3_full_unlock(tp);
5261
5262         if (!err)
5263                 tg3_phy_start(tp);
5264 }
5265
5266 static void tg3_dump_short_state(struct tg3 *tp)
5267 {
5268         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5269                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5270         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5271                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5272 }
5273
5274 static void tg3_tx_timeout(struct net_device *dev)
5275 {
5276         struct tg3 *tp = netdev_priv(dev);
5277
5278         if (netif_msg_tx_err(tp)) {
5279                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5280                        dev->name);
5281                 tg3_dump_short_state(tp);
5282         }
5283
5284         schedule_work(&tp->reset_task);
5285 }
5286
5287 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5288 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5289 {
5290         u32 base = (u32) mapping & 0xffffffff;
5291
5292         return ((base > 0xffffdcc0) &&
5293                 (base + len + 8 < base));
5294 }
5295
5296 /* Test for DMA addresses > 40-bit */
5297 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5298                                           int len)
5299 {
5300 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5301         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5302                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5303         return 0;
5304 #else
5305         return 0;
5306 #endif
5307 }
5308
5309 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5310
5311 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5312 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5313                                        struct sk_buff *skb, u32 last_plus_one,
5314                                        u32 *start, u32 base_flags, u32 mss)
5315 {
5316         struct tg3 *tp = tnapi->tp;
5317         struct sk_buff *new_skb;
5318         dma_addr_t new_addr = 0;
5319         u32 entry = *start;
5320         int i, ret = 0;
5321
5322         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5323                 new_skb = skb_copy(skb, GFP_ATOMIC);
5324         else {
5325                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5326
5327                 new_skb = skb_copy_expand(skb,
5328                                           skb_headroom(skb) + more_headroom,
5329                                           skb_tailroom(skb), GFP_ATOMIC);
5330         }
5331
5332         if (!new_skb) {
5333                 ret = -1;
5334         } else {
5335                 /* New SKB is guaranteed to be linear. */
5336                 entry = *start;
5337                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5338                 new_addr = skb_shinfo(new_skb)->dma_head;
5339
5340                 /* Make sure new skb does not cross any 4G boundaries.
5341                  * Drop the packet if it does.
5342                  */
5343                 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5344                             tg3_4g_overflow_test(new_addr, new_skb->len))) {
5345                         if (!ret)
5346                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5347                                               DMA_TO_DEVICE);
5348                         ret = -1;
5349                         dev_kfree_skb(new_skb);
5350                         new_skb = NULL;
5351                 } else {
5352                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5353                                     base_flags, 1 | (mss << 1));
5354                         *start = NEXT_TX(entry);
5355                 }
5356         }
5357
5358         /* Now clean up the sw ring entries. */
5359         i = 0;
5360         while (entry != last_plus_one) {
5361                 if (i == 0)
5362                         tnapi->tx_buffers[entry].skb = new_skb;
5363                 else
5364                         tnapi->tx_buffers[entry].skb = NULL;
5365                 entry = NEXT_TX(entry);
5366                 i++;
5367         }
5368
5369         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5370         dev_kfree_skb(skb);
5371
5372         return ret;
5373 }
5374
5375 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5376                         dma_addr_t mapping, int len, u32 flags,
5377                         u32 mss_and_is_end)
5378 {
5379         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5380         int is_end = (mss_and_is_end & 0x1);
5381         u32 mss = (mss_and_is_end >> 1);
5382         u32 vlan_tag = 0;
5383
5384         if (is_end)
5385                 flags |= TXD_FLAG_END;
5386         if (flags & TXD_FLAG_VLAN) {
5387                 vlan_tag = flags >> 16;
5388                 flags &= 0xffff;
5389         }
5390         vlan_tag |= (mss << TXD_MSS_SHIFT);
5391
5392         txd->addr_hi = ((u64) mapping >> 32);
5393         txd->addr_lo = ((u64) mapping & 0xffffffff);
5394         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5395         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5396 }
5397
5398 /* hard_start_xmit for devices that don't have any bugs and
5399  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5400  */
5401 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5402                                   struct net_device *dev)
5403 {
5404         struct tg3 *tp = netdev_priv(dev);
5405         u32 len, entry, base_flags, mss;
5406         struct skb_shared_info *sp;
5407         dma_addr_t mapping;
5408         struct tg3_napi *tnapi;
5409         struct netdev_queue *txq;
5410
5411         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5412         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5413         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5414                 tnapi++;
5415
5416         /* We are running in BH disabled context with netif_tx_lock
5417          * and TX reclaim runs via tp->napi.poll inside of a software
5418          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5419          * no IRQ context deadlocks to worry about either.  Rejoice!
5420          */
5421         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5422                 if (!netif_tx_queue_stopped(txq)) {
5423                         netif_tx_stop_queue(txq);
5424
5425                         /* This is a hard error, log it. */
5426                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5427                                "queue awake!\n", dev->name);
5428                 }
5429                 return NETDEV_TX_BUSY;
5430         }
5431
5432         entry = tnapi->tx_prod;
5433         base_flags = 0;
5434         mss = 0;
5435         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5436                 int tcp_opt_len, ip_tcp_len;
5437                 u32 hdrlen;
5438
5439                 if (skb_header_cloned(skb) &&
5440                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5441                         dev_kfree_skb(skb);
5442                         goto out_unlock;
5443                 }
5444
5445                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5446                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5447                 else {
5448                         struct iphdr *iph = ip_hdr(skb);
5449
5450                         tcp_opt_len = tcp_optlen(skb);
5451                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5452
5453                         iph->check = 0;
5454                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5455                         hdrlen = ip_tcp_len + tcp_opt_len;
5456                 }
5457
5458                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5459                         mss |= (hdrlen & 0xc) << 12;
5460                         if (hdrlen & 0x10)
5461                                 base_flags |= 0x00000010;
5462                         base_flags |= (hdrlen & 0x3e0) << 5;
5463                 } else
5464                         mss |= hdrlen << 9;
5465
5466                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5467                                TXD_FLAG_CPU_POST_DMA);
5468
5469                 tcp_hdr(skb)->check = 0;
5470
5471         }
5472         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5473                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5474 #if TG3_VLAN_TAG_USED
5475         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5476                 base_flags |= (TXD_FLAG_VLAN |
5477                                (vlan_tx_tag_get(skb) << 16));
5478 #endif
5479
5480         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5481                 dev_kfree_skb(skb);
5482                 goto out_unlock;
5483         }
5484
5485         sp = skb_shinfo(skb);
5486
5487         mapping = sp->dma_head;
5488
5489         tnapi->tx_buffers[entry].skb = skb;
5490
5491         len = skb_headlen(skb);
5492
5493         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5494             !mss && skb->len > ETH_DATA_LEN)
5495                 base_flags |= TXD_FLAG_JMB_PKT;
5496
5497         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5498                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5499
5500         entry = NEXT_TX(entry);
5501
5502         /* Now loop through additional data fragments, and queue them. */
5503         if (skb_shinfo(skb)->nr_frags > 0) {
5504                 unsigned int i, last;
5505
5506                 last = skb_shinfo(skb)->nr_frags - 1;
5507                 for (i = 0; i <= last; i++) {
5508                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5509
5510                         len = frag->size;
5511                         mapping = sp->dma_maps[i];
5512                         tnapi->tx_buffers[entry].skb = NULL;
5513
5514                         tg3_set_txd(tnapi, entry, mapping, len,
5515                                     base_flags, (i == last) | (mss << 1));
5516
5517                         entry = NEXT_TX(entry);
5518                 }
5519         }
5520
5521         /* Packets are ready, update Tx producer idx local and on card. */
5522         tw32_tx_mbox(tnapi->prodmbox, entry);
5523
5524         tnapi->tx_prod = entry;
5525         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5526                 netif_tx_stop_queue(txq);
5527                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5528                         netif_tx_wake_queue(txq);
5529         }
5530
5531 out_unlock:
5532         mmiowb();
5533
5534         return NETDEV_TX_OK;
5535 }
5536
5537 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5538                                           struct net_device *);
5539
5540 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5541  * TSO header is greater than 80 bytes.
5542  */
5543 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5544 {
5545         struct sk_buff *segs, *nskb;
5546         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5547
5548         /* Estimate the number of fragments in the worst case */
5549         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5550                 netif_stop_queue(tp->dev);
5551                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5552                         return NETDEV_TX_BUSY;
5553
5554                 netif_wake_queue(tp->dev);
5555         }
5556
5557         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5558         if (IS_ERR(segs))
5559                 goto tg3_tso_bug_end;
5560
5561         do {
5562                 nskb = segs;
5563                 segs = segs->next;
5564                 nskb->next = NULL;
5565                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5566         } while (segs);
5567
5568 tg3_tso_bug_end:
5569         dev_kfree_skb(skb);
5570
5571         return NETDEV_TX_OK;
5572 }
5573
5574 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5575  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5576  */
5577 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5578                                           struct net_device *dev)
5579 {
5580         struct tg3 *tp = netdev_priv(dev);
5581         u32 len, entry, base_flags, mss;
5582         struct skb_shared_info *sp;
5583         int would_hit_hwbug;
5584         dma_addr_t mapping;
5585         struct tg3_napi *tnapi;
5586         struct netdev_queue *txq;
5587
5588         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5589         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5590         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5591                 tnapi++;
5592
5593         /* We are running in BH disabled context with netif_tx_lock
5594          * and TX reclaim runs via tp->napi.poll inside of a software
5595          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5596          * no IRQ context deadlocks to worry about either.  Rejoice!
5597          */
5598         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5599                 if (!netif_tx_queue_stopped(txq)) {
5600                         netif_tx_stop_queue(txq);
5601
5602                         /* This is a hard error, log it. */
5603                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5604                                "queue awake!\n", dev->name);
5605                 }
5606                 return NETDEV_TX_BUSY;
5607         }
5608
5609         entry = tnapi->tx_prod;
5610         base_flags = 0;
5611         if (skb->ip_summed == CHECKSUM_PARTIAL)
5612                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5613
5614         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5615                 struct iphdr *iph;
5616                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5617
5618                 if (skb_header_cloned(skb) &&
5619                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5620                         dev_kfree_skb(skb);
5621                         goto out_unlock;
5622                 }
5623
5624                 tcp_opt_len = tcp_optlen(skb);
5625                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5626
5627                 hdr_len = ip_tcp_len + tcp_opt_len;
5628                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5629                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5630                         return (tg3_tso_bug(tp, skb));
5631
5632                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5633                                TXD_FLAG_CPU_POST_DMA);
5634
5635                 iph = ip_hdr(skb);
5636                 iph->check = 0;
5637                 iph->tot_len = htons(mss + hdr_len);
5638                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5639                         tcp_hdr(skb)->check = 0;
5640                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5641                 } else
5642                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5643                                                                  iph->daddr, 0,
5644                                                                  IPPROTO_TCP,
5645                                                                  0);
5646
5647                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5648                         mss |= (hdr_len & 0xc) << 12;
5649                         if (hdr_len & 0x10)
5650                                 base_flags |= 0x00000010;
5651                         base_flags |= (hdr_len & 0x3e0) << 5;
5652                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5653                         mss |= hdr_len << 9;
5654                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5655                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5656                         if (tcp_opt_len || iph->ihl > 5) {
5657                                 int tsflags;
5658
5659                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5660                                 mss |= (tsflags << 11);
5661                         }
5662                 } else {
5663                         if (tcp_opt_len || iph->ihl > 5) {
5664                                 int tsflags;
5665
5666                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5667                                 base_flags |= tsflags << 12;
5668                         }
5669                 }
5670         }
5671 #if TG3_VLAN_TAG_USED
5672         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5673                 base_flags |= (TXD_FLAG_VLAN |
5674                                (vlan_tx_tag_get(skb) << 16));
5675 #endif
5676
5677         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5678             !mss && skb->len > ETH_DATA_LEN)
5679                 base_flags |= TXD_FLAG_JMB_PKT;
5680
5681         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5682                 dev_kfree_skb(skb);
5683                 goto out_unlock;
5684         }
5685
5686         sp = skb_shinfo(skb);
5687
5688         mapping = sp->dma_head;
5689
5690         tnapi->tx_buffers[entry].skb = skb;
5691
5692         would_hit_hwbug = 0;
5693
5694         len = skb_headlen(skb);
5695
5696         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5697                 would_hit_hwbug = 1;
5698
5699         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5700             tg3_4g_overflow_test(mapping, len))
5701                 would_hit_hwbug = 1;
5702
5703         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5704             tg3_40bit_overflow_test(tp, mapping, len))
5705                 would_hit_hwbug = 1;
5706
5707         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5708                 would_hit_hwbug = 1;
5709
5710         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5711                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5712
5713         entry = NEXT_TX(entry);
5714
5715         /* Now loop through additional data fragments, and queue them. */
5716         if (skb_shinfo(skb)->nr_frags > 0) {
5717                 unsigned int i, last;
5718
5719                 last = skb_shinfo(skb)->nr_frags - 1;
5720                 for (i = 0; i <= last; i++) {
5721                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5722
5723                         len = frag->size;
5724                         mapping = sp->dma_maps[i];
5725
5726                         tnapi->tx_buffers[entry].skb = NULL;
5727
5728                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5729                             len <= 8)
5730                                 would_hit_hwbug = 1;
5731
5732                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5733                             tg3_4g_overflow_test(mapping, len))
5734                                 would_hit_hwbug = 1;
5735
5736                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5737                             tg3_40bit_overflow_test(tp, mapping, len))
5738                                 would_hit_hwbug = 1;
5739
5740                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5741                                 tg3_set_txd(tnapi, entry, mapping, len,
5742                                             base_flags, (i == last)|(mss << 1));
5743                         else
5744                                 tg3_set_txd(tnapi, entry, mapping, len,
5745                                             base_flags, (i == last));
5746
5747                         entry = NEXT_TX(entry);
5748                 }
5749         }
5750
5751         if (would_hit_hwbug) {
5752                 u32 last_plus_one = entry;
5753                 u32 start;
5754
5755                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5756                 start &= (TG3_TX_RING_SIZE - 1);
5757
5758                 /* If the workaround fails due to memory/mapping
5759                  * failure, silently drop this packet.
5760                  */
5761                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5762                                                 &start, base_flags, mss))
5763                         goto out_unlock;
5764
5765                 entry = start;
5766         }
5767
5768         /* Packets are ready, update Tx producer idx local and on card. */
5769         tw32_tx_mbox(tnapi->prodmbox, entry);
5770
5771         tnapi->tx_prod = entry;
5772         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5773                 netif_tx_stop_queue(txq);
5774                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5775                         netif_tx_wake_queue(txq);
5776         }
5777
5778 out_unlock:
5779         mmiowb();
5780
5781         return NETDEV_TX_OK;
5782 }
5783
5784 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5785                                int new_mtu)
5786 {
5787         dev->mtu = new_mtu;
5788
5789         if (new_mtu > ETH_DATA_LEN) {
5790                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5791                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5792                         ethtool_op_set_tso(dev, 0);
5793                 }
5794                 else
5795                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5796         } else {
5797                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5798                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5799                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5800         }
5801 }
5802
5803 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5804 {
5805         struct tg3 *tp = netdev_priv(dev);
5806         int err;
5807
5808         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5809                 return -EINVAL;
5810
5811         if (!netif_running(dev)) {
5812                 /* We'll just catch it later when the
5813                  * device is up'd.
5814                  */
5815                 tg3_set_mtu(dev, tp, new_mtu);
5816                 return 0;
5817         }
5818
5819         tg3_phy_stop(tp);
5820
5821         tg3_netif_stop(tp);
5822
5823         tg3_full_lock(tp, 1);
5824
5825         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5826
5827         tg3_set_mtu(dev, tp, new_mtu);
5828
5829         err = tg3_restart_hw(tp, 0);
5830
5831         if (!err)
5832                 tg3_netif_start(tp);
5833
5834         tg3_full_unlock(tp);
5835
5836         if (!err)
5837                 tg3_phy_start(tp);
5838
5839         return err;
5840 }
5841
5842 static void tg3_rx_prodring_free(struct tg3 *tp,
5843                                  struct tg3_rx_prodring_set *tpr)
5844 {
5845         int i;
5846
5847         if (tpr != &tp->prodring[0]) {
5848                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5849                      i = (i + 1) % TG3_RX_RING_SIZE)
5850                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5851                                         tp->rx_pkt_map_sz);
5852
5853                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5854                         for (i = tpr->rx_jmb_cons_idx;
5855                              i != tpr->rx_jmb_prod_idx;
5856                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5857                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5858                                                 TG3_RX_JMB_MAP_SZ);
5859                         }
5860                 }
5861
5862                 return;
5863         }
5864
5865         for (i = 0; i < TG3_RX_RING_SIZE; i++)
5866                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5867                                 tp->rx_pkt_map_sz);
5868
5869         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5870                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5871                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5872                                         TG3_RX_JMB_MAP_SZ);
5873         }
5874 }
5875
5876 /* Initialize tx/rx rings for packet processing.
5877  *
5878  * The chip has been shut down and the driver detached from
5879  * the networking, so no interrupts or new tx packets will
5880  * end up in the driver.  tp->{tx,}lock are held and thus
5881  * we may not sleep.
5882  */
5883 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5884                                  struct tg3_rx_prodring_set *tpr)
5885 {
5886         u32 i, rx_pkt_dma_sz;
5887
5888         tpr->rx_std_cons_idx = 0;
5889         tpr->rx_std_prod_idx = 0;
5890         tpr->rx_jmb_cons_idx = 0;
5891         tpr->rx_jmb_prod_idx = 0;
5892
5893         if (tpr != &tp->prodring[0]) {
5894                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5895                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5896                         memset(&tpr->rx_jmb_buffers[0], 0,
5897                                TG3_RX_JMB_BUFF_RING_SIZE);
5898                 goto done;
5899         }
5900
5901         /* Zero out all descriptors. */
5902         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5903
5904         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5905         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5906             tp->dev->mtu > ETH_DATA_LEN)
5907                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5908         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5909
5910         /* Initialize invariants of the rings, we only set this
5911          * stuff once.  This works because the card does not
5912          * write into the rx buffer posting rings.
5913          */
5914         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5915                 struct tg3_rx_buffer_desc *rxd;
5916
5917                 rxd = &tpr->rx_std[i];
5918                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5919                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5920                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5921                                (i << RXD_OPAQUE_INDEX_SHIFT));
5922         }
5923
5924         /* Now allocate fresh SKBs for each rx ring. */
5925         for (i = 0; i < tp->rx_pending; i++) {
5926                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
5927                         printk(KERN_WARNING PFX
5928                                "%s: Using a smaller RX standard ring, "
5929                                "only %d out of %d buffers were allocated "
5930                                "successfully.\n",
5931                                tp->dev->name, i, tp->rx_pending);
5932                         if (i == 0)
5933                                 goto initfail;
5934                         tp->rx_pending = i;
5935                         break;
5936                 }
5937         }
5938
5939         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5940                 goto done;
5941
5942         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5943
5944         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5945                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5946                         struct tg3_rx_buffer_desc *rxd;
5947
5948                         rxd = &tpr->rx_jmb[i].std;
5949                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5950                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5951                                 RXD_FLAG_JUMBO;
5952                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5953                                (i << RXD_OPAQUE_INDEX_SHIFT));
5954                 }
5955
5956                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5957                         if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
5958                                              i) < 0) {
5959                                 printk(KERN_WARNING PFX
5960                                        "%s: Using a smaller RX jumbo ring, "
5961                                        "only %d out of %d buffers were "
5962                                        "allocated successfully.\n",
5963                                        tp->dev->name, i, tp->rx_jumbo_pending);
5964                                 if (i == 0)
5965                                         goto initfail;
5966                                 tp->rx_jumbo_pending = i;
5967                                 break;
5968                         }
5969                 }
5970         }
5971
5972 done:
5973         return 0;
5974
5975 initfail:
5976         tg3_rx_prodring_free(tp, tpr);
5977         return -ENOMEM;
5978 }
5979
5980 static void tg3_rx_prodring_fini(struct tg3 *tp,
5981                                  struct tg3_rx_prodring_set *tpr)
5982 {
5983         kfree(tpr->rx_std_buffers);
5984         tpr->rx_std_buffers = NULL;
5985         kfree(tpr->rx_jmb_buffers);
5986         tpr->rx_jmb_buffers = NULL;
5987         if (tpr->rx_std) {
5988                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5989                                     tpr->rx_std, tpr->rx_std_mapping);
5990                 tpr->rx_std = NULL;
5991         }
5992         if (tpr->rx_jmb) {
5993                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5994                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5995                 tpr->rx_jmb = NULL;
5996         }
5997 }
5998
5999 static int tg3_rx_prodring_init(struct tg3 *tp,
6000                                 struct tg3_rx_prodring_set *tpr)
6001 {
6002         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6003         if (!tpr->rx_std_buffers)
6004                 return -ENOMEM;
6005
6006         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6007                                            &tpr->rx_std_mapping);
6008         if (!tpr->rx_std)
6009                 goto err_out;
6010
6011         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6012                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6013                                               GFP_KERNEL);
6014                 if (!tpr->rx_jmb_buffers)
6015                         goto err_out;
6016
6017                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6018                                                    TG3_RX_JUMBO_RING_BYTES,
6019                                                    &tpr->rx_jmb_mapping);
6020                 if (!tpr->rx_jmb)
6021                         goto err_out;
6022         }
6023
6024         return 0;
6025
6026 err_out:
6027         tg3_rx_prodring_fini(tp, tpr);
6028         return -ENOMEM;
6029 }
6030
6031 /* Free up pending packets in all rx/tx rings.
6032  *
6033  * The chip has been shut down and the driver detached from
6034  * the networking, so no interrupts or new tx packets will
6035  * end up in the driver.  tp->{tx,}lock is not held and we are not
6036  * in an interrupt context and thus may sleep.
6037  */
6038 static void tg3_free_rings(struct tg3 *tp)
6039 {
6040         int i, j;
6041
6042         for (j = 0; j < tp->irq_cnt; j++) {
6043                 struct tg3_napi *tnapi = &tp->napi[j];
6044
6045                 if (!tnapi->tx_buffers)
6046                         continue;
6047
6048                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6049                         struct tx_ring_info *txp;
6050                         struct sk_buff *skb;
6051
6052                         txp = &tnapi->tx_buffers[i];
6053                         skb = txp->skb;
6054
6055                         if (skb == NULL) {
6056                                 i++;
6057                                 continue;
6058                         }
6059
6060                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
6061
6062                         txp->skb = NULL;
6063
6064                         i += skb_shinfo(skb)->nr_frags + 1;
6065
6066                         dev_kfree_skb_any(skb);
6067                 }
6068
6069                 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6070                         tg3_rx_prodring_free(tp, &tp->prodring[j]);
6071         }
6072 }
6073
6074 /* Initialize tx/rx rings for packet processing.
6075  *
6076  * The chip has been shut down and the driver detached from
6077  * the networking, so no interrupts or new tx packets will
6078  * end up in the driver.  tp->{tx,}lock are held and thus
6079  * we may not sleep.
6080  */
6081 static int tg3_init_rings(struct tg3 *tp)
6082 {
6083         int i;
6084
6085         /* Free up all the SKBs. */
6086         tg3_free_rings(tp);
6087
6088         for (i = 0; i < tp->irq_cnt; i++) {
6089                 struct tg3_napi *tnapi = &tp->napi[i];
6090
6091                 tnapi->last_tag = 0;
6092                 tnapi->last_irq_tag = 0;
6093                 tnapi->hw_status->status = 0;
6094                 tnapi->hw_status->status_tag = 0;
6095                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6096
6097                 tnapi->tx_prod = 0;
6098                 tnapi->tx_cons = 0;
6099                 if (tnapi->tx_ring)
6100                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6101
6102                 tnapi->rx_rcb_ptr = 0;
6103                 if (tnapi->rx_rcb)
6104                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6105
6106                 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6107                         tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6108                         return -ENOMEM;
6109         }
6110
6111         return 0;
6112 }
6113
6114 /*
6115  * Must not be invoked with interrupt sources disabled and
6116  * the hardware shutdown down.
6117  */
6118 static void tg3_free_consistent(struct tg3 *tp)
6119 {
6120         int i;
6121
6122         for (i = 0; i < tp->irq_cnt; i++) {
6123                 struct tg3_napi *tnapi = &tp->napi[i];
6124
6125                 if (tnapi->tx_ring) {
6126                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6127                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6128                         tnapi->tx_ring = NULL;
6129                 }
6130
6131                 kfree(tnapi->tx_buffers);
6132                 tnapi->tx_buffers = NULL;
6133
6134                 if (tnapi->rx_rcb) {
6135                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6136                                             tnapi->rx_rcb,
6137                                             tnapi->rx_rcb_mapping);
6138                         tnapi->rx_rcb = NULL;
6139                 }
6140
6141                 if (tnapi->hw_status) {
6142                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6143                                             tnapi->hw_status,
6144                                             tnapi->status_mapping);
6145                         tnapi->hw_status = NULL;
6146                 }
6147         }
6148
6149         if (tp->hw_stats) {
6150                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6151                                     tp->hw_stats, tp->stats_mapping);
6152                 tp->hw_stats = NULL;
6153         }
6154
6155         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6156                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6157 }
6158
6159 /*
6160  * Must not be invoked with interrupt sources disabled and
6161  * the hardware shutdown down.  Can sleep.
6162  */
6163 static int tg3_alloc_consistent(struct tg3 *tp)
6164 {
6165         int i;
6166
6167         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6168                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6169                         goto err_out;
6170         }
6171
6172         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6173                                             sizeof(struct tg3_hw_stats),
6174                                             &tp->stats_mapping);
6175         if (!tp->hw_stats)
6176                 goto err_out;
6177
6178         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6179
6180         for (i = 0; i < tp->irq_cnt; i++) {
6181                 struct tg3_napi *tnapi = &tp->napi[i];
6182                 struct tg3_hw_status *sblk;
6183
6184                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6185                                                         TG3_HW_STATUS_SIZE,
6186                                                         &tnapi->status_mapping);
6187                 if (!tnapi->hw_status)
6188                         goto err_out;
6189
6190                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6191                 sblk = tnapi->hw_status;
6192
6193                 /*
6194                  * When RSS is enabled, the status block format changes
6195                  * slightly.  The "rx_jumbo_consumer", "reserved",
6196                  * and "rx_mini_consumer" members get mapped to the
6197                  * other three rx return ring producer indexes.
6198                  */
6199                 switch (i) {
6200                 default:
6201                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6202                         break;
6203                 case 2:
6204                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6205                         break;
6206                 case 3:
6207                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6208                         break;
6209                 case 4:
6210                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6211                         break;
6212                 }
6213
6214                 if (tp->irq_cnt == 1)
6215                         tnapi->prodring = &tp->prodring[0];
6216                 else if (i)
6217                         tnapi->prodring = &tp->prodring[i - 1];
6218
6219                 /*
6220                  * If multivector RSS is enabled, vector 0 does not handle
6221                  * rx or tx interrupts.  Don't allocate any resources for it.
6222                  */
6223                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6224                         continue;
6225
6226                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6227                                                      TG3_RX_RCB_RING_BYTES(tp),
6228                                                      &tnapi->rx_rcb_mapping);
6229                 if (!tnapi->rx_rcb)
6230                         goto err_out;
6231
6232                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6233
6234                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6235                                             TG3_TX_RING_SIZE, GFP_KERNEL);
6236                 if (!tnapi->tx_buffers)
6237                         goto err_out;
6238
6239                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6240                                                       TG3_TX_RING_BYTES,
6241                                                       &tnapi->tx_desc_mapping);
6242                 if (!tnapi->tx_ring)
6243                         goto err_out;
6244         }
6245
6246         return 0;
6247
6248 err_out:
6249         tg3_free_consistent(tp);
6250         return -ENOMEM;
6251 }
6252
6253 #define MAX_WAIT_CNT 1000
6254
6255 /* To stop a block, clear the enable bit and poll till it
6256  * clears.  tp->lock is held.
6257  */
6258 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6259 {
6260         unsigned int i;
6261         u32 val;
6262
6263         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6264                 switch (ofs) {
6265                 case RCVLSC_MODE:
6266                 case DMAC_MODE:
6267                 case MBFREE_MODE:
6268                 case BUFMGR_MODE:
6269                 case MEMARB_MODE:
6270                         /* We can't enable/disable these bits of the
6271                          * 5705/5750, just say success.
6272                          */
6273                         return 0;
6274
6275                 default:
6276                         break;
6277                 }
6278         }
6279
6280         val = tr32(ofs);
6281         val &= ~enable_bit;
6282         tw32_f(ofs, val);
6283
6284         for (i = 0; i < MAX_WAIT_CNT; i++) {
6285                 udelay(100);
6286                 val = tr32(ofs);
6287                 if ((val & enable_bit) == 0)
6288                         break;
6289         }
6290
6291         if (i == MAX_WAIT_CNT && !silent) {
6292                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6293                        "ofs=%lx enable_bit=%x\n",
6294                        ofs, enable_bit);
6295                 return -ENODEV;
6296         }
6297
6298         return 0;
6299 }
6300
6301 /* tp->lock is held. */
6302 static int tg3_abort_hw(struct tg3 *tp, int silent)
6303 {
6304         int i, err;
6305
6306         tg3_disable_ints(tp);
6307
6308         tp->rx_mode &= ~RX_MODE_ENABLE;
6309         tw32_f(MAC_RX_MODE, tp->rx_mode);
6310         udelay(10);
6311
6312         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6313         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6314         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6315         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6316         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6317         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6318
6319         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6320         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6321         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6322         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6323         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6324         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6325         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6326
6327         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6328         tw32_f(MAC_MODE, tp->mac_mode);
6329         udelay(40);
6330
6331         tp->tx_mode &= ~TX_MODE_ENABLE;
6332         tw32_f(MAC_TX_MODE, tp->tx_mode);
6333
6334         for (i = 0; i < MAX_WAIT_CNT; i++) {
6335                 udelay(100);
6336                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6337                         break;
6338         }
6339         if (i >= MAX_WAIT_CNT) {
6340                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6341                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6342                        tp->dev->name, tr32(MAC_TX_MODE));
6343                 err |= -ENODEV;
6344         }
6345
6346         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6347         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6348         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6349
6350         tw32(FTQ_RESET, 0xffffffff);
6351         tw32(FTQ_RESET, 0x00000000);
6352
6353         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6354         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6355
6356         for (i = 0; i < tp->irq_cnt; i++) {
6357                 struct tg3_napi *tnapi = &tp->napi[i];
6358                 if (tnapi->hw_status)
6359                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6360         }
6361         if (tp->hw_stats)
6362                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6363
6364         return err;
6365 }
6366
6367 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6368 {
6369         int i;
6370         u32 apedata;
6371
6372         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6373         if (apedata != APE_SEG_SIG_MAGIC)
6374                 return;
6375
6376         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6377         if (!(apedata & APE_FW_STATUS_READY))
6378                 return;
6379
6380         /* Wait for up to 1 millisecond for APE to service previous event. */
6381         for (i = 0; i < 10; i++) {
6382                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6383                         return;
6384
6385                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6386
6387                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6388                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6389                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6390
6391                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6392
6393                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6394                         break;
6395
6396                 udelay(100);
6397         }
6398
6399         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6400                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6401 }
6402
6403 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6404 {
6405         u32 event;
6406         u32 apedata;
6407
6408         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6409                 return;
6410
6411         switch (kind) {
6412                 case RESET_KIND_INIT:
6413                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6414                                         APE_HOST_SEG_SIG_MAGIC);
6415                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6416                                         APE_HOST_SEG_LEN_MAGIC);
6417                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6418                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6419                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6420                                         APE_HOST_DRIVER_ID_MAGIC);
6421                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6422                                         APE_HOST_BEHAV_NO_PHYLOCK);
6423
6424                         event = APE_EVENT_STATUS_STATE_START;
6425                         break;
6426                 case RESET_KIND_SHUTDOWN:
6427                         /* With the interface we are currently using,
6428                          * APE does not track driver state.  Wiping
6429                          * out the HOST SEGMENT SIGNATURE forces
6430                          * the APE to assume OS absent status.
6431                          */
6432                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6433
6434                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6435                         break;
6436                 case RESET_KIND_SUSPEND:
6437                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6438                         break;
6439                 default:
6440                         return;
6441         }
6442
6443         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6444
6445         tg3_ape_send_event(tp, event);
6446 }
6447
6448 /* tp->lock is held. */
6449 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6450 {
6451         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6452                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6453
6454         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6455                 switch (kind) {
6456                 case RESET_KIND_INIT:
6457                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6458                                       DRV_STATE_START);
6459                         break;
6460
6461                 case RESET_KIND_SHUTDOWN:
6462                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6463                                       DRV_STATE_UNLOAD);
6464                         break;
6465
6466                 case RESET_KIND_SUSPEND:
6467                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6468                                       DRV_STATE_SUSPEND);
6469                         break;
6470
6471                 default:
6472                         break;
6473                 }
6474         }
6475
6476         if (kind == RESET_KIND_INIT ||
6477             kind == RESET_KIND_SUSPEND)
6478                 tg3_ape_driver_state_change(tp, kind);
6479 }
6480
6481 /* tp->lock is held. */
6482 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6483 {
6484         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6485                 switch (kind) {
6486                 case RESET_KIND_INIT:
6487                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6488                                       DRV_STATE_START_DONE);
6489                         break;
6490
6491                 case RESET_KIND_SHUTDOWN:
6492                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6493                                       DRV_STATE_UNLOAD_DONE);
6494                         break;
6495
6496                 default:
6497                         break;
6498                 }
6499         }
6500
6501         if (kind == RESET_KIND_SHUTDOWN)
6502                 tg3_ape_driver_state_change(tp, kind);
6503 }
6504
6505 /* tp->lock is held. */
6506 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6507 {
6508         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6509                 switch (kind) {
6510                 case RESET_KIND_INIT:
6511                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6512                                       DRV_STATE_START);
6513                         break;
6514
6515                 case RESET_KIND_SHUTDOWN:
6516                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6517                                       DRV_STATE_UNLOAD);
6518                         break;
6519
6520                 case RESET_KIND_SUSPEND:
6521                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6522                                       DRV_STATE_SUSPEND);
6523                         break;
6524
6525                 default:
6526                         break;
6527                 }
6528         }
6529 }
6530
6531 static int tg3_poll_fw(struct tg3 *tp)
6532 {
6533         int i;
6534         u32 val;
6535
6536         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6537                 /* Wait up to 20ms for init done. */
6538                 for (i = 0; i < 200; i++) {
6539                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6540                                 return 0;
6541                         udelay(100);
6542                 }
6543                 return -ENODEV;
6544         }
6545
6546         /* Wait for firmware initialization to complete. */
6547         for (i = 0; i < 100000; i++) {
6548                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6549                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6550                         break;
6551                 udelay(10);
6552         }
6553
6554         /* Chip might not be fitted with firmware.  Some Sun onboard
6555          * parts are configured like that.  So don't signal the timeout
6556          * of the above loop as an error, but do report the lack of
6557          * running firmware once.
6558          */
6559         if (i >= 100000 &&
6560             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6561                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6562
6563                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6564                        tp->dev->name);
6565         }
6566
6567         return 0;
6568 }
6569
6570 /* Save PCI command register before chip reset */
6571 static void tg3_save_pci_state(struct tg3 *tp)
6572 {
6573         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6574 }
6575
6576 /* Restore PCI state after chip reset */
6577 static void tg3_restore_pci_state(struct tg3 *tp)
6578 {
6579         u32 val;
6580
6581         /* Re-enable indirect register accesses. */
6582         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6583                                tp->misc_host_ctrl);
6584
6585         /* Set MAX PCI retry to zero. */
6586         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6587         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6588             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6589                 val |= PCISTATE_RETRY_SAME_DMA;
6590         /* Allow reads and writes to the APE register and memory space. */
6591         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6592                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6593                        PCISTATE_ALLOW_APE_SHMEM_WR;
6594         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6595
6596         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6597
6598         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6599                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6600                         pcie_set_readrq(tp->pdev, 4096);
6601                 else {
6602                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6603                                               tp->pci_cacheline_sz);
6604                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6605                                               tp->pci_lat_timer);
6606                 }
6607         }
6608
6609         /* Make sure PCI-X relaxed ordering bit is clear. */
6610         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6611                 u16 pcix_cmd;
6612
6613                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6614                                      &pcix_cmd);
6615                 pcix_cmd &= ~PCI_X_CMD_ERO;
6616                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6617                                       pcix_cmd);
6618         }
6619
6620         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6621
6622                 /* Chip reset on 5780 will reset MSI enable bit,
6623                  * so need to restore it.
6624                  */
6625                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6626                         u16 ctrl;
6627
6628                         pci_read_config_word(tp->pdev,
6629                                              tp->msi_cap + PCI_MSI_FLAGS,
6630                                              &ctrl);
6631                         pci_write_config_word(tp->pdev,
6632                                               tp->msi_cap + PCI_MSI_FLAGS,
6633                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6634                         val = tr32(MSGINT_MODE);
6635                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6636                 }
6637         }
6638 }
6639
6640 static void tg3_stop_fw(struct tg3 *);
6641
6642 /* tp->lock is held. */
6643 static int tg3_chip_reset(struct tg3 *tp)
6644 {
6645         u32 val;
6646         void (*write_op)(struct tg3 *, u32, u32);
6647         int i, err;
6648
6649         tg3_nvram_lock(tp);
6650
6651         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6652
6653         /* No matching tg3_nvram_unlock() after this because
6654          * chip reset below will undo the nvram lock.
6655          */
6656         tp->nvram_lock_cnt = 0;
6657
6658         /* GRC_MISC_CFG core clock reset will clear the memory
6659          * enable bit in PCI register 4 and the MSI enable bit
6660          * on some chips, so we save relevant registers here.
6661          */
6662         tg3_save_pci_state(tp);
6663
6664         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6665             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6666                 tw32(GRC_FASTBOOT_PC, 0);
6667
6668         /*
6669          * We must avoid the readl() that normally takes place.
6670          * It locks machines, causes machine checks, and other
6671          * fun things.  So, temporarily disable the 5701
6672          * hardware workaround, while we do the reset.
6673          */
6674         write_op = tp->write32;
6675         if (write_op == tg3_write_flush_reg32)
6676                 tp->write32 = tg3_write32;
6677
6678         /* Prevent the irq handler from reading or writing PCI registers
6679          * during chip reset when the memory enable bit in the PCI command
6680          * register may be cleared.  The chip does not generate interrupt
6681          * at this time, but the irq handler may still be called due to irq
6682          * sharing or irqpoll.
6683          */
6684         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6685         for (i = 0; i < tp->irq_cnt; i++) {
6686                 struct tg3_napi *tnapi = &tp->napi[i];
6687                 if (tnapi->hw_status) {
6688                         tnapi->hw_status->status = 0;
6689                         tnapi->hw_status->status_tag = 0;
6690                 }
6691                 tnapi->last_tag = 0;
6692                 tnapi->last_irq_tag = 0;
6693         }
6694         smp_mb();
6695
6696         for (i = 0; i < tp->irq_cnt; i++)
6697                 synchronize_irq(tp->napi[i].irq_vec);
6698
6699         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6700                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6701                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6702         }
6703
6704         /* do the reset */
6705         val = GRC_MISC_CFG_CORECLK_RESET;
6706
6707         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6708                 if (tr32(0x7e2c) == 0x60) {
6709                         tw32(0x7e2c, 0x20);
6710                 }
6711                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6712                         tw32(GRC_MISC_CFG, (1 << 29));
6713                         val |= (1 << 29);
6714                 }
6715         }
6716
6717         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6718                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6719                 tw32(GRC_VCPU_EXT_CTRL,
6720                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6721         }
6722
6723         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6724                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6725         tw32(GRC_MISC_CFG, val);
6726
6727         /* restore 5701 hardware bug workaround write method */
6728         tp->write32 = write_op;
6729
6730         /* Unfortunately, we have to delay before the PCI read back.
6731          * Some 575X chips even will not respond to a PCI cfg access
6732          * when the reset command is given to the chip.
6733          *
6734          * How do these hardware designers expect things to work
6735          * properly if the PCI write is posted for a long period
6736          * of time?  It is always necessary to have some method by
6737          * which a register read back can occur to push the write
6738          * out which does the reset.
6739          *
6740          * For most tg3 variants the trick below was working.
6741          * Ho hum...
6742          */
6743         udelay(120);
6744
6745         /* Flush PCI posted writes.  The normal MMIO registers
6746          * are inaccessible at this time so this is the only
6747          * way to make this reliably (actually, this is no longer
6748          * the case, see above).  I tried to use indirect
6749          * register read/write but this upset some 5701 variants.
6750          */
6751         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6752
6753         udelay(120);
6754
6755         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6756                 u16 val16;
6757
6758                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6759                         int i;
6760                         u32 cfg_val;
6761
6762                         /* Wait for link training to complete.  */
6763                         for (i = 0; i < 5000; i++)
6764                                 udelay(100);
6765
6766                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6767                         pci_write_config_dword(tp->pdev, 0xc4,
6768                                                cfg_val | (1 << 15));
6769                 }
6770
6771                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6772                 pci_read_config_word(tp->pdev,
6773                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6774                                      &val16);
6775                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6776                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6777                 /*
6778                  * Older PCIe devices only support the 128 byte
6779                  * MPS setting.  Enforce the restriction.
6780                  */
6781                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6782                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6783                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6784                 pci_write_config_word(tp->pdev,
6785                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6786                                       val16);
6787
6788                 pcie_set_readrq(tp->pdev, 4096);
6789
6790                 /* Clear error status */
6791                 pci_write_config_word(tp->pdev,
6792                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6793                                       PCI_EXP_DEVSTA_CED |
6794                                       PCI_EXP_DEVSTA_NFED |
6795                                       PCI_EXP_DEVSTA_FED |
6796                                       PCI_EXP_DEVSTA_URD);
6797         }
6798
6799         tg3_restore_pci_state(tp);
6800
6801         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6802
6803         val = 0;
6804         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6805                 val = tr32(MEMARB_MODE);
6806         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6807
6808         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6809                 tg3_stop_fw(tp);
6810                 tw32(0x5000, 0x400);
6811         }
6812
6813         tw32(GRC_MODE, tp->grc_mode);
6814
6815         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6816                 val = tr32(0xc4);
6817
6818                 tw32(0xc4, val | (1 << 15));
6819         }
6820
6821         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6822             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6823                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6824                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6825                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6826                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6827         }
6828
6829         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6830                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6831                 tw32_f(MAC_MODE, tp->mac_mode);
6832         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6833                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6834                 tw32_f(MAC_MODE, tp->mac_mode);
6835         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6836                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6837                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6838                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6839                 tw32_f(MAC_MODE, tp->mac_mode);
6840         } else
6841                 tw32_f(MAC_MODE, 0);
6842         udelay(40);
6843
6844         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6845
6846         err = tg3_poll_fw(tp);
6847         if (err)
6848                 return err;
6849
6850         tg3_mdio_start(tp);
6851
6852         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6853                 u8 phy_addr;
6854
6855                 phy_addr = tp->phy_addr;
6856                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6857
6858                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6859                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6860                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6861                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6862                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6863                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6864                 udelay(10);
6865
6866                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6867                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6868                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6869                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6870                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6871                 udelay(10);
6872
6873                 tp->phy_addr = phy_addr;
6874         }
6875
6876         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6877             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6878             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6879             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6880                 val = tr32(0x7c00);
6881
6882                 tw32(0x7c00, val | (1 << 25));
6883         }
6884
6885         /* Reprobe ASF enable state.  */
6886         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6887         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6888         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6889         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6890                 u32 nic_cfg;
6891
6892                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6893                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6894                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6895                         tp->last_event_jiffies = jiffies;
6896                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6897                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6898                 }
6899         }
6900
6901         return 0;
6902 }
6903
6904 /* tp->lock is held. */
6905 static void tg3_stop_fw(struct tg3 *tp)
6906 {
6907         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6908            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6909                 /* Wait for RX cpu to ACK the previous event. */
6910                 tg3_wait_for_event_ack(tp);
6911
6912                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6913
6914                 tg3_generate_fw_event(tp);
6915
6916                 /* Wait for RX cpu to ACK this event. */
6917                 tg3_wait_for_event_ack(tp);
6918         }
6919 }
6920
6921 /* tp->lock is held. */
6922 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6923 {
6924         int err;
6925
6926         tg3_stop_fw(tp);
6927
6928         tg3_write_sig_pre_reset(tp, kind);
6929
6930         tg3_abort_hw(tp, silent);
6931         err = tg3_chip_reset(tp);
6932
6933         __tg3_set_mac_addr(tp, 0);
6934
6935         tg3_write_sig_legacy(tp, kind);
6936         tg3_write_sig_post_reset(tp, kind);
6937
6938         if (err)
6939                 return err;
6940
6941         return 0;
6942 }
6943
6944 #define RX_CPU_SCRATCH_BASE     0x30000
6945 #define RX_CPU_SCRATCH_SIZE     0x04000
6946 #define TX_CPU_SCRATCH_BASE     0x34000
6947 #define TX_CPU_SCRATCH_SIZE     0x04000
6948
6949 /* tp->lock is held. */
6950 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6951 {
6952         int i;
6953
6954         BUG_ON(offset == TX_CPU_BASE &&
6955             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6956
6957         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6958                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6959
6960                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6961                 return 0;
6962         }
6963         if (offset == RX_CPU_BASE) {
6964                 for (i = 0; i < 10000; i++) {
6965                         tw32(offset + CPU_STATE, 0xffffffff);
6966                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6967                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6968                                 break;
6969                 }
6970
6971                 tw32(offset + CPU_STATE, 0xffffffff);
6972                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6973                 udelay(10);
6974         } else {
6975                 for (i = 0; i < 10000; i++) {
6976                         tw32(offset + CPU_STATE, 0xffffffff);
6977                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6978                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6979                                 break;
6980                 }
6981         }
6982
6983         if (i >= 10000) {
6984                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6985                        "and %s CPU\n",
6986                        tp->dev->name,
6987                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6988                 return -ENODEV;
6989         }
6990
6991         /* Clear firmware's nvram arbitration. */
6992         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6993                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6994         return 0;
6995 }
6996
6997 struct fw_info {
6998         unsigned int fw_base;
6999         unsigned int fw_len;
7000         const __be32 *fw_data;
7001 };
7002
7003 /* tp->lock is held. */
7004 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7005                                  int cpu_scratch_size, struct fw_info *info)
7006 {
7007         int err, lock_err, i;
7008         void (*write_op)(struct tg3 *, u32, u32);
7009
7010         if (cpu_base == TX_CPU_BASE &&
7011             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7012                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7013                        "TX cpu firmware on %s which is 5705.\n",
7014                        tp->dev->name);
7015                 return -EINVAL;
7016         }
7017
7018         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7019                 write_op = tg3_write_mem;
7020         else
7021                 write_op = tg3_write_indirect_reg32;
7022
7023         /* It is possible that bootcode is still loading at this point.
7024          * Get the nvram lock first before halting the cpu.
7025          */
7026         lock_err = tg3_nvram_lock(tp);
7027         err = tg3_halt_cpu(tp, cpu_base);
7028         if (!lock_err)
7029                 tg3_nvram_unlock(tp);
7030         if (err)
7031                 goto out;
7032
7033         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7034                 write_op(tp, cpu_scratch_base + i, 0);
7035         tw32(cpu_base + CPU_STATE, 0xffffffff);
7036         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7037         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7038                 write_op(tp, (cpu_scratch_base +
7039                               (info->fw_base & 0xffff) +
7040                               (i * sizeof(u32))),
7041                               be32_to_cpu(info->fw_data[i]));
7042
7043         err = 0;
7044
7045 out:
7046         return err;
7047 }
7048
7049 /* tp->lock is held. */
7050 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7051 {
7052         struct fw_info info;
7053         const __be32 *fw_data;
7054         int err, i;
7055
7056         fw_data = (void *)tp->fw->data;
7057
7058         /* Firmware blob starts with version numbers, followed by
7059            start address and length. We are setting complete length.
7060            length = end_address_of_bss - start_address_of_text.
7061            Remainder is the blob to be loaded contiguously
7062            from start address. */
7063
7064         info.fw_base = be32_to_cpu(fw_data[1]);
7065         info.fw_len = tp->fw->size - 12;
7066         info.fw_data = &fw_data[3];
7067
7068         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7069                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7070                                     &info);
7071         if (err)
7072                 return err;
7073
7074         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7075                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7076                                     &info);
7077         if (err)
7078                 return err;
7079
7080         /* Now startup only the RX cpu. */
7081         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7082         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7083
7084         for (i = 0; i < 5; i++) {
7085                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7086                         break;
7087                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7088                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7089                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7090                 udelay(1000);
7091         }
7092         if (i >= 5) {
7093                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7094                        "to set RX CPU PC, is %08x should be %08x\n",
7095                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7096                        info.fw_base);
7097                 return -ENODEV;
7098         }
7099         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7100         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7101
7102         return 0;
7103 }
7104
7105 /* 5705 needs a special version of the TSO firmware.  */
7106
7107 /* tp->lock is held. */
7108 static int tg3_load_tso_firmware(struct tg3 *tp)
7109 {
7110         struct fw_info info;
7111         const __be32 *fw_data;
7112         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7113         int err, i;
7114
7115         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7116                 return 0;
7117
7118         fw_data = (void *)tp->fw->data;
7119
7120         /* Firmware blob starts with version numbers, followed by
7121            start address and length. We are setting complete length.
7122            length = end_address_of_bss - start_address_of_text.
7123            Remainder is the blob to be loaded contiguously
7124            from start address. */
7125
7126         info.fw_base = be32_to_cpu(fw_data[1]);
7127         cpu_scratch_size = tp->fw_len;
7128         info.fw_len = tp->fw->size - 12;
7129         info.fw_data = &fw_data[3];
7130
7131         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7132                 cpu_base = RX_CPU_BASE;
7133                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7134         } else {
7135                 cpu_base = TX_CPU_BASE;
7136                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7137                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7138         }
7139
7140         err = tg3_load_firmware_cpu(tp, cpu_base,
7141                                     cpu_scratch_base, cpu_scratch_size,
7142                                     &info);
7143         if (err)
7144                 return err;
7145
7146         /* Now startup the cpu. */
7147         tw32(cpu_base + CPU_STATE, 0xffffffff);
7148         tw32_f(cpu_base + CPU_PC, info.fw_base);
7149
7150         for (i = 0; i < 5; i++) {
7151                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7152                         break;
7153                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7154                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7155                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7156                 udelay(1000);
7157         }
7158         if (i >= 5) {
7159                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7160                        "to set CPU PC, is %08x should be %08x\n",
7161                        tp->dev->name, tr32(cpu_base + CPU_PC),
7162                        info.fw_base);
7163                 return -ENODEV;
7164         }
7165         tw32(cpu_base + CPU_STATE, 0xffffffff);
7166         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7167         return 0;
7168 }
7169
7170
7171 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7172 {
7173         struct tg3 *tp = netdev_priv(dev);
7174         struct sockaddr *addr = p;
7175         int err = 0, skip_mac_1 = 0;
7176
7177         if (!is_valid_ether_addr(addr->sa_data))
7178                 return -EINVAL;
7179
7180         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7181
7182         if (!netif_running(dev))
7183                 return 0;
7184
7185         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7186                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7187
7188                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7189                 addr0_low = tr32(MAC_ADDR_0_LOW);
7190                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7191                 addr1_low = tr32(MAC_ADDR_1_LOW);
7192
7193                 /* Skip MAC addr 1 if ASF is using it. */
7194                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7195                     !(addr1_high == 0 && addr1_low == 0))
7196                         skip_mac_1 = 1;
7197         }
7198         spin_lock_bh(&tp->lock);
7199         __tg3_set_mac_addr(tp, skip_mac_1);
7200         spin_unlock_bh(&tp->lock);
7201
7202         return err;
7203 }
7204
7205 /* tp->lock is held. */
7206 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7207                            dma_addr_t mapping, u32 maxlen_flags,
7208                            u32 nic_addr)
7209 {
7210         tg3_write_mem(tp,
7211                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7212                       ((u64) mapping >> 32));
7213         tg3_write_mem(tp,
7214                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7215                       ((u64) mapping & 0xffffffff));
7216         tg3_write_mem(tp,
7217                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7218                        maxlen_flags);
7219
7220         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7221                 tg3_write_mem(tp,
7222                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7223                               nic_addr);
7224 }
7225
7226 static void __tg3_set_rx_mode(struct net_device *);
7227 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7228 {
7229         int i;
7230
7231         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7232                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7233                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7234                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7235
7236                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7237                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7238                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7239         } else {
7240                 tw32(HOSTCC_TXCOL_TICKS, 0);
7241                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7242                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7243
7244                 tw32(HOSTCC_RXCOL_TICKS, 0);
7245                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7246                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7247         }
7248
7249         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7250                 u32 val = ec->stats_block_coalesce_usecs;
7251
7252                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7253                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7254
7255                 if (!netif_carrier_ok(tp->dev))
7256                         val = 0;
7257
7258                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7259         }
7260
7261         for (i = 0; i < tp->irq_cnt - 1; i++) {
7262                 u32 reg;
7263
7264                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7265                 tw32(reg, ec->rx_coalesce_usecs);
7266                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7267                 tw32(reg, ec->tx_coalesce_usecs);
7268                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7269                 tw32(reg, ec->rx_max_coalesced_frames);
7270                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7271                 tw32(reg, ec->tx_max_coalesced_frames);
7272                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7273                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7274                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7275                 tw32(reg, ec->tx_max_coalesced_frames_irq);
7276         }
7277
7278         for (; i < tp->irq_max - 1; i++) {
7279                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7280                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7281                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7282                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7283                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7284                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7285         }
7286 }
7287
7288 /* tp->lock is held. */
7289 static void tg3_rings_reset(struct tg3 *tp)
7290 {
7291         int i;
7292         u32 stblk, txrcb, rxrcb, limit;
7293         struct tg3_napi *tnapi = &tp->napi[0];
7294
7295         /* Disable all transmit rings but the first. */
7296         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7297                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7298         else
7299                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7300
7301         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7302              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7303                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7304                               BDINFO_FLAGS_DISABLED);
7305
7306
7307         /* Disable all receive return rings but the first. */
7308         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7309                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7310         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7311                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7312         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7313                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7314         else
7315                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7316
7317         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7318              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7319                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7320                               BDINFO_FLAGS_DISABLED);
7321
7322         /* Disable interrupts */
7323         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7324
7325         /* Zero mailbox registers. */
7326         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7327                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7328                         tp->napi[i].tx_prod = 0;
7329                         tp->napi[i].tx_cons = 0;
7330                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7331                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7332                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7333                 }
7334         } else {
7335                 tp->napi[0].tx_prod = 0;
7336                 tp->napi[0].tx_cons = 0;
7337                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7338                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7339         }
7340
7341         /* Make sure the NIC-based send BD rings are disabled. */
7342         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7343                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7344                 for (i = 0; i < 16; i++)
7345                         tw32_tx_mbox(mbox + i * 8, 0);
7346         }
7347
7348         txrcb = NIC_SRAM_SEND_RCB;
7349         rxrcb = NIC_SRAM_RCV_RET_RCB;
7350
7351         /* Clear status block in ram. */
7352         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7353
7354         /* Set status block DMA address */
7355         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7356              ((u64) tnapi->status_mapping >> 32));
7357         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7358              ((u64) tnapi->status_mapping & 0xffffffff));
7359
7360         if (tnapi->tx_ring) {
7361                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7362                                (TG3_TX_RING_SIZE <<
7363                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7364                                NIC_SRAM_TX_BUFFER_DESC);
7365                 txrcb += TG3_BDINFO_SIZE;
7366         }
7367
7368         if (tnapi->rx_rcb) {
7369                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7370                                (TG3_RX_RCB_RING_SIZE(tp) <<
7371                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7372                 rxrcb += TG3_BDINFO_SIZE;
7373         }
7374
7375         stblk = HOSTCC_STATBLCK_RING1;
7376
7377         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7378                 u64 mapping = (u64)tnapi->status_mapping;
7379                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7380                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7381
7382                 /* Clear status block in ram. */
7383                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7384
7385                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7386                                (TG3_TX_RING_SIZE <<
7387                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7388                                NIC_SRAM_TX_BUFFER_DESC);
7389
7390                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7391                                (TG3_RX_RCB_RING_SIZE(tp) <<
7392                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7393
7394                 stblk += 8;
7395                 txrcb += TG3_BDINFO_SIZE;
7396                 rxrcb += TG3_BDINFO_SIZE;
7397         }
7398 }
7399
7400 /* tp->lock is held. */
7401 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7402 {
7403         u32 val, rdmac_mode;
7404         int i, err, limit;
7405         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7406
7407         tg3_disable_ints(tp);
7408
7409         tg3_stop_fw(tp);
7410
7411         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7412
7413         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7414                 tg3_abort_hw(tp, 1);
7415         }
7416
7417         if (reset_phy &&
7418             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7419                 tg3_phy_reset(tp);
7420
7421         err = tg3_chip_reset(tp);
7422         if (err)
7423                 return err;
7424
7425         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7426
7427         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7428                 val = tr32(TG3_CPMU_CTRL);
7429                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7430                 tw32(TG3_CPMU_CTRL, val);
7431
7432                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7433                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7434                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7435                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7436
7437                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7438                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7439                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7440                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7441
7442                 val = tr32(TG3_CPMU_HST_ACC);
7443                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7444                 val |= CPMU_HST_ACC_MACCLK_6_25;
7445                 tw32(TG3_CPMU_HST_ACC, val);
7446         }
7447
7448         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7449                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7450                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7451                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7452                 tw32(PCIE_PWR_MGMT_THRESH, val);
7453
7454                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7455                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7456
7457                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7458
7459                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7460                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7461         }
7462
7463         /* This works around an issue with Athlon chipsets on
7464          * B3 tigon3 silicon.  This bit has no effect on any
7465          * other revision.  But do not set this on PCI Express
7466          * chips and don't even touch the clocks if the CPMU is present.
7467          */
7468         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7469                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7470                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7471                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7472         }
7473
7474         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7475             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7476                 val = tr32(TG3PCI_PCISTATE);
7477                 val |= PCISTATE_RETRY_SAME_DMA;
7478                 tw32(TG3PCI_PCISTATE, val);
7479         }
7480
7481         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7482                 /* Allow reads and writes to the
7483                  * APE register and memory space.
7484                  */
7485                 val = tr32(TG3PCI_PCISTATE);
7486                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7487                        PCISTATE_ALLOW_APE_SHMEM_WR;
7488                 tw32(TG3PCI_PCISTATE, val);
7489         }
7490
7491         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7492                 /* Enable some hw fixes.  */
7493                 val = tr32(TG3PCI_MSI_DATA);
7494                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7495                 tw32(TG3PCI_MSI_DATA, val);
7496         }
7497
7498         /* Descriptor ring init may make accesses to the
7499          * NIC SRAM area to setup the TX descriptors, so we
7500          * can only do this after the hardware has been
7501          * successfully reset.
7502          */
7503         err = tg3_init_rings(tp);
7504         if (err)
7505                 return err;
7506
7507         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7508                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7509                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7510                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7511         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7512                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7513                 /* This value is determined during the probe time DMA
7514                  * engine test, tg3_test_dma.
7515                  */
7516                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7517         }
7518
7519         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7520                           GRC_MODE_4X_NIC_SEND_RINGS |
7521                           GRC_MODE_NO_TX_PHDR_CSUM |
7522                           GRC_MODE_NO_RX_PHDR_CSUM);
7523         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7524
7525         /* Pseudo-header checksum is done by hardware logic and not
7526          * the offload processers, so make the chip do the pseudo-
7527          * header checksums on receive.  For transmit it is more
7528          * convenient to do the pseudo-header checksum in software
7529          * as Linux does that on transmit for us in all cases.
7530          */
7531         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7532
7533         tw32(GRC_MODE,
7534              tp->grc_mode |
7535              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7536
7537         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7538         val = tr32(GRC_MISC_CFG);
7539         val &= ~0xff;
7540         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7541         tw32(GRC_MISC_CFG, val);
7542
7543         /* Initialize MBUF/DESC pool. */
7544         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7545                 /* Do nothing.  */
7546         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7547                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7548                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7549                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7550                 else
7551                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7552                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7553                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7554         }
7555         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7556                 int fw_len;
7557
7558                 fw_len = tp->fw_len;
7559                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7560                 tw32(BUFMGR_MB_POOL_ADDR,
7561                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7562                 tw32(BUFMGR_MB_POOL_SIZE,
7563                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7564         }
7565
7566         if (tp->dev->mtu <= ETH_DATA_LEN) {
7567                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7568                      tp->bufmgr_config.mbuf_read_dma_low_water);
7569                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7570                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7571                 tw32(BUFMGR_MB_HIGH_WATER,
7572                      tp->bufmgr_config.mbuf_high_water);
7573         } else {
7574                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7575                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7576                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7577                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7578                 tw32(BUFMGR_MB_HIGH_WATER,
7579                      tp->bufmgr_config.mbuf_high_water_jumbo);
7580         }
7581         tw32(BUFMGR_DMA_LOW_WATER,
7582              tp->bufmgr_config.dma_low_water);
7583         tw32(BUFMGR_DMA_HIGH_WATER,
7584              tp->bufmgr_config.dma_high_water);
7585
7586         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7587         for (i = 0; i < 2000; i++) {
7588                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7589                         break;
7590                 udelay(10);
7591         }
7592         if (i >= 2000) {
7593                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7594                        tp->dev->name);
7595                 return -ENODEV;
7596         }
7597
7598         /* Setup replenish threshold. */
7599         val = tp->rx_pending / 8;
7600         if (val == 0)
7601                 val = 1;
7602         else if (val > tp->rx_std_max_post)
7603                 val = tp->rx_std_max_post;
7604         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7605                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7606                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7607
7608                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7609                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7610         }
7611
7612         tw32(RCVBDI_STD_THRESH, val);
7613
7614         /* Initialize TG3_BDINFO's at:
7615          *  RCVDBDI_STD_BD:     standard eth size rx ring
7616          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7617          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7618          *
7619          * like so:
7620          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7621          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7622          *                              ring attribute flags
7623          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7624          *
7625          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7626          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7627          *
7628          * The size of each ring is fixed in the firmware, but the location is
7629          * configurable.
7630          */
7631         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7632              ((u64) tpr->rx_std_mapping >> 32));
7633         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7634              ((u64) tpr->rx_std_mapping & 0xffffffff));
7635         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7636                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7637                      NIC_SRAM_RX_BUFFER_DESC);
7638
7639         /* Disable the mini ring */
7640         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7641                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7642                      BDINFO_FLAGS_DISABLED);
7643
7644         /* Program the jumbo buffer descriptor ring control
7645          * blocks on those devices that have them.
7646          */
7647         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7648             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7649                 /* Setup replenish threshold. */
7650                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7651
7652                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7653                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7654                              ((u64) tpr->rx_jmb_mapping >> 32));
7655                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7656                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7657                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7658                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7659                              BDINFO_FLAGS_USE_EXT_RECV);
7660                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7661                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7662                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7663                 } else {
7664                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7665                              BDINFO_FLAGS_DISABLED);
7666                 }
7667
7668                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7669                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7670                               (RX_STD_MAX_SIZE << 2);
7671                 else
7672                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7673         } else
7674                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7675
7676         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7677
7678         tpr->rx_std_prod_idx = tp->rx_pending;
7679         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7680
7681         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7682                           tp->rx_jumbo_pending : 0;
7683         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7684
7685         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7686                 tw32(STD_REPLENISH_LWM, 32);
7687                 tw32(JMB_REPLENISH_LWM, 16);
7688         }
7689
7690         tg3_rings_reset(tp);
7691
7692         /* Initialize MAC address and backoff seed. */
7693         __tg3_set_mac_addr(tp, 0);
7694
7695         /* MTU + ethernet header + FCS + optional VLAN tag */
7696         tw32(MAC_RX_MTU_SIZE,
7697              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7698
7699         /* The slot time is changed by tg3_setup_phy if we
7700          * run at gigabit with half duplex.
7701          */
7702         tw32(MAC_TX_LENGTHS,
7703              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7704              (6 << TX_LENGTHS_IPG_SHIFT) |
7705              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7706
7707         /* Receive rules. */
7708         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7709         tw32(RCVLPC_CONFIG, 0x0181);
7710
7711         /* Calculate RDMAC_MODE setting early, we need it to determine
7712          * the RCVLPC_STATE_ENABLE mask.
7713          */
7714         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7715                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7716                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7717                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7718                       RDMAC_MODE_LNGREAD_ENAB);
7719
7720         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7721             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7722             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7723                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7724                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7725                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7726
7727         /* If statement applies to 5705 and 5750 PCI devices only */
7728         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7729              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7730             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7731                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7732                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7733                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7734                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7735                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7736                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7737                 }
7738         }
7739
7740         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7741                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7742
7743         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7744                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7745
7746         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7747             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7748             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7749                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7750
7751         /* Receive/send statistics. */
7752         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7753                 val = tr32(RCVLPC_STATS_ENABLE);
7754                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7755                 tw32(RCVLPC_STATS_ENABLE, val);
7756         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7757                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7758                 val = tr32(RCVLPC_STATS_ENABLE);
7759                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7760                 tw32(RCVLPC_STATS_ENABLE, val);
7761         } else {
7762                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7763         }
7764         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7765         tw32(SNDDATAI_STATSENAB, 0xffffff);
7766         tw32(SNDDATAI_STATSCTRL,
7767              (SNDDATAI_SCTRL_ENABLE |
7768               SNDDATAI_SCTRL_FASTUPD));
7769
7770         /* Setup host coalescing engine. */
7771         tw32(HOSTCC_MODE, 0);
7772         for (i = 0; i < 2000; i++) {
7773                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7774                         break;
7775                 udelay(10);
7776         }
7777
7778         __tg3_set_coalesce(tp, &tp->coal);
7779
7780         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7781                 /* Status/statistics block address.  See tg3_timer,
7782                  * the tg3_periodic_fetch_stats call there, and
7783                  * tg3_get_stats to see how this works for 5705/5750 chips.
7784                  */
7785                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7786                      ((u64) tp->stats_mapping >> 32));
7787                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7788                      ((u64) tp->stats_mapping & 0xffffffff));
7789                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7790
7791                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7792
7793                 /* Clear statistics and status block memory areas */
7794                 for (i = NIC_SRAM_STATS_BLK;
7795                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7796                      i += sizeof(u32)) {
7797                         tg3_write_mem(tp, i, 0);
7798                         udelay(40);
7799                 }
7800         }
7801
7802         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7803
7804         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7805         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7806         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7807                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7808
7809         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7810                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7811                 /* reset to prevent losing 1st rx packet intermittently */
7812                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7813                 udelay(10);
7814         }
7815
7816         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7817                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7818         else
7819                 tp->mac_mode = 0;
7820         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7821                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7822         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7823             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7824             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7825                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7826         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7827         udelay(40);
7828
7829         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7830          * If TG3_FLG2_IS_NIC is zero, we should read the
7831          * register to preserve the GPIO settings for LOMs. The GPIOs,
7832          * whether used as inputs or outputs, are set by boot code after
7833          * reset.
7834          */
7835         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7836                 u32 gpio_mask;
7837
7838                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7839                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7840                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7841
7842                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7843                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7844                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7845
7846                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7847                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7848
7849                 tp->grc_local_ctrl &= ~gpio_mask;
7850                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7851
7852                 /* GPIO1 must be driven high for eeprom write protect */
7853                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7854                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7855                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7856         }
7857         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7858         udelay(100);
7859
7860         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7861                 val = tr32(MSGINT_MODE);
7862                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7863                 tw32(MSGINT_MODE, val);
7864         }
7865
7866         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7867                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7868                 udelay(40);
7869         }
7870
7871         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7872                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7873                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7874                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7875                WDMAC_MODE_LNGREAD_ENAB);
7876
7877         /* If statement applies to 5705 and 5750 PCI devices only */
7878         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7879              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7880             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7881                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7882                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7883                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7884                         /* nothing */
7885                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7886                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7887                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7888                         val |= WDMAC_MODE_RX_ACCEL;
7889                 }
7890         }
7891
7892         /* Enable host coalescing bug fix */
7893         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7894                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7895
7896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7897                 val |= WDMAC_MODE_BURST_ALL_DATA;
7898
7899         tw32_f(WDMAC_MODE, val);
7900         udelay(40);
7901
7902         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7903                 u16 pcix_cmd;
7904
7905                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7906                                      &pcix_cmd);
7907                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7908                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7909                         pcix_cmd |= PCI_X_CMD_READ_2K;
7910                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7911                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7912                         pcix_cmd |= PCI_X_CMD_READ_2K;
7913                 }
7914                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7915                                       pcix_cmd);
7916         }
7917
7918         tw32_f(RDMAC_MODE, rdmac_mode);
7919         udelay(40);
7920
7921         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7922         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7923                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7924
7925         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7926                 tw32(SNDDATAC_MODE,
7927                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7928         else
7929                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7930
7931         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7932         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7933         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7934         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7935         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7936                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7937         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7938         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7939                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7940         tw32(SNDBDI_MODE, val);
7941         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7942
7943         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7944                 err = tg3_load_5701_a0_firmware_fix(tp);
7945                 if (err)
7946                         return err;
7947         }
7948
7949         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7950                 err = tg3_load_tso_firmware(tp);
7951                 if (err)
7952                         return err;
7953         }
7954
7955         tp->tx_mode = TX_MODE_ENABLE;
7956         tw32_f(MAC_TX_MODE, tp->tx_mode);
7957         udelay(100);
7958
7959         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7960                 u32 reg = MAC_RSS_INDIR_TBL_0;
7961                 u8 *ent = (u8 *)&val;
7962
7963                 /* Setup the indirection table */
7964                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7965                         int idx = i % sizeof(val);
7966
7967                         ent[idx] = i % (tp->irq_cnt - 1);
7968                         if (idx == sizeof(val) - 1) {
7969                                 tw32(reg, val);
7970                                 reg += 4;
7971                         }
7972                 }
7973
7974                 /* Setup the "secret" hash key. */
7975                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7976                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7977                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7978                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7979                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7980                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7981                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7982                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7983                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7984                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7985         }
7986
7987         tp->rx_mode = RX_MODE_ENABLE;
7988         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7989                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7990
7991         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7992                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7993                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7994                                RX_MODE_RSS_IPV6_HASH_EN |
7995                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7996                                RX_MODE_RSS_IPV4_HASH_EN |
7997                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7998
7999         tw32_f(MAC_RX_MODE, tp->rx_mode);
8000         udelay(10);
8001
8002         tw32(MAC_LED_CTRL, tp->led_ctrl);
8003
8004         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8005         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8006                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8007                 udelay(10);
8008         }
8009         tw32_f(MAC_RX_MODE, tp->rx_mode);
8010         udelay(10);
8011
8012         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8013                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8014                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8015                         /* Set drive transmission level to 1.2V  */
8016                         /* only if the signal pre-emphasis bit is not set  */
8017                         val = tr32(MAC_SERDES_CFG);
8018                         val &= 0xfffff000;
8019                         val |= 0x880;
8020                         tw32(MAC_SERDES_CFG, val);
8021                 }
8022                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8023                         tw32(MAC_SERDES_CFG, 0x616000);
8024         }
8025
8026         /* Prevent chip from dropping frames when flow control
8027          * is enabled.
8028          */
8029         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
8030
8031         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8032             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8033                 /* Use hardware link auto-negotiation */
8034                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8035         }
8036
8037         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8038             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8039                 u32 tmp;
8040
8041                 tmp = tr32(SERDES_RX_CTRL);
8042                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8043                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8044                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8045                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8046         }
8047
8048         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8049                 if (tp->link_config.phy_is_low_power) {
8050                         tp->link_config.phy_is_low_power = 0;
8051                         tp->link_config.speed = tp->link_config.orig_speed;
8052                         tp->link_config.duplex = tp->link_config.orig_duplex;
8053                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8054                 }
8055
8056                 err = tg3_setup_phy(tp, 0);
8057                 if (err)
8058                         return err;
8059
8060                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8061                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8062                         u32 tmp;
8063
8064                         /* Clear CRC stats. */
8065                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8066                                 tg3_writephy(tp, MII_TG3_TEST1,
8067                                              tmp | MII_TG3_TEST1_CRC_EN);
8068                                 tg3_readphy(tp, 0x14, &tmp);
8069                         }
8070                 }
8071         }
8072
8073         __tg3_set_rx_mode(tp->dev);
8074
8075         /* Initialize receive rules. */
8076         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8077         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8078         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8079         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8080
8081         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8082             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8083                 limit = 8;
8084         else
8085                 limit = 16;
8086         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8087                 limit -= 4;
8088         switch (limit) {
8089         case 16:
8090                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8091         case 15:
8092                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8093         case 14:
8094                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8095         case 13:
8096                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8097         case 12:
8098                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8099         case 11:
8100                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8101         case 10:
8102                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8103         case 9:
8104                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8105         case 8:
8106                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8107         case 7:
8108                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8109         case 6:
8110                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8111         case 5:
8112                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8113         case 4:
8114                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8115         case 3:
8116                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8117         case 2:
8118         case 1:
8119
8120         default:
8121                 break;
8122         }
8123
8124         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8125                 /* Write our heartbeat update interval to APE. */
8126                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8127                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8128
8129         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8130
8131         return 0;
8132 }
8133
8134 /* Called at device open time to get the chip ready for
8135  * packet processing.  Invoked with tp->lock held.
8136  */
8137 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8138 {
8139         tg3_switch_clocks(tp);
8140
8141         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8142
8143         return tg3_reset_hw(tp, reset_phy);
8144 }
8145
8146 #define TG3_STAT_ADD32(PSTAT, REG) \
8147 do {    u32 __val = tr32(REG); \
8148         (PSTAT)->low += __val; \
8149         if ((PSTAT)->low < __val) \
8150                 (PSTAT)->high += 1; \
8151 } while (0)
8152
8153 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8154 {
8155         struct tg3_hw_stats *sp = tp->hw_stats;
8156
8157         if (!netif_carrier_ok(tp->dev))
8158                 return;
8159
8160         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8161         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8162         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8163         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8164         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8165         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8166         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8167         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8168         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8169         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8170         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8171         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8172         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8173
8174         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8175         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8176         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8177         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8178         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8179         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8180         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8181         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8182         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8183         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8184         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8185         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8186         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8187         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8188
8189         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8190         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8191         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8192 }
8193
8194 static void tg3_timer(unsigned long __opaque)
8195 {
8196         struct tg3 *tp = (struct tg3 *) __opaque;
8197
8198         if (tp->irq_sync)
8199                 goto restart_timer;
8200
8201         spin_lock(&tp->lock);
8202
8203         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8204                 /* All of this garbage is because when using non-tagged
8205                  * IRQ status the mailbox/status_block protocol the chip
8206                  * uses with the cpu is race prone.
8207                  */
8208                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8209                         tw32(GRC_LOCAL_CTRL,
8210                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8211                 } else {
8212                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8213                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8214                 }
8215
8216                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8217                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8218                         spin_unlock(&tp->lock);
8219                         schedule_work(&tp->reset_task);
8220                         return;
8221                 }
8222         }
8223
8224         /* This part only runs once per second. */
8225         if (!--tp->timer_counter) {
8226                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8227                         tg3_periodic_fetch_stats(tp);
8228
8229                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8230                         u32 mac_stat;
8231                         int phy_event;
8232
8233                         mac_stat = tr32(MAC_STATUS);
8234
8235                         phy_event = 0;
8236                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8237                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8238                                         phy_event = 1;
8239                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8240                                 phy_event = 1;
8241
8242                         if (phy_event)
8243                                 tg3_setup_phy(tp, 0);
8244                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8245                         u32 mac_stat = tr32(MAC_STATUS);
8246                         int need_setup = 0;
8247
8248                         if (netif_carrier_ok(tp->dev) &&
8249                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8250                                 need_setup = 1;
8251                         }
8252                         if (! netif_carrier_ok(tp->dev) &&
8253                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8254                                          MAC_STATUS_SIGNAL_DET))) {
8255                                 need_setup = 1;
8256                         }
8257                         if (need_setup) {
8258                                 if (!tp->serdes_counter) {
8259                                         tw32_f(MAC_MODE,
8260                                              (tp->mac_mode &
8261                                               ~MAC_MODE_PORT_MODE_MASK));
8262                                         udelay(40);
8263                                         tw32_f(MAC_MODE, tp->mac_mode);
8264                                         udelay(40);
8265                                 }
8266                                 tg3_setup_phy(tp, 0);
8267                         }
8268                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8269                         tg3_serdes_parallel_detect(tp);
8270
8271                 tp->timer_counter = tp->timer_multiplier;
8272         }
8273
8274         /* Heartbeat is only sent once every 2 seconds.
8275          *
8276          * The heartbeat is to tell the ASF firmware that the host
8277          * driver is still alive.  In the event that the OS crashes,
8278          * ASF needs to reset the hardware to free up the FIFO space
8279          * that may be filled with rx packets destined for the host.
8280          * If the FIFO is full, ASF will no longer function properly.
8281          *
8282          * Unintended resets have been reported on real time kernels
8283          * where the timer doesn't run on time.  Netpoll will also have
8284          * same problem.
8285          *
8286          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8287          * to check the ring condition when the heartbeat is expiring
8288          * before doing the reset.  This will prevent most unintended
8289          * resets.
8290          */
8291         if (!--tp->asf_counter) {
8292                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8293                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8294                         tg3_wait_for_event_ack(tp);
8295
8296                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8297                                       FWCMD_NICDRV_ALIVE3);
8298                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8299                         /* 5 seconds timeout */
8300                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8301
8302                         tg3_generate_fw_event(tp);
8303                 }
8304                 tp->asf_counter = tp->asf_multiplier;
8305         }
8306
8307         spin_unlock(&tp->lock);
8308
8309 restart_timer:
8310         tp->timer.expires = jiffies + tp->timer_offset;
8311         add_timer(&tp->timer);
8312 }
8313
8314 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8315 {
8316         irq_handler_t fn;
8317         unsigned long flags;
8318         char *name;
8319         struct tg3_napi *tnapi = &tp->napi[irq_num];
8320
8321         if (tp->irq_cnt == 1)
8322                 name = tp->dev->name;
8323         else {
8324                 name = &tnapi->irq_lbl[0];
8325                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8326                 name[IFNAMSIZ-1] = 0;
8327         }
8328
8329         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8330                 fn = tg3_msi;
8331                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8332                         fn = tg3_msi_1shot;
8333                 flags = IRQF_SAMPLE_RANDOM;
8334         } else {
8335                 fn = tg3_interrupt;
8336                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8337                         fn = tg3_interrupt_tagged;
8338                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8339         }
8340
8341         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8342 }
8343
8344 static int tg3_test_interrupt(struct tg3 *tp)
8345 {
8346         struct tg3_napi *tnapi = &tp->napi[0];
8347         struct net_device *dev = tp->dev;
8348         int err, i, intr_ok = 0;
8349         u32 val;
8350
8351         if (!netif_running(dev))
8352                 return -ENODEV;
8353
8354         tg3_disable_ints(tp);
8355
8356         free_irq(tnapi->irq_vec, tnapi);
8357
8358         /*
8359          * Turn off MSI one shot mode.  Otherwise this test has no
8360          * observable way to know whether the interrupt was delivered.
8361          */
8362         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8363             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8364                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8365                 tw32(MSGINT_MODE, val);
8366         }
8367
8368         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8369                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8370         if (err)
8371                 return err;
8372
8373         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8374         tg3_enable_ints(tp);
8375
8376         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8377                tnapi->coal_now);
8378
8379         for (i = 0; i < 5; i++) {
8380                 u32 int_mbox, misc_host_ctrl;
8381
8382                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8383                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8384
8385                 if ((int_mbox != 0) ||
8386                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8387                         intr_ok = 1;
8388                         break;
8389                 }
8390
8391                 msleep(10);
8392         }
8393
8394         tg3_disable_ints(tp);
8395
8396         free_irq(tnapi->irq_vec, tnapi);
8397
8398         err = tg3_request_irq(tp, 0);
8399
8400         if (err)
8401                 return err;
8402
8403         if (intr_ok) {
8404                 /* Reenable MSI one shot mode. */
8405                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8406                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8407                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8408                         tw32(MSGINT_MODE, val);
8409                 }
8410                 return 0;
8411         }
8412
8413         return -EIO;
8414 }
8415
8416 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8417  * successfully restored
8418  */
8419 static int tg3_test_msi(struct tg3 *tp)
8420 {
8421         int err;
8422         u16 pci_cmd;
8423
8424         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8425                 return 0;
8426
8427         /* Turn off SERR reporting in case MSI terminates with Master
8428          * Abort.
8429          */
8430         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8431         pci_write_config_word(tp->pdev, PCI_COMMAND,
8432                               pci_cmd & ~PCI_COMMAND_SERR);
8433
8434         err = tg3_test_interrupt(tp);
8435
8436         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8437
8438         if (!err)
8439                 return 0;
8440
8441         /* other failures */
8442         if (err != -EIO)
8443                 return err;
8444
8445         /* MSI test failed, go back to INTx mode */
8446         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8447                "switching to INTx mode. Please report this failure to "
8448                "the PCI maintainer and include system chipset information.\n",
8449                        tp->dev->name);
8450
8451         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8452
8453         pci_disable_msi(tp->pdev);
8454
8455         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8456
8457         err = tg3_request_irq(tp, 0);
8458         if (err)
8459                 return err;
8460
8461         /* Need to reset the chip because the MSI cycle may have terminated
8462          * with Master Abort.
8463          */
8464         tg3_full_lock(tp, 1);
8465
8466         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8467         err = tg3_init_hw(tp, 1);
8468
8469         tg3_full_unlock(tp);
8470
8471         if (err)
8472                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8473
8474         return err;
8475 }
8476
8477 static int tg3_request_firmware(struct tg3 *tp)
8478 {
8479         const __be32 *fw_data;
8480
8481         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8482                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8483                        tp->dev->name, tp->fw_needed);
8484                 return -ENOENT;
8485         }
8486
8487         fw_data = (void *)tp->fw->data;
8488
8489         /* Firmware blob starts with version numbers, followed by
8490          * start address and _full_ length including BSS sections
8491          * (which must be longer than the actual data, of course
8492          */
8493
8494         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8495         if (tp->fw_len < (tp->fw->size - 12)) {
8496                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8497                        tp->dev->name, tp->fw_len, tp->fw_needed);
8498                 release_firmware(tp->fw);
8499                 tp->fw = NULL;
8500                 return -EINVAL;
8501         }
8502
8503         /* We no longer need firmware; we have it. */
8504         tp->fw_needed = NULL;
8505         return 0;
8506 }
8507
8508 static bool tg3_enable_msix(struct tg3 *tp)
8509 {
8510         int i, rc, cpus = num_online_cpus();
8511         struct msix_entry msix_ent[tp->irq_max];
8512
8513         if (cpus == 1)
8514                 /* Just fallback to the simpler MSI mode. */
8515                 return false;
8516
8517         /*
8518          * We want as many rx rings enabled as there are cpus.
8519          * The first MSIX vector only deals with link interrupts, etc,
8520          * so we add one to the number of vectors we are requesting.
8521          */
8522         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8523
8524         for (i = 0; i < tp->irq_max; i++) {
8525                 msix_ent[i].entry  = i;
8526                 msix_ent[i].vector = 0;
8527         }
8528
8529         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8530         if (rc != 0) {
8531                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8532                         return false;
8533                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8534                         return false;
8535                 printk(KERN_NOTICE
8536                        "%s: Requested %d MSI-X vectors, received %d\n",
8537                        tp->dev->name, tp->irq_cnt, rc);
8538                 tp->irq_cnt = rc;
8539         }
8540
8541         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8542
8543         for (i = 0; i < tp->irq_max; i++)
8544                 tp->napi[i].irq_vec = msix_ent[i].vector;
8545
8546         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8547
8548         return true;
8549 }
8550
8551 static void tg3_ints_init(struct tg3 *tp)
8552 {
8553         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8554             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8555                 /* All MSI supporting chips should support tagged
8556                  * status.  Assert that this is the case.
8557                  */
8558                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8559                        "Not using MSI.\n", tp->dev->name);
8560                 goto defcfg;
8561         }
8562
8563         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8564                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8565         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8566                  pci_enable_msi(tp->pdev) == 0)
8567                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8568
8569         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8570                 u32 msi_mode = tr32(MSGINT_MODE);
8571                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8572                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8573                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8574         }
8575 defcfg:
8576         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8577                 tp->irq_cnt = 1;
8578                 tp->napi[0].irq_vec = tp->pdev->irq;
8579                 tp->dev->real_num_tx_queues = 1;
8580         }
8581 }
8582
8583 static void tg3_ints_fini(struct tg3 *tp)
8584 {
8585         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8586                 pci_disable_msix(tp->pdev);
8587         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8588                 pci_disable_msi(tp->pdev);
8589         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8590         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8591 }
8592
8593 static int tg3_open(struct net_device *dev)
8594 {
8595         struct tg3 *tp = netdev_priv(dev);
8596         int i, err;
8597
8598         if (tp->fw_needed) {
8599                 err = tg3_request_firmware(tp);
8600                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8601                         if (err)
8602                                 return err;
8603                 } else if (err) {
8604                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8605                                tp->dev->name);
8606                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8607                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8608                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8609                                tp->dev->name);
8610                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8611                 }
8612         }
8613
8614         netif_carrier_off(tp->dev);
8615
8616         err = tg3_set_power_state(tp, PCI_D0);
8617         if (err)
8618                 return err;
8619
8620         tg3_full_lock(tp, 0);
8621
8622         tg3_disable_ints(tp);
8623         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8624
8625         tg3_full_unlock(tp);
8626
8627         /*
8628          * Setup interrupts first so we know how
8629          * many NAPI resources to allocate
8630          */
8631         tg3_ints_init(tp);
8632
8633         /* The placement of this call is tied
8634          * to the setup and use of Host TX descriptors.
8635          */
8636         err = tg3_alloc_consistent(tp);
8637         if (err)
8638                 goto err_out1;
8639
8640         tg3_napi_enable(tp);
8641
8642         for (i = 0; i < tp->irq_cnt; i++) {
8643                 struct tg3_napi *tnapi = &tp->napi[i];
8644                 err = tg3_request_irq(tp, i);
8645                 if (err) {
8646                         for (i--; i >= 0; i--)
8647                                 free_irq(tnapi->irq_vec, tnapi);
8648                         break;
8649                 }
8650         }
8651
8652         if (err)
8653                 goto err_out2;
8654
8655         tg3_full_lock(tp, 0);
8656
8657         err = tg3_init_hw(tp, 1);
8658         if (err) {
8659                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8660                 tg3_free_rings(tp);
8661         } else {
8662                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8663                         tp->timer_offset = HZ;
8664                 else
8665                         tp->timer_offset = HZ / 10;
8666
8667                 BUG_ON(tp->timer_offset > HZ);
8668                 tp->timer_counter = tp->timer_multiplier =
8669                         (HZ / tp->timer_offset);
8670                 tp->asf_counter = tp->asf_multiplier =
8671                         ((HZ / tp->timer_offset) * 2);
8672
8673                 init_timer(&tp->timer);
8674                 tp->timer.expires = jiffies + tp->timer_offset;
8675                 tp->timer.data = (unsigned long) tp;
8676                 tp->timer.function = tg3_timer;
8677         }
8678
8679         tg3_full_unlock(tp);
8680
8681         if (err)
8682                 goto err_out3;
8683
8684         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8685                 err = tg3_test_msi(tp);
8686
8687                 if (err) {
8688                         tg3_full_lock(tp, 0);
8689                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8690                         tg3_free_rings(tp);
8691                         tg3_full_unlock(tp);
8692
8693                         goto err_out2;
8694                 }
8695
8696                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8697                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8698                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8699                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8700
8701                         tw32(PCIE_TRANSACTION_CFG,
8702                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8703                 }
8704         }
8705
8706         tg3_phy_start(tp);
8707
8708         tg3_full_lock(tp, 0);
8709
8710         add_timer(&tp->timer);
8711         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8712         tg3_enable_ints(tp);
8713
8714         tg3_full_unlock(tp);
8715
8716         netif_tx_start_all_queues(dev);
8717
8718         return 0;
8719
8720 err_out3:
8721         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8722                 struct tg3_napi *tnapi = &tp->napi[i];
8723                 free_irq(tnapi->irq_vec, tnapi);
8724         }
8725
8726 err_out2:
8727         tg3_napi_disable(tp);
8728         tg3_free_consistent(tp);
8729
8730 err_out1:
8731         tg3_ints_fini(tp);
8732         return err;
8733 }
8734
8735 #if 0
8736 /*static*/ void tg3_dump_state(struct tg3 *tp)
8737 {
8738         u32 val32, val32_2, val32_3, val32_4, val32_5;
8739         u16 val16;
8740         int i;
8741         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8742
8743         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8744         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8745         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8746                val16, val32);
8747
8748         /* MAC block */
8749         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8750                tr32(MAC_MODE), tr32(MAC_STATUS));
8751         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8752                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8753         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8754                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8755         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8756                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8757
8758         /* Send data initiator control block */
8759         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8760                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8761         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8762                tr32(SNDDATAI_STATSCTRL));
8763
8764         /* Send data completion control block */
8765         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8766
8767         /* Send BD ring selector block */
8768         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8769                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8770
8771         /* Send BD initiator control block */
8772         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8773                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8774
8775         /* Send BD completion control block */
8776         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8777
8778         /* Receive list placement control block */
8779         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8780                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8781         printk("       RCVLPC_STATSCTRL[%08x]\n",
8782                tr32(RCVLPC_STATSCTRL));
8783
8784         /* Receive data and receive BD initiator control block */
8785         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8786                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8787
8788         /* Receive data completion control block */
8789         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8790                tr32(RCVDCC_MODE));
8791
8792         /* Receive BD initiator control block */
8793         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8794                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8795
8796         /* Receive BD completion control block */
8797         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8798                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8799
8800         /* Receive list selector control block */
8801         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8802                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8803
8804         /* Mbuf cluster free block */
8805         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8806                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8807
8808         /* Host coalescing control block */
8809         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8810                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8811         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8812                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8813                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8814         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8815                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8816                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8817         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8818                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8819         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8820                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8821
8822         /* Memory arbiter control block */
8823         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8824                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8825
8826         /* Buffer manager control block */
8827         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8828                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8829         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8830                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8831         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8832                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8833                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8834                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8835
8836         /* Read DMA control block */
8837         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8838                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8839
8840         /* Write DMA control block */
8841         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8842                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8843
8844         /* DMA completion block */
8845         printk("DEBUG: DMAC_MODE[%08x]\n",
8846                tr32(DMAC_MODE));
8847
8848         /* GRC block */
8849         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8850                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8851         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8852                tr32(GRC_LOCAL_CTRL));
8853
8854         /* TG3_BDINFOs */
8855         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8856                tr32(RCVDBDI_JUMBO_BD + 0x0),
8857                tr32(RCVDBDI_JUMBO_BD + 0x4),
8858                tr32(RCVDBDI_JUMBO_BD + 0x8),
8859                tr32(RCVDBDI_JUMBO_BD + 0xc));
8860         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8861                tr32(RCVDBDI_STD_BD + 0x0),
8862                tr32(RCVDBDI_STD_BD + 0x4),
8863                tr32(RCVDBDI_STD_BD + 0x8),
8864                tr32(RCVDBDI_STD_BD + 0xc));
8865         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8866                tr32(RCVDBDI_MINI_BD + 0x0),
8867                tr32(RCVDBDI_MINI_BD + 0x4),
8868                tr32(RCVDBDI_MINI_BD + 0x8),
8869                tr32(RCVDBDI_MINI_BD + 0xc));
8870
8871         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8872         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8873         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8874         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8875         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8876                val32, val32_2, val32_3, val32_4);
8877
8878         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8879         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8880         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8881         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8882         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8883                val32, val32_2, val32_3, val32_4);
8884
8885         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8886         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8887         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8888         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8889         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8890         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8891                val32, val32_2, val32_3, val32_4, val32_5);
8892
8893         /* SW status block */
8894         printk(KERN_DEBUG
8895          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8896                sblk->status,
8897                sblk->status_tag,
8898                sblk->rx_jumbo_consumer,
8899                sblk->rx_consumer,
8900                sblk->rx_mini_consumer,
8901                sblk->idx[0].rx_producer,
8902                sblk->idx[0].tx_consumer);
8903
8904         /* SW statistics block */
8905         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8906                ((u32 *)tp->hw_stats)[0],
8907                ((u32 *)tp->hw_stats)[1],
8908                ((u32 *)tp->hw_stats)[2],
8909                ((u32 *)tp->hw_stats)[3]);
8910
8911         /* Mailboxes */
8912         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8913                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8914                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8915                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8916                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8917
8918         /* NIC side send descriptors. */
8919         for (i = 0; i < 6; i++) {
8920                 unsigned long txd;
8921
8922                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8923                         + (i * sizeof(struct tg3_tx_buffer_desc));
8924                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8925                        i,
8926                        readl(txd + 0x0), readl(txd + 0x4),
8927                        readl(txd + 0x8), readl(txd + 0xc));
8928         }
8929
8930         /* NIC side RX descriptors. */
8931         for (i = 0; i < 6; i++) {
8932                 unsigned long rxd;
8933
8934                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8935                         + (i * sizeof(struct tg3_rx_buffer_desc));
8936                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8937                        i,
8938                        readl(rxd + 0x0), readl(rxd + 0x4),
8939                        readl(rxd + 0x8), readl(rxd + 0xc));
8940                 rxd += (4 * sizeof(u32));
8941                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8942                        i,
8943                        readl(rxd + 0x0), readl(rxd + 0x4),
8944                        readl(rxd + 0x8), readl(rxd + 0xc));
8945         }
8946
8947         for (i = 0; i < 6; i++) {
8948                 unsigned long rxd;
8949
8950                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8951                         + (i * sizeof(struct tg3_rx_buffer_desc));
8952                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8953                        i,
8954                        readl(rxd + 0x0), readl(rxd + 0x4),
8955                        readl(rxd + 0x8), readl(rxd + 0xc));
8956                 rxd += (4 * sizeof(u32));
8957                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8958                        i,
8959                        readl(rxd + 0x0), readl(rxd + 0x4),
8960                        readl(rxd + 0x8), readl(rxd + 0xc));
8961         }
8962 }
8963 #endif
8964
8965 static struct net_device_stats *tg3_get_stats(struct net_device *);
8966 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8967
8968 static int tg3_close(struct net_device *dev)
8969 {
8970         int i;
8971         struct tg3 *tp = netdev_priv(dev);
8972
8973         tg3_napi_disable(tp);
8974         cancel_work_sync(&tp->reset_task);
8975
8976         netif_tx_stop_all_queues(dev);
8977
8978         del_timer_sync(&tp->timer);
8979
8980         tg3_phy_stop(tp);
8981
8982         tg3_full_lock(tp, 1);
8983 #if 0
8984         tg3_dump_state(tp);
8985 #endif
8986
8987         tg3_disable_ints(tp);
8988
8989         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8990         tg3_free_rings(tp);
8991         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8992
8993         tg3_full_unlock(tp);
8994
8995         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8996                 struct tg3_napi *tnapi = &tp->napi[i];
8997                 free_irq(tnapi->irq_vec, tnapi);
8998         }
8999
9000         tg3_ints_fini(tp);
9001
9002         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9003                sizeof(tp->net_stats_prev));
9004         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9005                sizeof(tp->estats_prev));
9006
9007         tg3_free_consistent(tp);
9008
9009         tg3_set_power_state(tp, PCI_D3hot);
9010
9011         netif_carrier_off(tp->dev);
9012
9013         return 0;
9014 }
9015
9016 static inline unsigned long get_stat64(tg3_stat64_t *val)
9017 {
9018         unsigned long ret;
9019
9020 #if (BITS_PER_LONG == 32)
9021         ret = val->low;
9022 #else
9023         ret = ((u64)val->high << 32) | ((u64)val->low);
9024 #endif
9025         return ret;
9026 }
9027
9028 static inline u64 get_estat64(tg3_stat64_t *val)
9029 {
9030        return ((u64)val->high << 32) | ((u64)val->low);
9031 }
9032
9033 static unsigned long calc_crc_errors(struct tg3 *tp)
9034 {
9035         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9036
9037         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9038             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9039              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9040                 u32 val;
9041
9042                 spin_lock_bh(&tp->lock);
9043                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9044                         tg3_writephy(tp, MII_TG3_TEST1,
9045                                      val | MII_TG3_TEST1_CRC_EN);
9046                         tg3_readphy(tp, 0x14, &val);
9047                 } else
9048                         val = 0;
9049                 spin_unlock_bh(&tp->lock);
9050
9051                 tp->phy_crc_errors += val;
9052
9053                 return tp->phy_crc_errors;
9054         }
9055
9056         return get_stat64(&hw_stats->rx_fcs_errors);
9057 }
9058
9059 #define ESTAT_ADD(member) \
9060         estats->member =        old_estats->member + \
9061                                 get_estat64(&hw_stats->member)
9062
9063 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9064 {
9065         struct tg3_ethtool_stats *estats = &tp->estats;
9066         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9067         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9068
9069         if (!hw_stats)
9070                 return old_estats;
9071
9072         ESTAT_ADD(rx_octets);
9073         ESTAT_ADD(rx_fragments);
9074         ESTAT_ADD(rx_ucast_packets);
9075         ESTAT_ADD(rx_mcast_packets);
9076         ESTAT_ADD(rx_bcast_packets);
9077         ESTAT_ADD(rx_fcs_errors);
9078         ESTAT_ADD(rx_align_errors);
9079         ESTAT_ADD(rx_xon_pause_rcvd);
9080         ESTAT_ADD(rx_xoff_pause_rcvd);
9081         ESTAT_ADD(rx_mac_ctrl_rcvd);
9082         ESTAT_ADD(rx_xoff_entered);
9083         ESTAT_ADD(rx_frame_too_long_errors);
9084         ESTAT_ADD(rx_jabbers);
9085         ESTAT_ADD(rx_undersize_packets);
9086         ESTAT_ADD(rx_in_length_errors);
9087         ESTAT_ADD(rx_out_length_errors);
9088         ESTAT_ADD(rx_64_or_less_octet_packets);
9089         ESTAT_ADD(rx_65_to_127_octet_packets);
9090         ESTAT_ADD(rx_128_to_255_octet_packets);
9091         ESTAT_ADD(rx_256_to_511_octet_packets);
9092         ESTAT_ADD(rx_512_to_1023_octet_packets);
9093         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9094         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9095         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9096         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9097         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9098
9099         ESTAT_ADD(tx_octets);
9100         ESTAT_ADD(tx_collisions);
9101         ESTAT_ADD(tx_xon_sent);
9102         ESTAT_ADD(tx_xoff_sent);
9103         ESTAT_ADD(tx_flow_control);
9104         ESTAT_ADD(tx_mac_errors);
9105         ESTAT_ADD(tx_single_collisions);
9106         ESTAT_ADD(tx_mult_collisions);
9107         ESTAT_ADD(tx_deferred);
9108         ESTAT_ADD(tx_excessive_collisions);
9109         ESTAT_ADD(tx_late_collisions);
9110         ESTAT_ADD(tx_collide_2times);
9111         ESTAT_ADD(tx_collide_3times);
9112         ESTAT_ADD(tx_collide_4times);
9113         ESTAT_ADD(tx_collide_5times);
9114         ESTAT_ADD(tx_collide_6times);
9115         ESTAT_ADD(tx_collide_7times);
9116         ESTAT_ADD(tx_collide_8times);
9117         ESTAT_ADD(tx_collide_9times);
9118         ESTAT_ADD(tx_collide_10times);
9119         ESTAT_ADD(tx_collide_11times);
9120         ESTAT_ADD(tx_collide_12times);
9121         ESTAT_ADD(tx_collide_13times);
9122         ESTAT_ADD(tx_collide_14times);
9123         ESTAT_ADD(tx_collide_15times);
9124         ESTAT_ADD(tx_ucast_packets);
9125         ESTAT_ADD(tx_mcast_packets);
9126         ESTAT_ADD(tx_bcast_packets);
9127         ESTAT_ADD(tx_carrier_sense_errors);
9128         ESTAT_ADD(tx_discards);
9129         ESTAT_ADD(tx_errors);
9130
9131         ESTAT_ADD(dma_writeq_full);
9132         ESTAT_ADD(dma_write_prioq_full);
9133         ESTAT_ADD(rxbds_empty);
9134         ESTAT_ADD(rx_discards);
9135         ESTAT_ADD(rx_errors);
9136         ESTAT_ADD(rx_threshold_hit);
9137
9138         ESTAT_ADD(dma_readq_full);
9139         ESTAT_ADD(dma_read_prioq_full);
9140         ESTAT_ADD(tx_comp_queue_full);
9141
9142         ESTAT_ADD(ring_set_send_prod_index);
9143         ESTAT_ADD(ring_status_update);
9144         ESTAT_ADD(nic_irqs);
9145         ESTAT_ADD(nic_avoided_irqs);
9146         ESTAT_ADD(nic_tx_threshold_hit);
9147
9148         return estats;
9149 }
9150
9151 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9152 {
9153         struct tg3 *tp = netdev_priv(dev);
9154         struct net_device_stats *stats = &tp->net_stats;
9155         struct net_device_stats *old_stats = &tp->net_stats_prev;
9156         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9157
9158         if (!hw_stats)
9159                 return old_stats;
9160
9161         stats->rx_packets = old_stats->rx_packets +
9162                 get_stat64(&hw_stats->rx_ucast_packets) +
9163                 get_stat64(&hw_stats->rx_mcast_packets) +
9164                 get_stat64(&hw_stats->rx_bcast_packets);
9165
9166         stats->tx_packets = old_stats->tx_packets +
9167                 get_stat64(&hw_stats->tx_ucast_packets) +
9168                 get_stat64(&hw_stats->tx_mcast_packets) +
9169                 get_stat64(&hw_stats->tx_bcast_packets);
9170
9171         stats->rx_bytes = old_stats->rx_bytes +
9172                 get_stat64(&hw_stats->rx_octets);
9173         stats->tx_bytes = old_stats->tx_bytes +
9174                 get_stat64(&hw_stats->tx_octets);
9175
9176         stats->rx_errors = old_stats->rx_errors +
9177                 get_stat64(&hw_stats->rx_errors);
9178         stats->tx_errors = old_stats->tx_errors +
9179                 get_stat64(&hw_stats->tx_errors) +
9180                 get_stat64(&hw_stats->tx_mac_errors) +
9181                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9182                 get_stat64(&hw_stats->tx_discards);
9183
9184         stats->multicast = old_stats->multicast +
9185                 get_stat64(&hw_stats->rx_mcast_packets);
9186         stats->collisions = old_stats->collisions +
9187                 get_stat64(&hw_stats->tx_collisions);
9188
9189         stats->rx_length_errors = old_stats->rx_length_errors +
9190                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9191                 get_stat64(&hw_stats->rx_undersize_packets);
9192
9193         stats->rx_over_errors = old_stats->rx_over_errors +
9194                 get_stat64(&hw_stats->rxbds_empty);
9195         stats->rx_frame_errors = old_stats->rx_frame_errors +
9196                 get_stat64(&hw_stats->rx_align_errors);
9197         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9198                 get_stat64(&hw_stats->tx_discards);
9199         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9200                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9201
9202         stats->rx_crc_errors = old_stats->rx_crc_errors +
9203                 calc_crc_errors(tp);
9204
9205         stats->rx_missed_errors = old_stats->rx_missed_errors +
9206                 get_stat64(&hw_stats->rx_discards);
9207
9208         return stats;
9209 }
9210
9211 static inline u32 calc_crc(unsigned char *buf, int len)
9212 {
9213         u32 reg;
9214         u32 tmp;
9215         int j, k;
9216
9217         reg = 0xffffffff;
9218
9219         for (j = 0; j < len; j++) {
9220                 reg ^= buf[j];
9221
9222                 for (k = 0; k < 8; k++) {
9223                         tmp = reg & 0x01;
9224
9225                         reg >>= 1;
9226
9227                         if (tmp) {
9228                                 reg ^= 0xedb88320;
9229                         }
9230                 }
9231         }
9232
9233         return ~reg;
9234 }
9235
9236 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9237 {
9238         /* accept or reject all multicast frames */
9239         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9240         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9241         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9242         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9243 }
9244
9245 static void __tg3_set_rx_mode(struct net_device *dev)
9246 {
9247         struct tg3 *tp = netdev_priv(dev);
9248         u32 rx_mode;
9249
9250         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9251                                   RX_MODE_KEEP_VLAN_TAG);
9252
9253         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9254          * flag clear.
9255          */
9256 #if TG3_VLAN_TAG_USED
9257         if (!tp->vlgrp &&
9258             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9259                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9260 #else
9261         /* By definition, VLAN is disabled always in this
9262          * case.
9263          */
9264         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9265                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9266 #endif
9267
9268         if (dev->flags & IFF_PROMISC) {
9269                 /* Promiscuous mode. */
9270                 rx_mode |= RX_MODE_PROMISC;
9271         } else if (dev->flags & IFF_ALLMULTI) {
9272                 /* Accept all multicast. */
9273                 tg3_set_multi (tp, 1);
9274         } else if (dev->mc_count < 1) {
9275                 /* Reject all multicast. */
9276                 tg3_set_multi (tp, 0);
9277         } else {
9278                 /* Accept one or more multicast(s). */
9279                 struct dev_mc_list *mclist;
9280                 unsigned int i;
9281                 u32 mc_filter[4] = { 0, };
9282                 u32 regidx;
9283                 u32 bit;
9284                 u32 crc;
9285
9286                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9287                      i++, mclist = mclist->next) {
9288
9289                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9290                         bit = ~crc & 0x7f;
9291                         regidx = (bit & 0x60) >> 5;
9292                         bit &= 0x1f;
9293                         mc_filter[regidx] |= (1 << bit);
9294                 }
9295
9296                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9297                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9298                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9299                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9300         }
9301
9302         if (rx_mode != tp->rx_mode) {
9303                 tp->rx_mode = rx_mode;
9304                 tw32_f(MAC_RX_MODE, rx_mode);
9305                 udelay(10);
9306         }
9307 }
9308
9309 static void tg3_set_rx_mode(struct net_device *dev)
9310 {
9311         struct tg3 *tp = netdev_priv(dev);
9312
9313         if (!netif_running(dev))
9314                 return;
9315
9316         tg3_full_lock(tp, 0);
9317         __tg3_set_rx_mode(dev);
9318         tg3_full_unlock(tp);
9319 }
9320
9321 #define TG3_REGDUMP_LEN         (32 * 1024)
9322
9323 static int tg3_get_regs_len(struct net_device *dev)
9324 {
9325         return TG3_REGDUMP_LEN;
9326 }
9327
9328 static void tg3_get_regs(struct net_device *dev,
9329                 struct ethtool_regs *regs, void *_p)
9330 {
9331         u32 *p = _p;
9332         struct tg3 *tp = netdev_priv(dev);
9333         u8 *orig_p = _p;
9334         int i;
9335
9336         regs->version = 0;
9337
9338         memset(p, 0, TG3_REGDUMP_LEN);
9339
9340         if (tp->link_config.phy_is_low_power)
9341                 return;
9342
9343         tg3_full_lock(tp, 0);
9344
9345 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9346 #define GET_REG32_LOOP(base,len)                \
9347 do {    p = (u32 *)(orig_p + (base));           \
9348         for (i = 0; i < len; i += 4)            \
9349                 __GET_REG32((base) + i);        \
9350 } while (0)
9351 #define GET_REG32_1(reg)                        \
9352 do {    p = (u32 *)(orig_p + (reg));            \
9353         __GET_REG32((reg));                     \
9354 } while (0)
9355
9356         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9357         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9358         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9359         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9360         GET_REG32_1(SNDDATAC_MODE);
9361         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9362         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9363         GET_REG32_1(SNDBDC_MODE);
9364         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9365         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9366         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9367         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9368         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9369         GET_REG32_1(RCVDCC_MODE);
9370         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9371         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9372         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9373         GET_REG32_1(MBFREE_MODE);
9374         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9375         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9376         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9377         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9378         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9379         GET_REG32_1(RX_CPU_MODE);
9380         GET_REG32_1(RX_CPU_STATE);
9381         GET_REG32_1(RX_CPU_PGMCTR);
9382         GET_REG32_1(RX_CPU_HWBKPT);
9383         GET_REG32_1(TX_CPU_MODE);
9384         GET_REG32_1(TX_CPU_STATE);
9385         GET_REG32_1(TX_CPU_PGMCTR);
9386         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9387         GET_REG32_LOOP(FTQ_RESET, 0x120);
9388         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9389         GET_REG32_1(DMAC_MODE);
9390         GET_REG32_LOOP(GRC_MODE, 0x4c);
9391         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9392                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9393
9394 #undef __GET_REG32
9395 #undef GET_REG32_LOOP
9396 #undef GET_REG32_1
9397
9398         tg3_full_unlock(tp);
9399 }
9400
9401 static int tg3_get_eeprom_len(struct net_device *dev)
9402 {
9403         struct tg3 *tp = netdev_priv(dev);
9404
9405         return tp->nvram_size;
9406 }
9407
9408 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9409 {
9410         struct tg3 *tp = netdev_priv(dev);
9411         int ret;
9412         u8  *pd;
9413         u32 i, offset, len, b_offset, b_count;
9414         __be32 val;
9415
9416         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9417                 return -EINVAL;
9418
9419         if (tp->link_config.phy_is_low_power)
9420                 return -EAGAIN;
9421
9422         offset = eeprom->offset;
9423         len = eeprom->len;
9424         eeprom->len = 0;
9425
9426         eeprom->magic = TG3_EEPROM_MAGIC;
9427
9428         if (offset & 3) {
9429                 /* adjustments to start on required 4 byte boundary */
9430                 b_offset = offset & 3;
9431                 b_count = 4 - b_offset;
9432                 if (b_count > len) {
9433                         /* i.e. offset=1 len=2 */
9434                         b_count = len;
9435                 }
9436                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9437                 if (ret)
9438                         return ret;
9439                 memcpy(data, ((char*)&val) + b_offset, b_count);
9440                 len -= b_count;
9441                 offset += b_count;
9442                 eeprom->len += b_count;
9443         }
9444
9445         /* read bytes upto the last 4 byte boundary */
9446         pd = &data[eeprom->len];
9447         for (i = 0; i < (len - (len & 3)); i += 4) {
9448                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9449                 if (ret) {
9450                         eeprom->len += i;
9451                         return ret;
9452                 }
9453                 memcpy(pd + i, &val, 4);
9454         }
9455         eeprom->len += i;
9456
9457         if (len & 3) {
9458                 /* read last bytes not ending on 4 byte boundary */
9459                 pd = &data[eeprom->len];
9460                 b_count = len & 3;
9461                 b_offset = offset + len - b_count;
9462                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9463                 if (ret)
9464                         return ret;
9465                 memcpy(pd, &val, b_count);
9466                 eeprom->len += b_count;
9467         }
9468         return 0;
9469 }
9470
9471 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9472
9473 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9474 {
9475         struct tg3 *tp = netdev_priv(dev);
9476         int ret;
9477         u32 offset, len, b_offset, odd_len;
9478         u8 *buf;
9479         __be32 start, end;
9480
9481         if (tp->link_config.phy_is_low_power)
9482                 return -EAGAIN;
9483
9484         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9485             eeprom->magic != TG3_EEPROM_MAGIC)
9486                 return -EINVAL;
9487
9488         offset = eeprom->offset;
9489         len = eeprom->len;
9490
9491         if ((b_offset = (offset & 3))) {
9492                 /* adjustments to start on required 4 byte boundary */
9493                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9494                 if (ret)
9495                         return ret;
9496                 len += b_offset;
9497                 offset &= ~3;
9498                 if (len < 4)
9499                         len = 4;
9500         }
9501
9502         odd_len = 0;
9503         if (len & 3) {
9504                 /* adjustments to end on required 4 byte boundary */
9505                 odd_len = 1;
9506                 len = (len + 3) & ~3;
9507                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9508                 if (ret)
9509                         return ret;
9510         }
9511
9512         buf = data;
9513         if (b_offset || odd_len) {
9514                 buf = kmalloc(len, GFP_KERNEL);
9515                 if (!buf)
9516                         return -ENOMEM;
9517                 if (b_offset)
9518                         memcpy(buf, &start, 4);
9519                 if (odd_len)
9520                         memcpy(buf+len-4, &end, 4);
9521                 memcpy(buf + b_offset, data, eeprom->len);
9522         }
9523
9524         ret = tg3_nvram_write_block(tp, offset, len, buf);
9525
9526         if (buf != data)
9527                 kfree(buf);
9528
9529         return ret;
9530 }
9531
9532 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9533 {
9534         struct tg3 *tp = netdev_priv(dev);
9535
9536         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9537                 struct phy_device *phydev;
9538                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9539                         return -EAGAIN;
9540                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9541                 return phy_ethtool_gset(phydev, cmd);
9542         }
9543
9544         cmd->supported = (SUPPORTED_Autoneg);
9545
9546         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9547                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9548                                    SUPPORTED_1000baseT_Full);
9549
9550         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9551                 cmd->supported |= (SUPPORTED_100baseT_Half |
9552                                   SUPPORTED_100baseT_Full |
9553                                   SUPPORTED_10baseT_Half |
9554                                   SUPPORTED_10baseT_Full |
9555                                   SUPPORTED_TP);
9556                 cmd->port = PORT_TP;
9557         } else {
9558                 cmd->supported |= SUPPORTED_FIBRE;
9559                 cmd->port = PORT_FIBRE;
9560         }
9561
9562         cmd->advertising = tp->link_config.advertising;
9563         if (netif_running(dev)) {
9564                 cmd->speed = tp->link_config.active_speed;
9565                 cmd->duplex = tp->link_config.active_duplex;
9566         }
9567         cmd->phy_address = tp->phy_addr;
9568         cmd->transceiver = XCVR_INTERNAL;
9569         cmd->autoneg = tp->link_config.autoneg;
9570         cmd->maxtxpkt = 0;
9571         cmd->maxrxpkt = 0;
9572         return 0;
9573 }
9574
9575 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9576 {
9577         struct tg3 *tp = netdev_priv(dev);
9578
9579         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9580                 struct phy_device *phydev;
9581                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9582                         return -EAGAIN;
9583                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9584                 return phy_ethtool_sset(phydev, cmd);
9585         }
9586
9587         if (cmd->autoneg != AUTONEG_ENABLE &&
9588             cmd->autoneg != AUTONEG_DISABLE)
9589                 return -EINVAL;
9590
9591         if (cmd->autoneg == AUTONEG_DISABLE &&
9592             cmd->duplex != DUPLEX_FULL &&
9593             cmd->duplex != DUPLEX_HALF)
9594                 return -EINVAL;
9595
9596         if (cmd->autoneg == AUTONEG_ENABLE) {
9597                 u32 mask = ADVERTISED_Autoneg |
9598                            ADVERTISED_Pause |
9599                            ADVERTISED_Asym_Pause;
9600
9601                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9602                         mask |= ADVERTISED_1000baseT_Half |
9603                                 ADVERTISED_1000baseT_Full;
9604
9605                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9606                         mask |= ADVERTISED_100baseT_Half |
9607                                 ADVERTISED_100baseT_Full |
9608                                 ADVERTISED_10baseT_Half |
9609                                 ADVERTISED_10baseT_Full |
9610                                 ADVERTISED_TP;
9611                 else
9612                         mask |= ADVERTISED_FIBRE;
9613
9614                 if (cmd->advertising & ~mask)
9615                         return -EINVAL;
9616
9617                 mask &= (ADVERTISED_1000baseT_Half |
9618                          ADVERTISED_1000baseT_Full |
9619                          ADVERTISED_100baseT_Half |
9620                          ADVERTISED_100baseT_Full |
9621                          ADVERTISED_10baseT_Half |
9622                          ADVERTISED_10baseT_Full);
9623
9624                 cmd->advertising &= mask;
9625         } else {
9626                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9627                         if (cmd->speed != SPEED_1000)
9628                                 return -EINVAL;
9629
9630                         if (cmd->duplex != DUPLEX_FULL)
9631                                 return -EINVAL;
9632                 } else {
9633                         if (cmd->speed != SPEED_100 &&
9634                             cmd->speed != SPEED_10)
9635                                 return -EINVAL;
9636                 }
9637         }
9638
9639         tg3_full_lock(tp, 0);
9640
9641         tp->link_config.autoneg = cmd->autoneg;
9642         if (cmd->autoneg == AUTONEG_ENABLE) {
9643                 tp->link_config.advertising = (cmd->advertising |
9644                                               ADVERTISED_Autoneg);
9645                 tp->link_config.speed = SPEED_INVALID;
9646                 tp->link_config.duplex = DUPLEX_INVALID;
9647         } else {
9648                 tp->link_config.advertising = 0;
9649                 tp->link_config.speed = cmd->speed;
9650                 tp->link_config.duplex = cmd->duplex;
9651         }
9652
9653         tp->link_config.orig_speed = tp->link_config.speed;
9654         tp->link_config.orig_duplex = tp->link_config.duplex;
9655         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9656
9657         if (netif_running(dev))
9658                 tg3_setup_phy(tp, 1);
9659
9660         tg3_full_unlock(tp);
9661
9662         return 0;
9663 }
9664
9665 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9666 {
9667         struct tg3 *tp = netdev_priv(dev);
9668
9669         strcpy(info->driver, DRV_MODULE_NAME);
9670         strcpy(info->version, DRV_MODULE_VERSION);
9671         strcpy(info->fw_version, tp->fw_ver);
9672         strcpy(info->bus_info, pci_name(tp->pdev));
9673 }
9674
9675 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9676 {
9677         struct tg3 *tp = netdev_priv(dev);
9678
9679         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9680             device_can_wakeup(&tp->pdev->dev))
9681                 wol->supported = WAKE_MAGIC;
9682         else
9683                 wol->supported = 0;
9684         wol->wolopts = 0;
9685         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9686             device_can_wakeup(&tp->pdev->dev))
9687                 wol->wolopts = WAKE_MAGIC;
9688         memset(&wol->sopass, 0, sizeof(wol->sopass));
9689 }
9690
9691 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9692 {
9693         struct tg3 *tp = netdev_priv(dev);
9694         struct device *dp = &tp->pdev->dev;
9695
9696         if (wol->wolopts & ~WAKE_MAGIC)
9697                 return -EINVAL;
9698         if ((wol->wolopts & WAKE_MAGIC) &&
9699             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9700                 return -EINVAL;
9701
9702         spin_lock_bh(&tp->lock);
9703         if (wol->wolopts & WAKE_MAGIC) {
9704                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9705                 device_set_wakeup_enable(dp, true);
9706         } else {
9707                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9708                 device_set_wakeup_enable(dp, false);
9709         }
9710         spin_unlock_bh(&tp->lock);
9711
9712         return 0;
9713 }
9714
9715 static u32 tg3_get_msglevel(struct net_device *dev)
9716 {
9717         struct tg3 *tp = netdev_priv(dev);
9718         return tp->msg_enable;
9719 }
9720
9721 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9722 {
9723         struct tg3 *tp = netdev_priv(dev);
9724         tp->msg_enable = value;
9725 }
9726
9727 static int tg3_set_tso(struct net_device *dev, u32 value)
9728 {
9729         struct tg3 *tp = netdev_priv(dev);
9730
9731         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9732                 if (value)
9733                         return -EINVAL;
9734                 return 0;
9735         }
9736         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9737             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9738              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9739                 if (value) {
9740                         dev->features |= NETIF_F_TSO6;
9741                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9742                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9743                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9744                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9745                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9746                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9747                                 dev->features |= NETIF_F_TSO_ECN;
9748                 } else
9749                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9750         }
9751         return ethtool_op_set_tso(dev, value);
9752 }
9753
9754 static int tg3_nway_reset(struct net_device *dev)
9755 {
9756         struct tg3 *tp = netdev_priv(dev);
9757         int r;
9758
9759         if (!netif_running(dev))
9760                 return -EAGAIN;
9761
9762         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9763                 return -EINVAL;
9764
9765         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9766                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9767                         return -EAGAIN;
9768                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9769         } else {
9770                 u32 bmcr;
9771
9772                 spin_lock_bh(&tp->lock);
9773                 r = -EINVAL;
9774                 tg3_readphy(tp, MII_BMCR, &bmcr);
9775                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9776                     ((bmcr & BMCR_ANENABLE) ||
9777                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9778                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9779                                                    BMCR_ANENABLE);
9780                         r = 0;
9781                 }
9782                 spin_unlock_bh(&tp->lock);
9783         }
9784
9785         return r;
9786 }
9787
9788 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9789 {
9790         struct tg3 *tp = netdev_priv(dev);
9791
9792         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9793         ering->rx_mini_max_pending = 0;
9794         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9795                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9796         else
9797                 ering->rx_jumbo_max_pending = 0;
9798
9799         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9800
9801         ering->rx_pending = tp->rx_pending;
9802         ering->rx_mini_pending = 0;
9803         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9804                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9805         else
9806                 ering->rx_jumbo_pending = 0;
9807
9808         ering->tx_pending = tp->napi[0].tx_pending;
9809 }
9810
9811 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9812 {
9813         struct tg3 *tp = netdev_priv(dev);
9814         int i, irq_sync = 0, err = 0;
9815
9816         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9817             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9818             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9819             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9820             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9821              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9822                 return -EINVAL;
9823
9824         if (netif_running(dev)) {
9825                 tg3_phy_stop(tp);
9826                 tg3_netif_stop(tp);
9827                 irq_sync = 1;
9828         }
9829
9830         tg3_full_lock(tp, irq_sync);
9831
9832         tp->rx_pending = ering->rx_pending;
9833
9834         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9835             tp->rx_pending > 63)
9836                 tp->rx_pending = 63;
9837         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9838
9839         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9840                 tp->napi[i].tx_pending = ering->tx_pending;
9841
9842         if (netif_running(dev)) {
9843                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9844                 err = tg3_restart_hw(tp, 1);
9845                 if (!err)
9846                         tg3_netif_start(tp);
9847         }
9848
9849         tg3_full_unlock(tp);
9850
9851         if (irq_sync && !err)
9852                 tg3_phy_start(tp);
9853
9854         return err;
9855 }
9856
9857 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9858 {
9859         struct tg3 *tp = netdev_priv(dev);
9860
9861         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9862
9863         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9864                 epause->rx_pause = 1;
9865         else
9866                 epause->rx_pause = 0;
9867
9868         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9869                 epause->tx_pause = 1;
9870         else
9871                 epause->tx_pause = 0;
9872 }
9873
9874 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9875 {
9876         struct tg3 *tp = netdev_priv(dev);
9877         int err = 0;
9878
9879         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9880                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9881                         return -EAGAIN;
9882
9883                 if (epause->autoneg) {
9884                         u32 newadv;
9885                         struct phy_device *phydev;
9886
9887                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9888
9889                         if (epause->rx_pause) {
9890                                 if (epause->tx_pause)
9891                                         newadv = ADVERTISED_Pause;
9892                                 else
9893                                         newadv = ADVERTISED_Pause |
9894                                                  ADVERTISED_Asym_Pause;
9895                         } else if (epause->tx_pause) {
9896                                 newadv = ADVERTISED_Asym_Pause;
9897                         } else
9898                                 newadv = 0;
9899
9900                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9901                                 u32 oldadv = phydev->advertising &
9902                                              (ADVERTISED_Pause |
9903                                               ADVERTISED_Asym_Pause);
9904                                 if (oldadv != newadv) {
9905                                         phydev->advertising &=
9906                                                 ~(ADVERTISED_Pause |
9907                                                   ADVERTISED_Asym_Pause);
9908                                         phydev->advertising |= newadv;
9909                                         err = phy_start_aneg(phydev);
9910                                 }
9911                         } else {
9912                                 tp->link_config.advertising &=
9913                                                 ~(ADVERTISED_Pause |
9914                                                   ADVERTISED_Asym_Pause);
9915                                 tp->link_config.advertising |= newadv;
9916                         }
9917                 } else {
9918                         if (epause->rx_pause)
9919                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9920                         else
9921                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9922
9923                         if (epause->tx_pause)
9924                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9925                         else
9926                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9927
9928                         if (netif_running(dev))
9929                                 tg3_setup_flow_control(tp, 0, 0);
9930                 }
9931         } else {
9932                 int irq_sync = 0;
9933
9934                 if (netif_running(dev)) {
9935                         tg3_netif_stop(tp);
9936                         irq_sync = 1;
9937                 }
9938
9939                 tg3_full_lock(tp, irq_sync);
9940
9941                 if (epause->autoneg)
9942                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9943                 else
9944                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9945                 if (epause->rx_pause)
9946                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9947                 else
9948                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9949                 if (epause->tx_pause)
9950                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9951                 else
9952                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9953
9954                 if (netif_running(dev)) {
9955                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9956                         err = tg3_restart_hw(tp, 1);
9957                         if (!err)
9958                                 tg3_netif_start(tp);
9959                 }
9960
9961                 tg3_full_unlock(tp);
9962         }
9963
9964         return err;
9965 }
9966
9967 static u32 tg3_get_rx_csum(struct net_device *dev)
9968 {
9969         struct tg3 *tp = netdev_priv(dev);
9970         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9971 }
9972
9973 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9974 {
9975         struct tg3 *tp = netdev_priv(dev);
9976
9977         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9978                 if (data != 0)
9979                         return -EINVAL;
9980                 return 0;
9981         }
9982
9983         spin_lock_bh(&tp->lock);
9984         if (data)
9985                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9986         else
9987                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9988         spin_unlock_bh(&tp->lock);
9989
9990         return 0;
9991 }
9992
9993 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9994 {
9995         struct tg3 *tp = netdev_priv(dev);
9996
9997         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9998                 if (data != 0)
9999                         return -EINVAL;
10000                 return 0;
10001         }
10002
10003         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10004                 ethtool_op_set_tx_ipv6_csum(dev, data);
10005         else
10006                 ethtool_op_set_tx_csum(dev, data);
10007
10008         return 0;
10009 }
10010
10011 static int tg3_get_sset_count (struct net_device *dev, int sset)
10012 {
10013         switch (sset) {
10014         case ETH_SS_TEST:
10015                 return TG3_NUM_TEST;
10016         case ETH_SS_STATS:
10017                 return TG3_NUM_STATS;
10018         default:
10019                 return -EOPNOTSUPP;
10020         }
10021 }
10022
10023 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10024 {
10025         switch (stringset) {
10026         case ETH_SS_STATS:
10027                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10028                 break;
10029         case ETH_SS_TEST:
10030                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10031                 break;
10032         default:
10033                 WARN_ON(1);     /* we need a WARN() */
10034                 break;
10035         }
10036 }
10037
10038 static int tg3_phys_id(struct net_device *dev, u32 data)
10039 {
10040         struct tg3 *tp = netdev_priv(dev);
10041         int i;
10042
10043         if (!netif_running(tp->dev))
10044                 return -EAGAIN;
10045
10046         if (data == 0)
10047                 data = UINT_MAX / 2;
10048
10049         for (i = 0; i < (data * 2); i++) {
10050                 if ((i % 2) == 0)
10051                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10052                                            LED_CTRL_1000MBPS_ON |
10053                                            LED_CTRL_100MBPS_ON |
10054                                            LED_CTRL_10MBPS_ON |
10055                                            LED_CTRL_TRAFFIC_OVERRIDE |
10056                                            LED_CTRL_TRAFFIC_BLINK |
10057                                            LED_CTRL_TRAFFIC_LED);
10058
10059                 else
10060                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10061                                            LED_CTRL_TRAFFIC_OVERRIDE);
10062
10063                 if (msleep_interruptible(500))
10064                         break;
10065         }
10066         tw32(MAC_LED_CTRL, tp->led_ctrl);
10067         return 0;
10068 }
10069
10070 static void tg3_get_ethtool_stats (struct net_device *dev,
10071                                    struct ethtool_stats *estats, u64 *tmp_stats)
10072 {
10073         struct tg3 *tp = netdev_priv(dev);
10074         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10075 }
10076
10077 #define NVRAM_TEST_SIZE 0x100
10078 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10079 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10080 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10081 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10082 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10083
10084 static int tg3_test_nvram(struct tg3 *tp)
10085 {
10086         u32 csum, magic;
10087         __be32 *buf;
10088         int i, j, k, err = 0, size;
10089
10090         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10091                 return 0;
10092
10093         if (tg3_nvram_read(tp, 0, &magic) != 0)
10094                 return -EIO;
10095
10096         if (magic == TG3_EEPROM_MAGIC)
10097                 size = NVRAM_TEST_SIZE;
10098         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10099                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10100                     TG3_EEPROM_SB_FORMAT_1) {
10101                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10102                         case TG3_EEPROM_SB_REVISION_0:
10103                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10104                                 break;
10105                         case TG3_EEPROM_SB_REVISION_2:
10106                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10107                                 break;
10108                         case TG3_EEPROM_SB_REVISION_3:
10109                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10110                                 break;
10111                         default:
10112                                 return 0;
10113                         }
10114                 } else
10115                         return 0;
10116         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10117                 size = NVRAM_SELFBOOT_HW_SIZE;
10118         else
10119                 return -EIO;
10120
10121         buf = kmalloc(size, GFP_KERNEL);
10122         if (buf == NULL)
10123                 return -ENOMEM;
10124
10125         err = -EIO;
10126         for (i = 0, j = 0; i < size; i += 4, j++) {
10127                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10128                 if (err)
10129                         break;
10130         }
10131         if (i < size)
10132                 goto out;
10133
10134         /* Selfboot format */
10135         magic = be32_to_cpu(buf[0]);
10136         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10137             TG3_EEPROM_MAGIC_FW) {
10138                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10139
10140                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10141                     TG3_EEPROM_SB_REVISION_2) {
10142                         /* For rev 2, the csum doesn't include the MBA. */
10143                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10144                                 csum8 += buf8[i];
10145                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10146                                 csum8 += buf8[i];
10147                 } else {
10148                         for (i = 0; i < size; i++)
10149                                 csum8 += buf8[i];
10150                 }
10151
10152                 if (csum8 == 0) {
10153                         err = 0;
10154                         goto out;
10155                 }
10156
10157                 err = -EIO;
10158                 goto out;
10159         }
10160
10161         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10162             TG3_EEPROM_MAGIC_HW) {
10163                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10164                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10165                 u8 *buf8 = (u8 *) buf;
10166
10167                 /* Separate the parity bits and the data bytes.  */
10168                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10169                         if ((i == 0) || (i == 8)) {
10170                                 int l;
10171                                 u8 msk;
10172
10173                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10174                                         parity[k++] = buf8[i] & msk;
10175                                 i++;
10176                         }
10177                         else if (i == 16) {
10178                                 int l;
10179                                 u8 msk;
10180
10181                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10182                                         parity[k++] = buf8[i] & msk;
10183                                 i++;
10184
10185                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10186                                         parity[k++] = buf8[i] & msk;
10187                                 i++;
10188                         }
10189                         data[j++] = buf8[i];
10190                 }
10191
10192                 err = -EIO;
10193                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10194                         u8 hw8 = hweight8(data[i]);
10195
10196                         if ((hw8 & 0x1) && parity[i])
10197                                 goto out;
10198                         else if (!(hw8 & 0x1) && !parity[i])
10199                                 goto out;
10200                 }
10201                 err = 0;
10202                 goto out;
10203         }
10204
10205         /* Bootstrap checksum at offset 0x10 */
10206         csum = calc_crc((unsigned char *) buf, 0x10);
10207         if (csum != be32_to_cpu(buf[0x10/4]))
10208                 goto out;
10209
10210         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10211         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10212         if (csum != be32_to_cpu(buf[0xfc/4]))
10213                 goto out;
10214
10215         err = 0;
10216
10217 out:
10218         kfree(buf);
10219         return err;
10220 }
10221
10222 #define TG3_SERDES_TIMEOUT_SEC  2
10223 #define TG3_COPPER_TIMEOUT_SEC  6
10224
10225 static int tg3_test_link(struct tg3 *tp)
10226 {
10227         int i, max;
10228
10229         if (!netif_running(tp->dev))
10230                 return -ENODEV;
10231
10232         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10233                 max = TG3_SERDES_TIMEOUT_SEC;
10234         else
10235                 max = TG3_COPPER_TIMEOUT_SEC;
10236
10237         for (i = 0; i < max; i++) {
10238                 if (netif_carrier_ok(tp->dev))
10239                         return 0;
10240
10241                 if (msleep_interruptible(1000))
10242                         break;
10243         }
10244
10245         return -EIO;
10246 }
10247
10248 /* Only test the commonly used registers */
10249 static int tg3_test_registers(struct tg3 *tp)
10250 {
10251         int i, is_5705, is_5750;
10252         u32 offset, read_mask, write_mask, val, save_val, read_val;
10253         static struct {
10254                 u16 offset;
10255                 u16 flags;
10256 #define TG3_FL_5705     0x1
10257 #define TG3_FL_NOT_5705 0x2
10258 #define TG3_FL_NOT_5788 0x4
10259 #define TG3_FL_NOT_5750 0x8
10260                 u32 read_mask;
10261                 u32 write_mask;
10262         } reg_tbl[] = {
10263                 /* MAC Control Registers */
10264                 { MAC_MODE, TG3_FL_NOT_5705,
10265                         0x00000000, 0x00ef6f8c },
10266                 { MAC_MODE, TG3_FL_5705,
10267                         0x00000000, 0x01ef6b8c },
10268                 { MAC_STATUS, TG3_FL_NOT_5705,
10269                         0x03800107, 0x00000000 },
10270                 { MAC_STATUS, TG3_FL_5705,
10271                         0x03800100, 0x00000000 },
10272                 { MAC_ADDR_0_HIGH, 0x0000,
10273                         0x00000000, 0x0000ffff },
10274                 { MAC_ADDR_0_LOW, 0x0000,
10275                         0x00000000, 0xffffffff },
10276                 { MAC_RX_MTU_SIZE, 0x0000,
10277                         0x00000000, 0x0000ffff },
10278                 { MAC_TX_MODE, 0x0000,
10279                         0x00000000, 0x00000070 },
10280                 { MAC_TX_LENGTHS, 0x0000,
10281                         0x00000000, 0x00003fff },
10282                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10283                         0x00000000, 0x000007fc },
10284                 { MAC_RX_MODE, TG3_FL_5705,
10285                         0x00000000, 0x000007dc },
10286                 { MAC_HASH_REG_0, 0x0000,
10287                         0x00000000, 0xffffffff },
10288                 { MAC_HASH_REG_1, 0x0000,
10289                         0x00000000, 0xffffffff },
10290                 { MAC_HASH_REG_2, 0x0000,
10291                         0x00000000, 0xffffffff },
10292                 { MAC_HASH_REG_3, 0x0000,
10293                         0x00000000, 0xffffffff },
10294
10295                 /* Receive Data and Receive BD Initiator Control Registers. */
10296                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10297                         0x00000000, 0xffffffff },
10298                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10299                         0x00000000, 0xffffffff },
10300                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10301                         0x00000000, 0x00000003 },
10302                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10303                         0x00000000, 0xffffffff },
10304                 { RCVDBDI_STD_BD+0, 0x0000,
10305                         0x00000000, 0xffffffff },
10306                 { RCVDBDI_STD_BD+4, 0x0000,
10307                         0x00000000, 0xffffffff },
10308                 { RCVDBDI_STD_BD+8, 0x0000,
10309                         0x00000000, 0xffff0002 },
10310                 { RCVDBDI_STD_BD+0xc, 0x0000,
10311                         0x00000000, 0xffffffff },
10312
10313                 /* Receive BD Initiator Control Registers. */
10314                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10315                         0x00000000, 0xffffffff },
10316                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10317                         0x00000000, 0x000003ff },
10318                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10319                         0x00000000, 0xffffffff },
10320
10321                 /* Host Coalescing Control Registers. */
10322                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10323                         0x00000000, 0x00000004 },
10324                 { HOSTCC_MODE, TG3_FL_5705,
10325                         0x00000000, 0x000000f6 },
10326                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10327                         0x00000000, 0xffffffff },
10328                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10329                         0x00000000, 0x000003ff },
10330                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10331                         0x00000000, 0xffffffff },
10332                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10333                         0x00000000, 0x000003ff },
10334                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10335                         0x00000000, 0xffffffff },
10336                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10337                         0x00000000, 0x000000ff },
10338                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10339                         0x00000000, 0xffffffff },
10340                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10341                         0x00000000, 0x000000ff },
10342                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10343                         0x00000000, 0xffffffff },
10344                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10345                         0x00000000, 0xffffffff },
10346                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10347                         0x00000000, 0xffffffff },
10348                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10349                         0x00000000, 0x000000ff },
10350                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10351                         0x00000000, 0xffffffff },
10352                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10353                         0x00000000, 0x000000ff },
10354                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10355                         0x00000000, 0xffffffff },
10356                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10357                         0x00000000, 0xffffffff },
10358                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10359                         0x00000000, 0xffffffff },
10360                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10361                         0x00000000, 0xffffffff },
10362                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10363                         0x00000000, 0xffffffff },
10364                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10365                         0xffffffff, 0x00000000 },
10366                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10367                         0xffffffff, 0x00000000 },
10368
10369                 /* Buffer Manager Control Registers. */
10370                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10371                         0x00000000, 0x007fff80 },
10372                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10373                         0x00000000, 0x007fffff },
10374                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10375                         0x00000000, 0x0000003f },
10376                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10377                         0x00000000, 0x000001ff },
10378                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10379                         0x00000000, 0x000001ff },
10380                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10381                         0xffffffff, 0x00000000 },
10382                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10383                         0xffffffff, 0x00000000 },
10384
10385                 /* Mailbox Registers */
10386                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10387                         0x00000000, 0x000001ff },
10388                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10389                         0x00000000, 0x000001ff },
10390                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10391                         0x00000000, 0x000007ff },
10392                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10393                         0x00000000, 0x000001ff },
10394
10395                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10396         };
10397
10398         is_5705 = is_5750 = 0;
10399         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10400                 is_5705 = 1;
10401                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10402                         is_5750 = 1;
10403         }
10404
10405         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10406                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10407                         continue;
10408
10409                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10410                         continue;
10411
10412                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10413                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10414                         continue;
10415
10416                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10417                         continue;
10418
10419                 offset = (u32) reg_tbl[i].offset;
10420                 read_mask = reg_tbl[i].read_mask;
10421                 write_mask = reg_tbl[i].write_mask;
10422
10423                 /* Save the original register content */
10424                 save_val = tr32(offset);
10425
10426                 /* Determine the read-only value. */
10427                 read_val = save_val & read_mask;
10428
10429                 /* Write zero to the register, then make sure the read-only bits
10430                  * are not changed and the read/write bits are all zeros.
10431                  */
10432                 tw32(offset, 0);
10433
10434                 val = tr32(offset);
10435
10436                 /* Test the read-only and read/write bits. */
10437                 if (((val & read_mask) != read_val) || (val & write_mask))
10438                         goto out;
10439
10440                 /* Write ones to all the bits defined by RdMask and WrMask, then
10441                  * make sure the read-only bits are not changed and the
10442                  * read/write bits are all ones.
10443                  */
10444                 tw32(offset, read_mask | write_mask);
10445
10446                 val = tr32(offset);
10447
10448                 /* Test the read-only bits. */
10449                 if ((val & read_mask) != read_val)
10450                         goto out;
10451
10452                 /* Test the read/write bits. */
10453                 if ((val & write_mask) != write_mask)
10454                         goto out;
10455
10456                 tw32(offset, save_val);
10457         }
10458
10459         return 0;
10460
10461 out:
10462         if (netif_msg_hw(tp))
10463                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10464                        offset);
10465         tw32(offset, save_val);
10466         return -EIO;
10467 }
10468
10469 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10470 {
10471         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10472         int i;
10473         u32 j;
10474
10475         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10476                 for (j = 0; j < len; j += 4) {
10477                         u32 val;
10478
10479                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10480                         tg3_read_mem(tp, offset + j, &val);
10481                         if (val != test_pattern[i])
10482                                 return -EIO;
10483                 }
10484         }
10485         return 0;
10486 }
10487
10488 static int tg3_test_memory(struct tg3 *tp)
10489 {
10490         static struct mem_entry {
10491                 u32 offset;
10492                 u32 len;
10493         } mem_tbl_570x[] = {
10494                 { 0x00000000, 0x00b50},
10495                 { 0x00002000, 0x1c000},
10496                 { 0xffffffff, 0x00000}
10497         }, mem_tbl_5705[] = {
10498                 { 0x00000100, 0x0000c},
10499                 { 0x00000200, 0x00008},
10500                 { 0x00004000, 0x00800},
10501                 { 0x00006000, 0x01000},
10502                 { 0x00008000, 0x02000},
10503                 { 0x00010000, 0x0e000},
10504                 { 0xffffffff, 0x00000}
10505         }, mem_tbl_5755[] = {
10506                 { 0x00000200, 0x00008},
10507                 { 0x00004000, 0x00800},
10508                 { 0x00006000, 0x00800},
10509                 { 0x00008000, 0x02000},
10510                 { 0x00010000, 0x0c000},
10511                 { 0xffffffff, 0x00000}
10512         }, mem_tbl_5906[] = {
10513                 { 0x00000200, 0x00008},
10514                 { 0x00004000, 0x00400},
10515                 { 0x00006000, 0x00400},
10516                 { 0x00008000, 0x01000},
10517                 { 0x00010000, 0x01000},
10518                 { 0xffffffff, 0x00000}
10519         };
10520         struct mem_entry *mem_tbl;
10521         int err = 0;
10522         int i;
10523
10524         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10525                 mem_tbl = mem_tbl_5755;
10526         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10527                 mem_tbl = mem_tbl_5906;
10528         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10529                 mem_tbl = mem_tbl_5705;
10530         else
10531                 mem_tbl = mem_tbl_570x;
10532
10533         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10534                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10535                     mem_tbl[i].len)) != 0)
10536                         break;
10537         }
10538
10539         return err;
10540 }
10541
10542 #define TG3_MAC_LOOPBACK        0
10543 #define TG3_PHY_LOOPBACK        1
10544
10545 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10546 {
10547         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10548         u32 desc_idx, coal_now;
10549         struct sk_buff *skb, *rx_skb;
10550         u8 *tx_data;
10551         dma_addr_t map;
10552         int num_pkts, tx_len, rx_len, i, err;
10553         struct tg3_rx_buffer_desc *desc;
10554         struct tg3_napi *tnapi, *rnapi;
10555         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10556
10557         if (tp->irq_cnt > 1) {
10558                 tnapi = &tp->napi[1];
10559                 rnapi = &tp->napi[1];
10560         } else {
10561                 tnapi = &tp->napi[0];
10562                 rnapi = &tp->napi[0];
10563         }
10564         coal_now = tnapi->coal_now | rnapi->coal_now;
10565
10566         if (loopback_mode == TG3_MAC_LOOPBACK) {
10567                 /* HW errata - mac loopback fails in some cases on 5780.
10568                  * Normal traffic and PHY loopback are not affected by
10569                  * errata.
10570                  */
10571                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10572                         return 0;
10573
10574                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10575                            MAC_MODE_PORT_INT_LPBACK;
10576                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10577                         mac_mode |= MAC_MODE_LINK_POLARITY;
10578                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10579                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10580                 else
10581                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10582                 tw32(MAC_MODE, mac_mode);
10583         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10584                 u32 val;
10585
10586                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10587                         tg3_phy_fet_toggle_apd(tp, false);
10588                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10589                 } else
10590                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10591
10592                 tg3_phy_toggle_automdix(tp, 0);
10593
10594                 tg3_writephy(tp, MII_BMCR, val);
10595                 udelay(40);
10596
10597                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10598                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10599                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10600                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10601                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10602                 } else
10603                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10604
10605                 /* reset to prevent losing 1st rx packet intermittently */
10606                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10607                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10608                         udelay(10);
10609                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10610                 }
10611                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10612                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10613                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10614                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10615                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10616                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10617                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10618                 }
10619                 tw32(MAC_MODE, mac_mode);
10620         }
10621         else
10622                 return -EINVAL;
10623
10624         err = -EIO;
10625
10626         tx_len = 1514;
10627         skb = netdev_alloc_skb(tp->dev, tx_len);
10628         if (!skb)
10629                 return -ENOMEM;
10630
10631         tx_data = skb_put(skb, tx_len);
10632         memcpy(tx_data, tp->dev->dev_addr, 6);
10633         memset(tx_data + 6, 0x0, 8);
10634
10635         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10636
10637         for (i = 14; i < tx_len; i++)
10638                 tx_data[i] = (u8) (i & 0xff);
10639
10640         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10641                 dev_kfree_skb(skb);
10642                 return -EIO;
10643         }
10644
10645         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10646                rnapi->coal_now);
10647
10648         udelay(10);
10649
10650         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10651
10652         num_pkts = 0;
10653
10654         tg3_set_txd(tnapi, tnapi->tx_prod,
10655                     skb_shinfo(skb)->dma_head, tx_len, 0, 1);
10656
10657         tnapi->tx_prod++;
10658         num_pkts++;
10659
10660         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10661         tr32_mailbox(tnapi->prodmbox);
10662
10663         udelay(10);
10664
10665         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10666         for (i = 0; i < 35; i++) {
10667                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10668                        coal_now);
10669
10670                 udelay(10);
10671
10672                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10673                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10674                 if ((tx_idx == tnapi->tx_prod) &&
10675                     (rx_idx == (rx_start_idx + num_pkts)))
10676                         break;
10677         }
10678
10679         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
10680         dev_kfree_skb(skb);
10681
10682         if (tx_idx != tnapi->tx_prod)
10683                 goto out;
10684
10685         if (rx_idx != rx_start_idx + num_pkts)
10686                 goto out;
10687
10688         desc = &rnapi->rx_rcb[rx_start_idx];
10689         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10690         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10691         if (opaque_key != RXD_OPAQUE_RING_STD)
10692                 goto out;
10693
10694         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10695             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10696                 goto out;
10697
10698         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10699         if (rx_len != tx_len)
10700                 goto out;
10701
10702         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10703
10704         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10705         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10706
10707         for (i = 14; i < tx_len; i++) {
10708                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10709                         goto out;
10710         }
10711         err = 0;
10712
10713         /* tg3_free_rings will unmap and free the rx_skb */
10714 out:
10715         return err;
10716 }
10717
10718 #define TG3_MAC_LOOPBACK_FAILED         1
10719 #define TG3_PHY_LOOPBACK_FAILED         2
10720 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10721                                          TG3_PHY_LOOPBACK_FAILED)
10722
10723 static int tg3_test_loopback(struct tg3 *tp)
10724 {
10725         int err = 0;
10726         u32 cpmuctrl = 0;
10727
10728         if (!netif_running(tp->dev))
10729                 return TG3_LOOPBACK_FAILED;
10730
10731         err = tg3_reset_hw(tp, 1);
10732         if (err)
10733                 return TG3_LOOPBACK_FAILED;
10734
10735         /* Turn off gphy autopowerdown. */
10736         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10737                 tg3_phy_toggle_apd(tp, false);
10738
10739         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10740                 int i;
10741                 u32 status;
10742
10743                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10744
10745                 /* Wait for up to 40 microseconds to acquire lock. */
10746                 for (i = 0; i < 4; i++) {
10747                         status = tr32(TG3_CPMU_MUTEX_GNT);
10748                         if (status == CPMU_MUTEX_GNT_DRIVER)
10749                                 break;
10750                         udelay(10);
10751                 }
10752
10753                 if (status != CPMU_MUTEX_GNT_DRIVER)
10754                         return TG3_LOOPBACK_FAILED;
10755
10756                 /* Turn off link-based power management. */
10757                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10758                 tw32(TG3_CPMU_CTRL,
10759                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10760                                   CPMU_CTRL_LINK_AWARE_MODE));
10761         }
10762
10763         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10764                 err |= TG3_MAC_LOOPBACK_FAILED;
10765
10766         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10767                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10768
10769                 /* Release the mutex */
10770                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10771         }
10772
10773         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10774             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10775                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10776                         err |= TG3_PHY_LOOPBACK_FAILED;
10777         }
10778
10779         /* Re-enable gphy autopowerdown. */
10780         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10781                 tg3_phy_toggle_apd(tp, true);
10782
10783         return err;
10784 }
10785
10786 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10787                           u64 *data)
10788 {
10789         struct tg3 *tp = netdev_priv(dev);
10790
10791         if (tp->link_config.phy_is_low_power)
10792                 tg3_set_power_state(tp, PCI_D0);
10793
10794         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10795
10796         if (tg3_test_nvram(tp) != 0) {
10797                 etest->flags |= ETH_TEST_FL_FAILED;
10798                 data[0] = 1;
10799         }
10800         if (tg3_test_link(tp) != 0) {
10801                 etest->flags |= ETH_TEST_FL_FAILED;
10802                 data[1] = 1;
10803         }
10804         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10805                 int err, err2 = 0, irq_sync = 0;
10806
10807                 if (netif_running(dev)) {
10808                         tg3_phy_stop(tp);
10809                         tg3_netif_stop(tp);
10810                         irq_sync = 1;
10811                 }
10812
10813                 tg3_full_lock(tp, irq_sync);
10814
10815                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10816                 err = tg3_nvram_lock(tp);
10817                 tg3_halt_cpu(tp, RX_CPU_BASE);
10818                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10819                         tg3_halt_cpu(tp, TX_CPU_BASE);
10820                 if (!err)
10821                         tg3_nvram_unlock(tp);
10822
10823                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10824                         tg3_phy_reset(tp);
10825
10826                 if (tg3_test_registers(tp) != 0) {
10827                         etest->flags |= ETH_TEST_FL_FAILED;
10828                         data[2] = 1;
10829                 }
10830                 if (tg3_test_memory(tp) != 0) {
10831                         etest->flags |= ETH_TEST_FL_FAILED;
10832                         data[3] = 1;
10833                 }
10834                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10835                         etest->flags |= ETH_TEST_FL_FAILED;
10836
10837                 tg3_full_unlock(tp);
10838
10839                 if (tg3_test_interrupt(tp) != 0) {
10840                         etest->flags |= ETH_TEST_FL_FAILED;
10841                         data[5] = 1;
10842                 }
10843
10844                 tg3_full_lock(tp, 0);
10845
10846                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10847                 if (netif_running(dev)) {
10848                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10849                         err2 = tg3_restart_hw(tp, 1);
10850                         if (!err2)
10851                                 tg3_netif_start(tp);
10852                 }
10853
10854                 tg3_full_unlock(tp);
10855
10856                 if (irq_sync && !err2)
10857                         tg3_phy_start(tp);
10858         }
10859         if (tp->link_config.phy_is_low_power)
10860                 tg3_set_power_state(tp, PCI_D3hot);
10861
10862 }
10863
10864 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10865 {
10866         struct mii_ioctl_data *data = if_mii(ifr);
10867         struct tg3 *tp = netdev_priv(dev);
10868         int err;
10869
10870         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10871                 struct phy_device *phydev;
10872                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10873                         return -EAGAIN;
10874                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10875                 return phy_mii_ioctl(phydev, data, cmd);
10876         }
10877
10878         switch(cmd) {
10879         case SIOCGMIIPHY:
10880                 data->phy_id = tp->phy_addr;
10881
10882                 /* fallthru */
10883         case SIOCGMIIREG: {
10884                 u32 mii_regval;
10885
10886                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10887                         break;                  /* We have no PHY */
10888
10889                 if (tp->link_config.phy_is_low_power)
10890                         return -EAGAIN;
10891
10892                 spin_lock_bh(&tp->lock);
10893                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10894                 spin_unlock_bh(&tp->lock);
10895
10896                 data->val_out = mii_regval;
10897
10898                 return err;
10899         }
10900
10901         case SIOCSMIIREG:
10902                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10903                         break;                  /* We have no PHY */
10904
10905                 if (tp->link_config.phy_is_low_power)
10906                         return -EAGAIN;
10907
10908                 spin_lock_bh(&tp->lock);
10909                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10910                 spin_unlock_bh(&tp->lock);
10911
10912                 return err;
10913
10914         default:
10915                 /* do nothing */
10916                 break;
10917         }
10918         return -EOPNOTSUPP;
10919 }
10920
10921 #if TG3_VLAN_TAG_USED
10922 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10923 {
10924         struct tg3 *tp = netdev_priv(dev);
10925
10926         if (!netif_running(dev)) {
10927                 tp->vlgrp = grp;
10928                 return;
10929         }
10930
10931         tg3_netif_stop(tp);
10932
10933         tg3_full_lock(tp, 0);
10934
10935         tp->vlgrp = grp;
10936
10937         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10938         __tg3_set_rx_mode(dev);
10939
10940         tg3_netif_start(tp);
10941
10942         tg3_full_unlock(tp);
10943 }
10944 #endif
10945
10946 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10947 {
10948         struct tg3 *tp = netdev_priv(dev);
10949
10950         memcpy(ec, &tp->coal, sizeof(*ec));
10951         return 0;
10952 }
10953
10954 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10955 {
10956         struct tg3 *tp = netdev_priv(dev);
10957         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10958         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10959
10960         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10961                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10962                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10963                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10964                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10965         }
10966
10967         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10968             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10969             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10970             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10971             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10972             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10973             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10974             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10975             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10976             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10977                 return -EINVAL;
10978
10979         /* No rx interrupts will be generated if both are zero */
10980         if ((ec->rx_coalesce_usecs == 0) &&
10981             (ec->rx_max_coalesced_frames == 0))
10982                 return -EINVAL;
10983
10984         /* No tx interrupts will be generated if both are zero */
10985         if ((ec->tx_coalesce_usecs == 0) &&
10986             (ec->tx_max_coalesced_frames == 0))
10987                 return -EINVAL;
10988
10989         /* Only copy relevant parameters, ignore all others. */
10990         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10991         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10992         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10993         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10994         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10995         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10996         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10997         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10998         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10999
11000         if (netif_running(dev)) {
11001                 tg3_full_lock(tp, 0);
11002                 __tg3_set_coalesce(tp, &tp->coal);
11003                 tg3_full_unlock(tp);
11004         }
11005         return 0;
11006 }
11007
11008 static const struct ethtool_ops tg3_ethtool_ops = {
11009         .get_settings           = tg3_get_settings,
11010         .set_settings           = tg3_set_settings,
11011         .get_drvinfo            = tg3_get_drvinfo,
11012         .get_regs_len           = tg3_get_regs_len,
11013         .get_regs               = tg3_get_regs,
11014         .get_wol                = tg3_get_wol,
11015         .set_wol                = tg3_set_wol,
11016         .get_msglevel           = tg3_get_msglevel,
11017         .set_msglevel           = tg3_set_msglevel,
11018         .nway_reset             = tg3_nway_reset,
11019         .get_link               = ethtool_op_get_link,
11020         .get_eeprom_len         = tg3_get_eeprom_len,
11021         .get_eeprom             = tg3_get_eeprom,
11022         .set_eeprom             = tg3_set_eeprom,
11023         .get_ringparam          = tg3_get_ringparam,
11024         .set_ringparam          = tg3_set_ringparam,
11025         .get_pauseparam         = tg3_get_pauseparam,
11026         .set_pauseparam         = tg3_set_pauseparam,
11027         .get_rx_csum            = tg3_get_rx_csum,
11028         .set_rx_csum            = tg3_set_rx_csum,
11029         .set_tx_csum            = tg3_set_tx_csum,
11030         .set_sg                 = ethtool_op_set_sg,
11031         .set_tso                = tg3_set_tso,
11032         .self_test              = tg3_self_test,
11033         .get_strings            = tg3_get_strings,
11034         .phys_id                = tg3_phys_id,
11035         .get_ethtool_stats      = tg3_get_ethtool_stats,
11036         .get_coalesce           = tg3_get_coalesce,
11037         .set_coalesce           = tg3_set_coalesce,
11038         .get_sset_count         = tg3_get_sset_count,
11039 };
11040
11041 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11042 {
11043         u32 cursize, val, magic;
11044
11045         tp->nvram_size = EEPROM_CHIP_SIZE;
11046
11047         if (tg3_nvram_read(tp, 0, &magic) != 0)
11048                 return;
11049
11050         if ((magic != TG3_EEPROM_MAGIC) &&
11051             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11052             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11053                 return;
11054
11055         /*
11056          * Size the chip by reading offsets at increasing powers of two.
11057          * When we encounter our validation signature, we know the addressing
11058          * has wrapped around, and thus have our chip size.
11059          */
11060         cursize = 0x10;
11061
11062         while (cursize < tp->nvram_size) {
11063                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11064                         return;
11065
11066                 if (val == magic)
11067                         break;
11068
11069                 cursize <<= 1;
11070         }
11071
11072         tp->nvram_size = cursize;
11073 }
11074
11075 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11076 {
11077         u32 val;
11078
11079         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11080             tg3_nvram_read(tp, 0, &val) != 0)
11081                 return;
11082
11083         /* Selfboot format */
11084         if (val != TG3_EEPROM_MAGIC) {
11085                 tg3_get_eeprom_size(tp);
11086                 return;
11087         }
11088
11089         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11090                 if (val != 0) {
11091                         /* This is confusing.  We want to operate on the
11092                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11093                          * call will read from NVRAM and byteswap the data
11094                          * according to the byteswapping settings for all
11095                          * other register accesses.  This ensures the data we
11096                          * want will always reside in the lower 16-bits.
11097                          * However, the data in NVRAM is in LE format, which
11098                          * means the data from the NVRAM read will always be
11099                          * opposite the endianness of the CPU.  The 16-bit
11100                          * byteswap then brings the data to CPU endianness.
11101                          */
11102                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11103                         return;
11104                 }
11105         }
11106         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11107 }
11108
11109 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11110 {
11111         u32 nvcfg1;
11112
11113         nvcfg1 = tr32(NVRAM_CFG1);
11114         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11115                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11116         } else {
11117                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11118                 tw32(NVRAM_CFG1, nvcfg1);
11119         }
11120
11121         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11122             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11123                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11124                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11125                         tp->nvram_jedecnum = JEDEC_ATMEL;
11126                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11127                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11128                         break;
11129                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11130                         tp->nvram_jedecnum = JEDEC_ATMEL;
11131                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11132                         break;
11133                 case FLASH_VENDOR_ATMEL_EEPROM:
11134                         tp->nvram_jedecnum = JEDEC_ATMEL;
11135                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11136                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11137                         break;
11138                 case FLASH_VENDOR_ST:
11139                         tp->nvram_jedecnum = JEDEC_ST;
11140                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11141                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11142                         break;
11143                 case FLASH_VENDOR_SAIFUN:
11144                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11145                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11146                         break;
11147                 case FLASH_VENDOR_SST_SMALL:
11148                 case FLASH_VENDOR_SST_LARGE:
11149                         tp->nvram_jedecnum = JEDEC_SST;
11150                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11151                         break;
11152                 }
11153         } else {
11154                 tp->nvram_jedecnum = JEDEC_ATMEL;
11155                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11156                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11157         }
11158 }
11159
11160 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11161 {
11162         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11163         case FLASH_5752PAGE_SIZE_256:
11164                 tp->nvram_pagesize = 256;
11165                 break;
11166         case FLASH_5752PAGE_SIZE_512:
11167                 tp->nvram_pagesize = 512;
11168                 break;
11169         case FLASH_5752PAGE_SIZE_1K:
11170                 tp->nvram_pagesize = 1024;
11171                 break;
11172         case FLASH_5752PAGE_SIZE_2K:
11173                 tp->nvram_pagesize = 2048;
11174                 break;
11175         case FLASH_5752PAGE_SIZE_4K:
11176                 tp->nvram_pagesize = 4096;
11177                 break;
11178         case FLASH_5752PAGE_SIZE_264:
11179                 tp->nvram_pagesize = 264;
11180                 break;
11181         case FLASH_5752PAGE_SIZE_528:
11182                 tp->nvram_pagesize = 528;
11183                 break;
11184         }
11185 }
11186
11187 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11188 {
11189         u32 nvcfg1;
11190
11191         nvcfg1 = tr32(NVRAM_CFG1);
11192
11193         /* NVRAM protection for TPM */
11194         if (nvcfg1 & (1 << 27))
11195                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11196
11197         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11198         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11199         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11200                 tp->nvram_jedecnum = JEDEC_ATMEL;
11201                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11202                 break;
11203         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11204                 tp->nvram_jedecnum = JEDEC_ATMEL;
11205                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11206                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11207                 break;
11208         case FLASH_5752VENDOR_ST_M45PE10:
11209         case FLASH_5752VENDOR_ST_M45PE20:
11210         case FLASH_5752VENDOR_ST_M45PE40:
11211                 tp->nvram_jedecnum = JEDEC_ST;
11212                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11213                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11214                 break;
11215         }
11216
11217         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11218                 tg3_nvram_get_pagesize(tp, nvcfg1);
11219         } else {
11220                 /* For eeprom, set pagesize to maximum eeprom size */
11221                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11222
11223                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11224                 tw32(NVRAM_CFG1, nvcfg1);
11225         }
11226 }
11227
11228 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11229 {
11230         u32 nvcfg1, protect = 0;
11231
11232         nvcfg1 = tr32(NVRAM_CFG1);
11233
11234         /* NVRAM protection for TPM */
11235         if (nvcfg1 & (1 << 27)) {
11236                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11237                 protect = 1;
11238         }
11239
11240         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11241         switch (nvcfg1) {
11242         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11243         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11244         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11245         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11246                 tp->nvram_jedecnum = JEDEC_ATMEL;
11247                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11248                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11249                 tp->nvram_pagesize = 264;
11250                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11251                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11252                         tp->nvram_size = (protect ? 0x3e200 :
11253                                           TG3_NVRAM_SIZE_512KB);
11254                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11255                         tp->nvram_size = (protect ? 0x1f200 :
11256                                           TG3_NVRAM_SIZE_256KB);
11257                 else
11258                         tp->nvram_size = (protect ? 0x1f200 :
11259                                           TG3_NVRAM_SIZE_128KB);
11260                 break;
11261         case FLASH_5752VENDOR_ST_M45PE10:
11262         case FLASH_5752VENDOR_ST_M45PE20:
11263         case FLASH_5752VENDOR_ST_M45PE40:
11264                 tp->nvram_jedecnum = JEDEC_ST;
11265                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11266                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11267                 tp->nvram_pagesize = 256;
11268                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11269                         tp->nvram_size = (protect ?
11270                                           TG3_NVRAM_SIZE_64KB :
11271                                           TG3_NVRAM_SIZE_128KB);
11272                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11273                         tp->nvram_size = (protect ?
11274                                           TG3_NVRAM_SIZE_64KB :
11275                                           TG3_NVRAM_SIZE_256KB);
11276                 else
11277                         tp->nvram_size = (protect ?
11278                                           TG3_NVRAM_SIZE_128KB :
11279                                           TG3_NVRAM_SIZE_512KB);
11280                 break;
11281         }
11282 }
11283
11284 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11285 {
11286         u32 nvcfg1;
11287
11288         nvcfg1 = tr32(NVRAM_CFG1);
11289
11290         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11291         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11292         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11293         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11294         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11295                 tp->nvram_jedecnum = JEDEC_ATMEL;
11296                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11297                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11298
11299                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11300                 tw32(NVRAM_CFG1, nvcfg1);
11301                 break;
11302         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11303         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11304         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11305         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11306                 tp->nvram_jedecnum = JEDEC_ATMEL;
11307                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11308                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11309                 tp->nvram_pagesize = 264;
11310                 break;
11311         case FLASH_5752VENDOR_ST_M45PE10:
11312         case FLASH_5752VENDOR_ST_M45PE20:
11313         case FLASH_5752VENDOR_ST_M45PE40:
11314                 tp->nvram_jedecnum = JEDEC_ST;
11315                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11316                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11317                 tp->nvram_pagesize = 256;
11318                 break;
11319         }
11320 }
11321
11322 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11323 {
11324         u32 nvcfg1, protect = 0;
11325
11326         nvcfg1 = tr32(NVRAM_CFG1);
11327
11328         /* NVRAM protection for TPM */
11329         if (nvcfg1 & (1 << 27)) {
11330                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11331                 protect = 1;
11332         }
11333
11334         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11335         switch (nvcfg1) {
11336         case FLASH_5761VENDOR_ATMEL_ADB021D:
11337         case FLASH_5761VENDOR_ATMEL_ADB041D:
11338         case FLASH_5761VENDOR_ATMEL_ADB081D:
11339         case FLASH_5761VENDOR_ATMEL_ADB161D:
11340         case FLASH_5761VENDOR_ATMEL_MDB021D:
11341         case FLASH_5761VENDOR_ATMEL_MDB041D:
11342         case FLASH_5761VENDOR_ATMEL_MDB081D:
11343         case FLASH_5761VENDOR_ATMEL_MDB161D:
11344                 tp->nvram_jedecnum = JEDEC_ATMEL;
11345                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11346                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11347                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11348                 tp->nvram_pagesize = 256;
11349                 break;
11350         case FLASH_5761VENDOR_ST_A_M45PE20:
11351         case FLASH_5761VENDOR_ST_A_M45PE40:
11352         case FLASH_5761VENDOR_ST_A_M45PE80:
11353         case FLASH_5761VENDOR_ST_A_M45PE16:
11354         case FLASH_5761VENDOR_ST_M_M45PE20:
11355         case FLASH_5761VENDOR_ST_M_M45PE40:
11356         case FLASH_5761VENDOR_ST_M_M45PE80:
11357         case FLASH_5761VENDOR_ST_M_M45PE16:
11358                 tp->nvram_jedecnum = JEDEC_ST;
11359                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11360                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11361                 tp->nvram_pagesize = 256;
11362                 break;
11363         }
11364
11365         if (protect) {
11366                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11367         } else {
11368                 switch (nvcfg1) {
11369                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11370                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11371                 case FLASH_5761VENDOR_ST_A_M45PE16:
11372                 case FLASH_5761VENDOR_ST_M_M45PE16:
11373                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11374                         break;
11375                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11376                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11377                 case FLASH_5761VENDOR_ST_A_M45PE80:
11378                 case FLASH_5761VENDOR_ST_M_M45PE80:
11379                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11380                         break;
11381                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11382                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11383                 case FLASH_5761VENDOR_ST_A_M45PE40:
11384                 case FLASH_5761VENDOR_ST_M_M45PE40:
11385                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11386                         break;
11387                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11388                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11389                 case FLASH_5761VENDOR_ST_A_M45PE20:
11390                 case FLASH_5761VENDOR_ST_M_M45PE20:
11391                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11392                         break;
11393                 }
11394         }
11395 }
11396
11397 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11398 {
11399         tp->nvram_jedecnum = JEDEC_ATMEL;
11400         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11401         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11402 }
11403
11404 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11405 {
11406         u32 nvcfg1;
11407
11408         nvcfg1 = tr32(NVRAM_CFG1);
11409
11410         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11411         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11412         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11413                 tp->nvram_jedecnum = JEDEC_ATMEL;
11414                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11415                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11416
11417                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11418                 tw32(NVRAM_CFG1, nvcfg1);
11419                 return;
11420         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11421         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11422         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11423         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11424         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11425         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11426         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11427                 tp->nvram_jedecnum = JEDEC_ATMEL;
11428                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11429                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11430
11431                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11432                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11433                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11434                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11435                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11436                         break;
11437                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11438                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11439                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11440                         break;
11441                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11442                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11443                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11444                         break;
11445                 }
11446                 break;
11447         case FLASH_5752VENDOR_ST_M45PE10:
11448         case FLASH_5752VENDOR_ST_M45PE20:
11449         case FLASH_5752VENDOR_ST_M45PE40:
11450                 tp->nvram_jedecnum = JEDEC_ST;
11451                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11452                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11453
11454                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11455                 case FLASH_5752VENDOR_ST_M45PE10:
11456                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11457                         break;
11458                 case FLASH_5752VENDOR_ST_M45PE20:
11459                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11460                         break;
11461                 case FLASH_5752VENDOR_ST_M45PE40:
11462                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11463                         break;
11464                 }
11465                 break;
11466         default:
11467                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11468                 return;
11469         }
11470
11471         tg3_nvram_get_pagesize(tp, nvcfg1);
11472         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11473                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11474 }
11475
11476
11477 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11478 {
11479         u32 nvcfg1;
11480
11481         nvcfg1 = tr32(NVRAM_CFG1);
11482
11483         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11484         case FLASH_5717VENDOR_ATMEL_EEPROM:
11485         case FLASH_5717VENDOR_MICRO_EEPROM:
11486                 tp->nvram_jedecnum = JEDEC_ATMEL;
11487                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11488                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11489
11490                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11491                 tw32(NVRAM_CFG1, nvcfg1);
11492                 return;
11493         case FLASH_5717VENDOR_ATMEL_MDB011D:
11494         case FLASH_5717VENDOR_ATMEL_ADB011B:
11495         case FLASH_5717VENDOR_ATMEL_ADB011D:
11496         case FLASH_5717VENDOR_ATMEL_MDB021D:
11497         case FLASH_5717VENDOR_ATMEL_ADB021B:
11498         case FLASH_5717VENDOR_ATMEL_ADB021D:
11499         case FLASH_5717VENDOR_ATMEL_45USPT:
11500                 tp->nvram_jedecnum = JEDEC_ATMEL;
11501                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11502                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11503
11504                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11505                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11506                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11507                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11508                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11509                         break;
11510                 default:
11511                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11512                         break;
11513                 }
11514                 break;
11515         case FLASH_5717VENDOR_ST_M_M25PE10:
11516         case FLASH_5717VENDOR_ST_A_M25PE10:
11517         case FLASH_5717VENDOR_ST_M_M45PE10:
11518         case FLASH_5717VENDOR_ST_A_M45PE10:
11519         case FLASH_5717VENDOR_ST_M_M25PE20:
11520         case FLASH_5717VENDOR_ST_A_M25PE20:
11521         case FLASH_5717VENDOR_ST_M_M45PE20:
11522         case FLASH_5717VENDOR_ST_A_M45PE20:
11523         case FLASH_5717VENDOR_ST_25USPT:
11524         case FLASH_5717VENDOR_ST_45USPT:
11525                 tp->nvram_jedecnum = JEDEC_ST;
11526                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11527                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11528
11529                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11530                 case FLASH_5717VENDOR_ST_M_M25PE20:
11531                 case FLASH_5717VENDOR_ST_A_M25PE20:
11532                 case FLASH_5717VENDOR_ST_M_M45PE20:
11533                 case FLASH_5717VENDOR_ST_A_M45PE20:
11534                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11535                         break;
11536                 default:
11537                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11538                         break;
11539                 }
11540                 break;
11541         default:
11542                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11543                 return;
11544         }
11545
11546         tg3_nvram_get_pagesize(tp, nvcfg1);
11547         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11548                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11549 }
11550
11551 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11552 static void __devinit tg3_nvram_init(struct tg3 *tp)
11553 {
11554         tw32_f(GRC_EEPROM_ADDR,
11555              (EEPROM_ADDR_FSM_RESET |
11556               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11557                EEPROM_ADDR_CLKPERD_SHIFT)));
11558
11559         msleep(1);
11560
11561         /* Enable seeprom accesses. */
11562         tw32_f(GRC_LOCAL_CTRL,
11563              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11564         udelay(100);
11565
11566         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11567             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11568                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11569
11570                 if (tg3_nvram_lock(tp)) {
11571                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11572                                "tg3_nvram_init failed.\n", tp->dev->name);
11573                         return;
11574                 }
11575                 tg3_enable_nvram_access(tp);
11576
11577                 tp->nvram_size = 0;
11578
11579                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11580                         tg3_get_5752_nvram_info(tp);
11581                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11582                         tg3_get_5755_nvram_info(tp);
11583                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11584                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11585                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11586                         tg3_get_5787_nvram_info(tp);
11587                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11588                         tg3_get_5761_nvram_info(tp);
11589                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11590                         tg3_get_5906_nvram_info(tp);
11591                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11592                         tg3_get_57780_nvram_info(tp);
11593                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11594                         tg3_get_5717_nvram_info(tp);
11595                 else
11596                         tg3_get_nvram_info(tp);
11597
11598                 if (tp->nvram_size == 0)
11599                         tg3_get_nvram_size(tp);
11600
11601                 tg3_disable_nvram_access(tp);
11602                 tg3_nvram_unlock(tp);
11603
11604         } else {
11605                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11606
11607                 tg3_get_eeprom_size(tp);
11608         }
11609 }
11610
11611 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11612                                     u32 offset, u32 len, u8 *buf)
11613 {
11614         int i, j, rc = 0;
11615         u32 val;
11616
11617         for (i = 0; i < len; i += 4) {
11618                 u32 addr;
11619                 __be32 data;
11620
11621                 addr = offset + i;
11622
11623                 memcpy(&data, buf + i, 4);
11624
11625                 /*
11626                  * The SEEPROM interface expects the data to always be opposite
11627                  * the native endian format.  We accomplish this by reversing
11628                  * all the operations that would have been performed on the
11629                  * data from a call to tg3_nvram_read_be32().
11630                  */
11631                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11632
11633                 val = tr32(GRC_EEPROM_ADDR);
11634                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11635
11636                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11637                         EEPROM_ADDR_READ);
11638                 tw32(GRC_EEPROM_ADDR, val |
11639                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11640                         (addr & EEPROM_ADDR_ADDR_MASK) |
11641                         EEPROM_ADDR_START |
11642                         EEPROM_ADDR_WRITE);
11643
11644                 for (j = 0; j < 1000; j++) {
11645                         val = tr32(GRC_EEPROM_ADDR);
11646
11647                         if (val & EEPROM_ADDR_COMPLETE)
11648                                 break;
11649                         msleep(1);
11650                 }
11651                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11652                         rc = -EBUSY;
11653                         break;
11654                 }
11655         }
11656
11657         return rc;
11658 }
11659
11660 /* offset and length are dword aligned */
11661 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11662                 u8 *buf)
11663 {
11664         int ret = 0;
11665         u32 pagesize = tp->nvram_pagesize;
11666         u32 pagemask = pagesize - 1;
11667         u32 nvram_cmd;
11668         u8 *tmp;
11669
11670         tmp = kmalloc(pagesize, GFP_KERNEL);
11671         if (tmp == NULL)
11672                 return -ENOMEM;
11673
11674         while (len) {
11675                 int j;
11676                 u32 phy_addr, page_off, size;
11677
11678                 phy_addr = offset & ~pagemask;
11679
11680                 for (j = 0; j < pagesize; j += 4) {
11681                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11682                                                   (__be32 *) (tmp + j));
11683                         if (ret)
11684                                 break;
11685                 }
11686                 if (ret)
11687                         break;
11688
11689                 page_off = offset & pagemask;
11690                 size = pagesize;
11691                 if (len < size)
11692                         size = len;
11693
11694                 len -= size;
11695
11696                 memcpy(tmp + page_off, buf, size);
11697
11698                 offset = offset + (pagesize - page_off);
11699
11700                 tg3_enable_nvram_access(tp);
11701
11702                 /*
11703                  * Before we can erase the flash page, we need
11704                  * to issue a special "write enable" command.
11705                  */
11706                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11707
11708                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11709                         break;
11710
11711                 /* Erase the target page */
11712                 tw32(NVRAM_ADDR, phy_addr);
11713
11714                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11715                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11716
11717                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11718                         break;
11719
11720                 /* Issue another write enable to start the write. */
11721                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11722
11723                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11724                         break;
11725
11726                 for (j = 0; j < pagesize; j += 4) {
11727                         __be32 data;
11728
11729                         data = *((__be32 *) (tmp + j));
11730
11731                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11732
11733                         tw32(NVRAM_ADDR, phy_addr + j);
11734
11735                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11736                                 NVRAM_CMD_WR;
11737
11738                         if (j == 0)
11739                                 nvram_cmd |= NVRAM_CMD_FIRST;
11740                         else if (j == (pagesize - 4))
11741                                 nvram_cmd |= NVRAM_CMD_LAST;
11742
11743                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11744                                 break;
11745                 }
11746                 if (ret)
11747                         break;
11748         }
11749
11750         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11751         tg3_nvram_exec_cmd(tp, nvram_cmd);
11752
11753         kfree(tmp);
11754
11755         return ret;
11756 }
11757
11758 /* offset and length are dword aligned */
11759 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11760                 u8 *buf)
11761 {
11762         int i, ret = 0;
11763
11764         for (i = 0; i < len; i += 4, offset += 4) {
11765                 u32 page_off, phy_addr, nvram_cmd;
11766                 __be32 data;
11767
11768                 memcpy(&data, buf + i, 4);
11769                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11770
11771                 page_off = offset % tp->nvram_pagesize;
11772
11773                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11774
11775                 tw32(NVRAM_ADDR, phy_addr);
11776
11777                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11778
11779                 if ((page_off == 0) || (i == 0))
11780                         nvram_cmd |= NVRAM_CMD_FIRST;
11781                 if (page_off == (tp->nvram_pagesize - 4))
11782                         nvram_cmd |= NVRAM_CMD_LAST;
11783
11784                 if (i == (len - 4))
11785                         nvram_cmd |= NVRAM_CMD_LAST;
11786
11787                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11788                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11789                     (tp->nvram_jedecnum == JEDEC_ST) &&
11790                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11791
11792                         if ((ret = tg3_nvram_exec_cmd(tp,
11793                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11794                                 NVRAM_CMD_DONE)))
11795
11796                                 break;
11797                 }
11798                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11799                         /* We always do complete word writes to eeprom. */
11800                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11801                 }
11802
11803                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11804                         break;
11805         }
11806         return ret;
11807 }
11808
11809 /* offset and length are dword aligned */
11810 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11811 {
11812         int ret;
11813
11814         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11815                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11816                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11817                 udelay(40);
11818         }
11819
11820         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11821                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11822         }
11823         else {
11824                 u32 grc_mode;
11825
11826                 ret = tg3_nvram_lock(tp);
11827                 if (ret)
11828                         return ret;
11829
11830                 tg3_enable_nvram_access(tp);
11831                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11832                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11833                         tw32(NVRAM_WRITE1, 0x406);
11834
11835                 grc_mode = tr32(GRC_MODE);
11836                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11837
11838                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11839                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11840
11841                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11842                                 buf);
11843                 }
11844                 else {
11845                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11846                                 buf);
11847                 }
11848
11849                 grc_mode = tr32(GRC_MODE);
11850                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11851
11852                 tg3_disable_nvram_access(tp);
11853                 tg3_nvram_unlock(tp);
11854         }
11855
11856         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11857                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11858                 udelay(40);
11859         }
11860
11861         return ret;
11862 }
11863
11864 struct subsys_tbl_ent {
11865         u16 subsys_vendor, subsys_devid;
11866         u32 phy_id;
11867 };
11868
11869 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11870         /* Broadcom boards. */
11871         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11872         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11873         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11874         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11875         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11876         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11877         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11878         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11879         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11880         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11881         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11882
11883         /* 3com boards. */
11884         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11885         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11886         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11887         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11888         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11889
11890         /* DELL boards. */
11891         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11892         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11893         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11894         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11895
11896         /* Compaq boards. */
11897         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11898         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11899         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11900         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11901         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11902
11903         /* IBM boards. */
11904         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11905 };
11906
11907 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11908 {
11909         int i;
11910
11911         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11912                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11913                      tp->pdev->subsystem_vendor) &&
11914                     (subsys_id_to_phy_id[i].subsys_devid ==
11915                      tp->pdev->subsystem_device))
11916                         return &subsys_id_to_phy_id[i];
11917         }
11918         return NULL;
11919 }
11920
11921 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11922 {
11923         u32 val;
11924         u16 pmcsr;
11925
11926         /* On some early chips the SRAM cannot be accessed in D3hot state,
11927          * so need make sure we're in D0.
11928          */
11929         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11930         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11931         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11932         msleep(1);
11933
11934         /* Make sure register accesses (indirect or otherwise)
11935          * will function correctly.
11936          */
11937         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11938                                tp->misc_host_ctrl);
11939
11940         /* The memory arbiter has to be enabled in order for SRAM accesses
11941          * to succeed.  Normally on powerup the tg3 chip firmware will make
11942          * sure it is enabled, but other entities such as system netboot
11943          * code might disable it.
11944          */
11945         val = tr32(MEMARB_MODE);
11946         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11947
11948         tp->phy_id = PHY_ID_INVALID;
11949         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11950
11951         /* Assume an onboard device and WOL capable by default.  */
11952         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11953
11954         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11955                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11956                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11957                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11958                 }
11959                 val = tr32(VCPU_CFGSHDW);
11960                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11961                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11962                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11963                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11964                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11965                 goto done;
11966         }
11967
11968         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11969         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11970                 u32 nic_cfg, led_cfg;
11971                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11972                 int eeprom_phy_serdes = 0;
11973
11974                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11975                 tp->nic_sram_data_cfg = nic_cfg;
11976
11977                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11978                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11979                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11980                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11981                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11982                     (ver > 0) && (ver < 0x100))
11983                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11984
11985                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11986                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11987
11988                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11989                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11990                         eeprom_phy_serdes = 1;
11991
11992                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11993                 if (nic_phy_id != 0) {
11994                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11995                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11996
11997                         eeprom_phy_id  = (id1 >> 16) << 10;
11998                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11999                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12000                 } else
12001                         eeprom_phy_id = 0;
12002
12003                 tp->phy_id = eeprom_phy_id;
12004                 if (eeprom_phy_serdes) {
12005                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
12006                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12007                         else
12008                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12009                 }
12010
12011                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12012                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12013                                     SHASTA_EXT_LED_MODE_MASK);
12014                 else
12015                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12016
12017                 switch (led_cfg) {
12018                 default:
12019                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12020                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12021                         break;
12022
12023                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12024                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12025                         break;
12026
12027                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12028                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12029
12030                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12031                          * read on some older 5700/5701 bootcode.
12032                          */
12033                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12034                             ASIC_REV_5700 ||
12035                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12036                             ASIC_REV_5701)
12037                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12038
12039                         break;
12040
12041                 case SHASTA_EXT_LED_SHARED:
12042                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12043                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12044                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12045                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12046                                                  LED_CTRL_MODE_PHY_2);
12047                         break;
12048
12049                 case SHASTA_EXT_LED_MAC:
12050                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12051                         break;
12052
12053                 case SHASTA_EXT_LED_COMBO:
12054                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12055                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12056                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12057                                                  LED_CTRL_MODE_PHY_2);
12058                         break;
12059
12060                 }
12061
12062                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12063                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12064                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12065                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12066
12067                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12068                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12069
12070                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12071                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12072                         if ((tp->pdev->subsystem_vendor ==
12073                              PCI_VENDOR_ID_ARIMA) &&
12074                             (tp->pdev->subsystem_device == 0x205a ||
12075                              tp->pdev->subsystem_device == 0x2063))
12076                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12077                 } else {
12078                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12079                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12080                 }
12081
12082                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12083                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12084                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12085                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12086                 }
12087
12088                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12089                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12090                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12091
12092                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12093                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12094                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12095
12096                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12097                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12098                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12099
12100                 if (cfg2 & (1 << 17))
12101                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12102
12103                 /* serdes signal pre-emphasis in register 0x590 set by */
12104                 /* bootcode if bit 18 is set */
12105                 if (cfg2 & (1 << 18))
12106                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12107
12108                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12109                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12110                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12111                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12112
12113                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12114                         u32 cfg3;
12115
12116                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12117                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12118                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12119                 }
12120
12121                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12122                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12123                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12124                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12125                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12126                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12127         }
12128 done:
12129         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12130         device_set_wakeup_enable(&tp->pdev->dev,
12131                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12132 }
12133
12134 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12135 {
12136         int i;
12137         u32 val;
12138
12139         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12140         tw32(OTP_CTRL, cmd);
12141
12142         /* Wait for up to 1 ms for command to execute. */
12143         for (i = 0; i < 100; i++) {
12144                 val = tr32(OTP_STATUS);
12145                 if (val & OTP_STATUS_CMD_DONE)
12146                         break;
12147                 udelay(10);
12148         }
12149
12150         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12151 }
12152
12153 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12154  * configuration is a 32-bit value that straddles the alignment boundary.
12155  * We do two 32-bit reads and then shift and merge the results.
12156  */
12157 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12158 {
12159         u32 bhalf_otp, thalf_otp;
12160
12161         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12162
12163         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12164                 return 0;
12165
12166         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12167
12168         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12169                 return 0;
12170
12171         thalf_otp = tr32(OTP_READ_DATA);
12172
12173         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12174
12175         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12176                 return 0;
12177
12178         bhalf_otp = tr32(OTP_READ_DATA);
12179
12180         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12181 }
12182
12183 static int __devinit tg3_phy_probe(struct tg3 *tp)
12184 {
12185         u32 hw_phy_id_1, hw_phy_id_2;
12186         u32 hw_phy_id, hw_phy_id_masked;
12187         int err;
12188
12189         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12190                 return tg3_phy_init(tp);
12191
12192         /* Reading the PHY ID register can conflict with ASF
12193          * firmware access to the PHY hardware.
12194          */
12195         err = 0;
12196         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12197             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12198                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12199         } else {
12200                 /* Now read the physical PHY_ID from the chip and verify
12201                  * that it is sane.  If it doesn't look good, we fall back
12202                  * to either the hard-coded table based PHY_ID and failing
12203                  * that the value found in the eeprom area.
12204                  */
12205                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12206                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12207
12208                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12209                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12210                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12211
12212                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12213         }
12214
12215         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12216                 tp->phy_id = hw_phy_id;
12217                 if (hw_phy_id_masked == PHY_ID_BCM8002)
12218                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12219                 else
12220                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12221         } else {
12222                 if (tp->phy_id != PHY_ID_INVALID) {
12223                         /* Do nothing, phy ID already set up in
12224                          * tg3_get_eeprom_hw_cfg().
12225                          */
12226                 } else {
12227                         struct subsys_tbl_ent *p;
12228
12229                         /* No eeprom signature?  Try the hardcoded
12230                          * subsys device table.
12231                          */
12232                         p = lookup_by_subsys(tp);
12233                         if (!p)
12234                                 return -ENODEV;
12235
12236                         tp->phy_id = p->phy_id;
12237                         if (!tp->phy_id ||
12238                             tp->phy_id == PHY_ID_BCM8002)
12239                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12240                 }
12241         }
12242
12243         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12244             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12245             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12246                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12247
12248                 tg3_readphy(tp, MII_BMSR, &bmsr);
12249                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12250                     (bmsr & BMSR_LSTATUS))
12251                         goto skip_phy_reset;
12252
12253                 err = tg3_phy_reset(tp);
12254                 if (err)
12255                         return err;
12256
12257                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12258                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12259                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12260                 tg3_ctrl = 0;
12261                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12262                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12263                                     MII_TG3_CTRL_ADV_1000_FULL);
12264                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12265                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12266                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12267                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12268                 }
12269
12270                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12271                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12272                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12273                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12274                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12275
12276                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12277                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12278
12279                         tg3_writephy(tp, MII_BMCR,
12280                                      BMCR_ANENABLE | BMCR_ANRESTART);
12281                 }
12282                 tg3_phy_set_wirespeed(tp);
12283
12284                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12285                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12286                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12287         }
12288
12289 skip_phy_reset:
12290         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12291                 err = tg3_init_5401phy_dsp(tp);
12292                 if (err)
12293                         return err;
12294         }
12295
12296         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12297                 err = tg3_init_5401phy_dsp(tp);
12298         }
12299
12300         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12301                 tp->link_config.advertising =
12302                         (ADVERTISED_1000baseT_Half |
12303                          ADVERTISED_1000baseT_Full |
12304                          ADVERTISED_Autoneg |
12305                          ADVERTISED_FIBRE);
12306         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12307                 tp->link_config.advertising &=
12308                         ~(ADVERTISED_1000baseT_Half |
12309                           ADVERTISED_1000baseT_Full);
12310
12311         return err;
12312 }
12313
12314 static void __devinit tg3_read_partno(struct tg3 *tp)
12315 {
12316         unsigned char vpd_data[256];   /* in little-endian format */
12317         unsigned int i;
12318         u32 magic;
12319
12320         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12321             tg3_nvram_read(tp, 0x0, &magic))
12322                 goto out_not_found;
12323
12324         if (magic == TG3_EEPROM_MAGIC) {
12325                 for (i = 0; i < 256; i += 4) {
12326                         u32 tmp;
12327
12328                         /* The data is in little-endian format in NVRAM.
12329                          * Use the big-endian read routines to preserve
12330                          * the byte order as it exists in NVRAM.
12331                          */
12332                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12333                                 goto out_not_found;
12334
12335                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12336                 }
12337         } else {
12338                 int vpd_cap;
12339
12340                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12341                 for (i = 0; i < 256; i += 4) {
12342                         u32 tmp, j = 0;
12343                         __le32 v;
12344                         u16 tmp16;
12345
12346                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12347                                               i);
12348                         while (j++ < 100) {
12349                                 pci_read_config_word(tp->pdev, vpd_cap +
12350                                                      PCI_VPD_ADDR, &tmp16);
12351                                 if (tmp16 & 0x8000)
12352                                         break;
12353                                 msleep(1);
12354                         }
12355                         if (!(tmp16 & 0x8000))
12356                                 goto out_not_found;
12357
12358                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12359                                               &tmp);
12360                         v = cpu_to_le32(tmp);
12361                         memcpy(&vpd_data[i], &v, sizeof(v));
12362                 }
12363         }
12364
12365         /* Now parse and find the part number. */
12366         for (i = 0; i < 254; ) {
12367                 unsigned char val = vpd_data[i];
12368                 unsigned int block_end;
12369
12370                 if (val == 0x82 || val == 0x91) {
12371                         i = (i + 3 +
12372                              (vpd_data[i + 1] +
12373                               (vpd_data[i + 2] << 8)));
12374                         continue;
12375                 }
12376
12377                 if (val != 0x90)
12378                         goto out_not_found;
12379
12380                 block_end = (i + 3 +
12381                              (vpd_data[i + 1] +
12382                               (vpd_data[i + 2] << 8)));
12383                 i += 3;
12384
12385                 if (block_end > 256)
12386                         goto out_not_found;
12387
12388                 while (i < (block_end - 2)) {
12389                         if (vpd_data[i + 0] == 'P' &&
12390                             vpd_data[i + 1] == 'N') {
12391                                 int partno_len = vpd_data[i + 2];
12392
12393                                 i += 3;
12394                                 if (partno_len > 24 || (partno_len + i) > 256)
12395                                         goto out_not_found;
12396
12397                                 memcpy(tp->board_part_number,
12398                                        &vpd_data[i], partno_len);
12399
12400                                 /* Success. */
12401                                 return;
12402                         }
12403                         i += 3 + vpd_data[i + 2];
12404                 }
12405
12406                 /* Part number not found. */
12407                 goto out_not_found;
12408         }
12409
12410 out_not_found:
12411         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12412                 strcpy(tp->board_part_number, "BCM95906");
12413         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12414                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12415                 strcpy(tp->board_part_number, "BCM57780");
12416         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12417                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12418                 strcpy(tp->board_part_number, "BCM57760");
12419         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12420                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12421                 strcpy(tp->board_part_number, "BCM57790");
12422         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12423                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12424                 strcpy(tp->board_part_number, "BCM57788");
12425         else
12426                 strcpy(tp->board_part_number, "none");
12427 }
12428
12429 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12430 {
12431         u32 val;
12432
12433         if (tg3_nvram_read(tp, offset, &val) ||
12434             (val & 0xfc000000) != 0x0c000000 ||
12435             tg3_nvram_read(tp, offset + 4, &val) ||
12436             val != 0)
12437                 return 0;
12438
12439         return 1;
12440 }
12441
12442 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12443 {
12444         u32 val, offset, start, ver_offset;
12445         int i;
12446         bool newver = false;
12447
12448         if (tg3_nvram_read(tp, 0xc, &offset) ||
12449             tg3_nvram_read(tp, 0x4, &start))
12450                 return;
12451
12452         offset = tg3_nvram_logical_addr(tp, offset);
12453
12454         if (tg3_nvram_read(tp, offset, &val))
12455                 return;
12456
12457         if ((val & 0xfc000000) == 0x0c000000) {
12458                 if (tg3_nvram_read(tp, offset + 4, &val))
12459                         return;
12460
12461                 if (val == 0)
12462                         newver = true;
12463         }
12464
12465         if (newver) {
12466                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12467                         return;
12468
12469                 offset = offset + ver_offset - start;
12470                 for (i = 0; i < 16; i += 4) {
12471                         __be32 v;
12472                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12473                                 return;
12474
12475                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12476                 }
12477         } else {
12478                 u32 major, minor;
12479
12480                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12481                         return;
12482
12483                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12484                         TG3_NVM_BCVER_MAJSFT;
12485                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12486                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12487         }
12488 }
12489
12490 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12491 {
12492         u32 val, major, minor;
12493
12494         /* Use native endian representation */
12495         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12496                 return;
12497
12498         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12499                 TG3_NVM_HWSB_CFG1_MAJSFT;
12500         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12501                 TG3_NVM_HWSB_CFG1_MINSFT;
12502
12503         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12504 }
12505
12506 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12507 {
12508         u32 offset, major, minor, build;
12509
12510         tp->fw_ver[0] = 's';
12511         tp->fw_ver[1] = 'b';
12512         tp->fw_ver[2] = '\0';
12513
12514         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12515                 return;
12516
12517         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12518         case TG3_EEPROM_SB_REVISION_0:
12519                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12520                 break;
12521         case TG3_EEPROM_SB_REVISION_2:
12522                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12523                 break;
12524         case TG3_EEPROM_SB_REVISION_3:
12525                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12526                 break;
12527         default:
12528                 return;
12529         }
12530
12531         if (tg3_nvram_read(tp, offset, &val))
12532                 return;
12533
12534         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12535                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12536         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12537                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12538         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12539
12540         if (minor > 99 || build > 26)
12541                 return;
12542
12543         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12544
12545         if (build > 0) {
12546                 tp->fw_ver[8] = 'a' + build - 1;
12547                 tp->fw_ver[9] = '\0';
12548         }
12549 }
12550
12551 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12552 {
12553         u32 val, offset, start;
12554         int i, vlen;
12555
12556         for (offset = TG3_NVM_DIR_START;
12557              offset < TG3_NVM_DIR_END;
12558              offset += TG3_NVM_DIRENT_SIZE) {
12559                 if (tg3_nvram_read(tp, offset, &val))
12560                         return;
12561
12562                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12563                         break;
12564         }
12565
12566         if (offset == TG3_NVM_DIR_END)
12567                 return;
12568
12569         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12570                 start = 0x08000000;
12571         else if (tg3_nvram_read(tp, offset - 4, &start))
12572                 return;
12573
12574         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12575             !tg3_fw_img_is_valid(tp, offset) ||
12576             tg3_nvram_read(tp, offset + 8, &val))
12577                 return;
12578
12579         offset += val - start;
12580
12581         vlen = strlen(tp->fw_ver);
12582
12583         tp->fw_ver[vlen++] = ',';
12584         tp->fw_ver[vlen++] = ' ';
12585
12586         for (i = 0; i < 4; i++) {
12587                 __be32 v;
12588                 if (tg3_nvram_read_be32(tp, offset, &v))
12589                         return;
12590
12591                 offset += sizeof(v);
12592
12593                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12594                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12595                         break;
12596                 }
12597
12598                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12599                 vlen += sizeof(v);
12600         }
12601 }
12602
12603 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12604 {
12605         int vlen;
12606         u32 apedata;
12607
12608         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12609             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12610                 return;
12611
12612         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12613         if (apedata != APE_SEG_SIG_MAGIC)
12614                 return;
12615
12616         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12617         if (!(apedata & APE_FW_STATUS_READY))
12618                 return;
12619
12620         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12621
12622         vlen = strlen(tp->fw_ver);
12623
12624         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12625                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12626                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12627                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12628                  (apedata & APE_FW_VERSION_BLDMSK));
12629 }
12630
12631 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12632 {
12633         u32 val;
12634
12635         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12636                 tp->fw_ver[0] = 's';
12637                 tp->fw_ver[1] = 'b';
12638                 tp->fw_ver[2] = '\0';
12639
12640                 return;
12641         }
12642
12643         if (tg3_nvram_read(tp, 0, &val))
12644                 return;
12645
12646         if (val == TG3_EEPROM_MAGIC)
12647                 tg3_read_bc_ver(tp);
12648         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12649                 tg3_read_sb_ver(tp, val);
12650         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12651                 tg3_read_hwsb_ver(tp);
12652         else
12653                 return;
12654
12655         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12656              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12657                 return;
12658
12659         tg3_read_mgmtfw_ver(tp);
12660
12661         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12662 }
12663
12664 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12665
12666 static int __devinit tg3_get_invariants(struct tg3 *tp)
12667 {
12668         static struct pci_device_id write_reorder_chipsets[] = {
12669                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12670                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12671                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12672                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12673                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12674                              PCI_DEVICE_ID_VIA_8385_0) },
12675                 { },
12676         };
12677         u32 misc_ctrl_reg;
12678         u32 pci_state_reg, grc_misc_cfg;
12679         u32 val;
12680         u16 pci_cmd;
12681         int err;
12682
12683         /* Force memory write invalidate off.  If we leave it on,
12684          * then on 5700_BX chips we have to enable a workaround.
12685          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12686          * to match the cacheline size.  The Broadcom driver have this
12687          * workaround but turns MWI off all the times so never uses
12688          * it.  This seems to suggest that the workaround is insufficient.
12689          */
12690         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12691         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12692         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12693
12694         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12695          * has the register indirect write enable bit set before
12696          * we try to access any of the MMIO registers.  It is also
12697          * critical that the PCI-X hw workaround situation is decided
12698          * before that as well.
12699          */
12700         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12701                               &misc_ctrl_reg);
12702
12703         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12704                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12705         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12706                 u32 prod_id_asic_rev;
12707
12708                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12709                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12710                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12711                         pci_read_config_dword(tp->pdev,
12712                                               TG3PCI_GEN2_PRODID_ASICREV,
12713                                               &prod_id_asic_rev);
12714                 else
12715                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12716                                               &prod_id_asic_rev);
12717
12718                 tp->pci_chip_rev_id = prod_id_asic_rev;
12719         }
12720
12721         /* Wrong chip ID in 5752 A0. This code can be removed later
12722          * as A0 is not in production.
12723          */
12724         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12725                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12726
12727         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12728          * we need to disable memory and use config. cycles
12729          * only to access all registers. The 5702/03 chips
12730          * can mistakenly decode the special cycles from the
12731          * ICH chipsets as memory write cycles, causing corruption
12732          * of register and memory space. Only certain ICH bridges
12733          * will drive special cycles with non-zero data during the
12734          * address phase which can fall within the 5703's address
12735          * range. This is not an ICH bug as the PCI spec allows
12736          * non-zero address during special cycles. However, only
12737          * these ICH bridges are known to drive non-zero addresses
12738          * during special cycles.
12739          *
12740          * Since special cycles do not cross PCI bridges, we only
12741          * enable this workaround if the 5703 is on the secondary
12742          * bus of these ICH bridges.
12743          */
12744         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12745             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12746                 static struct tg3_dev_id {
12747                         u32     vendor;
12748                         u32     device;
12749                         u32     rev;
12750                 } ich_chipsets[] = {
12751                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12752                           PCI_ANY_ID },
12753                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12754                           PCI_ANY_ID },
12755                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12756                           0xa },
12757                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12758                           PCI_ANY_ID },
12759                         { },
12760                 };
12761                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12762                 struct pci_dev *bridge = NULL;
12763
12764                 while (pci_id->vendor != 0) {
12765                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12766                                                 bridge);
12767                         if (!bridge) {
12768                                 pci_id++;
12769                                 continue;
12770                         }
12771                         if (pci_id->rev != PCI_ANY_ID) {
12772                                 if (bridge->revision > pci_id->rev)
12773                                         continue;
12774                         }
12775                         if (bridge->subordinate &&
12776                             (bridge->subordinate->number ==
12777                              tp->pdev->bus->number)) {
12778
12779                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12780                                 pci_dev_put(bridge);
12781                                 break;
12782                         }
12783                 }
12784         }
12785
12786         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12787                 static struct tg3_dev_id {
12788                         u32     vendor;
12789                         u32     device;
12790                 } bridge_chipsets[] = {
12791                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12792                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12793                         { },
12794                 };
12795                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12796                 struct pci_dev *bridge = NULL;
12797
12798                 while (pci_id->vendor != 0) {
12799                         bridge = pci_get_device(pci_id->vendor,
12800                                                 pci_id->device,
12801                                                 bridge);
12802                         if (!bridge) {
12803                                 pci_id++;
12804                                 continue;
12805                         }
12806                         if (bridge->subordinate &&
12807                             (bridge->subordinate->number <=
12808                              tp->pdev->bus->number) &&
12809                             (bridge->subordinate->subordinate >=
12810                              tp->pdev->bus->number)) {
12811                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12812                                 pci_dev_put(bridge);
12813                                 break;
12814                         }
12815                 }
12816         }
12817
12818         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12819          * DMA addresses > 40-bit. This bridge may have other additional
12820          * 57xx devices behind it in some 4-port NIC designs for example.
12821          * Any tg3 device found behind the bridge will also need the 40-bit
12822          * DMA workaround.
12823          */
12824         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12825             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12826                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12827                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12828                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12829         }
12830         else {
12831                 struct pci_dev *bridge = NULL;
12832
12833                 do {
12834                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12835                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12836                                                 bridge);
12837                         if (bridge && bridge->subordinate &&
12838                             (bridge->subordinate->number <=
12839                              tp->pdev->bus->number) &&
12840                             (bridge->subordinate->subordinate >=
12841                              tp->pdev->bus->number)) {
12842                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12843                                 pci_dev_put(bridge);
12844                                 break;
12845                         }
12846                 } while (bridge);
12847         }
12848
12849         /* Initialize misc host control in PCI block. */
12850         tp->misc_host_ctrl |= (misc_ctrl_reg &
12851                                MISC_HOST_CTRL_CHIPREV);
12852         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12853                                tp->misc_host_ctrl);
12854
12855         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12856             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12857             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12858                 tp->pdev_peer = tg3_find_peer(tp);
12859
12860         /* Intentionally exclude ASIC_REV_5906 */
12861         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12862             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12863             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12864             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12865             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12866             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12867             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12868                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12869
12870         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12871             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12872             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12873             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12874             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12875                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12876
12877         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12878             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12879                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12880
12881         /* 5700 B0 chips do not support checksumming correctly due
12882          * to hardware bugs.
12883          */
12884         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12885                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12886         else {
12887                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12888                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12889                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12890                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12891         }
12892
12893         /* Determine TSO capabilities */
12894         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12895                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12896         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12897                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12898                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12899         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12900                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12901                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12902                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12903                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12904         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12905                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12906                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12907                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12908                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12909                         tp->fw_needed = FIRMWARE_TG3TSO5;
12910                 else
12911                         tp->fw_needed = FIRMWARE_TG3TSO;
12912         }
12913
12914         tp->irq_max = 1;
12915
12916         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12917                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12918                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12919                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12920                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12921                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12922                      tp->pdev_peer == tp->pdev))
12923                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12924
12925                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12926                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12927                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12928                 }
12929
12930                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12931                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12932                         tp->irq_max = TG3_IRQ_MAX_VECS;
12933                 }
12934         }
12935
12936         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12937             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12938                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12939         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12940                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12941                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12942         }
12943
12944         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12945              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12946             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12947                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12948
12949         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12950                               &pci_state_reg);
12951
12952         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12953         if (tp->pcie_cap != 0) {
12954                 u16 lnkctl;
12955
12956                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12957
12958                 pcie_set_readrq(tp->pdev, 4096);
12959
12960                 pci_read_config_word(tp->pdev,
12961                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12962                                      &lnkctl);
12963                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12964                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12965                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12966                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12967                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12968                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12969                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12970                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12971                 }
12972         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12973                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12974         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12975                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12976                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12977                 if (!tp->pcix_cap) {
12978                         printk(KERN_ERR PFX "Cannot find PCI-X "
12979                                             "capability, aborting.\n");
12980                         return -EIO;
12981                 }
12982
12983                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12984                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12985         }
12986
12987         /* If we have an AMD 762 or VIA K8T800 chipset, write
12988          * reordering to the mailbox registers done by the host
12989          * controller can cause major troubles.  We read back from
12990          * every mailbox register write to force the writes to be
12991          * posted to the chip in order.
12992          */
12993         if (pci_dev_present(write_reorder_chipsets) &&
12994             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12995                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12996
12997         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12998                              &tp->pci_cacheline_sz);
12999         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13000                              &tp->pci_lat_timer);
13001         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13002             tp->pci_lat_timer < 64) {
13003                 tp->pci_lat_timer = 64;
13004                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13005                                       tp->pci_lat_timer);
13006         }
13007
13008         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13009                 /* 5700 BX chips need to have their TX producer index
13010                  * mailboxes written twice to workaround a bug.
13011                  */
13012                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13013
13014                 /* If we are in PCI-X mode, enable register write workaround.
13015                  *
13016                  * The workaround is to use indirect register accesses
13017                  * for all chip writes not to mailbox registers.
13018                  */
13019                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13020                         u32 pm_reg;
13021
13022                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13023
13024                         /* The chip can have it's power management PCI config
13025                          * space registers clobbered due to this bug.
13026                          * So explicitly force the chip into D0 here.
13027                          */
13028                         pci_read_config_dword(tp->pdev,
13029                                               tp->pm_cap + PCI_PM_CTRL,
13030                                               &pm_reg);
13031                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13032                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13033                         pci_write_config_dword(tp->pdev,
13034                                                tp->pm_cap + PCI_PM_CTRL,
13035                                                pm_reg);
13036
13037                         /* Also, force SERR#/PERR# in PCI command. */
13038                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13039                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13040                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13041                 }
13042         }
13043
13044         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13045                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13046         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13047                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13048
13049         /* Chip-specific fixup from Broadcom driver */
13050         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13051             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13052                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13053                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13054         }
13055
13056         /* Default fast path register access methods */
13057         tp->read32 = tg3_read32;
13058         tp->write32 = tg3_write32;
13059         tp->read32_mbox = tg3_read32;
13060         tp->write32_mbox = tg3_write32;
13061         tp->write32_tx_mbox = tg3_write32;
13062         tp->write32_rx_mbox = tg3_write32;
13063
13064         /* Various workaround register access methods */
13065         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13066                 tp->write32 = tg3_write_indirect_reg32;
13067         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13068                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13069                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13070                 /*
13071                  * Back to back register writes can cause problems on these
13072                  * chips, the workaround is to read back all reg writes
13073                  * except those to mailbox regs.
13074                  *
13075                  * See tg3_write_indirect_reg32().
13076                  */
13077                 tp->write32 = tg3_write_flush_reg32;
13078         }
13079
13080         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13081             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13082                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13083                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13084                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13085         }
13086
13087         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13088                 tp->read32 = tg3_read_indirect_reg32;
13089                 tp->write32 = tg3_write_indirect_reg32;
13090                 tp->read32_mbox = tg3_read_indirect_mbox;
13091                 tp->write32_mbox = tg3_write_indirect_mbox;
13092                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13093                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13094
13095                 iounmap(tp->regs);
13096                 tp->regs = NULL;
13097
13098                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13099                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13100                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13101         }
13102         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13103                 tp->read32_mbox = tg3_read32_mbox_5906;
13104                 tp->write32_mbox = tg3_write32_mbox_5906;
13105                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13106                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13107         }
13108
13109         if (tp->write32 == tg3_write_indirect_reg32 ||
13110             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13111              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13112               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13113                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13114
13115         /* Get eeprom hw config before calling tg3_set_power_state().
13116          * In particular, the TG3_FLG2_IS_NIC flag must be
13117          * determined before calling tg3_set_power_state() so that
13118          * we know whether or not to switch out of Vaux power.
13119          * When the flag is set, it means that GPIO1 is used for eeprom
13120          * write protect and also implies that it is a LOM where GPIOs
13121          * are not used to switch power.
13122          */
13123         tg3_get_eeprom_hw_cfg(tp);
13124
13125         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13126                 /* Allow reads and writes to the
13127                  * APE register and memory space.
13128                  */
13129                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13130                                  PCISTATE_ALLOW_APE_SHMEM_WR;
13131                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13132                                        pci_state_reg);
13133         }
13134
13135         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13136             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13137             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13138             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13139             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13140                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13141
13142         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13143          * GPIO1 driven high will bring 5700's external PHY out of reset.
13144          * It is also used as eeprom write protect on LOMs.
13145          */
13146         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13147         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13148             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13149                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13150                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13151         /* Unused GPIO3 must be driven as output on 5752 because there
13152          * are no pull-up resistors on unused GPIO pins.
13153          */
13154         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13155                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13156
13157         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13158             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13159                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13160
13161         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13162             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13163                 /* Turn off the debug UART. */
13164                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13165                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13166                         /* Keep VMain power. */
13167                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13168                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13169         }
13170
13171         /* Force the chip into D0. */
13172         err = tg3_set_power_state(tp, PCI_D0);
13173         if (err) {
13174                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13175                        pci_name(tp->pdev));
13176                 return err;
13177         }
13178
13179         /* Derive initial jumbo mode from MTU assigned in
13180          * ether_setup() via the alloc_etherdev() call
13181          */
13182         if (tp->dev->mtu > ETH_DATA_LEN &&
13183             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13184                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13185
13186         /* Determine WakeOnLan speed to use. */
13187         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13188             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13189             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13190             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13191                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13192         } else {
13193                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13194         }
13195
13196         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13197                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13198
13199         /* A few boards don't want Ethernet@WireSpeed phy feature */
13200         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13201             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13202              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13203              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13204             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13205             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13206                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13207
13208         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13209             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13210                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13211         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13212                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13213
13214         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13215             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13216             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13217             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13218             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13219                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13220                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13221                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13222                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13223                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13224                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13225                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13226                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13227                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13228                 } else
13229                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13230         }
13231
13232         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13233             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13234                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13235                 if (tp->phy_otp == 0)
13236                         tp->phy_otp = TG3_OTP_DEFAULT;
13237         }
13238
13239         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13240                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13241         else
13242                 tp->mi_mode = MAC_MI_MODE_BASE;
13243
13244         tp->coalesce_mode = 0;
13245         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13246             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13247                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13248
13249         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13250             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13251                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13252
13253         err = tg3_mdio_init(tp);
13254         if (err)
13255                 return err;
13256
13257         /* Initialize data/descriptor byte/word swapping. */
13258         val = tr32(GRC_MODE);
13259         val &= GRC_MODE_HOST_STACKUP;
13260         tw32(GRC_MODE, val | tp->grc_mode);
13261
13262         tg3_switch_clocks(tp);
13263
13264         /* Clear this out for sanity. */
13265         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13266
13267         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13268                               &pci_state_reg);
13269         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13270             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13271                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13272
13273                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13274                     chiprevid == CHIPREV_ID_5701_B0 ||
13275                     chiprevid == CHIPREV_ID_5701_B2 ||
13276                     chiprevid == CHIPREV_ID_5701_B5) {
13277                         void __iomem *sram_base;
13278
13279                         /* Write some dummy words into the SRAM status block
13280                          * area, see if it reads back correctly.  If the return
13281                          * value is bad, force enable the PCIX workaround.
13282                          */
13283                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13284
13285                         writel(0x00000000, sram_base);
13286                         writel(0x00000000, sram_base + 4);
13287                         writel(0xffffffff, sram_base + 4);
13288                         if (readl(sram_base) != 0x00000000)
13289                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13290                 }
13291         }
13292
13293         udelay(50);
13294         tg3_nvram_init(tp);
13295
13296         grc_misc_cfg = tr32(GRC_MISC_CFG);
13297         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13298
13299         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13300             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13301              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13302                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13303
13304         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13305             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13306                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13307         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13308                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13309                                       HOSTCC_MODE_CLRTICK_TXBD);
13310
13311                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13312                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13313                                        tp->misc_host_ctrl);
13314         }
13315
13316         /* Preserve the APE MAC_MODE bits */
13317         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13318                 tp->mac_mode = tr32(MAC_MODE) |
13319                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13320         else
13321                 tp->mac_mode = TG3_DEF_MAC_MODE;
13322
13323         /* these are limited to 10/100 only */
13324         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13325              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13326             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13327              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13328              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13329               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13330               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13331             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13332              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13333               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13334               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13335             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13336             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13337                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13338
13339         err = tg3_phy_probe(tp);
13340         if (err) {
13341                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13342                        pci_name(tp->pdev), err);
13343                 /* ... but do not return immediately ... */
13344                 tg3_mdio_fini(tp);
13345         }
13346
13347         tg3_read_partno(tp);
13348         tg3_read_fw_ver(tp);
13349
13350         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13351                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13352         } else {
13353                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13354                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13355                 else
13356                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13357         }
13358
13359         /* 5700 {AX,BX} chips have a broken status block link
13360          * change bit implementation, so we must use the
13361          * status register in those cases.
13362          */
13363         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13364                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13365         else
13366                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13367
13368         /* The led_ctrl is set during tg3_phy_probe, here we might
13369          * have to force the link status polling mechanism based
13370          * upon subsystem IDs.
13371          */
13372         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13373             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13374             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13375                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13376                                   TG3_FLAG_USE_LINKCHG_REG);
13377         }
13378
13379         /* For all SERDES we poll the MAC status register. */
13380         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13381                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13382         else
13383                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13384
13385         tp->rx_offset = NET_IP_ALIGN;
13386         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13387             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13388                 tp->rx_offset = 0;
13389
13390         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13391
13392         /* Increment the rx prod index on the rx std ring by at most
13393          * 8 for these chips to workaround hw errata.
13394          */
13395         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13396             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13397             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13398                 tp->rx_std_max_post = 8;
13399
13400         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13401                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13402                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13403
13404         return err;
13405 }
13406
13407 #ifdef CONFIG_SPARC
13408 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13409 {
13410         struct net_device *dev = tp->dev;
13411         struct pci_dev *pdev = tp->pdev;
13412         struct device_node *dp = pci_device_to_OF_node(pdev);
13413         const unsigned char *addr;
13414         int len;
13415
13416         addr = of_get_property(dp, "local-mac-address", &len);
13417         if (addr && len == 6) {
13418                 memcpy(dev->dev_addr, addr, 6);
13419                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13420                 return 0;
13421         }
13422         return -ENODEV;
13423 }
13424
13425 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13426 {
13427         struct net_device *dev = tp->dev;
13428
13429         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13430         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13431         return 0;
13432 }
13433 #endif
13434
13435 static int __devinit tg3_get_device_address(struct tg3 *tp)
13436 {
13437         struct net_device *dev = tp->dev;
13438         u32 hi, lo, mac_offset;
13439         int addr_ok = 0;
13440
13441 #ifdef CONFIG_SPARC
13442         if (!tg3_get_macaddr_sparc(tp))
13443                 return 0;
13444 #endif
13445
13446         mac_offset = 0x7c;
13447         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13448             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13449                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13450                         mac_offset = 0xcc;
13451                 if (tg3_nvram_lock(tp))
13452                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13453                 else
13454                         tg3_nvram_unlock(tp);
13455         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13456                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13457                         mac_offset = 0xcc;
13458         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13459                 mac_offset = 0x10;
13460
13461         /* First try to get it from MAC address mailbox. */
13462         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13463         if ((hi >> 16) == 0x484b) {
13464                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13465                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13466
13467                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13468                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13469                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13470                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13471                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13472
13473                 /* Some old bootcode may report a 0 MAC address in SRAM */
13474                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13475         }
13476         if (!addr_ok) {
13477                 /* Next, try NVRAM. */
13478                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13479                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13480                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13481                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13482                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13483                 }
13484                 /* Finally just fetch it out of the MAC control regs. */
13485                 else {
13486                         hi = tr32(MAC_ADDR_0_HIGH);
13487                         lo = tr32(MAC_ADDR_0_LOW);
13488
13489                         dev->dev_addr[5] = lo & 0xff;
13490                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13491                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13492                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13493                         dev->dev_addr[1] = hi & 0xff;
13494                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13495                 }
13496         }
13497
13498         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13499 #ifdef CONFIG_SPARC
13500                 if (!tg3_get_default_macaddr_sparc(tp))
13501                         return 0;
13502 #endif
13503                 return -EINVAL;
13504         }
13505         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13506         return 0;
13507 }
13508
13509 #define BOUNDARY_SINGLE_CACHELINE       1
13510 #define BOUNDARY_MULTI_CACHELINE        2
13511
13512 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13513 {
13514         int cacheline_size;
13515         u8 byte;
13516         int goal;
13517
13518         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13519         if (byte == 0)
13520                 cacheline_size = 1024;
13521         else
13522                 cacheline_size = (int) byte * 4;
13523
13524         /* On 5703 and later chips, the boundary bits have no
13525          * effect.
13526          */
13527         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13528             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13529             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13530                 goto out;
13531
13532 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13533         goal = BOUNDARY_MULTI_CACHELINE;
13534 #else
13535 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13536         goal = BOUNDARY_SINGLE_CACHELINE;
13537 #else
13538         goal = 0;
13539 #endif
13540 #endif
13541
13542         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13543                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13544                 goto out;
13545         }
13546
13547         if (!goal)
13548                 goto out;
13549
13550         /* PCI controllers on most RISC systems tend to disconnect
13551          * when a device tries to burst across a cache-line boundary.
13552          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13553          *
13554          * Unfortunately, for PCI-E there are only limited
13555          * write-side controls for this, and thus for reads
13556          * we will still get the disconnects.  We'll also waste
13557          * these PCI cycles for both read and write for chips
13558          * other than 5700 and 5701 which do not implement the
13559          * boundary bits.
13560          */
13561         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13562             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13563                 switch (cacheline_size) {
13564                 case 16:
13565                 case 32:
13566                 case 64:
13567                 case 128:
13568                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13569                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13570                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13571                         } else {
13572                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13573                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13574                         }
13575                         break;
13576
13577                 case 256:
13578                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13579                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13580                         break;
13581
13582                 default:
13583                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13584                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13585                         break;
13586                 }
13587         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13588                 switch (cacheline_size) {
13589                 case 16:
13590                 case 32:
13591                 case 64:
13592                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13593                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13594                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13595                                 break;
13596                         }
13597                         /* fallthrough */
13598                 case 128:
13599                 default:
13600                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13601                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13602                         break;
13603                 }
13604         } else {
13605                 switch (cacheline_size) {
13606                 case 16:
13607                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13608                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13609                                         DMA_RWCTRL_WRITE_BNDRY_16);
13610                                 break;
13611                         }
13612                         /* fallthrough */
13613                 case 32:
13614                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13615                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13616                                         DMA_RWCTRL_WRITE_BNDRY_32);
13617                                 break;
13618                         }
13619                         /* fallthrough */
13620                 case 64:
13621                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13622                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13623                                         DMA_RWCTRL_WRITE_BNDRY_64);
13624                                 break;
13625                         }
13626                         /* fallthrough */
13627                 case 128:
13628                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13629                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13630                                         DMA_RWCTRL_WRITE_BNDRY_128);
13631                                 break;
13632                         }
13633                         /* fallthrough */
13634                 case 256:
13635                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13636                                 DMA_RWCTRL_WRITE_BNDRY_256);
13637                         break;
13638                 case 512:
13639                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13640                                 DMA_RWCTRL_WRITE_BNDRY_512);
13641                         break;
13642                 case 1024:
13643                 default:
13644                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13645                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13646                         break;
13647                 }
13648         }
13649
13650 out:
13651         return val;
13652 }
13653
13654 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13655 {
13656         struct tg3_internal_buffer_desc test_desc;
13657         u32 sram_dma_descs;
13658         int i, ret;
13659
13660         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13661
13662         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13663         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13664         tw32(RDMAC_STATUS, 0);
13665         tw32(WDMAC_STATUS, 0);
13666
13667         tw32(BUFMGR_MODE, 0);
13668         tw32(FTQ_RESET, 0);
13669
13670         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13671         test_desc.addr_lo = buf_dma & 0xffffffff;
13672         test_desc.nic_mbuf = 0x00002100;
13673         test_desc.len = size;
13674
13675         /*
13676          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13677          * the *second* time the tg3 driver was getting loaded after an
13678          * initial scan.
13679          *
13680          * Broadcom tells me:
13681          *   ...the DMA engine is connected to the GRC block and a DMA
13682          *   reset may affect the GRC block in some unpredictable way...
13683          *   The behavior of resets to individual blocks has not been tested.
13684          *
13685          * Broadcom noted the GRC reset will also reset all sub-components.
13686          */
13687         if (to_device) {
13688                 test_desc.cqid_sqid = (13 << 8) | 2;
13689
13690                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13691                 udelay(40);
13692         } else {
13693                 test_desc.cqid_sqid = (16 << 8) | 7;
13694
13695                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13696                 udelay(40);
13697         }
13698         test_desc.flags = 0x00000005;
13699
13700         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13701                 u32 val;
13702
13703                 val = *(((u32 *)&test_desc) + i);
13704                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13705                                        sram_dma_descs + (i * sizeof(u32)));
13706                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13707         }
13708         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13709
13710         if (to_device) {
13711                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13712         } else {
13713                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13714         }
13715
13716         ret = -ENODEV;
13717         for (i = 0; i < 40; i++) {
13718                 u32 val;
13719
13720                 if (to_device)
13721                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13722                 else
13723                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13724                 if ((val & 0xffff) == sram_dma_descs) {
13725                         ret = 0;
13726                         break;
13727                 }
13728
13729                 udelay(100);
13730         }
13731
13732         return ret;
13733 }
13734
13735 #define TEST_BUFFER_SIZE        0x2000
13736
13737 static int __devinit tg3_test_dma(struct tg3 *tp)
13738 {
13739         dma_addr_t buf_dma;
13740         u32 *buf, saved_dma_rwctrl;
13741         int ret = 0;
13742
13743         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13744         if (!buf) {
13745                 ret = -ENOMEM;
13746                 goto out_nofree;
13747         }
13748
13749         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13750                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13751
13752         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13753
13754         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13755                 goto out;
13756
13757         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13758                 /* DMA read watermark not used on PCIE */
13759                 tp->dma_rwctrl |= 0x00180000;
13760         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13761                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13762                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13763                         tp->dma_rwctrl |= 0x003f0000;
13764                 else
13765                         tp->dma_rwctrl |= 0x003f000f;
13766         } else {
13767                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13768                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13769                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13770                         u32 read_water = 0x7;
13771
13772                         /* If the 5704 is behind the EPB bridge, we can
13773                          * do the less restrictive ONE_DMA workaround for
13774                          * better performance.
13775                          */
13776                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13777                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13778                                 tp->dma_rwctrl |= 0x8000;
13779                         else if (ccval == 0x6 || ccval == 0x7)
13780                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13781
13782                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13783                                 read_water = 4;
13784                         /* Set bit 23 to enable PCIX hw bug fix */
13785                         tp->dma_rwctrl |=
13786                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13787                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13788                                 (1 << 23);
13789                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13790                         /* 5780 always in PCIX mode */
13791                         tp->dma_rwctrl |= 0x00144000;
13792                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13793                         /* 5714 always in PCIX mode */
13794                         tp->dma_rwctrl |= 0x00148000;
13795                 } else {
13796                         tp->dma_rwctrl |= 0x001b000f;
13797                 }
13798         }
13799
13800         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13801             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13802                 tp->dma_rwctrl &= 0xfffffff0;
13803
13804         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13805             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13806                 /* Remove this if it causes problems for some boards. */
13807                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13808
13809                 /* On 5700/5701 chips, we need to set this bit.
13810                  * Otherwise the chip will issue cacheline transactions
13811                  * to streamable DMA memory with not all the byte
13812                  * enables turned on.  This is an error on several
13813                  * RISC PCI controllers, in particular sparc64.
13814                  *
13815                  * On 5703/5704 chips, this bit has been reassigned
13816                  * a different meaning.  In particular, it is used
13817                  * on those chips to enable a PCI-X workaround.
13818                  */
13819                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13820         }
13821
13822         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13823
13824 #if 0
13825         /* Unneeded, already done by tg3_get_invariants.  */
13826         tg3_switch_clocks(tp);
13827 #endif
13828
13829         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13830             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13831                 goto out;
13832
13833         /* It is best to perform DMA test with maximum write burst size
13834          * to expose the 5700/5701 write DMA bug.
13835          */
13836         saved_dma_rwctrl = tp->dma_rwctrl;
13837         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13838         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13839
13840         while (1) {
13841                 u32 *p = buf, i;
13842
13843                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13844                         p[i] = i;
13845
13846                 /* Send the buffer to the chip. */
13847                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13848                 if (ret) {
13849                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13850                         break;
13851                 }
13852
13853 #if 0
13854                 /* validate data reached card RAM correctly. */
13855                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13856                         u32 val;
13857                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13858                         if (le32_to_cpu(val) != p[i]) {
13859                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13860                                 /* ret = -ENODEV here? */
13861                         }
13862                         p[i] = 0;
13863                 }
13864 #endif
13865                 /* Now read it back. */
13866                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13867                 if (ret) {
13868                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13869
13870                         break;
13871                 }
13872
13873                 /* Verify it. */
13874                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13875                         if (p[i] == i)
13876                                 continue;
13877
13878                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13879                             DMA_RWCTRL_WRITE_BNDRY_16) {
13880                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13881                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13882                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13883                                 break;
13884                         } else {
13885                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13886                                 ret = -ENODEV;
13887                                 goto out;
13888                         }
13889                 }
13890
13891                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13892                         /* Success. */
13893                         ret = 0;
13894                         break;
13895                 }
13896         }
13897         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13898             DMA_RWCTRL_WRITE_BNDRY_16) {
13899                 static struct pci_device_id dma_wait_state_chipsets[] = {
13900                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13901                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13902                         { },
13903                 };
13904
13905                 /* DMA test passed without adjusting DMA boundary,
13906                  * now look for chipsets that are known to expose the
13907                  * DMA bug without failing the test.
13908                  */
13909                 if (pci_dev_present(dma_wait_state_chipsets)) {
13910                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13911                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13912                 }
13913                 else
13914                         /* Safe to use the calculated DMA boundary. */
13915                         tp->dma_rwctrl = saved_dma_rwctrl;
13916
13917                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13918         }
13919
13920 out:
13921         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13922 out_nofree:
13923         return ret;
13924 }
13925
13926 static void __devinit tg3_init_link_config(struct tg3 *tp)
13927 {
13928         tp->link_config.advertising =
13929                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13930                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13931                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13932                  ADVERTISED_Autoneg | ADVERTISED_MII);
13933         tp->link_config.speed = SPEED_INVALID;
13934         tp->link_config.duplex = DUPLEX_INVALID;
13935         tp->link_config.autoneg = AUTONEG_ENABLE;
13936         tp->link_config.active_speed = SPEED_INVALID;
13937         tp->link_config.active_duplex = DUPLEX_INVALID;
13938         tp->link_config.phy_is_low_power = 0;
13939         tp->link_config.orig_speed = SPEED_INVALID;
13940         tp->link_config.orig_duplex = DUPLEX_INVALID;
13941         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13942 }
13943
13944 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13945 {
13946         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13947             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13948                 tp->bufmgr_config.mbuf_read_dma_low_water =
13949                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13950                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13951                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13952                 tp->bufmgr_config.mbuf_high_water =
13953                         DEFAULT_MB_HIGH_WATER_5705;
13954                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13955                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13956                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13957                         tp->bufmgr_config.mbuf_high_water =
13958                                 DEFAULT_MB_HIGH_WATER_5906;
13959                 }
13960
13961                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13962                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13963                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13964                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13965                 tp->bufmgr_config.mbuf_high_water_jumbo =
13966                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13967         } else {
13968                 tp->bufmgr_config.mbuf_read_dma_low_water =
13969                         DEFAULT_MB_RDMA_LOW_WATER;
13970                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13971                         DEFAULT_MB_MACRX_LOW_WATER;
13972                 tp->bufmgr_config.mbuf_high_water =
13973                         DEFAULT_MB_HIGH_WATER;
13974
13975                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13976                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13977                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13978                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13979                 tp->bufmgr_config.mbuf_high_water_jumbo =
13980                         DEFAULT_MB_HIGH_WATER_JUMBO;
13981         }
13982
13983         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13984         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13985 }
13986
13987 static char * __devinit tg3_phy_string(struct tg3 *tp)
13988 {
13989         switch (tp->phy_id & PHY_ID_MASK) {
13990         case PHY_ID_BCM5400:    return "5400";
13991         case PHY_ID_BCM5401:    return "5401";
13992         case PHY_ID_BCM5411:    return "5411";
13993         case PHY_ID_BCM5701:    return "5701";
13994         case PHY_ID_BCM5703:    return "5703";
13995         case PHY_ID_BCM5704:    return "5704";
13996         case PHY_ID_BCM5705:    return "5705";
13997         case PHY_ID_BCM5750:    return "5750";
13998         case PHY_ID_BCM5752:    return "5752";
13999         case PHY_ID_BCM5714:    return "5714";
14000         case PHY_ID_BCM5780:    return "5780";
14001         case PHY_ID_BCM5755:    return "5755";
14002         case PHY_ID_BCM5787:    return "5787";
14003         case PHY_ID_BCM5784:    return "5784";
14004         case PHY_ID_BCM5756:    return "5722/5756";
14005         case PHY_ID_BCM5906:    return "5906";
14006         case PHY_ID_BCM5761:    return "5761";
14007         case PHY_ID_BCM5717:    return "5717";
14008         case PHY_ID_BCM8002:    return "8002/serdes";
14009         case 0:                 return "serdes";
14010         default:                return "unknown";
14011         }
14012 }
14013
14014 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14015 {
14016         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14017                 strcpy(str, "PCI Express");
14018                 return str;
14019         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14020                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14021
14022                 strcpy(str, "PCIX:");
14023
14024                 if ((clock_ctrl == 7) ||
14025                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14026                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14027                         strcat(str, "133MHz");
14028                 else if (clock_ctrl == 0)
14029                         strcat(str, "33MHz");
14030                 else if (clock_ctrl == 2)
14031                         strcat(str, "50MHz");
14032                 else if (clock_ctrl == 4)
14033                         strcat(str, "66MHz");
14034                 else if (clock_ctrl == 6)
14035                         strcat(str, "100MHz");
14036         } else {
14037                 strcpy(str, "PCI:");
14038                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14039                         strcat(str, "66MHz");
14040                 else
14041                         strcat(str, "33MHz");
14042         }
14043         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14044                 strcat(str, ":32-bit");
14045         else
14046                 strcat(str, ":64-bit");
14047         return str;
14048 }
14049
14050 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14051 {
14052         struct pci_dev *peer;
14053         unsigned int func, devnr = tp->pdev->devfn & ~7;
14054
14055         for (func = 0; func < 8; func++) {
14056                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14057                 if (peer && peer != tp->pdev)
14058                         break;
14059                 pci_dev_put(peer);
14060         }
14061         /* 5704 can be configured in single-port mode, set peer to
14062          * tp->pdev in that case.
14063          */
14064         if (!peer) {
14065                 peer = tp->pdev;
14066                 return peer;
14067         }
14068
14069         /*
14070          * We don't need to keep the refcount elevated; there's no way
14071          * to remove one half of this device without removing the other
14072          */
14073         pci_dev_put(peer);
14074
14075         return peer;
14076 }
14077
14078 static void __devinit tg3_init_coal(struct tg3 *tp)
14079 {
14080         struct ethtool_coalesce *ec = &tp->coal;
14081
14082         memset(ec, 0, sizeof(*ec));
14083         ec->cmd = ETHTOOL_GCOALESCE;
14084         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14085         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14086         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14087         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14088         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14089         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14090         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14091         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14092         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14093
14094         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14095                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14096                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14097                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14098                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14099                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14100         }
14101
14102         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14103                 ec->rx_coalesce_usecs_irq = 0;
14104                 ec->tx_coalesce_usecs_irq = 0;
14105                 ec->stats_block_coalesce_usecs = 0;
14106         }
14107 }
14108
14109 static const struct net_device_ops tg3_netdev_ops = {
14110         .ndo_open               = tg3_open,
14111         .ndo_stop               = tg3_close,
14112         .ndo_start_xmit         = tg3_start_xmit,
14113         .ndo_get_stats          = tg3_get_stats,
14114         .ndo_validate_addr      = eth_validate_addr,
14115         .ndo_set_multicast_list = tg3_set_rx_mode,
14116         .ndo_set_mac_address    = tg3_set_mac_addr,
14117         .ndo_do_ioctl           = tg3_ioctl,
14118         .ndo_tx_timeout         = tg3_tx_timeout,
14119         .ndo_change_mtu         = tg3_change_mtu,
14120 #if TG3_VLAN_TAG_USED
14121         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14122 #endif
14123 #ifdef CONFIG_NET_POLL_CONTROLLER
14124         .ndo_poll_controller    = tg3_poll_controller,
14125 #endif
14126 };
14127
14128 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14129         .ndo_open               = tg3_open,
14130         .ndo_stop               = tg3_close,
14131         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14132         .ndo_get_stats          = tg3_get_stats,
14133         .ndo_validate_addr      = eth_validate_addr,
14134         .ndo_set_multicast_list = tg3_set_rx_mode,
14135         .ndo_set_mac_address    = tg3_set_mac_addr,
14136         .ndo_do_ioctl           = tg3_ioctl,
14137         .ndo_tx_timeout         = tg3_tx_timeout,
14138         .ndo_change_mtu         = tg3_change_mtu,
14139 #if TG3_VLAN_TAG_USED
14140         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14141 #endif
14142 #ifdef CONFIG_NET_POLL_CONTROLLER
14143         .ndo_poll_controller    = tg3_poll_controller,
14144 #endif
14145 };
14146
14147 static int __devinit tg3_init_one(struct pci_dev *pdev,
14148                                   const struct pci_device_id *ent)
14149 {
14150         static int tg3_version_printed = 0;
14151         struct net_device *dev;
14152         struct tg3 *tp;
14153         int i, err, pm_cap;
14154         u32 sndmbx, rcvmbx, intmbx;
14155         char str[40];
14156         u64 dma_mask, persist_dma_mask;
14157
14158         if (tg3_version_printed++ == 0)
14159                 printk(KERN_INFO "%s", version);
14160
14161         err = pci_enable_device(pdev);
14162         if (err) {
14163                 printk(KERN_ERR PFX "Cannot enable PCI device, "
14164                        "aborting.\n");
14165                 return err;
14166         }
14167
14168         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14169         if (err) {
14170                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14171                        "aborting.\n");
14172                 goto err_out_disable_pdev;
14173         }
14174
14175         pci_set_master(pdev);
14176
14177         /* Find power-management capability. */
14178         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14179         if (pm_cap == 0) {
14180                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14181                        "aborting.\n");
14182                 err = -EIO;
14183                 goto err_out_free_res;
14184         }
14185
14186         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14187         if (!dev) {
14188                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14189                 err = -ENOMEM;
14190                 goto err_out_free_res;
14191         }
14192
14193         SET_NETDEV_DEV(dev, &pdev->dev);
14194
14195 #if TG3_VLAN_TAG_USED
14196         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14197 #endif
14198
14199         tp = netdev_priv(dev);
14200         tp->pdev = pdev;
14201         tp->dev = dev;
14202         tp->pm_cap = pm_cap;
14203         tp->rx_mode = TG3_DEF_RX_MODE;
14204         tp->tx_mode = TG3_DEF_TX_MODE;
14205
14206         if (tg3_debug > 0)
14207                 tp->msg_enable = tg3_debug;
14208         else
14209                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14210
14211         /* The word/byte swap controls here control register access byte
14212          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14213          * setting below.
14214          */
14215         tp->misc_host_ctrl =
14216                 MISC_HOST_CTRL_MASK_PCI_INT |
14217                 MISC_HOST_CTRL_WORD_SWAP |
14218                 MISC_HOST_CTRL_INDIR_ACCESS |
14219                 MISC_HOST_CTRL_PCISTATE_RW;
14220
14221         /* The NONFRM (non-frame) byte/word swap controls take effect
14222          * on descriptor entries, anything which isn't packet data.
14223          *
14224          * The StrongARM chips on the board (one for tx, one for rx)
14225          * are running in big-endian mode.
14226          */
14227         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14228                         GRC_MODE_WSWAP_NONFRM_DATA);
14229 #ifdef __BIG_ENDIAN
14230         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14231 #endif
14232         spin_lock_init(&tp->lock);
14233         spin_lock_init(&tp->indirect_lock);
14234         INIT_WORK(&tp->reset_task, tg3_reset_task);
14235
14236         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14237         if (!tp->regs) {
14238                 printk(KERN_ERR PFX "Cannot map device registers, "
14239                        "aborting.\n");
14240                 err = -ENOMEM;
14241                 goto err_out_free_dev;
14242         }
14243
14244         tg3_init_link_config(tp);
14245
14246         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14247         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14248
14249         dev->ethtool_ops = &tg3_ethtool_ops;
14250         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14251         dev->irq = pdev->irq;
14252
14253         err = tg3_get_invariants(tp);
14254         if (err) {
14255                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14256                        "aborting.\n");
14257                 goto err_out_iounmap;
14258         }
14259
14260         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14261             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14262                 dev->netdev_ops = &tg3_netdev_ops;
14263         else
14264                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14265
14266
14267         /* The EPB bridge inside 5714, 5715, and 5780 and any
14268          * device behind the EPB cannot support DMA addresses > 40-bit.
14269          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14270          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14271          * do DMA address check in tg3_start_xmit().
14272          */
14273         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14274                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14275         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14276                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14277 #ifdef CONFIG_HIGHMEM
14278                 dma_mask = DMA_BIT_MASK(64);
14279 #endif
14280         } else
14281                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14282
14283         /* Configure DMA attributes. */
14284         if (dma_mask > DMA_BIT_MASK(32)) {
14285                 err = pci_set_dma_mask(pdev, dma_mask);
14286                 if (!err) {
14287                         dev->features |= NETIF_F_HIGHDMA;
14288                         err = pci_set_consistent_dma_mask(pdev,
14289                                                           persist_dma_mask);
14290                         if (err < 0) {
14291                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14292                                        "DMA for consistent allocations\n");
14293                                 goto err_out_iounmap;
14294                         }
14295                 }
14296         }
14297         if (err || dma_mask == DMA_BIT_MASK(32)) {
14298                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14299                 if (err) {
14300                         printk(KERN_ERR PFX "No usable DMA configuration, "
14301                                "aborting.\n");
14302                         goto err_out_iounmap;
14303                 }
14304         }
14305
14306         tg3_init_bufmgr_config(tp);
14307
14308         /* Selectively allow TSO based on operating conditions */
14309         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14310             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14311                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14312         else {
14313                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14314                 tp->fw_needed = NULL;
14315         }
14316
14317         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14318                 tp->fw_needed = FIRMWARE_TG3;
14319
14320         /* TSO is on by default on chips that support hardware TSO.
14321          * Firmware TSO on older chips gives lower performance, so it
14322          * is off by default, but can be enabled using ethtool.
14323          */
14324         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14325             (dev->features & NETIF_F_IP_CSUM))
14326                 dev->features |= NETIF_F_TSO;
14327
14328         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14329             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14330                 if (dev->features & NETIF_F_IPV6_CSUM)
14331                         dev->features |= NETIF_F_TSO6;
14332                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14333                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14334                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14335                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14336                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14337                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14338                         dev->features |= NETIF_F_TSO_ECN;
14339         }
14340
14341         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14342             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14343             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14344                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14345                 tp->rx_pending = 63;
14346         }
14347
14348         err = tg3_get_device_address(tp);
14349         if (err) {
14350                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14351                        "aborting.\n");
14352                 goto err_out_fw;
14353         }
14354
14355         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14356                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14357                 if (!tp->aperegs) {
14358                         printk(KERN_ERR PFX "Cannot map APE registers, "
14359                                "aborting.\n");
14360                         err = -ENOMEM;
14361                         goto err_out_fw;
14362                 }
14363
14364                 tg3_ape_lock_init(tp);
14365
14366                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14367                         tg3_read_dash_ver(tp);
14368         }
14369
14370         /*
14371          * Reset chip in case UNDI or EFI driver did not shutdown
14372          * DMA self test will enable WDMAC and we'll see (spurious)
14373          * pending DMA on the PCI bus at that point.
14374          */
14375         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14376             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14377                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14378                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14379         }
14380
14381         err = tg3_test_dma(tp);
14382         if (err) {
14383                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14384                 goto err_out_apeunmap;
14385         }
14386
14387         /* flow control autonegotiation is default behavior */
14388         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14389         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14390
14391         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14392         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14393         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14394         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14395                 struct tg3_napi *tnapi = &tp->napi[i];
14396
14397                 tnapi->tp = tp;
14398                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14399
14400                 tnapi->int_mbox = intmbx;
14401                 if (i < 4)
14402                         intmbx += 0x8;
14403                 else
14404                         intmbx += 0x4;
14405
14406                 tnapi->consmbox = rcvmbx;
14407                 tnapi->prodmbox = sndmbx;
14408
14409                 if (i) {
14410                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14411                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14412                 } else {
14413                         tnapi->coal_now = HOSTCC_MODE_NOW;
14414                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14415                 }
14416
14417                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14418                         break;
14419
14420                 /*
14421                  * If we support MSIX, we'll be using RSS.  If we're using
14422                  * RSS, the first vector only handles link interrupts and the
14423                  * remaining vectors handle rx and tx interrupts.  Reuse the
14424                  * mailbox values for the next iteration.  The values we setup
14425                  * above are still useful for the single vectored mode.
14426                  */
14427                 if (!i)
14428                         continue;
14429
14430                 rcvmbx += 0x8;
14431
14432                 if (sndmbx & 0x4)
14433                         sndmbx -= 0x4;
14434                 else
14435                         sndmbx += 0xc;
14436         }
14437
14438         tg3_init_coal(tp);
14439
14440         pci_set_drvdata(pdev, dev);
14441
14442         err = register_netdev(dev);
14443         if (err) {
14444                 printk(KERN_ERR PFX "Cannot register net device, "
14445                        "aborting.\n");
14446                 goto err_out_apeunmap;
14447         }
14448
14449         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14450                dev->name,
14451                tp->board_part_number,
14452                tp->pci_chip_rev_id,
14453                tg3_bus_string(tp, str),
14454                dev->dev_addr);
14455
14456         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14457                 struct phy_device *phydev;
14458                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14459                 printk(KERN_INFO
14460                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14461                        tp->dev->name, phydev->drv->name,
14462                        dev_name(&phydev->dev));
14463         } else
14464                 printk(KERN_INFO
14465                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14466                        tp->dev->name, tg3_phy_string(tp),
14467                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14468                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14469                          "10/100/1000Base-T")),
14470                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14471
14472         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14473                dev->name,
14474                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14475                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14476                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14477                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14478                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14479         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14480                dev->name, tp->dma_rwctrl,
14481                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14482                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14483
14484         return 0;
14485
14486 err_out_apeunmap:
14487         if (tp->aperegs) {
14488                 iounmap(tp->aperegs);
14489                 tp->aperegs = NULL;
14490         }
14491
14492 err_out_fw:
14493         if (tp->fw)
14494                 release_firmware(tp->fw);
14495
14496 err_out_iounmap:
14497         if (tp->regs) {
14498                 iounmap(tp->regs);
14499                 tp->regs = NULL;
14500         }
14501
14502 err_out_free_dev:
14503         free_netdev(dev);
14504
14505 err_out_free_res:
14506         pci_release_regions(pdev);
14507
14508 err_out_disable_pdev:
14509         pci_disable_device(pdev);
14510         pci_set_drvdata(pdev, NULL);
14511         return err;
14512 }
14513
14514 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14515 {
14516         struct net_device *dev = pci_get_drvdata(pdev);
14517
14518         if (dev) {
14519                 struct tg3 *tp = netdev_priv(dev);
14520
14521                 if (tp->fw)
14522                         release_firmware(tp->fw);
14523
14524                 flush_scheduled_work();
14525
14526                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14527                         tg3_phy_fini(tp);
14528                         tg3_mdio_fini(tp);
14529                 }
14530
14531                 unregister_netdev(dev);
14532                 if (tp->aperegs) {
14533                         iounmap(tp->aperegs);
14534                         tp->aperegs = NULL;
14535                 }
14536                 if (tp->regs) {
14537                         iounmap(tp->regs);
14538                         tp->regs = NULL;
14539                 }
14540                 free_netdev(dev);
14541                 pci_release_regions(pdev);
14542                 pci_disable_device(pdev);
14543                 pci_set_drvdata(pdev, NULL);
14544         }
14545 }
14546
14547 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14548 {
14549         struct net_device *dev = pci_get_drvdata(pdev);
14550         struct tg3 *tp = netdev_priv(dev);
14551         pci_power_t target_state;
14552         int err;
14553
14554         /* PCI register 4 needs to be saved whether netif_running() or not.
14555          * MSI address and data need to be saved if using MSI and
14556          * netif_running().
14557          */
14558         pci_save_state(pdev);
14559
14560         if (!netif_running(dev))
14561                 return 0;
14562
14563         flush_scheduled_work();
14564         tg3_phy_stop(tp);
14565         tg3_netif_stop(tp);
14566
14567         del_timer_sync(&tp->timer);
14568
14569         tg3_full_lock(tp, 1);
14570         tg3_disable_ints(tp);
14571         tg3_full_unlock(tp);
14572
14573         netif_device_detach(dev);
14574
14575         tg3_full_lock(tp, 0);
14576         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14577         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14578         tg3_full_unlock(tp);
14579
14580         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14581
14582         err = tg3_set_power_state(tp, target_state);
14583         if (err) {
14584                 int err2;
14585
14586                 tg3_full_lock(tp, 0);
14587
14588                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14589                 err2 = tg3_restart_hw(tp, 1);
14590                 if (err2)
14591                         goto out;
14592
14593                 tp->timer.expires = jiffies + tp->timer_offset;
14594                 add_timer(&tp->timer);
14595
14596                 netif_device_attach(dev);
14597                 tg3_netif_start(tp);
14598
14599 out:
14600                 tg3_full_unlock(tp);
14601
14602                 if (!err2)
14603                         tg3_phy_start(tp);
14604         }
14605
14606         return err;
14607 }
14608
14609 static int tg3_resume(struct pci_dev *pdev)
14610 {
14611         struct net_device *dev = pci_get_drvdata(pdev);
14612         struct tg3 *tp = netdev_priv(dev);
14613         int err;
14614
14615         pci_restore_state(tp->pdev);
14616
14617         if (!netif_running(dev))
14618                 return 0;
14619
14620         err = tg3_set_power_state(tp, PCI_D0);
14621         if (err)
14622                 return err;
14623
14624         netif_device_attach(dev);
14625
14626         tg3_full_lock(tp, 0);
14627
14628         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14629         err = tg3_restart_hw(tp, 1);
14630         if (err)
14631                 goto out;
14632
14633         tp->timer.expires = jiffies + tp->timer_offset;
14634         add_timer(&tp->timer);
14635
14636         tg3_netif_start(tp);
14637
14638 out:
14639         tg3_full_unlock(tp);
14640
14641         if (!err)
14642                 tg3_phy_start(tp);
14643
14644         return err;
14645 }
14646
14647 static struct pci_driver tg3_driver = {
14648         .name           = DRV_MODULE_NAME,
14649         .id_table       = tg3_pci_tbl,
14650         .probe          = tg3_init_one,
14651         .remove         = __devexit_p(tg3_remove_one),
14652         .suspend        = tg3_suspend,
14653         .resume         = tg3_resume
14654 };
14655
14656 static int __init tg3_init(void)
14657 {
14658         return pci_register_driver(&tg3_driver);
14659 }
14660
14661 static void __exit tg3_cleanup(void)
14662 {
14663         pci_unregister_driver(&tg3_driver);
14664 }
14665
14666 module_init(tg3_init);
14667 module_exit(tg3_cleanup);