drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.101"
  72 #define DRV_MODULE_RELDATE      "August 28, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 512 : 1024)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 /* minimum number of free TX descriptors required to wake up TX process */
 141 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 142
 143 #define TG3_RAW_IP_ALIGN 2
 144
 145 /* number of ETHTOOL_GSTATS u64's */
 146 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 147
 148 #define TG3_NUM_TEST            6
 149
 150 #define FIRMWARE_TG3            "tigon/tg3.bin"
 151 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 152 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 153
 154 static char version[] __devinitdata =
 155         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 156
 157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_MODULE_VERSION);
 161 MODULE_FIRMWARE(FIRMWARE_TG3);
 162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 164
 165 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 166
 167 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 168 module_param(tg3_debug, int, 0);
 169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 170
 171 static struct pci_device_id tg3_pci_tbl[] = {
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 245         {}
 246 };
 247
 248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 249
 250 static const struct {
 251         const char string[ETH_GSTRING_LEN];
 252 } ethtool_stats_keys[TG3_NUM_STATS] = {
 253         { "rx_octets" },
 254         { "rx_fragments" },
 255         { "rx_ucast_packets" },
 256         { "rx_mcast_packets" },
 257         { "rx_bcast_packets" },
 258         { "rx_fcs_errors" },
 259         { "rx_align_errors" },
 260         { "rx_xon_pause_rcvd" },
 261         { "rx_xoff_pause_rcvd" },
 262         { "rx_mac_ctrl_rcvd" },
 263         { "rx_xoff_entered" },
 264         { "rx_frame_too_long_errors" },
 265         { "rx_jabbers" },
 266         { "rx_undersize_packets" },
 267         { "rx_in_length_errors" },
 268         { "rx_out_length_errors" },
 269         { "rx_64_or_less_octet_packets" },
 270         { "rx_65_to_127_octet_packets" },
 271         { "rx_128_to_255_octet_packets" },
 272         { "rx_256_to_511_octet_packets" },
 273         { "rx_512_to_1023_octet_packets" },
 274         { "rx_1024_to_1522_octet_packets" },
 275         { "rx_1523_to_2047_octet_packets" },
 276         { "rx_2048_to_4095_octet_packets" },
 277         { "rx_4096_to_8191_octet_packets" },
 278         { "rx_8192_to_9022_octet_packets" },
 279
 280         { "tx_octets" },
 281         { "tx_collisions" },
 282
 283         { "tx_xon_sent" },
 284         { "tx_xoff_sent" },
 285         { "tx_flow_control" },
 286         { "tx_mac_errors" },
 287         { "tx_single_collisions" },
 288         { "tx_mult_collisions" },
 289         { "tx_deferred" },
 290         { "tx_excessive_collisions" },
 291         { "tx_late_collisions" },
 292         { "tx_collide_2times" },
 293         { "tx_collide_3times" },
 294         { "tx_collide_4times" },
 295         { "tx_collide_5times" },
 296         { "tx_collide_6times" },
 297         { "tx_collide_7times" },
 298         { "tx_collide_8times" },
 299         { "tx_collide_9times" },
 300         { "tx_collide_10times" },
 301         { "tx_collide_11times" },
 302         { "tx_collide_12times" },
 303         { "tx_collide_13times" },
 304         { "tx_collide_14times" },
 305         { "tx_collide_15times" },
 306         { "tx_ucast_packets" },
 307         { "tx_mcast_packets" },
 308         { "tx_bcast_packets" },
 309         { "tx_carrier_sense_errors" },
 310         { "tx_discards" },
 311         { "tx_errors" },
 312
 313         { "dma_writeq_full" },
 314         { "dma_write_prioq_full" },
 315         { "rxbds_empty" },
 316         { "rx_discards" },
 317         { "rx_errors" },
 318         { "rx_threshold_hit" },
 319
 320         { "dma_readq_full" },
 321         { "dma_read_prioq_full" },
 322         { "tx_comp_queue_full" },
 323
 324         { "ring_set_send_prod_index" },
 325         { "ring_status_update" },
 326         { "nic_irqs" },
 327         { "nic_avoided_irqs" },
 328         { "nic_tx_threshold_hit" }
 329 };
 330
 331 static const struct {
 332         const char string[ETH_GSTRING_LEN];
 333 } ethtool_test_keys[TG3_NUM_TEST] = {
 334         { "nvram test     (online) " },
 335         { "link test      (online) " },
 336         { "register test  (offline)" },
 337         { "memory test    (offline)" },
 338         { "loopback test  (offline)" },
 339         { "interrupt test (offline)" },
 340 };
 341
 342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 343 {
 344         writel(val, tp->regs + off);
 345 }
 346
 347 static u32 tg3_read32(struct tg3 *tp, u32 off)
 348 {
 349         return (readl(tp->regs + off));
 350 }
 351
 352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 353 {
 354         writel(val, tp->aperegs + off);
 355 }
 356
 357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 358 {
 359         return (readl(tp->aperegs + off));
 360 }
 361
 362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 363 {
 364         unsigned long flags;
 365
 366         spin_lock_irqsave(&tp->indirect_lock, flags);
 367         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 368         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 369         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 370 }
 371
 372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         writel(val, tp->regs + off);
 375         readl(tp->regs + off);
 376 }
 377
 378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 379 {
 380         unsigned long flags;
 381         u32 val;
 382
 383         spin_lock_irqsave(&tp->indirect_lock, flags);
 384         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 385         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 386         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 387         return val;
 388 }
 389
 390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 391 {
 392         unsigned long flags;
 393
 394         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 395                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 396                                        TG3_64BIT_REG_LOW, val);
 397                 return;
 398         }
 399         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 400                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 401                                        TG3_64BIT_REG_LOW, val);
 402                 return;
 403         }
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409
 410         /* In indirect mode when disabling interrupts, we also need
 411          * to clear the interrupt bit in the GRC local ctrl register.
 412          */
 413         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 414             (val == 0x1)) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 416                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 417         }
 418 }
 419
 420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 421 {
 422         unsigned long flags;
 423         u32 val;
 424
 425         spin_lock_irqsave(&tp->indirect_lock, flags);
 426         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 427         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 428         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 429         return val;
 430 }
 431
 432 /* usec_wait specifies the wait time in usec when writing to certain registers
 433  * where it is unsafe to read back the register without some delay.
 434  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 435  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 436  */
 437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 438 {
 439         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 440             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 441                 /* Non-posted methods */
 442                 tp->write32(tp, off, val);
 443         else {
 444                 /* Posted method */
 445                 tg3_write32(tp, off, val);
 446                 if (usec_wait)
 447                         udelay(usec_wait);
 448                 tp->read32(tp, off);
 449         }
 450         /* Wait again after the read for the posted method to guarantee that
 451          * the wait time is met.
 452          */
 453         if (usec_wait)
 454                 udelay(usec_wait);
 455 }
 456
 457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 458 {
 459         tp->write32_mbox(tp, off, val);
 460         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 461             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 462                 tp->read32_mbox(tp, off);
 463 }
 464
 465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 466 {
 467         void __iomem *mbox = tp->regs + off;
 468         writel(val, mbox);
 469         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 470                 writel(val, mbox);
 471         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 472                 readl(mbox);
 473 }
 474
 475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 476 {
 477         return (readl(tp->regs + off + GRCMBOX_BASE));
 478 }
 479
 480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         writel(val, tp->regs + off + GRCMBOX_BASE);
 483 }
 484
 485 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 486 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 487 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 488 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 489 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 490
 491 #define tw32(reg,val)           tp->write32(tp, reg, val)
 492 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 494 #define tr32(reg)               tp->read32(tp, reg)
 495
 496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         unsigned long flags;
 499
 500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 501             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 502                 return;
 503
 504         spin_lock_irqsave(&tp->indirect_lock, flags);
 505         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 508
 509                 /* Always leave this as zero. */
 510                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 511         } else {
 512                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 513                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 514
 515                 /* Always leave this as zero. */
 516                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 517         }
 518         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 519 }
 520
 521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 522 {
 523         unsigned long flags;
 524
 525         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 526             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 527                 *val = 0;
 528                 return;
 529         }
 530
 531         spin_lock_irqsave(&tp->indirect_lock, flags);
 532         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 533                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 534                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 535
 536                 /* Always leave this as zero. */
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 538         } else {
 539                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 540                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 541
 542                 /* Always leave this as zero. */
 543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 544         }
 545         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 546 }
 547
 548 static void tg3_ape_lock_init(struct tg3 *tp)
 549 {
 550         int i;
 551
 552         /* Make sure the driver hasn't any stale locks. */
 553         for (i = 0; i < 8; i++)
 554                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 555                                 APE_LOCK_GRANT_DRIVER);
 556 }
 557
 558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 559 {
 560         int i, off;
 561         int ret = 0;
 562         u32 status;
 563
 564         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 565                 return 0;
 566
 567         switch (locknum) {
 568                 case TG3_APE_LOCK_GRC:
 569                 case TG3_APE_LOCK_MEM:
 570                         break;
 571                 default:
 572                         return -EINVAL;
 573         }
 574
 575         off = 4 * locknum;
 576
 577         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 578
 579         /* Wait for up to 1 millisecond to acquire lock. */
 580         for (i = 0; i < 100; i++) {
 581                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 582                 if (status == APE_LOCK_GRANT_DRIVER)
 583                         break;
 584                 udelay(10);
 585         }
 586
 587         if (status != APE_LOCK_GRANT_DRIVER) {
 588                 /* Revoke the lock request. */
 589                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 590                                 APE_LOCK_GRANT_DRIVER);
 591
 592                 ret = -EBUSY;
 593         }
 594
 595         return ret;
 596 }
 597
 598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 599 {
 600         int off;
 601
 602         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 603                 return;
 604
 605         switch (locknum) {
 606                 case TG3_APE_LOCK_GRC:
 607                 case TG3_APE_LOCK_MEM:
 608                         break;
 609                 default:
 610                         return;
 611         }
 612
 613         off = 4 * locknum;
 614         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 615 }
 616
 617 static void tg3_disable_ints(struct tg3 *tp)
 618 {
 619         int i;
 620
 621         tw32(TG3PCI_MISC_HOST_CTRL,
 622              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 623         for (i = 0; i < tp->irq_max; i++)
 624                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 625 }
 626
 627 static void tg3_enable_ints(struct tg3 *tp)
 628 {
 629         int i;
 630         u32 coal_now = 0;
 631
 632         tp->irq_sync = 0;
 633         wmb();
 634
 635         tw32(TG3PCI_MISC_HOST_CTRL,
 636              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 637
 638         for (i = 0; i < tp->irq_cnt; i++) {
 639                 struct tg3_napi *tnapi = &tp->napi[i];
 640                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 641                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 642                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 643
 644                 coal_now |= tnapi->coal_now;
 645         }
 646
 647         /* Force an initial interrupt */
 648         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 649             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 650                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 651         else
 652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 653                      HOSTCC_MODE_ENABLE | coal_now);
 654 }
 655
 656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 657 {
 658         struct tg3 *tp = tnapi->tp;
 659         struct tg3_hw_status *sblk = tnapi->hw_status;
 660         unsigned int work_exists = 0;
 661
 662         /* check for phy events */
 663         if (!(tp->tg3_flags &
 664               (TG3_FLAG_USE_LINKCHG_REG |
 665                TG3_FLAG_POLL_SERDES))) {
 666                 if (sblk->status & SD_STATUS_LINK_CHG)
 667                         work_exists = 1;
 668         }
 669         /* check for RX/TX work to do */
 670         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 671             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 672                 work_exists = 1;
 673
 674         return work_exists;
 675 }
 676
 677 /* tg3_int_reenable
 678  *  similar to tg3_enable_ints, but it accurately determines whether there
 679  *  is new work pending and can return without flushing the PIO write
 680  *  which reenables interrupts
 681  */
 682 static void tg3_int_reenable(struct tg3_napi *tnapi)
 683 {
 684         struct tg3 *tp = tnapi->tp;
 685
 686         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 687         mmiowb();
 688
 689         /* When doing tagged status, this work check is unnecessary.
 690          * The last_tag we write above tells the chip which piece of
 691          * work we've completed.
 692          */
 693         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 694             tg3_has_work(tnapi))
 695                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 696                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 697 }
 698
 699 static void tg3_napi_disable(struct tg3 *tp)
 700 {
 701         int i;
 702
 703         for (i = tp->irq_cnt - 1; i >= 0; i--)
 704                 napi_disable(&tp->napi[i].napi);
 705 }
 706
 707 static void tg3_napi_enable(struct tg3 *tp)
 708 {
 709         int i;
 710
 711         for (i = 0; i < tp->irq_cnt; i++)
 712                 napi_enable(&tp->napi[i].napi);
 713 }
 714
 715 static inline void tg3_netif_stop(struct tg3 *tp)
 716 {
 717         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 718         tg3_napi_disable(tp);
 719         netif_tx_disable(tp->dev);
 720 }
 721
 722 static inline void tg3_netif_start(struct tg3 *tp)
 723 {
 724         /* NOTE: unconditional netif_tx_wake_all_queues is only
 725          * appropriate so long as all callers are assured to
 726          * have free tx slots (such as after tg3_init_hw)
 727          */
 728         netif_tx_wake_all_queues(tp->dev);
 729
 730         tg3_napi_enable(tp);
 731         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 732         tg3_enable_ints(tp);
 733 }
 734
 735 static void tg3_switch_clocks(struct tg3 *tp)
 736 {
 737         u32 clock_ctrl;
 738         u32 orig_clock_ctrl;
 739
 740         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 741             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 742                 return;
 743
 744         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 745
 746         orig_clock_ctrl = clock_ctrl;
 747         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 748                        CLOCK_CTRL_CLKRUN_OENABLE |
 749                        0x1f);
 750         tp->pci_clock_ctrl = clock_ctrl;
 751
 752         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 753                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 754                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 755                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 756                 }
 757         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 758                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 759                             clock_ctrl |
 760                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 761                             40);
 762                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 763                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 764                             40);
 765         }
 766         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 767 }
 768
 769 #define PHY_BUSY_LOOPS  5000
 770
 771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 772 {
 773         u32 frame_val;
 774         unsigned int loops;
 775         int ret;
 776
 777         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 778                 tw32_f(MAC_MI_MODE,
 779                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 780                 udelay(80);
 781         }
 782
 783         *val = 0x0;
 784
 785         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 786                       MI_COM_PHY_ADDR_MASK);
 787         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 788                       MI_COM_REG_ADDR_MASK);
 789         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 790
 791         tw32_f(MAC_MI_COM, frame_val);
 792
 793         loops = PHY_BUSY_LOOPS;
 794         while (loops != 0) {
 795                 udelay(10);
 796                 frame_val = tr32(MAC_MI_COM);
 797
 798                 if ((frame_val & MI_COM_BUSY) == 0) {
 799                         udelay(5);
 800                         frame_val = tr32(MAC_MI_COM);
 801                         break;
 802                 }
 803                 loops -= 1;
 804         }
 805
 806         ret = -EBUSY;
 807         if (loops != 0) {
 808                 *val = frame_val & MI_COM_DATA_MASK;
 809                 ret = 0;
 810         }
 811
 812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 813                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 814                 udelay(80);
 815         }
 816
 817         return ret;
 818 }
 819
 820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 821 {
 822         u32 frame_val;
 823         unsigned int loops;
 824         int ret;
 825
 826         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 827             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 828                 return 0;
 829
 830         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 831                 tw32_f(MAC_MI_MODE,
 832                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 833                 udelay(80);
 834         }
 835
 836         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 837                       MI_COM_PHY_ADDR_MASK);
 838         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 839                       MI_COM_REG_ADDR_MASK);
 840         frame_val |= (val & MI_COM_DATA_MASK);
 841         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 842
 843         tw32_f(MAC_MI_COM, frame_val);
 844
 845         loops = PHY_BUSY_LOOPS;
 846         while (loops != 0) {
 847                 udelay(10);
 848                 frame_val = tr32(MAC_MI_COM);
 849                 if ((frame_val & MI_COM_BUSY) == 0) {
 850                         udelay(5);
 851                         frame_val = tr32(MAC_MI_COM);
 852                         break;
 853                 }
 854                 loops -= 1;
 855         }
 856
 857         ret = -EBUSY;
 858         if (loops != 0)
 859                 ret = 0;
 860
 861         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 862                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 863                 udelay(80);
 864         }
 865
 866         return ret;
 867 }
 868
 869 static int tg3_bmcr_reset(struct tg3 *tp)
 870 {
 871         u32 phy_control;
 872         int limit, err;
 873
 874         /* OK, reset it, and poll the BMCR_RESET bit until it
 875          * clears or we time out.
 876          */
 877         phy_control = BMCR_RESET;
 878         err = tg3_writephy(tp, MII_BMCR, phy_control);
 879         if (err != 0)
 880                 return -EBUSY;
 881
 882         limit = 5000;
 883         while (limit--) {
 884                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 885                 if (err != 0)
 886                         return -EBUSY;
 887
 888                 if ((phy_control & BMCR_RESET) == 0) {
 889                         udelay(40);
 890                         break;
 891                 }
 892                 udelay(10);
 893         }
 894         if (limit < 0)
 895                 return -EBUSY;
 896
 897         return 0;
 898 }
 899
 900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 901 {
 902         struct tg3 *tp = bp->priv;
 903         u32 val;
 904
 905         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 906                 return -EAGAIN;
 907
 908         if (tg3_readphy(tp, reg, &val))
 909                 return -EIO;
 910
 911         return val;
 912 }
 913
 914 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 915 {
 916         struct tg3 *tp = bp->priv;
 917
 918         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 919                 return -EAGAIN;
 920
 921         if (tg3_writephy(tp, reg, val))
 922                 return -EIO;
 923
 924         return 0;
 925 }
 926
 927 static int tg3_mdio_reset(struct mii_bus *bp)
 928 {
 929         return 0;
 930 }
 931
 932 static void tg3_mdio_config_5785(struct tg3 *tp)
 933 {
 934         u32 val;
 935         struct phy_device *phydev;
 936
 937         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 938         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 939         case TG3_PHY_ID_BCM50610:
 940                 val = MAC_PHYCFG2_50610_LED_MODES;
 941                 break;
 942         case TG3_PHY_ID_BCMAC131:
 943                 val = MAC_PHYCFG2_AC131_LED_MODES;
 944                 break;
 945         case TG3_PHY_ID_RTL8211C:
 946                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 947                 break;
 948         case TG3_PHY_ID_RTL8201E:
 949                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 950                 break;
 951         default:
 952                 return;
 953         }
 954
 955         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 956                 tw32(MAC_PHYCFG2, val);
 957
 958                 val = tr32(MAC_PHYCFG1);
 959                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 960                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 961                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 962                 tw32(MAC_PHYCFG1, val);
 963
 964                 return;
 965         }
 966
 967         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 968                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 969                        MAC_PHYCFG2_FMODE_MASK_MASK |
 970                        MAC_PHYCFG2_GMODE_MASK_MASK |
 971                        MAC_PHYCFG2_ACT_MASK_MASK   |
 972                        MAC_PHYCFG2_QUAL_MASK_MASK |
 973                        MAC_PHYCFG2_INBAND_ENABLE;
 974
 975         tw32(MAC_PHYCFG2, val);
 976
 977         val = tr32(MAC_PHYCFG1);
 978         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 979                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 980         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 981                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 982                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 983                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 984                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 985         }
 986         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 987                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 988         tw32(MAC_PHYCFG1, val);
 989
 990         val = tr32(MAC_EXT_RGMII_MODE);
 991         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 992                  MAC_RGMII_MODE_RX_QUALITY |
 993                  MAC_RGMII_MODE_RX_ACTIVITY |
 994                  MAC_RGMII_MODE_RX_ENG_DET |
 995                  MAC_RGMII_MODE_TX_ENABLE |
 996                  MAC_RGMII_MODE_TX_LOWPWR |
 997                  MAC_RGMII_MODE_TX_RESET);
 998         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 999                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1000                         val |= MAC_RGMII_MODE_RX_INT_B |
1001                                MAC_RGMII_MODE_RX_QUALITY |
1002                                MAC_RGMII_MODE_RX_ACTIVITY |
1003                                MAC_RGMII_MODE_RX_ENG_DET;
1004                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1005                         val |= MAC_RGMII_MODE_TX_ENABLE |
1006                                MAC_RGMII_MODE_TX_LOWPWR |
1007                                MAC_RGMII_MODE_TX_RESET;
1008         }
1009         tw32(MAC_EXT_RGMII_MODE, val);
1010 }
1011
1012 static void tg3_mdio_start(struct tg3 *tp)
1013 {
1014         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1015                 mutex_lock(&tp->mdio_bus->mdio_lock);
1016                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1017                 mutex_unlock(&tp->mdio_bus->mdio_lock);
1018         }
1019
1020         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1021         tw32_f(MAC_MI_MODE, tp->mi_mode);
1022         udelay(80);
1023
1024         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1025             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1026                 tg3_mdio_config_5785(tp);
1027 }
1028
1029 static void tg3_mdio_stop(struct tg3 *tp)
1030 {
1031         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1032                 mutex_lock(&tp->mdio_bus->mdio_lock);
1033                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
1034                 mutex_unlock(&tp->mdio_bus->mdio_lock);
1035         }
1036 }
1037
1038 static int tg3_mdio_init(struct tg3 *tp)
1039 {
1040         int i;
1041         u32 reg;
1042         struct phy_device *phydev;
1043
1044         tg3_mdio_start(tp);
1045
1046         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1047             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1048                 return 0;
1049
1050         tp->mdio_bus = mdiobus_alloc();
1051         if (tp->mdio_bus == NULL)
1052                 return -ENOMEM;
1053
1054         tp->mdio_bus->name     = "tg3 mdio bus";
1055         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1056                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1057         tp->mdio_bus->priv     = tp;
1058         tp->mdio_bus->parent   = &tp->pdev->dev;
1059         tp->mdio_bus->read     = &tg3_mdio_read;
1060         tp->mdio_bus->write    = &tg3_mdio_write;
1061         tp->mdio_bus->reset    = &tg3_mdio_reset;
1062         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1063         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1064
1065         for (i = 0; i < PHY_MAX_ADDR; i++)
1066                 tp->mdio_bus->irq[i] = PHY_POLL;
1067
1068         /* The bus registration will look for all the PHYs on the mdio bus.
1069          * Unfortunately, it does not ensure the PHY is powered up before
1070          * accessing the PHY ID registers.  A chip reset is the
1071          * quickest way to bring the device back to an operational state..
1072          */
1073         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1074                 tg3_bmcr_reset(tp);
1075
1076         i = mdiobus_register(tp->mdio_bus);
1077         if (i) {
1078                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1079                         tp->dev->name, i);
1080                 mdiobus_free(tp->mdio_bus);
1081                 return i;
1082         }
1083
1084         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1085
1086         if (!phydev || !phydev->drv) {
1087                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1088                 mdiobus_unregister(tp->mdio_bus);
1089                 mdiobus_free(tp->mdio_bus);
1090                 return -ENODEV;
1091         }
1092
1093         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1094         case TG3_PHY_ID_BCM57780:
1095                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1096                 break;
1097         case TG3_PHY_ID_BCM50610:
1098                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1099                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1100                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1101                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1102                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1103                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1104                 /* fallthru */
1105         case TG3_PHY_ID_RTL8211C:
1106                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1107                 break;
1108         case TG3_PHY_ID_RTL8201E:
1109         case TG3_PHY_ID_BCMAC131:
1110                 phydev->interface = PHY_INTERFACE_MODE_MII;
1111                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1112                 break;
1113         }
1114
1115         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1116
1117         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1118                 tg3_mdio_config_5785(tp);
1119
1120         return 0;
1121 }
1122
1123 static void tg3_mdio_fini(struct tg3 *tp)
1124 {
1125         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1126                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1127                 mdiobus_unregister(tp->mdio_bus);
1128                 mdiobus_free(tp->mdio_bus);
1129                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1130         }
1131 }
1132
1133 /* tp->lock is held. */
1134 static inline void tg3_generate_fw_event(struct tg3 *tp)
1135 {
1136         u32 val;
1137
1138         val = tr32(GRC_RX_CPU_EVENT);
1139         val |= GRC_RX_CPU_DRIVER_EVENT;
1140         tw32_f(GRC_RX_CPU_EVENT, val);
1141
1142         tp->last_event_jiffies = jiffies;
1143 }
1144
1145 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1146
1147 /* tp->lock is held. */
1148 static void tg3_wait_for_event_ack(struct tg3 *tp)
1149 {
1150         int i;
1151         unsigned int delay_cnt;
1152         long time_remain;
1153
1154         /* If enough time has passed, no wait is necessary. */
1155         time_remain = (long)(tp->last_event_jiffies + 1 +
1156                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1157                       (long)jiffies;
1158         if (time_remain < 0)
1159                 return;
1160
1161         /* Check if we can shorten the wait time. */
1162         delay_cnt = jiffies_to_usecs(time_remain);
1163         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1164                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1165         delay_cnt = (delay_cnt >> 3) + 1;
1166
1167         for (i = 0; i < delay_cnt; i++) {
1168                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1169                         break;
1170                 udelay(8);
1171         }
1172 }
1173
1174 /* tp->lock is held. */
1175 static void tg3_ump_link_report(struct tg3 *tp)
1176 {
1177         u32 reg;
1178         u32 val;
1179
1180         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1181             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1182                 return;
1183
1184         tg3_wait_for_event_ack(tp);
1185
1186         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1187
1188         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1189
1190         val = 0;
1191         if (!tg3_readphy(tp, MII_BMCR, &reg))
1192                 val = reg << 16;
1193         if (!tg3_readphy(tp, MII_BMSR, &reg))
1194                 val |= (reg & 0xffff);
1195         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1196
1197         val = 0;
1198         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1199                 val = reg << 16;
1200         if (!tg3_readphy(tp, MII_LPA, &reg))
1201                 val |= (reg & 0xffff);
1202         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1203
1204         val = 0;
1205         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1206                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1207                         val = reg << 16;
1208                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1209                         val |= (reg & 0xffff);
1210         }
1211         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1212
1213         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1214                 val = reg << 16;
1215         else
1216                 val = 0;
1217         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1218
1219         tg3_generate_fw_event(tp);
1220 }
1221
1222 static void tg3_link_report(struct tg3 *tp)
1223 {
1224         if (!netif_carrier_ok(tp->dev)) {
1225                 if (netif_msg_link(tp))
1226                         printk(KERN_INFO PFX "%s: Link is down.\n",
1227                                tp->dev->name);
1228                 tg3_ump_link_report(tp);
1229         } else if (netif_msg_link(tp)) {
1230                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1231                        tp->dev->name,
1232                        (tp->link_config.active_speed == SPEED_1000 ?
1233                         1000 :
1234                         (tp->link_config.active_speed == SPEED_100 ?
1235                          100 : 10)),
1236                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1237                         "full" : "half"));
1238
1239                 printk(KERN_INFO PFX
1240                        "%s: Flow control is %s for TX and %s for RX.\n",
1241                        tp->dev->name,
1242                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1243                        "on" : "off",
1244                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1245                        "on" : "off");
1246                 tg3_ump_link_report(tp);
1247         }
1248 }
1249
1250 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1251 {
1252         u16 miireg;
1253
1254         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1255                 miireg = ADVERTISE_PAUSE_CAP;
1256         else if (flow_ctrl & FLOW_CTRL_TX)
1257                 miireg = ADVERTISE_PAUSE_ASYM;
1258         else if (flow_ctrl & FLOW_CTRL_RX)
1259                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1260         else
1261                 miireg = 0;
1262
1263         return miireg;
1264 }
1265
1266 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1267 {
1268         u16 miireg;
1269
1270         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1271                 miireg = ADVERTISE_1000XPAUSE;
1272         else if (flow_ctrl & FLOW_CTRL_TX)
1273                 miireg = ADVERTISE_1000XPSE_ASYM;
1274         else if (flow_ctrl & FLOW_CTRL_RX)
1275                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1276         else
1277                 miireg = 0;
1278
1279         return miireg;
1280 }
1281
1282 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1283 {
1284         u8 cap = 0;
1285
1286         if (lcladv & ADVERTISE_1000XPAUSE) {
1287                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1288                         if (rmtadv & LPA_1000XPAUSE)
1289                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1290                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1291                                 cap = FLOW_CTRL_RX;
1292                 } else {
1293                         if (rmtadv & LPA_1000XPAUSE)
1294                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1295                 }
1296         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1297                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1298                         cap = FLOW_CTRL_TX;
1299         }
1300
1301         return cap;
1302 }
1303
1304 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1305 {
1306         u8 autoneg;
1307         u8 flowctrl = 0;
1308         u32 old_rx_mode = tp->rx_mode;
1309         u32 old_tx_mode = tp->tx_mode;
1310
1311         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1312                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1313         else
1314                 autoneg = tp->link_config.autoneg;
1315
1316         if (autoneg == AUTONEG_ENABLE &&
1317             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1318                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1319                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1320                 else
1321                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1322         } else
1323                 flowctrl = tp->link_config.flowctrl;
1324
1325         tp->link_config.active_flowctrl = flowctrl;
1326
1327         if (flowctrl & FLOW_CTRL_RX)
1328                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1329         else
1330                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1331
1332         if (old_rx_mode != tp->rx_mode)
1333                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1334
1335         if (flowctrl & FLOW_CTRL_TX)
1336                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1337         else
1338                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1339
1340         if (old_tx_mode != tp->tx_mode)
1341                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1342 }
1343
1344 static void tg3_adjust_link(struct net_device *dev)
1345 {
1346         u8 oldflowctrl, linkmesg = 0;
1347         u32 mac_mode, lcl_adv, rmt_adv;
1348         struct tg3 *tp = netdev_priv(dev);
1349         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1350
1351         spin_lock(&tp->lock);
1352
1353         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1354                                     MAC_MODE_HALF_DUPLEX);
1355
1356         oldflowctrl = tp->link_config.active_flowctrl;
1357
1358         if (phydev->link) {
1359                 lcl_adv = 0;
1360                 rmt_adv = 0;
1361
1362                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1363                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1364                 else
1365                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1366
1367                 if (phydev->duplex == DUPLEX_HALF)
1368                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1369                 else {
1370                         lcl_adv = tg3_advert_flowctrl_1000T(
1371                                   tp->link_config.flowctrl);
1372
1373                         if (phydev->pause)
1374                                 rmt_adv = LPA_PAUSE_CAP;
1375                         if (phydev->asym_pause)
1376                                 rmt_adv |= LPA_PAUSE_ASYM;
1377                 }
1378
1379                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1380         } else
1381                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1382
1383         if (mac_mode != tp->mac_mode) {
1384                 tp->mac_mode = mac_mode;
1385                 tw32_f(MAC_MODE, tp->mac_mode);
1386                 udelay(40);
1387         }
1388
1389         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1390                 if (phydev->speed == SPEED_10)
1391                         tw32(MAC_MI_STAT,
1392                              MAC_MI_STAT_10MBPS_MODE |
1393                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1394                 else
1395                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1396         }
1397
1398         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1399                 tw32(MAC_TX_LENGTHS,
1400                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1401                       (6 << TX_LENGTHS_IPG_SHIFT) |
1402                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1403         else
1404                 tw32(MAC_TX_LENGTHS,
1405                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1406                       (6 << TX_LENGTHS_IPG_SHIFT) |
1407                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1408
1409         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1410             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1411             phydev->speed != tp->link_config.active_speed ||
1412             phydev->duplex != tp->link_config.active_duplex ||
1413             oldflowctrl != tp->link_config.active_flowctrl)
1414             linkmesg = 1;
1415
1416         tp->link_config.active_speed = phydev->speed;
1417         tp->link_config.active_duplex = phydev->duplex;
1418
1419         spin_unlock(&tp->lock);
1420
1421         if (linkmesg)
1422                 tg3_link_report(tp);
1423 }
1424
1425 static int tg3_phy_init(struct tg3 *tp)
1426 {
1427         struct phy_device *phydev;
1428
1429         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1430                 return 0;
1431
1432         /* Bring the PHY back to a known state. */
1433         tg3_bmcr_reset(tp);
1434
1435         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1436
1437         /* Attach the MAC to the PHY. */
1438         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1439                              phydev->dev_flags, phydev->interface);
1440         if (IS_ERR(phydev)) {
1441                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1442                 return PTR_ERR(phydev);
1443         }
1444
1445         /* Mask with MAC supported features. */
1446         switch (phydev->interface) {
1447         case PHY_INTERFACE_MODE_GMII:
1448         case PHY_INTERFACE_MODE_RGMII:
1449                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1450                         phydev->supported &= (PHY_GBIT_FEATURES |
1451                                               SUPPORTED_Pause |
1452                                               SUPPORTED_Asym_Pause);
1453                         break;
1454                 }
1455                 /* fallthru */
1456         case PHY_INTERFACE_MODE_MII:
1457                 phydev->supported &= (PHY_BASIC_FEATURES |
1458                                       SUPPORTED_Pause |
1459                                       SUPPORTED_Asym_Pause);
1460                 break;
1461         default:
1462                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1463                 return -EINVAL;
1464         }
1465
1466         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1467
1468         phydev->advertising = phydev->supported;
1469
1470         return 0;
1471 }
1472
1473 static void tg3_phy_start(struct tg3 *tp)
1474 {
1475         struct phy_device *phydev;
1476
1477         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1478                 return;
1479
1480         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1481
1482         if (tp->link_config.phy_is_low_power) {
1483                 tp->link_config.phy_is_low_power = 0;
1484                 phydev->speed = tp->link_config.orig_speed;
1485                 phydev->duplex = tp->link_config.orig_duplex;
1486                 phydev->autoneg = tp->link_config.orig_autoneg;
1487                 phydev->advertising = tp->link_config.orig_advertising;
1488         }
1489
1490         phy_start(phydev);
1491
1492         phy_start_aneg(phydev);
1493 }
1494
1495 static void tg3_phy_stop(struct tg3 *tp)
1496 {
1497         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1498                 return;
1499
1500         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1501 }
1502
1503 static void tg3_phy_fini(struct tg3 *tp)
1504 {
1505         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1506                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1507                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1508         }
1509 }
1510
1511 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1512 {
1513         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1514         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1515 }
1516
1517 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1518 {
1519         u32 phytest;
1520
1521         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1522                 u32 phy;
1523
1524                 tg3_writephy(tp, MII_TG3_FET_TEST,
1525                              phytest | MII_TG3_FET_SHADOW_EN);
1526                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1527                         if (enable)
1528                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1529                         else
1530                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1531                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1532                 }
1533                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1534         }
1535 }
1536
1537 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1538 {
1539         u32 reg;
1540
1541         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1542                 return;
1543
1544         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1545                 tg3_phy_fet_toggle_apd(tp, enable);
1546                 return;
1547         }
1548
1549         reg = MII_TG3_MISC_SHDW_WREN |
1550               MII_TG3_MISC_SHDW_SCR5_SEL |
1551               MII_TG3_MISC_SHDW_SCR5_LPED |
1552               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1553               MII_TG3_MISC_SHDW_SCR5_SDTL |
1554               MII_TG3_MISC_SHDW_SCR5_C125OE;
1555         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1556                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1557
1558         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1559
1560
1561         reg = MII_TG3_MISC_SHDW_WREN |
1562               MII_TG3_MISC_SHDW_APD_SEL |
1563               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1564         if (enable)
1565                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1566
1567         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1568 }
1569
1570 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1571 {
1572         u32 phy;
1573
1574         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1575             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1576                 return;
1577
1578         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1579                 u32 ephy;
1580
1581                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1582                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1583
1584                         tg3_writephy(tp, MII_TG3_FET_TEST,
1585                                      ephy | MII_TG3_FET_SHADOW_EN);
1586                         if (!tg3_readphy(tp, reg, &phy)) {
1587                                 if (enable)
1588                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1589                                 else
1590                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1591                                 tg3_writephy(tp, reg, phy);
1592                         }
1593                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1594                 }
1595         } else {
1596                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1597                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1598                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1599                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1600                         if (enable)
1601                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1602                         else
1603                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1604                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1605                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1606                 }
1607         }
1608 }
1609
1610 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1611 {
1612         u32 val;
1613
1614         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1615                 return;
1616
1617         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1618             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1619                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1620                              (val | (1 << 15) | (1 << 4)));
1621 }
1622
1623 static void tg3_phy_apply_otp(struct tg3 *tp)
1624 {
1625         u32 otp, phy;
1626
1627         if (!tp->phy_otp)
1628                 return;
1629
1630         otp = tp->phy_otp;
1631
1632         /* Enable SM_DSP clock and tx 6dB coding. */
1633         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1634               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1635               MII_TG3_AUXCTL_ACTL_TX_6DB;
1636         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1637
1638         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1639         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1640         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1641
1642         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1643               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1644         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1645
1646         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1647         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1648         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1649
1650         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1651         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1652
1653         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1654         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1655
1656         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1657               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1658         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1659
1660         /* Turn off SM_DSP clock. */
1661         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1662               MII_TG3_AUXCTL_ACTL_TX_6DB;
1663         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1664 }
1665
1666 static int tg3_wait_macro_done(struct tg3 *tp)
1667 {
1668         int limit = 100;
1669
1670         while (limit--) {
1671                 u32 tmp32;
1672
1673                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1674                         if ((tmp32 & 0x1000) == 0)
1675                                 break;
1676                 }
1677         }
1678         if (limit < 0)
1679                 return -EBUSY;
1680
1681         return 0;
1682 }
1683
1684 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1685 {
1686         static const u32 test_pat[4][6] = {
1687         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1688         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1689         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1690         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1691         };
1692         int chan;
1693
1694         for (chan = 0; chan < 4; chan++) {
1695                 int i;
1696
1697                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1698                              (chan * 0x2000) | 0x0200);
1699                 tg3_writephy(tp, 0x16, 0x0002);
1700
1701                 for (i = 0; i < 6; i++)
1702                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1703                                      test_pat[chan][i]);
1704
1705                 tg3_writephy(tp, 0x16, 0x0202);
1706                 if (tg3_wait_macro_done(tp)) {
1707                         *resetp = 1;
1708                         return -EBUSY;
1709                 }
1710
1711                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1712                              (chan * 0x2000) | 0x0200);
1713                 tg3_writephy(tp, 0x16, 0x0082);
1714                 if (tg3_wait_macro_done(tp)) {
1715                         *resetp = 1;
1716                         return -EBUSY;
1717                 }
1718
1719                 tg3_writephy(tp, 0x16, 0x0802);
1720                 if (tg3_wait_macro_done(tp)) {
1721                         *resetp = 1;
1722                         return -EBUSY;
1723                 }
1724
1725                 for (i = 0; i < 6; i += 2) {
1726                         u32 low, high;
1727
1728                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1729                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1730                             tg3_wait_macro_done(tp)) {
1731                                 *resetp = 1;
1732                                 return -EBUSY;
1733                         }
1734                         low &= 0x7fff;
1735                         high &= 0x000f;
1736                         if (low != test_pat[chan][i] ||
1737                             high != test_pat[chan][i+1]) {
1738                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1739                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1740                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1741
1742                                 return -EBUSY;
1743                         }
1744                 }
1745         }
1746
1747         return 0;
1748 }
1749
1750 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1751 {
1752         int chan;
1753
1754         for (chan = 0; chan < 4; chan++) {
1755                 int i;
1756
1757                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1758                              (chan * 0x2000) | 0x0200);
1759                 tg3_writephy(tp, 0x16, 0x0002);
1760                 for (i = 0; i < 6; i++)
1761                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1762                 tg3_writephy(tp, 0x16, 0x0202);
1763                 if (tg3_wait_macro_done(tp))
1764                         return -EBUSY;
1765         }
1766
1767         return 0;
1768 }
1769
1770 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1771 {
1772         u32 reg32, phy9_orig;
1773         int retries, do_phy_reset, err;
1774
1775         retries = 10;
1776         do_phy_reset = 1;
1777         do {
1778                 if (do_phy_reset) {
1779                         err = tg3_bmcr_reset(tp);
1780                         if (err)
1781                                 return err;
1782                         do_phy_reset = 0;
1783                 }
1784
1785                 /* Disable transmitter and interrupt.  */
1786                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1787                         continue;
1788
1789                 reg32 |= 0x3000;
1790                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1791
1792                 /* Set full-duplex, 1000 mbps.  */
1793                 tg3_writephy(tp, MII_BMCR,
1794                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1795
1796                 /* Set to master mode.  */
1797                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1798                         continue;
1799
1800                 tg3_writephy(tp, MII_TG3_CTRL,
1801                              (MII_TG3_CTRL_AS_MASTER |
1802                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1803
1804                 /* Enable SM_DSP_CLOCK and 6dB.  */
1805                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1806
1807                 /* Block the PHY control access.  */
1808                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1809                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1810
1811                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1812                 if (!err)
1813                         break;
1814         } while (--retries);
1815
1816         err = tg3_phy_reset_chanpat(tp);
1817         if (err)
1818                 return err;
1819
1820         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1821         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1822
1823         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1824         tg3_writephy(tp, 0x16, 0x0000);
1825
1826         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1827             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1828                 /* Set Extended packet length bit for jumbo frames */
1829                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1830         }
1831         else {
1832                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1833         }
1834
1835         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1836
1837         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1838                 reg32 &= ~0x3000;
1839                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1840         } else if (!err)
1841                 err = -EBUSY;
1842
1843         return err;
1844 }
1845
1846 /* This will reset the tigon3 PHY if there is no valid
1847  * link unless the FORCE argument is non-zero.
1848  */
1849 static int tg3_phy_reset(struct tg3 *tp)
1850 {
1851         u32 cpmuctrl;
1852         u32 phy_status;
1853         int err;
1854
1855         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1856                 u32 val;
1857
1858                 val = tr32(GRC_MISC_CFG);
1859                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1860                 udelay(40);
1861         }
1862         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1863         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1864         if (err != 0)
1865                 return -EBUSY;
1866
1867         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1868                 netif_carrier_off(tp->dev);
1869                 tg3_link_report(tp);
1870         }
1871
1872         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1873             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1874             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1875                 err = tg3_phy_reset_5703_4_5(tp);
1876                 if (err)
1877                         return err;
1878                 goto out;
1879         }
1880
1881         cpmuctrl = 0;
1882         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1883             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1884                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1885                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1886                         tw32(TG3_CPMU_CTRL,
1887                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1888         }
1889
1890         err = tg3_bmcr_reset(tp);
1891         if (err)
1892                 return err;
1893
1894         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1895                 u32 phy;
1896
1897                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1898                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1899
1900                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1901         }
1902
1903         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1904             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1905                 u32 val;
1906
1907                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1908                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1909                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1910                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1911                         udelay(40);
1912                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1913                 }
1914         }
1915
1916         tg3_phy_apply_otp(tp);
1917
1918         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1919                 tg3_phy_toggle_apd(tp, true);
1920         else
1921                 tg3_phy_toggle_apd(tp, false);
1922
1923 out:
1924         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1925                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1926                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1927                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1928                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1929                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1930                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1931         }
1932         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1933                 tg3_writephy(tp, 0x1c, 0x8d68);
1934                 tg3_writephy(tp, 0x1c, 0x8d68);
1935         }
1936         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1937                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1938                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1939                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1940                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1941                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1942                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1943                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1944                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1945         }
1946         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1947                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1949                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1950                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1951                         tg3_writephy(tp, MII_TG3_TEST1,
1952                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1953                 } else
1954                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1955                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1956         }
1957         /* Set Extended packet length bit (bit 14) on all chips that */
1958         /* support jumbo frames */
1959         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1960                 /* Cannot do read-modify-write on 5401 */
1961                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1962         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1963                 u32 phy_reg;
1964
1965                 /* Set bit 14 with read-modify-write to preserve other bits */
1966                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1967                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1968                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1969         }
1970
1971         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1972          * jumbo frames transmission.
1973          */
1974         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1975                 u32 phy_reg;
1976
1977                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1978                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1979                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1980         }
1981
1982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1983                 /* adjust output voltage */
1984                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1985         }
1986
1987         tg3_phy_toggle_automdix(tp, 1);
1988         tg3_phy_set_wirespeed(tp);
1989         return 0;
1990 }
1991
1992 static void tg3_frob_aux_power(struct tg3 *tp)
1993 {
1994         struct tg3 *tp_peer = tp;
1995
1996         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1997                 return;
1998
1999         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2000             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2002                 struct net_device *dev_peer;
2003
2004                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2005                 /* remove_one() may have been run on the peer. */
2006                 if (!dev_peer)
2007                         tp_peer = tp;
2008                 else
2009                         tp_peer = netdev_priv(dev_peer);
2010         }
2011
2012         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2013             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2014             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2015             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2016                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2017                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2018                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2019                                     (GRC_LCLCTRL_GPIO_OE0 |
2020                                      GRC_LCLCTRL_GPIO_OE1 |
2021                                      GRC_LCLCTRL_GPIO_OE2 |
2022                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2023                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2024                                     100);
2025                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2026                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2027                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2028                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2029                                              GRC_LCLCTRL_GPIO_OE1 |
2030                                              GRC_LCLCTRL_GPIO_OE2 |
2031                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2032                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2033                                              tp->grc_local_ctrl;
2034                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2035
2036                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2037                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2038
2039                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2040                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2041                 } else {
2042                         u32 no_gpio2;
2043                         u32 grc_local_ctrl = 0;
2044
2045                         if (tp_peer != tp &&
2046                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2047                                 return;
2048
2049                         /* Workaround to prevent overdrawing Amps. */
2050                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2051                             ASIC_REV_5714) {
2052                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2053                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2054                                             grc_local_ctrl, 100);
2055                         }
2056
2057                         /* On 5753 and variants, GPIO2 cannot be used. */
2058                         no_gpio2 = tp->nic_sram_data_cfg &
2059                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2060
2061                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2062                                          GRC_LCLCTRL_GPIO_OE1 |
2063                                          GRC_LCLCTRL_GPIO_OE2 |
2064                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2065                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2066                         if (no_gpio2) {
2067                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2068                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2069                         }
2070                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2071                                                     grc_local_ctrl, 100);
2072
2073                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2074
2075                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2076                                                     grc_local_ctrl, 100);
2077
2078                         if (!no_gpio2) {
2079                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2080                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2081                                             grc_local_ctrl, 100);
2082                         }
2083                 }
2084         } else {
2085                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2086                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2087                         if (tp_peer != tp &&
2088                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2089                                 return;
2090
2091                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2092                                     (GRC_LCLCTRL_GPIO_OE1 |
2093                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2094
2095                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2096                                     GRC_LCLCTRL_GPIO_OE1, 100);
2097
2098                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2099                                     (GRC_LCLCTRL_GPIO_OE1 |
2100                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2101                 }
2102         }
2103 }
2104
2105 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2106 {
2107         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2108                 return 1;
2109         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2110                 if (speed != SPEED_10)
2111                         return 1;
2112         } else if (speed == SPEED_10)
2113                 return 1;
2114
2115         return 0;
2116 }
2117
2118 static int tg3_setup_phy(struct tg3 *, int);
2119
2120 #define RESET_KIND_SHUTDOWN     0
2121 #define RESET_KIND_INIT         1
2122 #define RESET_KIND_SUSPEND      2
2123
2124 static void tg3_write_sig_post_reset(struct tg3 *, int);
2125 static int tg3_halt_cpu(struct tg3 *, u32);
2126
2127 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2128 {
2129         u32 val;
2130
2131         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2132                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2133                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2134                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2135
2136                         sg_dig_ctrl |=
2137                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2138                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2139                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2140                 }
2141                 return;
2142         }
2143
2144         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2145                 tg3_bmcr_reset(tp);
2146                 val = tr32(GRC_MISC_CFG);
2147                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2148                 udelay(40);
2149                 return;
2150         } else if (do_low_power) {
2151                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2152                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2153
2154                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2155                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2156                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2157                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2158                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2159         }
2160
2161         /* The PHY should not be powered down on some chips because
2162          * of bugs.
2163          */
2164         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2165             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2166             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2167              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2168                 return;
2169
2170         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2171             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2172                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2173                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2174                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2175                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2176         }
2177
2178         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2179 }
2180
2181 /* tp->lock is held. */
2182 static int tg3_nvram_lock(struct tg3 *tp)
2183 {
2184         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2185                 int i;
2186
2187                 if (tp->nvram_lock_cnt == 0) {
2188                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2189                         for (i = 0; i < 8000; i++) {
2190                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2191                                         break;
2192                                 udelay(20);
2193                         }
2194                         if (i == 8000) {
2195                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2196                                 return -ENODEV;
2197                         }
2198                 }
2199                 tp->nvram_lock_cnt++;
2200         }
2201         return 0;
2202 }
2203
2204 /* tp->lock is held. */
2205 static void tg3_nvram_unlock(struct tg3 *tp)
2206 {
2207         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2208                 if (tp->nvram_lock_cnt > 0)
2209                         tp->nvram_lock_cnt--;
2210                 if (tp->nvram_lock_cnt == 0)
2211                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2212         }
2213 }
2214
2215 /* tp->lock is held. */
2216 static void tg3_enable_nvram_access(struct tg3 *tp)
2217 {
2218         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2219             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2220                 u32 nvaccess = tr32(NVRAM_ACCESS);
2221
2222                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2223         }
2224 }
2225
2226 /* tp->lock is held. */
2227 static void tg3_disable_nvram_access(struct tg3 *tp)
2228 {
2229         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2230             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2231                 u32 nvaccess = tr32(NVRAM_ACCESS);
2232
2233                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2234         }
2235 }
2236
2237 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2238                                         u32 offset, u32 *val)
2239 {
2240         u32 tmp;
2241         int i;
2242
2243         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2244                 return -EINVAL;
2245
2246         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2247                                         EEPROM_ADDR_DEVID_MASK |
2248                                         EEPROM_ADDR_READ);
2249         tw32(GRC_EEPROM_ADDR,
2250              tmp |
2251              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2252              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2253               EEPROM_ADDR_ADDR_MASK) |
2254              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2255
2256         for (i = 0; i < 1000; i++) {
2257                 tmp = tr32(GRC_EEPROM_ADDR);
2258
2259                 if (tmp & EEPROM_ADDR_COMPLETE)
2260                         break;
2261                 msleep(1);
2262         }
2263         if (!(tmp & EEPROM_ADDR_COMPLETE))
2264                 return -EBUSY;
2265
2266         tmp = tr32(GRC_EEPROM_DATA);
2267
2268         /*
2269          * The data will always be opposite the native endian
2270          * format.  Perform a blind byteswap to compensate.
2271          */
2272         *val = swab32(tmp);
2273
2274         return 0;
2275 }
2276
2277 #define NVRAM_CMD_TIMEOUT 10000
2278
2279 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2280 {
2281         int i;
2282
2283         tw32(NVRAM_CMD, nvram_cmd);
2284         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2285                 udelay(10);
2286                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2287                         udelay(10);
2288                         break;
2289                 }
2290         }
2291
2292         if (i == NVRAM_CMD_TIMEOUT)
2293                 return -EBUSY;
2294
2295         return 0;
2296 }
2297
2298 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2299 {
2300         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2301             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2302             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2303            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2304             (tp->nvram_jedecnum == JEDEC_ATMEL))
2305
2306                 addr = ((addr / tp->nvram_pagesize) <<
2307                         ATMEL_AT45DB0X1B_PAGE_POS) +
2308                        (addr % tp->nvram_pagesize);
2309
2310         return addr;
2311 }
2312
2313 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2314 {
2315         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2316             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2317             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2318            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2319             (tp->nvram_jedecnum == JEDEC_ATMEL))
2320
2321                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2322                         tp->nvram_pagesize) +
2323                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2324
2325         return addr;
2326 }
2327
2328 /* NOTE: Data read in from NVRAM is byteswapped according to
2329  * the byteswapping settings for all other register accesses.
2330  * tg3 devices are BE devices, so on a BE machine, the data
2331  * returned will be exactly as it is seen in NVRAM.  On a LE
2332  * machine, the 32-bit value will be byteswapped.
2333  */
2334 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2335 {
2336         int ret;
2337
2338         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2339                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2340
2341         offset = tg3_nvram_phys_addr(tp, offset);
2342
2343         if (offset > NVRAM_ADDR_MSK)
2344                 return -EINVAL;
2345
2346         ret = tg3_nvram_lock(tp);
2347         if (ret)
2348                 return ret;
2349
2350         tg3_enable_nvram_access(tp);
2351
2352         tw32(NVRAM_ADDR, offset);
2353         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2354                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2355
2356         if (ret == 0)
2357                 *val = tr32(NVRAM_RDDATA);
2358
2359         tg3_disable_nvram_access(tp);
2360
2361         tg3_nvram_unlock(tp);
2362
2363         return ret;
2364 }
2365
2366 /* Ensures NVRAM data is in bytestream format. */
2367 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2368 {
2369         u32 v;
2370         int res = tg3_nvram_read(tp, offset, &v);
2371         if (!res)
2372                 *val = cpu_to_be32(v);
2373         return res;
2374 }
2375
2376 /* tp->lock is held. */
2377 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2378 {
2379         u32 addr_high, addr_low;
2380         int i;
2381
2382         addr_high = ((tp->dev->dev_addr[0] << 8) |
2383                      tp->dev->dev_addr[1]);
2384         addr_low = ((tp->dev->dev_addr[2] << 24) |
2385                     (tp->dev->dev_addr[3] << 16) |
2386                     (tp->dev->dev_addr[4] <<  8) |
2387                     (tp->dev->dev_addr[5] <<  0));
2388         for (i = 0; i < 4; i++) {
2389                 if (i == 1 && skip_mac_1)
2390                         continue;
2391                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2392                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2393         }
2394
2395         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2396             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2397                 for (i = 0; i < 12; i++) {
2398                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2399                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2400                 }
2401         }
2402
2403         addr_high = (tp->dev->dev_addr[0] +
2404                      tp->dev->dev_addr[1] +
2405                      tp->dev->dev_addr[2] +
2406                      tp->dev->dev_addr[3] +
2407                      tp->dev->dev_addr[4] +
2408                      tp->dev->dev_addr[5]) &
2409                 TX_BACKOFF_SEED_MASK;
2410         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2411 }
2412
2413 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2414 {
2415         u32 misc_host_ctrl;
2416         bool device_should_wake, do_low_power;
2417
2418         /* Make sure register accesses (indirect or otherwise)
2419          * will function correctly.
2420          */
2421         pci_write_config_dword(tp->pdev,
2422                                TG3PCI_MISC_HOST_CTRL,
2423                                tp->misc_host_ctrl);
2424
2425         switch (state) {
2426         case PCI_D0:
2427                 pci_enable_wake(tp->pdev, state, false);
2428                 pci_set_power_state(tp->pdev, PCI_D0);
2429
2430                 /* Switch out of Vaux if it is a NIC */
2431                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2432                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2433
2434                 return 0;
2435
2436         case PCI_D1:
2437         case PCI_D2:
2438         case PCI_D3hot:
2439                 break;
2440
2441         default:
2442                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2443                         tp->dev->name, state);
2444                 return -EINVAL;
2445         }
2446
2447         /* Restore the CLKREQ setting. */
2448         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2449                 u16 lnkctl;
2450
2451                 pci_read_config_word(tp->pdev,
2452                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2453                                      &lnkctl);
2454                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2455                 pci_write_config_word(tp->pdev,
2456                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2457                                       lnkctl);
2458         }
2459
2460         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2461         tw32(TG3PCI_MISC_HOST_CTRL,
2462              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2463
2464         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2465                              device_may_wakeup(&tp->pdev->dev) &&
2466                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2467
2468         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2469                 do_low_power = false;
2470                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2471                     !tp->link_config.phy_is_low_power) {
2472                         struct phy_device *phydev;
2473                         u32 phyid, advertising;
2474
2475                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2476
2477                         tp->link_config.phy_is_low_power = 1;
2478
2479                         tp->link_config.orig_speed = phydev->speed;
2480                         tp->link_config.orig_duplex = phydev->duplex;
2481                         tp->link_config.orig_autoneg = phydev->autoneg;
2482                         tp->link_config.orig_advertising = phydev->advertising;
2483
2484                         advertising = ADVERTISED_TP |
2485                                       ADVERTISED_Pause |
2486                                       ADVERTISED_Autoneg |
2487                                       ADVERTISED_10baseT_Half;
2488
2489                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2490                             device_should_wake) {
2491                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2492                                         advertising |=
2493                                                 ADVERTISED_100baseT_Half |
2494                                                 ADVERTISED_100baseT_Full |
2495                                                 ADVERTISED_10baseT_Full;
2496                                 else
2497                                         advertising |= ADVERTISED_10baseT_Full;
2498                         }
2499
2500                         phydev->advertising = advertising;
2501
2502                         phy_start_aneg(phydev);
2503
2504                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2505                         if (phyid != TG3_PHY_ID_BCMAC131) {
2506                                 phyid &= TG3_PHY_OUI_MASK;
2507                                 if (phyid == TG3_PHY_OUI_1 ||
2508                                     phyid == TG3_PHY_OUI_2 ||
2509                                     phyid == TG3_PHY_OUI_3)
2510                                         do_low_power = true;
2511                         }
2512                 }
2513         } else {
2514                 do_low_power = true;
2515
2516                 if (tp->link_config.phy_is_low_power == 0) {
2517                         tp->link_config.phy_is_low_power = 1;
2518                         tp->link_config.orig_speed = tp->link_config.speed;
2519                         tp->link_config.orig_duplex = tp->link_config.duplex;
2520                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2521                 }
2522
2523                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2524                         tp->link_config.speed = SPEED_10;
2525                         tp->link_config.duplex = DUPLEX_HALF;
2526                         tp->link_config.autoneg = AUTONEG_ENABLE;
2527                         tg3_setup_phy(tp, 0);
2528                 }
2529         }
2530
2531         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2532                 u32 val;
2533
2534                 val = tr32(GRC_VCPU_EXT_CTRL);
2535                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2536         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2537                 int i;
2538                 u32 val;
2539
2540                 for (i = 0; i < 200; i++) {
2541                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2542                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2543                                 break;
2544                         msleep(1);
2545                 }
2546         }
2547         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2548                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2549                                                      WOL_DRV_STATE_SHUTDOWN |
2550                                                      WOL_DRV_WOL |
2551                                                      WOL_SET_MAGIC_PKT);
2552
2553         if (device_should_wake) {
2554                 u32 mac_mode;
2555
2556                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2557                         if (do_low_power) {
2558                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2559                                 udelay(40);
2560                         }
2561
2562                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2563                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2564                         else
2565                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2566
2567                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2568                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2569                             ASIC_REV_5700) {
2570                                 u32 speed = (tp->tg3_flags &
2571                                              TG3_FLAG_WOL_SPEED_100MB) ?
2572                                              SPEED_100 : SPEED_10;
2573                                 if (tg3_5700_link_polarity(tp, speed))
2574                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2575                                 else
2576                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2577                         }
2578                 } else {
2579                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2580                 }
2581
2582                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2583                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2584
2585                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2586                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2587                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2588                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2589                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2590                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2591
2592                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2593                         mac_mode |= tp->mac_mode &
2594                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2595                         if (mac_mode & MAC_MODE_APE_TX_EN)
2596                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2597                 }
2598
2599                 tw32_f(MAC_MODE, mac_mode);
2600                 udelay(100);
2601
2602                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2603                 udelay(10);
2604         }
2605
2606         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2607             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2608              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2609                 u32 base_val;
2610
2611                 base_val = tp->pci_clock_ctrl;
2612                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2613                              CLOCK_CTRL_TXCLK_DISABLE);
2614
2615                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2616                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2617         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2618                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2619                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2620                 /* do nothing */
2621         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2622                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2623                 u32 newbits1, newbits2;
2624
2625                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2626                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2627                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2628                                     CLOCK_CTRL_TXCLK_DISABLE |
2629                                     CLOCK_CTRL_ALTCLK);
2630                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2631                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2632                         newbits1 = CLOCK_CTRL_625_CORE;
2633                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2634                 } else {
2635                         newbits1 = CLOCK_CTRL_ALTCLK;
2636                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2637                 }
2638
2639                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2640                             40);
2641
2642                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2643                             40);
2644
2645                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2646                         u32 newbits3;
2647
2648                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2649                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2650                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2651                                             CLOCK_CTRL_TXCLK_DISABLE |
2652                                             CLOCK_CTRL_44MHZ_CORE);
2653                         } else {
2654                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2655                         }
2656
2657                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2658                                     tp->pci_clock_ctrl | newbits3, 40);
2659                 }
2660         }
2661
2662         if (!(device_should_wake) &&
2663             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2664                 tg3_power_down_phy(tp, do_low_power);
2665
2666         tg3_frob_aux_power(tp);
2667
2668         /* Workaround for unstable PLL clock */
2669         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2670             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2671                 u32 val = tr32(0x7d00);
2672
2673                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2674                 tw32(0x7d00, val);
2675                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2676                         int err;
2677
2678                         err = tg3_nvram_lock(tp);
2679                         tg3_halt_cpu(tp, RX_CPU_BASE);
2680                         if (!err)
2681                                 tg3_nvram_unlock(tp);
2682                 }
2683         }
2684
2685         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2686
2687         if (device_should_wake)
2688                 pci_enable_wake(tp->pdev, state, true);
2689
2690         /* Finally, set the new power state. */
2691         pci_set_power_state(tp->pdev, state);
2692
2693         return 0;
2694 }
2695
2696 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2697 {
2698         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2699         case MII_TG3_AUX_STAT_10HALF:
2700                 *speed = SPEED_10;
2701                 *duplex = DUPLEX_HALF;
2702                 break;
2703
2704         case MII_TG3_AUX_STAT_10FULL:
2705                 *speed = SPEED_10;
2706                 *duplex = DUPLEX_FULL;
2707                 break;
2708
2709         case MII_TG3_AUX_STAT_100HALF:
2710                 *speed = SPEED_100;
2711                 *duplex = DUPLEX_HALF;
2712                 break;
2713
2714         case MII_TG3_AUX_STAT_100FULL:
2715                 *speed = SPEED_100;
2716                 *duplex = DUPLEX_FULL;
2717                 break;
2718
2719         case MII_TG3_AUX_STAT_1000HALF:
2720                 *speed = SPEED_1000;
2721                 *duplex = DUPLEX_HALF;
2722                 break;
2723
2724         case MII_TG3_AUX_STAT_1000FULL:
2725                 *speed = SPEED_1000;
2726                 *duplex = DUPLEX_FULL;
2727                 break;
2728
2729         default:
2730                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2731                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2732                                  SPEED_10;
2733                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2734                                   DUPLEX_HALF;
2735                         break;
2736                 }
2737                 *speed = SPEED_INVALID;
2738                 *duplex = DUPLEX_INVALID;
2739                 break;
2740         }
2741 }
2742
2743 static void tg3_phy_copper_begin(struct tg3 *tp)
2744 {
2745         u32 new_adv;
2746         int i;
2747
2748         if (tp->link_config.phy_is_low_power) {
2749                 /* Entering low power mode.  Disable gigabit and
2750                  * 100baseT advertisements.
2751                  */
2752                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2753
2754                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2755                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2756                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2757                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2758
2759                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2760         } else if (tp->link_config.speed == SPEED_INVALID) {
2761                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2762                         tp->link_config.advertising &=
2763                                 ~(ADVERTISED_1000baseT_Half |
2764                                   ADVERTISED_1000baseT_Full);
2765
2766                 new_adv = ADVERTISE_CSMA;
2767                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2768                         new_adv |= ADVERTISE_10HALF;
2769                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2770                         new_adv |= ADVERTISE_10FULL;
2771                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2772                         new_adv |= ADVERTISE_100HALF;
2773                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2774                         new_adv |= ADVERTISE_100FULL;
2775
2776                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2777
2778                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2779
2780                 if (tp->link_config.advertising &
2781                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2782                         new_adv = 0;
2783                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2784                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2785                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2786                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2787                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2788                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2789                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2790                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2791                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2792                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2793                 } else {
2794                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2795                 }
2796         } else {
2797                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2798                 new_adv |= ADVERTISE_CSMA;
2799
2800                 /* Asking for a specific link mode. */
2801                 if (tp->link_config.speed == SPEED_1000) {
2802                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2803
2804                         if (tp->link_config.duplex == DUPLEX_FULL)
2805                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2806                         else
2807                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2808                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2809                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2810                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2811                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2812                 } else {
2813                         if (tp->link_config.speed == SPEED_100) {
2814                                 if (tp->link_config.duplex == DUPLEX_FULL)
2815                                         new_adv |= ADVERTISE_100FULL;
2816                                 else
2817                                         new_adv |= ADVERTISE_100HALF;
2818                         } else {
2819                                 if (tp->link_config.duplex == DUPLEX_FULL)
2820                                         new_adv |= ADVERTISE_10FULL;
2821                                 else
2822                                         new_adv |= ADVERTISE_10HALF;
2823                         }
2824                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2825
2826                         new_adv = 0;
2827                 }
2828
2829                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2830         }
2831
2832         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2833             tp->link_config.speed != SPEED_INVALID) {
2834                 u32 bmcr, orig_bmcr;
2835
2836                 tp->link_config.active_speed = tp->link_config.speed;
2837                 tp->link_config.active_duplex = tp->link_config.duplex;
2838
2839                 bmcr = 0;
2840                 switch (tp->link_config.speed) {
2841                 default:
2842                 case SPEED_10:
2843                         break;
2844
2845                 case SPEED_100:
2846                         bmcr |= BMCR_SPEED100;
2847                         break;
2848
2849                 case SPEED_1000:
2850                         bmcr |= TG3_BMCR_SPEED1000;
2851                         break;
2852                 }
2853
2854                 if (tp->link_config.duplex == DUPLEX_FULL)
2855                         bmcr |= BMCR_FULLDPLX;
2856
2857                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2858                     (bmcr != orig_bmcr)) {
2859                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2860                         for (i = 0; i < 1500; i++) {
2861                                 u32 tmp;
2862
2863                                 udelay(10);
2864                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2865                                     tg3_readphy(tp, MII_BMSR, &tmp))
2866                                         continue;
2867                                 if (!(tmp & BMSR_LSTATUS)) {
2868                                         udelay(40);
2869                                         break;
2870                                 }
2871                         }
2872                         tg3_writephy(tp, MII_BMCR, bmcr);
2873                         udelay(40);
2874                 }
2875         } else {
2876                 tg3_writephy(tp, MII_BMCR,
2877                              BMCR_ANENABLE | BMCR_ANRESTART);
2878         }
2879 }
2880
2881 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2882 {
2883         int err;
2884
2885         /* Turn off tap power management. */
2886         /* Set Extended packet length bit */
2887         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2888
2889         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2890         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2891
2892         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2893         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2894
2895         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2896         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2897
2898         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2899         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2900
2901         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2902         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2903
2904         udelay(40);
2905
2906         return err;
2907 }
2908
2909 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2910 {
2911         u32 adv_reg, all_mask = 0;
2912
2913         if (mask & ADVERTISED_10baseT_Half)
2914                 all_mask |= ADVERTISE_10HALF;
2915         if (mask & ADVERTISED_10baseT_Full)
2916                 all_mask |= ADVERTISE_10FULL;
2917         if (mask & ADVERTISED_100baseT_Half)
2918                 all_mask |= ADVERTISE_100HALF;
2919         if (mask & ADVERTISED_100baseT_Full)
2920                 all_mask |= ADVERTISE_100FULL;
2921
2922         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2923                 return 0;
2924
2925         if ((adv_reg & all_mask) != all_mask)
2926                 return 0;
2927         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2928                 u32 tg3_ctrl;
2929
2930                 all_mask = 0;
2931                 if (mask & ADVERTISED_1000baseT_Half)
2932                         all_mask |= ADVERTISE_1000HALF;
2933                 if (mask & ADVERTISED_1000baseT_Full)
2934                         all_mask |= ADVERTISE_1000FULL;
2935
2936                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2937                         return 0;
2938
2939                 if ((tg3_ctrl & all_mask) != all_mask)
2940                         return 0;
2941         }
2942         return 1;
2943 }
2944
2945 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2946 {
2947         u32 curadv, reqadv;
2948
2949         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2950                 return 1;
2951
2952         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2953         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2954
2955         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2956                 if (curadv != reqadv)
2957                         return 0;
2958
2959                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2960                         tg3_readphy(tp, MII_LPA, rmtadv);
2961         } else {
2962                 /* Reprogram the advertisement register, even if it
2963                  * does not affect the current link.  If the link
2964                  * gets renegotiated in the future, we can save an
2965                  * additional renegotiation cycle by advertising
2966                  * it correctly in the first place.
2967                  */
2968                 if (curadv != reqadv) {
2969                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2970                                      ADVERTISE_PAUSE_ASYM);
2971                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2972                 }
2973         }
2974
2975         return 1;
2976 }
2977
2978 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2979 {
2980         int current_link_up;
2981         u32 bmsr, dummy;
2982         u32 lcl_adv, rmt_adv;
2983         u16 current_speed;
2984         u8 current_duplex;
2985         int i, err;
2986
2987         tw32(MAC_EVENT, 0);
2988
2989         tw32_f(MAC_STATUS,
2990              (MAC_STATUS_SYNC_CHANGED |
2991               MAC_STATUS_CFG_CHANGED |
2992               MAC_STATUS_MI_COMPLETION |
2993               MAC_STATUS_LNKSTATE_CHANGED));
2994         udelay(40);
2995
2996         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2997                 tw32_f(MAC_MI_MODE,
2998                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2999                 udelay(80);
3000         }
3001
3002         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3003
3004         /* Some third-party PHYs need to be reset on link going
3005          * down.
3006          */
3007         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3008              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3009              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3010             netif_carrier_ok(tp->dev)) {
3011                 tg3_readphy(tp, MII_BMSR, &bmsr);
3012                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3013                     !(bmsr & BMSR_LSTATUS))
3014                         force_reset = 1;
3015         }
3016         if (force_reset)
3017                 tg3_phy_reset(tp);
3018
3019         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3020                 tg3_readphy(tp, MII_BMSR, &bmsr);
3021                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3022                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3023                         bmsr = 0;
3024
3025                 if (!(bmsr & BMSR_LSTATUS)) {
3026                         err = tg3_init_5401phy_dsp(tp);
3027                         if (err)
3028                                 return err;
3029
3030                         tg3_readphy(tp, MII_BMSR, &bmsr);
3031                         for (i = 0; i < 1000; i++) {
3032                                 udelay(10);
3033                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3034                                     (bmsr & BMSR_LSTATUS)) {
3035                                         udelay(40);
3036                                         break;
3037                                 }
3038                         }
3039
3040                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3041                             !(bmsr & BMSR_LSTATUS) &&
3042                             tp->link_config.active_speed == SPEED_1000) {
3043                                 err = tg3_phy_reset(tp);
3044                                 if (!err)
3045                                         err = tg3_init_5401phy_dsp(tp);
3046                                 if (err)
3047                                         return err;
3048                         }
3049                 }
3050         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3051                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3052                 /* 5701 {A0,B0} CRC bug workaround */
3053                 tg3_writephy(tp, 0x15, 0x0a75);
3054                 tg3_writephy(tp, 0x1c, 0x8c68);
3055                 tg3_writephy(tp, 0x1c, 0x8d68);
3056                 tg3_writephy(tp, 0x1c, 0x8c68);
3057         }
3058
3059         /* Clear pending interrupts... */
3060         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3061         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3062
3063         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3064                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3065         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3066                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3067
3068         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3069             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3070                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3071                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3072                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3073                 else
3074                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3075         }
3076
3077         current_link_up = 0;
3078         current_speed = SPEED_INVALID;
3079         current_duplex = DUPLEX_INVALID;
3080
3081         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3082                 u32 val;
3083
3084                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3085                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3086                 if (!(val & (1 << 10))) {
3087                         val |= (1 << 10);
3088                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3089                         goto relink;
3090                 }
3091         }
3092
3093         bmsr = 0;
3094         for (i = 0; i < 100; i++) {
3095                 tg3_readphy(tp, MII_BMSR, &bmsr);
3096                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3097                     (bmsr & BMSR_LSTATUS))
3098                         break;
3099                 udelay(40);
3100         }
3101
3102         if (bmsr & BMSR_LSTATUS) {
3103                 u32 aux_stat, bmcr;
3104
3105                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3106                 for (i = 0; i < 2000; i++) {
3107                         udelay(10);
3108                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3109                             aux_stat)
3110                                 break;
3111                 }
3112
3113                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3114                                              &current_speed,
3115                                              &current_duplex);
3116
3117                 bmcr = 0;
3118                 for (i = 0; i < 200; i++) {
3119                         tg3_readphy(tp, MII_BMCR, &bmcr);
3120                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3121                                 continue;
3122                         if (bmcr && bmcr != 0x7fff)
3123                                 break;
3124                         udelay(10);
3125                 }
3126
3127                 lcl_adv = 0;
3128                 rmt_adv = 0;
3129
3130                 tp->link_config.active_speed = current_speed;
3131                 tp->link_config.active_duplex = current_duplex;
3132
3133                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3134                         if ((bmcr & BMCR_ANENABLE) &&
3135                             tg3_copper_is_advertising_all(tp,
3136                                                 tp->link_config.advertising)) {
3137                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3138                                                                   &rmt_adv))
3139                                         current_link_up = 1;
3140                         }
3141                 } else {
3142                         if (!(bmcr & BMCR_ANENABLE) &&
3143                             tp->link_config.speed == current_speed &&
3144                             tp->link_config.duplex == current_duplex &&
3145                             tp->link_config.flowctrl ==
3146                             tp->link_config.active_flowctrl) {
3147                                 current_link_up = 1;
3148                         }
3149                 }
3150
3151                 if (current_link_up == 1 &&
3152                     tp->link_config.active_duplex == DUPLEX_FULL)
3153                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3154         }
3155
3156 relink:
3157         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3158                 u32 tmp;
3159
3160                 tg3_phy_copper_begin(tp);
3161
3162                 tg3_readphy(tp, MII_BMSR, &tmp);
3163                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3164                     (tmp & BMSR_LSTATUS))
3165                         current_link_up = 1;
3166         }
3167
3168         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3169         if (current_link_up == 1) {
3170                 if (tp->link_config.active_speed == SPEED_100 ||
3171                     tp->link_config.active_speed == SPEED_10)
3172                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3173                 else
3174                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3175         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3176                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3177         else
3178                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3179
3180         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3181         if (tp->link_config.active_duplex == DUPLEX_HALF)
3182                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3183
3184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3185                 if (current_link_up == 1 &&
3186                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3187                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3188                 else
3189                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3190         }
3191
3192         /* ??? Without this setting Netgear GA302T PHY does not
3193          * ??? send/receive packets...
3194          */
3195         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3196             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3197                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3198                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3199                 udelay(80);
3200         }
3201
3202         tw32_f(MAC_MODE, tp->mac_mode);
3203         udelay(40);
3204
3205         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3206                 /* Polled via timer. */
3207                 tw32_f(MAC_EVENT, 0);
3208         } else {
3209                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3210         }
3211         udelay(40);
3212
3213         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3214             current_link_up == 1 &&
3215             tp->link_config.active_speed == SPEED_1000 &&
3216             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3217              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3218                 udelay(120);
3219                 tw32_f(MAC_STATUS,
3220                      (MAC_STATUS_SYNC_CHANGED |
3221                       MAC_STATUS_CFG_CHANGED));
3222                 udelay(40);
3223                 tg3_write_mem(tp,
3224                               NIC_SRAM_FIRMWARE_MBOX,
3225                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3226         }
3227
3228         /* Prevent send BD corruption. */
3229         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3230                 u16 oldlnkctl, newlnkctl;
3231
3232                 pci_read_config_word(tp->pdev,
3233                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3234                                      &oldlnkctl);
3235                 if (tp->link_config.active_speed == SPEED_100 ||
3236                     tp->link_config.active_speed == SPEED_10)
3237                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3238                 else
3239                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3240                 if (newlnkctl != oldlnkctl)
3241                         pci_write_config_word(tp->pdev,
3242                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3243                                               newlnkctl);
3244         } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3245                 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3246                 if (tp->link_config.active_speed == SPEED_100 ||
3247                     tp->link_config.active_speed == SPEED_10)
3248                         newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3249                 else
3250                         newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3251                 if (newreg != oldreg)
3252                         tw32(TG3_PCIE_LNKCTL, newreg);
3253         }
3254
3255         if (current_link_up != netif_carrier_ok(tp->dev)) {
3256                 if (current_link_up)
3257                         netif_carrier_on(tp->dev);
3258                 else
3259                         netif_carrier_off(tp->dev);
3260                 tg3_link_report(tp);
3261         }
3262
3263         return 0;
3264 }
3265
3266 struct tg3_fiber_aneginfo {
3267         int state;
3268 #define ANEG_STATE_UNKNOWN              0
3269 #define ANEG_STATE_AN_ENABLE            1
3270 #define ANEG_STATE_RESTART_INIT         2
3271 #define ANEG_STATE_RESTART              3
3272 #define ANEG_STATE_DISABLE_LINK_OK      4
3273 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3274 #define ANEG_STATE_ABILITY_DETECT       6
3275 #define ANEG_STATE_ACK_DETECT_INIT      7
3276 #define ANEG_STATE_ACK_DETECT           8
3277 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3278 #define ANEG_STATE_COMPLETE_ACK         10
3279 #define ANEG_STATE_IDLE_DETECT_INIT     11
3280 #define ANEG_STATE_IDLE_DETECT          12
3281 #define ANEG_STATE_LINK_OK              13
3282 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3283 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3284
3285         u32 flags;
3286 #define MR_AN_ENABLE            0x00000001
3287 #define MR_RESTART_AN           0x00000002
3288 #define MR_AN_COMPLETE          0x00000004
3289 #define MR_PAGE_RX              0x00000008
3290 #define MR_NP_LOADED            0x00000010
3291 #define MR_TOGGLE_TX            0x00000020
3292 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3293 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3294 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3295 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3296 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3297 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3298 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3299 #define MR_TOGGLE_RX            0x00002000
3300 #define MR_NP_RX                0x00004000
3301
3302 #define MR_LINK_OK              0x80000000
3303
3304         unsigned long link_time, cur_time;
3305
3306         u32 ability_match_cfg;
3307         int ability_match_count;
3308
3309         char ability_match, idle_match, ack_match;
3310
3311         u32 txconfig, rxconfig;
3312 #define ANEG_CFG_NP             0x00000080
3313 #define ANEG_CFG_ACK            0x00000040
3314 #define ANEG_CFG_RF2            0x00000020
3315 #define ANEG_CFG_RF1            0x00000010
3316 #define ANEG_CFG_PS2            0x00000001
3317 #define ANEG_CFG_PS1            0x00008000
3318 #define ANEG_CFG_HD             0x00004000
3319 #define ANEG_CFG_FD             0x00002000
3320 #define ANEG_CFG_INVAL          0x00001f06
3321
3322 };
3323 #define ANEG_OK         0
3324 #define ANEG_DONE       1
3325 #define ANEG_TIMER_ENAB 2
3326 #define ANEG_FAILED     -1
3327
3328 #define ANEG_STATE_SETTLE_TIME  10000
3329
3330 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3331                                    struct tg3_fiber_aneginfo *ap)
3332 {
3333         u16 flowctrl;
3334         unsigned long delta;
3335         u32 rx_cfg_reg;
3336         int ret;
3337
3338         if (ap->state == ANEG_STATE_UNKNOWN) {
3339                 ap->rxconfig = 0;
3340                 ap->link_time = 0;
3341                 ap->cur_time = 0;
3342                 ap->ability_match_cfg = 0;
3343                 ap->ability_match_count = 0;
3344                 ap->ability_match = 0;
3345                 ap->idle_match = 0;
3346                 ap->ack_match = 0;
3347         }
3348         ap->cur_time++;
3349
3350         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3351                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3352
3353                 if (rx_cfg_reg != ap->ability_match_cfg) {
3354                         ap->ability_match_cfg = rx_cfg_reg;
3355                         ap->ability_match = 0;
3356                         ap->ability_match_count = 0;
3357                 } else {
3358                         if (++ap->ability_match_count > 1) {
3359                                 ap->ability_match = 1;
3360                                 ap->ability_match_cfg = rx_cfg_reg;
3361                         }
3362                 }
3363                 if (rx_cfg_reg & ANEG_CFG_ACK)
3364                         ap->ack_match = 1;
3365                 else
3366                         ap->ack_match = 0;
3367
3368                 ap->idle_match = 0;
3369         } else {
3370                 ap->idle_match = 1;
3371                 ap->ability_match_cfg = 0;
3372                 ap->ability_match_count = 0;
3373                 ap->ability_match = 0;
3374                 ap->ack_match = 0;
3375
3376                 rx_cfg_reg = 0;
3377         }
3378
3379         ap->rxconfig = rx_cfg_reg;
3380         ret = ANEG_OK;
3381
3382         switch(ap->state) {
3383         case ANEG_STATE_UNKNOWN:
3384                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3385                         ap->state = ANEG_STATE_AN_ENABLE;
3386
3387                 /* fallthru */
3388         case ANEG_STATE_AN_ENABLE:
3389                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3390                 if (ap->flags & MR_AN_ENABLE) {
3391                         ap->link_time = 0;
3392                         ap->cur_time = 0;
3393                         ap->ability_match_cfg = 0;
3394                         ap->ability_match_count = 0;
3395                         ap->ability_match = 0;
3396                         ap->idle_match = 0;
3397                         ap->ack_match = 0;
3398
3399                         ap->state = ANEG_STATE_RESTART_INIT;
3400                 } else {
3401                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3402                 }
3403                 break;
3404
3405         case ANEG_STATE_RESTART_INIT:
3406                 ap->link_time = ap->cur_time;
3407                 ap->flags &= ~(MR_NP_LOADED);
3408                 ap->txconfig = 0;
3409                 tw32(MAC_TX_AUTO_NEG, 0);
3410                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3411                 tw32_f(MAC_MODE, tp->mac_mode);
3412                 udelay(40);
3413
3414                 ret = ANEG_TIMER_ENAB;
3415                 ap->state = ANEG_STATE_RESTART;
3416
3417                 /* fallthru */
3418         case ANEG_STATE_RESTART:
3419                 delta = ap->cur_time - ap->link_time;
3420                 if (delta > ANEG_STATE_SETTLE_TIME) {
3421                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3422                 } else {
3423                         ret = ANEG_TIMER_ENAB;
3424                 }
3425                 break;
3426
3427         case ANEG_STATE_DISABLE_LINK_OK:
3428                 ret = ANEG_DONE;
3429                 break;
3430
3431         case ANEG_STATE_ABILITY_DETECT_INIT:
3432                 ap->flags &= ~(MR_TOGGLE_TX);
3433                 ap->txconfig = ANEG_CFG_FD;
3434                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3435                 if (flowctrl & ADVERTISE_1000XPAUSE)
3436                         ap->txconfig |= ANEG_CFG_PS1;
3437                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3438                         ap->txconfig |= ANEG_CFG_PS2;
3439                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3440                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3441                 tw32_f(MAC_MODE, tp->mac_mode);
3442                 udelay(40);
3443
3444                 ap->state = ANEG_STATE_ABILITY_DETECT;
3445                 break;
3446
3447         case ANEG_STATE_ABILITY_DETECT:
3448                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3449                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3450                 }
3451                 break;
3452
3453         case ANEG_STATE_ACK_DETECT_INIT:
3454                 ap->txconfig |= ANEG_CFG_ACK;
3455                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3456                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3457                 tw32_f(MAC_MODE, tp->mac_mode);
3458                 udelay(40);
3459
3460                 ap->state = ANEG_STATE_ACK_DETECT;
3461
3462                 /* fallthru */
3463         case ANEG_STATE_ACK_DETECT:
3464                 if (ap->ack_match != 0) {
3465                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3466                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3467                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3468                         } else {
3469                                 ap->state = ANEG_STATE_AN_ENABLE;
3470                         }
3471                 } else if (ap->ability_match != 0 &&
3472                            ap->rxconfig == 0) {
3473                         ap->state = ANEG_STATE_AN_ENABLE;
3474                 }
3475                 break;
3476
3477         case ANEG_STATE_COMPLETE_ACK_INIT:
3478                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3479                         ret = ANEG_FAILED;
3480                         break;
3481                 }
3482                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3483                                MR_LP_ADV_HALF_DUPLEX |
3484                                MR_LP_ADV_SYM_PAUSE |
3485                                MR_LP_ADV_ASYM_PAUSE |
3486                                MR_LP_ADV_REMOTE_FAULT1 |
3487                                MR_LP_ADV_REMOTE_FAULT2 |
3488                                MR_LP_ADV_NEXT_PAGE |
3489                                MR_TOGGLE_RX |
3490                                MR_NP_RX);
3491                 if (ap->rxconfig & ANEG_CFG_FD)
3492                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3493                 if (ap->rxconfig & ANEG_CFG_HD)
3494                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3495                 if (ap->rxconfig & ANEG_CFG_PS1)
3496                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3497                 if (ap->rxconfig & ANEG_CFG_PS2)
3498                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3499                 if (ap->rxconfig & ANEG_CFG_RF1)
3500                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3501                 if (ap->rxconfig & ANEG_CFG_RF2)
3502                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3503                 if (ap->rxconfig & ANEG_CFG_NP)
3504                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3505
3506                 ap->link_time = ap->cur_time;
3507
3508                 ap->flags ^= (MR_TOGGLE_TX);
3509                 if (ap->rxconfig & 0x0008)
3510                         ap->flags |= MR_TOGGLE_RX;
3511                 if (ap->rxconfig & ANEG_CFG_NP)
3512                         ap->flags |= MR_NP_RX;
3513                 ap->flags |= MR_PAGE_RX;
3514
3515                 ap->state = ANEG_STATE_COMPLETE_ACK;
3516                 ret = ANEG_TIMER_ENAB;
3517                 break;
3518
3519         case ANEG_STATE_COMPLETE_ACK:
3520                 if (ap->ability_match != 0 &&
3521                     ap->rxconfig == 0) {
3522                         ap->state = ANEG_STATE_AN_ENABLE;
3523                         break;
3524                 }
3525                 delta = ap->cur_time - ap->link_time;
3526                 if (delta > ANEG_STATE_SETTLE_TIME) {
3527                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3528                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3529                         } else {
3530                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3531                                     !(ap->flags & MR_NP_RX)) {
3532                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3533                                 } else {
3534                                         ret = ANEG_FAILED;
3535                                 }
3536                         }
3537                 }
3538                 break;
3539
3540         case ANEG_STATE_IDLE_DETECT_INIT:
3541                 ap->link_time = ap->cur_time;
3542                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3543                 tw32_f(MAC_MODE, tp->mac_mode);
3544                 udelay(40);
3545
3546                 ap->state = ANEG_STATE_IDLE_DETECT;
3547                 ret = ANEG_TIMER_ENAB;
3548                 break;
3549
3550         case ANEG_STATE_IDLE_DETECT:
3551                 if (ap->ability_match != 0 &&
3552                     ap->rxconfig == 0) {
3553                         ap->state = ANEG_STATE_AN_ENABLE;
3554                         break;
3555                 }
3556                 delta = ap->cur_time - ap->link_time;
3557                 if (delta > ANEG_STATE_SETTLE_TIME) {
3558                         /* XXX another gem from the Broadcom driver :( */
3559                         ap->state = ANEG_STATE_LINK_OK;
3560                 }
3561                 break;
3562
3563         case ANEG_STATE_LINK_OK:
3564                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3565                 ret = ANEG_DONE;
3566                 break;
3567
3568         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3569                 /* ??? unimplemented */
3570                 break;
3571
3572         case ANEG_STATE_NEXT_PAGE_WAIT:
3573                 /* ??? unimplemented */
3574                 break;
3575
3576         default:
3577                 ret = ANEG_FAILED;
3578                 break;
3579         }
3580
3581         return ret;
3582 }
3583
3584 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3585 {
3586         int res = 0;
3587         struct tg3_fiber_aneginfo aninfo;
3588         int status = ANEG_FAILED;
3589         unsigned int tick;
3590         u32 tmp;
3591
3592         tw32_f(MAC_TX_AUTO_NEG, 0);
3593
3594         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3595         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3596         udelay(40);
3597
3598         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3599         udelay(40);
3600
3601         memset(&aninfo, 0, sizeof(aninfo));
3602         aninfo.flags |= MR_AN_ENABLE;
3603         aninfo.state = ANEG_STATE_UNKNOWN;
3604         aninfo.cur_time = 0;
3605         tick = 0;
3606         while (++tick < 195000) {
3607                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3608                 if (status == ANEG_DONE || status == ANEG_FAILED)
3609                         break;
3610
3611                 udelay(1);
3612         }
3613
3614         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3615         tw32_f(MAC_MODE, tp->mac_mode);
3616         udelay(40);
3617
3618         *txflags = aninfo.txconfig;
3619         *rxflags = aninfo.flags;
3620
3621         if (status == ANEG_DONE &&
3622             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3623                              MR_LP_ADV_FULL_DUPLEX)))
3624                 res = 1;
3625
3626         return res;
3627 }
3628
3629 static void tg3_init_bcm8002(struct tg3 *tp)
3630 {
3631         u32 mac_status = tr32(MAC_STATUS);
3632         int i;
3633
3634         /* Reset when initting first time or we have a link. */
3635         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3636             !(mac_status & MAC_STATUS_PCS_SYNCED))
3637                 return;
3638
3639         /* Set PLL lock range. */
3640         tg3_writephy(tp, 0x16, 0x8007);
3641
3642         /* SW reset */
3643         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3644
3645         /* Wait for reset to complete. */
3646         /* XXX schedule_timeout() ... */
3647         for (i = 0; i < 500; i++)
3648                 udelay(10);
3649
3650         /* Config mode; select PMA/Ch 1 regs. */
3651         tg3_writephy(tp, 0x10, 0x8411);
3652
3653         /* Enable auto-lock and comdet, select txclk for tx. */
3654         tg3_writephy(tp, 0x11, 0x0a10);
3655
3656         tg3_writephy(tp, 0x18, 0x00a0);
3657         tg3_writephy(tp, 0x16, 0x41ff);
3658
3659         /* Assert and deassert POR. */
3660         tg3_writephy(tp, 0x13, 0x0400);
3661         udelay(40);
3662         tg3_writephy(tp, 0x13, 0x0000);
3663
3664         tg3_writephy(tp, 0x11, 0x0a50);
3665         udelay(40);
3666         tg3_writephy(tp, 0x11, 0x0a10);
3667
3668         /* Wait for signal to stabilize */
3669         /* XXX schedule_timeout() ... */
3670         for (i = 0; i < 15000; i++)
3671                 udelay(10);
3672
3673         /* Deselect the channel register so we can read the PHYID
3674          * later.
3675          */
3676         tg3_writephy(tp, 0x10, 0x8011);
3677 }
3678
3679 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3680 {
3681         u16 flowctrl;
3682         u32 sg_dig_ctrl, sg_dig_status;
3683         u32 serdes_cfg, expected_sg_dig_ctrl;
3684         int workaround, port_a;
3685         int current_link_up;
3686
3687         serdes_cfg = 0;
3688         expected_sg_dig_ctrl = 0;
3689         workaround = 0;
3690         port_a = 1;
3691         current_link_up = 0;
3692
3693         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3694             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3695                 workaround = 1;
3696                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3697                         port_a = 0;
3698
3699                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3700                 /* preserve bits 20-23 for voltage regulator */
3701                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3702         }
3703
3704         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3705
3706         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3707                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3708                         if (workaround) {
3709                                 u32 val = serdes_cfg;
3710
3711                                 if (port_a)
3712                                         val |= 0xc010000;
3713                                 else
3714                                         val |= 0x4010000;
3715                                 tw32_f(MAC_SERDES_CFG, val);
3716                         }
3717
3718                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3719                 }
3720                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3721                         tg3_setup_flow_control(tp, 0, 0);
3722                         current_link_up = 1;
3723                 }
3724                 goto out;
3725         }
3726
3727         /* Want auto-negotiation.  */
3728         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3729
3730         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3731         if (flowctrl & ADVERTISE_1000XPAUSE)
3732                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3733         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3734                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3735
3736         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3737                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3738                     tp->serdes_counter &&
3739                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3740                                     MAC_STATUS_RCVD_CFG)) ==
3741                      MAC_STATUS_PCS_SYNCED)) {
3742                         tp->serdes_counter--;
3743                         current_link_up = 1;
3744                         goto out;
3745                 }
3746 restart_autoneg:
3747                 if (workaround)
3748                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3749                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3750                 udelay(5);
3751                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3752
3753                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3754                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3755         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3756                                  MAC_STATUS_SIGNAL_DET)) {
3757                 sg_dig_status = tr32(SG_DIG_STATUS);
3758                 mac_status = tr32(MAC_STATUS);
3759
3760                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3761                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3762                         u32 local_adv = 0, remote_adv = 0;
3763
3764                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3765                                 local_adv |= ADVERTISE_1000XPAUSE;
3766                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3767                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3768
3769                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3770                                 remote_adv |= LPA_1000XPAUSE;
3771                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3772                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3773
3774                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3775                         current_link_up = 1;
3776                         tp->serdes_counter = 0;
3777                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3778                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3779                         if (tp->serdes_counter)
3780                                 tp->serdes_counter--;
3781                         else {
3782                                 if (workaround) {
3783                                         u32 val = serdes_cfg;
3784
3785                                         if (port_a)
3786                                                 val |= 0xc010000;
3787                                         else
3788                                                 val |= 0x4010000;
3789
3790                                         tw32_f(MAC_SERDES_CFG, val);
3791                                 }
3792
3793                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3794                                 udelay(40);
3795
3796                                 /* Link parallel detection - link is up */
3797                                 /* only if we have PCS_SYNC and not */
3798                                 /* receiving config code words */
3799                                 mac_status = tr32(MAC_STATUS);
3800                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3801                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3802                                         tg3_setup_flow_control(tp, 0, 0);
3803                                         current_link_up = 1;
3804                                         tp->tg3_flags2 |=
3805                                                 TG3_FLG2_PARALLEL_DETECT;
3806                                         tp->serdes_counter =
3807                                                 SERDES_PARALLEL_DET_TIMEOUT;
3808                                 } else
3809                                         goto restart_autoneg;
3810                         }
3811                 }
3812         } else {
3813                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3814                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3815         }
3816
3817 out:
3818         return current_link_up;
3819 }
3820
3821 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3822 {
3823         int current_link_up = 0;
3824
3825         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3826                 goto out;
3827
3828         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3829                 u32 txflags, rxflags;
3830                 int i;
3831
3832                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3833                         u32 local_adv = 0, remote_adv = 0;
3834
3835                         if (txflags & ANEG_CFG_PS1)
3836                                 local_adv |= ADVERTISE_1000XPAUSE;
3837                         if (txflags & ANEG_CFG_PS2)
3838                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3839
3840                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3841                                 remote_adv |= LPA_1000XPAUSE;
3842                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3843                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3844
3845                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3846
3847                         current_link_up = 1;
3848                 }
3849                 for (i = 0; i < 30; i++) {
3850                         udelay(20);
3851                         tw32_f(MAC_STATUS,
3852                                (MAC_STATUS_SYNC_CHANGED |
3853                                 MAC_STATUS_CFG_CHANGED));
3854                         udelay(40);
3855                         if ((tr32(MAC_STATUS) &
3856                              (MAC_STATUS_SYNC_CHANGED |
3857                               MAC_STATUS_CFG_CHANGED)) == 0)
3858                                 break;
3859                 }
3860
3861                 mac_status = tr32(MAC_STATUS);
3862                 if (current_link_up == 0 &&
3863                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3864                     !(mac_status & MAC_STATUS_RCVD_CFG))
3865                         current_link_up = 1;
3866         } else {
3867                 tg3_setup_flow_control(tp, 0, 0);
3868
3869                 /* Forcing 1000FD link up. */
3870                 current_link_up = 1;
3871
3872                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3873                 udelay(40);
3874
3875                 tw32_f(MAC_MODE, tp->mac_mode);
3876                 udelay(40);
3877         }
3878
3879 out:
3880         return current_link_up;
3881 }
3882
3883 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3884 {
3885         u32 orig_pause_cfg;
3886         u16 orig_active_speed;
3887         u8 orig_active_duplex;
3888         u32 mac_status;
3889         int current_link_up;
3890         int i;
3891
3892         orig_pause_cfg = tp->link_config.active_flowctrl;
3893         orig_active_speed = tp->link_config.active_speed;
3894         orig_active_duplex = tp->link_config.active_duplex;
3895
3896         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3897             netif_carrier_ok(tp->dev) &&
3898             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3899                 mac_status = tr32(MAC_STATUS);
3900                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3901                                MAC_STATUS_SIGNAL_DET |
3902                                MAC_STATUS_CFG_CHANGED |
3903                                MAC_STATUS_RCVD_CFG);
3904                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3905                                    MAC_STATUS_SIGNAL_DET)) {
3906                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3907                                             MAC_STATUS_CFG_CHANGED));
3908                         return 0;
3909                 }
3910         }
3911
3912         tw32_f(MAC_TX_AUTO_NEG, 0);
3913
3914         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3915         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3916         tw32_f(MAC_MODE, tp->mac_mode);
3917         udelay(40);
3918
3919         if (tp->phy_id == PHY_ID_BCM8002)
3920                 tg3_init_bcm8002(tp);
3921
3922         /* Enable link change event even when serdes polling.  */
3923         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3924         udelay(40);
3925
3926         current_link_up = 0;
3927         mac_status = tr32(MAC_STATUS);
3928
3929         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3930                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3931         else
3932                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3933
3934         tp->napi[0].hw_status->status =
3935                 (SD_STATUS_UPDATED |
3936                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3937
3938         for (i = 0; i < 100; i++) {
3939                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3940                                     MAC_STATUS_CFG_CHANGED));
3941                 udelay(5);
3942                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3943                                          MAC_STATUS_CFG_CHANGED |
3944                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3945                         break;
3946         }
3947
3948         mac_status = tr32(MAC_STATUS);
3949         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3950                 current_link_up = 0;
3951                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3952                     tp->serdes_counter == 0) {
3953                         tw32_f(MAC_MODE, (tp->mac_mode |
3954                                           MAC_MODE_SEND_CONFIGS));
3955                         udelay(1);
3956                         tw32_f(MAC_MODE, tp->mac_mode);
3957                 }
3958         }
3959
3960         if (current_link_up == 1) {
3961                 tp->link_config.active_speed = SPEED_1000;
3962                 tp->link_config.active_duplex = DUPLEX_FULL;
3963                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3964                                     LED_CTRL_LNKLED_OVERRIDE |
3965                                     LED_CTRL_1000MBPS_ON));
3966         } else {
3967                 tp->link_config.active_speed = SPEED_INVALID;
3968                 tp->link_config.active_duplex = DUPLEX_INVALID;
3969                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3970                                     LED_CTRL_LNKLED_OVERRIDE |
3971                                     LED_CTRL_TRAFFIC_OVERRIDE));
3972         }
3973
3974         if (current_link_up != netif_carrier_ok(tp->dev)) {
3975                 if (current_link_up)
3976                         netif_carrier_on(tp->dev);
3977                 else
3978                         netif_carrier_off(tp->dev);
3979                 tg3_link_report(tp);
3980         } else {
3981                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3982                 if (orig_pause_cfg != now_pause_cfg ||
3983                     orig_active_speed != tp->link_config.active_speed ||
3984                     orig_active_duplex != tp->link_config.active_duplex)
3985                         tg3_link_report(tp);
3986         }
3987
3988         return 0;
3989 }
3990
3991 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3992 {
3993         int current_link_up, err = 0;
3994         u32 bmsr, bmcr;
3995         u16 current_speed;
3996         u8 current_duplex;
3997         u32 local_adv, remote_adv;
3998
3999         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4000         tw32_f(MAC_MODE, tp->mac_mode);
4001         udelay(40);
4002
4003         tw32(MAC_EVENT, 0);
4004
4005         tw32_f(MAC_STATUS,
4006              (MAC_STATUS_SYNC_CHANGED |
4007               MAC_STATUS_CFG_CHANGED |
4008               MAC_STATUS_MI_COMPLETION |
4009               MAC_STATUS_LNKSTATE_CHANGED));
4010         udelay(40);
4011
4012         if (force_reset)
4013                 tg3_phy_reset(tp);
4014
4015         current_link_up = 0;
4016         current_speed = SPEED_INVALID;
4017         current_duplex = DUPLEX_INVALID;
4018
4019         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4020         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4022                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4023                         bmsr |= BMSR_LSTATUS;
4024                 else
4025                         bmsr &= ~BMSR_LSTATUS;
4026         }
4027
4028         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4029
4030         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4031             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4032                 /* do nothing, just check for link up at the end */
4033         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4034                 u32 adv, new_adv;
4035
4036                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4037                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4038                                   ADVERTISE_1000XPAUSE |
4039                                   ADVERTISE_1000XPSE_ASYM |
4040                                   ADVERTISE_SLCT);
4041
4042                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4043
4044                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4045                         new_adv |= ADVERTISE_1000XHALF;
4046                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4047                         new_adv |= ADVERTISE_1000XFULL;
4048
4049                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4050                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4051                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4052                         tg3_writephy(tp, MII_BMCR, bmcr);
4053
4054                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4055                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4056                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4057
4058                         return err;
4059                 }
4060         } else {
4061                 u32 new_bmcr;
4062
4063                 bmcr &= ~BMCR_SPEED1000;
4064                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4065
4066                 if (tp->link_config.duplex == DUPLEX_FULL)
4067                         new_bmcr |= BMCR_FULLDPLX;
4068
4069                 if (new_bmcr != bmcr) {
4070                         /* BMCR_SPEED1000 is a reserved bit that needs
4071                          * to be set on write.
4072                          */
4073                         new_bmcr |= BMCR_SPEED1000;
4074
4075                         /* Force a linkdown */
4076                         if (netif_carrier_ok(tp->dev)) {
4077                                 u32 adv;
4078
4079                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4080                                 adv &= ~(ADVERTISE_1000XFULL |
4081                                          ADVERTISE_1000XHALF |
4082                                          ADVERTISE_SLCT);
4083                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4084                                 tg3_writephy(tp, MII_BMCR, bmcr |
4085                                                            BMCR_ANRESTART |
4086                                                            BMCR_ANENABLE);
4087                                 udelay(10);
4088                                 netif_carrier_off(tp->dev);
4089                         }
4090                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4091                         bmcr = new_bmcr;
4092                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4093                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4094                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4095                             ASIC_REV_5714) {
4096                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4097                                         bmsr |= BMSR_LSTATUS;
4098                                 else
4099                                         bmsr &= ~BMSR_LSTATUS;
4100                         }
4101                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4102                 }
4103         }
4104
4105         if (bmsr & BMSR_LSTATUS) {
4106                 current_speed = SPEED_1000;
4107                 current_link_up = 1;
4108                 if (bmcr & BMCR_FULLDPLX)
4109                         current_duplex = DUPLEX_FULL;
4110                 else
4111                         current_duplex = DUPLEX_HALF;
4112
4113                 local_adv = 0;
4114                 remote_adv = 0;
4115
4116                 if (bmcr & BMCR_ANENABLE) {
4117                         u32 common;
4118
4119                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4120                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4121                         common = local_adv & remote_adv;
4122                         if (common & (ADVERTISE_1000XHALF |
4123                                       ADVERTISE_1000XFULL)) {
4124                                 if (common & ADVERTISE_1000XFULL)
4125                                         current_duplex = DUPLEX_FULL;
4126                                 else
4127                                         current_duplex = DUPLEX_HALF;
4128                         }
4129                         else
4130                                 current_link_up = 0;
4131                 }
4132         }
4133
4134         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4135                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4136
4137         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4138         if (tp->link_config.active_duplex == DUPLEX_HALF)
4139                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4140
4141         tw32_f(MAC_MODE, tp->mac_mode);
4142         udelay(40);
4143
4144         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4145
4146         tp->link_config.active_speed = current_speed;
4147         tp->link_config.active_duplex = current_duplex;
4148
4149         if (current_link_up != netif_carrier_ok(tp->dev)) {
4150                 if (current_link_up)
4151                         netif_carrier_on(tp->dev);
4152                 else {
4153                         netif_carrier_off(tp->dev);
4154                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4155                 }
4156                 tg3_link_report(tp);
4157         }
4158         return err;
4159 }
4160
4161 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4162 {
4163         if (tp->serdes_counter) {
4164                 /* Give autoneg time to complete. */
4165                 tp->serdes_counter--;
4166                 return;
4167         }
4168         if (!netif_carrier_ok(tp->dev) &&
4169             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4170                 u32 bmcr;
4171
4172                 tg3_readphy(tp, MII_BMCR, &bmcr);
4173                 if (bmcr & BMCR_ANENABLE) {
4174                         u32 phy1, phy2;
4175
4176                         /* Select shadow register 0x1f */
4177                         tg3_writephy(tp, 0x1c, 0x7c00);
4178                         tg3_readphy(tp, 0x1c, &phy1);
4179
4180                         /* Select expansion interrupt status register */
4181                         tg3_writephy(tp, 0x17, 0x0f01);
4182                         tg3_readphy(tp, 0x15, &phy2);
4183                         tg3_readphy(tp, 0x15, &phy2);
4184
4185                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4186                                 /* We have signal detect and not receiving
4187                                  * config code words, link is up by parallel
4188                                  * detection.
4189                                  */
4190
4191                                 bmcr &= ~BMCR_ANENABLE;
4192                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4193                                 tg3_writephy(tp, MII_BMCR, bmcr);
4194                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4195                         }
4196                 }
4197         }
4198         else if (netif_carrier_ok(tp->dev) &&
4199                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4200                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4201                 u32 phy2;
4202
4203                 /* Select expansion interrupt status register */
4204                 tg3_writephy(tp, 0x17, 0x0f01);
4205                 tg3_readphy(tp, 0x15, &phy2);
4206                 if (phy2 & 0x20) {
4207                         u32 bmcr;
4208
4209                         /* Config code words received, turn on autoneg. */
4210                         tg3_readphy(tp, MII_BMCR, &bmcr);
4211                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4212
4213                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4214
4215                 }
4216         }
4217 }
4218
4219 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4220 {
4221         int err;
4222
4223         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4224                 err = tg3_setup_fiber_phy(tp, force_reset);
4225         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4226                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4227         } else {
4228                 err = tg3_setup_copper_phy(tp, force_reset);
4229         }
4230
4231         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4232                 u32 val, scale;
4233
4234                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4235                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4236                         scale = 65;
4237                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4238                         scale = 6;
4239                 else
4240                         scale = 12;
4241
4242                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4243                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4244                 tw32(GRC_MISC_CFG, val);
4245         }
4246
4247         if (tp->link_config.active_speed == SPEED_1000 &&
4248             tp->link_config.active_duplex == DUPLEX_HALF)
4249                 tw32(MAC_TX_LENGTHS,
4250                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4251                       (6 << TX_LENGTHS_IPG_SHIFT) |
4252                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4253         else
4254                 tw32(MAC_TX_LENGTHS,
4255                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4256                       (6 << TX_LENGTHS_IPG_SHIFT) |
4257                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4258
4259         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4260                 if (netif_carrier_ok(tp->dev)) {
4261                         tw32(HOSTCC_STAT_COAL_TICKS,
4262                              tp->coal.stats_block_coalesce_usecs);
4263                 } else {
4264                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4265                 }
4266         }
4267
4268         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4269                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4270                 if (!netif_carrier_ok(tp->dev))
4271                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4272                               tp->pwrmgmt_thresh;
4273                 else
4274                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4275                 tw32(PCIE_PWR_MGMT_THRESH, val);
4276         }
4277
4278         return err;
4279 }
4280
4281 /* This is called whenever we suspect that the system chipset is re-
4282  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4283  * is bogus tx completions. We try to recover by setting the
4284  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4285  * in the workqueue.
4286  */
4287 static void tg3_tx_recover(struct tg3 *tp)
4288 {
4289         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4290                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4291
4292         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4293                "mapped I/O cycles to the network device, attempting to "
4294                "recover. Please report the problem to the driver maintainer "
4295                "and include system chipset information.\n", tp->dev->name);
4296
4297         spin_lock(&tp->lock);
4298         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4299         spin_unlock(&tp->lock);
4300 }
4301
4302 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4303 {
4304         smp_mb();
4305         return tnapi->tx_pending -
4306                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4307 }
4308
4309 /* Tigon3 never reports partial packet sends.  So we do not
4310  * need special logic to handle SKBs that have not had all
4311  * of their frags sent yet, like SunGEM does.
4312  */
4313 static void tg3_tx(struct tg3_napi *tnapi)
4314 {
4315         struct tg3 *tp = tnapi->tp;
4316         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4317         u32 sw_idx = tnapi->tx_cons;
4318         struct netdev_queue *txq;
4319         int index = tnapi - tp->napi;
4320
4321         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4322                 index--;
4323
4324         txq = netdev_get_tx_queue(tp->dev, index);
4325
4326         while (sw_idx != hw_idx) {
4327                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4328                 struct sk_buff *skb = ri->skb;
4329                 int i, tx_bug = 0;
4330
4331                 if (unlikely(skb == NULL)) {
4332                         tg3_tx_recover(tp);
4333                         return;
4334                 }
4335
4336                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4337
4338                 ri->skb = NULL;
4339
4340                 sw_idx = NEXT_TX(sw_idx);
4341
4342                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4343                         ri = &tnapi->tx_buffers[sw_idx];
4344                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4345                                 tx_bug = 1;
4346                         sw_idx = NEXT_TX(sw_idx);
4347                 }
4348
4349                 dev_kfree_skb(skb);
4350
4351                 if (unlikely(tx_bug)) {
4352                         tg3_tx_recover(tp);
4353                         return;
4354                 }
4355         }
4356
4357         tnapi->tx_cons = sw_idx;
4358
4359         /* Need to make the tx_cons update visible to tg3_start_xmit()
4360          * before checking for netif_queue_stopped().  Without the
4361          * memory barrier, there is a small possibility that tg3_start_xmit()
4362          * will miss it and cause the queue to be stopped forever.
4363          */
4364         smp_mb();
4365
4366         if (unlikely(netif_tx_queue_stopped(txq) &&
4367                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4368                 __netif_tx_lock(txq, smp_processor_id());
4369                 if (netif_tx_queue_stopped(txq) &&
4370                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4371                         netif_tx_wake_queue(txq);
4372                 __netif_tx_unlock(txq);
4373         }
4374 }
4375
4376 /* Returns size of skb allocated or < 0 on error.
4377  *
4378  * We only need to fill in the address because the other members
4379  * of the RX descriptor are invariant, see tg3_init_rings.
4380  *
4381  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4382  * posting buffers we only dirty the first cache line of the RX
4383  * descriptor (containing the address).  Whereas for the RX status
4384  * buffers the cpu only reads the last cacheline of the RX descriptor
4385  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4386  */
4387 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4388                             int src_idx, u32 dest_idx_unmasked)
4389 {
4390         struct tg3 *tp = tnapi->tp;
4391         struct tg3_rx_buffer_desc *desc;
4392         struct ring_info *map, *src_map;
4393         struct sk_buff *skb;
4394         dma_addr_t mapping;
4395         int skb_size, dest_idx;
4396         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4397
4398         src_map = NULL;
4399         switch (opaque_key) {
4400         case RXD_OPAQUE_RING_STD:
4401                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4402                 desc = &tpr->rx_std[dest_idx];
4403                 map = &tpr->rx_std_buffers[dest_idx];
4404                 if (src_idx >= 0)
4405                         src_map = &tpr->rx_std_buffers[src_idx];
4406                 skb_size = tp->rx_pkt_map_sz;
4407                 break;
4408
4409         case RXD_OPAQUE_RING_JUMBO:
4410                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4411                 desc = &tpr->rx_jmb[dest_idx].std;
4412                 map = &tpr->rx_jmb_buffers[dest_idx];
4413                 if (src_idx >= 0)
4414                         src_map = &tpr->rx_jmb_buffers[src_idx];
4415                 skb_size = TG3_RX_JMB_MAP_SZ;
4416                 break;
4417
4418         default:
4419                 return -EINVAL;
4420         }
4421
4422         /* Do not overwrite any of the map or rp information
4423          * until we are sure we can commit to a new buffer.
4424          *
4425          * Callers depend upon this behavior and assume that
4426          * we leave everything unchanged if we fail.
4427          */
4428         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4429         if (skb == NULL)
4430                 return -ENOMEM;
4431
4432         skb_reserve(skb, tp->rx_offset);
4433
4434         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4435                                  PCI_DMA_FROMDEVICE);
4436
4437         map->skb = skb;
4438         pci_unmap_addr_set(map, mapping, mapping);
4439
4440         if (src_map != NULL)
4441                 src_map->skb = NULL;
4442
4443         desc->addr_hi = ((u64)mapping >> 32);
4444         desc->addr_lo = ((u64)mapping & 0xffffffff);
4445
4446         return skb_size;
4447 }
4448
4449 /* We only need to move over in the address because the other
4450  * members of the RX descriptor are invariant.  See notes above
4451  * tg3_alloc_rx_skb for full details.
4452  */
4453 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4454                            int src_idx, u32 dest_idx_unmasked)
4455 {
4456         struct tg3 *tp = tnapi->tp;
4457         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4458         struct ring_info *src_map, *dest_map;
4459         int dest_idx;
4460         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4461
4462         switch (opaque_key) {
4463         case RXD_OPAQUE_RING_STD:
4464                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4465                 dest_desc = &tpr->rx_std[dest_idx];
4466                 dest_map = &tpr->rx_std_buffers[dest_idx];
4467                 src_desc = &tpr->rx_std[src_idx];
4468                 src_map = &tpr->rx_std_buffers[src_idx];
4469                 break;
4470
4471         case RXD_OPAQUE_RING_JUMBO:
4472                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4473                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4474                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4475                 src_desc = &tpr->rx_jmb[src_idx].std;
4476                 src_map = &tpr->rx_jmb_buffers[src_idx];
4477                 break;
4478
4479         default:
4480                 return;
4481         }
4482
4483         dest_map->skb = src_map->skb;
4484         pci_unmap_addr_set(dest_map, mapping,
4485                            pci_unmap_addr(src_map, mapping));
4486         dest_desc->addr_hi = src_desc->addr_hi;
4487         dest_desc->addr_lo = src_desc->addr_lo;
4488
4489         src_map->skb = NULL;
4490 }
4491
4492 /* The RX ring scheme is composed of multiple rings which post fresh
4493  * buffers to the chip, and one special ring the chip uses to report
4494  * status back to the host.
4495  *
4496  * The special ring reports the status of received packets to the
4497  * host.  The chip does not write into the original descriptor the
4498  * RX buffer was obtained from.  The chip simply takes the original
4499  * descriptor as provided by the host, updates the status and length
4500  * field, then writes this into the next status ring entry.
4501  *
4502  * Each ring the host uses to post buffers to the chip is described
4503  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4504  * it is first placed into the on-chip ram.  When the packet's length
4505  * is known, it walks down the TG3_BDINFO entries to select the ring.
4506  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4507  * which is within the range of the new packet's length is chosen.
4508  *
4509  * The "separate ring for rx status" scheme may sound queer, but it makes
4510  * sense from a cache coherency perspective.  If only the host writes
4511  * to the buffer post rings, and only the chip writes to the rx status
4512  * rings, then cache lines never move beyond shared-modified state.
4513  * If both the host and chip were to write into the same ring, cache line
4514  * eviction could occur since both entities want it in an exclusive state.
4515  */
4516 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4517 {
4518         struct tg3 *tp = tnapi->tp;
4519         u32 work_mask, rx_std_posted = 0;
4520         u32 sw_idx = tnapi->rx_rcb_ptr;
4521         u16 hw_idx;
4522         int received;
4523         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4524
4525         hw_idx = *(tnapi->rx_rcb_prod_idx);
4526         /*
4527          * We need to order the read of hw_idx and the read of
4528          * the opaque cookie.
4529          */
4530         rmb();
4531         work_mask = 0;
4532         received = 0;
4533         while (sw_idx != hw_idx && budget > 0) {
4534                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4535                 unsigned int len;
4536                 struct sk_buff *skb;
4537                 dma_addr_t dma_addr;
4538                 u32 opaque_key, desc_idx, *post_ptr;
4539
4540                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4541                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4542                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4543                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4544                         dma_addr = pci_unmap_addr(ri, mapping);
4545                         skb = ri->skb;
4546                         post_ptr = &tpr->rx_std_ptr;
4547                         rx_std_posted++;
4548                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4549                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4550                         dma_addr = pci_unmap_addr(ri, mapping);
4551                         skb = ri->skb;
4552                         post_ptr = &tpr->rx_jmb_ptr;
4553                 } else
4554                         goto next_pkt_nopost;
4555
4556                 work_mask |= opaque_key;
4557
4558                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4559                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4560                 drop_it:
4561                         tg3_recycle_rx(tnapi, opaque_key,
4562                                        desc_idx, *post_ptr);
4563                 drop_it_no_recycle:
4564                         /* Other statistics kept track of by card. */
4565                         tp->net_stats.rx_dropped++;
4566                         goto next_pkt;
4567                 }
4568
4569                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4570                       ETH_FCS_LEN;
4571
4572                 if (len > RX_COPY_THRESHOLD
4573                         && tp->rx_offset == NET_IP_ALIGN
4574                         /* rx_offset will likely not equal NET_IP_ALIGN
4575                          * if this is a 5701 card running in PCI-X mode
4576                          * [see tg3_get_invariants()]
4577                          */
4578                 ) {
4579                         int skb_size;
4580
4581                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4582                                                     desc_idx, *post_ptr);
4583                         if (skb_size < 0)
4584                                 goto drop_it;
4585
4586                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4587                                          PCI_DMA_FROMDEVICE);
4588
4589                         skb_put(skb, len);
4590                 } else {
4591                         struct sk_buff *copy_skb;
4592
4593                         tg3_recycle_rx(tnapi, opaque_key,
4594                                        desc_idx, *post_ptr);
4595
4596                         copy_skb = netdev_alloc_skb(tp->dev,
4597                                                     len + TG3_RAW_IP_ALIGN);
4598                         if (copy_skb == NULL)
4599                                 goto drop_it_no_recycle;
4600
4601                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4602                         skb_put(copy_skb, len);
4603                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4604                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4605                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4606
4607                         /* We'll reuse the original ring buffer. */
4608                         skb = copy_skb;
4609                 }
4610
4611                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4612                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4613                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4614                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4615                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4616                 else
4617                         skb->ip_summed = CHECKSUM_NONE;
4618
4619                 skb->protocol = eth_type_trans(skb, tp->dev);
4620
4621                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4622                     skb->protocol != htons(ETH_P_8021Q)) {
4623                         dev_kfree_skb(skb);
4624                         goto next_pkt;
4625                 }
4626
4627 #if TG3_VLAN_TAG_USED
4628                 if (tp->vlgrp != NULL &&
4629                     desc->type_flags & RXD_FLAG_VLAN) {
4630                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4631                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4632                 } else
4633 #endif
4634                         napi_gro_receive(&tnapi->napi, skb);
4635
4636                 received++;
4637                 budget--;
4638
4639 next_pkt:
4640                 (*post_ptr)++;
4641
4642                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4643                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4644
4645                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4646                                      TG3_64BIT_REG_LOW, idx);
4647                         work_mask &= ~RXD_OPAQUE_RING_STD;
4648                         rx_std_posted = 0;
4649                 }
4650 next_pkt_nopost:
4651                 sw_idx++;
4652                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4653
4654                 /* Refresh hw_idx to see if there is new work */
4655                 if (sw_idx == hw_idx) {
4656                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4657                         rmb();
4658                 }
4659         }
4660
4661         /* ACK the status ring. */
4662         tnapi->rx_rcb_ptr = sw_idx;
4663         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4664
4665         /* Refill RX ring(s). */
4666         if (work_mask & RXD_OPAQUE_RING_STD) {
4667                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4668                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4669                              sw_idx);
4670         }
4671         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4672                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4673                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4674                              sw_idx);
4675         }
4676         mmiowb();
4677
4678         return received;
4679 }
4680
4681 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4682 {
4683         struct tg3 *tp = tnapi->tp;
4684         struct tg3_hw_status *sblk = tnapi->hw_status;
4685
4686         /* handle link change and other phy events */
4687         if (!(tp->tg3_flags &
4688               (TG3_FLAG_USE_LINKCHG_REG |
4689                TG3_FLAG_POLL_SERDES))) {
4690                 if (sblk->status & SD_STATUS_LINK_CHG) {
4691                         sblk->status = SD_STATUS_UPDATED |
4692                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4693                         spin_lock(&tp->lock);
4694                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4695                                 tw32_f(MAC_STATUS,
4696                                      (MAC_STATUS_SYNC_CHANGED |
4697                                       MAC_STATUS_CFG_CHANGED |
4698                                       MAC_STATUS_MI_COMPLETION |
4699                                       MAC_STATUS_LNKSTATE_CHANGED));
4700                                 udelay(40);
4701                         } else
4702                                 tg3_setup_phy(tp, 0);
4703                         spin_unlock(&tp->lock);
4704                 }
4705         }
4706
4707         /* run TX completion thread */
4708         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4709                 tg3_tx(tnapi);
4710                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4711                         return work_done;
4712         }
4713
4714         /* run RX thread, within the bounds set by NAPI.
4715          * All RX "locking" is done by ensuring outside
4716          * code synchronizes with tg3->napi.poll()
4717          */
4718         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4719                 work_done += tg3_rx(tnapi, budget - work_done);
4720
4721         return work_done;
4722 }
4723
4724 static int tg3_poll(struct napi_struct *napi, int budget)
4725 {
4726         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4727         struct tg3 *tp = tnapi->tp;
4728         int work_done = 0;
4729         struct tg3_hw_status *sblk = tnapi->hw_status;
4730
4731         while (1) {
4732                 work_done = tg3_poll_work(tnapi, work_done, budget);
4733
4734                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4735                         goto tx_recovery;
4736
4737                 if (unlikely(work_done >= budget))
4738                         break;
4739
4740                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4741                         /* tp->last_tag is used in tg3_int_reenable() below
4742                          * to tell the hw how much work has been processed,
4743                          * so we must read it before checking for more work.
4744                          */
4745                         tnapi->last_tag = sblk->status_tag;
4746                         tnapi->last_irq_tag = tnapi->last_tag;
4747                         rmb();
4748                 } else
4749                         sblk->status &= ~SD_STATUS_UPDATED;
4750
4751                 if (likely(!tg3_has_work(tnapi))) {
4752                         napi_complete(napi);
4753                         tg3_int_reenable(tnapi);
4754                         break;
4755                 }
4756         }
4757
4758         return work_done;
4759
4760 tx_recovery:
4761         /* work_done is guaranteed to be less than budget. */
4762         napi_complete(napi);
4763         schedule_work(&tp->reset_task);
4764         return work_done;
4765 }
4766
4767 static void tg3_irq_quiesce(struct tg3 *tp)
4768 {
4769         int i;
4770
4771         BUG_ON(tp->irq_sync);
4772
4773         tp->irq_sync = 1;
4774         smp_mb();
4775
4776         for (i = 0; i < tp->irq_cnt; i++)
4777                 synchronize_irq(tp->napi[i].irq_vec);
4778 }
4779
4780 static inline int tg3_irq_sync(struct tg3 *tp)
4781 {
4782         return tp->irq_sync;
4783 }
4784
4785 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4786  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4787  * with as well.  Most of the time, this is not necessary except when
4788  * shutting down the device.
4789  */
4790 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4791 {
4792         spin_lock_bh(&tp->lock);
4793         if (irq_sync)
4794                 tg3_irq_quiesce(tp);
4795 }
4796
4797 static inline void tg3_full_unlock(struct tg3 *tp)
4798 {
4799         spin_unlock_bh(&tp->lock);
4800 }
4801
4802 /* One-shot MSI handler - Chip automatically disables interrupt
4803  * after sending MSI so driver doesn't have to do it.
4804  */
4805 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4806 {
4807         struct tg3_napi *tnapi = dev_id;
4808         struct tg3 *tp = tnapi->tp;
4809
4810         prefetch(tnapi->hw_status);
4811         if (tnapi->rx_rcb)
4812                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4813
4814         if (likely(!tg3_irq_sync(tp)))
4815                 napi_schedule(&tnapi->napi);
4816
4817         return IRQ_HANDLED;
4818 }
4819
4820 /* MSI ISR - No need to check for interrupt sharing and no need to
4821  * flush status block and interrupt mailbox. PCI ordering rules
4822  * guarantee that MSI will arrive after the status block.
4823  */
4824 static irqreturn_t tg3_msi(int irq, void *dev_id)
4825 {
4826         struct tg3_napi *tnapi = dev_id;
4827         struct tg3 *tp = tnapi->tp;
4828
4829         prefetch(tnapi->hw_status);
4830         if (tnapi->rx_rcb)
4831                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4832         /*
4833          * Writing any value to intr-mbox-0 clears PCI INTA# and
4834          * chip-internal interrupt pending events.
4835          * Writing non-zero to intr-mbox-0 additional tells the
4836          * NIC to stop sending us irqs, engaging "in-intr-handler"
4837          * event coalescing.
4838          */
4839         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4840         if (likely(!tg3_irq_sync(tp)))
4841                 napi_schedule(&tnapi->napi);
4842
4843         return IRQ_RETVAL(1);
4844 }
4845
4846 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4847 {
4848         struct tg3_napi *tnapi = dev_id;
4849         struct tg3 *tp = tnapi->tp;
4850         struct tg3_hw_status *sblk = tnapi->hw_status;
4851         unsigned int handled = 1;
4852
4853         /* In INTx mode, it is possible for the interrupt to arrive at
4854          * the CPU before the status block posted prior to the interrupt.
4855          * Reading the PCI State register will confirm whether the
4856          * interrupt is ours and will flush the status block.
4857          */
4858         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4859                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4860                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4861                         handled = 0;
4862                         goto out;
4863                 }
4864         }
4865
4866         /*
4867          * Writing any value to intr-mbox-0 clears PCI INTA# and
4868          * chip-internal interrupt pending events.
4869          * Writing non-zero to intr-mbox-0 additional tells the
4870          * NIC to stop sending us irqs, engaging "in-intr-handler"
4871          * event coalescing.
4872          *
4873          * Flush the mailbox to de-assert the IRQ immediately to prevent
4874          * spurious interrupts.  The flush impacts performance but
4875          * excessive spurious interrupts can be worse in some cases.
4876          */
4877         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4878         if (tg3_irq_sync(tp))
4879                 goto out;
4880         sblk->status &= ~SD_STATUS_UPDATED;
4881         if (likely(tg3_has_work(tnapi))) {
4882                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4883                 napi_schedule(&tnapi->napi);
4884         } else {
4885                 /* No work, shared interrupt perhaps?  re-enable
4886                  * interrupts, and flush that PCI write
4887                  */
4888                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4889                                0x00000000);
4890         }
4891 out:
4892         return IRQ_RETVAL(handled);
4893 }
4894
4895 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4896 {
4897         struct tg3_napi *tnapi = dev_id;
4898         struct tg3 *tp = tnapi->tp;
4899         struct tg3_hw_status *sblk = tnapi->hw_status;
4900         unsigned int handled = 1;
4901
4902         /* In INTx mode, it is possible for the interrupt to arrive at
4903          * the CPU before the status block posted prior to the interrupt.
4904          * Reading the PCI State register will confirm whether the
4905          * interrupt is ours and will flush the status block.
4906          */
4907         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4908                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4909                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4910                         handled = 0;
4911                         goto out;
4912                 }
4913         }
4914
4915         /*
4916          * writing any value to intr-mbox-0 clears PCI INTA# and
4917          * chip-internal interrupt pending events.
4918          * writing non-zero to intr-mbox-0 additional tells the
4919          * NIC to stop sending us irqs, engaging "in-intr-handler"
4920          * event coalescing.
4921          *
4922          * Flush the mailbox to de-assert the IRQ immediately to prevent
4923          * spurious interrupts.  The flush impacts performance but
4924          * excessive spurious interrupts can be worse in some cases.
4925          */
4926         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4927
4928         /*
4929          * In a shared interrupt configuration, sometimes other devices'
4930          * interrupts will scream.  We record the current status tag here
4931          * so that the above check can report that the screaming interrupts
4932          * are unhandled.  Eventually they will be silenced.
4933          */
4934         tnapi->last_irq_tag = sblk->status_tag;
4935
4936         if (tg3_irq_sync(tp))
4937                 goto out;
4938
4939         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4940
4941         napi_schedule(&tnapi->napi);
4942
4943 out:
4944         return IRQ_RETVAL(handled);
4945 }
4946
4947 /* ISR for interrupt test */
4948 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4949 {
4950         struct tg3_napi *tnapi = dev_id;
4951         struct tg3 *tp = tnapi->tp;
4952         struct tg3_hw_status *sblk = tnapi->hw_status;
4953
4954         if ((sblk->status & SD_STATUS_UPDATED) ||
4955             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4956                 tg3_disable_ints(tp);
4957                 return IRQ_RETVAL(1);
4958         }
4959         return IRQ_RETVAL(0);
4960 }
4961
4962 static int tg3_init_hw(struct tg3 *, int);
4963 static int tg3_halt(struct tg3 *, int, int);
4964
4965 /* Restart hardware after configuration changes, self-test, etc.
4966  * Invoked with tp->lock held.
4967  */
4968 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4969         __releases(tp->lock)
4970         __acquires(tp->lock)
4971 {
4972         int err;
4973
4974         err = tg3_init_hw(tp, reset_phy);
4975         if (err) {
4976                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4977                        "aborting.\n", tp->dev->name);
4978                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4979                 tg3_full_unlock(tp);
4980                 del_timer_sync(&tp->timer);
4981                 tp->irq_sync = 0;
4982                 tg3_napi_enable(tp);
4983                 dev_close(tp->dev);
4984                 tg3_full_lock(tp, 0);
4985         }
4986         return err;
4987 }
4988
4989 #ifdef CONFIG_NET_POLL_CONTROLLER
4990 static void tg3_poll_controller(struct net_device *dev)
4991 {
4992         int i;
4993         struct tg3 *tp = netdev_priv(dev);
4994
4995         for (i = 0; i < tp->irq_cnt; i++)
4996                 tg3_interrupt(tp->napi[i].irq_vec, dev);
4997 }
4998 #endif
4999
5000 static void tg3_reset_task(struct work_struct *work)
5001 {
5002         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5003         int err;
5004         unsigned int restart_timer;
5005
5006         tg3_full_lock(tp, 0);
5007
5008         if (!netif_running(tp->dev)) {
5009                 tg3_full_unlock(tp);
5010                 return;
5011         }
5012
5013         tg3_full_unlock(tp);
5014
5015         tg3_phy_stop(tp);
5016
5017         tg3_netif_stop(tp);
5018
5019         tg3_full_lock(tp, 1);
5020
5021         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5022         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5023
5024         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5025                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5026                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5027                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5028                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5029         }
5030
5031         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5032         err = tg3_init_hw(tp, 1);
5033         if (err)
5034                 goto out;
5035
5036         tg3_netif_start(tp);
5037
5038         if (restart_timer)
5039                 mod_timer(&tp->timer, jiffies + 1);
5040
5041 out:
5042         tg3_full_unlock(tp);
5043
5044         if (!err)
5045                 tg3_phy_start(tp);
5046 }
5047
5048 static void tg3_dump_short_state(struct tg3 *tp)
5049 {
5050         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5051                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5052         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5053                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5054 }
5055
5056 static void tg3_tx_timeout(struct net_device *dev)
5057 {
5058         struct tg3 *tp = netdev_priv(dev);
5059
5060         if (netif_msg_tx_err(tp)) {
5061                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5062                        dev->name);
5063                 tg3_dump_short_state(tp);
5064         }
5065
5066         schedule_work(&tp->reset_task);
5067 }
5068
5069 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5070 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5071 {
5072         u32 base = (u32) mapping & 0xffffffff;
5073
5074         return ((base > 0xffffdcc0) &&
5075                 (base + len + 8 < base));
5076 }
5077
5078 /* Test for DMA addresses > 40-bit */
5079 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5080                                           int len)
5081 {
5082 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5083         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5084                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5085         return 0;
5086 #else
5087         return 0;
5088 #endif
5089 }
5090
5091 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5092
5093 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5094 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5095                                        u32 last_plus_one, u32 *start,
5096                                        u32 base_flags, u32 mss)
5097 {
5098         struct tg3_napi *tnapi = &tp->napi[0];
5099         struct sk_buff *new_skb;
5100         dma_addr_t new_addr = 0;
5101         u32 entry = *start;
5102         int i, ret = 0;
5103
5104         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5105                 new_skb = skb_copy(skb, GFP_ATOMIC);
5106         else {
5107                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5108
5109                 new_skb = skb_copy_expand(skb,
5110                                           skb_headroom(skb) + more_headroom,
5111                                           skb_tailroom(skb), GFP_ATOMIC);
5112         }
5113
5114         if (!new_skb) {
5115                 ret = -1;
5116         } else {
5117                 /* New SKB is guaranteed to be linear. */
5118                 entry = *start;
5119                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5120                 new_addr = skb_shinfo(new_skb)->dma_head;
5121
5122                 /* Make sure new skb does not cross any 4G boundaries.
5123                  * Drop the packet if it does.
5124                  */
5125                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5126                         if (!ret)
5127                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5128                                               DMA_TO_DEVICE);
5129                         ret = -1;
5130                         dev_kfree_skb(new_skb);
5131                         new_skb = NULL;
5132                 } else {
5133                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5134                                     base_flags, 1 | (mss << 1));
5135                         *start = NEXT_TX(entry);
5136                 }
5137         }
5138
5139         /* Now clean up the sw ring entries. */
5140         i = 0;
5141         while (entry != last_plus_one) {
5142                 if (i == 0)
5143                         tnapi->tx_buffers[entry].skb = new_skb;
5144                 else
5145                         tnapi->tx_buffers[entry].skb = NULL;
5146                 entry = NEXT_TX(entry);
5147                 i++;
5148         }
5149
5150         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5151         dev_kfree_skb(skb);
5152
5153         return ret;
5154 }
5155
5156 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5157                         dma_addr_t mapping, int len, u32 flags,
5158                         u32 mss_and_is_end)
5159 {
5160         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5161         int is_end = (mss_and_is_end & 0x1);
5162         u32 mss = (mss_and_is_end >> 1);
5163         u32 vlan_tag = 0;
5164
5165         if (is_end)
5166                 flags |= TXD_FLAG_END;
5167         if (flags & TXD_FLAG_VLAN) {
5168                 vlan_tag = flags >> 16;
5169                 flags &= 0xffff;
5170         }
5171         vlan_tag |= (mss << TXD_MSS_SHIFT);
5172
5173         txd->addr_hi = ((u64) mapping >> 32);
5174         txd->addr_lo = ((u64) mapping & 0xffffffff);
5175         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5176         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5177 }
5178
5179 /* hard_start_xmit for devices that don't have any bugs and
5180  * support TG3_FLG2_HW_TSO_2 only.
5181  */
5182 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5183                                   struct net_device *dev)
5184 {
5185         struct tg3 *tp = netdev_priv(dev);
5186         u32 len, entry, base_flags, mss;
5187         struct skb_shared_info *sp;
5188         dma_addr_t mapping;
5189         struct tg3_napi *tnapi;
5190         struct netdev_queue *txq;
5191
5192         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5193         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5194         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5195                 tnapi++;
5196
5197         /* We are running in BH disabled context with netif_tx_lock
5198          * and TX reclaim runs via tp->napi.poll inside of a software
5199          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5200          * no IRQ context deadlocks to worry about either.  Rejoice!
5201          */
5202         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5203                 if (!netif_tx_queue_stopped(txq)) {
5204                         netif_tx_stop_queue(txq);
5205
5206                         /* This is a hard error, log it. */
5207                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5208                                "queue awake!\n", dev->name);
5209                 }
5210                 return NETDEV_TX_BUSY;
5211         }
5212
5213         entry = tnapi->tx_prod;
5214         base_flags = 0;
5215         mss = 0;
5216         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5217                 int tcp_opt_len, ip_tcp_len;
5218                 u32 hdrlen;
5219
5220                 if (skb_header_cloned(skb) &&
5221                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5222                         dev_kfree_skb(skb);
5223                         goto out_unlock;
5224                 }
5225
5226                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5227                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5228                 else {
5229                         struct iphdr *iph = ip_hdr(skb);
5230
5231                         tcp_opt_len = tcp_optlen(skb);
5232                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5233
5234                         iph->check = 0;
5235                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5236                         hdrlen = ip_tcp_len + tcp_opt_len;
5237                 }
5238
5239                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5240                         mss |= (hdrlen & 0xc) << 12;
5241                         if (hdrlen & 0x10)
5242                                 base_flags |= 0x00000010;
5243                         base_flags |= (hdrlen & 0x3e0) << 5;
5244                 } else
5245                         mss |= hdrlen << 9;
5246
5247                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5248                                TXD_FLAG_CPU_POST_DMA);
5249
5250                 tcp_hdr(skb)->check = 0;
5251
5252         }
5253         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5254                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5255 #if TG3_VLAN_TAG_USED
5256         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5257                 base_flags |= (TXD_FLAG_VLAN |
5258                                (vlan_tx_tag_get(skb) << 16));
5259 #endif
5260
5261         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5262                 dev_kfree_skb(skb);
5263                 goto out_unlock;
5264         }
5265
5266         sp = skb_shinfo(skb);
5267
5268         mapping = sp->dma_head;
5269
5270         tnapi->tx_buffers[entry].skb = skb;
5271
5272         len = skb_headlen(skb);
5273
5274         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5275             !mss && skb->len > ETH_DATA_LEN)
5276                 base_flags |= TXD_FLAG_JMB_PKT;
5277
5278         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5279                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5280
5281         entry = NEXT_TX(entry);
5282
5283         /* Now loop through additional data fragments, and queue them. */
5284         if (skb_shinfo(skb)->nr_frags > 0) {
5285                 unsigned int i, last;
5286
5287                 last = skb_shinfo(skb)->nr_frags - 1;
5288                 for (i = 0; i <= last; i++) {
5289                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5290
5291                         len = frag->size;
5292                         mapping = sp->dma_maps[i];
5293                         tnapi->tx_buffers[entry].skb = NULL;
5294
5295                         tg3_set_txd(tnapi, entry, mapping, len,
5296                                     base_flags, (i == last) | (mss << 1));
5297
5298                         entry = NEXT_TX(entry);
5299                 }
5300         }
5301
5302         /* Packets are ready, update Tx producer idx local and on card. */
5303         tw32_tx_mbox(tnapi->prodmbox, entry);
5304
5305         tnapi->tx_prod = entry;
5306         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5307                 netif_tx_stop_queue(txq);
5308                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5309                         netif_tx_wake_queue(txq);
5310         }
5311
5312 out_unlock:
5313         mmiowb();
5314
5315         return NETDEV_TX_OK;
5316 }
5317
5318 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5319                                           struct net_device *);
5320
5321 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5322  * TSO header is greater than 80 bytes.
5323  */
5324 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5325 {
5326         struct sk_buff *segs, *nskb;
5327         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5328
5329         /* Estimate the number of fragments in the worst case */
5330         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5331                 netif_stop_queue(tp->dev);
5332                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5333                         return NETDEV_TX_BUSY;
5334
5335                 netif_wake_queue(tp->dev);
5336         }
5337
5338         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5339         if (IS_ERR(segs))
5340                 goto tg3_tso_bug_end;
5341
5342         do {
5343                 nskb = segs;
5344                 segs = segs->next;
5345                 nskb->next = NULL;
5346                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5347         } while (segs);
5348
5349 tg3_tso_bug_end:
5350         dev_kfree_skb(skb);
5351
5352         return NETDEV_TX_OK;
5353 }
5354
5355 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5356  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5357  */
5358 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5359                                           struct net_device *dev)
5360 {
5361         struct tg3 *tp = netdev_priv(dev);
5362         u32 len, entry, base_flags, mss;
5363         struct skb_shared_info *sp;
5364         int would_hit_hwbug;
5365         dma_addr_t mapping;
5366         struct tg3_napi *tnapi = &tp->napi[0];
5367
5368         len = skb_headlen(skb);
5369
5370         /* We are running in BH disabled context with netif_tx_lock
5371          * and TX reclaim runs via tp->napi.poll inside of a software
5372          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5373          * no IRQ context deadlocks to worry about either.  Rejoice!
5374          */
5375         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5376                 if (!netif_queue_stopped(dev)) {
5377                         netif_stop_queue(dev);
5378
5379                         /* This is a hard error, log it. */
5380                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5381                                "queue awake!\n", dev->name);
5382                 }
5383                 return NETDEV_TX_BUSY;
5384         }
5385
5386         entry = tnapi->tx_prod;
5387         base_flags = 0;
5388         if (skb->ip_summed == CHECKSUM_PARTIAL)
5389                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5390         mss = 0;
5391         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5392                 struct iphdr *iph;
5393                 int tcp_opt_len, ip_tcp_len, hdr_len;
5394
5395                 if (skb_header_cloned(skb) &&
5396                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5397                         dev_kfree_skb(skb);
5398                         goto out_unlock;
5399                 }
5400
5401                 tcp_opt_len = tcp_optlen(skb);
5402                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5403
5404                 hdr_len = ip_tcp_len + tcp_opt_len;
5405                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5406                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5407                         return (tg3_tso_bug(tp, skb));
5408
5409                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5410                                TXD_FLAG_CPU_POST_DMA);
5411
5412                 iph = ip_hdr(skb);
5413                 iph->check = 0;
5414                 iph->tot_len = htons(mss + hdr_len);
5415                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5416                         tcp_hdr(skb)->check = 0;
5417                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5418                 } else
5419                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5420                                                                  iph->daddr, 0,
5421                                                                  IPPROTO_TCP,
5422                                                                  0);
5423
5424                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5425                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5426                         if (tcp_opt_len || iph->ihl > 5) {
5427                                 int tsflags;
5428
5429                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5430                                 mss |= (tsflags << 11);
5431                         }
5432                 } else {
5433                         if (tcp_opt_len || iph->ihl > 5) {
5434                                 int tsflags;
5435
5436                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5437                                 base_flags |= tsflags << 12;
5438                         }
5439                 }
5440         }
5441 #if TG3_VLAN_TAG_USED
5442         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5443                 base_flags |= (TXD_FLAG_VLAN |
5444                                (vlan_tx_tag_get(skb) << 16));
5445 #endif
5446
5447         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5448                 dev_kfree_skb(skb);
5449                 goto out_unlock;
5450         }
5451
5452         sp = skb_shinfo(skb);
5453
5454         mapping = sp->dma_head;
5455
5456         tnapi->tx_buffers[entry].skb = skb;
5457
5458         would_hit_hwbug = 0;
5459
5460         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5461                 would_hit_hwbug = 1;
5462         else if (tg3_4g_overflow_test(mapping, len))
5463                 would_hit_hwbug = 1;
5464
5465         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5466                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5467
5468         entry = NEXT_TX(entry);
5469
5470         /* Now loop through additional data fragments, and queue them. */
5471         if (skb_shinfo(skb)->nr_frags > 0) {
5472                 unsigned int i, last;
5473
5474                 last = skb_shinfo(skb)->nr_frags - 1;
5475                 for (i = 0; i <= last; i++) {
5476                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5477
5478                         len = frag->size;
5479                         mapping = sp->dma_maps[i];
5480
5481                         tnapi->tx_buffers[entry].skb = NULL;
5482
5483                         if (tg3_4g_overflow_test(mapping, len))
5484                                 would_hit_hwbug = 1;
5485
5486                         if (tg3_40bit_overflow_test(tp, mapping, len))
5487                                 would_hit_hwbug = 1;
5488
5489                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5490                                 tg3_set_txd(tnapi, entry, mapping, len,
5491                                             base_flags, (i == last)|(mss << 1));
5492                         else
5493                                 tg3_set_txd(tnapi, entry, mapping, len,
5494                                             base_flags, (i == last));
5495
5496                         entry = NEXT_TX(entry);
5497                 }
5498         }
5499
5500         if (would_hit_hwbug) {
5501                 u32 last_plus_one = entry;
5502                 u32 start;
5503
5504                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5505                 start &= (TG3_TX_RING_SIZE - 1);
5506
5507                 /* If the workaround fails due to memory/mapping
5508                  * failure, silently drop this packet.
5509                  */
5510                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5511                                                 &start, base_flags, mss))
5512                         goto out_unlock;
5513
5514                 entry = start;
5515         }
5516
5517         /* Packets are ready, update Tx producer idx local and on card. */
5518         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5519
5520         tnapi->tx_prod = entry;
5521         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5522                 netif_stop_queue(dev);
5523                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5524                         netif_wake_queue(tp->dev);
5525         }
5526
5527 out_unlock:
5528         mmiowb();
5529
5530         return NETDEV_TX_OK;
5531 }
5532
5533 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5534                                int new_mtu)
5535 {
5536         dev->mtu = new_mtu;
5537
5538         if (new_mtu > ETH_DATA_LEN) {
5539                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5540                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5541                         ethtool_op_set_tso(dev, 0);
5542                 }
5543                 else
5544                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5545         } else {
5546                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5547                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5548                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5549         }
5550 }
5551
5552 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5553 {
5554         struct tg3 *tp = netdev_priv(dev);
5555         int err;
5556
5557         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5558                 return -EINVAL;
5559
5560         if (!netif_running(dev)) {
5561                 /* We'll just catch it later when the
5562                  * device is up'd.
5563                  */
5564                 tg3_set_mtu(dev, tp, new_mtu);
5565                 return 0;
5566         }
5567
5568         tg3_phy_stop(tp);
5569
5570         tg3_netif_stop(tp);
5571
5572         tg3_full_lock(tp, 1);
5573
5574         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5575
5576         tg3_set_mtu(dev, tp, new_mtu);
5577
5578         err = tg3_restart_hw(tp, 0);
5579
5580         if (!err)
5581                 tg3_netif_start(tp);
5582
5583         tg3_full_unlock(tp);
5584
5585         if (!err)
5586                 tg3_phy_start(tp);
5587
5588         return err;
5589 }
5590
5591 static void tg3_rx_prodring_free(struct tg3 *tp,
5592                                  struct tg3_rx_prodring_set *tpr)
5593 {
5594         int i;
5595         struct ring_info *rxp;
5596
5597         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5598                 rxp = &tpr->rx_std_buffers[i];
5599
5600                 if (rxp->skb == NULL)
5601                         continue;
5602
5603                 pci_unmap_single(tp->pdev,
5604                                  pci_unmap_addr(rxp, mapping),
5605                                  tp->rx_pkt_map_sz,
5606                                  PCI_DMA_FROMDEVICE);
5607                 dev_kfree_skb_any(rxp->skb);
5608                 rxp->skb = NULL;
5609         }
5610
5611         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5612                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5613                         rxp = &tpr->rx_jmb_buffers[i];
5614
5615                         if (rxp->skb == NULL)
5616                                 continue;
5617
5618                         pci_unmap_single(tp->pdev,
5619                                          pci_unmap_addr(rxp, mapping),
5620                                          TG3_RX_JMB_MAP_SZ,
5621                                          PCI_DMA_FROMDEVICE);
5622                         dev_kfree_skb_any(rxp->skb);
5623                         rxp->skb = NULL;
5624                 }
5625         }
5626 }
5627
5628 /* Initialize tx/rx rings for packet processing.
5629  *
5630  * The chip has been shut down and the driver detached from
5631  * the networking, so no interrupts or new tx packets will
5632  * end up in the driver.  tp->{tx,}lock are held and thus
5633  * we may not sleep.
5634  */
5635 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5636                                  struct tg3_rx_prodring_set *tpr)
5637 {
5638         u32 i, rx_pkt_dma_sz;
5639         struct tg3_napi *tnapi = &tp->napi[0];
5640
5641         /* Zero out all descriptors. */
5642         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5643
5644         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5645         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5646             tp->dev->mtu > ETH_DATA_LEN)
5647                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5648         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5649
5650         /* Initialize invariants of the rings, we only set this
5651          * stuff once.  This works because the card does not
5652          * write into the rx buffer posting rings.
5653          */
5654         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5655                 struct tg3_rx_buffer_desc *rxd;
5656
5657                 rxd = &tpr->rx_std[i];
5658                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5659                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5660                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5661                                (i << RXD_OPAQUE_INDEX_SHIFT));
5662         }
5663
5664         /* Now allocate fresh SKBs for each rx ring. */
5665         for (i = 0; i < tp->rx_pending; i++) {
5666                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5667                         printk(KERN_WARNING PFX
5668                                "%s: Using a smaller RX standard ring, "
5669                                "only %d out of %d buffers were allocated "
5670                                "successfully.\n",
5671                                tp->dev->name, i, tp->rx_pending);
5672                         if (i == 0)
5673                                 goto initfail;
5674                         tp->rx_pending = i;
5675                         break;
5676                 }
5677         }
5678
5679         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5680                 goto done;
5681
5682         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5683
5684         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5685                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5686                         struct tg3_rx_buffer_desc *rxd;
5687
5688                         rxd = &tpr->rx_jmb[i].std;
5689                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5690                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5691                                 RXD_FLAG_JUMBO;
5692                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5693                                (i << RXD_OPAQUE_INDEX_SHIFT));
5694                 }
5695
5696                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5697                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5698                                              -1, i) < 0) {
5699                                 printk(KERN_WARNING PFX
5700                                        "%s: Using a smaller RX jumbo ring, "
5701                                        "only %d out of %d buffers were "
5702                                        "allocated successfully.\n",
5703                                        tp->dev->name, i, tp->rx_jumbo_pending);
5704                                 if (i == 0)
5705                                         goto initfail;
5706                                 tp->rx_jumbo_pending = i;
5707                                 break;
5708                         }
5709                 }
5710         }
5711
5712 done:
5713         return 0;
5714
5715 initfail:
5716         tg3_rx_prodring_free(tp, tpr);
5717         return -ENOMEM;
5718 }
5719
5720 static void tg3_rx_prodring_fini(struct tg3 *tp,
5721                                  struct tg3_rx_prodring_set *tpr)
5722 {
5723         kfree(tpr->rx_std_buffers);
5724         tpr->rx_std_buffers = NULL;
5725         kfree(tpr->rx_jmb_buffers);
5726         tpr->rx_jmb_buffers = NULL;
5727         if (tpr->rx_std) {
5728                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5729                                     tpr->rx_std, tpr->rx_std_mapping);
5730                 tpr->rx_std = NULL;
5731         }
5732         if (tpr->rx_jmb) {
5733                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5734                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5735                 tpr->rx_jmb = NULL;
5736         }
5737 }
5738
5739 static int tg3_rx_prodring_init(struct tg3 *tp,
5740                                 struct tg3_rx_prodring_set *tpr)
5741 {
5742         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5743                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5744         if (!tpr->rx_std_buffers)
5745                 return -ENOMEM;
5746
5747         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5748                                            &tpr->rx_std_mapping);
5749         if (!tpr->rx_std)
5750                 goto err_out;
5751
5752         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5753                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5754                                               TG3_RX_JUMBO_RING_SIZE,
5755                                               GFP_KERNEL);
5756                 if (!tpr->rx_jmb_buffers)
5757                         goto err_out;
5758
5759                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5760                                                    TG3_RX_JUMBO_RING_BYTES,
5761                                                    &tpr->rx_jmb_mapping);
5762                 if (!tpr->rx_jmb)
5763                         goto err_out;
5764         }
5765
5766         return 0;
5767
5768 err_out:
5769         tg3_rx_prodring_fini(tp, tpr);
5770         return -ENOMEM;
5771 }
5772
5773 /* Free up pending packets in all rx/tx rings.
5774  *
5775  * The chip has been shut down and the driver detached from
5776  * the networking, so no interrupts or new tx packets will
5777  * end up in the driver.  tp->{tx,}lock is not held and we are not
5778  * in an interrupt context and thus may sleep.
5779  */
5780 static void tg3_free_rings(struct tg3 *tp)
5781 {
5782         int i, j;
5783
5784         for (j = 0; j < tp->irq_cnt; j++) {
5785                 struct tg3_napi *tnapi = &tp->napi[j];
5786
5787                 if (!tnapi->tx_buffers)
5788                         continue;
5789
5790                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5791                         struct tx_ring_info *txp;
5792                         struct sk_buff *skb;
5793
5794                         txp = &tnapi->tx_buffers[i];
5795                         skb = txp->skb;
5796
5797                         if (skb == NULL) {
5798                                 i++;
5799                                 continue;
5800                         }
5801
5802                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5803
5804                         txp->skb = NULL;
5805
5806                         i += skb_shinfo(skb)->nr_frags + 1;
5807
5808                         dev_kfree_skb_any(skb);
5809                 }
5810         }
5811
5812         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5813 }
5814
5815 /* Initialize tx/rx rings for packet processing.
5816  *
5817  * The chip has been shut down and the driver detached from
5818  * the networking, so no interrupts or new tx packets will
5819  * end up in the driver.  tp->{tx,}lock are held and thus
5820  * we may not sleep.
5821  */
5822 static int tg3_init_rings(struct tg3 *tp)
5823 {
5824         int i;
5825
5826         /* Free up all the SKBs. */
5827         tg3_free_rings(tp);
5828
5829         for (i = 0; i < tp->irq_cnt; i++) {
5830                 struct tg3_napi *tnapi = &tp->napi[i];
5831
5832                 tnapi->last_tag = 0;
5833                 tnapi->last_irq_tag = 0;
5834                 tnapi->hw_status->status = 0;
5835                 tnapi->hw_status->status_tag = 0;
5836                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5837
5838                 tnapi->tx_prod = 0;
5839                 tnapi->tx_cons = 0;
5840                 if (tnapi->tx_ring)
5841                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5842
5843                 tnapi->rx_rcb_ptr = 0;
5844                 if (tnapi->rx_rcb)
5845                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5846         }
5847
5848         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5849 }
5850
5851 /*
5852  * Must not be invoked with interrupt sources disabled and
5853  * the hardware shutdown down.
5854  */
5855 static void tg3_free_consistent(struct tg3 *tp)
5856 {
5857         int i;
5858
5859         for (i = 0; i < tp->irq_cnt; i++) {
5860                 struct tg3_napi *tnapi = &tp->napi[i];
5861
5862                 if (tnapi->tx_ring) {
5863                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5864                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5865                         tnapi->tx_ring = NULL;
5866                 }
5867
5868                 kfree(tnapi->tx_buffers);
5869                 tnapi->tx_buffers = NULL;
5870
5871                 if (tnapi->rx_rcb) {
5872                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5873                                             tnapi->rx_rcb,
5874                                             tnapi->rx_rcb_mapping);
5875                         tnapi->rx_rcb = NULL;
5876                 }
5877
5878                 if (tnapi->hw_status) {
5879                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5880                                             tnapi->hw_status,
5881                                             tnapi->status_mapping);
5882                         tnapi->hw_status = NULL;
5883                 }
5884         }
5885
5886         if (tp->hw_stats) {
5887                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5888                                     tp->hw_stats, tp->stats_mapping);
5889                 tp->hw_stats = NULL;
5890         }
5891
5892         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5893 }
5894
5895 /*
5896  * Must not be invoked with interrupt sources disabled and
5897  * the hardware shutdown down.  Can sleep.
5898  */
5899 static int tg3_alloc_consistent(struct tg3 *tp)
5900 {
5901         int i;
5902
5903         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5904                 return -ENOMEM;
5905
5906         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5907                                             sizeof(struct tg3_hw_stats),
5908                                             &tp->stats_mapping);
5909         if (!tp->hw_stats)
5910                 goto err_out;
5911
5912         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5913
5914         for (i = 0; i < tp->irq_cnt; i++) {
5915                 struct tg3_napi *tnapi = &tp->napi[i];
5916                 struct tg3_hw_status *sblk;
5917
5918                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5919                                                         TG3_HW_STATUS_SIZE,
5920                                                         &tnapi->status_mapping);
5921                 if (!tnapi->hw_status)
5922                         goto err_out;
5923
5924                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5925                 sblk = tnapi->hw_status;
5926
5927                 /*
5928                  * When RSS is enabled, the status block format changes
5929                  * slightly.  The "rx_jumbo_consumer", "reserved",
5930                  * and "rx_mini_consumer" members get mapped to the
5931                  * other three rx return ring producer indexes.
5932                  */
5933                 switch (i) {
5934                 default:
5935                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5936                         break;
5937                 case 2:
5938                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5939                         break;
5940                 case 3:
5941                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
5942                         break;
5943                 case 4:
5944                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5945                         break;
5946                 }
5947
5948                 /*
5949                  * If multivector RSS is enabled, vector 0 does not handle
5950                  * rx or tx interrupts.  Don't allocate any resources for it.
5951                  */
5952                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5953                         continue;
5954
5955                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5956                                                      TG3_RX_RCB_RING_BYTES(tp),
5957                                                      &tnapi->rx_rcb_mapping);
5958                 if (!tnapi->rx_rcb)
5959                         goto err_out;
5960
5961                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5962
5963                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5964                                             TG3_TX_RING_SIZE, GFP_KERNEL);
5965                 if (!tnapi->tx_buffers)
5966                         goto err_out;
5967
5968                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
5969                                                       TG3_TX_RING_BYTES,
5970                                                       &tnapi->tx_desc_mapping);
5971                 if (!tnapi->tx_ring)
5972                         goto err_out;
5973         }
5974
5975         return 0;
5976
5977 err_out:
5978         tg3_free_consistent(tp);
5979         return -ENOMEM;
5980 }
5981
5982 #define MAX_WAIT_CNT 1000
5983
5984 /* To stop a block, clear the enable bit and poll till it
5985  * clears.  tp->lock is held.
5986  */
5987 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5988 {
5989         unsigned int i;
5990         u32 val;
5991
5992         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5993                 switch (ofs) {
5994                 case RCVLSC_MODE:
5995                 case DMAC_MODE:
5996                 case MBFREE_MODE:
5997                 case BUFMGR_MODE:
5998                 case MEMARB_MODE:
5999                         /* We can't enable/disable these bits of the
6000                          * 5705/5750, just say success.
6001                          */
6002                         return 0;
6003
6004                 default:
6005                         break;
6006                 }
6007         }
6008
6009         val = tr32(ofs);
6010         val &= ~enable_bit;
6011         tw32_f(ofs, val);
6012
6013         for (i = 0; i < MAX_WAIT_CNT; i++) {
6014                 udelay(100);
6015                 val = tr32(ofs);
6016                 if ((val & enable_bit) == 0)
6017                         break;
6018         }
6019
6020         if (i == MAX_WAIT_CNT && !silent) {
6021                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6022                        "ofs=%lx enable_bit=%x\n",
6023                        ofs, enable_bit);
6024                 return -ENODEV;
6025         }
6026
6027         return 0;
6028 }
6029
6030 /* tp->lock is held. */
6031 static int tg3_abort_hw(struct tg3 *tp, int silent)
6032 {
6033         int i, err;
6034
6035         tg3_disable_ints(tp);
6036
6037         tp->rx_mode &= ~RX_MODE_ENABLE;
6038         tw32_f(MAC_RX_MODE, tp->rx_mode);
6039         udelay(10);
6040
6041         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6042         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6043         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6044         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6045         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6046         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6047
6048         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6049         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6050         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6051         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6052         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6053         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6054         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6055
6056         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6057         tw32_f(MAC_MODE, tp->mac_mode);
6058         udelay(40);
6059
6060         tp->tx_mode &= ~TX_MODE_ENABLE;
6061         tw32_f(MAC_TX_MODE, tp->tx_mode);
6062
6063         for (i = 0; i < MAX_WAIT_CNT; i++) {
6064                 udelay(100);
6065                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6066                         break;
6067         }
6068         if (i >= MAX_WAIT_CNT) {
6069                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6070                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6071                        tp->dev->name, tr32(MAC_TX_MODE));
6072                 err |= -ENODEV;
6073         }
6074
6075         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6076         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6077         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6078
6079         tw32(FTQ_RESET, 0xffffffff);
6080         tw32(FTQ_RESET, 0x00000000);
6081
6082         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6083         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6084
6085         for (i = 0; i < tp->irq_cnt; i++) {
6086                 struct tg3_napi *tnapi = &tp->napi[i];
6087                 if (tnapi->hw_status)
6088                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6089         }
6090         if (tp->hw_stats)
6091                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6092
6093         return err;
6094 }
6095
6096 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6097 {
6098         int i;
6099         u32 apedata;
6100
6101         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6102         if (apedata != APE_SEG_SIG_MAGIC)
6103                 return;
6104
6105         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6106         if (!(apedata & APE_FW_STATUS_READY))
6107                 return;
6108
6109         /* Wait for up to 1 millisecond for APE to service previous event. */
6110         for (i = 0; i < 10; i++) {
6111                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6112                         return;
6113
6114                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6115
6116                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6117                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6118                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6119
6120                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6121
6122                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6123                         break;
6124
6125                 udelay(100);
6126         }
6127
6128         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6129                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6130 }
6131
6132 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6133 {
6134         u32 event;
6135         u32 apedata;
6136
6137         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6138                 return;
6139
6140         switch (kind) {
6141                 case RESET_KIND_INIT:
6142                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6143                                         APE_HOST_SEG_SIG_MAGIC);
6144                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6145                                         APE_HOST_SEG_LEN_MAGIC);
6146                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6147                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6148                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6149                                         APE_HOST_DRIVER_ID_MAGIC);
6150                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6151                                         APE_HOST_BEHAV_NO_PHYLOCK);
6152
6153                         event = APE_EVENT_STATUS_STATE_START;
6154                         break;
6155                 case RESET_KIND_SHUTDOWN:
6156                         /* With the interface we are currently using,
6157                          * APE does not track driver state.  Wiping
6158                          * out the HOST SEGMENT SIGNATURE forces
6159                          * the APE to assume OS absent status.
6160                          */
6161                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6162
6163                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6164                         break;
6165                 case RESET_KIND_SUSPEND:
6166                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6167                         break;
6168                 default:
6169                         return;
6170         }
6171
6172         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6173
6174         tg3_ape_send_event(tp, event);
6175 }
6176
6177 /* tp->lock is held. */
6178 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6179 {
6180         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6181                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6182
6183         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6184                 switch (kind) {
6185                 case RESET_KIND_INIT:
6186                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6187                                       DRV_STATE_START);
6188                         break;
6189
6190                 case RESET_KIND_SHUTDOWN:
6191                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6192                                       DRV_STATE_UNLOAD);
6193                         break;
6194
6195                 case RESET_KIND_SUSPEND:
6196                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6197                                       DRV_STATE_SUSPEND);
6198                         break;
6199
6200                 default:
6201                         break;
6202                 }
6203         }
6204
6205         if (kind == RESET_KIND_INIT ||
6206             kind == RESET_KIND_SUSPEND)
6207                 tg3_ape_driver_state_change(tp, kind);
6208 }
6209
6210 /* tp->lock is held. */
6211 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6212 {
6213         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6214                 switch (kind) {
6215                 case RESET_KIND_INIT:
6216                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6217                                       DRV_STATE_START_DONE);
6218                         break;
6219
6220                 case RESET_KIND_SHUTDOWN:
6221                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6222                                       DRV_STATE_UNLOAD_DONE);
6223                         break;
6224
6225                 default:
6226                         break;
6227                 }
6228         }
6229
6230         if (kind == RESET_KIND_SHUTDOWN)
6231                 tg3_ape_driver_state_change(tp, kind);
6232 }
6233
6234 /* tp->lock is held. */
6235 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6236 {
6237         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6238                 switch (kind) {
6239                 case RESET_KIND_INIT:
6240                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6241                                       DRV_STATE_START);
6242                         break;
6243
6244                 case RESET_KIND_SHUTDOWN:
6245                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6246                                       DRV_STATE_UNLOAD);
6247                         break;
6248
6249                 case RESET_KIND_SUSPEND:
6250                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6251                                       DRV_STATE_SUSPEND);
6252                         break;
6253
6254                 default:
6255                         break;
6256                 }
6257         }
6258 }
6259
6260 static int tg3_poll_fw(struct tg3 *tp)
6261 {
6262         int i;
6263         u32 val;
6264
6265         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6266                 /* Wait up to 20ms for init done. */
6267                 for (i = 0; i < 200; i++) {
6268                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6269                                 return 0;
6270                         udelay(100);
6271                 }
6272                 return -ENODEV;
6273         }
6274
6275         /* Wait for firmware initialization to complete. */
6276         for (i = 0; i < 100000; i++) {
6277                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6278                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6279                         break;
6280                 udelay(10);
6281         }
6282
6283         /* Chip might not be fitted with firmware.  Some Sun onboard
6284          * parts are configured like that.  So don't signal the timeout
6285          * of the above loop as an error, but do report the lack of
6286          * running firmware once.
6287          */
6288         if (i >= 100000 &&
6289             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6290                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6291
6292                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6293                        tp->dev->name);
6294         }
6295
6296         return 0;
6297 }
6298
6299 /* Save PCI command register before chip reset */
6300 static void tg3_save_pci_state(struct tg3 *tp)
6301 {
6302         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6303 }
6304
6305 /* Restore PCI state after chip reset */
6306 static void tg3_restore_pci_state(struct tg3 *tp)
6307 {
6308         u32 val;
6309
6310         /* Re-enable indirect register accesses. */
6311         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6312                                tp->misc_host_ctrl);
6313
6314         /* Set MAX PCI retry to zero. */
6315         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6316         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6317             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6318                 val |= PCISTATE_RETRY_SAME_DMA;
6319         /* Allow reads and writes to the APE register and memory space. */
6320         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6321                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6322                        PCISTATE_ALLOW_APE_SHMEM_WR;
6323         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6324
6325         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6326
6327         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6328                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6329                         pcie_set_readrq(tp->pdev, 4096);
6330                 else {
6331                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6332                                               tp->pci_cacheline_sz);
6333                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6334                                               tp->pci_lat_timer);
6335                 }
6336         }
6337
6338         /* Make sure PCI-X relaxed ordering bit is clear. */
6339         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6340                 u16 pcix_cmd;
6341
6342                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6343                                      &pcix_cmd);
6344                 pcix_cmd &= ~PCI_X_CMD_ERO;
6345                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6346                                       pcix_cmd);
6347         }
6348
6349         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6350
6351                 /* Chip reset on 5780 will reset MSI enable bit,
6352                  * so need to restore it.
6353                  */
6354                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6355                         u16 ctrl;
6356
6357                         pci_read_config_word(tp->pdev,
6358                                              tp->msi_cap + PCI_MSI_FLAGS,
6359                                              &ctrl);
6360                         pci_write_config_word(tp->pdev,
6361                                               tp->msi_cap + PCI_MSI_FLAGS,
6362                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6363                         val = tr32(MSGINT_MODE);
6364                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6365                 }
6366         }
6367 }
6368
6369 static void tg3_stop_fw(struct tg3 *);
6370
6371 /* tp->lock is held. */
6372 static int tg3_chip_reset(struct tg3 *tp)
6373 {
6374         u32 val;
6375         void (*write_op)(struct tg3 *, u32, u32);
6376         int i, err;
6377
6378         tg3_nvram_lock(tp);
6379
6380         tg3_mdio_stop(tp);
6381
6382         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6383
6384         /* No matching tg3_nvram_unlock() after this because
6385          * chip reset below will undo the nvram lock.
6386          */
6387         tp->nvram_lock_cnt = 0;
6388
6389         /* GRC_MISC_CFG core clock reset will clear the memory
6390          * enable bit in PCI register 4 and the MSI enable bit
6391          * on some chips, so we save relevant registers here.
6392          */
6393         tg3_save_pci_state(tp);
6394
6395         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6396             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6397                 tw32(GRC_FASTBOOT_PC, 0);
6398
6399         /*
6400          * We must avoid the readl() that normally takes place.
6401          * It locks machines, causes machine checks, and other
6402          * fun things.  So, temporarily disable the 5701
6403          * hardware workaround, while we do the reset.
6404          */
6405         write_op = tp->write32;
6406         if (write_op == tg3_write_flush_reg32)
6407                 tp->write32 = tg3_write32;
6408
6409         /* Prevent the irq handler from reading or writing PCI registers
6410          * during chip reset when the memory enable bit in the PCI command
6411          * register may be cleared.  The chip does not generate interrupt
6412          * at this time, but the irq handler may still be called due to irq
6413          * sharing or irqpoll.
6414          */
6415         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6416         for (i = 0; i < tp->irq_cnt; i++) {
6417                 struct tg3_napi *tnapi = &tp->napi[i];
6418                 if (tnapi->hw_status) {
6419                         tnapi->hw_status->status = 0;
6420                         tnapi->hw_status->status_tag = 0;
6421                 }
6422                 tnapi->last_tag = 0;
6423                 tnapi->last_irq_tag = 0;
6424         }
6425         smp_mb();
6426
6427         for (i = 0; i < tp->irq_cnt; i++)
6428                 synchronize_irq(tp->napi[i].irq_vec);
6429
6430         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6431                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6432                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6433         }
6434
6435         /* do the reset */
6436         val = GRC_MISC_CFG_CORECLK_RESET;
6437
6438         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6439                 if (tr32(0x7e2c) == 0x60) {
6440                         tw32(0x7e2c, 0x20);
6441                 }
6442                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6443                         tw32(GRC_MISC_CFG, (1 << 29));
6444                         val |= (1 << 29);
6445                 }
6446         }
6447
6448         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6449                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6450                 tw32(GRC_VCPU_EXT_CTRL,
6451                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6452         }
6453
6454         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6455                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6456         tw32(GRC_MISC_CFG, val);
6457
6458         /* restore 5701 hardware bug workaround write method */
6459         tp->write32 = write_op;
6460
6461         /* Unfortunately, we have to delay before the PCI read back.
6462          * Some 575X chips even will not respond to a PCI cfg access
6463          * when the reset command is given to the chip.
6464          *
6465          * How do these hardware designers expect things to work
6466          * properly if the PCI write is posted for a long period
6467          * of time?  It is always necessary to have some method by
6468          * which a register read back can occur to push the write
6469          * out which does the reset.
6470          *
6471          * For most tg3 variants the trick below was working.
6472          * Ho hum...
6473          */
6474         udelay(120);
6475
6476         /* Flush PCI posted writes.  The normal MMIO registers
6477          * are inaccessible at this time so this is the only
6478          * way to make this reliably (actually, this is no longer
6479          * the case, see above).  I tried to use indirect
6480          * register read/write but this upset some 5701 variants.
6481          */
6482         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6483
6484         udelay(120);
6485
6486         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6487                 u16 val16;
6488
6489                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6490                         int i;
6491                         u32 cfg_val;
6492
6493                         /* Wait for link training to complete.  */
6494                         for (i = 0; i < 5000; i++)
6495                                 udelay(100);
6496
6497                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6498                         pci_write_config_dword(tp->pdev, 0xc4,
6499                                                cfg_val | (1 << 15));
6500                 }
6501
6502                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6503                 pci_read_config_word(tp->pdev,
6504                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6505                                      &val16);
6506                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6507                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6508                 /*
6509                  * Older PCIe devices only support the 128 byte
6510                  * MPS setting.  Enforce the restriction.
6511                  */
6512                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6513                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6514                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6515                 pci_write_config_word(tp->pdev,
6516                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6517                                       val16);
6518
6519                 pcie_set_readrq(tp->pdev, 4096);
6520
6521                 /* Clear error status */
6522                 pci_write_config_word(tp->pdev,
6523                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6524                                       PCI_EXP_DEVSTA_CED |
6525                                       PCI_EXP_DEVSTA_NFED |
6526                                       PCI_EXP_DEVSTA_FED |
6527                                       PCI_EXP_DEVSTA_URD);
6528         }
6529
6530         tg3_restore_pci_state(tp);
6531
6532         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6533
6534         val = 0;
6535         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6536                 val = tr32(MEMARB_MODE);
6537         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6538
6539         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6540                 tg3_stop_fw(tp);
6541                 tw32(0x5000, 0x400);
6542         }
6543
6544         tw32(GRC_MODE, tp->grc_mode);
6545
6546         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6547                 val = tr32(0xc4);
6548
6549                 tw32(0xc4, val | (1 << 15));
6550         }
6551
6552         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6553             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6554                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6555                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6556                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6557                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6558         }
6559
6560         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6561                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6562                 tw32_f(MAC_MODE, tp->mac_mode);
6563         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6564                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6565                 tw32_f(MAC_MODE, tp->mac_mode);
6566         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6567                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6568                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6569                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6570                 tw32_f(MAC_MODE, tp->mac_mode);
6571         } else
6572                 tw32_f(MAC_MODE, 0);
6573         udelay(40);
6574
6575         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6576
6577         err = tg3_poll_fw(tp);
6578         if (err)
6579                 return err;
6580
6581         tg3_mdio_start(tp);
6582
6583         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6584             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6585             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6586             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6587                 val = tr32(0x7c00);
6588
6589                 tw32(0x7c00, val | (1 << 25));
6590         }
6591
6592         /* Reprobe ASF enable state.  */
6593         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6594         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6595         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6596         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6597                 u32 nic_cfg;
6598
6599                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6600                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6601                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6602                         tp->last_event_jiffies = jiffies;
6603                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6604                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6605                 }
6606         }
6607
6608         return 0;
6609 }
6610
6611 /* tp->lock is held. */
6612 static void tg3_stop_fw(struct tg3 *tp)
6613 {
6614         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6615            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6616                 /* Wait for RX cpu to ACK the previous event. */
6617                 tg3_wait_for_event_ack(tp);
6618
6619                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6620
6621                 tg3_generate_fw_event(tp);
6622
6623                 /* Wait for RX cpu to ACK this event. */
6624                 tg3_wait_for_event_ack(tp);
6625         }
6626 }
6627
6628 /* tp->lock is held. */
6629 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6630 {
6631         int err;
6632
6633         tg3_stop_fw(tp);
6634
6635         tg3_write_sig_pre_reset(tp, kind);
6636
6637         tg3_abort_hw(tp, silent);
6638         err = tg3_chip_reset(tp);
6639
6640         __tg3_set_mac_addr(tp, 0);
6641
6642         tg3_write_sig_legacy(tp, kind);
6643         tg3_write_sig_post_reset(tp, kind);
6644
6645         if (err)
6646                 return err;
6647
6648         return 0;
6649 }
6650
6651 #define RX_CPU_SCRATCH_BASE     0x30000
6652 #define RX_CPU_SCRATCH_SIZE     0x04000
6653 #define TX_CPU_SCRATCH_BASE     0x34000
6654 #define TX_CPU_SCRATCH_SIZE     0x04000
6655
6656 /* tp->lock is held. */
6657 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6658 {
6659         int i;
6660
6661         BUG_ON(offset == TX_CPU_BASE &&
6662             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6663
6664         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6665                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6666
6667                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6668                 return 0;
6669         }
6670         if (offset == RX_CPU_BASE) {
6671                 for (i = 0; i < 10000; i++) {
6672                         tw32(offset + CPU_STATE, 0xffffffff);
6673                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6674                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6675                                 break;
6676                 }
6677
6678                 tw32(offset + CPU_STATE, 0xffffffff);
6679                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6680                 udelay(10);
6681         } else {
6682                 for (i = 0; i < 10000; i++) {
6683                         tw32(offset + CPU_STATE, 0xffffffff);
6684                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6685                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6686                                 break;
6687                 }
6688         }
6689
6690         if (i >= 10000) {
6691                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6692                        "and %s CPU\n",
6693                        tp->dev->name,
6694                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6695                 return -ENODEV;
6696         }
6697
6698         /* Clear firmware's nvram arbitration. */
6699         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6700                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6701         return 0;
6702 }
6703
6704 struct fw_info {
6705         unsigned int fw_base;
6706         unsigned int fw_len;
6707         const __be32 *fw_data;
6708 };
6709
6710 /* tp->lock is held. */
6711 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6712                                  int cpu_scratch_size, struct fw_info *info)
6713 {
6714         int err, lock_err, i;
6715         void (*write_op)(struct tg3 *, u32, u32);
6716
6717         if (cpu_base == TX_CPU_BASE &&
6718             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6719                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6720                        "TX cpu firmware on %s which is 5705.\n",
6721                        tp->dev->name);
6722                 return -EINVAL;
6723         }
6724
6725         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6726                 write_op = tg3_write_mem;
6727         else
6728                 write_op = tg3_write_indirect_reg32;
6729
6730         /* It is possible that bootcode is still loading at this point.
6731          * Get the nvram lock first before halting the cpu.
6732          */
6733         lock_err = tg3_nvram_lock(tp);
6734         err = tg3_halt_cpu(tp, cpu_base);
6735         if (!lock_err)
6736                 tg3_nvram_unlock(tp);
6737         if (err)
6738                 goto out;
6739
6740         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6741                 write_op(tp, cpu_scratch_base + i, 0);
6742         tw32(cpu_base + CPU_STATE, 0xffffffff);
6743         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6744         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6745                 write_op(tp, (cpu_scratch_base +
6746                               (info->fw_base & 0xffff) +
6747                               (i * sizeof(u32))),
6748                               be32_to_cpu(info->fw_data[i]));
6749
6750         err = 0;
6751
6752 out:
6753         return err;
6754 }
6755
6756 /* tp->lock is held. */
6757 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6758 {
6759         struct fw_info info;
6760         const __be32 *fw_data;
6761         int err, i;
6762
6763         fw_data = (void *)tp->fw->data;
6764
6765         /* Firmware blob starts with version numbers, followed by
6766            start address and length. We are setting complete length.
6767            length = end_address_of_bss - start_address_of_text.
6768            Remainder is the blob to be loaded contiguously
6769            from start address. */
6770
6771         info.fw_base = be32_to_cpu(fw_data[1]);
6772         info.fw_len = tp->fw->size - 12;
6773         info.fw_data = &fw_data[3];
6774
6775         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6776                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6777                                     &info);
6778         if (err)
6779                 return err;
6780
6781         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6782                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6783                                     &info);
6784         if (err)
6785                 return err;
6786
6787         /* Now startup only the RX cpu. */
6788         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6789         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6790
6791         for (i = 0; i < 5; i++) {
6792                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6793                         break;
6794                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6795                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6796                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6797                 udelay(1000);
6798         }
6799         if (i >= 5) {
6800                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6801                        "to set RX CPU PC, is %08x should be %08x\n",
6802                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6803                        info.fw_base);
6804                 return -ENODEV;
6805         }
6806         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6807         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6808
6809         return 0;
6810 }
6811
6812 /* 5705 needs a special version of the TSO firmware.  */
6813
6814 /* tp->lock is held. */
6815 static int tg3_load_tso_firmware(struct tg3 *tp)
6816 {
6817         struct fw_info info;
6818         const __be32 *fw_data;
6819         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6820         int err, i;
6821
6822         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6823                 return 0;
6824
6825         fw_data = (void *)tp->fw->data;
6826
6827         /* Firmware blob starts with version numbers, followed by
6828            start address and length. We are setting complete length.
6829            length = end_address_of_bss - start_address_of_text.
6830            Remainder is the blob to be loaded contiguously
6831            from start address. */
6832
6833         info.fw_base = be32_to_cpu(fw_data[1]);
6834         cpu_scratch_size = tp->fw_len;
6835         info.fw_len = tp->fw->size - 12;
6836         info.fw_data = &fw_data[3];
6837
6838         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6839                 cpu_base = RX_CPU_BASE;
6840                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6841         } else {
6842                 cpu_base = TX_CPU_BASE;
6843                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6844                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6845         }
6846
6847         err = tg3_load_firmware_cpu(tp, cpu_base,
6848                                     cpu_scratch_base, cpu_scratch_size,
6849                                     &info);
6850         if (err)
6851                 return err;
6852
6853         /* Now startup the cpu. */
6854         tw32(cpu_base + CPU_STATE, 0xffffffff);
6855         tw32_f(cpu_base + CPU_PC, info.fw_base);
6856
6857         for (i = 0; i < 5; i++) {
6858                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6859                         break;
6860                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6861                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6862                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6863                 udelay(1000);
6864         }
6865         if (i >= 5) {
6866                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6867                        "to set CPU PC, is %08x should be %08x\n",
6868                        tp->dev->name, tr32(cpu_base + CPU_PC),
6869                        info.fw_base);
6870                 return -ENODEV;
6871         }
6872         tw32(cpu_base + CPU_STATE, 0xffffffff);
6873         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6874         return 0;
6875 }
6876
6877
6878 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6879 {
6880         struct tg3 *tp = netdev_priv(dev);
6881         struct sockaddr *addr = p;
6882         int err = 0, skip_mac_1 = 0;
6883
6884         if (!is_valid_ether_addr(addr->sa_data))
6885                 return -EINVAL;
6886
6887         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6888
6889         if (!netif_running(dev))
6890                 return 0;
6891
6892         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6893                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6894
6895                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6896                 addr0_low = tr32(MAC_ADDR_0_LOW);
6897                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6898                 addr1_low = tr32(MAC_ADDR_1_LOW);
6899
6900                 /* Skip MAC addr 1 if ASF is using it. */
6901                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6902                     !(addr1_high == 0 && addr1_low == 0))
6903                         skip_mac_1 = 1;
6904         }
6905         spin_lock_bh(&tp->lock);
6906         __tg3_set_mac_addr(tp, skip_mac_1);
6907         spin_unlock_bh(&tp->lock);
6908
6909         return err;
6910 }
6911
6912 /* tp->lock is held. */
6913 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6914                            dma_addr_t mapping, u32 maxlen_flags,
6915                            u32 nic_addr)
6916 {
6917         tg3_write_mem(tp,
6918                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6919                       ((u64) mapping >> 32));
6920         tg3_write_mem(tp,
6921                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6922                       ((u64) mapping & 0xffffffff));
6923         tg3_write_mem(tp,
6924                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6925                        maxlen_flags);
6926
6927         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6928                 tg3_write_mem(tp,
6929                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6930                               nic_addr);
6931 }
6932
6933 static void __tg3_set_rx_mode(struct net_device *);
6934 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6935 {
6936         int i;
6937
6938         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
6939                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6940                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6941                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6942
6943                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6944                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6945                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6946         } else {
6947                 tw32(HOSTCC_TXCOL_TICKS, 0);
6948                 tw32(HOSTCC_TXMAX_FRAMES, 0);
6949                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
6950
6951                 tw32(HOSTCC_RXCOL_TICKS, 0);
6952                 tw32(HOSTCC_RXMAX_FRAMES, 0);
6953                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
6954         }
6955
6956         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6957                 u32 val = ec->stats_block_coalesce_usecs;
6958
6959                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6960                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6961
6962                 if (!netif_carrier_ok(tp->dev))
6963                         val = 0;
6964
6965                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6966         }
6967
6968         for (i = 0; i < tp->irq_cnt - 1; i++) {
6969                 u32 reg;
6970
6971                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
6972                 tw32(reg, ec->rx_coalesce_usecs);
6973                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
6974                 tw32(reg, ec->tx_coalesce_usecs);
6975                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
6976                 tw32(reg, ec->rx_max_coalesced_frames);
6977                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
6978                 tw32(reg, ec->tx_max_coalesced_frames);
6979                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
6980                 tw32(reg, ec->rx_max_coalesced_frames_irq);
6981                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
6982                 tw32(reg, ec->tx_max_coalesced_frames_irq);
6983         }
6984
6985         for (; i < tp->irq_max - 1; i++) {
6986                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
6987                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
6988                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
6989                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
6990                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
6991                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
6992         }
6993 }
6994
6995 /* tp->lock is held. */
6996 static void tg3_rings_reset(struct tg3 *tp)
6997 {
6998         int i;
6999         u32 stblk, txrcb, rxrcb, limit;
7000         struct tg3_napi *tnapi = &tp->napi[0];
7001
7002         /* Disable all transmit rings but the first. */
7003         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7004                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7005         else
7006                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7007
7008         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7009              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7010                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7011                               BDINFO_FLAGS_DISABLED);
7012
7013
7014         /* Disable all receive return rings but the first. */
7015         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7016                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7017         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7018                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7019         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7020                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7021         else
7022                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7023
7024         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7025              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7026                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7027                               BDINFO_FLAGS_DISABLED);
7028
7029         /* Disable interrupts */
7030         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7031
7032         /* Zero mailbox registers. */
7033         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7034                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7035                         tp->napi[i].tx_prod = 0;
7036                         tp->napi[i].tx_cons = 0;
7037                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7038                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7039                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7040                 }
7041         } else {
7042                 tp->napi[0].tx_prod = 0;
7043                 tp->napi[0].tx_cons = 0;
7044                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7045                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7046         }
7047
7048         /* Make sure the NIC-based send BD rings are disabled. */
7049         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7050                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7051                 for (i = 0; i < 16; i++)
7052                         tw32_tx_mbox(mbox + i * 8, 0);
7053         }
7054
7055         txrcb = NIC_SRAM_SEND_RCB;
7056         rxrcb = NIC_SRAM_RCV_RET_RCB;
7057
7058         /* Clear status block in ram. */
7059         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7060
7061         /* Set status block DMA address */
7062         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7063              ((u64) tnapi->status_mapping >> 32));
7064         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7065              ((u64) tnapi->status_mapping & 0xffffffff));
7066
7067         if (tnapi->tx_ring) {
7068                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7069                                (TG3_TX_RING_SIZE <<
7070                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7071                                NIC_SRAM_TX_BUFFER_DESC);
7072                 txrcb += TG3_BDINFO_SIZE;
7073         }
7074
7075         if (tnapi->rx_rcb) {
7076                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7077                                (TG3_RX_RCB_RING_SIZE(tp) <<
7078                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7079                 rxrcb += TG3_BDINFO_SIZE;
7080         }
7081
7082         stblk = HOSTCC_STATBLCK_RING1;
7083
7084         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7085                 u64 mapping = (u64)tnapi->status_mapping;
7086                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7087                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7088
7089                 /* Clear status block in ram. */
7090                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7091
7092                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7093                                (TG3_TX_RING_SIZE <<
7094                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7095                                NIC_SRAM_TX_BUFFER_DESC);
7096
7097                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7098                                (TG3_RX_RCB_RING_SIZE(tp) <<
7099                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7100
7101                 stblk += 8;
7102                 txrcb += TG3_BDINFO_SIZE;
7103                 rxrcb += TG3_BDINFO_SIZE;
7104         }
7105 }
7106
7107 /* tp->lock is held. */
7108 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7109 {
7110         u32 val, rdmac_mode;
7111         int i, err, limit;
7112         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7113
7114         tg3_disable_ints(tp);
7115
7116         tg3_stop_fw(tp);
7117
7118         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7119
7120         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7121                 tg3_abort_hw(tp, 1);
7122         }
7123
7124         if (reset_phy &&
7125             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7126                 tg3_phy_reset(tp);
7127
7128         err = tg3_chip_reset(tp);
7129         if (err)
7130                 return err;
7131
7132         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7133
7134         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7135                 val = tr32(TG3_CPMU_CTRL);
7136                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7137                 tw32(TG3_CPMU_CTRL, val);
7138
7139                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7140                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7141                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7142                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7143
7144                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7145                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7146                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7147                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7148
7149                 val = tr32(TG3_CPMU_HST_ACC);
7150                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7151                 val |= CPMU_HST_ACC_MACCLK_6_25;
7152                 tw32(TG3_CPMU_HST_ACC, val);
7153         }
7154
7155         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7156                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7157                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7158                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7159                 tw32(PCIE_PWR_MGMT_THRESH, val);
7160
7161                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7162                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7163
7164                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7165         }
7166
7167         if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
7168                 val = tr32(TG3_PCIE_LNKCTL);
7169                 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
7170                         val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7171                 else
7172                         val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7173                 tw32(TG3_PCIE_LNKCTL, val);
7174         }
7175
7176         /* This works around an issue with Athlon chipsets on
7177          * B3 tigon3 silicon.  This bit has no effect on any
7178          * other revision.  But do not set this on PCI Express
7179          * chips and don't even touch the clocks if the CPMU is present.
7180          */
7181         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7182                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7183                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7184                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7185         }
7186
7187         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7188             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7189                 val = tr32(TG3PCI_PCISTATE);
7190                 val |= PCISTATE_RETRY_SAME_DMA;
7191                 tw32(TG3PCI_PCISTATE, val);
7192         }
7193
7194         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7195                 /* Allow reads and writes to the
7196                  * APE register and memory space.
7197                  */
7198                 val = tr32(TG3PCI_PCISTATE);
7199                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7200                        PCISTATE_ALLOW_APE_SHMEM_WR;
7201                 tw32(TG3PCI_PCISTATE, val);
7202         }
7203
7204         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7205                 /* Enable some hw fixes.  */
7206                 val = tr32(TG3PCI_MSI_DATA);
7207                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7208                 tw32(TG3PCI_MSI_DATA, val);
7209         }
7210
7211         /* Descriptor ring init may make accesses to the
7212          * NIC SRAM area to setup the TX descriptors, so we
7213          * can only do this after the hardware has been
7214          * successfully reset.
7215          */
7216         err = tg3_init_rings(tp);
7217         if (err)
7218                 return err;
7219
7220         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7221             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7222             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
7223                 /* This value is determined during the probe time DMA
7224                  * engine test, tg3_test_dma.
7225                  */
7226                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7227         }
7228
7229         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7230                           GRC_MODE_4X_NIC_SEND_RINGS |
7231                           GRC_MODE_NO_TX_PHDR_CSUM |
7232                           GRC_MODE_NO_RX_PHDR_CSUM);
7233         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7234
7235         /* Pseudo-header checksum is done by hardware logic and not
7236          * the offload processers, so make the chip do the pseudo-
7237          * header checksums on receive.  For transmit it is more
7238          * convenient to do the pseudo-header checksum in software
7239          * as Linux does that on transmit for us in all cases.
7240          */
7241         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7242
7243         tw32(GRC_MODE,
7244              tp->grc_mode |
7245              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7246
7247         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7248         val = tr32(GRC_MISC_CFG);
7249         val &= ~0xff;
7250         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7251         tw32(GRC_MISC_CFG, val);
7252
7253         /* Initialize MBUF/DESC pool. */
7254         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7255                 /* Do nothing.  */
7256         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7257                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7258                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7259                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7260                 else
7261                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7262                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7263                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7264         }
7265         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7266                 int fw_len;
7267
7268                 fw_len = tp->fw_len;
7269                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7270                 tw32(BUFMGR_MB_POOL_ADDR,
7271                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7272                 tw32(BUFMGR_MB_POOL_SIZE,
7273                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7274         }
7275
7276         if (tp->dev->mtu <= ETH_DATA_LEN) {
7277                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7278                      tp->bufmgr_config.mbuf_read_dma_low_water);
7279                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7280                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7281                 tw32(BUFMGR_MB_HIGH_WATER,
7282                      tp->bufmgr_config.mbuf_high_water);
7283         } else {
7284                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7285                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7286                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7287                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7288                 tw32(BUFMGR_MB_HIGH_WATER,
7289                      tp->bufmgr_config.mbuf_high_water_jumbo);
7290         }
7291         tw32(BUFMGR_DMA_LOW_WATER,
7292              tp->bufmgr_config.dma_low_water);
7293         tw32(BUFMGR_DMA_HIGH_WATER,
7294              tp->bufmgr_config.dma_high_water);
7295
7296         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7297         for (i = 0; i < 2000; i++) {
7298                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7299                         break;
7300                 udelay(10);
7301         }
7302         if (i >= 2000) {
7303                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7304                        tp->dev->name);
7305                 return -ENODEV;
7306         }
7307
7308         /* Setup replenish threshold. */
7309         val = tp->rx_pending / 8;
7310         if (val == 0)
7311                 val = 1;
7312         else if (val > tp->rx_std_max_post)
7313                 val = tp->rx_std_max_post;
7314         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7315                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7316                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7317
7318                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7319                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7320         }
7321
7322         tw32(RCVBDI_STD_THRESH, val);
7323
7324         /* Initialize TG3_BDINFO's at:
7325          *  RCVDBDI_STD_BD:     standard eth size rx ring
7326          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7327          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7328          *
7329          * like so:
7330          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7331          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7332          *                              ring attribute flags
7333          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7334          *
7335          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7336          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7337          *
7338          * The size of each ring is fixed in the firmware, but the location is
7339          * configurable.
7340          */
7341         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7342              ((u64) tpr->rx_std_mapping >> 32));
7343         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7344              ((u64) tpr->rx_std_mapping & 0xffffffff));
7345         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7346              NIC_SRAM_RX_BUFFER_DESC);
7347
7348         /* Disable the mini ring */
7349         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7350                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7351                      BDINFO_FLAGS_DISABLED);
7352
7353         /* Program the jumbo buffer descriptor ring control
7354          * blocks on those devices that have them.
7355          */
7356         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7357             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7358                 /* Setup replenish threshold. */
7359                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7360
7361                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7362                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7363                              ((u64) tpr->rx_jmb_mapping >> 32));
7364                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7365                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7366                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7367                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7368                              BDINFO_FLAGS_USE_EXT_RECV);
7369                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7370                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7371                 } else {
7372                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7373                              BDINFO_FLAGS_DISABLED);
7374                 }
7375
7376                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7377                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7378                               (RX_STD_MAX_SIZE << 2);
7379                 else
7380                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7381         } else
7382                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7383
7384         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7385
7386         tpr->rx_std_ptr = tp->rx_pending;
7387         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7388                      tpr->rx_std_ptr);
7389
7390         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7391                           tp->rx_jumbo_pending : 0;
7392         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7393                      tpr->rx_jmb_ptr);
7394
7395         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7396                 tw32(STD_REPLENISH_LWM, 32);
7397                 tw32(JMB_REPLENISH_LWM, 16);
7398         }
7399
7400         tg3_rings_reset(tp);
7401
7402         /* Initialize MAC address and backoff seed. */
7403         __tg3_set_mac_addr(tp, 0);
7404
7405         /* MTU + ethernet header + FCS + optional VLAN tag */
7406         tw32(MAC_RX_MTU_SIZE,
7407              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7408
7409         /* The slot time is changed by tg3_setup_phy if we
7410          * run at gigabit with half duplex.
7411          */
7412         tw32(MAC_TX_LENGTHS,
7413              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7414              (6 << TX_LENGTHS_IPG_SHIFT) |
7415              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7416
7417         /* Receive rules. */
7418         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7419         tw32(RCVLPC_CONFIG, 0x0181);
7420
7421         /* Calculate RDMAC_MODE setting early, we need it to determine
7422          * the RCVLPC_STATE_ENABLE mask.
7423          */
7424         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7425                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7426                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7427                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7428                       RDMAC_MODE_LNGREAD_ENAB);
7429
7430         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7431             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7432             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7433                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7434                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7435                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7436
7437         /* If statement applies to 5705 and 5750 PCI devices only */
7438         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7439              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7440             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7441                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7442                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7443                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7444                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7445                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7446                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7447                 }
7448         }
7449
7450         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7451                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7452
7453         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7454                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7455
7456         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7457             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7458                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7459
7460         /* Receive/send statistics. */
7461         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7462                 val = tr32(RCVLPC_STATS_ENABLE);
7463                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7464                 tw32(RCVLPC_STATS_ENABLE, val);
7465         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7466                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7467                 val = tr32(RCVLPC_STATS_ENABLE);
7468                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7469                 tw32(RCVLPC_STATS_ENABLE, val);
7470         } else {
7471                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7472         }
7473         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7474         tw32(SNDDATAI_STATSENAB, 0xffffff);
7475         tw32(SNDDATAI_STATSCTRL,
7476              (SNDDATAI_SCTRL_ENABLE |
7477               SNDDATAI_SCTRL_FASTUPD));
7478
7479         /* Setup host coalescing engine. */
7480         tw32(HOSTCC_MODE, 0);
7481         for (i = 0; i < 2000; i++) {
7482                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7483                         break;
7484                 udelay(10);
7485         }
7486
7487         __tg3_set_coalesce(tp, &tp->coal);
7488
7489         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7490                 /* Status/statistics block address.  See tg3_timer,
7491                  * the tg3_periodic_fetch_stats call there, and
7492                  * tg3_get_stats to see how this works for 5705/5750 chips.
7493                  */
7494                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7495                      ((u64) tp->stats_mapping >> 32));
7496                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7497                      ((u64) tp->stats_mapping & 0xffffffff));
7498                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7499
7500                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7501
7502                 /* Clear statistics and status block memory areas */
7503                 for (i = NIC_SRAM_STATS_BLK;
7504                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7505                      i += sizeof(u32)) {
7506                         tg3_write_mem(tp, i, 0);
7507                         udelay(40);
7508                 }
7509         }
7510
7511         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7512
7513         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7514         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7515         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7516                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7517
7518         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7519                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7520                 /* reset to prevent losing 1st rx packet intermittently */
7521                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7522                 udelay(10);
7523         }
7524
7525         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7526                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7527         else
7528                 tp->mac_mode = 0;
7529         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7530                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7531         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7532             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7533             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7534                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7535         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7536         udelay(40);
7537
7538         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7539          * If TG3_FLG2_IS_NIC is zero, we should read the
7540          * register to preserve the GPIO settings for LOMs. The GPIOs,
7541          * whether used as inputs or outputs, are set by boot code after
7542          * reset.
7543          */
7544         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7545                 u32 gpio_mask;
7546
7547                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7548                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7549                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7550
7551                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7552                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7553                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7554
7555                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7556                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7557
7558                 tp->grc_local_ctrl &= ~gpio_mask;
7559                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7560
7561                 /* GPIO1 must be driven high for eeprom write protect */
7562                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7563                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7564                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7565         }
7566         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7567         udelay(100);
7568
7569         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7570                 val = tr32(MSGINT_MODE);
7571                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7572                 tw32(MSGINT_MODE, val);
7573         }
7574
7575         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7576                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7577                 udelay(40);
7578         }
7579
7580         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7581                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7582                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7583                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7584                WDMAC_MODE_LNGREAD_ENAB);
7585
7586         /* If statement applies to 5705 and 5750 PCI devices only */
7587         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7588              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7589             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7590                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7591                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7592                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7593                         /* nothing */
7594                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7595                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7596                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7597                         val |= WDMAC_MODE_RX_ACCEL;
7598                 }
7599         }
7600
7601         /* Enable host coalescing bug fix */
7602         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7603                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7604
7605         tw32_f(WDMAC_MODE, val);
7606         udelay(40);
7607
7608         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7609                 u16 pcix_cmd;
7610
7611                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7612                                      &pcix_cmd);
7613                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7614                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7615                         pcix_cmd |= PCI_X_CMD_READ_2K;
7616                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7617                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7618                         pcix_cmd |= PCI_X_CMD_READ_2K;
7619                 }
7620                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7621                                       pcix_cmd);
7622         }
7623
7624         tw32_f(RDMAC_MODE, rdmac_mode);
7625         udelay(40);
7626
7627         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7628         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7629                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7630
7631         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7632                 tw32(SNDDATAC_MODE,
7633                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7634         else
7635                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7636
7637         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7638         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7639         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7640         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7641         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7642                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7643         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7644         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7645                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7646         tw32(SNDBDI_MODE, val);
7647         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7648
7649         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7650                 err = tg3_load_5701_a0_firmware_fix(tp);
7651                 if (err)
7652                         return err;
7653         }
7654
7655         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7656                 err = tg3_load_tso_firmware(tp);
7657                 if (err)
7658                         return err;
7659         }
7660
7661         tp->tx_mode = TX_MODE_ENABLE;
7662         tw32_f(MAC_TX_MODE, tp->tx_mode);
7663         udelay(100);
7664
7665         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7666                 u32 reg = MAC_RSS_INDIR_TBL_0;
7667                 u8 *ent = (u8 *)&val;
7668
7669                 /* Setup the indirection table */
7670                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7671                         int idx = i % sizeof(val);
7672
7673                         ent[idx] = i % (tp->irq_cnt - 1);
7674                         if (idx == sizeof(val) - 1) {
7675                                 tw32(reg, val);
7676                                 reg += 4;
7677                         }
7678                 }
7679
7680                 /* Setup the "secret" hash key. */
7681                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7682                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7683                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7684                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7685                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7686                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7687                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7688                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7689                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7690                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7691         }
7692
7693         tp->rx_mode = RX_MODE_ENABLE;
7694         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7695                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7696
7697         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7698                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7699                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7700                                RX_MODE_RSS_IPV6_HASH_EN |
7701                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7702                                RX_MODE_RSS_IPV4_HASH_EN |
7703                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7704
7705         tw32_f(MAC_RX_MODE, tp->rx_mode);
7706         udelay(10);
7707
7708         tw32(MAC_LED_CTRL, tp->led_ctrl);
7709
7710         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7711         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7712                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7713                 udelay(10);
7714         }
7715         tw32_f(MAC_RX_MODE, tp->rx_mode);
7716         udelay(10);
7717
7718         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7719                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7720                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7721                         /* Set drive transmission level to 1.2V  */
7722                         /* only if the signal pre-emphasis bit is not set  */
7723                         val = tr32(MAC_SERDES_CFG);
7724                         val &= 0xfffff000;
7725                         val |= 0x880;
7726                         tw32(MAC_SERDES_CFG, val);
7727                 }
7728                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7729                         tw32(MAC_SERDES_CFG, 0x616000);
7730         }
7731
7732         /* Prevent chip from dropping frames when flow control
7733          * is enabled.
7734          */
7735         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7736
7737         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7738             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7739                 /* Use hardware link auto-negotiation */
7740                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7741         }
7742
7743         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7744             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7745                 u32 tmp;
7746
7747                 tmp = tr32(SERDES_RX_CTRL);
7748                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7749                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7750                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7751                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7752         }
7753
7754         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7755                 if (tp->link_config.phy_is_low_power) {
7756                         tp->link_config.phy_is_low_power = 0;
7757                         tp->link_config.speed = tp->link_config.orig_speed;
7758                         tp->link_config.duplex = tp->link_config.orig_duplex;
7759                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7760                 }
7761
7762                 err = tg3_setup_phy(tp, 0);
7763                 if (err)
7764                         return err;
7765
7766                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7767                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7768                         u32 tmp;
7769
7770                         /* Clear CRC stats. */
7771                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7772                                 tg3_writephy(tp, MII_TG3_TEST1,
7773                                              tmp | MII_TG3_TEST1_CRC_EN);
7774                                 tg3_readphy(tp, 0x14, &tmp);
7775                         }
7776                 }
7777         }
7778
7779         __tg3_set_rx_mode(tp->dev);
7780
7781         /* Initialize receive rules. */
7782         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7783         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7784         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7785         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7786
7787         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7788             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7789                 limit = 8;
7790         else
7791                 limit = 16;
7792         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7793                 limit -= 4;
7794         switch (limit) {
7795         case 16:
7796                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7797         case 15:
7798                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7799         case 14:
7800                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7801         case 13:
7802                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7803         case 12:
7804                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7805         case 11:
7806                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7807         case 10:
7808                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7809         case 9:
7810                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7811         case 8:
7812                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7813         case 7:
7814                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7815         case 6:
7816                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7817         case 5:
7818                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7819         case 4:
7820                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7821         case 3:
7822                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7823         case 2:
7824         case 1:
7825
7826         default:
7827                 break;
7828         }
7829
7830         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7831                 /* Write our heartbeat update interval to APE. */
7832                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7833                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7834
7835         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7836
7837         return 0;
7838 }
7839
7840 /* Called at device open time to get the chip ready for
7841  * packet processing.  Invoked with tp->lock held.
7842  */
7843 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7844 {
7845         tg3_switch_clocks(tp);
7846
7847         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7848
7849         return tg3_reset_hw(tp, reset_phy);
7850 }
7851
7852 #define TG3_STAT_ADD32(PSTAT, REG) \
7853 do {    u32 __val = tr32(REG); \
7854         (PSTAT)->low += __val; \
7855         if ((PSTAT)->low < __val) \
7856                 (PSTAT)->high += 1; \
7857 } while (0)
7858
7859 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7860 {
7861         struct tg3_hw_stats *sp = tp->hw_stats;
7862
7863         if (!netif_carrier_ok(tp->dev))
7864                 return;
7865
7866         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7867         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7868         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7869         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7870         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7871         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7872         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7873         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7874         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7875         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7876         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7877         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7878         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7879
7880         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7881         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7882         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7883         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7884         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7885         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7886         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7887         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7888         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7889         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7890         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7891         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7892         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7893         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7894
7895         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7896         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7897         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7898 }
7899
7900 static void tg3_timer(unsigned long __opaque)
7901 {
7902         struct tg3 *tp = (struct tg3 *) __opaque;
7903
7904         if (tp->irq_sync)
7905                 goto restart_timer;
7906
7907         spin_lock(&tp->lock);
7908
7909         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7910                 /* All of this garbage is because when using non-tagged
7911                  * IRQ status the mailbox/status_block protocol the chip
7912                  * uses with the cpu is race prone.
7913                  */
7914                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7915                         tw32(GRC_LOCAL_CTRL,
7916                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7917                 } else {
7918                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7919                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7920                 }
7921
7922                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7923                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7924                         spin_unlock(&tp->lock);
7925                         schedule_work(&tp->reset_task);
7926                         return;
7927                 }
7928         }
7929
7930         /* This part only runs once per second. */
7931         if (!--tp->timer_counter) {
7932                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7933                         tg3_periodic_fetch_stats(tp);
7934
7935                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7936                         u32 mac_stat;
7937                         int phy_event;
7938
7939                         mac_stat = tr32(MAC_STATUS);
7940
7941                         phy_event = 0;
7942                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7943                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7944                                         phy_event = 1;
7945                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7946                                 phy_event = 1;
7947
7948                         if (phy_event)
7949                                 tg3_setup_phy(tp, 0);
7950                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7951                         u32 mac_stat = tr32(MAC_STATUS);
7952                         int need_setup = 0;
7953
7954                         if (netif_carrier_ok(tp->dev) &&
7955                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7956                                 need_setup = 1;
7957                         }
7958                         if (! netif_carrier_ok(tp->dev) &&
7959                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7960                                          MAC_STATUS_SIGNAL_DET))) {
7961                                 need_setup = 1;
7962                         }
7963                         if (need_setup) {
7964                                 if (!tp->serdes_counter) {
7965                                         tw32_f(MAC_MODE,
7966                                              (tp->mac_mode &
7967                                               ~MAC_MODE_PORT_MODE_MASK));
7968                                         udelay(40);
7969                                         tw32_f(MAC_MODE, tp->mac_mode);
7970                                         udelay(40);
7971                                 }
7972                                 tg3_setup_phy(tp, 0);
7973                         }
7974                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7975                         tg3_serdes_parallel_detect(tp);
7976
7977                 tp->timer_counter = tp->timer_multiplier;
7978         }
7979
7980         /* Heartbeat is only sent once every 2 seconds.
7981          *
7982          * The heartbeat is to tell the ASF firmware that the host
7983          * driver is still alive.  In the event that the OS crashes,
7984          * ASF needs to reset the hardware to free up the FIFO space
7985          * that may be filled with rx packets destined for the host.
7986          * If the FIFO is full, ASF will no longer function properly.
7987          *
7988          * Unintended resets have been reported on real time kernels
7989          * where the timer doesn't run on time.  Netpoll will also have
7990          * same problem.
7991          *
7992          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7993          * to check the ring condition when the heartbeat is expiring
7994          * before doing the reset.  This will prevent most unintended
7995          * resets.
7996          */
7997         if (!--tp->asf_counter) {
7998                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7999                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8000                         tg3_wait_for_event_ack(tp);
8001
8002                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8003                                       FWCMD_NICDRV_ALIVE3);
8004                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8005                         /* 5 seconds timeout */
8006                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8007
8008                         tg3_generate_fw_event(tp);
8009                 }
8010                 tp->asf_counter = tp->asf_multiplier;
8011         }
8012
8013         spin_unlock(&tp->lock);
8014
8015 restart_timer:
8016         tp->timer.expires = jiffies + tp->timer_offset;
8017         add_timer(&tp->timer);
8018 }
8019
8020 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8021 {
8022         irq_handler_t fn;
8023         unsigned long flags;
8024         char *name;
8025         struct tg3_napi *tnapi = &tp->napi[irq_num];
8026
8027         if (tp->irq_cnt == 1)
8028                 name = tp->dev->name;
8029         else {
8030                 name = &tnapi->irq_lbl[0];
8031                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8032                 name[IFNAMSIZ-1] = 0;
8033         }
8034
8035         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8036                 fn = tg3_msi;
8037                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8038                         fn = tg3_msi_1shot;
8039                 flags = IRQF_SAMPLE_RANDOM;
8040         } else {
8041                 fn = tg3_interrupt;
8042                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8043                         fn = tg3_interrupt_tagged;
8044                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8045         }
8046
8047         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8048 }
8049
8050 static int tg3_test_interrupt(struct tg3 *tp)
8051 {
8052         struct tg3_napi *tnapi = &tp->napi[0];
8053         struct net_device *dev = tp->dev;
8054         int err, i, intr_ok = 0;
8055         u32 val;
8056
8057         if (!netif_running(dev))
8058                 return -ENODEV;
8059
8060         tg3_disable_ints(tp);
8061
8062         free_irq(tnapi->irq_vec, tnapi);
8063
8064         /*
8065          * Turn off MSI one shot mode.  Otherwise this test has no
8066          * observable way to know whether the interrupt was delivered.
8067          */
8068         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8069             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8070                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8071                 tw32(MSGINT_MODE, val);
8072         }
8073
8074         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8075                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8076         if (err)
8077                 return err;
8078
8079         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8080         tg3_enable_ints(tp);
8081
8082         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8083                tnapi->coal_now);
8084
8085         for (i = 0; i < 5; i++) {
8086                 u32 int_mbox, misc_host_ctrl;
8087
8088                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8089                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8090
8091                 if ((int_mbox != 0) ||
8092                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8093                         intr_ok = 1;
8094                         break;
8095                 }
8096
8097                 msleep(10);
8098         }
8099
8100         tg3_disable_ints(tp);
8101
8102         free_irq(tnapi->irq_vec, tnapi);
8103
8104         err = tg3_request_irq(tp, 0);
8105
8106         if (err)
8107                 return err;
8108
8109         if (intr_ok) {
8110                 /* Reenable MSI one shot mode. */
8111                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8112                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8113                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8114                         tw32(MSGINT_MODE, val);
8115                 }
8116                 return 0;
8117         }
8118
8119         return -EIO;
8120 }
8121
8122 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8123  * successfully restored
8124  */
8125 static int tg3_test_msi(struct tg3 *tp)
8126 {
8127         int err;
8128         u16 pci_cmd;
8129
8130         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8131                 return 0;
8132
8133         /* Turn off SERR reporting in case MSI terminates with Master
8134          * Abort.
8135          */
8136         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8137         pci_write_config_word(tp->pdev, PCI_COMMAND,
8138                               pci_cmd & ~PCI_COMMAND_SERR);
8139
8140         err = tg3_test_interrupt(tp);
8141
8142         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8143
8144         if (!err)
8145                 return 0;
8146
8147         /* other failures */
8148         if (err != -EIO)
8149                 return err;
8150
8151         /* MSI test failed, go back to INTx mode */
8152         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8153                "switching to INTx mode. Please report this failure to "
8154                "the PCI maintainer and include system chipset information.\n",
8155                        tp->dev->name);
8156
8157         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8158
8159         pci_disable_msi(tp->pdev);
8160
8161         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8162
8163         err = tg3_request_irq(tp, 0);
8164         if (err)
8165                 return err;
8166
8167         /* Need to reset the chip because the MSI cycle may have terminated
8168          * with Master Abort.
8169          */
8170         tg3_full_lock(tp, 1);
8171
8172         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8173         err = tg3_init_hw(tp, 1);
8174
8175         tg3_full_unlock(tp);
8176
8177         if (err)
8178                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8179
8180         return err;
8181 }
8182
8183 static int tg3_request_firmware(struct tg3 *tp)
8184 {
8185         const __be32 *fw_data;
8186
8187         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8188                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8189                        tp->dev->name, tp->fw_needed);
8190                 return -ENOENT;
8191         }
8192
8193         fw_data = (void *)tp->fw->data;
8194
8195         /* Firmware blob starts with version numbers, followed by
8196          * start address and _full_ length including BSS sections
8197          * (which must be longer than the actual data, of course
8198          */
8199
8200         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8201         if (tp->fw_len < (tp->fw->size - 12)) {
8202                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8203                        tp->dev->name, tp->fw_len, tp->fw_needed);
8204                 release_firmware(tp->fw);
8205                 tp->fw = NULL;
8206                 return -EINVAL;
8207         }
8208
8209         /* We no longer need firmware; we have it. */
8210         tp->fw_needed = NULL;
8211         return 0;
8212 }
8213
8214 static bool tg3_enable_msix(struct tg3 *tp)
8215 {
8216         int i, rc, cpus = num_online_cpus();
8217         struct msix_entry msix_ent[tp->irq_max];
8218
8219         if (cpus == 1)
8220                 /* Just fallback to the simpler MSI mode. */
8221                 return false;
8222
8223         /*
8224          * We want as many rx rings enabled as there are cpus.
8225          * The first MSIX vector only deals with link interrupts, etc,
8226          * so we add one to the number of vectors we are requesting.
8227          */
8228         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8229
8230         for (i = 0; i < tp->irq_max; i++) {
8231                 msix_ent[i].entry  = i;
8232                 msix_ent[i].vector = 0;
8233         }
8234
8235         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8236         if (rc != 0) {
8237                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8238                         return false;
8239                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8240                         return false;
8241                 printk(KERN_NOTICE
8242                        "%s: Requested %d MSI-X vectors, received %d\n",
8243                        tp->dev->name, tp->irq_cnt, rc);
8244                 tp->irq_cnt = rc;
8245         }
8246
8247         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8248
8249         for (i = 0; i < tp->irq_max; i++)
8250                 tp->napi[i].irq_vec = msix_ent[i].vector;
8251
8252         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8253
8254         return true;
8255 }
8256
8257 static void tg3_ints_init(struct tg3 *tp)
8258 {
8259         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8260             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8261                 /* All MSI supporting chips should support tagged
8262                  * status.  Assert that this is the case.
8263                  */
8264                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8265                        "Not using MSI.\n", tp->dev->name);
8266                 goto defcfg;
8267         }
8268
8269         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8270                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8271         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8272                  pci_enable_msi(tp->pdev) == 0)
8273                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8274
8275         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8276                 u32 msi_mode = tr32(MSGINT_MODE);
8277                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8278                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8279                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8280         }
8281 defcfg:
8282         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8283                 tp->irq_cnt = 1;
8284                 tp->napi[0].irq_vec = tp->pdev->irq;
8285                 tp->dev->real_num_tx_queues = 1;
8286         }
8287 }
8288
8289 static void tg3_ints_fini(struct tg3 *tp)
8290 {
8291         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8292                 pci_disable_msix(tp->pdev);
8293         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8294                 pci_disable_msi(tp->pdev);
8295         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8296         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8297 }
8298
8299 static int tg3_open(struct net_device *dev)
8300 {
8301         struct tg3 *tp = netdev_priv(dev);
8302         int i, err;
8303
8304         if (tp->fw_needed) {
8305                 err = tg3_request_firmware(tp);
8306                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8307                         if (err)
8308                                 return err;
8309                 } else if (err) {
8310                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8311                                tp->dev->name);
8312                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8313                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8314                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8315                                tp->dev->name);
8316                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8317                 }
8318         }
8319
8320         netif_carrier_off(tp->dev);
8321
8322         err = tg3_set_power_state(tp, PCI_D0);
8323         if (err)
8324                 return err;
8325
8326         tg3_full_lock(tp, 0);
8327
8328         tg3_disable_ints(tp);
8329         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8330
8331         tg3_full_unlock(tp);
8332
8333         /*
8334          * Setup interrupts first so we know how
8335          * many NAPI resources to allocate
8336          */
8337         tg3_ints_init(tp);
8338
8339         /* The placement of this call is tied
8340          * to the setup and use of Host TX descriptors.
8341          */
8342         err = tg3_alloc_consistent(tp);
8343         if (err)
8344                 goto err_out1;
8345
8346         tg3_napi_enable(tp);
8347
8348         for (i = 0; i < tp->irq_cnt; i++) {
8349                 struct tg3_napi *tnapi = &tp->napi[i];
8350                 err = tg3_request_irq(tp, i);
8351                 if (err) {
8352                         for (i--; i >= 0; i--)
8353                                 free_irq(tnapi->irq_vec, tnapi);
8354                         break;
8355                 }
8356         }
8357
8358         if (err)
8359                 goto err_out2;
8360
8361         tg3_full_lock(tp, 0);
8362
8363         err = tg3_init_hw(tp, 1);
8364         if (err) {
8365                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8366                 tg3_free_rings(tp);
8367         } else {
8368                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8369                         tp->timer_offset = HZ;
8370                 else
8371                         tp->timer_offset = HZ / 10;
8372
8373                 BUG_ON(tp->timer_offset > HZ);
8374                 tp->timer_counter = tp->timer_multiplier =
8375                         (HZ / tp->timer_offset);
8376                 tp->asf_counter = tp->asf_multiplier =
8377                         ((HZ / tp->timer_offset) * 2);
8378
8379                 init_timer(&tp->timer);
8380                 tp->timer.expires = jiffies + tp->timer_offset;
8381                 tp->timer.data = (unsigned long) tp;
8382                 tp->timer.function = tg3_timer;
8383         }
8384
8385         tg3_full_unlock(tp);
8386
8387         if (err)
8388                 goto err_out3;
8389
8390         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8391                 err = tg3_test_msi(tp);
8392
8393                 if (err) {
8394                         tg3_full_lock(tp, 0);
8395                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8396                         tg3_free_rings(tp);
8397                         tg3_full_unlock(tp);
8398
8399                         goto err_out2;
8400                 }
8401
8402                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8403                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8404                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8405                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8406
8407                         tw32(PCIE_TRANSACTION_CFG,
8408                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8409                 }
8410         }
8411
8412         tg3_phy_start(tp);
8413
8414         tg3_full_lock(tp, 0);
8415
8416         add_timer(&tp->timer);
8417         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8418         tg3_enable_ints(tp);
8419
8420         tg3_full_unlock(tp);
8421
8422         netif_tx_start_all_queues(dev);
8423
8424         return 0;
8425
8426 err_out3:
8427         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8428                 struct tg3_napi *tnapi = &tp->napi[i];
8429                 free_irq(tnapi->irq_vec, tnapi);
8430         }
8431
8432 err_out2:
8433         tg3_napi_disable(tp);
8434         tg3_free_consistent(tp);
8435
8436 err_out1:
8437         tg3_ints_fini(tp);
8438         return err;
8439 }
8440
8441 #if 0
8442 /*static*/ void tg3_dump_state(struct tg3 *tp)
8443 {
8444         u32 val32, val32_2, val32_3, val32_4, val32_5;
8445         u16 val16;
8446         int i;
8447         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8448
8449         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8450         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8451         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8452                val16, val32);
8453
8454         /* MAC block */
8455         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8456                tr32(MAC_MODE), tr32(MAC_STATUS));
8457         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8458                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8459         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8460                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8461         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8462                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8463
8464         /* Send data initiator control block */
8465         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8466                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8467         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8468                tr32(SNDDATAI_STATSCTRL));
8469
8470         /* Send data completion control block */
8471         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8472
8473         /* Send BD ring selector block */
8474         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8475                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8476
8477         /* Send BD initiator control block */
8478         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8479                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8480
8481         /* Send BD completion control block */
8482         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8483
8484         /* Receive list placement control block */
8485         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8486                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8487         printk("       RCVLPC_STATSCTRL[%08x]\n",
8488                tr32(RCVLPC_STATSCTRL));
8489
8490         /* Receive data and receive BD initiator control block */
8491         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8492                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8493
8494         /* Receive data completion control block */
8495         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8496                tr32(RCVDCC_MODE));
8497
8498         /* Receive BD initiator control block */
8499         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8500                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8501
8502         /* Receive BD completion control block */
8503         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8504                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8505
8506         /* Receive list selector control block */
8507         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8508                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8509
8510         /* Mbuf cluster free block */
8511         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8512                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8513
8514         /* Host coalescing control block */
8515         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8516                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8517         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8518                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8519                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8520         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8521                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8522                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8523         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8524                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8525         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8526                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8527
8528         /* Memory arbiter control block */
8529         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8530                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8531
8532         /* Buffer manager control block */
8533         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8534                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8535         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8536                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8537         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8538                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8539                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8540                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8541
8542         /* Read DMA control block */
8543         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8544                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8545
8546         /* Write DMA control block */
8547         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8548                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8549
8550         /* DMA completion block */
8551         printk("DEBUG: DMAC_MODE[%08x]\n",
8552                tr32(DMAC_MODE));
8553
8554         /* GRC block */
8555         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8556                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8557         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8558                tr32(GRC_LOCAL_CTRL));
8559
8560         /* TG3_BDINFOs */
8561         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8562                tr32(RCVDBDI_JUMBO_BD + 0x0),
8563                tr32(RCVDBDI_JUMBO_BD + 0x4),
8564                tr32(RCVDBDI_JUMBO_BD + 0x8),
8565                tr32(RCVDBDI_JUMBO_BD + 0xc));
8566         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8567                tr32(RCVDBDI_STD_BD + 0x0),
8568                tr32(RCVDBDI_STD_BD + 0x4),
8569                tr32(RCVDBDI_STD_BD + 0x8),
8570                tr32(RCVDBDI_STD_BD + 0xc));
8571         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8572                tr32(RCVDBDI_MINI_BD + 0x0),
8573                tr32(RCVDBDI_MINI_BD + 0x4),
8574                tr32(RCVDBDI_MINI_BD + 0x8),
8575                tr32(RCVDBDI_MINI_BD + 0xc));
8576
8577         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8578         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8579         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8580         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8581         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8582                val32, val32_2, val32_3, val32_4);
8583
8584         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8585         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8586         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8587         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8588         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8589                val32, val32_2, val32_3, val32_4);
8590
8591         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8592         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8593         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8594         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8595         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8596         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8597                val32, val32_2, val32_3, val32_4, val32_5);
8598
8599         /* SW status block */
8600         printk(KERN_DEBUG
8601          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8602                sblk->status,
8603                sblk->status_tag,
8604                sblk->rx_jumbo_consumer,
8605                sblk->rx_consumer,
8606                sblk->rx_mini_consumer,
8607                sblk->idx[0].rx_producer,
8608                sblk->idx[0].tx_consumer);
8609
8610         /* SW statistics block */
8611         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8612                ((u32 *)tp->hw_stats)[0],
8613                ((u32 *)tp->hw_stats)[1],
8614                ((u32 *)tp->hw_stats)[2],
8615                ((u32 *)tp->hw_stats)[3]);
8616
8617         /* Mailboxes */
8618         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8619                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8620                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8621                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8622                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8623
8624         /* NIC side send descriptors. */
8625         for (i = 0; i < 6; i++) {
8626                 unsigned long txd;
8627
8628                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8629                         + (i * sizeof(struct tg3_tx_buffer_desc));
8630                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8631                        i,
8632                        readl(txd + 0x0), readl(txd + 0x4),
8633                        readl(txd + 0x8), readl(txd + 0xc));
8634         }
8635
8636         /* NIC side RX descriptors. */
8637         for (i = 0; i < 6; i++) {
8638                 unsigned long rxd;
8639
8640                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8641                         + (i * sizeof(struct tg3_rx_buffer_desc));
8642                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8643                        i,
8644                        readl(rxd + 0x0), readl(rxd + 0x4),
8645                        readl(rxd + 0x8), readl(rxd + 0xc));
8646                 rxd += (4 * sizeof(u32));
8647                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8648                        i,
8649                        readl(rxd + 0x0), readl(rxd + 0x4),
8650                        readl(rxd + 0x8), readl(rxd + 0xc));
8651         }
8652
8653         for (i = 0; i < 6; i++) {
8654                 unsigned long rxd;
8655
8656                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8657                         + (i * sizeof(struct tg3_rx_buffer_desc));
8658                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8659                        i,
8660                        readl(rxd + 0x0), readl(rxd + 0x4),
8661                        readl(rxd + 0x8), readl(rxd + 0xc));
8662                 rxd += (4 * sizeof(u32));
8663                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8664                        i,
8665                        readl(rxd + 0x0), readl(rxd + 0x4),
8666                        readl(rxd + 0x8), readl(rxd + 0xc));
8667         }
8668 }
8669 #endif
8670
8671 static struct net_device_stats *tg3_get_stats(struct net_device *);
8672 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8673
8674 static int tg3_close(struct net_device *dev)
8675 {
8676         int i;
8677         struct tg3 *tp = netdev_priv(dev);
8678
8679         tg3_napi_disable(tp);
8680         cancel_work_sync(&tp->reset_task);
8681
8682         netif_tx_stop_all_queues(dev);
8683
8684         del_timer_sync(&tp->timer);
8685
8686         tg3_full_lock(tp, 1);
8687 #if 0
8688         tg3_dump_state(tp);
8689 #endif
8690
8691         tg3_disable_ints(tp);
8692
8693         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8694         tg3_free_rings(tp);
8695         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8696
8697         tg3_full_unlock(tp);
8698
8699         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8700                 struct tg3_napi *tnapi = &tp->napi[i];
8701                 free_irq(tnapi->irq_vec, tnapi);
8702         }
8703
8704         tg3_ints_fini(tp);
8705
8706         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8707                sizeof(tp->net_stats_prev));
8708         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8709                sizeof(tp->estats_prev));
8710
8711         tg3_free_consistent(tp);
8712
8713         tg3_set_power_state(tp, PCI_D3hot);
8714
8715         netif_carrier_off(tp->dev);
8716
8717         return 0;
8718 }
8719
8720 static inline unsigned long get_stat64(tg3_stat64_t *val)
8721 {
8722         unsigned long ret;
8723
8724 #if (BITS_PER_LONG == 32)
8725         ret = val->low;
8726 #else
8727         ret = ((u64)val->high << 32) | ((u64)val->low);
8728 #endif
8729         return ret;
8730 }
8731
8732 static inline u64 get_estat64(tg3_stat64_t *val)
8733 {
8734        return ((u64)val->high << 32) | ((u64)val->low);
8735 }
8736
8737 static unsigned long calc_crc_errors(struct tg3 *tp)
8738 {
8739         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8740
8741         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8742             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8743              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8744                 u32 val;
8745
8746                 spin_lock_bh(&tp->lock);
8747                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8748                         tg3_writephy(tp, MII_TG3_TEST1,
8749                                      val | MII_TG3_TEST1_CRC_EN);
8750                         tg3_readphy(tp, 0x14, &val);
8751                 } else
8752                         val = 0;
8753                 spin_unlock_bh(&tp->lock);
8754
8755                 tp->phy_crc_errors += val;
8756
8757                 return tp->phy_crc_errors;
8758         }
8759
8760         return get_stat64(&hw_stats->rx_fcs_errors);
8761 }
8762
8763 #define ESTAT_ADD(member) \
8764         estats->member =        old_estats->member + \
8765                                 get_estat64(&hw_stats->member)
8766
8767 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8768 {
8769         struct tg3_ethtool_stats *estats = &tp->estats;
8770         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8771         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8772
8773         if (!hw_stats)
8774                 return old_estats;
8775
8776         ESTAT_ADD(rx_octets);
8777         ESTAT_ADD(rx_fragments);
8778         ESTAT_ADD(rx_ucast_packets);
8779         ESTAT_ADD(rx_mcast_packets);
8780         ESTAT_ADD(rx_bcast_packets);
8781         ESTAT_ADD(rx_fcs_errors);
8782         ESTAT_ADD(rx_align_errors);
8783         ESTAT_ADD(rx_xon_pause_rcvd);
8784         ESTAT_ADD(rx_xoff_pause_rcvd);
8785         ESTAT_ADD(rx_mac_ctrl_rcvd);
8786         ESTAT_ADD(rx_xoff_entered);
8787         ESTAT_ADD(rx_frame_too_long_errors);
8788         ESTAT_ADD(rx_jabbers);
8789         ESTAT_ADD(rx_undersize_packets);
8790         ESTAT_ADD(rx_in_length_errors);
8791         ESTAT_ADD(rx_out_length_errors);
8792         ESTAT_ADD(rx_64_or_less_octet_packets);
8793         ESTAT_ADD(rx_65_to_127_octet_packets);
8794         ESTAT_ADD(rx_128_to_255_octet_packets);
8795         ESTAT_ADD(rx_256_to_511_octet_packets);
8796         ESTAT_ADD(rx_512_to_1023_octet_packets);
8797         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8798         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8799         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8800         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8801         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8802
8803         ESTAT_ADD(tx_octets);
8804         ESTAT_ADD(tx_collisions);
8805         ESTAT_ADD(tx_xon_sent);
8806         ESTAT_ADD(tx_xoff_sent);
8807         ESTAT_ADD(tx_flow_control);
8808         ESTAT_ADD(tx_mac_errors);
8809         ESTAT_ADD(tx_single_collisions);
8810         ESTAT_ADD(tx_mult_collisions);
8811         ESTAT_ADD(tx_deferred);
8812         ESTAT_ADD(tx_excessive_collisions);
8813         ESTAT_ADD(tx_late_collisions);
8814         ESTAT_ADD(tx_collide_2times);
8815         ESTAT_ADD(tx_collide_3times);
8816         ESTAT_ADD(tx_collide_4times);
8817         ESTAT_ADD(tx_collide_5times);
8818         ESTAT_ADD(tx_collide_6times);
8819         ESTAT_ADD(tx_collide_7times);
8820         ESTAT_ADD(tx_collide_8times);
8821         ESTAT_ADD(tx_collide_9times);
8822         ESTAT_ADD(tx_collide_10times);
8823         ESTAT_ADD(tx_collide_11times);
8824         ESTAT_ADD(tx_collide_12times);
8825         ESTAT_ADD(tx_collide_13times);
8826         ESTAT_ADD(tx_collide_14times);
8827         ESTAT_ADD(tx_collide_15times);
8828         ESTAT_ADD(tx_ucast_packets);
8829         ESTAT_ADD(tx_mcast_packets);
8830         ESTAT_ADD(tx_bcast_packets);
8831         ESTAT_ADD(tx_carrier_sense_errors);
8832         ESTAT_ADD(tx_discards);
8833         ESTAT_ADD(tx_errors);
8834
8835         ESTAT_ADD(dma_writeq_full);
8836         ESTAT_ADD(dma_write_prioq_full);
8837         ESTAT_ADD(rxbds_empty);
8838         ESTAT_ADD(rx_discards);
8839         ESTAT_ADD(rx_errors);
8840         ESTAT_ADD(rx_threshold_hit);
8841
8842         ESTAT_ADD(dma_readq_full);
8843         ESTAT_ADD(dma_read_prioq_full);
8844         ESTAT_ADD(tx_comp_queue_full);
8845
8846         ESTAT_ADD(ring_set_send_prod_index);
8847         ESTAT_ADD(ring_status_update);
8848         ESTAT_ADD(nic_irqs);
8849         ESTAT_ADD(nic_avoided_irqs);
8850         ESTAT_ADD(nic_tx_threshold_hit);
8851
8852         return estats;
8853 }
8854
8855 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8856 {
8857         struct tg3 *tp = netdev_priv(dev);
8858         struct net_device_stats *stats = &tp->net_stats;
8859         struct net_device_stats *old_stats = &tp->net_stats_prev;
8860         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8861
8862         if (!hw_stats)
8863                 return old_stats;
8864
8865         stats->rx_packets = old_stats->rx_packets +
8866                 get_stat64(&hw_stats->rx_ucast_packets) +
8867                 get_stat64(&hw_stats->rx_mcast_packets) +
8868                 get_stat64(&hw_stats->rx_bcast_packets);
8869
8870         stats->tx_packets = old_stats->tx_packets +
8871                 get_stat64(&hw_stats->tx_ucast_packets) +
8872                 get_stat64(&hw_stats->tx_mcast_packets) +
8873                 get_stat64(&hw_stats->tx_bcast_packets);
8874
8875         stats->rx_bytes = old_stats->rx_bytes +
8876                 get_stat64(&hw_stats->rx_octets);
8877         stats->tx_bytes = old_stats->tx_bytes +
8878                 get_stat64(&hw_stats->tx_octets);
8879
8880         stats->rx_errors = old_stats->rx_errors +
8881                 get_stat64(&hw_stats->rx_errors);
8882         stats->tx_errors = old_stats->tx_errors +
8883                 get_stat64(&hw_stats->tx_errors) +
8884                 get_stat64(&hw_stats->tx_mac_errors) +
8885                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8886                 get_stat64(&hw_stats->tx_discards);
8887
8888         stats->multicast = old_stats->multicast +
8889                 get_stat64(&hw_stats->rx_mcast_packets);
8890         stats->collisions = old_stats->collisions +
8891                 get_stat64(&hw_stats->tx_collisions);
8892
8893         stats->rx_length_errors = old_stats->rx_length_errors +
8894                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8895                 get_stat64(&hw_stats->rx_undersize_packets);
8896
8897         stats->rx_over_errors = old_stats->rx_over_errors +
8898                 get_stat64(&hw_stats->rxbds_empty);
8899         stats->rx_frame_errors = old_stats->rx_frame_errors +
8900                 get_stat64(&hw_stats->rx_align_errors);
8901         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8902                 get_stat64(&hw_stats->tx_discards);
8903         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8904                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8905
8906         stats->rx_crc_errors = old_stats->rx_crc_errors +
8907                 calc_crc_errors(tp);
8908
8909         stats->rx_missed_errors = old_stats->rx_missed_errors +
8910                 get_stat64(&hw_stats->rx_discards);
8911
8912         return stats;
8913 }
8914
8915 static inline u32 calc_crc(unsigned char *buf, int len)
8916 {
8917         u32 reg;
8918         u32 tmp;
8919         int j, k;
8920
8921         reg = 0xffffffff;
8922
8923         for (j = 0; j < len; j++) {
8924                 reg ^= buf[j];
8925
8926                 for (k = 0; k < 8; k++) {
8927                         tmp = reg & 0x01;
8928
8929                         reg >>= 1;
8930
8931                         if (tmp) {
8932                                 reg ^= 0xedb88320;
8933                         }
8934                 }
8935         }
8936
8937         return ~reg;
8938 }
8939
8940 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8941 {
8942         /* accept or reject all multicast frames */
8943         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8944         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8945         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8946         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8947 }
8948
8949 static void __tg3_set_rx_mode(struct net_device *dev)
8950 {
8951         struct tg3 *tp = netdev_priv(dev);
8952         u32 rx_mode;
8953
8954         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8955                                   RX_MODE_KEEP_VLAN_TAG);
8956
8957         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8958          * flag clear.
8959          */
8960 #if TG3_VLAN_TAG_USED
8961         if (!tp->vlgrp &&
8962             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8963                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8964 #else
8965         /* By definition, VLAN is disabled always in this
8966          * case.
8967          */
8968         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8969                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8970 #endif
8971
8972         if (dev->flags & IFF_PROMISC) {
8973                 /* Promiscuous mode. */
8974                 rx_mode |= RX_MODE_PROMISC;
8975         } else if (dev->flags & IFF_ALLMULTI) {
8976                 /* Accept all multicast. */
8977                 tg3_set_multi (tp, 1);
8978         } else if (dev->mc_count < 1) {
8979                 /* Reject all multicast. */
8980                 tg3_set_multi (tp, 0);
8981         } else {
8982                 /* Accept one or more multicast(s). */
8983                 struct dev_mc_list *mclist;
8984                 unsigned int i;
8985                 u32 mc_filter[4] = { 0, };
8986                 u32 regidx;
8987                 u32 bit;
8988                 u32 crc;
8989
8990                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8991                      i++, mclist = mclist->next) {
8992
8993                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8994                         bit = ~crc & 0x7f;
8995                         regidx = (bit & 0x60) >> 5;
8996                         bit &= 0x1f;
8997                         mc_filter[regidx] |= (1 << bit);
8998                 }
8999
9000                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9001                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9002                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9003                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9004         }
9005
9006         if (rx_mode != tp->rx_mode) {
9007                 tp->rx_mode = rx_mode;
9008                 tw32_f(MAC_RX_MODE, rx_mode);
9009                 udelay(10);
9010         }
9011 }
9012
9013 static void tg3_set_rx_mode(struct net_device *dev)
9014 {
9015         struct tg3 *tp = netdev_priv(dev);
9016
9017         if (!netif_running(dev))
9018                 return;
9019
9020         tg3_full_lock(tp, 0);
9021         __tg3_set_rx_mode(dev);
9022         tg3_full_unlock(tp);
9023 }
9024
9025 #define TG3_REGDUMP_LEN         (32 * 1024)
9026
9027 static int tg3_get_regs_len(struct net_device *dev)
9028 {
9029         return TG3_REGDUMP_LEN;
9030 }
9031
9032 static void tg3_get_regs(struct net_device *dev,
9033                 struct ethtool_regs *regs, void *_p)
9034 {
9035         u32 *p = _p;
9036         struct tg3 *tp = netdev_priv(dev);
9037         u8 *orig_p = _p;
9038         int i;
9039
9040         regs->version = 0;
9041
9042         memset(p, 0, TG3_REGDUMP_LEN);
9043
9044         if (tp->link_config.phy_is_low_power)
9045                 return;
9046
9047         tg3_full_lock(tp, 0);
9048
9049 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9050 #define GET_REG32_LOOP(base,len)                \
9051 do {    p = (u32 *)(orig_p + (base));           \
9052         for (i = 0; i < len; i += 4)            \
9053                 __GET_REG32((base) + i);        \
9054 } while (0)
9055 #define GET_REG32_1(reg)                        \
9056 do {    p = (u32 *)(orig_p + (reg));            \
9057         __GET_REG32((reg));                     \
9058 } while (0)
9059
9060         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9061         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9062         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9063         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9064         GET_REG32_1(SNDDATAC_MODE);
9065         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9066         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9067         GET_REG32_1(SNDBDC_MODE);
9068         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9069         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9070         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9071         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9072         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9073         GET_REG32_1(RCVDCC_MODE);
9074         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9075         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9076         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9077         GET_REG32_1(MBFREE_MODE);
9078         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9079         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9080         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9081         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9082         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9083         GET_REG32_1(RX_CPU_MODE);
9084         GET_REG32_1(RX_CPU_STATE);
9085         GET_REG32_1(RX_CPU_PGMCTR);
9086         GET_REG32_1(RX_CPU_HWBKPT);
9087         GET_REG32_1(TX_CPU_MODE);
9088         GET_REG32_1(TX_CPU_STATE);
9089         GET_REG32_1(TX_CPU_PGMCTR);
9090         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9091         GET_REG32_LOOP(FTQ_RESET, 0x120);
9092         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9093         GET_REG32_1(DMAC_MODE);
9094         GET_REG32_LOOP(GRC_MODE, 0x4c);
9095         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9096                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9097
9098 #undef __GET_REG32
9099 #undef GET_REG32_LOOP
9100 #undef GET_REG32_1
9101
9102         tg3_full_unlock(tp);
9103 }
9104
9105 static int tg3_get_eeprom_len(struct net_device *dev)
9106 {
9107         struct tg3 *tp = netdev_priv(dev);
9108
9109         return tp->nvram_size;
9110 }
9111
9112 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9113 {
9114         struct tg3 *tp = netdev_priv(dev);
9115         int ret;
9116         u8  *pd;
9117         u32 i, offset, len, b_offset, b_count;
9118         __be32 val;
9119
9120         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9121                 return -EINVAL;
9122
9123         if (tp->link_config.phy_is_low_power)
9124                 return -EAGAIN;
9125
9126         offset = eeprom->offset;
9127         len = eeprom->len;
9128         eeprom->len = 0;
9129
9130         eeprom->magic = TG3_EEPROM_MAGIC;
9131
9132         if (offset & 3) {
9133                 /* adjustments to start on required 4 byte boundary */
9134                 b_offset = offset & 3;
9135                 b_count = 4 - b_offset;
9136                 if (b_count > len) {
9137                         /* i.e. offset=1 len=2 */
9138                         b_count = len;
9139                 }
9140                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9141                 if (ret)
9142                         return ret;
9143                 memcpy(data, ((char*)&val) + b_offset, b_count);
9144                 len -= b_count;
9145                 offset += b_count;
9146                 eeprom->len += b_count;
9147         }
9148
9149         /* read bytes upto the last 4 byte boundary */
9150         pd = &data[eeprom->len];
9151         for (i = 0; i < (len - (len & 3)); i += 4) {
9152                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9153                 if (ret) {
9154                         eeprom->len += i;
9155                         return ret;
9156                 }
9157                 memcpy(pd + i, &val, 4);
9158         }
9159         eeprom->len += i;
9160
9161         if (len & 3) {
9162                 /* read last bytes not ending on 4 byte boundary */
9163                 pd = &data[eeprom->len];
9164                 b_count = len & 3;
9165                 b_offset = offset + len - b_count;
9166                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9167                 if (ret)
9168                         return ret;
9169                 memcpy(pd, &val, b_count);
9170                 eeprom->len += b_count;
9171         }
9172         return 0;
9173 }
9174
9175 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9176
9177 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9178 {
9179         struct tg3 *tp = netdev_priv(dev);
9180         int ret;
9181         u32 offset, len, b_offset, odd_len;
9182         u8 *buf;
9183         __be32 start, end;
9184
9185         if (tp->link_config.phy_is_low_power)
9186                 return -EAGAIN;
9187
9188         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9189             eeprom->magic != TG3_EEPROM_MAGIC)
9190                 return -EINVAL;
9191
9192         offset = eeprom->offset;
9193         len = eeprom->len;
9194
9195         if ((b_offset = (offset & 3))) {
9196                 /* adjustments to start on required 4 byte boundary */
9197                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9198                 if (ret)
9199                         return ret;
9200                 len += b_offset;
9201                 offset &= ~3;
9202                 if (len < 4)
9203                         len = 4;
9204         }
9205
9206         odd_len = 0;
9207         if (len & 3) {
9208                 /* adjustments to end on required 4 byte boundary */
9209                 odd_len = 1;
9210                 len = (len + 3) & ~3;
9211                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9212                 if (ret)
9213                         return ret;
9214         }
9215
9216         buf = data;
9217         if (b_offset || odd_len) {
9218                 buf = kmalloc(len, GFP_KERNEL);
9219                 if (!buf)
9220                         return -ENOMEM;
9221                 if (b_offset)
9222                         memcpy(buf, &start, 4);
9223                 if (odd_len)
9224                         memcpy(buf+len-4, &end, 4);
9225                 memcpy(buf + b_offset, data, eeprom->len);
9226         }
9227
9228         ret = tg3_nvram_write_block(tp, offset, len, buf);
9229
9230         if (buf != data)
9231                 kfree(buf);
9232
9233         return ret;
9234 }
9235
9236 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9237 {
9238         struct tg3 *tp = netdev_priv(dev);
9239
9240         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9241                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9242                         return -EAGAIN;
9243                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9244         }
9245
9246         cmd->supported = (SUPPORTED_Autoneg);
9247
9248         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9249                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9250                                    SUPPORTED_1000baseT_Full);
9251
9252         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9253                 cmd->supported |= (SUPPORTED_100baseT_Half |
9254                                   SUPPORTED_100baseT_Full |
9255                                   SUPPORTED_10baseT_Half |
9256                                   SUPPORTED_10baseT_Full |
9257                                   SUPPORTED_TP);
9258                 cmd->port = PORT_TP;
9259         } else {
9260                 cmd->supported |= SUPPORTED_FIBRE;
9261                 cmd->port = PORT_FIBRE;
9262         }
9263
9264         cmd->advertising = tp->link_config.advertising;
9265         if (netif_running(dev)) {
9266                 cmd->speed = tp->link_config.active_speed;
9267                 cmd->duplex = tp->link_config.active_duplex;
9268         }
9269         cmd->phy_address = PHY_ADDR;
9270         cmd->transceiver = XCVR_INTERNAL;
9271         cmd->autoneg = tp->link_config.autoneg;
9272         cmd->maxtxpkt = 0;
9273         cmd->maxrxpkt = 0;
9274         return 0;
9275 }
9276
9277 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9278 {
9279         struct tg3 *tp = netdev_priv(dev);
9280
9281         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9282                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9283                         return -EAGAIN;
9284                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9285         }
9286
9287         if (cmd->autoneg != AUTONEG_ENABLE &&
9288             cmd->autoneg != AUTONEG_DISABLE)
9289                 return -EINVAL;
9290
9291         if (cmd->autoneg == AUTONEG_DISABLE &&
9292             cmd->duplex != DUPLEX_FULL &&
9293             cmd->duplex != DUPLEX_HALF)
9294                 return -EINVAL;
9295
9296         if (cmd->autoneg == AUTONEG_ENABLE) {
9297                 u32 mask = ADVERTISED_Autoneg |
9298                            ADVERTISED_Pause |
9299                            ADVERTISED_Asym_Pause;
9300
9301                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9302                         mask |= ADVERTISED_1000baseT_Half |
9303                                 ADVERTISED_1000baseT_Full;
9304
9305                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9306                         mask |= ADVERTISED_100baseT_Half |
9307                                 ADVERTISED_100baseT_Full |
9308                                 ADVERTISED_10baseT_Half |
9309                                 ADVERTISED_10baseT_Full |
9310                                 ADVERTISED_TP;
9311                 else
9312                         mask |= ADVERTISED_FIBRE;
9313
9314                 if (cmd->advertising & ~mask)
9315                         return -EINVAL;
9316
9317                 mask &= (ADVERTISED_1000baseT_Half |
9318                          ADVERTISED_1000baseT_Full |
9319                          ADVERTISED_100baseT_Half |
9320                          ADVERTISED_100baseT_Full |
9321                          ADVERTISED_10baseT_Half |
9322                          ADVERTISED_10baseT_Full);
9323
9324                 cmd->advertising &= mask;
9325         } else {
9326                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9327                         if (cmd->speed != SPEED_1000)
9328                                 return -EINVAL;
9329
9330                         if (cmd->duplex != DUPLEX_FULL)
9331                                 return -EINVAL;
9332                 } else {
9333                         if (cmd->speed != SPEED_100 &&
9334                             cmd->speed != SPEED_10)
9335                                 return -EINVAL;
9336                 }
9337         }
9338
9339         tg3_full_lock(tp, 0);
9340
9341         tp->link_config.autoneg = cmd->autoneg;
9342         if (cmd->autoneg == AUTONEG_ENABLE) {
9343                 tp->link_config.advertising = (cmd->advertising |
9344                                               ADVERTISED_Autoneg);
9345                 tp->link_config.speed = SPEED_INVALID;
9346                 tp->link_config.duplex = DUPLEX_INVALID;
9347         } else {
9348                 tp->link_config.advertising = 0;
9349                 tp->link_config.speed = cmd->speed;
9350                 tp->link_config.duplex = cmd->duplex;
9351         }
9352
9353         tp->link_config.orig_speed = tp->link_config.speed;
9354         tp->link_config.orig_duplex = tp->link_config.duplex;
9355         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9356
9357         if (netif_running(dev))
9358                 tg3_setup_phy(tp, 1);
9359
9360         tg3_full_unlock(tp);
9361
9362         return 0;
9363 }
9364
9365 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9366 {
9367         struct tg3 *tp = netdev_priv(dev);
9368
9369         strcpy(info->driver, DRV_MODULE_NAME);
9370         strcpy(info->version, DRV_MODULE_VERSION);
9371         strcpy(info->fw_version, tp->fw_ver);
9372         strcpy(info->bus_info, pci_name(tp->pdev));
9373 }
9374
9375 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9376 {
9377         struct tg3 *tp = netdev_priv(dev);
9378
9379         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9380             device_can_wakeup(&tp->pdev->dev))
9381                 wol->supported = WAKE_MAGIC;
9382         else
9383                 wol->supported = 0;
9384         wol->wolopts = 0;
9385         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9386             device_can_wakeup(&tp->pdev->dev))
9387                 wol->wolopts = WAKE_MAGIC;
9388         memset(&wol->sopass, 0, sizeof(wol->sopass));
9389 }
9390
9391 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9392 {
9393         struct tg3 *tp = netdev_priv(dev);
9394         struct device *dp = &tp->pdev->dev;
9395
9396         if (wol->wolopts & ~WAKE_MAGIC)
9397                 return -EINVAL;
9398         if ((wol->wolopts & WAKE_MAGIC) &&
9399             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9400                 return -EINVAL;
9401
9402         spin_lock_bh(&tp->lock);
9403         if (wol->wolopts & WAKE_MAGIC) {
9404                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9405                 device_set_wakeup_enable(dp, true);
9406         } else {
9407                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9408                 device_set_wakeup_enable(dp, false);
9409         }
9410         spin_unlock_bh(&tp->lock);
9411
9412         return 0;
9413 }
9414
9415 static u32 tg3_get_msglevel(struct net_device *dev)
9416 {
9417         struct tg3 *tp = netdev_priv(dev);
9418         return tp->msg_enable;
9419 }
9420
9421 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9422 {
9423         struct tg3 *tp = netdev_priv(dev);
9424         tp->msg_enable = value;
9425 }
9426
9427 static int tg3_set_tso(struct net_device *dev, u32 value)
9428 {
9429         struct tg3 *tp = netdev_priv(dev);
9430
9431         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9432                 if (value)
9433                         return -EINVAL;
9434                 return 0;
9435         }
9436         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9437             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9438                 if (value) {
9439                         dev->features |= NETIF_F_TSO6;
9440                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9441                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9442                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9443                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9444                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9445                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9446                                 dev->features |= NETIF_F_TSO_ECN;
9447                 } else
9448                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9449         }
9450         return ethtool_op_set_tso(dev, value);
9451 }
9452
9453 static int tg3_nway_reset(struct net_device *dev)
9454 {
9455         struct tg3 *tp = netdev_priv(dev);
9456         int r;
9457
9458         if (!netif_running(dev))
9459                 return -EAGAIN;
9460
9461         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9462                 return -EINVAL;
9463
9464         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9465                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9466                         return -EAGAIN;
9467                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
9468         } else {
9469                 u32 bmcr;
9470
9471                 spin_lock_bh(&tp->lock);
9472                 r = -EINVAL;
9473                 tg3_readphy(tp, MII_BMCR, &bmcr);
9474                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9475                     ((bmcr & BMCR_ANENABLE) ||
9476                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9477                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9478                                                    BMCR_ANENABLE);
9479                         r = 0;
9480                 }
9481                 spin_unlock_bh(&tp->lock);
9482         }
9483
9484         return r;
9485 }
9486
9487 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9488 {
9489         struct tg3 *tp = netdev_priv(dev);
9490
9491         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9492         ering->rx_mini_max_pending = 0;
9493         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9494                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9495         else
9496                 ering->rx_jumbo_max_pending = 0;
9497
9498         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9499
9500         ering->rx_pending = tp->rx_pending;
9501         ering->rx_mini_pending = 0;
9502         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9503                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9504         else
9505                 ering->rx_jumbo_pending = 0;
9506
9507         ering->tx_pending = tp->napi[0].tx_pending;
9508 }
9509
9510 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9511 {
9512         struct tg3 *tp = netdev_priv(dev);
9513         int i, irq_sync = 0, err = 0;
9514
9515         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9516             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9517             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9518             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9519             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9520              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9521                 return -EINVAL;
9522
9523         if (netif_running(dev)) {
9524                 tg3_phy_stop(tp);
9525                 tg3_netif_stop(tp);
9526                 irq_sync = 1;
9527         }
9528
9529         tg3_full_lock(tp, irq_sync);
9530
9531         tp->rx_pending = ering->rx_pending;
9532
9533         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9534             tp->rx_pending > 63)
9535                 tp->rx_pending = 63;
9536         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9537
9538         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9539                 tp->napi[i].tx_pending = ering->tx_pending;
9540
9541         if (netif_running(dev)) {
9542                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9543                 err = tg3_restart_hw(tp, 1);
9544                 if (!err)
9545                         tg3_netif_start(tp);
9546         }
9547
9548         tg3_full_unlock(tp);
9549
9550         if (irq_sync && !err)
9551                 tg3_phy_start(tp);
9552
9553         return err;
9554 }
9555
9556 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9557 {
9558         struct tg3 *tp = netdev_priv(dev);
9559
9560         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9561
9562         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9563                 epause->rx_pause = 1;
9564         else
9565                 epause->rx_pause = 0;
9566
9567         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9568                 epause->tx_pause = 1;
9569         else
9570                 epause->tx_pause = 0;
9571 }
9572
9573 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9574 {
9575         struct tg3 *tp = netdev_priv(dev);
9576         int err = 0;
9577
9578         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9579                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9580                         return -EAGAIN;
9581
9582                 if (epause->autoneg) {
9583                         u32 newadv;
9584                         struct phy_device *phydev;
9585
9586                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9587
9588                         if (epause->rx_pause) {
9589                                 if (epause->tx_pause)
9590                                         newadv = ADVERTISED_Pause;
9591                                 else
9592                                         newadv = ADVERTISED_Pause |
9593                                                  ADVERTISED_Asym_Pause;
9594                         } else if (epause->tx_pause) {
9595                                 newadv = ADVERTISED_Asym_Pause;
9596                         } else
9597                                 newadv = 0;
9598
9599                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9600                                 u32 oldadv = phydev->advertising &
9601                                              (ADVERTISED_Pause |
9602                                               ADVERTISED_Asym_Pause);
9603                                 if (oldadv != newadv) {
9604                                         phydev->advertising &=
9605                                                 ~(ADVERTISED_Pause |
9606                                                   ADVERTISED_Asym_Pause);
9607                                         phydev->advertising |= newadv;
9608                                         err = phy_start_aneg(phydev);
9609                                 }
9610                         } else {
9611                                 tp->link_config.advertising &=
9612                                                 ~(ADVERTISED_Pause |
9613                                                   ADVERTISED_Asym_Pause);
9614                                 tp->link_config.advertising |= newadv;
9615                         }
9616                 } else {
9617                         if (epause->rx_pause)
9618                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9619                         else
9620                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9621
9622                         if (epause->tx_pause)
9623                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9624                         else
9625                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9626
9627                         if (netif_running(dev))
9628                                 tg3_setup_flow_control(tp, 0, 0);
9629                 }
9630         } else {
9631                 int irq_sync = 0;
9632
9633                 if (netif_running(dev)) {
9634                         tg3_netif_stop(tp);
9635                         irq_sync = 1;
9636                 }
9637
9638                 tg3_full_lock(tp, irq_sync);
9639
9640                 if (epause->autoneg)
9641                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9642                 else
9643                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9644                 if (epause->rx_pause)
9645                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9646                 else
9647                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9648                 if (epause->tx_pause)
9649                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9650                 else
9651                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9652
9653                 if (netif_running(dev)) {
9654                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9655                         err = tg3_restart_hw(tp, 1);
9656                         if (!err)
9657                                 tg3_netif_start(tp);
9658                 }
9659
9660                 tg3_full_unlock(tp);
9661         }
9662
9663         return err;
9664 }
9665
9666 static u32 tg3_get_rx_csum(struct net_device *dev)
9667 {
9668         struct tg3 *tp = netdev_priv(dev);
9669         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9670 }
9671
9672 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9673 {
9674         struct tg3 *tp = netdev_priv(dev);
9675
9676         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9677                 if (data != 0)
9678                         return -EINVAL;
9679                 return 0;
9680         }
9681
9682         spin_lock_bh(&tp->lock);
9683         if (data)
9684                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9685         else
9686                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9687         spin_unlock_bh(&tp->lock);
9688
9689         return 0;
9690 }
9691
9692 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9693 {
9694         struct tg3 *tp = netdev_priv(dev);
9695
9696         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9697                 if (data != 0)
9698                         return -EINVAL;
9699                 return 0;
9700         }
9701
9702         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9703                 ethtool_op_set_tx_ipv6_csum(dev, data);
9704         else
9705                 ethtool_op_set_tx_csum(dev, data);
9706
9707         return 0;
9708 }
9709
9710 static int tg3_get_sset_count (struct net_device *dev, int sset)
9711 {
9712         switch (sset) {
9713         case ETH_SS_TEST:
9714                 return TG3_NUM_TEST;
9715         case ETH_SS_STATS:
9716                 return TG3_NUM_STATS;
9717         default:
9718                 return -EOPNOTSUPP;
9719         }
9720 }
9721
9722 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9723 {
9724         switch (stringset) {
9725         case ETH_SS_STATS:
9726                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9727                 break;
9728         case ETH_SS_TEST:
9729                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9730                 break;
9731         default:
9732                 WARN_ON(1);     /* we need a WARN() */
9733                 break;
9734         }
9735 }
9736
9737 static int tg3_phys_id(struct net_device *dev, u32 data)
9738 {
9739         struct tg3 *tp = netdev_priv(dev);
9740         int i;
9741
9742         if (!netif_running(tp->dev))
9743                 return -EAGAIN;
9744
9745         if (data == 0)
9746                 data = UINT_MAX / 2;
9747
9748         for (i = 0; i < (data * 2); i++) {
9749                 if ((i % 2) == 0)
9750                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9751                                            LED_CTRL_1000MBPS_ON |
9752                                            LED_CTRL_100MBPS_ON |
9753                                            LED_CTRL_10MBPS_ON |
9754                                            LED_CTRL_TRAFFIC_OVERRIDE |
9755                                            LED_CTRL_TRAFFIC_BLINK |
9756                                            LED_CTRL_TRAFFIC_LED);
9757
9758                 else
9759                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9760                                            LED_CTRL_TRAFFIC_OVERRIDE);
9761
9762                 if (msleep_interruptible(500))
9763                         break;
9764         }
9765         tw32(MAC_LED_CTRL, tp->led_ctrl);
9766         return 0;
9767 }
9768
9769 static void tg3_get_ethtool_stats (struct net_device *dev,
9770                                    struct ethtool_stats *estats, u64 *tmp_stats)
9771 {
9772         struct tg3 *tp = netdev_priv(dev);
9773         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9774 }
9775
9776 #define NVRAM_TEST_SIZE 0x100
9777 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9778 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9779 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9780 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9781 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9782
9783 static int tg3_test_nvram(struct tg3 *tp)
9784 {
9785         u32 csum, magic;
9786         __be32 *buf;
9787         int i, j, k, err = 0, size;
9788
9789         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9790                 return 0;
9791
9792         if (tg3_nvram_read(tp, 0, &magic) != 0)
9793                 return -EIO;
9794
9795         if (magic == TG3_EEPROM_MAGIC)
9796                 size = NVRAM_TEST_SIZE;
9797         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9798                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9799                     TG3_EEPROM_SB_FORMAT_1) {
9800                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9801                         case TG3_EEPROM_SB_REVISION_0:
9802                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9803                                 break;
9804                         case TG3_EEPROM_SB_REVISION_2:
9805                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9806                                 break;
9807                         case TG3_EEPROM_SB_REVISION_3:
9808                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9809                                 break;
9810                         default:
9811                                 return 0;
9812                         }
9813                 } else
9814                         return 0;
9815         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9816                 size = NVRAM_SELFBOOT_HW_SIZE;
9817         else
9818                 return -EIO;
9819
9820         buf = kmalloc(size, GFP_KERNEL);
9821         if (buf == NULL)
9822                 return -ENOMEM;
9823
9824         err = -EIO;
9825         for (i = 0, j = 0; i < size; i += 4, j++) {
9826                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9827                 if (err)
9828                         break;
9829         }
9830         if (i < size)
9831                 goto out;
9832
9833         /* Selfboot format */
9834         magic = be32_to_cpu(buf[0]);
9835         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9836             TG3_EEPROM_MAGIC_FW) {
9837                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9838
9839                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9840                     TG3_EEPROM_SB_REVISION_2) {
9841                         /* For rev 2, the csum doesn't include the MBA. */
9842                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9843                                 csum8 += buf8[i];
9844                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9845                                 csum8 += buf8[i];
9846                 } else {
9847                         for (i = 0; i < size; i++)
9848                                 csum8 += buf8[i];
9849                 }
9850
9851                 if (csum8 == 0) {
9852                         err = 0;
9853                         goto out;
9854                 }
9855
9856                 err = -EIO;
9857                 goto out;
9858         }
9859
9860         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9861             TG3_EEPROM_MAGIC_HW) {
9862                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9863                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9864                 u8 *buf8 = (u8 *) buf;
9865
9866                 /* Separate the parity bits and the data bytes.  */
9867                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9868                         if ((i == 0) || (i == 8)) {
9869                                 int l;
9870                                 u8 msk;
9871
9872                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9873                                         parity[k++] = buf8[i] & msk;
9874                                 i++;
9875                         }
9876                         else if (i == 16) {
9877                                 int l;
9878                                 u8 msk;
9879
9880                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9881                                         parity[k++] = buf8[i] & msk;
9882                                 i++;
9883
9884                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9885                                         parity[k++] = buf8[i] & msk;
9886                                 i++;
9887                         }
9888                         data[j++] = buf8[i];
9889                 }
9890
9891                 err = -EIO;
9892                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9893                         u8 hw8 = hweight8(data[i]);
9894
9895                         if ((hw8 & 0x1) && parity[i])
9896                                 goto out;
9897                         else if (!(hw8 & 0x1) && !parity[i])
9898                                 goto out;
9899                 }
9900                 err = 0;
9901                 goto out;
9902         }
9903
9904         /* Bootstrap checksum at offset 0x10 */
9905         csum = calc_crc((unsigned char *) buf, 0x10);
9906         if (csum != be32_to_cpu(buf[0x10/4]))
9907                 goto out;
9908
9909         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9910         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9911         if (csum != be32_to_cpu(buf[0xfc/4]))
9912                 goto out;
9913
9914         err = 0;
9915
9916 out:
9917         kfree(buf);
9918         return err;
9919 }
9920
9921 #define TG3_SERDES_TIMEOUT_SEC  2
9922 #define TG3_COPPER_TIMEOUT_SEC  6
9923
9924 static int tg3_test_link(struct tg3 *tp)
9925 {
9926         int i, max;
9927
9928         if (!netif_running(tp->dev))
9929                 return -ENODEV;
9930
9931         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9932                 max = TG3_SERDES_TIMEOUT_SEC;
9933         else
9934                 max = TG3_COPPER_TIMEOUT_SEC;
9935
9936         for (i = 0; i < max; i++) {
9937                 if (netif_carrier_ok(tp->dev))
9938                         return 0;
9939
9940                 if (msleep_interruptible(1000))
9941                         break;
9942         }
9943
9944         return -EIO;
9945 }
9946
9947 /* Only test the commonly used registers */
9948 static int tg3_test_registers(struct tg3 *tp)
9949 {
9950         int i, is_5705, is_5750;
9951         u32 offset, read_mask, write_mask, val, save_val, read_val;
9952         static struct {
9953                 u16 offset;
9954                 u16 flags;
9955 #define TG3_FL_5705     0x1
9956 #define TG3_FL_NOT_5705 0x2
9957 #define TG3_FL_NOT_5788 0x4
9958 #define TG3_FL_NOT_5750 0x8
9959                 u32 read_mask;
9960                 u32 write_mask;
9961         } reg_tbl[] = {
9962                 /* MAC Control Registers */
9963                 { MAC_MODE, TG3_FL_NOT_5705,
9964                         0x00000000, 0x00ef6f8c },
9965                 { MAC_MODE, TG3_FL_5705,
9966                         0x00000000, 0x01ef6b8c },
9967                 { MAC_STATUS, TG3_FL_NOT_5705,
9968                         0x03800107, 0x00000000 },
9969                 { MAC_STATUS, TG3_FL_5705,
9970                         0x03800100, 0x00000000 },
9971                 { MAC_ADDR_0_HIGH, 0x0000,
9972                         0x00000000, 0x0000ffff },
9973                 { MAC_ADDR_0_LOW, 0x0000,
9974                         0x00000000, 0xffffffff },
9975                 { MAC_RX_MTU_SIZE, 0x0000,
9976                         0x00000000, 0x0000ffff },
9977                 { MAC_TX_MODE, 0x0000,
9978                         0x00000000, 0x00000070 },
9979                 { MAC_TX_LENGTHS, 0x0000,
9980                         0x00000000, 0x00003fff },
9981                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9982                         0x00000000, 0x000007fc },
9983                 { MAC_RX_MODE, TG3_FL_5705,
9984                         0x00000000, 0x000007dc },
9985                 { MAC_HASH_REG_0, 0x0000,
9986                         0x00000000, 0xffffffff },
9987                 { MAC_HASH_REG_1, 0x0000,
9988                         0x00000000, 0xffffffff },
9989                 { MAC_HASH_REG_2, 0x0000,
9990                         0x00000000, 0xffffffff },
9991                 { MAC_HASH_REG_3, 0x0000,
9992                         0x00000000, 0xffffffff },
9993
9994                 /* Receive Data and Receive BD Initiator Control Registers. */
9995                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9996                         0x00000000, 0xffffffff },
9997                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9998                         0x00000000, 0xffffffff },
9999                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10000                         0x00000000, 0x00000003 },
10001                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10002                         0x00000000, 0xffffffff },
10003                 { RCVDBDI_STD_BD+0, 0x0000,
10004                         0x00000000, 0xffffffff },
10005                 { RCVDBDI_STD_BD+4, 0x0000,
10006                         0x00000000, 0xffffffff },
10007                 { RCVDBDI_STD_BD+8, 0x0000,
10008                         0x00000000, 0xffff0002 },
10009                 { RCVDBDI_STD_BD+0xc, 0x0000,
10010                         0x00000000, 0xffffffff },
10011
10012                 /* Receive BD Initiator Control Registers. */
10013                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10014                         0x00000000, 0xffffffff },
10015                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10016                         0x00000000, 0x000003ff },
10017                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10018                         0x00000000, 0xffffffff },
10019
10020                 /* Host Coalescing Control Registers. */
10021                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10022                         0x00000000, 0x00000004 },
10023                 { HOSTCC_MODE, TG3_FL_5705,
10024                         0x00000000, 0x000000f6 },
10025                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10026                         0x00000000, 0xffffffff },
10027                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10028                         0x00000000, 0x000003ff },
10029                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10030                         0x00000000, 0xffffffff },
10031                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10032                         0x00000000, 0x000003ff },
10033                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10034                         0x00000000, 0xffffffff },
10035                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10036                         0x00000000, 0x000000ff },
10037                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10038                         0x00000000, 0xffffffff },
10039                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10040                         0x00000000, 0x000000ff },
10041                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10042                         0x00000000, 0xffffffff },
10043                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10044                         0x00000000, 0xffffffff },
10045                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10046                         0x00000000, 0xffffffff },
10047                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10048                         0x00000000, 0x000000ff },
10049                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10050                         0x00000000, 0xffffffff },
10051                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10052                         0x00000000, 0x000000ff },
10053                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10054                         0x00000000, 0xffffffff },
10055                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10056                         0x00000000, 0xffffffff },
10057                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10058                         0x00000000, 0xffffffff },
10059                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10060                         0x00000000, 0xffffffff },
10061                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10062                         0x00000000, 0xffffffff },
10063                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10064                         0xffffffff, 0x00000000 },
10065                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10066                         0xffffffff, 0x00000000 },
10067
10068                 /* Buffer Manager Control Registers. */
10069                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10070                         0x00000000, 0x007fff80 },
10071                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10072                         0x00000000, 0x007fffff },
10073                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10074                         0x00000000, 0x0000003f },
10075                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10076                         0x00000000, 0x000001ff },
10077                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10078                         0x00000000, 0x000001ff },
10079                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10080                         0xffffffff, 0x00000000 },
10081                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10082                         0xffffffff, 0x00000000 },
10083
10084                 /* Mailbox Registers */
10085                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10086                         0x00000000, 0x000001ff },
10087                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10088                         0x00000000, 0x000001ff },
10089                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10090                         0x00000000, 0x000007ff },
10091                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10092                         0x00000000, 0x000001ff },
10093
10094                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10095         };
10096
10097         is_5705 = is_5750 = 0;
10098         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10099                 is_5705 = 1;
10100                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10101                         is_5750 = 1;
10102         }
10103
10104         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10105                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10106                         continue;
10107
10108                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10109                         continue;
10110
10111                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10112                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10113                         continue;
10114
10115                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10116                         continue;
10117
10118                 offset = (u32) reg_tbl[i].offset;
10119                 read_mask = reg_tbl[i].read_mask;
10120                 write_mask = reg_tbl[i].write_mask;
10121
10122                 /* Save the original register content */
10123                 save_val = tr32(offset);
10124
10125                 /* Determine the read-only value. */
10126                 read_val = save_val & read_mask;
10127
10128                 /* Write zero to the register, then make sure the read-only bits
10129                  * are not changed and the read/write bits are all zeros.
10130                  */
10131                 tw32(offset, 0);
10132
10133                 val = tr32(offset);
10134
10135                 /* Test the read-only and read/write bits. */
10136                 if (((val & read_mask) != read_val) || (val & write_mask))
10137                         goto out;
10138
10139                 /* Write ones to all the bits defined by RdMask and WrMask, then
10140                  * make sure the read-only bits are not changed and the
10141                  * read/write bits are all ones.
10142                  */
10143                 tw32(offset, read_mask | write_mask);
10144
10145                 val = tr32(offset);
10146
10147                 /* Test the read-only bits. */
10148                 if ((val & read_mask) != read_val)
10149                         goto out;
10150
10151                 /* Test the read/write bits. */
10152                 if ((val & write_mask) != write_mask)
10153                         goto out;
10154
10155                 tw32(offset, save_val);
10156         }
10157
10158         return 0;
10159
10160 out:
10161         if (netif_msg_hw(tp))
10162                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10163                        offset);
10164         tw32(offset, save_val);
10165         return -EIO;
10166 }
10167
10168 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10169 {
10170         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10171         int i;
10172         u32 j;
10173
10174         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10175                 for (j = 0; j < len; j += 4) {
10176                         u32 val;
10177
10178                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10179                         tg3_read_mem(tp, offset + j, &val);
10180                         if (val != test_pattern[i])
10181                                 return -EIO;
10182                 }
10183         }
10184         return 0;
10185 }
10186
10187 static int tg3_test_memory(struct tg3 *tp)
10188 {
10189         static struct mem_entry {
10190                 u32 offset;
10191                 u32 len;
10192         } mem_tbl_570x[] = {
10193                 { 0x00000000, 0x00b50},
10194                 { 0x00002000, 0x1c000},
10195                 { 0xffffffff, 0x00000}
10196         }, mem_tbl_5705[] = {
10197                 { 0x00000100, 0x0000c},
10198                 { 0x00000200, 0x00008},
10199                 { 0x00004000, 0x00800},
10200                 { 0x00006000, 0x01000},
10201                 { 0x00008000, 0x02000},
10202                 { 0x00010000, 0x0e000},
10203                 { 0xffffffff, 0x00000}
10204         }, mem_tbl_5755[] = {
10205                 { 0x00000200, 0x00008},
10206                 { 0x00004000, 0x00800},
10207                 { 0x00006000, 0x00800},
10208                 { 0x00008000, 0x02000},
10209                 { 0x00010000, 0x0c000},
10210                 { 0xffffffff, 0x00000}
10211         }, mem_tbl_5906[] = {
10212                 { 0x00000200, 0x00008},
10213                 { 0x00004000, 0x00400},
10214                 { 0x00006000, 0x00400},
10215                 { 0x00008000, 0x01000},
10216                 { 0x00010000, 0x01000},
10217                 { 0xffffffff, 0x00000}
10218         };
10219         struct mem_entry *mem_tbl;
10220         int err = 0;
10221         int i;
10222
10223         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10224                 mem_tbl = mem_tbl_5755;
10225         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10226                 mem_tbl = mem_tbl_5906;
10227         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10228                 mem_tbl = mem_tbl_5705;
10229         else
10230                 mem_tbl = mem_tbl_570x;
10231
10232         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10233                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10234                     mem_tbl[i].len)) != 0)
10235                         break;
10236         }
10237
10238         return err;
10239 }
10240
10241 #define TG3_MAC_LOOPBACK        0
10242 #define TG3_PHY_LOOPBACK        1
10243
10244 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10245 {
10246         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10247         u32 desc_idx, coal_now;
10248         struct sk_buff *skb, *rx_skb;
10249         u8 *tx_data;
10250         dma_addr_t map;
10251         int num_pkts, tx_len, rx_len, i, err;
10252         struct tg3_rx_buffer_desc *desc;
10253         struct tg3_napi *tnapi, *rnapi;
10254         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10255
10256         if (tp->irq_cnt > 1) {
10257                 tnapi = &tp->napi[1];
10258                 rnapi = &tp->napi[1];
10259         } else {
10260                 tnapi = &tp->napi[0];
10261                 rnapi = &tp->napi[0];
10262         }
10263         coal_now = tnapi->coal_now | rnapi->coal_now;
10264
10265         if (loopback_mode == TG3_MAC_LOOPBACK) {
10266                 /* HW errata - mac loopback fails in some cases on 5780.
10267                  * Normal traffic and PHY loopback are not affected by
10268                  * errata.
10269                  */
10270                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10271                         return 0;
10272
10273                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10274                            MAC_MODE_PORT_INT_LPBACK;
10275                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10276                         mac_mode |= MAC_MODE_LINK_POLARITY;
10277                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10278                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10279                 else
10280                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10281                 tw32(MAC_MODE, mac_mode);
10282         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10283                 u32 val;
10284
10285                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10286                         tg3_phy_fet_toggle_apd(tp, false);
10287                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10288                 } else
10289                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10290
10291                 tg3_phy_toggle_automdix(tp, 0);
10292
10293                 tg3_writephy(tp, MII_BMCR, val);
10294                 udelay(40);
10295
10296                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10297                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10298                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10299                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10300                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10301                 } else
10302                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10303
10304                 /* reset to prevent losing 1st rx packet intermittently */
10305                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10306                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10307                         udelay(10);
10308                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10309                 }
10310                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10311                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10312                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10313                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10314                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10315                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10316                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10317                 }
10318                 tw32(MAC_MODE, mac_mode);
10319         }
10320         else
10321                 return -EINVAL;
10322
10323         err = -EIO;
10324
10325         tx_len = 1514;
10326         skb = netdev_alloc_skb(tp->dev, tx_len);
10327         if (!skb)
10328                 return -ENOMEM;
10329
10330         tx_data = skb_put(skb, tx_len);
10331         memcpy(tx_data, tp->dev->dev_addr, 6);
10332         memset(tx_data + 6, 0x0, 8);
10333
10334         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10335
10336         for (i = 14; i < tx_len; i++)
10337                 tx_data[i] = (u8) (i & 0xff);
10338
10339         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10340
10341         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10342                rnapi->coal_now);
10343
10344         udelay(10);
10345
10346         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10347
10348         num_pkts = 0;
10349
10350         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10351
10352         tnapi->tx_prod++;
10353         num_pkts++;
10354
10355         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10356         tr32_mailbox(tnapi->prodmbox);
10357
10358         udelay(10);
10359
10360         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
10361         for (i = 0; i < 25; i++) {
10362                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10363                        coal_now);
10364
10365                 udelay(10);
10366
10367                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10368                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10369                 if ((tx_idx == tnapi->tx_prod) &&
10370                     (rx_idx == (rx_start_idx + num_pkts)))
10371                         break;
10372         }
10373
10374         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10375         dev_kfree_skb(skb);
10376
10377         if (tx_idx != tnapi->tx_prod)
10378                 goto out;
10379
10380         if (rx_idx != rx_start_idx + num_pkts)
10381                 goto out;
10382
10383         desc = &rnapi->rx_rcb[rx_start_idx];
10384         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10385         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10386         if (opaque_key != RXD_OPAQUE_RING_STD)
10387                 goto out;
10388
10389         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10390             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10391                 goto out;
10392
10393         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10394         if (rx_len != tx_len)
10395                 goto out;
10396
10397         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10398
10399         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10400         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10401
10402         for (i = 14; i < tx_len; i++) {
10403                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10404                         goto out;
10405         }
10406         err = 0;
10407
10408         /* tg3_free_rings will unmap and free the rx_skb */
10409 out:
10410         return err;
10411 }
10412
10413 #define TG3_MAC_LOOPBACK_FAILED         1
10414 #define TG3_PHY_LOOPBACK_FAILED         2
10415 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10416                                          TG3_PHY_LOOPBACK_FAILED)
10417
10418 static int tg3_test_loopback(struct tg3 *tp)
10419 {
10420         int err = 0;
10421         u32 cpmuctrl = 0;
10422
10423         if (!netif_running(tp->dev))
10424                 return TG3_LOOPBACK_FAILED;
10425
10426         err = tg3_reset_hw(tp, 1);
10427         if (err)
10428                 return TG3_LOOPBACK_FAILED;
10429
10430         /* Turn off gphy autopowerdown. */
10431         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10432                 tg3_phy_toggle_apd(tp, false);
10433
10434         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10435                 int i;
10436                 u32 status;
10437
10438                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10439
10440                 /* Wait for up to 40 microseconds to acquire lock. */
10441                 for (i = 0; i < 4; i++) {
10442                         status = tr32(TG3_CPMU_MUTEX_GNT);
10443                         if (status == CPMU_MUTEX_GNT_DRIVER)
10444                                 break;
10445                         udelay(10);
10446                 }
10447
10448                 if (status != CPMU_MUTEX_GNT_DRIVER)
10449                         return TG3_LOOPBACK_FAILED;
10450
10451                 /* Turn off link-based power management. */
10452                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10453                 tw32(TG3_CPMU_CTRL,
10454                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10455                                   CPMU_CTRL_LINK_AWARE_MODE));
10456         }
10457
10458         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10459                 err |= TG3_MAC_LOOPBACK_FAILED;
10460
10461         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10462                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10463
10464                 /* Release the mutex */
10465                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10466         }
10467
10468         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10469             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10470                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10471                         err |= TG3_PHY_LOOPBACK_FAILED;
10472         }
10473
10474         /* Re-enable gphy autopowerdown. */
10475         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10476                 tg3_phy_toggle_apd(tp, true);
10477
10478         return err;
10479 }
10480
10481 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10482                           u64 *data)
10483 {
10484         struct tg3 *tp = netdev_priv(dev);
10485
10486         if (tp->link_config.phy_is_low_power)
10487                 tg3_set_power_state(tp, PCI_D0);
10488
10489         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10490
10491         if (tg3_test_nvram(tp) != 0) {
10492                 etest->flags |= ETH_TEST_FL_FAILED;
10493                 data[0] = 1;
10494         }
10495         if (tg3_test_link(tp) != 0) {
10496                 etest->flags |= ETH_TEST_FL_FAILED;
10497                 data[1] = 1;
10498         }
10499         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10500                 int err, err2 = 0, irq_sync = 0;
10501
10502                 if (netif_running(dev)) {
10503                         tg3_phy_stop(tp);
10504                         tg3_netif_stop(tp);
10505                         irq_sync = 1;
10506                 }
10507
10508                 tg3_full_lock(tp, irq_sync);
10509
10510                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10511                 err = tg3_nvram_lock(tp);
10512                 tg3_halt_cpu(tp, RX_CPU_BASE);
10513                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10514                         tg3_halt_cpu(tp, TX_CPU_BASE);
10515                 if (!err)
10516                         tg3_nvram_unlock(tp);
10517
10518                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10519                         tg3_phy_reset(tp);
10520
10521                 if (tg3_test_registers(tp) != 0) {
10522                         etest->flags |= ETH_TEST_FL_FAILED;
10523                         data[2] = 1;
10524                 }
10525                 if (tg3_test_memory(tp) != 0) {
10526                         etest->flags |= ETH_TEST_FL_FAILED;
10527                         data[3] = 1;
10528                 }
10529                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10530                         etest->flags |= ETH_TEST_FL_FAILED;
10531
10532                 tg3_full_unlock(tp);
10533
10534                 if (tg3_test_interrupt(tp) != 0) {
10535                         etest->flags |= ETH_TEST_FL_FAILED;
10536                         data[5] = 1;
10537                 }
10538
10539                 tg3_full_lock(tp, 0);
10540
10541                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10542                 if (netif_running(dev)) {
10543                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10544                         err2 = tg3_restart_hw(tp, 1);
10545                         if (!err2)
10546                                 tg3_netif_start(tp);
10547                 }
10548
10549                 tg3_full_unlock(tp);
10550
10551                 if (irq_sync && !err2)
10552                         tg3_phy_start(tp);
10553         }
10554         if (tp->link_config.phy_is_low_power)
10555                 tg3_set_power_state(tp, PCI_D3hot);
10556
10557 }
10558
10559 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10560 {
10561         struct mii_ioctl_data *data = if_mii(ifr);
10562         struct tg3 *tp = netdev_priv(dev);
10563         int err;
10564
10565         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10566                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10567                         return -EAGAIN;
10568                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10569         }
10570
10571         switch(cmd) {
10572         case SIOCGMIIPHY:
10573                 data->phy_id = PHY_ADDR;
10574
10575                 /* fallthru */
10576         case SIOCGMIIREG: {
10577                 u32 mii_regval;
10578
10579                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10580                         break;                  /* We have no PHY */
10581
10582                 if (tp->link_config.phy_is_low_power)
10583                         return -EAGAIN;
10584
10585                 spin_lock_bh(&tp->lock);
10586                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10587                 spin_unlock_bh(&tp->lock);
10588
10589                 data->val_out = mii_regval;
10590
10591                 return err;
10592         }
10593
10594         case SIOCSMIIREG:
10595                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10596                         break;                  /* We have no PHY */
10597
10598                 if (!capable(CAP_NET_ADMIN))
10599                         return -EPERM;
10600
10601                 if (tp->link_config.phy_is_low_power)
10602                         return -EAGAIN;
10603
10604                 spin_lock_bh(&tp->lock);
10605                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10606                 spin_unlock_bh(&tp->lock);
10607
10608                 return err;
10609
10610         default:
10611                 /* do nothing */
10612                 break;
10613         }
10614         return -EOPNOTSUPP;
10615 }
10616
10617 #if TG3_VLAN_TAG_USED
10618 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10619 {
10620         struct tg3 *tp = netdev_priv(dev);
10621
10622         if (!netif_running(dev)) {
10623                 tp->vlgrp = grp;
10624                 return;
10625         }
10626
10627         tg3_netif_stop(tp);
10628
10629         tg3_full_lock(tp, 0);
10630
10631         tp->vlgrp = grp;
10632
10633         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10634         __tg3_set_rx_mode(dev);
10635
10636         tg3_netif_start(tp);
10637
10638         tg3_full_unlock(tp);
10639 }
10640 #endif
10641
10642 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10643 {
10644         struct tg3 *tp = netdev_priv(dev);
10645
10646         memcpy(ec, &tp->coal, sizeof(*ec));
10647         return 0;
10648 }
10649
10650 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10651 {
10652         struct tg3 *tp = netdev_priv(dev);
10653         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10654         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10655
10656         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10657                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10658                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10659                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10660                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10661         }
10662
10663         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10664             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10665             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10666             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10667             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10668             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10669             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10670             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10671             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10672             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10673                 return -EINVAL;
10674
10675         /* No rx interrupts will be generated if both are zero */
10676         if ((ec->rx_coalesce_usecs == 0) &&
10677             (ec->rx_max_coalesced_frames == 0))
10678                 return -EINVAL;
10679
10680         /* No tx interrupts will be generated if both are zero */
10681         if ((ec->tx_coalesce_usecs == 0) &&
10682             (ec->tx_max_coalesced_frames == 0))
10683                 return -EINVAL;
10684
10685         /* Only copy relevant parameters, ignore all others. */
10686         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10687         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10688         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10689         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10690         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10691         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10692         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10693         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10694         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10695
10696         if (netif_running(dev)) {
10697                 tg3_full_lock(tp, 0);
10698                 __tg3_set_coalesce(tp, &tp->coal);
10699                 tg3_full_unlock(tp);
10700         }
10701         return 0;
10702 }
10703
10704 static const struct ethtool_ops tg3_ethtool_ops = {
10705         .get_settings           = tg3_get_settings,
10706         .set_settings           = tg3_set_settings,
10707         .get_drvinfo            = tg3_get_drvinfo,
10708         .get_regs_len           = tg3_get_regs_len,
10709         .get_regs               = tg3_get_regs,
10710         .get_wol                = tg3_get_wol,
10711         .set_wol                = tg3_set_wol,
10712         .get_msglevel           = tg3_get_msglevel,
10713         .set_msglevel           = tg3_set_msglevel,
10714         .nway_reset             = tg3_nway_reset,
10715         .get_link               = ethtool_op_get_link,
10716         .get_eeprom_len         = tg3_get_eeprom_len,
10717         .get_eeprom             = tg3_get_eeprom,
10718         .set_eeprom             = tg3_set_eeprom,
10719         .get_ringparam          = tg3_get_ringparam,
10720         .set_ringparam          = tg3_set_ringparam,
10721         .get_pauseparam         = tg3_get_pauseparam,
10722         .set_pauseparam         = tg3_set_pauseparam,
10723         .get_rx_csum            = tg3_get_rx_csum,
10724         .set_rx_csum            = tg3_set_rx_csum,
10725         .set_tx_csum            = tg3_set_tx_csum,
10726         .set_sg                 = ethtool_op_set_sg,
10727         .set_tso                = tg3_set_tso,
10728         .self_test              = tg3_self_test,
10729         .get_strings            = tg3_get_strings,
10730         .phys_id                = tg3_phys_id,
10731         .get_ethtool_stats      = tg3_get_ethtool_stats,
10732         .get_coalesce           = tg3_get_coalesce,
10733         .set_coalesce           = tg3_set_coalesce,
10734         .get_sset_count         = tg3_get_sset_count,
10735 };
10736
10737 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10738 {
10739         u32 cursize, val, magic;
10740
10741         tp->nvram_size = EEPROM_CHIP_SIZE;
10742
10743         if (tg3_nvram_read(tp, 0, &magic) != 0)
10744                 return;
10745
10746         if ((magic != TG3_EEPROM_MAGIC) &&
10747             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10748             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10749                 return;
10750
10751         /*
10752          * Size the chip by reading offsets at increasing powers of two.
10753          * When we encounter our validation signature, we know the addressing
10754          * has wrapped around, and thus have our chip size.
10755          */
10756         cursize = 0x10;
10757
10758         while (cursize < tp->nvram_size) {
10759                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10760                         return;
10761
10762                 if (val == magic)
10763                         break;
10764
10765                 cursize <<= 1;
10766         }
10767
10768         tp->nvram_size = cursize;
10769 }
10770
10771 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10772 {
10773         u32 val;
10774
10775         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10776             tg3_nvram_read(tp, 0, &val) != 0)
10777                 return;
10778
10779         /* Selfboot format */
10780         if (val != TG3_EEPROM_MAGIC) {
10781                 tg3_get_eeprom_size(tp);
10782                 return;
10783         }
10784
10785         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10786                 if (val != 0) {
10787                         /* This is confusing.  We want to operate on the
10788                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10789                          * call will read from NVRAM and byteswap the data
10790                          * according to the byteswapping settings for all
10791                          * other register accesses.  This ensures the data we
10792                          * want will always reside in the lower 16-bits.
10793                          * However, the data in NVRAM is in LE format, which
10794                          * means the data from the NVRAM read will always be
10795                          * opposite the endianness of the CPU.  The 16-bit
10796                          * byteswap then brings the data to CPU endianness.
10797                          */
10798                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10799                         return;
10800                 }
10801         }
10802         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10803 }
10804
10805 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10806 {
10807         u32 nvcfg1;
10808
10809         nvcfg1 = tr32(NVRAM_CFG1);
10810         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10811                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10812         } else {
10813                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10814                 tw32(NVRAM_CFG1, nvcfg1);
10815         }
10816
10817         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10818             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10819                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10820                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10821                         tp->nvram_jedecnum = JEDEC_ATMEL;
10822                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10823                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10824                         break;
10825                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10826                         tp->nvram_jedecnum = JEDEC_ATMEL;
10827                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10828                         break;
10829                 case FLASH_VENDOR_ATMEL_EEPROM:
10830                         tp->nvram_jedecnum = JEDEC_ATMEL;
10831                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10832                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10833                         break;
10834                 case FLASH_VENDOR_ST:
10835                         tp->nvram_jedecnum = JEDEC_ST;
10836                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10837                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10838                         break;
10839                 case FLASH_VENDOR_SAIFUN:
10840                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10841                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10842                         break;
10843                 case FLASH_VENDOR_SST_SMALL:
10844                 case FLASH_VENDOR_SST_LARGE:
10845                         tp->nvram_jedecnum = JEDEC_SST;
10846                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10847                         break;
10848                 }
10849         } else {
10850                 tp->nvram_jedecnum = JEDEC_ATMEL;
10851                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10852                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10853         }
10854 }
10855
10856 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10857 {
10858         u32 nvcfg1;
10859
10860         nvcfg1 = tr32(NVRAM_CFG1);
10861
10862         /* NVRAM protection for TPM */
10863         if (nvcfg1 & (1 << 27))
10864                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10865
10866         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10867         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10868         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10869                 tp->nvram_jedecnum = JEDEC_ATMEL;
10870                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10871                 break;
10872         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10873                 tp->nvram_jedecnum = JEDEC_ATMEL;
10874                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10875                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10876                 break;
10877         case FLASH_5752VENDOR_ST_M45PE10:
10878         case FLASH_5752VENDOR_ST_M45PE20:
10879         case FLASH_5752VENDOR_ST_M45PE40:
10880                 tp->nvram_jedecnum = JEDEC_ST;
10881                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10882                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10883                 break;
10884         }
10885
10886         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10887                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10888                 case FLASH_5752PAGE_SIZE_256:
10889                         tp->nvram_pagesize = 256;
10890                         break;
10891                 case FLASH_5752PAGE_SIZE_512:
10892                         tp->nvram_pagesize = 512;
10893                         break;
10894                 case FLASH_5752PAGE_SIZE_1K:
10895                         tp->nvram_pagesize = 1024;
10896                         break;
10897                 case FLASH_5752PAGE_SIZE_2K:
10898                         tp->nvram_pagesize = 2048;
10899                         break;
10900                 case FLASH_5752PAGE_SIZE_4K:
10901                         tp->nvram_pagesize = 4096;
10902                         break;
10903                 case FLASH_5752PAGE_SIZE_264:
10904                         tp->nvram_pagesize = 264;
10905                         break;
10906                 }
10907         } else {
10908                 /* For eeprom, set pagesize to maximum eeprom size */
10909                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10910
10911                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10912                 tw32(NVRAM_CFG1, nvcfg1);
10913         }
10914 }
10915
10916 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10917 {
10918         u32 nvcfg1, protect = 0;
10919
10920         nvcfg1 = tr32(NVRAM_CFG1);
10921
10922         /* NVRAM protection for TPM */
10923         if (nvcfg1 & (1 << 27)) {
10924                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10925                 protect = 1;
10926         }
10927
10928         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10929         switch (nvcfg1) {
10930         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10931         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10932         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10933         case FLASH_5755VENDOR_ATMEL_FLASH_5:
10934                 tp->nvram_jedecnum = JEDEC_ATMEL;
10935                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10936                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10937                 tp->nvram_pagesize = 264;
10938                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10939                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10940                         tp->nvram_size = (protect ? 0x3e200 :
10941                                           TG3_NVRAM_SIZE_512KB);
10942                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10943                         tp->nvram_size = (protect ? 0x1f200 :
10944                                           TG3_NVRAM_SIZE_256KB);
10945                 else
10946                         tp->nvram_size = (protect ? 0x1f200 :
10947                                           TG3_NVRAM_SIZE_128KB);
10948                 break;
10949         case FLASH_5752VENDOR_ST_M45PE10:
10950         case FLASH_5752VENDOR_ST_M45PE20:
10951         case FLASH_5752VENDOR_ST_M45PE40:
10952                 tp->nvram_jedecnum = JEDEC_ST;
10953                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10954                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10955                 tp->nvram_pagesize = 256;
10956                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10957                         tp->nvram_size = (protect ?
10958                                           TG3_NVRAM_SIZE_64KB :
10959                                           TG3_NVRAM_SIZE_128KB);
10960                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10961                         tp->nvram_size = (protect ?
10962                                           TG3_NVRAM_SIZE_64KB :
10963                                           TG3_NVRAM_SIZE_256KB);
10964                 else
10965                         tp->nvram_size = (protect ?
10966                                           TG3_NVRAM_SIZE_128KB :
10967                                           TG3_NVRAM_SIZE_512KB);
10968                 break;
10969         }
10970 }
10971
10972 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10973 {
10974         u32 nvcfg1;
10975
10976         nvcfg1 = tr32(NVRAM_CFG1);
10977
10978         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10979         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10980         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10981         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10982         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10983                 tp->nvram_jedecnum = JEDEC_ATMEL;
10984                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10985                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10986
10987                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10988                 tw32(NVRAM_CFG1, nvcfg1);
10989                 break;
10990         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10991         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10992         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10993         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10994                 tp->nvram_jedecnum = JEDEC_ATMEL;
10995                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10996                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10997                 tp->nvram_pagesize = 264;
10998                 break;
10999         case FLASH_5752VENDOR_ST_M45PE10:
11000         case FLASH_5752VENDOR_ST_M45PE20:
11001         case FLASH_5752VENDOR_ST_M45PE40:
11002                 tp->nvram_jedecnum = JEDEC_ST;
11003                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11004                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11005                 tp->nvram_pagesize = 256;
11006                 break;
11007         }
11008 }
11009
11010 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11011 {
11012         u32 nvcfg1, protect = 0;
11013
11014         nvcfg1 = tr32(NVRAM_CFG1);
11015
11016         /* NVRAM protection for TPM */
11017         if (nvcfg1 & (1 << 27)) {
11018                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11019                 protect = 1;
11020         }
11021
11022         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11023         switch (nvcfg1) {
11024         case FLASH_5761VENDOR_ATMEL_ADB021D:
11025         case FLASH_5761VENDOR_ATMEL_ADB041D:
11026         case FLASH_5761VENDOR_ATMEL_ADB081D:
11027         case FLASH_5761VENDOR_ATMEL_ADB161D:
11028         case FLASH_5761VENDOR_ATMEL_MDB021D:
11029         case FLASH_5761VENDOR_ATMEL_MDB041D:
11030         case FLASH_5761VENDOR_ATMEL_MDB081D:
11031         case FLASH_5761VENDOR_ATMEL_MDB161D:
11032                 tp->nvram_jedecnum = JEDEC_ATMEL;
11033                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11034                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11035                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11036                 tp->nvram_pagesize = 256;
11037                 break;
11038         case FLASH_5761VENDOR_ST_A_M45PE20:
11039         case FLASH_5761VENDOR_ST_A_M45PE40:
11040         case FLASH_5761VENDOR_ST_A_M45PE80:
11041         case FLASH_5761VENDOR_ST_A_M45PE16:
11042         case FLASH_5761VENDOR_ST_M_M45PE20:
11043         case FLASH_5761VENDOR_ST_M_M45PE40:
11044         case FLASH_5761VENDOR_ST_M_M45PE80:
11045         case FLASH_5761VENDOR_ST_M_M45PE16:
11046                 tp->nvram_jedecnum = JEDEC_ST;
11047                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11048                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11049                 tp->nvram_pagesize = 256;
11050                 break;
11051         }
11052
11053         if (protect) {
11054                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11055         } else {
11056                 switch (nvcfg1) {
11057                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11058                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11059                 case FLASH_5761VENDOR_ST_A_M45PE16:
11060                 case FLASH_5761VENDOR_ST_M_M45PE16:
11061                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11062                         break;
11063                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11064                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11065                 case FLASH_5761VENDOR_ST_A_M45PE80:
11066                 case FLASH_5761VENDOR_ST_M_M45PE80:
11067                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11068                         break;
11069                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11070                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11071                 case FLASH_5761VENDOR_ST_A_M45PE40:
11072                 case FLASH_5761VENDOR_ST_M_M45PE40:
11073                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11074                         break;
11075                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11076                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11077                 case FLASH_5761VENDOR_ST_A_M45PE20:
11078                 case FLASH_5761VENDOR_ST_M_M45PE20:
11079                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11080                         break;
11081                 }
11082         }
11083 }
11084
11085 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11086 {
11087         tp->nvram_jedecnum = JEDEC_ATMEL;
11088         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11089         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11090 }
11091
11092 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11093 {
11094         u32 nvcfg1;
11095
11096         nvcfg1 = tr32(NVRAM_CFG1);
11097
11098         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11099         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11100         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11101                 tp->nvram_jedecnum = JEDEC_ATMEL;
11102                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11103                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11104
11105                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11106                 tw32(NVRAM_CFG1, nvcfg1);
11107                 return;
11108         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11109         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11110         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11111         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11112         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11113         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11114         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11115                 tp->nvram_jedecnum = JEDEC_ATMEL;
11116                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11117                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11118
11119                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11120                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11121                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11122                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11123                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11124                         break;
11125                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11126                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11127                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11128                         break;
11129                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11130                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11131                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11132                         break;
11133                 }
11134                 break;
11135         case FLASH_5752VENDOR_ST_M45PE10:
11136         case FLASH_5752VENDOR_ST_M45PE20:
11137         case FLASH_5752VENDOR_ST_M45PE40:
11138                 tp->nvram_jedecnum = JEDEC_ST;
11139                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11140                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11141
11142                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11143                 case FLASH_5752VENDOR_ST_M45PE10:
11144                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11145                         break;
11146                 case FLASH_5752VENDOR_ST_M45PE20:
11147                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11148                         break;
11149                 case FLASH_5752VENDOR_ST_M45PE40:
11150                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11151                         break;
11152                 }
11153                 break;
11154         default:
11155                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11156                 return;
11157         }
11158
11159         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11160         case FLASH_5752PAGE_SIZE_256:
11161                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11162                 tp->nvram_pagesize = 256;
11163                 break;
11164         case FLASH_5752PAGE_SIZE_512:
11165                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11166                 tp->nvram_pagesize = 512;
11167                 break;
11168         case FLASH_5752PAGE_SIZE_1K:
11169                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11170                 tp->nvram_pagesize = 1024;
11171                 break;
11172         case FLASH_5752PAGE_SIZE_2K:
11173                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11174                 tp->nvram_pagesize = 2048;
11175                 break;
11176         case FLASH_5752PAGE_SIZE_4K:
11177                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11178                 tp->nvram_pagesize = 4096;
11179                 break;
11180         case FLASH_5752PAGE_SIZE_264:
11181                 tp->nvram_pagesize = 264;
11182                 break;
11183         case FLASH_5752PAGE_SIZE_528:
11184                 tp->nvram_pagesize = 528;
11185                 break;
11186         }
11187 }
11188
11189 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11190 static void __devinit tg3_nvram_init(struct tg3 *tp)
11191 {
11192         tw32_f(GRC_EEPROM_ADDR,
11193              (EEPROM_ADDR_FSM_RESET |
11194               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11195                EEPROM_ADDR_CLKPERD_SHIFT)));
11196
11197         msleep(1);
11198
11199         /* Enable seeprom accesses. */
11200         tw32_f(GRC_LOCAL_CTRL,
11201              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11202         udelay(100);
11203
11204         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11205             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11206                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11207
11208                 if (tg3_nvram_lock(tp)) {
11209                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11210                                "tg3_nvram_init failed.\n", tp->dev->name);
11211                         return;
11212                 }
11213                 tg3_enable_nvram_access(tp);
11214
11215                 tp->nvram_size = 0;
11216
11217                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11218                         tg3_get_5752_nvram_info(tp);
11219                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11220                         tg3_get_5755_nvram_info(tp);
11221                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11222                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11223                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11224                         tg3_get_5787_nvram_info(tp);
11225                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11226                         tg3_get_5761_nvram_info(tp);
11227                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11228                         tg3_get_5906_nvram_info(tp);
11229                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11230                         tg3_get_57780_nvram_info(tp);
11231                 else
11232                         tg3_get_nvram_info(tp);
11233
11234                 if (tp->nvram_size == 0)
11235                         tg3_get_nvram_size(tp);
11236
11237                 tg3_disable_nvram_access(tp);
11238                 tg3_nvram_unlock(tp);
11239
11240         } else {
11241                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11242
11243                 tg3_get_eeprom_size(tp);
11244         }
11245 }
11246
11247 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11248                                     u32 offset, u32 len, u8 *buf)
11249 {
11250         int i, j, rc = 0;
11251         u32 val;
11252
11253         for (i = 0; i < len; i += 4) {
11254                 u32 addr;
11255                 __be32 data;
11256
11257                 addr = offset + i;
11258
11259                 memcpy(&data, buf + i, 4);
11260
11261                 /*
11262                  * The SEEPROM interface expects the data to always be opposite
11263                  * the native endian format.  We accomplish this by reversing
11264                  * all the operations that would have been performed on the
11265                  * data from a call to tg3_nvram_read_be32().
11266                  */
11267                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11268
11269                 val = tr32(GRC_EEPROM_ADDR);
11270                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11271
11272                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11273                         EEPROM_ADDR_READ);
11274                 tw32(GRC_EEPROM_ADDR, val |
11275                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11276                         (addr & EEPROM_ADDR_ADDR_MASK) |
11277                         EEPROM_ADDR_START |
11278                         EEPROM_ADDR_WRITE);
11279
11280                 for (j = 0; j < 1000; j++) {
11281                         val = tr32(GRC_EEPROM_ADDR);
11282
11283                         if (val & EEPROM_ADDR_COMPLETE)
11284                                 break;
11285                         msleep(1);
11286                 }
11287                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11288                         rc = -EBUSY;
11289                         break;
11290                 }
11291         }
11292
11293         return rc;
11294 }
11295
11296 /* offset and length are dword aligned */
11297 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11298                 u8 *buf)
11299 {
11300         int ret = 0;
11301         u32 pagesize = tp->nvram_pagesize;
11302         u32 pagemask = pagesize - 1;
11303         u32 nvram_cmd;
11304         u8 *tmp;
11305
11306         tmp = kmalloc(pagesize, GFP_KERNEL);
11307         if (tmp == NULL)
11308                 return -ENOMEM;
11309
11310         while (len) {
11311                 int j;
11312                 u32 phy_addr, page_off, size;
11313
11314                 phy_addr = offset & ~pagemask;
11315
11316                 for (j = 0; j < pagesize; j += 4) {
11317                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11318                                                   (__be32 *) (tmp + j));
11319                         if (ret)
11320                                 break;
11321                 }
11322                 if (ret)
11323                         break;
11324
11325                 page_off = offset & pagemask;
11326                 size = pagesize;
11327                 if (len < size)
11328                         size = len;
11329
11330                 len -= size;
11331
11332                 memcpy(tmp + page_off, buf, size);
11333
11334                 offset = offset + (pagesize - page_off);
11335
11336                 tg3_enable_nvram_access(tp);
11337
11338                 /*
11339                  * Before we can erase the flash page, we need
11340                  * to issue a special "write enable" command.
11341                  */
11342                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11343
11344                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11345                         break;
11346
11347                 /* Erase the target page */
11348                 tw32(NVRAM_ADDR, phy_addr);
11349
11350                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11351                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11352
11353                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11354                         break;
11355
11356                 /* Issue another write enable to start the write. */
11357                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11358
11359                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11360                         break;
11361
11362                 for (j = 0; j < pagesize; j += 4) {
11363                         __be32 data;
11364
11365                         data = *((__be32 *) (tmp + j));
11366
11367                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11368
11369                         tw32(NVRAM_ADDR, phy_addr + j);
11370
11371                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11372                                 NVRAM_CMD_WR;
11373
11374                         if (j == 0)
11375                                 nvram_cmd |= NVRAM_CMD_FIRST;
11376                         else if (j == (pagesize - 4))
11377                                 nvram_cmd |= NVRAM_CMD_LAST;
11378
11379                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11380                                 break;
11381                 }
11382                 if (ret)
11383                         break;
11384         }
11385
11386         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11387         tg3_nvram_exec_cmd(tp, nvram_cmd);
11388
11389         kfree(tmp);
11390
11391         return ret;
11392 }
11393
11394 /* offset and length are dword aligned */
11395 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11396                 u8 *buf)
11397 {
11398         int i, ret = 0;
11399
11400         for (i = 0; i < len; i += 4, offset += 4) {
11401                 u32 page_off, phy_addr, nvram_cmd;
11402                 __be32 data;
11403
11404                 memcpy(&data, buf + i, 4);
11405                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11406
11407                 page_off = offset % tp->nvram_pagesize;
11408
11409                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11410
11411                 tw32(NVRAM_ADDR, phy_addr);
11412
11413                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11414
11415                 if ((page_off == 0) || (i == 0))
11416                         nvram_cmd |= NVRAM_CMD_FIRST;
11417                 if (page_off == (tp->nvram_pagesize - 4))
11418                         nvram_cmd |= NVRAM_CMD_LAST;
11419
11420                 if (i == (len - 4))
11421                         nvram_cmd |= NVRAM_CMD_LAST;
11422
11423                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11424                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11425                     (tp->nvram_jedecnum == JEDEC_ST) &&
11426                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11427
11428                         if ((ret = tg3_nvram_exec_cmd(tp,
11429                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11430                                 NVRAM_CMD_DONE)))
11431
11432                                 break;
11433                 }
11434                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11435                         /* We always do complete word writes to eeprom. */
11436                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11437                 }
11438
11439                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11440                         break;
11441         }
11442         return ret;
11443 }
11444
11445 /* offset and length are dword aligned */
11446 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11447 {
11448         int ret;
11449
11450         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11451                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11452                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11453                 udelay(40);
11454         }
11455
11456         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11457                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11458         }
11459         else {
11460                 u32 grc_mode;
11461
11462                 ret = tg3_nvram_lock(tp);
11463                 if (ret)
11464                         return ret;
11465
11466                 tg3_enable_nvram_access(tp);
11467                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11468                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11469                         tw32(NVRAM_WRITE1, 0x406);
11470
11471                 grc_mode = tr32(GRC_MODE);
11472                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11473
11474                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11475                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11476
11477                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11478                                 buf);
11479                 }
11480                 else {
11481                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11482                                 buf);
11483                 }
11484
11485                 grc_mode = tr32(GRC_MODE);
11486                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11487
11488                 tg3_disable_nvram_access(tp);
11489                 tg3_nvram_unlock(tp);
11490         }
11491
11492         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11493                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11494                 udelay(40);
11495         }
11496
11497         return ret;
11498 }
11499
11500 struct subsys_tbl_ent {
11501         u16 subsys_vendor, subsys_devid;
11502         u32 phy_id;
11503 };
11504
11505 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11506         /* Broadcom boards. */
11507         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11508         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11509         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11510         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11511         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11512         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11513         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11514         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11515         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11516         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11517         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11518
11519         /* 3com boards. */
11520         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11521         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11522         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11523         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11524         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11525
11526         /* DELL boards. */
11527         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11528         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11529         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11530         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11531
11532         /* Compaq boards. */
11533         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11534         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11535         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11536         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11537         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11538
11539         /* IBM boards. */
11540         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11541 };
11542
11543 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11544 {
11545         int i;
11546
11547         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11548                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11549                      tp->pdev->subsystem_vendor) &&
11550                     (subsys_id_to_phy_id[i].subsys_devid ==
11551                      tp->pdev->subsystem_device))
11552                         return &subsys_id_to_phy_id[i];
11553         }
11554         return NULL;
11555 }
11556
11557 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11558 {
11559         u32 val;
11560         u16 pmcsr;
11561
11562         /* On some early chips the SRAM cannot be accessed in D3hot state,
11563          * so need make sure we're in D0.
11564          */
11565         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11566         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11567         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11568         msleep(1);
11569
11570         /* Make sure register accesses (indirect or otherwise)
11571          * will function correctly.
11572          */
11573         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11574                                tp->misc_host_ctrl);
11575
11576         /* The memory arbiter has to be enabled in order for SRAM accesses
11577          * to succeed.  Normally on powerup the tg3 chip firmware will make
11578          * sure it is enabled, but other entities such as system netboot
11579          * code might disable it.
11580          */
11581         val = tr32(MEMARB_MODE);
11582         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11583
11584         tp->phy_id = PHY_ID_INVALID;
11585         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11586
11587         /* Assume an onboard device and WOL capable by default.  */
11588         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11589
11590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11591                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11592                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11593                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11594                 }
11595                 val = tr32(VCPU_CFGSHDW);
11596                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11597                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11598                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11599                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11600                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11601                 goto done;
11602         }
11603
11604         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11605         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11606                 u32 nic_cfg, led_cfg;
11607                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11608                 int eeprom_phy_serdes = 0;
11609
11610                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11611                 tp->nic_sram_data_cfg = nic_cfg;
11612
11613                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11614                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11615                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11616                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11617                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11618                     (ver > 0) && (ver < 0x100))
11619                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11620
11621                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11622                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11623
11624                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11625                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11626                         eeprom_phy_serdes = 1;
11627
11628                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11629                 if (nic_phy_id != 0) {
11630                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11631                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11632
11633                         eeprom_phy_id  = (id1 >> 16) << 10;
11634                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11635                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11636                 } else
11637                         eeprom_phy_id = 0;
11638
11639                 tp->phy_id = eeprom_phy_id;
11640                 if (eeprom_phy_serdes) {
11641                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11642                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11643                         else
11644                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11645                 }
11646
11647                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11648                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11649                                     SHASTA_EXT_LED_MODE_MASK);
11650                 else
11651                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11652
11653                 switch (led_cfg) {
11654                 default:
11655                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11656                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11657                         break;
11658
11659                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11660                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11661                         break;
11662
11663                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11664                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11665
11666                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11667                          * read on some older 5700/5701 bootcode.
11668                          */
11669                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11670                             ASIC_REV_5700 ||
11671                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11672                             ASIC_REV_5701)
11673                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11674
11675                         break;
11676
11677                 case SHASTA_EXT_LED_SHARED:
11678                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11679                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11680                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11681                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11682                                                  LED_CTRL_MODE_PHY_2);
11683                         break;
11684
11685                 case SHASTA_EXT_LED_MAC:
11686                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11687                         break;
11688
11689                 case SHASTA_EXT_LED_COMBO:
11690                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11691                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11692                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11693                                                  LED_CTRL_MODE_PHY_2);
11694                         break;
11695
11696                 }
11697
11698                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11699                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11700                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11701                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11702
11703                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11704                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11705
11706                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11707                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11708                         if ((tp->pdev->subsystem_vendor ==
11709                              PCI_VENDOR_ID_ARIMA) &&
11710                             (tp->pdev->subsystem_device == 0x205a ||
11711                              tp->pdev->subsystem_device == 0x2063))
11712                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11713                 } else {
11714                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11715                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11716                 }
11717
11718                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11719                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11720                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11721                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11722                 }
11723
11724                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11725                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11726                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11727
11728                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11729                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11730                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11731
11732                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11733                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11734                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11735
11736                 if (cfg2 & (1 << 17))
11737                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11738
11739                 /* serdes signal pre-emphasis in register 0x590 set by */
11740                 /* bootcode if bit 18 is set */
11741                 if (cfg2 & (1 << 18))
11742                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11743
11744                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11745                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11746                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11747                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11748
11749                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11750                         u32 cfg3;
11751
11752                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11753                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11754                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11755                 }
11756
11757                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11758                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11759                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11760                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11761                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11762                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11763         }
11764 done:
11765         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11766         device_set_wakeup_enable(&tp->pdev->dev,
11767                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11768 }
11769
11770 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11771 {
11772         int i;
11773         u32 val;
11774
11775         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11776         tw32(OTP_CTRL, cmd);
11777
11778         /* Wait for up to 1 ms for command to execute. */
11779         for (i = 0; i < 100; i++) {
11780                 val = tr32(OTP_STATUS);
11781                 if (val & OTP_STATUS_CMD_DONE)
11782                         break;
11783                 udelay(10);
11784         }
11785
11786         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11787 }
11788
11789 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11790  * configuration is a 32-bit value that straddles the alignment boundary.
11791  * We do two 32-bit reads and then shift and merge the results.
11792  */
11793 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11794 {
11795         u32 bhalf_otp, thalf_otp;
11796
11797         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11798
11799         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11800                 return 0;
11801
11802         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11803
11804         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11805                 return 0;
11806
11807         thalf_otp = tr32(OTP_READ_DATA);
11808
11809         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11810
11811         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11812                 return 0;
11813
11814         bhalf_otp = tr32(OTP_READ_DATA);
11815
11816         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11817 }
11818
11819 static int __devinit tg3_phy_probe(struct tg3 *tp)
11820 {
11821         u32 hw_phy_id_1, hw_phy_id_2;
11822         u32 hw_phy_id, hw_phy_id_masked;
11823         int err;
11824
11825         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11826                 return tg3_phy_init(tp);
11827
11828         /* Reading the PHY ID register can conflict with ASF
11829          * firmware access to the PHY hardware.
11830          */
11831         err = 0;
11832         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11833             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11834                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11835         } else {
11836                 /* Now read the physical PHY_ID from the chip and verify
11837                  * that it is sane.  If it doesn't look good, we fall back
11838                  * to either the hard-coded table based PHY_ID and failing
11839                  * that the value found in the eeprom area.
11840                  */
11841                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11842                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11843
11844                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11845                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11846                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11847
11848                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11849         }
11850
11851         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11852                 tp->phy_id = hw_phy_id;
11853                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11854                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11855                 else
11856                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11857         } else {
11858                 if (tp->phy_id != PHY_ID_INVALID) {
11859                         /* Do nothing, phy ID already set up in
11860                          * tg3_get_eeprom_hw_cfg().
11861                          */
11862                 } else {
11863                         struct subsys_tbl_ent *p;
11864
11865                         /* No eeprom signature?  Try the hardcoded
11866                          * subsys device table.
11867                          */
11868                         p = lookup_by_subsys(tp);
11869                         if (!p)
11870                                 return -ENODEV;
11871
11872                         tp->phy_id = p->phy_id;
11873                         if (!tp->phy_id ||
11874                             tp->phy_id == PHY_ID_BCM8002)
11875                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11876                 }
11877         }
11878
11879         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11880             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11881             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11882                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11883
11884                 tg3_readphy(tp, MII_BMSR, &bmsr);
11885                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11886                     (bmsr & BMSR_LSTATUS))
11887                         goto skip_phy_reset;
11888
11889                 err = tg3_phy_reset(tp);
11890                 if (err)
11891                         return err;
11892
11893                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11894                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11895                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11896                 tg3_ctrl = 0;
11897                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11898                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11899                                     MII_TG3_CTRL_ADV_1000_FULL);
11900                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11901                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11902                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11903                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11904                 }
11905
11906                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11907                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11908                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11909                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11910                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11911
11912                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11913                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11914
11915                         tg3_writephy(tp, MII_BMCR,
11916                                      BMCR_ANENABLE | BMCR_ANRESTART);
11917                 }
11918                 tg3_phy_set_wirespeed(tp);
11919
11920                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11921                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11922                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11923         }
11924
11925 skip_phy_reset:
11926         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11927                 err = tg3_init_5401phy_dsp(tp);
11928                 if (err)
11929                         return err;
11930         }
11931
11932         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11933                 err = tg3_init_5401phy_dsp(tp);
11934         }
11935
11936         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11937                 tp->link_config.advertising =
11938                         (ADVERTISED_1000baseT_Half |
11939                          ADVERTISED_1000baseT_Full |
11940                          ADVERTISED_Autoneg |
11941                          ADVERTISED_FIBRE);
11942         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11943                 tp->link_config.advertising &=
11944                         ~(ADVERTISED_1000baseT_Half |
11945                           ADVERTISED_1000baseT_Full);
11946
11947         return err;
11948 }
11949
11950 static void __devinit tg3_read_partno(struct tg3 *tp)
11951 {
11952         unsigned char vpd_data[256];   /* in little-endian format */
11953         unsigned int i;
11954         u32 magic;
11955
11956         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11957             tg3_nvram_read(tp, 0x0, &magic))
11958                 goto out_not_found;
11959
11960         if (magic == TG3_EEPROM_MAGIC) {
11961                 for (i = 0; i < 256; i += 4) {
11962                         u32 tmp;
11963
11964                         /* The data is in little-endian format in NVRAM.
11965                          * Use the big-endian read routines to preserve
11966                          * the byte order as it exists in NVRAM.
11967                          */
11968                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11969                                 goto out_not_found;
11970
11971                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11972                 }
11973         } else {
11974                 int vpd_cap;
11975
11976                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11977                 for (i = 0; i < 256; i += 4) {
11978                         u32 tmp, j = 0;
11979                         __le32 v;
11980                         u16 tmp16;
11981
11982                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11983                                               i);
11984                         while (j++ < 100) {
11985                                 pci_read_config_word(tp->pdev, vpd_cap +
11986                                                      PCI_VPD_ADDR, &tmp16);
11987                                 if (tmp16 & 0x8000)
11988                                         break;
11989                                 msleep(1);
11990                         }
11991                         if (!(tmp16 & 0x8000))
11992                                 goto out_not_found;
11993
11994                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11995                                               &tmp);
11996                         v = cpu_to_le32(tmp);
11997                         memcpy(&vpd_data[i], &v, sizeof(v));
11998                 }
11999         }
12000
12001         /* Now parse and find the part number. */
12002         for (i = 0; i < 254; ) {
12003                 unsigned char val = vpd_data[i];
12004                 unsigned int block_end;
12005
12006                 if (val == 0x82 || val == 0x91) {
12007                         i = (i + 3 +
12008                              (vpd_data[i + 1] +
12009                               (vpd_data[i + 2] << 8)));
12010                         continue;
12011                 }
12012
12013                 if (val != 0x90)
12014                         goto out_not_found;
12015
12016                 block_end = (i + 3 +
12017                              (vpd_data[i + 1] +
12018                               (vpd_data[i + 2] << 8)));
12019                 i += 3;
12020
12021                 if (block_end > 256)
12022                         goto out_not_found;
12023
12024                 while (i < (block_end - 2)) {
12025                         if (vpd_data[i + 0] == 'P' &&
12026                             vpd_data[i + 1] == 'N') {
12027                                 int partno_len = vpd_data[i + 2];
12028
12029                                 i += 3;
12030                                 if (partno_len > 24 || (partno_len + i) > 256)
12031                                         goto out_not_found;
12032
12033                                 memcpy(tp->board_part_number,
12034                                        &vpd_data[i], partno_len);
12035
12036                                 /* Success. */
12037                                 return;
12038                         }
12039                         i += 3 + vpd_data[i + 2];
12040                 }
12041
12042                 /* Part number not found. */
12043                 goto out_not_found;
12044         }
12045
12046 out_not_found:
12047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12048                 strcpy(tp->board_part_number, "BCM95906");
12049         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12050                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12051                 strcpy(tp->board_part_number, "BCM57780");
12052         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12053                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12054                 strcpy(tp->board_part_number, "BCM57760");
12055         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12056                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12057                 strcpy(tp->board_part_number, "BCM57790");
12058         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12059                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12060                 strcpy(tp->board_part_number, "BCM57788");
12061         else
12062                 strcpy(tp->board_part_number, "none");
12063 }
12064
12065 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12066 {
12067         u32 val;
12068
12069         if (tg3_nvram_read(tp, offset, &val) ||
12070             (val & 0xfc000000) != 0x0c000000 ||
12071             tg3_nvram_read(tp, offset + 4, &val) ||
12072             val != 0)
12073                 return 0;
12074
12075         return 1;
12076 }
12077
12078 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12079 {
12080         u32 val, offset, start, ver_offset;
12081         int i;
12082         bool newver = false;
12083
12084         if (tg3_nvram_read(tp, 0xc, &offset) ||
12085             tg3_nvram_read(tp, 0x4, &start))
12086                 return;
12087
12088         offset = tg3_nvram_logical_addr(tp, offset);
12089
12090         if (tg3_nvram_read(tp, offset, &val))
12091                 return;
12092
12093         if ((val & 0xfc000000) == 0x0c000000) {
12094                 if (tg3_nvram_read(tp, offset + 4, &val))
12095                         return;
12096
12097                 if (val == 0)
12098                         newver = true;
12099         }
12100
12101         if (newver) {
12102                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12103                         return;
12104
12105                 offset = offset + ver_offset - start;
12106                 for (i = 0; i < 16; i += 4) {
12107                         __be32 v;
12108                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12109                                 return;
12110
12111                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12112                 }
12113         } else {
12114                 u32 major, minor;
12115
12116                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12117                         return;
12118
12119                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12120                         TG3_NVM_BCVER_MAJSFT;
12121                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12122                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12123         }
12124 }
12125
12126 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12127 {
12128         u32 val, major, minor;
12129
12130         /* Use native endian representation */
12131         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12132                 return;
12133
12134         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12135                 TG3_NVM_HWSB_CFG1_MAJSFT;
12136         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12137                 TG3_NVM_HWSB_CFG1_MINSFT;
12138
12139         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12140 }
12141
12142 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12143 {
12144         u32 offset, major, minor, build;
12145
12146         tp->fw_ver[0] = 's';
12147         tp->fw_ver[1] = 'b';
12148         tp->fw_ver[2] = '\0';
12149
12150         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12151                 return;
12152
12153         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12154         case TG3_EEPROM_SB_REVISION_0:
12155                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12156                 break;
12157         case TG3_EEPROM_SB_REVISION_2:
12158                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12159                 break;
12160         case TG3_EEPROM_SB_REVISION_3:
12161                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12162                 break;
12163         default:
12164                 return;
12165         }
12166
12167         if (tg3_nvram_read(tp, offset, &val))
12168                 return;
12169
12170         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12171                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12172         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12173                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12174         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12175
12176         if (minor > 99 || build > 26)
12177                 return;
12178
12179         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12180
12181         if (build > 0) {
12182                 tp->fw_ver[8] = 'a' + build - 1;
12183                 tp->fw_ver[9] = '\0';
12184         }
12185 }
12186
12187 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12188 {
12189         u32 val, offset, start;
12190         int i, vlen;
12191
12192         for (offset = TG3_NVM_DIR_START;
12193              offset < TG3_NVM_DIR_END;
12194              offset += TG3_NVM_DIRENT_SIZE) {
12195                 if (tg3_nvram_read(tp, offset, &val))
12196                         return;
12197
12198                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12199                         break;
12200         }
12201
12202         if (offset == TG3_NVM_DIR_END)
12203                 return;
12204
12205         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12206                 start = 0x08000000;
12207         else if (tg3_nvram_read(tp, offset - 4, &start))
12208                 return;
12209
12210         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12211             !tg3_fw_img_is_valid(tp, offset) ||
12212             tg3_nvram_read(tp, offset + 8, &val))
12213                 return;
12214
12215         offset += val - start;
12216
12217         vlen = strlen(tp->fw_ver);
12218
12219         tp->fw_ver[vlen++] = ',';
12220         tp->fw_ver[vlen++] = ' ';
12221
12222         for (i = 0; i < 4; i++) {
12223                 __be32 v;
12224                 if (tg3_nvram_read_be32(tp, offset, &v))
12225                         return;
12226
12227                 offset += sizeof(v);
12228
12229                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12230                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12231                         break;
12232                 }
12233
12234                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12235                 vlen += sizeof(v);
12236         }
12237 }
12238
12239 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12240 {
12241         int vlen;
12242         u32 apedata;
12243
12244         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12245             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12246                 return;
12247
12248         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12249         if (apedata != APE_SEG_SIG_MAGIC)
12250                 return;
12251
12252         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12253         if (!(apedata & APE_FW_STATUS_READY))
12254                 return;
12255
12256         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12257
12258         vlen = strlen(tp->fw_ver);
12259
12260         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12261                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12262                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12263                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12264                  (apedata & APE_FW_VERSION_BLDMSK));
12265 }
12266
12267 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12268 {
12269         u32 val;
12270
12271         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12272                 tp->fw_ver[0] = 's';
12273                 tp->fw_ver[1] = 'b';
12274                 tp->fw_ver[2] = '\0';
12275
12276                 return;
12277         }
12278
12279         if (tg3_nvram_read(tp, 0, &val))
12280                 return;
12281
12282         if (val == TG3_EEPROM_MAGIC)
12283                 tg3_read_bc_ver(tp);
12284         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12285                 tg3_read_sb_ver(tp, val);
12286         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12287                 tg3_read_hwsb_ver(tp);
12288         else
12289                 return;
12290
12291         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12292              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12293                 return;
12294
12295         tg3_read_mgmtfw_ver(tp);
12296
12297         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12298 }
12299
12300 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12301
12302 static int __devinit tg3_get_invariants(struct tg3 *tp)
12303 {
12304         static struct pci_device_id write_reorder_chipsets[] = {
12305                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12306                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12307                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12308                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12309                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12310                              PCI_DEVICE_ID_VIA_8385_0) },
12311                 { },
12312         };
12313         u32 misc_ctrl_reg;
12314         u32 pci_state_reg, grc_misc_cfg;
12315         u32 val;
12316         u16 pci_cmd;
12317         int err;
12318
12319         /* Force memory write invalidate off.  If we leave it on,
12320          * then on 5700_BX chips we have to enable a workaround.
12321          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12322          * to match the cacheline size.  The Broadcom driver have this
12323          * workaround but turns MWI off all the times so never uses
12324          * it.  This seems to suggest that the workaround is insufficient.
12325          */
12326         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12327         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12328         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12329
12330         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12331          * has the register indirect write enable bit set before
12332          * we try to access any of the MMIO registers.  It is also
12333          * critical that the PCI-X hw workaround situation is decided
12334          * before that as well.
12335          */
12336         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12337                               &misc_ctrl_reg);
12338
12339         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12340                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12341         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12342                 u32 prod_id_asic_rev;
12343
12344                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12345                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12346                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12347                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12348                         pci_read_config_dword(tp->pdev,
12349                                               TG3PCI_GEN2_PRODID_ASICREV,
12350                                               &prod_id_asic_rev);
12351                 else
12352                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12353                                               &prod_id_asic_rev);
12354
12355                 tp->pci_chip_rev_id = prod_id_asic_rev;
12356         }
12357
12358         /* Wrong chip ID in 5752 A0. This code can be removed later
12359          * as A0 is not in production.
12360          */
12361         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12362                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12363
12364         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12365          * we need to disable memory and use config. cycles
12366          * only to access all registers. The 5702/03 chips
12367          * can mistakenly decode the special cycles from the
12368          * ICH chipsets as memory write cycles, causing corruption
12369          * of register and memory space. Only certain ICH bridges
12370          * will drive special cycles with non-zero data during the
12371          * address phase which can fall within the 5703's address
12372          * range. This is not an ICH bug as the PCI spec allows
12373          * non-zero address during special cycles. However, only
12374          * these ICH bridges are known to drive non-zero addresses
12375          * during special cycles.
12376          *
12377          * Since special cycles do not cross PCI bridges, we only
12378          * enable this workaround if the 5703 is on the secondary
12379          * bus of these ICH bridges.
12380          */
12381         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12382             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12383                 static struct tg3_dev_id {
12384                         u32     vendor;
12385                         u32     device;
12386                         u32     rev;
12387                 } ich_chipsets[] = {
12388                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12389                           PCI_ANY_ID },
12390                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12391                           PCI_ANY_ID },
12392                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12393                           0xa },
12394                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12395                           PCI_ANY_ID },
12396                         { },
12397                 };
12398                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12399                 struct pci_dev *bridge = NULL;
12400
12401                 while (pci_id->vendor != 0) {
12402                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12403                                                 bridge);
12404                         if (!bridge) {
12405                                 pci_id++;
12406                                 continue;
12407                         }
12408                         if (pci_id->rev != PCI_ANY_ID) {
12409                                 if (bridge->revision > pci_id->rev)
12410                                         continue;
12411                         }
12412                         if (bridge->subordinate &&
12413                             (bridge->subordinate->number ==
12414                              tp->pdev->bus->number)) {
12415
12416                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12417                                 pci_dev_put(bridge);
12418                                 break;
12419                         }
12420                 }
12421         }
12422
12423         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12424                 static struct tg3_dev_id {
12425                         u32     vendor;
12426                         u32     device;
12427                 } bridge_chipsets[] = {
12428                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12429                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12430                         { },
12431                 };
12432                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12433                 struct pci_dev *bridge = NULL;
12434
12435                 while (pci_id->vendor != 0) {
12436                         bridge = pci_get_device(pci_id->vendor,
12437                                                 pci_id->device,
12438                                                 bridge);
12439                         if (!bridge) {
12440                                 pci_id++;
12441                                 continue;
12442                         }
12443                         if (bridge->subordinate &&
12444                             (bridge->subordinate->number <=
12445                              tp->pdev->bus->number) &&
12446                             (bridge->subordinate->subordinate >=
12447                              tp->pdev->bus->number)) {
12448                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12449                                 pci_dev_put(bridge);
12450                                 break;
12451                         }
12452                 }
12453         }
12454
12455         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12456          * DMA addresses > 40-bit. This bridge may have other additional
12457          * 57xx devices behind it in some 4-port NIC designs for example.
12458          * Any tg3 device found behind the bridge will also need the 40-bit
12459          * DMA workaround.
12460          */
12461         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12462             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12463                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12464                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12465                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12466         }
12467         else {
12468                 struct pci_dev *bridge = NULL;
12469
12470                 do {
12471                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12472                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12473                                                 bridge);
12474                         if (bridge && bridge->subordinate &&
12475                             (bridge->subordinate->number <=
12476                              tp->pdev->bus->number) &&
12477                             (bridge->subordinate->subordinate >=
12478                              tp->pdev->bus->number)) {
12479                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12480                                 pci_dev_put(bridge);
12481                                 break;
12482                         }
12483                 } while (bridge);
12484         }
12485
12486         /* Initialize misc host control in PCI block. */
12487         tp->misc_host_ctrl |= (misc_ctrl_reg &
12488                                MISC_HOST_CTRL_CHIPREV);
12489         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12490                                tp->misc_host_ctrl);
12491
12492         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12493             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12494             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12495                 tp->pdev_peer = tg3_find_peer(tp);
12496
12497         /* Intentionally exclude ASIC_REV_5906 */
12498         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12499             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12500             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12501             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12502             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12503             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12504             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12505                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12506
12507         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12508             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12509             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12510             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12511             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12512                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12513
12514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12515             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12516                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12517
12518         /* 5700 B0 chips do not support checksumming correctly due
12519          * to hardware bugs.
12520          */
12521         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12522                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12523         else {
12524                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12525                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12526                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12527                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12528         }
12529
12530         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12531                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12532                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12533                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12534                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12535                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12536                      tp->pdev_peer == tp->pdev))
12537                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12538
12539                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12540                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12541                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12542                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12543                 } else {
12544                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12545                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12546                                 ASIC_REV_5750 &&
12547                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12548                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12549                 }
12550         }
12551
12552         tp->irq_max = 1;
12553
12554 #ifdef TG3_NAPI
12555         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12556                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12557                 tp->irq_max = TG3_IRQ_MAX_VECS;
12558         }
12559 #endif
12560
12561         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12562              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12563             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12564                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12565
12566         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12567                               &pci_state_reg);
12568
12569         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12570         if (tp->pcie_cap != 0) {
12571                 u16 lnkctl;
12572
12573                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12574
12575                 pcie_set_readrq(tp->pdev, 4096);
12576
12577                 pci_read_config_word(tp->pdev,
12578                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12579                                      &lnkctl);
12580                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12581                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12582                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12583                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12584                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12585                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12586                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12587                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12588                 }
12589         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12590                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12591         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12592                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12593                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12594                 if (!tp->pcix_cap) {
12595                         printk(KERN_ERR PFX "Cannot find PCI-X "
12596                                             "capability, aborting.\n");
12597                         return -EIO;
12598                 }
12599
12600                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12601                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12602         }
12603
12604         /* If we have an AMD 762 or VIA K8T800 chipset, write
12605          * reordering to the mailbox registers done by the host
12606          * controller can cause major troubles.  We read back from
12607          * every mailbox register write to force the writes to be
12608          * posted to the chip in order.
12609          */
12610         if (pci_dev_present(write_reorder_chipsets) &&
12611             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12612                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12613
12614         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12615                              &tp->pci_cacheline_sz);
12616         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12617                              &tp->pci_lat_timer);
12618         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12619             tp->pci_lat_timer < 64) {
12620                 tp->pci_lat_timer = 64;
12621                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12622                                       tp->pci_lat_timer);
12623         }
12624
12625         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12626                 /* 5700 BX chips need to have their TX producer index
12627                  * mailboxes written twice to workaround a bug.
12628                  */
12629                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12630
12631                 /* If we are in PCI-X mode, enable register write workaround.
12632                  *
12633                  * The workaround is to use indirect register accesses
12634                  * for all chip writes not to mailbox registers.
12635                  */
12636                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12637                         u32 pm_reg;
12638
12639                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12640
12641                         /* The chip can have it's power management PCI config
12642                          * space registers clobbered due to this bug.
12643                          * So explicitly force the chip into D0 here.
12644                          */
12645                         pci_read_config_dword(tp->pdev,
12646                                               tp->pm_cap + PCI_PM_CTRL,
12647                                               &pm_reg);
12648                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12649                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12650                         pci_write_config_dword(tp->pdev,
12651                                                tp->pm_cap + PCI_PM_CTRL,
12652                                                pm_reg);
12653
12654                         /* Also, force SERR#/PERR# in PCI command. */
12655                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12656                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12657                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12658                 }
12659         }
12660
12661         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12662                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12663         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12664                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12665
12666         /* Chip-specific fixup from Broadcom driver */
12667         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12668             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12669                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12670                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12671         }
12672
12673         /* Default fast path register access methods */
12674         tp->read32 = tg3_read32;
12675         tp->write32 = tg3_write32;
12676         tp->read32_mbox = tg3_read32;
12677         tp->write32_mbox = tg3_write32;
12678         tp->write32_tx_mbox = tg3_write32;
12679         tp->write32_rx_mbox = tg3_write32;
12680
12681         /* Various workaround register access methods */
12682         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12683                 tp->write32 = tg3_write_indirect_reg32;
12684         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12685                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12686                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12687                 /*
12688                  * Back to back register writes can cause problems on these
12689                  * chips, the workaround is to read back all reg writes
12690                  * except those to mailbox regs.
12691                  *
12692                  * See tg3_write_indirect_reg32().
12693                  */
12694                 tp->write32 = tg3_write_flush_reg32;
12695         }
12696
12697         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12698             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12699                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12700                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12701                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12702         }
12703
12704         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12705                 tp->read32 = tg3_read_indirect_reg32;
12706                 tp->write32 = tg3_write_indirect_reg32;
12707                 tp->read32_mbox = tg3_read_indirect_mbox;
12708                 tp->write32_mbox = tg3_write_indirect_mbox;
12709                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12710                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12711
12712                 iounmap(tp->regs);
12713                 tp->regs = NULL;
12714
12715                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12716                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12717                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12718         }
12719         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12720                 tp->read32_mbox = tg3_read32_mbox_5906;
12721                 tp->write32_mbox = tg3_write32_mbox_5906;
12722                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12723                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12724         }
12725
12726         if (tp->write32 == tg3_write_indirect_reg32 ||
12727             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12728              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12729               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12730                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12731
12732         /* Get eeprom hw config before calling tg3_set_power_state().
12733          * In particular, the TG3_FLG2_IS_NIC flag must be
12734          * determined before calling tg3_set_power_state() so that
12735          * we know whether or not to switch out of Vaux power.
12736          * When the flag is set, it means that GPIO1 is used for eeprom
12737          * write protect and also implies that it is a LOM where GPIOs
12738          * are not used to switch power.
12739          */
12740         tg3_get_eeprom_hw_cfg(tp);
12741
12742         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12743                 /* Allow reads and writes to the
12744                  * APE register and memory space.
12745                  */
12746                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12747                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12748                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12749                                        pci_state_reg);
12750         }
12751
12752         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12753             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12754             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12755             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12756             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12757                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12758
12759         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12760          * GPIO1 driven high will bring 5700's external PHY out of reset.
12761          * It is also used as eeprom write protect on LOMs.
12762          */
12763         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12764         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12765             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12766                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12767                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12768         /* Unused GPIO3 must be driven as output on 5752 because there
12769          * are no pull-up resistors on unused GPIO pins.
12770          */
12771         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12772                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12773
12774         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12775             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12776                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12777
12778         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12779             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12780                 /* Turn off the debug UART. */
12781                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12782                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12783                         /* Keep VMain power. */
12784                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12785                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12786         }
12787
12788         /* Force the chip into D0. */
12789         err = tg3_set_power_state(tp, PCI_D0);
12790         if (err) {
12791                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12792                        pci_name(tp->pdev));
12793                 return err;
12794         }
12795
12796         /* Derive initial jumbo mode from MTU assigned in
12797          * ether_setup() via the alloc_etherdev() call
12798          */
12799         if (tp->dev->mtu > ETH_DATA_LEN &&
12800             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12801                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12802
12803         /* Determine WakeOnLan speed to use. */
12804         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12805             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12806             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12807             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12808                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12809         } else {
12810                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12811         }
12812
12813         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12814                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12815
12816         /* A few boards don't want Ethernet@WireSpeed phy feature */
12817         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12818             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12819              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12820              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12821             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12822             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12823                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12824
12825         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12826             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12827                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12828         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12829                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12830
12831         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12832             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12833             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12834             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12835             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
12836                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12837                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12838                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12839                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12840                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12841                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12842                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12843                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12844                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12845                 } else
12846                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12847         }
12848
12849         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12850             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12851                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12852                 if (tp->phy_otp == 0)
12853                         tp->phy_otp = TG3_OTP_DEFAULT;
12854         }
12855
12856         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12857                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12858         else
12859                 tp->mi_mode = MAC_MI_MODE_BASE;
12860
12861         tp->coalesce_mode = 0;
12862         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12863             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12864                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12865
12866         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12867             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12868                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12869
12870         if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12871              tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12872             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12873                 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12874
12875         err = tg3_mdio_init(tp);
12876         if (err)
12877                 return err;
12878
12879         /* Initialize data/descriptor byte/word swapping. */
12880         val = tr32(GRC_MODE);
12881         val &= GRC_MODE_HOST_STACKUP;
12882         tw32(GRC_MODE, val | tp->grc_mode);
12883
12884         tg3_switch_clocks(tp);
12885
12886         /* Clear this out for sanity. */
12887         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12888
12889         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12890                               &pci_state_reg);
12891         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12892             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12893                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12894
12895                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12896                     chiprevid == CHIPREV_ID_5701_B0 ||
12897                     chiprevid == CHIPREV_ID_5701_B2 ||
12898                     chiprevid == CHIPREV_ID_5701_B5) {
12899                         void __iomem *sram_base;
12900
12901                         /* Write some dummy words into the SRAM status block
12902                          * area, see if it reads back correctly.  If the return
12903                          * value is bad, force enable the PCIX workaround.
12904                          */
12905                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12906
12907                         writel(0x00000000, sram_base);
12908                         writel(0x00000000, sram_base + 4);
12909                         writel(0xffffffff, sram_base + 4);
12910                         if (readl(sram_base) != 0x00000000)
12911                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12912                 }
12913         }
12914
12915         udelay(50);
12916         tg3_nvram_init(tp);
12917
12918         grc_misc_cfg = tr32(GRC_MISC_CFG);
12919         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12920
12921         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12922             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12923              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12924                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12925
12926         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12927             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12928                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12929         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12930                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12931                                       HOSTCC_MODE_CLRTICK_TXBD);
12932
12933                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12934                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12935                                        tp->misc_host_ctrl);
12936         }
12937
12938         /* Preserve the APE MAC_MODE bits */
12939         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12940                 tp->mac_mode = tr32(MAC_MODE) |
12941                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12942         else
12943                 tp->mac_mode = TG3_DEF_MAC_MODE;
12944
12945         /* these are limited to 10/100 only */
12946         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12947              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12948             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12949              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12950              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12951               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12952               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12953             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12954              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12955               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12956               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12957             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12958             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
12959                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12960
12961         err = tg3_phy_probe(tp);
12962         if (err) {
12963                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12964                        pci_name(tp->pdev), err);
12965                 /* ... but do not return immediately ... */
12966                 tg3_mdio_fini(tp);
12967         }
12968
12969         tg3_read_partno(tp);
12970         tg3_read_fw_ver(tp);
12971
12972         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12973                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12974         } else {
12975                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12976                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12977                 else
12978                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12979         }
12980
12981         /* 5700 {AX,BX} chips have a broken status block link
12982          * change bit implementation, so we must use the
12983          * status register in those cases.
12984          */
12985         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12986                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12987         else
12988                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12989
12990         /* The led_ctrl is set during tg3_phy_probe, here we might
12991          * have to force the link status polling mechanism based
12992          * upon subsystem IDs.
12993          */
12994         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12995             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12996             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12997                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12998                                   TG3_FLAG_USE_LINKCHG_REG);
12999         }
13000
13001         /* For all SERDES we poll the MAC status register. */
13002         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13003                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13004         else
13005                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13006
13007         tp->rx_offset = NET_IP_ALIGN;
13008         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13009             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13010                 tp->rx_offset = 0;
13011
13012         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13013
13014         /* Increment the rx prod index on the rx std ring by at most
13015          * 8 for these chips to workaround hw errata.
13016          */
13017         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13020                 tp->rx_std_max_post = 8;
13021
13022         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13023                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13024                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13025
13026         return err;
13027 }
13028
13029 #ifdef CONFIG_SPARC
13030 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13031 {
13032         struct net_device *dev = tp->dev;
13033         struct pci_dev *pdev = tp->pdev;
13034         struct device_node *dp = pci_device_to_OF_node(pdev);
13035         const unsigned char *addr;
13036         int len;
13037
13038         addr = of_get_property(dp, "local-mac-address", &len);
13039         if (addr && len == 6) {
13040                 memcpy(dev->dev_addr, addr, 6);
13041                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13042                 return 0;
13043         }
13044         return -ENODEV;
13045 }
13046
13047 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13048 {
13049         struct net_device *dev = tp->dev;
13050
13051         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13052         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13053         return 0;
13054 }
13055 #endif
13056
13057 static int __devinit tg3_get_device_address(struct tg3 *tp)
13058 {
13059         struct net_device *dev = tp->dev;
13060         u32 hi, lo, mac_offset;
13061         int addr_ok = 0;
13062
13063 #ifdef CONFIG_SPARC
13064         if (!tg3_get_macaddr_sparc(tp))
13065                 return 0;
13066 #endif
13067
13068         mac_offset = 0x7c;
13069         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13070             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13071                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13072                         mac_offset = 0xcc;
13073                 if (tg3_nvram_lock(tp))
13074                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13075                 else
13076                         tg3_nvram_unlock(tp);
13077         }
13078         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13079                 mac_offset = 0x10;
13080
13081         /* First try to get it from MAC address mailbox. */
13082         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13083         if ((hi >> 16) == 0x484b) {
13084                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13085                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13086
13087                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13088                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13089                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13090                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13091                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13092
13093                 /* Some old bootcode may report a 0 MAC address in SRAM */
13094                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13095         }
13096         if (!addr_ok) {
13097                 /* Next, try NVRAM. */
13098                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13099                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13100                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13101                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13102                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13103                 }
13104                 /* Finally just fetch it out of the MAC control regs. */
13105                 else {
13106                         hi = tr32(MAC_ADDR_0_HIGH);
13107                         lo = tr32(MAC_ADDR_0_LOW);
13108
13109                         dev->dev_addr[5] = lo & 0xff;
13110                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13111                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13112                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13113                         dev->dev_addr[1] = hi & 0xff;
13114                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13115                 }
13116         }
13117
13118         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13119 #ifdef CONFIG_SPARC
13120                 if (!tg3_get_default_macaddr_sparc(tp))
13121                         return 0;
13122 #endif
13123                 return -EINVAL;
13124         }
13125         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13126         return 0;
13127 }
13128
13129 #define BOUNDARY_SINGLE_CACHELINE       1
13130 #define BOUNDARY_MULTI_CACHELINE        2
13131
13132 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13133 {
13134         int cacheline_size;
13135         u8 byte;
13136         int goal;
13137
13138         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13139         if (byte == 0)
13140                 cacheline_size = 1024;
13141         else
13142                 cacheline_size = (int) byte * 4;
13143
13144         /* On 5703 and later chips, the boundary bits have no
13145          * effect.
13146          */
13147         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13148             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13149             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13150                 goto out;
13151
13152 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13153         goal = BOUNDARY_MULTI_CACHELINE;
13154 #else
13155 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13156         goal = BOUNDARY_SINGLE_CACHELINE;
13157 #else
13158         goal = 0;
13159 #endif
13160 #endif
13161
13162         if (!goal)
13163                 goto out;
13164
13165         /* PCI controllers on most RISC systems tend to disconnect
13166          * when a device tries to burst across a cache-line boundary.
13167          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13168          *
13169          * Unfortunately, for PCI-E there are only limited
13170          * write-side controls for this, and thus for reads
13171          * we will still get the disconnects.  We'll also waste
13172          * these PCI cycles for both read and write for chips
13173          * other than 5700 and 5701 which do not implement the
13174          * boundary bits.
13175          */
13176         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13177             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13178                 switch (cacheline_size) {
13179                 case 16:
13180                 case 32:
13181                 case 64:
13182                 case 128:
13183                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13184                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13185                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13186                         } else {
13187                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13188                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13189                         }
13190                         break;
13191
13192                 case 256:
13193                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13194                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13195                         break;
13196
13197                 default:
13198                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13199                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13200                         break;
13201                 }
13202         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13203                 switch (cacheline_size) {
13204                 case 16:
13205                 case 32:
13206                 case 64:
13207                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13208                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13209                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13210                                 break;
13211                         }
13212                         /* fallthrough */
13213                 case 128:
13214                 default:
13215                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13216                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13217                         break;
13218                 }
13219         } else {
13220                 switch (cacheline_size) {
13221                 case 16:
13222                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13223                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13224                                         DMA_RWCTRL_WRITE_BNDRY_16);
13225                                 break;
13226                         }
13227                         /* fallthrough */
13228                 case 32:
13229                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13230                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13231                                         DMA_RWCTRL_WRITE_BNDRY_32);
13232                                 break;
13233                         }
13234                         /* fallthrough */
13235                 case 64:
13236                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13237                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13238                                         DMA_RWCTRL_WRITE_BNDRY_64);
13239                                 break;
13240                         }
13241                         /* fallthrough */
13242                 case 128:
13243                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13244                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13245                                         DMA_RWCTRL_WRITE_BNDRY_128);
13246                                 break;
13247                         }
13248                         /* fallthrough */
13249                 case 256:
13250                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13251                                 DMA_RWCTRL_WRITE_BNDRY_256);
13252                         break;
13253                 case 512:
13254                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13255                                 DMA_RWCTRL_WRITE_BNDRY_512);
13256                         break;
13257                 case 1024:
13258                 default:
13259                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13260                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13261                         break;
13262                 }
13263         }
13264
13265 out:
13266         return val;
13267 }
13268
13269 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13270 {
13271         struct tg3_internal_buffer_desc test_desc;
13272         u32 sram_dma_descs;
13273         int i, ret;
13274
13275         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13276
13277         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13278         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13279         tw32(RDMAC_STATUS, 0);
13280         tw32(WDMAC_STATUS, 0);
13281
13282         tw32(BUFMGR_MODE, 0);
13283         tw32(FTQ_RESET, 0);
13284
13285         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13286         test_desc.addr_lo = buf_dma & 0xffffffff;
13287         test_desc.nic_mbuf = 0x00002100;
13288         test_desc.len = size;
13289
13290         /*
13291          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13292          * the *second* time the tg3 driver was getting loaded after an
13293          * initial scan.
13294          *
13295          * Broadcom tells me:
13296          *   ...the DMA engine is connected to the GRC block and a DMA
13297          *   reset may affect the GRC block in some unpredictable way...
13298          *   The behavior of resets to individual blocks has not been tested.
13299          *
13300          * Broadcom noted the GRC reset will also reset all sub-components.
13301          */
13302         if (to_device) {
13303                 test_desc.cqid_sqid = (13 << 8) | 2;
13304
13305                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13306                 udelay(40);
13307         } else {
13308                 test_desc.cqid_sqid = (16 << 8) | 7;
13309
13310                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13311                 udelay(40);
13312         }
13313         test_desc.flags = 0x00000005;
13314
13315         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13316                 u32 val;
13317
13318                 val = *(((u32 *)&test_desc) + i);
13319                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13320                                        sram_dma_descs + (i * sizeof(u32)));
13321                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13322         }
13323         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13324
13325         if (to_device) {
13326                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13327         } else {
13328                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13329         }
13330
13331         ret = -ENODEV;
13332         for (i = 0; i < 40; i++) {
13333                 u32 val;
13334
13335                 if (to_device)
13336                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13337                 else
13338                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13339                 if ((val & 0xffff) == sram_dma_descs) {
13340                         ret = 0;
13341                         break;
13342                 }
13343
13344                 udelay(100);
13345         }
13346
13347         return ret;
13348 }
13349
13350 #define TEST_BUFFER_SIZE        0x2000
13351
13352 static int __devinit tg3_test_dma(struct tg3 *tp)
13353 {
13354         dma_addr_t buf_dma;
13355         u32 *buf, saved_dma_rwctrl;
13356         int ret;
13357
13358         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13359         if (!buf) {
13360                 ret = -ENOMEM;
13361                 goto out_nofree;
13362         }
13363
13364         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13365                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13366
13367         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13368
13369         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13370                 /* DMA read watermark not used on PCIE */
13371                 tp->dma_rwctrl |= 0x00180000;
13372         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13373                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13374                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13375                         tp->dma_rwctrl |= 0x003f0000;
13376                 else
13377                         tp->dma_rwctrl |= 0x003f000f;
13378         } else {
13379                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13380                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13381                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13382                         u32 read_water = 0x7;
13383
13384                         /* If the 5704 is behind the EPB bridge, we can
13385                          * do the less restrictive ONE_DMA workaround for
13386                          * better performance.
13387                          */
13388                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13389                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13390                                 tp->dma_rwctrl |= 0x8000;
13391                         else if (ccval == 0x6 || ccval == 0x7)
13392                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13393
13394                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13395                                 read_water = 4;
13396                         /* Set bit 23 to enable PCIX hw bug fix */
13397                         tp->dma_rwctrl |=
13398                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13399                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13400                                 (1 << 23);
13401                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13402                         /* 5780 always in PCIX mode */
13403                         tp->dma_rwctrl |= 0x00144000;
13404                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13405                         /* 5714 always in PCIX mode */
13406                         tp->dma_rwctrl |= 0x00148000;
13407                 } else {
13408                         tp->dma_rwctrl |= 0x001b000f;
13409                 }
13410         }
13411
13412         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13413             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13414                 tp->dma_rwctrl &= 0xfffffff0;
13415
13416         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13417             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13418                 /* Remove this if it causes problems for some boards. */
13419                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13420
13421                 /* On 5700/5701 chips, we need to set this bit.
13422                  * Otherwise the chip will issue cacheline transactions
13423                  * to streamable DMA memory with not all the byte
13424                  * enables turned on.  This is an error on several
13425                  * RISC PCI controllers, in particular sparc64.
13426                  *
13427                  * On 5703/5704 chips, this bit has been reassigned
13428                  * a different meaning.  In particular, it is used
13429                  * on those chips to enable a PCI-X workaround.
13430                  */
13431                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13432         }
13433
13434         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13435
13436 #if 0
13437         /* Unneeded, already done by tg3_get_invariants.  */
13438         tg3_switch_clocks(tp);
13439 #endif
13440
13441         ret = 0;
13442         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13443             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13444                 goto out;
13445
13446         /* It is best to perform DMA test with maximum write burst size
13447          * to expose the 5700/5701 write DMA bug.
13448          */
13449         saved_dma_rwctrl = tp->dma_rwctrl;
13450         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13451         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13452
13453         while (1) {
13454                 u32 *p = buf, i;
13455
13456                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13457                         p[i] = i;
13458
13459                 /* Send the buffer to the chip. */
13460                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13461                 if (ret) {
13462                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13463                         break;
13464                 }
13465
13466 #if 0
13467                 /* validate data reached card RAM correctly. */
13468                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13469                         u32 val;
13470                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13471                         if (le32_to_cpu(val) != p[i]) {
13472                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13473                                 /* ret = -ENODEV here? */
13474                         }
13475                         p[i] = 0;
13476                 }
13477 #endif
13478                 /* Now read it back. */
13479                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13480                 if (ret) {
13481                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13482
13483                         break;
13484                 }
13485
13486                 /* Verify it. */
13487                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13488                         if (p[i] == i)
13489                                 continue;
13490
13491                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13492                             DMA_RWCTRL_WRITE_BNDRY_16) {
13493                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13494                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13495                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13496                                 break;
13497                         } else {
13498                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13499                                 ret = -ENODEV;
13500                                 goto out;
13501                         }
13502                 }
13503
13504                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13505                         /* Success. */
13506                         ret = 0;
13507                         break;
13508                 }
13509         }
13510         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13511             DMA_RWCTRL_WRITE_BNDRY_16) {
13512                 static struct pci_device_id dma_wait_state_chipsets[] = {
13513                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13514                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13515                         { },
13516                 };
13517
13518                 /* DMA test passed without adjusting DMA boundary,
13519                  * now look for chipsets that are known to expose the
13520                  * DMA bug without failing the test.
13521                  */
13522                 if (pci_dev_present(dma_wait_state_chipsets)) {
13523                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13524                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13525                 }
13526                 else
13527                         /* Safe to use the calculated DMA boundary. */
13528                         tp->dma_rwctrl = saved_dma_rwctrl;
13529
13530                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13531         }
13532
13533 out:
13534         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13535 out_nofree:
13536         return ret;
13537 }
13538
13539 static void __devinit tg3_init_link_config(struct tg3 *tp)
13540 {
13541         tp->link_config.advertising =
13542                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13543                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13544                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13545                  ADVERTISED_Autoneg | ADVERTISED_MII);
13546         tp->link_config.speed = SPEED_INVALID;
13547         tp->link_config.duplex = DUPLEX_INVALID;
13548         tp->link_config.autoneg = AUTONEG_ENABLE;
13549         tp->link_config.active_speed = SPEED_INVALID;
13550         tp->link_config.active_duplex = DUPLEX_INVALID;
13551         tp->link_config.phy_is_low_power = 0;
13552         tp->link_config.orig_speed = SPEED_INVALID;
13553         tp->link_config.orig_duplex = DUPLEX_INVALID;
13554         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13555 }
13556
13557 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13558 {
13559         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13560             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13561                 tp->bufmgr_config.mbuf_read_dma_low_water =
13562                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13563                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13564                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13565                 tp->bufmgr_config.mbuf_high_water =
13566                         DEFAULT_MB_HIGH_WATER_5705;
13567                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13568                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13569                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13570                         tp->bufmgr_config.mbuf_high_water =
13571                                 DEFAULT_MB_HIGH_WATER_5906;
13572                 }
13573
13574                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13575                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13576                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13577                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13578                 tp->bufmgr_config.mbuf_high_water_jumbo =
13579                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13580         } else {
13581                 tp->bufmgr_config.mbuf_read_dma_low_water =
13582                         DEFAULT_MB_RDMA_LOW_WATER;
13583                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13584                         DEFAULT_MB_MACRX_LOW_WATER;
13585                 tp->bufmgr_config.mbuf_high_water =
13586                         DEFAULT_MB_HIGH_WATER;
13587
13588                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13589                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13590                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13591                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13592                 tp->bufmgr_config.mbuf_high_water_jumbo =
13593                         DEFAULT_MB_HIGH_WATER_JUMBO;
13594         }
13595
13596         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13597         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13598 }
13599
13600 static char * __devinit tg3_phy_string(struct tg3 *tp)
13601 {
13602         switch (tp->phy_id & PHY_ID_MASK) {
13603         case PHY_ID_BCM5400:    return "5400";
13604         case PHY_ID_BCM5401:    return "5401";
13605         case PHY_ID_BCM5411:    return "5411";
13606         case PHY_ID_BCM5701:    return "5701";
13607         case PHY_ID_BCM5703:    return "5703";
13608         case PHY_ID_BCM5704:    return "5704";
13609         case PHY_ID_BCM5705:    return "5705";
13610         case PHY_ID_BCM5750:    return "5750";
13611         case PHY_ID_BCM5752:    return "5752";
13612         case PHY_ID_BCM5714:    return "5714";
13613         case PHY_ID_BCM5780:    return "5780";
13614         case PHY_ID_BCM5755:    return "5755";
13615         case PHY_ID_BCM5787:    return "5787";
13616         case PHY_ID_BCM5784:    return "5784";
13617         case PHY_ID_BCM5756:    return "5722/5756";
13618         case PHY_ID_BCM5906:    return "5906";
13619         case PHY_ID_BCM5761:    return "5761";
13620         case PHY_ID_BCM8002:    return "8002/serdes";
13621         case 0:                 return "serdes";
13622         default:                return "unknown";
13623         }
13624 }
13625
13626 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13627 {
13628         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13629                 strcpy(str, "PCI Express");
13630                 return str;
13631         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13632                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13633
13634                 strcpy(str, "PCIX:");
13635
13636                 if ((clock_ctrl == 7) ||
13637                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13638                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13639                         strcat(str, "133MHz");
13640                 else if (clock_ctrl == 0)
13641                         strcat(str, "33MHz");
13642                 else if (clock_ctrl == 2)
13643                         strcat(str, "50MHz");
13644                 else if (clock_ctrl == 4)
13645                         strcat(str, "66MHz");
13646                 else if (clock_ctrl == 6)
13647                         strcat(str, "100MHz");
13648         } else {
13649                 strcpy(str, "PCI:");
13650                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13651                         strcat(str, "66MHz");
13652                 else
13653                         strcat(str, "33MHz");
13654         }
13655         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13656                 strcat(str, ":32-bit");
13657         else
13658                 strcat(str, ":64-bit");
13659         return str;
13660 }
13661
13662 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13663 {
13664         struct pci_dev *peer;
13665         unsigned int func, devnr = tp->pdev->devfn & ~7;
13666
13667         for (func = 0; func < 8; func++) {
13668                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13669                 if (peer && peer != tp->pdev)
13670                         break;
13671                 pci_dev_put(peer);
13672         }
13673         /* 5704 can be configured in single-port mode, set peer to
13674          * tp->pdev in that case.
13675          */
13676         if (!peer) {
13677                 peer = tp->pdev;
13678                 return peer;
13679         }
13680
13681         /*
13682          * We don't need to keep the refcount elevated; there's no way
13683          * to remove one half of this device without removing the other
13684          */
13685         pci_dev_put(peer);
13686
13687         return peer;
13688 }
13689
13690 static void __devinit tg3_init_coal(struct tg3 *tp)
13691 {
13692         struct ethtool_coalesce *ec = &tp->coal;
13693
13694         memset(ec, 0, sizeof(*ec));
13695         ec->cmd = ETHTOOL_GCOALESCE;
13696         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13697         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13698         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13699         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13700         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13701         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13702         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13703         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13704         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13705
13706         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13707                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13708                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13709                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13710                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13711                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13712         }
13713
13714         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13715                 ec->rx_coalesce_usecs_irq = 0;
13716                 ec->tx_coalesce_usecs_irq = 0;
13717                 ec->stats_block_coalesce_usecs = 0;
13718         }
13719 }
13720
13721 static const struct net_device_ops tg3_netdev_ops = {
13722         .ndo_open               = tg3_open,
13723         .ndo_stop               = tg3_close,
13724         .ndo_start_xmit         = tg3_start_xmit,
13725         .ndo_get_stats          = tg3_get_stats,
13726         .ndo_validate_addr      = eth_validate_addr,
13727         .ndo_set_multicast_list = tg3_set_rx_mode,
13728         .ndo_set_mac_address    = tg3_set_mac_addr,
13729         .ndo_do_ioctl           = tg3_ioctl,
13730         .ndo_tx_timeout         = tg3_tx_timeout,
13731         .ndo_change_mtu         = tg3_change_mtu,
13732 #if TG3_VLAN_TAG_USED
13733         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13734 #endif
13735 #ifdef CONFIG_NET_POLL_CONTROLLER
13736         .ndo_poll_controller    = tg3_poll_controller,
13737 #endif
13738 };
13739
13740 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13741         .ndo_open               = tg3_open,
13742         .ndo_stop               = tg3_close,
13743         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13744         .ndo_get_stats          = tg3_get_stats,
13745         .ndo_validate_addr      = eth_validate_addr,
13746         .ndo_set_multicast_list = tg3_set_rx_mode,
13747         .ndo_set_mac_address    = tg3_set_mac_addr,
13748         .ndo_do_ioctl           = tg3_ioctl,
13749         .ndo_tx_timeout         = tg3_tx_timeout,
13750         .ndo_change_mtu         = tg3_change_mtu,
13751 #if TG3_VLAN_TAG_USED
13752         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13753 #endif
13754 #ifdef CONFIG_NET_POLL_CONTROLLER
13755         .ndo_poll_controller    = tg3_poll_controller,
13756 #endif
13757 };
13758
13759 static int __devinit tg3_init_one(struct pci_dev *pdev,
13760                                   const struct pci_device_id *ent)
13761 {
13762         static int tg3_version_printed = 0;
13763         struct net_device *dev;
13764         struct tg3 *tp;
13765         int i, err, pm_cap;
13766         u32 sndmbx, rcvmbx, intmbx;
13767         char str[40];
13768         u64 dma_mask, persist_dma_mask;
13769
13770         if (tg3_version_printed++ == 0)
13771                 printk(KERN_INFO "%s", version);
13772
13773         err = pci_enable_device(pdev);
13774         if (err) {
13775                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13776                        "aborting.\n");
13777                 return err;
13778         }
13779
13780         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13781         if (err) {
13782                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13783                        "aborting.\n");
13784                 goto err_out_disable_pdev;
13785         }
13786
13787         pci_set_master(pdev);
13788
13789         /* Find power-management capability. */
13790         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13791         if (pm_cap == 0) {
13792                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13793                        "aborting.\n");
13794                 err = -EIO;
13795                 goto err_out_free_res;
13796         }
13797
13798         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13799         if (!dev) {
13800                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13801                 err = -ENOMEM;
13802                 goto err_out_free_res;
13803         }
13804
13805         SET_NETDEV_DEV(dev, &pdev->dev);
13806
13807 #if TG3_VLAN_TAG_USED
13808         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13809 #endif
13810
13811         tp = netdev_priv(dev);
13812         tp->pdev = pdev;
13813         tp->dev = dev;
13814         tp->pm_cap = pm_cap;
13815         tp->rx_mode = TG3_DEF_RX_MODE;
13816         tp->tx_mode = TG3_DEF_TX_MODE;
13817
13818         if (tg3_debug > 0)
13819                 tp->msg_enable = tg3_debug;
13820         else
13821                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13822
13823         /* The word/byte swap controls here control register access byte
13824          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13825          * setting below.
13826          */
13827         tp->misc_host_ctrl =
13828                 MISC_HOST_CTRL_MASK_PCI_INT |
13829                 MISC_HOST_CTRL_WORD_SWAP |
13830                 MISC_HOST_CTRL_INDIR_ACCESS |
13831                 MISC_HOST_CTRL_PCISTATE_RW;
13832
13833         /* The NONFRM (non-frame) byte/word swap controls take effect
13834          * on descriptor entries, anything which isn't packet data.
13835          *
13836          * The StrongARM chips on the board (one for tx, one for rx)
13837          * are running in big-endian mode.
13838          */
13839         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13840                         GRC_MODE_WSWAP_NONFRM_DATA);
13841 #ifdef __BIG_ENDIAN
13842         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13843 #endif
13844         spin_lock_init(&tp->lock);
13845         spin_lock_init(&tp->indirect_lock);
13846         INIT_WORK(&tp->reset_task, tg3_reset_task);
13847
13848         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13849         if (!tp->regs) {
13850                 printk(KERN_ERR PFX "Cannot map device registers, "
13851                        "aborting.\n");
13852                 err = -ENOMEM;
13853                 goto err_out_free_dev;
13854         }
13855
13856         tg3_init_link_config(tp);
13857
13858         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13859         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13860
13861         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13862         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13863         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13864         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13865                 struct tg3_napi *tnapi = &tp->napi[i];
13866
13867                 tnapi->tp = tp;
13868                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
13869
13870                 tnapi->int_mbox = intmbx;
13871                 if (i < 4)
13872                         intmbx += 0x8;
13873                 else
13874                         intmbx += 0x4;
13875
13876                 tnapi->consmbox = rcvmbx;
13877                 tnapi->prodmbox = sndmbx;
13878
13879                 if (i)
13880                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
13881                 else
13882                         tnapi->coal_now = HOSTCC_MODE_NOW;
13883
13884                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
13885                         break;
13886
13887                 /*
13888                  * If we support MSIX, we'll be using RSS.  If we're using
13889                  * RSS, the first vector only handles link interrupts and the
13890                  * remaining vectors handle rx and tx interrupts.  Reuse the
13891                  * mailbox values for the next iteration.  The values we setup
13892                  * above are still useful for the single vectored mode.
13893                  */
13894                 if (!i)
13895                         continue;
13896
13897                 rcvmbx += 0x8;
13898
13899                 if (sndmbx & 0x4)
13900                         sndmbx -= 0x4;
13901                 else
13902                         sndmbx += 0xc;
13903         }
13904
13905         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
13906         dev->ethtool_ops = &tg3_ethtool_ops;
13907         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13908         dev->irq = pdev->irq;
13909
13910         err = tg3_get_invariants(tp);
13911         if (err) {
13912                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13913                        "aborting.\n");
13914                 goto err_out_iounmap;
13915         }
13916
13917         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13918             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13919                 dev->netdev_ops = &tg3_netdev_ops;
13920         else
13921                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13922
13923
13924         /* The EPB bridge inside 5714, 5715, and 5780 and any
13925          * device behind the EPB cannot support DMA addresses > 40-bit.
13926          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13927          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13928          * do DMA address check in tg3_start_xmit().
13929          */
13930         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13931                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13932         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13933                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13934 #ifdef CONFIG_HIGHMEM
13935                 dma_mask = DMA_BIT_MASK(64);
13936 #endif
13937         } else
13938                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13939
13940         /* Configure DMA attributes. */
13941         if (dma_mask > DMA_BIT_MASK(32)) {
13942                 err = pci_set_dma_mask(pdev, dma_mask);
13943                 if (!err) {
13944                         dev->features |= NETIF_F_HIGHDMA;
13945                         err = pci_set_consistent_dma_mask(pdev,
13946                                                           persist_dma_mask);
13947                         if (err < 0) {
13948                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13949                                        "DMA for consistent allocations\n");
13950                                 goto err_out_iounmap;
13951                         }
13952                 }
13953         }
13954         if (err || dma_mask == DMA_BIT_MASK(32)) {
13955                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13956                 if (err) {
13957                         printk(KERN_ERR PFX "No usable DMA configuration, "
13958                                "aborting.\n");
13959                         goto err_out_iounmap;
13960                 }
13961         }
13962
13963         tg3_init_bufmgr_config(tp);
13964
13965         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13966                 tp->fw_needed = FIRMWARE_TG3;
13967
13968         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13969                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13970         }
13971         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13972             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13973             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13974             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13975             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13976                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13977         } else {
13978                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13979                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13980                         tp->fw_needed = FIRMWARE_TG3TSO5;
13981                 else
13982                         tp->fw_needed = FIRMWARE_TG3TSO;
13983         }
13984
13985         /* TSO is on by default on chips that support hardware TSO.
13986          * Firmware TSO on older chips gives lower performance, so it
13987          * is off by default, but can be enabled using ethtool.
13988          */
13989         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13990                 if (dev->features & NETIF_F_IP_CSUM)
13991                         dev->features |= NETIF_F_TSO;
13992                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13993                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13994                         dev->features |= NETIF_F_TSO6;
13995                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13996                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13997                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13998                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13999                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14000                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
14001                         dev->features |= NETIF_F_TSO_ECN;
14002         }
14003
14004
14005         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14006             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14007             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14008                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14009                 tp->rx_pending = 63;
14010         }
14011
14012         err = tg3_get_device_address(tp);
14013         if (err) {
14014                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14015                        "aborting.\n");
14016                 goto err_out_fw;
14017         }
14018
14019         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14020                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14021                 if (!tp->aperegs) {
14022                         printk(KERN_ERR PFX "Cannot map APE registers, "
14023                                "aborting.\n");
14024                         err = -ENOMEM;
14025                         goto err_out_fw;
14026                 }
14027
14028                 tg3_ape_lock_init(tp);
14029
14030                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14031                         tg3_read_dash_ver(tp);
14032         }
14033
14034         /*
14035          * Reset chip in case UNDI or EFI driver did not shutdown
14036          * DMA self test will enable WDMAC and we'll see (spurious)
14037          * pending DMA on the PCI bus at that point.
14038          */
14039         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14040             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14041                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14042                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14043         }
14044
14045         err = tg3_test_dma(tp);
14046         if (err) {
14047                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14048                 goto err_out_apeunmap;
14049         }
14050
14051         /* flow control autonegotiation is default behavior */
14052         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14053         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14054
14055         tg3_init_coal(tp);
14056
14057         pci_set_drvdata(pdev, dev);
14058
14059         err = register_netdev(dev);
14060         if (err) {
14061                 printk(KERN_ERR PFX "Cannot register net device, "
14062                        "aborting.\n");
14063                 goto err_out_apeunmap;
14064         }
14065
14066         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14067                dev->name,
14068                tp->board_part_number,
14069                tp->pci_chip_rev_id,
14070                tg3_bus_string(tp, str),
14071                dev->dev_addr);
14072
14073         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
14074                 printk(KERN_INFO
14075                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14076                        tp->dev->name,
14077                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
14078                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
14079         else
14080                 printk(KERN_INFO
14081                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14082                        tp->dev->name, tg3_phy_string(tp),
14083                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14084                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14085                          "10/100/1000Base-T")),
14086                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14087
14088         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14089                dev->name,
14090                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14091                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14092                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14093                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14094                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14095         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14096                dev->name, tp->dma_rwctrl,
14097                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14098                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14099
14100         return 0;
14101
14102 err_out_apeunmap:
14103         if (tp->aperegs) {
14104                 iounmap(tp->aperegs);
14105                 tp->aperegs = NULL;
14106         }
14107
14108 err_out_fw:
14109         if (tp->fw)
14110                 release_firmware(tp->fw);
14111
14112 err_out_iounmap:
14113         if (tp->regs) {
14114                 iounmap(tp->regs);
14115                 tp->regs = NULL;
14116         }
14117
14118 err_out_free_dev:
14119         free_netdev(dev);
14120
14121 err_out_free_res:
14122         pci_release_regions(pdev);
14123
14124 err_out_disable_pdev:
14125         pci_disable_device(pdev);
14126         pci_set_drvdata(pdev, NULL);
14127         return err;
14128 }
14129
14130 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14131 {
14132         struct net_device *dev = pci_get_drvdata(pdev);
14133
14134         if (dev) {
14135                 struct tg3 *tp = netdev_priv(dev);
14136
14137                 if (tp->fw)
14138                         release_firmware(tp->fw);
14139
14140                 flush_scheduled_work();
14141
14142                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14143                         tg3_phy_fini(tp);
14144                         tg3_mdio_fini(tp);
14145                 }
14146
14147                 unregister_netdev(dev);
14148                 if (tp->aperegs) {
14149                         iounmap(tp->aperegs);
14150                         tp->aperegs = NULL;
14151                 }
14152                 if (tp->regs) {
14153                         iounmap(tp->regs);
14154                         tp->regs = NULL;
14155                 }
14156                 free_netdev(dev);
14157                 pci_release_regions(pdev);
14158                 pci_disable_device(pdev);
14159                 pci_set_drvdata(pdev, NULL);
14160         }
14161 }
14162
14163 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14164 {
14165         struct net_device *dev = pci_get_drvdata(pdev);
14166         struct tg3 *tp = netdev_priv(dev);
14167         pci_power_t target_state;
14168         int err;
14169
14170         /* PCI register 4 needs to be saved whether netif_running() or not.
14171          * MSI address and data need to be saved if using MSI and
14172          * netif_running().
14173          */
14174         pci_save_state(pdev);
14175
14176         if (!netif_running(dev))
14177                 return 0;
14178
14179         flush_scheduled_work();
14180         tg3_phy_stop(tp);
14181         tg3_netif_stop(tp);
14182
14183         del_timer_sync(&tp->timer);
14184
14185         tg3_full_lock(tp, 1);
14186         tg3_disable_ints(tp);
14187         tg3_full_unlock(tp);
14188
14189         netif_device_detach(dev);
14190
14191         tg3_full_lock(tp, 0);
14192         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14193         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14194         tg3_full_unlock(tp);
14195
14196         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14197
14198         err = tg3_set_power_state(tp, target_state);
14199         if (err) {
14200                 int err2;
14201
14202                 tg3_full_lock(tp, 0);
14203
14204                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14205                 err2 = tg3_restart_hw(tp, 1);
14206                 if (err2)
14207                         goto out;
14208
14209                 tp->timer.expires = jiffies + tp->timer_offset;
14210                 add_timer(&tp->timer);
14211
14212                 netif_device_attach(dev);
14213                 tg3_netif_start(tp);
14214
14215 out:
14216                 tg3_full_unlock(tp);
14217
14218                 if (!err2)
14219                         tg3_phy_start(tp);
14220         }
14221
14222         return err;
14223 }
14224
14225 static int tg3_resume(struct pci_dev *pdev)
14226 {
14227         struct net_device *dev = pci_get_drvdata(pdev);
14228         struct tg3 *tp = netdev_priv(dev);
14229         int err;
14230
14231         pci_restore_state(tp->pdev);
14232
14233         if (!netif_running(dev))
14234                 return 0;
14235
14236         err = tg3_set_power_state(tp, PCI_D0);
14237         if (err)
14238                 return err;
14239
14240         netif_device_attach(dev);
14241
14242         tg3_full_lock(tp, 0);
14243
14244         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14245         err = tg3_restart_hw(tp, 1);
14246         if (err)
14247                 goto out;
14248
14249         tp->timer.expires = jiffies + tp->timer_offset;
14250         add_timer(&tp->timer);
14251
14252         tg3_netif_start(tp);
14253
14254 out:
14255         tg3_full_unlock(tp);
14256
14257         if (!err)
14258                 tg3_phy_start(tp);
14259
14260         return err;
14261 }
14262
14263 static struct pci_driver tg3_driver = {
14264         .name           = DRV_MODULE_NAME,
14265         .id_table       = tg3_pci_tbl,
14266         .probe          = tg3_init_one,
14267         .remove         = __devexit_p(tg3_remove_one),
14268         .suspend        = tg3_suspend,
14269         .resume         = tg3_resume
14270 };
14271
14272 static int __init tg3_init(void)
14273 {
14274         return pci_register_driver(&tg3_driver);
14275 }
14276
14277 static void __exit tg3_cleanup(void)
14278 {
14279         pci_unregister_driver(&tg3_driver);
14280 }
14281
14282 module_init(tg3_init);
14283 module_exit(tg3_cleanup);