drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.105"
  72 #define DRV_MODULE_RELDATE      "December 2, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 #define TG3_RX_STD_BUFF_RING_SIZE \
 141         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 142
 143 #define TG3_RX_JMB_BUFF_RING_SIZE \
 144         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 145
 146 /* minimum number of free TX descriptors required to wake up TX process */
 147 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 148
 149 #define TG3_RAW_IP_ALIGN 2
 150
 151 /* number of ETHTOOL_GSTATS u64's */
 152 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 153
 154 #define TG3_NUM_TEST            6
 155
 156 #define FIRMWARE_TG3            "tigon/tg3.bin"
 157 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 158 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 159
 160 static char version[] __devinitdata =
 161         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 162
 163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 165 MODULE_LICENSE("GPL");
 166 MODULE_VERSION(DRV_MODULE_VERSION);
 167 MODULE_FIRMWARE(FIRMWARE_TG3);
 168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 170
 171 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 172
 173 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 174 module_param(tg3_debug, int, 0);
 175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 176
 177 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 254         {}
 255 };
 256
 257 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 258
 259 static const struct {
 260         const char string[ETH_GSTRING_LEN];
 261 } ethtool_stats_keys[TG3_NUM_STATS] = {
 262         { "rx_octets" },
 263         { "rx_fragments" },
 264         { "rx_ucast_packets" },
 265         { "rx_mcast_packets" },
 266         { "rx_bcast_packets" },
 267         { "rx_fcs_errors" },
 268         { "rx_align_errors" },
 269         { "rx_xon_pause_rcvd" },
 270         { "rx_xoff_pause_rcvd" },
 271         { "rx_mac_ctrl_rcvd" },
 272         { "rx_xoff_entered" },
 273         { "rx_frame_too_long_errors" },
 274         { "rx_jabbers" },
 275         { "rx_undersize_packets" },
 276         { "rx_in_length_errors" },
 277         { "rx_out_length_errors" },
 278         { "rx_64_or_less_octet_packets" },
 279         { "rx_65_to_127_octet_packets" },
 280         { "rx_128_to_255_octet_packets" },
 281         { "rx_256_to_511_octet_packets" },
 282         { "rx_512_to_1023_octet_packets" },
 283         { "rx_1024_to_1522_octet_packets" },
 284         { "rx_1523_to_2047_octet_packets" },
 285         { "rx_2048_to_4095_octet_packets" },
 286         { "rx_4096_to_8191_octet_packets" },
 287         { "rx_8192_to_9022_octet_packets" },
 288
 289         { "tx_octets" },
 290         { "tx_collisions" },
 291
 292         { "tx_xon_sent" },
 293         { "tx_xoff_sent" },
 294         { "tx_flow_control" },
 295         { "tx_mac_errors" },
 296         { "tx_single_collisions" },
 297         { "tx_mult_collisions" },
 298         { "tx_deferred" },
 299         { "tx_excessive_collisions" },
 300         { "tx_late_collisions" },
 301         { "tx_collide_2times" },
 302         { "tx_collide_3times" },
 303         { "tx_collide_4times" },
 304         { "tx_collide_5times" },
 305         { "tx_collide_6times" },
 306         { "tx_collide_7times" },
 307         { "tx_collide_8times" },
 308         { "tx_collide_9times" },
 309         { "tx_collide_10times" },
 310         { "tx_collide_11times" },
 311         { "tx_collide_12times" },
 312         { "tx_collide_13times" },
 313         { "tx_collide_14times" },
 314         { "tx_collide_15times" },
 315         { "tx_ucast_packets" },
 316         { "tx_mcast_packets" },
 317         { "tx_bcast_packets" },
 318         { "tx_carrier_sense_errors" },
 319         { "tx_discards" },
 320         { "tx_errors" },
 321
 322         { "dma_writeq_full" },
 323         { "dma_write_prioq_full" },
 324         { "rxbds_empty" },
 325         { "rx_discards" },
 326         { "rx_errors" },
 327         { "rx_threshold_hit" },
 328
 329         { "dma_readq_full" },
 330         { "dma_read_prioq_full" },
 331         { "tx_comp_queue_full" },
 332
 333         { "ring_set_send_prod_index" },
 334         { "ring_status_update" },
 335         { "nic_irqs" },
 336         { "nic_avoided_irqs" },
 337         { "nic_tx_threshold_hit" }
 338 };
 339
 340 static const struct {
 341         const char string[ETH_GSTRING_LEN];
 342 } ethtool_test_keys[TG3_NUM_TEST] = {
 343         { "nvram test     (online) " },
 344         { "link test      (online) " },
 345         { "register test  (offline)" },
 346         { "memory test    (offline)" },
 347         { "loopback test  (offline)" },
 348         { "interrupt test (offline)" },
 349 };
 350
 351 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         writel(val, tp->regs + off);
 354 }
 355
 356 static u32 tg3_read32(struct tg3 *tp, u32 off)
 357 {
 358         return (readl(tp->regs + off));
 359 }
 360
 361 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         writel(val, tp->aperegs + off);
 364 }
 365
 366 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 367 {
 368         return (readl(tp->aperegs + off));
 369 }
 370
 371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 372 {
 373         unsigned long flags;
 374
 375         spin_lock_irqsave(&tp->indirect_lock, flags);
 376         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 377         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 378         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 379 }
 380
 381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->regs + off);
 384         readl(tp->regs + off);
 385 }
 386
 387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 388 {
 389         unsigned long flags;
 390         u32 val;
 391
 392         spin_lock_irqsave(&tp->indirect_lock, flags);
 393         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 394         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 395         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 396         return val;
 397 }
 398
 399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 404                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 405                                        TG3_64BIT_REG_LOW, val);
 406                 return;
 407         }
 408         if (off == TG3_RX_STD_PROD_IDX_REG) {
 409                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 410                                        TG3_64BIT_REG_LOW, val);
 411                 return;
 412         }
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 416         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418
 419         /* In indirect mode when disabling interrupts, we also need
 420          * to clear the interrupt bit in the GRC local ctrl register.
 421          */
 422         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 423             (val == 0x1)) {
 424                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 425                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 426         }
 427 }
 428
 429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 430 {
 431         unsigned long flags;
 432         u32 val;
 433
 434         spin_lock_irqsave(&tp->indirect_lock, flags);
 435         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 436         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 437         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 438         return val;
 439 }
 440
 441 /* usec_wait specifies the wait time in usec when writing to certain registers
 442  * where it is unsafe to read back the register without some delay.
 443  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 444  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 445  */
 446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 447 {
 448         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 449             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 450                 /* Non-posted methods */
 451                 tp->write32(tp, off, val);
 452         else {
 453                 /* Posted method */
 454                 tg3_write32(tp, off, val);
 455                 if (usec_wait)
 456                         udelay(usec_wait);
 457                 tp->read32(tp, off);
 458         }
 459         /* Wait again after the read for the posted method to guarantee that
 460          * the wait time is met.
 461          */
 462         if (usec_wait)
 463                 udelay(usec_wait);
 464 }
 465
 466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 467 {
 468         tp->write32_mbox(tp, off, val);
 469         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 470             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 471                 tp->read32_mbox(tp, off);
 472 }
 473
 474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 475 {
 476         void __iomem *mbox = tp->regs + off;
 477         writel(val, mbox);
 478         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 479                 writel(val, mbox);
 480         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 481                 readl(mbox);
 482 }
 483
 484 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 485 {
 486         return (readl(tp->regs + off + GRCMBOX_BASE));
 487 }
 488
 489 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 490 {
 491         writel(val, tp->regs + off + GRCMBOX_BASE);
 492 }
 493
 494 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 495 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 496 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 497 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 498 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 499
 500 #define tw32(reg,val)           tp->write32(tp, reg, val)
 501 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 502 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 503 #define tr32(reg)               tp->read32(tp, reg)
 504
 505 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 506 {
 507         unsigned long flags;
 508
 509         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 510             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 511                 return;
 512
 513         spin_lock_irqsave(&tp->indirect_lock, flags);
 514         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 515                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 516                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 517
 518                 /* Always leave this as zero. */
 519                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 520         } else {
 521                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 522                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 523
 524                 /* Always leave this as zero. */
 525                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 526         }
 527         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 528 }
 529
 530 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 531 {
 532         unsigned long flags;
 533
 534         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 535             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 536                 *val = 0;
 537                 return;
 538         }
 539
 540         spin_lock_irqsave(&tp->indirect_lock, flags);
 541         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 543                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 544
 545                 /* Always leave this as zero. */
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 547         } else {
 548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 549                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 550
 551                 /* Always leave this as zero. */
 552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 553         }
 554         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 555 }
 556
 557 static void tg3_ape_lock_init(struct tg3 *tp)
 558 {
 559         int i;
 560
 561         /* Make sure the driver hasn't any stale locks. */
 562         for (i = 0; i < 8; i++)
 563                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 564                                 APE_LOCK_GRANT_DRIVER);
 565 }
 566
 567 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 568 {
 569         int i, off;
 570         int ret = 0;
 571         u32 status;
 572
 573         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 574                 return 0;
 575
 576         switch (locknum) {
 577                 case TG3_APE_LOCK_GRC:
 578                 case TG3_APE_LOCK_MEM:
 579                         break;
 580                 default:
 581                         return -EINVAL;
 582         }
 583
 584         off = 4 * locknum;
 585
 586         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 587
 588         /* Wait for up to 1 millisecond to acquire lock. */
 589         for (i = 0; i < 100; i++) {
 590                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 591                 if (status == APE_LOCK_GRANT_DRIVER)
 592                         break;
 593                 udelay(10);
 594         }
 595
 596         if (status != APE_LOCK_GRANT_DRIVER) {
 597                 /* Revoke the lock request. */
 598                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 599                                 APE_LOCK_GRANT_DRIVER);
 600
 601                 ret = -EBUSY;
 602         }
 603
 604         return ret;
 605 }
 606
 607 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 608 {
 609         int off;
 610
 611         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 612                 return;
 613
 614         switch (locknum) {
 615                 case TG3_APE_LOCK_GRC:
 616                 case TG3_APE_LOCK_MEM:
 617                         break;
 618                 default:
 619                         return;
 620         }
 621
 622         off = 4 * locknum;
 623         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 624 }
 625
 626 static void tg3_disable_ints(struct tg3 *tp)
 627 {
 628         int i;
 629
 630         tw32(TG3PCI_MISC_HOST_CTRL,
 631              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 632         for (i = 0; i < tp->irq_max; i++)
 633                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 634 }
 635
 636 static void tg3_enable_ints(struct tg3 *tp)
 637 {
 638         int i;
 639         u32 coal_now = 0;
 640
 641         tp->irq_sync = 0;
 642         wmb();
 643
 644         tw32(TG3PCI_MISC_HOST_CTRL,
 645              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 646
 647         for (i = 0; i < tp->irq_cnt; i++) {
 648                 struct tg3_napi *tnapi = &tp->napi[i];
 649                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 650                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 651                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 652
 653                 coal_now |= tnapi->coal_now;
 654         }
 655
 656         /* Force an initial interrupt */
 657         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 658             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 659                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 660         else
 661                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 662                      HOSTCC_MODE_ENABLE | coal_now);
 663 }
 664
 665 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 666 {
 667         struct tg3 *tp = tnapi->tp;
 668         struct tg3_hw_status *sblk = tnapi->hw_status;
 669         unsigned int work_exists = 0;
 670
 671         /* check for phy events */
 672         if (!(tp->tg3_flags &
 673               (TG3_FLAG_USE_LINKCHG_REG |
 674                TG3_FLAG_POLL_SERDES))) {
 675                 if (sblk->status & SD_STATUS_LINK_CHG)
 676                         work_exists = 1;
 677         }
 678         /* check for RX/TX work to do */
 679         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 680             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 681                 work_exists = 1;
 682
 683         return work_exists;
 684 }
 685
 686 /* tg3_int_reenable
 687  *  similar to tg3_enable_ints, but it accurately determines whether there
 688  *  is new work pending and can return without flushing the PIO write
 689  *  which reenables interrupts
 690  */
 691 static void tg3_int_reenable(struct tg3_napi *tnapi)
 692 {
 693         struct tg3 *tp = tnapi->tp;
 694
 695         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 696         mmiowb();
 697
 698         /* When doing tagged status, this work check is unnecessary.
 699          * The last_tag we write above tells the chip which piece of
 700          * work we've completed.
 701          */
 702         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 703             tg3_has_work(tnapi))
 704                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 705                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 706 }
 707
 708 static void tg3_napi_disable(struct tg3 *tp)
 709 {
 710         int i;
 711
 712         for (i = tp->irq_cnt - 1; i >= 0; i--)
 713                 napi_disable(&tp->napi[i].napi);
 714 }
 715
 716 static void tg3_napi_enable(struct tg3 *tp)
 717 {
 718         int i;
 719
 720         for (i = 0; i < tp->irq_cnt; i++)
 721                 napi_enable(&tp->napi[i].napi);
 722 }
 723
 724 static inline void tg3_netif_stop(struct tg3 *tp)
 725 {
 726         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 727         tg3_napi_disable(tp);
 728         netif_tx_disable(tp->dev);
 729 }
 730
 731 static inline void tg3_netif_start(struct tg3 *tp)
 732 {
 733         /* NOTE: unconditional netif_tx_wake_all_queues is only
 734          * appropriate so long as all callers are assured to
 735          * have free tx slots (such as after tg3_init_hw)
 736          */
 737         netif_tx_wake_all_queues(tp->dev);
 738
 739         tg3_napi_enable(tp);
 740         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 741         tg3_enable_ints(tp);
 742 }
 743
 744 static void tg3_switch_clocks(struct tg3 *tp)
 745 {
 746         u32 clock_ctrl;
 747         u32 orig_clock_ctrl;
 748
 749         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 750             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 751                 return;
 752
 753         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 754
 755         orig_clock_ctrl = clock_ctrl;
 756         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 757                        CLOCK_CTRL_CLKRUN_OENABLE |
 758                        0x1f);
 759         tp->pci_clock_ctrl = clock_ctrl;
 760
 761         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 762                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 763                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 764                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 765                 }
 766         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 767                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 768                             clock_ctrl |
 769                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 770                             40);
 771                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 772                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 773                             40);
 774         }
 775         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 776 }
 777
 778 #define PHY_BUSY_LOOPS  5000
 779
 780 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 781 {
 782         u32 frame_val;
 783         unsigned int loops;
 784         int ret;
 785
 786         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 787                 tw32_f(MAC_MI_MODE,
 788                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 789                 udelay(80);
 790         }
 791
 792         *val = 0x0;
 793
 794         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 795                       MI_COM_PHY_ADDR_MASK);
 796         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 797                       MI_COM_REG_ADDR_MASK);
 798         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 799
 800         tw32_f(MAC_MI_COM, frame_val);
 801
 802         loops = PHY_BUSY_LOOPS;
 803         while (loops != 0) {
 804                 udelay(10);
 805                 frame_val = tr32(MAC_MI_COM);
 806
 807                 if ((frame_val & MI_COM_BUSY) == 0) {
 808                         udelay(5);
 809                         frame_val = tr32(MAC_MI_COM);
 810                         break;
 811                 }
 812                 loops -= 1;
 813         }
 814
 815         ret = -EBUSY;
 816         if (loops != 0) {
 817                 *val = frame_val & MI_COM_DATA_MASK;
 818                 ret = 0;
 819         }
 820
 821         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 822                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 823                 udelay(80);
 824         }
 825
 826         return ret;
 827 }
 828
 829 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 830 {
 831         u32 frame_val;
 832         unsigned int loops;
 833         int ret;
 834
 835         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 836             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 837                 return 0;
 838
 839         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 840                 tw32_f(MAC_MI_MODE,
 841                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 842                 udelay(80);
 843         }
 844
 845         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 846                       MI_COM_PHY_ADDR_MASK);
 847         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 848                       MI_COM_REG_ADDR_MASK);
 849         frame_val |= (val & MI_COM_DATA_MASK);
 850         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 851
 852         tw32_f(MAC_MI_COM, frame_val);
 853
 854         loops = PHY_BUSY_LOOPS;
 855         while (loops != 0) {
 856                 udelay(10);
 857                 frame_val = tr32(MAC_MI_COM);
 858                 if ((frame_val & MI_COM_BUSY) == 0) {
 859                         udelay(5);
 860                         frame_val = tr32(MAC_MI_COM);
 861                         break;
 862                 }
 863                 loops -= 1;
 864         }
 865
 866         ret = -EBUSY;
 867         if (loops != 0)
 868                 ret = 0;
 869
 870         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 871                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 872                 udelay(80);
 873         }
 874
 875         return ret;
 876 }
 877
 878 static int tg3_bmcr_reset(struct tg3 *tp)
 879 {
 880         u32 phy_control;
 881         int limit, err;
 882
 883         /* OK, reset it, and poll the BMCR_RESET bit until it
 884          * clears or we time out.
 885          */
 886         phy_control = BMCR_RESET;
 887         err = tg3_writephy(tp, MII_BMCR, phy_control);
 888         if (err != 0)
 889                 return -EBUSY;
 890
 891         limit = 5000;
 892         while (limit--) {
 893                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 894                 if (err != 0)
 895                         return -EBUSY;
 896
 897                 if ((phy_control & BMCR_RESET) == 0) {
 898                         udelay(40);
 899                         break;
 900                 }
 901                 udelay(10);
 902         }
 903         if (limit < 0)
 904                 return -EBUSY;
 905
 906         return 0;
 907 }
 908
 909 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 910 {
 911         struct tg3 *tp = bp->priv;
 912         u32 val;
 913
 914         spin_lock_bh(&tp->lock);
 915
 916         if (tg3_readphy(tp, reg, &val))
 917                 val = -EIO;
 918
 919         spin_unlock_bh(&tp->lock);
 920
 921         return val;
 922 }
 923
 924 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 925 {
 926         struct tg3 *tp = bp->priv;
 927         u32 ret = 0;
 928
 929         spin_lock_bh(&tp->lock);
 930
 931         if (tg3_writephy(tp, reg, val))
 932                 ret = -EIO;
 933
 934         spin_unlock_bh(&tp->lock);
 935
 936         return ret;
 937 }
 938
 939 static int tg3_mdio_reset(struct mii_bus *bp)
 940 {
 941         return 0;
 942 }
 943
 944 static void tg3_mdio_config_5785(struct tg3 *tp)
 945 {
 946         u32 val;
 947         struct phy_device *phydev;
 948
 949         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 950         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 951         case TG3_PHY_ID_BCM50610:
 952         case TG3_PHY_ID_BCM50610M:
 953                 val = MAC_PHYCFG2_50610_LED_MODES;
 954                 break;
 955         case TG3_PHY_ID_BCMAC131:
 956                 val = MAC_PHYCFG2_AC131_LED_MODES;
 957                 break;
 958         case TG3_PHY_ID_RTL8211C:
 959                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 960                 break;
 961         case TG3_PHY_ID_RTL8201E:
 962                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 963                 break;
 964         default:
 965                 return;
 966         }
 967
 968         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 969                 tw32(MAC_PHYCFG2, val);
 970
 971                 val = tr32(MAC_PHYCFG1);
 972                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 973                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 974                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 975                 tw32(MAC_PHYCFG1, val);
 976
 977                 return;
 978         }
 979
 980         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 981                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 982                        MAC_PHYCFG2_FMODE_MASK_MASK |
 983                        MAC_PHYCFG2_GMODE_MASK_MASK |
 984                        MAC_PHYCFG2_ACT_MASK_MASK   |
 985                        MAC_PHYCFG2_QUAL_MASK_MASK |
 986                        MAC_PHYCFG2_INBAND_ENABLE;
 987
 988         tw32(MAC_PHYCFG2, val);
 989
 990         val = tr32(MAC_PHYCFG1);
 991         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 992                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 994                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 995                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 996                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 997                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 998         }
 999         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001         tw32(MAC_PHYCFG1, val);
1002
1003         val = tr32(MAC_EXT_RGMII_MODE);
1004         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005                  MAC_RGMII_MODE_RX_QUALITY |
1006                  MAC_RGMII_MODE_RX_ACTIVITY |
1007                  MAC_RGMII_MODE_RX_ENG_DET |
1008                  MAC_RGMII_MODE_TX_ENABLE |
1009                  MAC_RGMII_MODE_TX_LOWPWR |
1010                  MAC_RGMII_MODE_TX_RESET);
1011         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1012                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013                         val |= MAC_RGMII_MODE_RX_INT_B |
1014                                MAC_RGMII_MODE_RX_QUALITY |
1015                                MAC_RGMII_MODE_RX_ACTIVITY |
1016                                MAC_RGMII_MODE_RX_ENG_DET;
1017                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018                         val |= MAC_RGMII_MODE_TX_ENABLE |
1019                                MAC_RGMII_MODE_TX_LOWPWR |
1020                                MAC_RGMII_MODE_TX_RESET;
1021         }
1022         tw32(MAC_EXT_RGMII_MODE, val);
1023 }
1024
1025 static void tg3_mdio_start(struct tg3 *tp)
1026 {
1027         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028         tw32_f(MAC_MI_MODE, tp->mi_mode);
1029         udelay(80);
1030
1031         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032                 u32 funcnum, is_serdes;
1033
1034                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1035                 if (funcnum)
1036                         tp->phy_addr = 2;
1037                 else
1038                         tp->phy_addr = 1;
1039
1040                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1041                 if (is_serdes)
1042                         tp->phy_addr += 7;
1043         } else
1044                 tp->phy_addr = TG3_PHY_MII_ADDR;
1045
1046         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048                 tg3_mdio_config_5785(tp);
1049 }
1050
1051 static int tg3_mdio_init(struct tg3 *tp)
1052 {
1053         int i;
1054         u32 reg;
1055         struct phy_device *phydev;
1056
1057         tg3_mdio_start(tp);
1058
1059         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1061                 return 0;
1062
1063         tp->mdio_bus = mdiobus_alloc();
1064         if (tp->mdio_bus == NULL)
1065                 return -ENOMEM;
1066
1067         tp->mdio_bus->name     = "tg3 mdio bus";
1068         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1069                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1070         tp->mdio_bus->priv     = tp;
1071         tp->mdio_bus->parent   = &tp->pdev->dev;
1072         tp->mdio_bus->read     = &tg3_mdio_read;
1073         tp->mdio_bus->write    = &tg3_mdio_write;
1074         tp->mdio_bus->reset    = &tg3_mdio_reset;
1075         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1076         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1077
1078         for (i = 0; i < PHY_MAX_ADDR; i++)
1079                 tp->mdio_bus->irq[i] = PHY_POLL;
1080
1081         /* The bus registration will look for all the PHYs on the mdio bus.
1082          * Unfortunately, it does not ensure the PHY is powered up before
1083          * accessing the PHY ID registers.  A chip reset is the
1084          * quickest way to bring the device back to an operational state..
1085          */
1086         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1087                 tg3_bmcr_reset(tp);
1088
1089         i = mdiobus_register(tp->mdio_bus);
1090         if (i) {
1091                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1092                         tp->dev->name, i);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return i;
1095         }
1096
1097         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1098
1099         if (!phydev || !phydev->drv) {
1100                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101                 mdiobus_unregister(tp->mdio_bus);
1102                 mdiobus_free(tp->mdio_bus);
1103                 return -ENODEV;
1104         }
1105
1106         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1107         case TG3_PHY_ID_BCM57780:
1108                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1109                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1110                 break;
1111         case TG3_PHY_ID_BCM50610:
1112         case TG3_PHY_ID_BCM50610M:
1113                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1114                                      PHY_BRCM_RX_REFCLK_UNUSED |
1115                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1116                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1117                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1123                 /* fallthru */
1124         case TG3_PHY_ID_RTL8211C:
1125                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1126                 break;
1127         case TG3_PHY_ID_RTL8201E:
1128         case TG3_PHY_ID_BCMAC131:
1129                 phydev->interface = PHY_INTERFACE_MODE_MII;
1130                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1131                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1132                 break;
1133         }
1134
1135         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1136
1137         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138                 tg3_mdio_config_5785(tp);
1139
1140         return 0;
1141 }
1142
1143 static void tg3_mdio_fini(struct tg3 *tp)
1144 {
1145         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1147                 mdiobus_unregister(tp->mdio_bus);
1148                 mdiobus_free(tp->mdio_bus);
1149         }
1150 }
1151
1152 /* tp->lock is held. */
1153 static inline void tg3_generate_fw_event(struct tg3 *tp)
1154 {
1155         u32 val;
1156
1157         val = tr32(GRC_RX_CPU_EVENT);
1158         val |= GRC_RX_CPU_DRIVER_EVENT;
1159         tw32_f(GRC_RX_CPU_EVENT, val);
1160
1161         tp->last_event_jiffies = jiffies;
1162 }
1163
1164 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1165
1166 /* tp->lock is held. */
1167 static void tg3_wait_for_event_ack(struct tg3 *tp)
1168 {
1169         int i;
1170         unsigned int delay_cnt;
1171         long time_remain;
1172
1173         /* If enough time has passed, no wait is necessary. */
1174         time_remain = (long)(tp->last_event_jiffies + 1 +
1175                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1176                       (long)jiffies;
1177         if (time_remain < 0)
1178                 return;
1179
1180         /* Check if we can shorten the wait time. */
1181         delay_cnt = jiffies_to_usecs(time_remain);
1182         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184         delay_cnt = (delay_cnt >> 3) + 1;
1185
1186         for (i = 0; i < delay_cnt; i++) {
1187                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1188                         break;
1189                 udelay(8);
1190         }
1191 }
1192
1193 /* tp->lock is held. */
1194 static void tg3_ump_link_report(struct tg3 *tp)
1195 {
1196         u32 reg;
1197         u32 val;
1198
1199         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1201                 return;
1202
1203         tg3_wait_for_event_ack(tp);
1204
1205         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1206
1207         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1208
1209         val = 0;
1210         if (!tg3_readphy(tp, MII_BMCR, &reg))
1211                 val = reg << 16;
1212         if (!tg3_readphy(tp, MII_BMSR, &reg))
1213                 val |= (reg & 0xffff);
1214         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1215
1216         val = 0;
1217         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1218                 val = reg << 16;
1219         if (!tg3_readphy(tp, MII_LPA, &reg))
1220                 val |= (reg & 0xffff);
1221         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1222
1223         val = 0;
1224         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1226                         val = reg << 16;
1227                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1228                         val |= (reg & 0xffff);
1229         }
1230         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1231
1232         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1233                 val = reg << 16;
1234         else
1235                 val = 0;
1236         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1237
1238         tg3_generate_fw_event(tp);
1239 }
1240
1241 static void tg3_link_report(struct tg3 *tp)
1242 {
1243         if (!netif_carrier_ok(tp->dev)) {
1244                 if (netif_msg_link(tp))
1245                         printk(KERN_INFO PFX "%s: Link is down.\n",
1246                                tp->dev->name);
1247                 tg3_ump_link_report(tp);
1248         } else if (netif_msg_link(tp)) {
1249                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1250                        tp->dev->name,
1251                        (tp->link_config.active_speed == SPEED_1000 ?
1252                         1000 :
1253                         (tp->link_config.active_speed == SPEED_100 ?
1254                          100 : 10)),
1255                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1256                         "full" : "half"));
1257
1258                 printk(KERN_INFO PFX
1259                        "%s: Flow control is %s for TX and %s for RX.\n",
1260                        tp->dev->name,
1261                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1262                        "on" : "off",
1263                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1264                        "on" : "off");
1265                 tg3_ump_link_report(tp);
1266         }
1267 }
1268
1269 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1270 {
1271         u16 miireg;
1272
1273         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1274                 miireg = ADVERTISE_PAUSE_CAP;
1275         else if (flow_ctrl & FLOW_CTRL_TX)
1276                 miireg = ADVERTISE_PAUSE_ASYM;
1277         else if (flow_ctrl & FLOW_CTRL_RX)
1278                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1279         else
1280                 miireg = 0;
1281
1282         return miireg;
1283 }
1284
1285 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1286 {
1287         u16 miireg;
1288
1289         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1290                 miireg = ADVERTISE_1000XPAUSE;
1291         else if (flow_ctrl & FLOW_CTRL_TX)
1292                 miireg = ADVERTISE_1000XPSE_ASYM;
1293         else if (flow_ctrl & FLOW_CTRL_RX)
1294                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1295         else
1296                 miireg = 0;
1297
1298         return miireg;
1299 }
1300
1301 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1302 {
1303         u8 cap = 0;
1304
1305         if (lcladv & ADVERTISE_1000XPAUSE) {
1306                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307                         if (rmtadv & LPA_1000XPAUSE)
1308                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1309                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1310                                 cap = FLOW_CTRL_RX;
1311                 } else {
1312                         if (rmtadv & LPA_1000XPAUSE)
1313                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1314                 }
1315         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1317                         cap = FLOW_CTRL_TX;
1318         }
1319
1320         return cap;
1321 }
1322
1323 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1324 {
1325         u8 autoneg;
1326         u8 flowctrl = 0;
1327         u32 old_rx_mode = tp->rx_mode;
1328         u32 old_tx_mode = tp->tx_mode;
1329
1330         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1331                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1332         else
1333                 autoneg = tp->link_config.autoneg;
1334
1335         if (autoneg == AUTONEG_ENABLE &&
1336             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1338                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1339                 else
1340                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1341         } else
1342                 flowctrl = tp->link_config.flowctrl;
1343
1344         tp->link_config.active_flowctrl = flowctrl;
1345
1346         if (flowctrl & FLOW_CTRL_RX)
1347                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1348         else
1349                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1350
1351         if (old_rx_mode != tp->rx_mode)
1352                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1353
1354         if (flowctrl & FLOW_CTRL_TX)
1355                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1356         else
1357                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1358
1359         if (old_tx_mode != tp->tx_mode)
1360                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1361 }
1362
1363 static void tg3_adjust_link(struct net_device *dev)
1364 {
1365         u8 oldflowctrl, linkmesg = 0;
1366         u32 mac_mode, lcl_adv, rmt_adv;
1367         struct tg3 *tp = netdev_priv(dev);
1368         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1369
1370         spin_lock_bh(&tp->lock);
1371
1372         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373                                     MAC_MODE_HALF_DUPLEX);
1374
1375         oldflowctrl = tp->link_config.active_flowctrl;
1376
1377         if (phydev->link) {
1378                 lcl_adv = 0;
1379                 rmt_adv = 0;
1380
1381                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1383                 else if (phydev->speed == SPEED_1000 ||
1384                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1385                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1386                 else
1387                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1388
1389                 if (phydev->duplex == DUPLEX_HALF)
1390                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1391                 else {
1392                         lcl_adv = tg3_advert_flowctrl_1000T(
1393                                   tp->link_config.flowctrl);
1394
1395                         if (phydev->pause)
1396                                 rmt_adv = LPA_PAUSE_CAP;
1397                         if (phydev->asym_pause)
1398                                 rmt_adv |= LPA_PAUSE_ASYM;
1399                 }
1400
1401                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1402         } else
1403                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1404
1405         if (mac_mode != tp->mac_mode) {
1406                 tp->mac_mode = mac_mode;
1407                 tw32_f(MAC_MODE, tp->mac_mode);
1408                 udelay(40);
1409         }
1410
1411         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412                 if (phydev->speed == SPEED_10)
1413                         tw32(MAC_MI_STAT,
1414                              MAC_MI_STAT_10MBPS_MODE |
1415                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1416                 else
1417                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1418         }
1419
1420         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421                 tw32(MAC_TX_LENGTHS,
1422                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423                       (6 << TX_LENGTHS_IPG_SHIFT) |
1424                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1425         else
1426                 tw32(MAC_TX_LENGTHS,
1427                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428                       (6 << TX_LENGTHS_IPG_SHIFT) |
1429                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430
1431         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433             phydev->speed != tp->link_config.active_speed ||
1434             phydev->duplex != tp->link_config.active_duplex ||
1435             oldflowctrl != tp->link_config.active_flowctrl)
1436             linkmesg = 1;
1437
1438         tp->link_config.active_speed = phydev->speed;
1439         tp->link_config.active_duplex = phydev->duplex;
1440
1441         spin_unlock_bh(&tp->lock);
1442
1443         if (linkmesg)
1444                 tg3_link_report(tp);
1445 }
1446
1447 static int tg3_phy_init(struct tg3 *tp)
1448 {
1449         struct phy_device *phydev;
1450
1451         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1452                 return 0;
1453
1454         /* Bring the PHY back to a known state. */
1455         tg3_bmcr_reset(tp);
1456
1457         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1458
1459         /* Attach the MAC to the PHY. */
1460         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1461                              phydev->dev_flags, phydev->interface);
1462         if (IS_ERR(phydev)) {
1463                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464                 return PTR_ERR(phydev);
1465         }
1466
1467         /* Mask with MAC supported features. */
1468         switch (phydev->interface) {
1469         case PHY_INTERFACE_MODE_GMII:
1470         case PHY_INTERFACE_MODE_RGMII:
1471                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472                         phydev->supported &= (PHY_GBIT_FEATURES |
1473                                               SUPPORTED_Pause |
1474                                               SUPPORTED_Asym_Pause);
1475                         break;
1476                 }
1477                 /* fallthru */
1478         case PHY_INTERFACE_MODE_MII:
1479                 phydev->supported &= (PHY_BASIC_FEATURES |
1480                                       SUPPORTED_Pause |
1481                                       SUPPORTED_Asym_Pause);
1482                 break;
1483         default:
1484                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1485                 return -EINVAL;
1486         }
1487
1488         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1489
1490         phydev->advertising = phydev->supported;
1491
1492         return 0;
1493 }
1494
1495 static void tg3_phy_start(struct tg3 *tp)
1496 {
1497         struct phy_device *phydev;
1498
1499         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500                 return;
1501
1502         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1503
1504         if (tp->link_config.phy_is_low_power) {
1505                 tp->link_config.phy_is_low_power = 0;
1506                 phydev->speed = tp->link_config.orig_speed;
1507                 phydev->duplex = tp->link_config.orig_duplex;
1508                 phydev->autoneg = tp->link_config.orig_autoneg;
1509                 phydev->advertising = tp->link_config.orig_advertising;
1510         }
1511
1512         phy_start(phydev);
1513
1514         phy_start_aneg(phydev);
1515 }
1516
1517 static void tg3_phy_stop(struct tg3 *tp)
1518 {
1519         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1520                 return;
1521
1522         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1523 }
1524
1525 static void tg3_phy_fini(struct tg3 *tp)
1526 {
1527         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1528                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1530         }
1531 }
1532
1533 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1534 {
1535         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1537 }
1538
1539 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1540 {
1541         u32 phytest;
1542
1543         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1544                 u32 phy;
1545
1546                 tg3_writephy(tp, MII_TG3_FET_TEST,
1547                              phytest | MII_TG3_FET_SHADOW_EN);
1548                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1549                         if (enable)
1550                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1551                         else
1552                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1554                 }
1555                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1556         }
1557 }
1558
1559 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1560 {
1561         u32 reg;
1562
1563         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1564                 return;
1565
1566         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1567                 tg3_phy_fet_toggle_apd(tp, enable);
1568                 return;
1569         }
1570
1571         reg = MII_TG3_MISC_SHDW_WREN |
1572               MII_TG3_MISC_SHDW_SCR5_SEL |
1573               MII_TG3_MISC_SHDW_SCR5_LPED |
1574               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1575               MII_TG3_MISC_SHDW_SCR5_SDTL |
1576               MII_TG3_MISC_SHDW_SCR5_C125OE;
1577         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1578                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1579
1580         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581
1582
1583         reg = MII_TG3_MISC_SHDW_WREN |
1584               MII_TG3_MISC_SHDW_APD_SEL |
1585               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1586         if (enable)
1587                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1588
1589         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1590 }
1591
1592 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1593 {
1594         u32 phy;
1595
1596         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1597             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1598                 return;
1599
1600         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1601                 u32 ephy;
1602
1603                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1604                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1605
1606                         tg3_writephy(tp, MII_TG3_FET_TEST,
1607                                      ephy | MII_TG3_FET_SHADOW_EN);
1608                         if (!tg3_readphy(tp, reg, &phy)) {
1609                                 if (enable)
1610                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1611                                 else
1612                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1613                                 tg3_writephy(tp, reg, phy);
1614                         }
1615                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1616                 }
1617         } else {
1618                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1619                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1620                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1621                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1622                         if (enable)
1623                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1624                         else
1625                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1627                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1628                 }
1629         }
1630 }
1631
1632 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1633 {
1634         u32 val;
1635
1636         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1637                 return;
1638
1639         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1640             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1641                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1642                              (val | (1 << 15) | (1 << 4)));
1643 }
1644
1645 static void tg3_phy_apply_otp(struct tg3 *tp)
1646 {
1647         u32 otp, phy;
1648
1649         if (!tp->phy_otp)
1650                 return;
1651
1652         otp = tp->phy_otp;
1653
1654         /* Enable SM_DSP clock and tx 6dB coding. */
1655         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1656               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1657               MII_TG3_AUXCTL_ACTL_TX_6DB;
1658         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1659
1660         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1661         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1662         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1663
1664         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1665               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1666         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1667
1668         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1669         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1670         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1671
1672         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1673         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1674
1675         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1676         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1677
1678         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1679               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1680         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1681
1682         /* Turn off SM_DSP clock. */
1683         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1684               MII_TG3_AUXCTL_ACTL_TX_6DB;
1685         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1686 }
1687
1688 static int tg3_wait_macro_done(struct tg3 *tp)
1689 {
1690         int limit = 100;
1691
1692         while (limit--) {
1693                 u32 tmp32;
1694
1695                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1696                         if ((tmp32 & 0x1000) == 0)
1697                                 break;
1698                 }
1699         }
1700         if (limit < 0)
1701                 return -EBUSY;
1702
1703         return 0;
1704 }
1705
1706 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1707 {
1708         static const u32 test_pat[4][6] = {
1709         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1710         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1711         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1712         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1713         };
1714         int chan;
1715
1716         for (chan = 0; chan < 4; chan++) {
1717                 int i;
1718
1719                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720                              (chan * 0x2000) | 0x0200);
1721                 tg3_writephy(tp, 0x16, 0x0002);
1722
1723                 for (i = 0; i < 6; i++)
1724                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1725                                      test_pat[chan][i]);
1726
1727                 tg3_writephy(tp, 0x16, 0x0202);
1728                 if (tg3_wait_macro_done(tp)) {
1729                         *resetp = 1;
1730                         return -EBUSY;
1731                 }
1732
1733                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1734                              (chan * 0x2000) | 0x0200);
1735                 tg3_writephy(tp, 0x16, 0x0082);
1736                 if (tg3_wait_macro_done(tp)) {
1737                         *resetp = 1;
1738                         return -EBUSY;
1739                 }
1740
1741                 tg3_writephy(tp, 0x16, 0x0802);
1742                 if (tg3_wait_macro_done(tp)) {
1743                         *resetp = 1;
1744                         return -EBUSY;
1745                 }
1746
1747                 for (i = 0; i < 6; i += 2) {
1748                         u32 low, high;
1749
1750                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1751                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1752                             tg3_wait_macro_done(tp)) {
1753                                 *resetp = 1;
1754                                 return -EBUSY;
1755                         }
1756                         low &= 0x7fff;
1757                         high &= 0x000f;
1758                         if (low != test_pat[chan][i] ||
1759                             high != test_pat[chan][i+1]) {
1760                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1761                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1762                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1763
1764                                 return -EBUSY;
1765                         }
1766                 }
1767         }
1768
1769         return 0;
1770 }
1771
1772 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1773 {
1774         int chan;
1775
1776         for (chan = 0; chan < 4; chan++) {
1777                 int i;
1778
1779                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1780                              (chan * 0x2000) | 0x0200);
1781                 tg3_writephy(tp, 0x16, 0x0002);
1782                 for (i = 0; i < 6; i++)
1783                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1784                 tg3_writephy(tp, 0x16, 0x0202);
1785                 if (tg3_wait_macro_done(tp))
1786                         return -EBUSY;
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1793 {
1794         u32 reg32, phy9_orig;
1795         int retries, do_phy_reset, err;
1796
1797         retries = 10;
1798         do_phy_reset = 1;
1799         do {
1800                 if (do_phy_reset) {
1801                         err = tg3_bmcr_reset(tp);
1802                         if (err)
1803                                 return err;
1804                         do_phy_reset = 0;
1805                 }
1806
1807                 /* Disable transmitter and interrupt.  */
1808                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1809                         continue;
1810
1811                 reg32 |= 0x3000;
1812                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1813
1814                 /* Set full-duplex, 1000 mbps.  */
1815                 tg3_writephy(tp, MII_BMCR,
1816                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1817
1818                 /* Set to master mode.  */
1819                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1820                         continue;
1821
1822                 tg3_writephy(tp, MII_TG3_CTRL,
1823                              (MII_TG3_CTRL_AS_MASTER |
1824                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1825
1826                 /* Enable SM_DSP_CLOCK and 6dB.  */
1827                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1828
1829                 /* Block the PHY control access.  */
1830                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1831                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1832
1833                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1834                 if (!err)
1835                         break;
1836         } while (--retries);
1837
1838         err = tg3_phy_reset_chanpat(tp);
1839         if (err)
1840                 return err;
1841
1842         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1843         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1844
1845         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1846         tg3_writephy(tp, 0x16, 0x0000);
1847
1848         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1849             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1850                 /* Set Extended packet length bit for jumbo frames */
1851                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1852         }
1853         else {
1854                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1855         }
1856
1857         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1858
1859         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1860                 reg32 &= ~0x3000;
1861                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1862         } else if (!err)
1863                 err = -EBUSY;
1864
1865         return err;
1866 }
1867
1868 /* This will reset the tigon3 PHY if there is no valid
1869  * link unless the FORCE argument is non-zero.
1870  */
1871 static int tg3_phy_reset(struct tg3 *tp)
1872 {
1873         u32 cpmuctrl;
1874         u32 phy_status;
1875         int err;
1876
1877         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1878                 u32 val;
1879
1880                 val = tr32(GRC_MISC_CFG);
1881                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1882                 udelay(40);
1883         }
1884         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1885         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1886         if (err != 0)
1887                 return -EBUSY;
1888
1889         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1890                 netif_carrier_off(tp->dev);
1891                 tg3_link_report(tp);
1892         }
1893
1894         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1895             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1896             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1897                 err = tg3_phy_reset_5703_4_5(tp);
1898                 if (err)
1899                         return err;
1900                 goto out;
1901         }
1902
1903         cpmuctrl = 0;
1904         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1905             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1906                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1907                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1908                         tw32(TG3_CPMU_CTRL,
1909                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1910         }
1911
1912         err = tg3_bmcr_reset(tp);
1913         if (err)
1914                 return err;
1915
1916         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1917                 u32 phy;
1918
1919                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1920                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1921
1922                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1923         }
1924
1925         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1926             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1927                 u32 val;
1928
1929                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1930                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1931                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1932                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1933                         udelay(40);
1934                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1935                 }
1936         }
1937
1938         tg3_phy_apply_otp(tp);
1939
1940         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1941                 tg3_phy_toggle_apd(tp, true);
1942         else
1943                 tg3_phy_toggle_apd(tp, false);
1944
1945 out:
1946         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1947                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1949                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1950                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1951                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1952                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1953         }
1954         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1955                 tg3_writephy(tp, 0x1c, 0x8d68);
1956                 tg3_writephy(tp, 0x1c, 0x8d68);
1957         }
1958         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1959                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1961                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1962                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1963                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1964                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1965                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1966                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1967         }
1968         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1970                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1971                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1972                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1973                         tg3_writephy(tp, MII_TG3_TEST1,
1974                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1975                 } else
1976                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1977                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1978         }
1979         /* Set Extended packet length bit (bit 14) on all chips that */
1980         /* support jumbo frames */
1981         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1982                 /* Cannot do read-modify-write on 5401 */
1983                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1984         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1985                 u32 phy_reg;
1986
1987                 /* Set bit 14 with read-modify-write to preserve other bits */
1988                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1990                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1991         }
1992
1993         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994          * jumbo frames transmission.
1995          */
1996         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1997                 u32 phy_reg;
1998
1999                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2000                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
2001                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2002         }
2003
2004         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2005                 /* adjust output voltage */
2006                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2007         }
2008
2009         tg3_phy_toggle_automdix(tp, 1);
2010         tg3_phy_set_wirespeed(tp);
2011         return 0;
2012 }
2013
2014 static void tg3_frob_aux_power(struct tg3 *tp)
2015 {
2016         struct tg3 *tp_peer = tp;
2017
2018         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2019                 return;
2020
2021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2022             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2023             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2024                 struct net_device *dev_peer;
2025
2026                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2027                 /* remove_one() may have been run on the peer. */
2028                 if (!dev_peer)
2029                         tp_peer = tp;
2030                 else
2031                         tp_peer = netdev_priv(dev_peer);
2032         }
2033
2034         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2035             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2036             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2037             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2038                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2039                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2040                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041                                     (GRC_LCLCTRL_GPIO_OE0 |
2042                                      GRC_LCLCTRL_GPIO_OE1 |
2043                                      GRC_LCLCTRL_GPIO_OE2 |
2044                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2045                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2046                                     100);
2047                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2048                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2049                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2050                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2051                                              GRC_LCLCTRL_GPIO_OE1 |
2052                                              GRC_LCLCTRL_GPIO_OE2 |
2053                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2054                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2055                                              tp->grc_local_ctrl;
2056                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2057
2058                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2059                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2060
2061                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2062                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2063                 } else {
2064                         u32 no_gpio2;
2065                         u32 grc_local_ctrl = 0;
2066
2067                         if (tp_peer != tp &&
2068                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2069                                 return;
2070
2071                         /* Workaround to prevent overdrawing Amps. */
2072                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2073                             ASIC_REV_5714) {
2074                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2075                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2076                                             grc_local_ctrl, 100);
2077                         }
2078
2079                         /* On 5753 and variants, GPIO2 cannot be used. */
2080                         no_gpio2 = tp->nic_sram_data_cfg &
2081                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2082
2083                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2084                                          GRC_LCLCTRL_GPIO_OE1 |
2085                                          GRC_LCLCTRL_GPIO_OE2 |
2086                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2087                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2088                         if (no_gpio2) {
2089                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2090                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2091                         }
2092                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2093                                                     grc_local_ctrl, 100);
2094
2095                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2096
2097                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098                                                     grc_local_ctrl, 100);
2099
2100                         if (!no_gpio2) {
2101                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2102                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2103                                             grc_local_ctrl, 100);
2104                         }
2105                 }
2106         } else {
2107                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2108                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2109                         if (tp_peer != tp &&
2110                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2111                                 return;
2112
2113                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2114                                     (GRC_LCLCTRL_GPIO_OE1 |
2115                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2116
2117                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118                                     GRC_LCLCTRL_GPIO_OE1, 100);
2119
2120                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121                                     (GRC_LCLCTRL_GPIO_OE1 |
2122                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2123                 }
2124         }
2125 }
2126
2127 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2128 {
2129         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2130                 return 1;
2131         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2132                 if (speed != SPEED_10)
2133                         return 1;
2134         } else if (speed == SPEED_10)
2135                 return 1;
2136
2137         return 0;
2138 }
2139
2140 static int tg3_setup_phy(struct tg3 *, int);
2141
2142 #define RESET_KIND_SHUTDOWN     0
2143 #define RESET_KIND_INIT         1
2144 #define RESET_KIND_SUSPEND      2
2145
2146 static void tg3_write_sig_post_reset(struct tg3 *, int);
2147 static int tg3_halt_cpu(struct tg3 *, u32);
2148
2149 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2150 {
2151         u32 val;
2152
2153         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2154                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2155                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2156                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2157
2158                         sg_dig_ctrl |=
2159                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2160                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2161                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2162                 }
2163                 return;
2164         }
2165
2166         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2167                 tg3_bmcr_reset(tp);
2168                 val = tr32(GRC_MISC_CFG);
2169                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2170                 udelay(40);
2171                 return;
2172         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2173                 u32 phytest;
2174                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2175                         u32 phy;
2176
2177                         tg3_writephy(tp, MII_ADVERTISE, 0);
2178                         tg3_writephy(tp, MII_BMCR,
2179                                      BMCR_ANENABLE | BMCR_ANRESTART);
2180
2181                         tg3_writephy(tp, MII_TG3_FET_TEST,
2182                                      phytest | MII_TG3_FET_SHADOW_EN);
2183                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2184                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2185                                 tg3_writephy(tp,
2186                                              MII_TG3_FET_SHDW_AUXMODE4,
2187                                              phy);
2188                         }
2189                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2190                 }
2191                 return;
2192         } else if (do_low_power) {
2193                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2194                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2195
2196                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2197                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2198                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2199                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2200                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2201         }
2202
2203         /* The PHY should not be powered down on some chips because
2204          * of bugs.
2205          */
2206         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2207             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2208             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2209              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2210                 return;
2211
2212         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2213             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2214                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2215                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2216                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2217                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2218         }
2219
2220         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2221 }
2222
2223 /* tp->lock is held. */
2224 static int tg3_nvram_lock(struct tg3 *tp)
2225 {
2226         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2227                 int i;
2228
2229                 if (tp->nvram_lock_cnt == 0) {
2230                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2231                         for (i = 0; i < 8000; i++) {
2232                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2233                                         break;
2234                                 udelay(20);
2235                         }
2236                         if (i == 8000) {
2237                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2238                                 return -ENODEV;
2239                         }
2240                 }
2241                 tp->nvram_lock_cnt++;
2242         }
2243         return 0;
2244 }
2245
2246 /* tp->lock is held. */
2247 static void tg3_nvram_unlock(struct tg3 *tp)
2248 {
2249         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2250                 if (tp->nvram_lock_cnt > 0)
2251                         tp->nvram_lock_cnt--;
2252                 if (tp->nvram_lock_cnt == 0)
2253                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2254         }
2255 }
2256
2257 /* tp->lock is held. */
2258 static void tg3_enable_nvram_access(struct tg3 *tp)
2259 {
2260         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2261             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2262                 u32 nvaccess = tr32(NVRAM_ACCESS);
2263
2264                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2265         }
2266 }
2267
2268 /* tp->lock is held. */
2269 static void tg3_disable_nvram_access(struct tg3 *tp)
2270 {
2271         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2272             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2273                 u32 nvaccess = tr32(NVRAM_ACCESS);
2274
2275                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2276         }
2277 }
2278
2279 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2280                                         u32 offset, u32 *val)
2281 {
2282         u32 tmp;
2283         int i;
2284
2285         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2286                 return -EINVAL;
2287
2288         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2289                                         EEPROM_ADDR_DEVID_MASK |
2290                                         EEPROM_ADDR_READ);
2291         tw32(GRC_EEPROM_ADDR,
2292              tmp |
2293              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2294              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2295               EEPROM_ADDR_ADDR_MASK) |
2296              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2297
2298         for (i = 0; i < 1000; i++) {
2299                 tmp = tr32(GRC_EEPROM_ADDR);
2300
2301                 if (tmp & EEPROM_ADDR_COMPLETE)
2302                         break;
2303                 msleep(1);
2304         }
2305         if (!(tmp & EEPROM_ADDR_COMPLETE))
2306                 return -EBUSY;
2307
2308         tmp = tr32(GRC_EEPROM_DATA);
2309
2310         /*
2311          * The data will always be opposite the native endian
2312          * format.  Perform a blind byteswap to compensate.
2313          */
2314         *val = swab32(tmp);
2315
2316         return 0;
2317 }
2318
2319 #define NVRAM_CMD_TIMEOUT 10000
2320
2321 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2322 {
2323         int i;
2324
2325         tw32(NVRAM_CMD, nvram_cmd);
2326         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2327                 udelay(10);
2328                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2329                         udelay(10);
2330                         break;
2331                 }
2332         }
2333
2334         if (i == NVRAM_CMD_TIMEOUT)
2335                 return -EBUSY;
2336
2337         return 0;
2338 }
2339
2340 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2341 {
2342         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2343             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2344             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2345            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2346             (tp->nvram_jedecnum == JEDEC_ATMEL))
2347
2348                 addr = ((addr / tp->nvram_pagesize) <<
2349                         ATMEL_AT45DB0X1B_PAGE_POS) +
2350                        (addr % tp->nvram_pagesize);
2351
2352         return addr;
2353 }
2354
2355 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2356 {
2357         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2358             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2359             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2360            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2361             (tp->nvram_jedecnum == JEDEC_ATMEL))
2362
2363                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2364                         tp->nvram_pagesize) +
2365                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2366
2367         return addr;
2368 }
2369
2370 /* NOTE: Data read in from NVRAM is byteswapped according to
2371  * the byteswapping settings for all other register accesses.
2372  * tg3 devices are BE devices, so on a BE machine, the data
2373  * returned will be exactly as it is seen in NVRAM.  On a LE
2374  * machine, the 32-bit value will be byteswapped.
2375  */
2376 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2377 {
2378         int ret;
2379
2380         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2381                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2382
2383         offset = tg3_nvram_phys_addr(tp, offset);
2384
2385         if (offset > NVRAM_ADDR_MSK)
2386                 return -EINVAL;
2387
2388         ret = tg3_nvram_lock(tp);
2389         if (ret)
2390                 return ret;
2391
2392         tg3_enable_nvram_access(tp);
2393
2394         tw32(NVRAM_ADDR, offset);
2395         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2396                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2397
2398         if (ret == 0)
2399                 *val = tr32(NVRAM_RDDATA);
2400
2401         tg3_disable_nvram_access(tp);
2402
2403         tg3_nvram_unlock(tp);
2404
2405         return ret;
2406 }
2407
2408 /* Ensures NVRAM data is in bytestream format. */
2409 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2410 {
2411         u32 v;
2412         int res = tg3_nvram_read(tp, offset, &v);
2413         if (!res)
2414                 *val = cpu_to_be32(v);
2415         return res;
2416 }
2417
2418 /* tp->lock is held. */
2419 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2420 {
2421         u32 addr_high, addr_low;
2422         int i;
2423
2424         addr_high = ((tp->dev->dev_addr[0] << 8) |
2425                      tp->dev->dev_addr[1]);
2426         addr_low = ((tp->dev->dev_addr[2] << 24) |
2427                     (tp->dev->dev_addr[3] << 16) |
2428                     (tp->dev->dev_addr[4] <<  8) |
2429                     (tp->dev->dev_addr[5] <<  0));
2430         for (i = 0; i < 4; i++) {
2431                 if (i == 1 && skip_mac_1)
2432                         continue;
2433                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2434                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2435         }
2436
2437         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2438             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2439                 for (i = 0; i < 12; i++) {
2440                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2441                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2442                 }
2443         }
2444
2445         addr_high = (tp->dev->dev_addr[0] +
2446                      tp->dev->dev_addr[1] +
2447                      tp->dev->dev_addr[2] +
2448                      tp->dev->dev_addr[3] +
2449                      tp->dev->dev_addr[4] +
2450                      tp->dev->dev_addr[5]) &
2451                 TX_BACKOFF_SEED_MASK;
2452         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2453 }
2454
2455 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2456 {
2457         u32 misc_host_ctrl;
2458         bool device_should_wake, do_low_power;
2459
2460         /* Make sure register accesses (indirect or otherwise)
2461          * will function correctly.
2462          */
2463         pci_write_config_dword(tp->pdev,
2464                                TG3PCI_MISC_HOST_CTRL,
2465                                tp->misc_host_ctrl);
2466
2467         switch (state) {
2468         case PCI_D0:
2469                 pci_enable_wake(tp->pdev, state, false);
2470                 pci_set_power_state(tp->pdev, PCI_D0);
2471
2472                 /* Switch out of Vaux if it is a NIC */
2473                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2474                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2475
2476                 return 0;
2477
2478         case PCI_D1:
2479         case PCI_D2:
2480         case PCI_D3hot:
2481                 break;
2482
2483         default:
2484                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2485                         tp->dev->name, state);
2486                 return -EINVAL;
2487         }
2488
2489         /* Restore the CLKREQ setting. */
2490         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2491                 u16 lnkctl;
2492
2493                 pci_read_config_word(tp->pdev,
2494                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2495                                      &lnkctl);
2496                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2497                 pci_write_config_word(tp->pdev,
2498                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2499                                       lnkctl);
2500         }
2501
2502         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2503         tw32(TG3PCI_MISC_HOST_CTRL,
2504              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2505
2506         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2507                              device_may_wakeup(&tp->pdev->dev) &&
2508                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2509
2510         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2511                 do_low_power = false;
2512                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2513                     !tp->link_config.phy_is_low_power) {
2514                         struct phy_device *phydev;
2515                         u32 phyid, advertising;
2516
2517                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2518
2519                         tp->link_config.phy_is_low_power = 1;
2520
2521                         tp->link_config.orig_speed = phydev->speed;
2522                         tp->link_config.orig_duplex = phydev->duplex;
2523                         tp->link_config.orig_autoneg = phydev->autoneg;
2524                         tp->link_config.orig_advertising = phydev->advertising;
2525
2526                         advertising = ADVERTISED_TP |
2527                                       ADVERTISED_Pause |
2528                                       ADVERTISED_Autoneg |
2529                                       ADVERTISED_10baseT_Half;
2530
2531                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2532                             device_should_wake) {
2533                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2534                                         advertising |=
2535                                                 ADVERTISED_100baseT_Half |
2536                                                 ADVERTISED_100baseT_Full |
2537                                                 ADVERTISED_10baseT_Full;
2538                                 else
2539                                         advertising |= ADVERTISED_10baseT_Full;
2540                         }
2541
2542                         phydev->advertising = advertising;
2543
2544                         phy_start_aneg(phydev);
2545
2546                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2547                         if (phyid != TG3_PHY_ID_BCMAC131) {
2548                                 phyid &= TG3_PHY_OUI_MASK;
2549                                 if (phyid == TG3_PHY_OUI_1 ||
2550                                     phyid == TG3_PHY_OUI_2 ||
2551                                     phyid == TG3_PHY_OUI_3)
2552                                         do_low_power = true;
2553                         }
2554                 }
2555         } else {
2556                 do_low_power = true;
2557
2558                 if (tp->link_config.phy_is_low_power == 0) {
2559                         tp->link_config.phy_is_low_power = 1;
2560                         tp->link_config.orig_speed = tp->link_config.speed;
2561                         tp->link_config.orig_duplex = tp->link_config.duplex;
2562                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2563                 }
2564
2565                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2566                         tp->link_config.speed = SPEED_10;
2567                         tp->link_config.duplex = DUPLEX_HALF;
2568                         tp->link_config.autoneg = AUTONEG_ENABLE;
2569                         tg3_setup_phy(tp, 0);
2570                 }
2571         }
2572
2573         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2574                 u32 val;
2575
2576                 val = tr32(GRC_VCPU_EXT_CTRL);
2577                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2578         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2579                 int i;
2580                 u32 val;
2581
2582                 for (i = 0; i < 200; i++) {
2583                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2584                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2585                                 break;
2586                         msleep(1);
2587                 }
2588         }
2589         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2590                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2591                                                      WOL_DRV_STATE_SHUTDOWN |
2592                                                      WOL_DRV_WOL |
2593                                                      WOL_SET_MAGIC_PKT);
2594
2595         if (device_should_wake) {
2596                 u32 mac_mode;
2597
2598                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2599                         if (do_low_power) {
2600                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2601                                 udelay(40);
2602                         }
2603
2604                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2605                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2606                         else
2607                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2608
2609                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2610                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2611                             ASIC_REV_5700) {
2612                                 u32 speed = (tp->tg3_flags &
2613                                              TG3_FLAG_WOL_SPEED_100MB) ?
2614                                              SPEED_100 : SPEED_10;
2615                                 if (tg3_5700_link_polarity(tp, speed))
2616                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2617                                 else
2618                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2619                         }
2620                 } else {
2621                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2622                 }
2623
2624                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2625                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2626
2627                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2628                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2629                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2630                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2631                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2632                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2633
2634                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2635                         mac_mode |= tp->mac_mode &
2636                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2637                         if (mac_mode & MAC_MODE_APE_TX_EN)
2638                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2639                 }
2640
2641                 tw32_f(MAC_MODE, mac_mode);
2642                 udelay(100);
2643
2644                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2645                 udelay(10);
2646         }
2647
2648         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2649             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2650              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2651                 u32 base_val;
2652
2653                 base_val = tp->pci_clock_ctrl;
2654                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2655                              CLOCK_CTRL_TXCLK_DISABLE);
2656
2657                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2658                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2659         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2660                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2661                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2662                 /* do nothing */
2663         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2664                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2665                 u32 newbits1, newbits2;
2666
2667                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2668                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2669                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2670                                     CLOCK_CTRL_TXCLK_DISABLE |
2671                                     CLOCK_CTRL_ALTCLK);
2672                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2673                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2674                         newbits1 = CLOCK_CTRL_625_CORE;
2675                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2676                 } else {
2677                         newbits1 = CLOCK_CTRL_ALTCLK;
2678                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2679                 }
2680
2681                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2682                             40);
2683
2684                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2685                             40);
2686
2687                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2688                         u32 newbits3;
2689
2690                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2691                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2692                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2693                                             CLOCK_CTRL_TXCLK_DISABLE |
2694                                             CLOCK_CTRL_44MHZ_CORE);
2695                         } else {
2696                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2697                         }
2698
2699                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2700                                     tp->pci_clock_ctrl | newbits3, 40);
2701                 }
2702         }
2703
2704         if (!(device_should_wake) &&
2705             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2706                 tg3_power_down_phy(tp, do_low_power);
2707
2708         tg3_frob_aux_power(tp);
2709
2710         /* Workaround for unstable PLL clock */
2711         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2712             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2713                 u32 val = tr32(0x7d00);
2714
2715                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2716                 tw32(0x7d00, val);
2717                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2718                         int err;
2719
2720                         err = tg3_nvram_lock(tp);
2721                         tg3_halt_cpu(tp, RX_CPU_BASE);
2722                         if (!err)
2723                                 tg3_nvram_unlock(tp);
2724                 }
2725         }
2726
2727         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2728
2729         if (device_should_wake)
2730                 pci_enable_wake(tp->pdev, state, true);
2731
2732         /* Finally, set the new power state. */
2733         pci_set_power_state(tp->pdev, state);
2734
2735         return 0;
2736 }
2737
2738 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2739 {
2740         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2741         case MII_TG3_AUX_STAT_10HALF:
2742                 *speed = SPEED_10;
2743                 *duplex = DUPLEX_HALF;
2744                 break;
2745
2746         case MII_TG3_AUX_STAT_10FULL:
2747                 *speed = SPEED_10;
2748                 *duplex = DUPLEX_FULL;
2749                 break;
2750
2751         case MII_TG3_AUX_STAT_100HALF:
2752                 *speed = SPEED_100;
2753                 *duplex = DUPLEX_HALF;
2754                 break;
2755
2756         case MII_TG3_AUX_STAT_100FULL:
2757                 *speed = SPEED_100;
2758                 *duplex = DUPLEX_FULL;
2759                 break;
2760
2761         case MII_TG3_AUX_STAT_1000HALF:
2762                 *speed = SPEED_1000;
2763                 *duplex = DUPLEX_HALF;
2764                 break;
2765
2766         case MII_TG3_AUX_STAT_1000FULL:
2767                 *speed = SPEED_1000;
2768                 *duplex = DUPLEX_FULL;
2769                 break;
2770
2771         default:
2772                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2773                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2774                                  SPEED_10;
2775                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2776                                   DUPLEX_HALF;
2777                         break;
2778                 }
2779                 *speed = SPEED_INVALID;
2780                 *duplex = DUPLEX_INVALID;
2781                 break;
2782         }
2783 }
2784
2785 static void tg3_phy_copper_begin(struct tg3 *tp)
2786 {
2787         u32 new_adv;
2788         int i;
2789
2790         if (tp->link_config.phy_is_low_power) {
2791                 /* Entering low power mode.  Disable gigabit and
2792                  * 100baseT advertisements.
2793                  */
2794                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2795
2796                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2797                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2798                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2799                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2800
2801                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2802         } else if (tp->link_config.speed == SPEED_INVALID) {
2803                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2804                         tp->link_config.advertising &=
2805                                 ~(ADVERTISED_1000baseT_Half |
2806                                   ADVERTISED_1000baseT_Full);
2807
2808                 new_adv = ADVERTISE_CSMA;
2809                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2810                         new_adv |= ADVERTISE_10HALF;
2811                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2812                         new_adv |= ADVERTISE_10FULL;
2813                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2814                         new_adv |= ADVERTISE_100HALF;
2815                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2816                         new_adv |= ADVERTISE_100FULL;
2817
2818                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2819
2820                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821
2822                 if (tp->link_config.advertising &
2823                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2824                         new_adv = 0;
2825                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2826                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2827                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2828                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2829                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2830                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2831                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2832                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2833                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2834                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2835                 } else {
2836                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2837                 }
2838         } else {
2839                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2840                 new_adv |= ADVERTISE_CSMA;
2841
2842                 /* Asking for a specific link mode. */
2843                 if (tp->link_config.speed == SPEED_1000) {
2844                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2845
2846                         if (tp->link_config.duplex == DUPLEX_FULL)
2847                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2848                         else
2849                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2850                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2851                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2852                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2853                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2854                 } else {
2855                         if (tp->link_config.speed == SPEED_100) {
2856                                 if (tp->link_config.duplex == DUPLEX_FULL)
2857                                         new_adv |= ADVERTISE_100FULL;
2858                                 else
2859                                         new_adv |= ADVERTISE_100HALF;
2860                         } else {
2861                                 if (tp->link_config.duplex == DUPLEX_FULL)
2862                                         new_adv |= ADVERTISE_10FULL;
2863                                 else
2864                                         new_adv |= ADVERTISE_10HALF;
2865                         }
2866                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2867
2868                         new_adv = 0;
2869                 }
2870
2871                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2872         }
2873
2874         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2875             tp->link_config.speed != SPEED_INVALID) {
2876                 u32 bmcr, orig_bmcr;
2877
2878                 tp->link_config.active_speed = tp->link_config.speed;
2879                 tp->link_config.active_duplex = tp->link_config.duplex;
2880
2881                 bmcr = 0;
2882                 switch (tp->link_config.speed) {
2883                 default:
2884                 case SPEED_10:
2885                         break;
2886
2887                 case SPEED_100:
2888                         bmcr |= BMCR_SPEED100;
2889                         break;
2890
2891                 case SPEED_1000:
2892                         bmcr |= TG3_BMCR_SPEED1000;
2893                         break;
2894                 }
2895
2896                 if (tp->link_config.duplex == DUPLEX_FULL)
2897                         bmcr |= BMCR_FULLDPLX;
2898
2899                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2900                     (bmcr != orig_bmcr)) {
2901                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2902                         for (i = 0; i < 1500; i++) {
2903                                 u32 tmp;
2904
2905                                 udelay(10);
2906                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2907                                     tg3_readphy(tp, MII_BMSR, &tmp))
2908                                         continue;
2909                                 if (!(tmp & BMSR_LSTATUS)) {
2910                                         udelay(40);
2911                                         break;
2912                                 }
2913                         }
2914                         tg3_writephy(tp, MII_BMCR, bmcr);
2915                         udelay(40);
2916                 }
2917         } else {
2918                 tg3_writephy(tp, MII_BMCR,
2919                              BMCR_ANENABLE | BMCR_ANRESTART);
2920         }
2921 }
2922
2923 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2924 {
2925         int err;
2926
2927         /* Turn off tap power management. */
2928         /* Set Extended packet length bit */
2929         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2930
2931         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2932         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2933
2934         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2935         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2936
2937         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2938         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2939
2940         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2941         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2942
2943         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2944         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2945
2946         udelay(40);
2947
2948         return err;
2949 }
2950
2951 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2952 {
2953         u32 adv_reg, all_mask = 0;
2954
2955         if (mask & ADVERTISED_10baseT_Half)
2956                 all_mask |= ADVERTISE_10HALF;
2957         if (mask & ADVERTISED_10baseT_Full)
2958                 all_mask |= ADVERTISE_10FULL;
2959         if (mask & ADVERTISED_100baseT_Half)
2960                 all_mask |= ADVERTISE_100HALF;
2961         if (mask & ADVERTISED_100baseT_Full)
2962                 all_mask |= ADVERTISE_100FULL;
2963
2964         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2965                 return 0;
2966
2967         if ((adv_reg & all_mask) != all_mask)
2968                 return 0;
2969         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2970                 u32 tg3_ctrl;
2971
2972                 all_mask = 0;
2973                 if (mask & ADVERTISED_1000baseT_Half)
2974                         all_mask |= ADVERTISE_1000HALF;
2975                 if (mask & ADVERTISED_1000baseT_Full)
2976                         all_mask |= ADVERTISE_1000FULL;
2977
2978                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2979                         return 0;
2980
2981                 if ((tg3_ctrl & all_mask) != all_mask)
2982                         return 0;
2983         }
2984         return 1;
2985 }
2986
2987 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2988 {
2989         u32 curadv, reqadv;
2990
2991         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2992                 return 1;
2993
2994         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2995         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2996
2997         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2998                 if (curadv != reqadv)
2999                         return 0;
3000
3001                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3002                         tg3_readphy(tp, MII_LPA, rmtadv);
3003         } else {
3004                 /* Reprogram the advertisement register, even if it
3005                  * does not affect the current link.  If the link
3006                  * gets renegotiated in the future, we can save an
3007                  * additional renegotiation cycle by advertising
3008                  * it correctly in the first place.
3009                  */
3010                 if (curadv != reqadv) {
3011                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3012                                      ADVERTISE_PAUSE_ASYM);
3013                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3014                 }
3015         }
3016
3017         return 1;
3018 }
3019
3020 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3021 {
3022         int current_link_up;
3023         u32 bmsr, dummy;
3024         u32 lcl_adv, rmt_adv;
3025         u16 current_speed;
3026         u8 current_duplex;
3027         int i, err;
3028
3029         tw32(MAC_EVENT, 0);
3030
3031         tw32_f(MAC_STATUS,
3032              (MAC_STATUS_SYNC_CHANGED |
3033               MAC_STATUS_CFG_CHANGED |
3034               MAC_STATUS_MI_COMPLETION |
3035               MAC_STATUS_LNKSTATE_CHANGED));
3036         udelay(40);
3037
3038         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3039                 tw32_f(MAC_MI_MODE,
3040                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3041                 udelay(80);
3042         }
3043
3044         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3045
3046         /* Some third-party PHYs need to be reset on link going
3047          * down.
3048          */
3049         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3050              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3051              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3052             netif_carrier_ok(tp->dev)) {
3053                 tg3_readphy(tp, MII_BMSR, &bmsr);
3054                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3055                     !(bmsr & BMSR_LSTATUS))
3056                         force_reset = 1;
3057         }
3058         if (force_reset)
3059                 tg3_phy_reset(tp);
3060
3061         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3062                 tg3_readphy(tp, MII_BMSR, &bmsr);
3063                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3064                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3065                         bmsr = 0;
3066
3067                 if (!(bmsr & BMSR_LSTATUS)) {
3068                         err = tg3_init_5401phy_dsp(tp);
3069                         if (err)
3070                                 return err;
3071
3072                         tg3_readphy(tp, MII_BMSR, &bmsr);
3073                         for (i = 0; i < 1000; i++) {
3074                                 udelay(10);
3075                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3076                                     (bmsr & BMSR_LSTATUS)) {
3077                                         udelay(40);
3078                                         break;
3079                                 }
3080                         }
3081
3082                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3083                             !(bmsr & BMSR_LSTATUS) &&
3084                             tp->link_config.active_speed == SPEED_1000) {
3085                                 err = tg3_phy_reset(tp);
3086                                 if (!err)
3087                                         err = tg3_init_5401phy_dsp(tp);
3088                                 if (err)
3089                                         return err;
3090                         }
3091                 }
3092         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3093                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3094                 /* 5701 {A0,B0} CRC bug workaround */
3095                 tg3_writephy(tp, 0x15, 0x0a75);
3096                 tg3_writephy(tp, 0x1c, 0x8c68);
3097                 tg3_writephy(tp, 0x1c, 0x8d68);
3098                 tg3_writephy(tp, 0x1c, 0x8c68);
3099         }
3100
3101         /* Clear pending interrupts... */
3102         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3103         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3104
3105         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3106                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3107         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3108                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3109
3110         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3111             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3112                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3113                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3115                 else
3116                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3117         }
3118
3119         current_link_up = 0;
3120         current_speed = SPEED_INVALID;
3121         current_duplex = DUPLEX_INVALID;
3122
3123         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3124                 u32 val;
3125
3126                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3127                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3128                 if (!(val & (1 << 10))) {
3129                         val |= (1 << 10);
3130                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3131                         goto relink;
3132                 }
3133         }
3134
3135         bmsr = 0;
3136         for (i = 0; i < 100; i++) {
3137                 tg3_readphy(tp, MII_BMSR, &bmsr);
3138                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3139                     (bmsr & BMSR_LSTATUS))
3140                         break;
3141                 udelay(40);
3142         }
3143
3144         if (bmsr & BMSR_LSTATUS) {
3145                 u32 aux_stat, bmcr;
3146
3147                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3148                 for (i = 0; i < 2000; i++) {
3149                         udelay(10);
3150                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3151                             aux_stat)
3152                                 break;
3153                 }
3154
3155                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3156                                              &current_speed,
3157                                              &current_duplex);
3158
3159                 bmcr = 0;
3160                 for (i = 0; i < 200; i++) {
3161                         tg3_readphy(tp, MII_BMCR, &bmcr);
3162                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3163                                 continue;
3164                         if (bmcr && bmcr != 0x7fff)
3165                                 break;
3166                         udelay(10);
3167                 }
3168
3169                 lcl_adv = 0;
3170                 rmt_adv = 0;
3171
3172                 tp->link_config.active_speed = current_speed;
3173                 tp->link_config.active_duplex = current_duplex;
3174
3175                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3176                         if ((bmcr & BMCR_ANENABLE) &&
3177                             tg3_copper_is_advertising_all(tp,
3178                                                 tp->link_config.advertising)) {
3179                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3180                                                                   &rmt_adv))
3181                                         current_link_up = 1;
3182                         }
3183                 } else {
3184                         if (!(bmcr & BMCR_ANENABLE) &&
3185                             tp->link_config.speed == current_speed &&
3186                             tp->link_config.duplex == current_duplex &&
3187                             tp->link_config.flowctrl ==
3188                             tp->link_config.active_flowctrl) {
3189                                 current_link_up = 1;
3190                         }
3191                 }
3192
3193                 if (current_link_up == 1 &&
3194                     tp->link_config.active_duplex == DUPLEX_FULL)
3195                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3196         }
3197
3198 relink:
3199         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3200                 u32 tmp;
3201
3202                 tg3_phy_copper_begin(tp);
3203
3204                 tg3_readphy(tp, MII_BMSR, &tmp);
3205                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3206                     (tmp & BMSR_LSTATUS))
3207                         current_link_up = 1;
3208         }
3209
3210         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3211         if (current_link_up == 1) {
3212                 if (tp->link_config.active_speed == SPEED_100 ||
3213                     tp->link_config.active_speed == SPEED_10)
3214                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3215                 else
3216                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3217         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3218                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3219         else
3220                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3221
3222         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3223         if (tp->link_config.active_duplex == DUPLEX_HALF)
3224                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3225
3226         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3227                 if (current_link_up == 1 &&
3228                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3229                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3230                 else
3231                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3232         }
3233
3234         /* ??? Without this setting Netgear GA302T PHY does not
3235          * ??? send/receive packets...
3236          */
3237         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3238             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3239                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3240                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3241                 udelay(80);
3242         }
3243
3244         tw32_f(MAC_MODE, tp->mac_mode);
3245         udelay(40);
3246
3247         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3248                 /* Polled via timer. */
3249                 tw32_f(MAC_EVENT, 0);
3250         } else {
3251                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3252         }
3253         udelay(40);
3254
3255         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3256             current_link_up == 1 &&
3257             tp->link_config.active_speed == SPEED_1000 &&
3258             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3259              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3260                 udelay(120);
3261                 tw32_f(MAC_STATUS,
3262                      (MAC_STATUS_SYNC_CHANGED |
3263                       MAC_STATUS_CFG_CHANGED));
3264                 udelay(40);
3265                 tg3_write_mem(tp,
3266                               NIC_SRAM_FIRMWARE_MBOX,
3267                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3268         }
3269
3270         /* Prevent send BD corruption. */
3271         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3272                 u16 oldlnkctl, newlnkctl;
3273
3274                 pci_read_config_word(tp->pdev,
3275                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3276                                      &oldlnkctl);
3277                 if (tp->link_config.active_speed == SPEED_100 ||
3278                     tp->link_config.active_speed == SPEED_10)
3279                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3280                 else
3281                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3282                 if (newlnkctl != oldlnkctl)
3283                         pci_write_config_word(tp->pdev,
3284                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3285                                               newlnkctl);
3286         }
3287
3288         if (current_link_up != netif_carrier_ok(tp->dev)) {
3289                 if (current_link_up)
3290                         netif_carrier_on(tp->dev);
3291                 else
3292                         netif_carrier_off(tp->dev);
3293                 tg3_link_report(tp);
3294         }
3295
3296         return 0;
3297 }
3298
3299 struct tg3_fiber_aneginfo {
3300         int state;
3301 #define ANEG_STATE_UNKNOWN              0
3302 #define ANEG_STATE_AN_ENABLE            1
3303 #define ANEG_STATE_RESTART_INIT         2
3304 #define ANEG_STATE_RESTART              3
3305 #define ANEG_STATE_DISABLE_LINK_OK      4
3306 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3307 #define ANEG_STATE_ABILITY_DETECT       6
3308 #define ANEG_STATE_ACK_DETECT_INIT      7
3309 #define ANEG_STATE_ACK_DETECT           8
3310 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3311 #define ANEG_STATE_COMPLETE_ACK         10
3312 #define ANEG_STATE_IDLE_DETECT_INIT     11
3313 #define ANEG_STATE_IDLE_DETECT          12
3314 #define ANEG_STATE_LINK_OK              13
3315 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3316 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3317
3318         u32 flags;
3319 #define MR_AN_ENABLE            0x00000001
3320 #define MR_RESTART_AN           0x00000002
3321 #define MR_AN_COMPLETE          0x00000004
3322 #define MR_PAGE_RX              0x00000008
3323 #define MR_NP_LOADED            0x00000010
3324 #define MR_TOGGLE_TX            0x00000020
3325 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3326 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3327 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3328 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3329 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3330 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3331 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3332 #define MR_TOGGLE_RX            0x00002000
3333 #define MR_NP_RX                0x00004000
3334
3335 #define MR_LINK_OK              0x80000000
3336
3337         unsigned long link_time, cur_time;
3338
3339         u32 ability_match_cfg;
3340         int ability_match_count;
3341
3342         char ability_match, idle_match, ack_match;
3343
3344         u32 txconfig, rxconfig;
3345 #define ANEG_CFG_NP             0x00000080
3346 #define ANEG_CFG_ACK            0x00000040
3347 #define ANEG_CFG_RF2            0x00000020
3348 #define ANEG_CFG_RF1            0x00000010
3349 #define ANEG_CFG_PS2            0x00000001
3350 #define ANEG_CFG_PS1            0x00008000
3351 #define ANEG_CFG_HD             0x00004000
3352 #define ANEG_CFG_FD             0x00002000
3353 #define ANEG_CFG_INVAL          0x00001f06
3354
3355 };
3356 #define ANEG_OK         0
3357 #define ANEG_DONE       1
3358 #define ANEG_TIMER_ENAB 2
3359 #define ANEG_FAILED     -1
3360
3361 #define ANEG_STATE_SETTLE_TIME  10000
3362
3363 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3364                                    struct tg3_fiber_aneginfo *ap)
3365 {
3366         u16 flowctrl;
3367         unsigned long delta;
3368         u32 rx_cfg_reg;
3369         int ret;
3370
3371         if (ap->state == ANEG_STATE_UNKNOWN) {
3372                 ap->rxconfig = 0;
3373                 ap->link_time = 0;
3374                 ap->cur_time = 0;
3375                 ap->ability_match_cfg = 0;
3376                 ap->ability_match_count = 0;
3377                 ap->ability_match = 0;
3378                 ap->idle_match = 0;
3379                 ap->ack_match = 0;
3380         }
3381         ap->cur_time++;
3382
3383         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3384                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3385
3386                 if (rx_cfg_reg != ap->ability_match_cfg) {
3387                         ap->ability_match_cfg = rx_cfg_reg;
3388                         ap->ability_match = 0;
3389                         ap->ability_match_count = 0;
3390                 } else {
3391                         if (++ap->ability_match_count > 1) {
3392                                 ap->ability_match = 1;
3393                                 ap->ability_match_cfg = rx_cfg_reg;
3394                         }
3395                 }
3396                 if (rx_cfg_reg & ANEG_CFG_ACK)
3397                         ap->ack_match = 1;
3398                 else
3399                         ap->ack_match = 0;
3400
3401                 ap->idle_match = 0;
3402         } else {
3403                 ap->idle_match = 1;
3404                 ap->ability_match_cfg = 0;
3405                 ap->ability_match_count = 0;
3406                 ap->ability_match = 0;
3407                 ap->ack_match = 0;
3408
3409                 rx_cfg_reg = 0;
3410         }
3411
3412         ap->rxconfig = rx_cfg_reg;
3413         ret = ANEG_OK;
3414
3415         switch(ap->state) {
3416         case ANEG_STATE_UNKNOWN:
3417                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3418                         ap->state = ANEG_STATE_AN_ENABLE;
3419
3420                 /* fallthru */
3421         case ANEG_STATE_AN_ENABLE:
3422                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3423                 if (ap->flags & MR_AN_ENABLE) {
3424                         ap->link_time = 0;
3425                         ap->cur_time = 0;
3426                         ap->ability_match_cfg = 0;
3427                         ap->ability_match_count = 0;
3428                         ap->ability_match = 0;
3429                         ap->idle_match = 0;
3430                         ap->ack_match = 0;
3431
3432                         ap->state = ANEG_STATE_RESTART_INIT;
3433                 } else {
3434                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3435                 }
3436                 break;
3437
3438         case ANEG_STATE_RESTART_INIT:
3439                 ap->link_time = ap->cur_time;
3440                 ap->flags &= ~(MR_NP_LOADED);
3441                 ap->txconfig = 0;
3442                 tw32(MAC_TX_AUTO_NEG, 0);
3443                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3444                 tw32_f(MAC_MODE, tp->mac_mode);
3445                 udelay(40);
3446
3447                 ret = ANEG_TIMER_ENAB;
3448                 ap->state = ANEG_STATE_RESTART;
3449
3450                 /* fallthru */
3451         case ANEG_STATE_RESTART:
3452                 delta = ap->cur_time - ap->link_time;
3453                 if (delta > ANEG_STATE_SETTLE_TIME) {
3454                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3455                 } else {
3456                         ret = ANEG_TIMER_ENAB;
3457                 }
3458                 break;
3459
3460         case ANEG_STATE_DISABLE_LINK_OK:
3461                 ret = ANEG_DONE;
3462                 break;
3463
3464         case ANEG_STATE_ABILITY_DETECT_INIT:
3465                 ap->flags &= ~(MR_TOGGLE_TX);
3466                 ap->txconfig = ANEG_CFG_FD;
3467                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3468                 if (flowctrl & ADVERTISE_1000XPAUSE)
3469                         ap->txconfig |= ANEG_CFG_PS1;
3470                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3471                         ap->txconfig |= ANEG_CFG_PS2;
3472                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3473                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3474                 tw32_f(MAC_MODE, tp->mac_mode);
3475                 udelay(40);
3476
3477                 ap->state = ANEG_STATE_ABILITY_DETECT;
3478                 break;
3479
3480         case ANEG_STATE_ABILITY_DETECT:
3481                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3482                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3483                 }
3484                 break;
3485
3486         case ANEG_STATE_ACK_DETECT_INIT:
3487                 ap->txconfig |= ANEG_CFG_ACK;
3488                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3489                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3490                 tw32_f(MAC_MODE, tp->mac_mode);
3491                 udelay(40);
3492
3493                 ap->state = ANEG_STATE_ACK_DETECT;
3494
3495                 /* fallthru */
3496         case ANEG_STATE_ACK_DETECT:
3497                 if (ap->ack_match != 0) {
3498                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3499                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3500                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3501                         } else {
3502                                 ap->state = ANEG_STATE_AN_ENABLE;
3503                         }
3504                 } else if (ap->ability_match != 0 &&
3505                            ap->rxconfig == 0) {
3506                         ap->state = ANEG_STATE_AN_ENABLE;
3507                 }
3508                 break;
3509
3510         case ANEG_STATE_COMPLETE_ACK_INIT:
3511                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3512                         ret = ANEG_FAILED;
3513                         break;
3514                 }
3515                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3516                                MR_LP_ADV_HALF_DUPLEX |
3517                                MR_LP_ADV_SYM_PAUSE |
3518                                MR_LP_ADV_ASYM_PAUSE |
3519                                MR_LP_ADV_REMOTE_FAULT1 |
3520                                MR_LP_ADV_REMOTE_FAULT2 |
3521                                MR_LP_ADV_NEXT_PAGE |
3522                                MR_TOGGLE_RX |
3523                                MR_NP_RX);
3524                 if (ap->rxconfig & ANEG_CFG_FD)
3525                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3526                 if (ap->rxconfig & ANEG_CFG_HD)
3527                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3528                 if (ap->rxconfig & ANEG_CFG_PS1)
3529                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3530                 if (ap->rxconfig & ANEG_CFG_PS2)
3531                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3532                 if (ap->rxconfig & ANEG_CFG_RF1)
3533                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3534                 if (ap->rxconfig & ANEG_CFG_RF2)
3535                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3536                 if (ap->rxconfig & ANEG_CFG_NP)
3537                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3538
3539                 ap->link_time = ap->cur_time;
3540
3541                 ap->flags ^= (MR_TOGGLE_TX);
3542                 if (ap->rxconfig & 0x0008)
3543                         ap->flags |= MR_TOGGLE_RX;
3544                 if (ap->rxconfig & ANEG_CFG_NP)
3545                         ap->flags |= MR_NP_RX;
3546                 ap->flags |= MR_PAGE_RX;
3547
3548                 ap->state = ANEG_STATE_COMPLETE_ACK;
3549                 ret = ANEG_TIMER_ENAB;
3550                 break;
3551
3552         case ANEG_STATE_COMPLETE_ACK:
3553                 if (ap->ability_match != 0 &&
3554                     ap->rxconfig == 0) {
3555                         ap->state = ANEG_STATE_AN_ENABLE;
3556                         break;
3557                 }
3558                 delta = ap->cur_time - ap->link_time;
3559                 if (delta > ANEG_STATE_SETTLE_TIME) {
3560                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3561                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3562                         } else {
3563                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3564                                     !(ap->flags & MR_NP_RX)) {
3565                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3566                                 } else {
3567                                         ret = ANEG_FAILED;
3568                                 }
3569                         }
3570                 }
3571                 break;
3572
3573         case ANEG_STATE_IDLE_DETECT_INIT:
3574                 ap->link_time = ap->cur_time;
3575                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3576                 tw32_f(MAC_MODE, tp->mac_mode);
3577                 udelay(40);
3578
3579                 ap->state = ANEG_STATE_IDLE_DETECT;
3580                 ret = ANEG_TIMER_ENAB;
3581                 break;
3582
3583         case ANEG_STATE_IDLE_DETECT:
3584                 if (ap->ability_match != 0 &&
3585                     ap->rxconfig == 0) {
3586                         ap->state = ANEG_STATE_AN_ENABLE;
3587                         break;
3588                 }
3589                 delta = ap->cur_time - ap->link_time;
3590                 if (delta > ANEG_STATE_SETTLE_TIME) {
3591                         /* XXX another gem from the Broadcom driver :( */
3592                         ap->state = ANEG_STATE_LINK_OK;
3593                 }
3594                 break;
3595
3596         case ANEG_STATE_LINK_OK:
3597                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3598                 ret = ANEG_DONE;
3599                 break;
3600
3601         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3602                 /* ??? unimplemented */
3603                 break;
3604
3605         case ANEG_STATE_NEXT_PAGE_WAIT:
3606                 /* ??? unimplemented */
3607                 break;
3608
3609         default:
3610                 ret = ANEG_FAILED;
3611                 break;
3612         }
3613
3614         return ret;
3615 }
3616
3617 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3618 {
3619         int res = 0;
3620         struct tg3_fiber_aneginfo aninfo;
3621         int status = ANEG_FAILED;
3622         unsigned int tick;
3623         u32 tmp;
3624
3625         tw32_f(MAC_TX_AUTO_NEG, 0);
3626
3627         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3628         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3629         udelay(40);
3630
3631         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3632         udelay(40);
3633
3634         memset(&aninfo, 0, sizeof(aninfo));
3635         aninfo.flags |= MR_AN_ENABLE;
3636         aninfo.state = ANEG_STATE_UNKNOWN;
3637         aninfo.cur_time = 0;
3638         tick = 0;
3639         while (++tick < 195000) {
3640                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3641                 if (status == ANEG_DONE || status == ANEG_FAILED)
3642                         break;
3643
3644                 udelay(1);
3645         }
3646
3647         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3648         tw32_f(MAC_MODE, tp->mac_mode);
3649         udelay(40);
3650
3651         *txflags = aninfo.txconfig;
3652         *rxflags = aninfo.flags;
3653
3654         if (status == ANEG_DONE &&
3655             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3656                              MR_LP_ADV_FULL_DUPLEX)))
3657                 res = 1;
3658
3659         return res;
3660 }
3661
3662 static void tg3_init_bcm8002(struct tg3 *tp)
3663 {
3664         u32 mac_status = tr32(MAC_STATUS);
3665         int i;
3666
3667         /* Reset when initting first time or we have a link. */
3668         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3669             !(mac_status & MAC_STATUS_PCS_SYNCED))
3670                 return;
3671
3672         /* Set PLL lock range. */
3673         tg3_writephy(tp, 0x16, 0x8007);
3674
3675         /* SW reset */
3676         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3677
3678         /* Wait for reset to complete. */
3679         /* XXX schedule_timeout() ... */
3680         for (i = 0; i < 500; i++)
3681                 udelay(10);
3682
3683         /* Config mode; select PMA/Ch 1 regs. */
3684         tg3_writephy(tp, 0x10, 0x8411);
3685
3686         /* Enable auto-lock and comdet, select txclk for tx. */
3687         tg3_writephy(tp, 0x11, 0x0a10);
3688
3689         tg3_writephy(tp, 0x18, 0x00a0);
3690         tg3_writephy(tp, 0x16, 0x41ff);
3691
3692         /* Assert and deassert POR. */
3693         tg3_writephy(tp, 0x13, 0x0400);
3694         udelay(40);
3695         tg3_writephy(tp, 0x13, 0x0000);
3696
3697         tg3_writephy(tp, 0x11, 0x0a50);
3698         udelay(40);
3699         tg3_writephy(tp, 0x11, 0x0a10);
3700
3701         /* Wait for signal to stabilize */
3702         /* XXX schedule_timeout() ... */
3703         for (i = 0; i < 15000; i++)
3704                 udelay(10);
3705
3706         /* Deselect the channel register so we can read the PHYID
3707          * later.
3708          */
3709         tg3_writephy(tp, 0x10, 0x8011);
3710 }
3711
3712 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3713 {
3714         u16 flowctrl;
3715         u32 sg_dig_ctrl, sg_dig_status;
3716         u32 serdes_cfg, expected_sg_dig_ctrl;
3717         int workaround, port_a;
3718         int current_link_up;
3719
3720         serdes_cfg = 0;
3721         expected_sg_dig_ctrl = 0;
3722         workaround = 0;
3723         port_a = 1;
3724         current_link_up = 0;
3725
3726         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3727             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3728                 workaround = 1;
3729                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3730                         port_a = 0;
3731
3732                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3733                 /* preserve bits 20-23 for voltage regulator */
3734                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3735         }
3736
3737         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3738
3739         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3740                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3741                         if (workaround) {
3742                                 u32 val = serdes_cfg;
3743
3744                                 if (port_a)
3745                                         val |= 0xc010000;
3746                                 else
3747                                         val |= 0x4010000;
3748                                 tw32_f(MAC_SERDES_CFG, val);
3749                         }
3750
3751                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3752                 }
3753                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3754                         tg3_setup_flow_control(tp, 0, 0);
3755                         current_link_up = 1;
3756                 }
3757                 goto out;
3758         }
3759
3760         /* Want auto-negotiation.  */
3761         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3762
3763         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3764         if (flowctrl & ADVERTISE_1000XPAUSE)
3765                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3766         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3767                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3768
3769         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3770                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3771                     tp->serdes_counter &&
3772                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3773                                     MAC_STATUS_RCVD_CFG)) ==
3774                      MAC_STATUS_PCS_SYNCED)) {
3775                         tp->serdes_counter--;
3776                         current_link_up = 1;
3777                         goto out;
3778                 }
3779 restart_autoneg:
3780                 if (workaround)
3781                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3782                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3783                 udelay(5);
3784                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3785
3786                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3787                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3788         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3789                                  MAC_STATUS_SIGNAL_DET)) {
3790                 sg_dig_status = tr32(SG_DIG_STATUS);
3791                 mac_status = tr32(MAC_STATUS);
3792
3793                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3794                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3795                         u32 local_adv = 0, remote_adv = 0;
3796
3797                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3798                                 local_adv |= ADVERTISE_1000XPAUSE;
3799                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3800                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3801
3802                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3803                                 remote_adv |= LPA_1000XPAUSE;
3804                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3805                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3806
3807                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3808                         current_link_up = 1;
3809                         tp->serdes_counter = 0;
3810                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3811                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3812                         if (tp->serdes_counter)
3813                                 tp->serdes_counter--;
3814                         else {
3815                                 if (workaround) {
3816                                         u32 val = serdes_cfg;
3817
3818                                         if (port_a)
3819                                                 val |= 0xc010000;
3820                                         else
3821                                                 val |= 0x4010000;
3822
3823                                         tw32_f(MAC_SERDES_CFG, val);
3824                                 }
3825
3826                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3827                                 udelay(40);
3828
3829                                 /* Link parallel detection - link is up */
3830                                 /* only if we have PCS_SYNC and not */
3831                                 /* receiving config code words */
3832                                 mac_status = tr32(MAC_STATUS);
3833                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3834                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3835                                         tg3_setup_flow_control(tp, 0, 0);
3836                                         current_link_up = 1;
3837                                         tp->tg3_flags2 |=
3838                                                 TG3_FLG2_PARALLEL_DETECT;
3839                                         tp->serdes_counter =
3840                                                 SERDES_PARALLEL_DET_TIMEOUT;
3841                                 } else
3842                                         goto restart_autoneg;
3843                         }
3844                 }
3845         } else {
3846                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3847                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3848         }
3849
3850 out:
3851         return current_link_up;
3852 }
3853
3854 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3855 {
3856         int current_link_up = 0;
3857
3858         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3859                 goto out;
3860
3861         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3862                 u32 txflags, rxflags;
3863                 int i;
3864
3865                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3866                         u32 local_adv = 0, remote_adv = 0;
3867
3868                         if (txflags & ANEG_CFG_PS1)
3869                                 local_adv |= ADVERTISE_1000XPAUSE;
3870                         if (txflags & ANEG_CFG_PS2)
3871                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3872
3873                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3874                                 remote_adv |= LPA_1000XPAUSE;
3875                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3876                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3877
3878                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3879
3880                         current_link_up = 1;
3881                 }
3882                 for (i = 0; i < 30; i++) {
3883                         udelay(20);
3884                         tw32_f(MAC_STATUS,
3885                                (MAC_STATUS_SYNC_CHANGED |
3886                                 MAC_STATUS_CFG_CHANGED));
3887                         udelay(40);
3888                         if ((tr32(MAC_STATUS) &
3889                              (MAC_STATUS_SYNC_CHANGED |
3890                               MAC_STATUS_CFG_CHANGED)) == 0)
3891                                 break;
3892                 }
3893
3894                 mac_status = tr32(MAC_STATUS);
3895                 if (current_link_up == 0 &&
3896                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3897                     !(mac_status & MAC_STATUS_RCVD_CFG))
3898                         current_link_up = 1;
3899         } else {
3900                 tg3_setup_flow_control(tp, 0, 0);
3901
3902                 /* Forcing 1000FD link up. */
3903                 current_link_up = 1;
3904
3905                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3906                 udelay(40);
3907
3908                 tw32_f(MAC_MODE, tp->mac_mode);
3909                 udelay(40);
3910         }
3911
3912 out:
3913         return current_link_up;
3914 }
3915
3916 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3917 {
3918         u32 orig_pause_cfg;
3919         u16 orig_active_speed;
3920         u8 orig_active_duplex;
3921         u32 mac_status;
3922         int current_link_up;
3923         int i;
3924
3925         orig_pause_cfg = tp->link_config.active_flowctrl;
3926         orig_active_speed = tp->link_config.active_speed;
3927         orig_active_duplex = tp->link_config.active_duplex;
3928
3929         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3930             netif_carrier_ok(tp->dev) &&
3931             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3932                 mac_status = tr32(MAC_STATUS);
3933                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3934                                MAC_STATUS_SIGNAL_DET |
3935                                MAC_STATUS_CFG_CHANGED |
3936                                MAC_STATUS_RCVD_CFG);
3937                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3938                                    MAC_STATUS_SIGNAL_DET)) {
3939                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3940                                             MAC_STATUS_CFG_CHANGED));
3941                         return 0;
3942                 }
3943         }
3944
3945         tw32_f(MAC_TX_AUTO_NEG, 0);
3946
3947         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3948         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3949         tw32_f(MAC_MODE, tp->mac_mode);
3950         udelay(40);
3951
3952         if (tp->phy_id == PHY_ID_BCM8002)
3953                 tg3_init_bcm8002(tp);
3954
3955         /* Enable link change event even when serdes polling.  */
3956         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3957         udelay(40);
3958
3959         current_link_up = 0;
3960         mac_status = tr32(MAC_STATUS);
3961
3962         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3963                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3964         else
3965                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3966
3967         tp->napi[0].hw_status->status =
3968                 (SD_STATUS_UPDATED |
3969                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3970
3971         for (i = 0; i < 100; i++) {
3972                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3973                                     MAC_STATUS_CFG_CHANGED));
3974                 udelay(5);
3975                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3976                                          MAC_STATUS_CFG_CHANGED |
3977                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3978                         break;
3979         }
3980
3981         mac_status = tr32(MAC_STATUS);
3982         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3983                 current_link_up = 0;
3984                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3985                     tp->serdes_counter == 0) {
3986                         tw32_f(MAC_MODE, (tp->mac_mode |
3987                                           MAC_MODE_SEND_CONFIGS));
3988                         udelay(1);
3989                         tw32_f(MAC_MODE, tp->mac_mode);
3990                 }
3991         }
3992
3993         if (current_link_up == 1) {
3994                 tp->link_config.active_speed = SPEED_1000;
3995                 tp->link_config.active_duplex = DUPLEX_FULL;
3996                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3997                                     LED_CTRL_LNKLED_OVERRIDE |
3998                                     LED_CTRL_1000MBPS_ON));
3999         } else {
4000                 tp->link_config.active_speed = SPEED_INVALID;
4001                 tp->link_config.active_duplex = DUPLEX_INVALID;
4002                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003                                     LED_CTRL_LNKLED_OVERRIDE |
4004                                     LED_CTRL_TRAFFIC_OVERRIDE));
4005         }
4006
4007         if (current_link_up != netif_carrier_ok(tp->dev)) {
4008                 if (current_link_up)
4009                         netif_carrier_on(tp->dev);
4010                 else
4011                         netif_carrier_off(tp->dev);
4012                 tg3_link_report(tp);
4013         } else {
4014                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4015                 if (orig_pause_cfg != now_pause_cfg ||
4016                     orig_active_speed != tp->link_config.active_speed ||
4017                     orig_active_duplex != tp->link_config.active_duplex)
4018                         tg3_link_report(tp);
4019         }
4020
4021         return 0;
4022 }
4023
4024 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4025 {
4026         int current_link_up, err = 0;
4027         u32 bmsr, bmcr;
4028         u16 current_speed;
4029         u8 current_duplex;
4030         u32 local_adv, remote_adv;
4031
4032         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4033         tw32_f(MAC_MODE, tp->mac_mode);
4034         udelay(40);
4035
4036         tw32(MAC_EVENT, 0);
4037
4038         tw32_f(MAC_STATUS,
4039              (MAC_STATUS_SYNC_CHANGED |
4040               MAC_STATUS_CFG_CHANGED |
4041               MAC_STATUS_MI_COMPLETION |
4042               MAC_STATUS_LNKSTATE_CHANGED));
4043         udelay(40);
4044
4045         if (force_reset)
4046                 tg3_phy_reset(tp);
4047
4048         current_link_up = 0;
4049         current_speed = SPEED_INVALID;
4050         current_duplex = DUPLEX_INVALID;
4051
4052         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4053         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4054         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4055                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4056                         bmsr |= BMSR_LSTATUS;
4057                 else
4058                         bmsr &= ~BMSR_LSTATUS;
4059         }
4060
4061         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4062
4063         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4064             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4065                 /* do nothing, just check for link up at the end */
4066         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4067                 u32 adv, new_adv;
4068
4069                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4070                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4071                                   ADVERTISE_1000XPAUSE |
4072                                   ADVERTISE_1000XPSE_ASYM |
4073                                   ADVERTISE_SLCT);
4074
4075                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4076
4077                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4078                         new_adv |= ADVERTISE_1000XHALF;
4079                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4080                         new_adv |= ADVERTISE_1000XFULL;
4081
4082                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4083                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4084                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4085                         tg3_writephy(tp, MII_BMCR, bmcr);
4086
4087                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4088                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4089                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4090
4091                         return err;
4092                 }
4093         } else {
4094                 u32 new_bmcr;
4095
4096                 bmcr &= ~BMCR_SPEED1000;
4097                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4098
4099                 if (tp->link_config.duplex == DUPLEX_FULL)
4100                         new_bmcr |= BMCR_FULLDPLX;
4101
4102                 if (new_bmcr != bmcr) {
4103                         /* BMCR_SPEED1000 is a reserved bit that needs
4104                          * to be set on write.
4105                          */
4106                         new_bmcr |= BMCR_SPEED1000;
4107
4108                         /* Force a linkdown */
4109                         if (netif_carrier_ok(tp->dev)) {
4110                                 u32 adv;
4111
4112                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4113                                 adv &= ~(ADVERTISE_1000XFULL |
4114                                          ADVERTISE_1000XHALF |
4115                                          ADVERTISE_SLCT);
4116                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4117                                 tg3_writephy(tp, MII_BMCR, bmcr |
4118                                                            BMCR_ANRESTART |
4119                                                            BMCR_ANENABLE);
4120                                 udelay(10);
4121                                 netif_carrier_off(tp->dev);
4122                         }
4123                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4124                         bmcr = new_bmcr;
4125                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4126                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4127                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4128                             ASIC_REV_5714) {
4129                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4130                                         bmsr |= BMSR_LSTATUS;
4131                                 else
4132                                         bmsr &= ~BMSR_LSTATUS;
4133                         }
4134                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4135                 }
4136         }
4137
4138         if (bmsr & BMSR_LSTATUS) {
4139                 current_speed = SPEED_1000;
4140                 current_link_up = 1;
4141                 if (bmcr & BMCR_FULLDPLX)
4142                         current_duplex = DUPLEX_FULL;
4143                 else
4144                         current_duplex = DUPLEX_HALF;
4145
4146                 local_adv = 0;
4147                 remote_adv = 0;
4148
4149                 if (bmcr & BMCR_ANENABLE) {
4150                         u32 common;
4151
4152                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4153                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4154                         common = local_adv & remote_adv;
4155                         if (common & (ADVERTISE_1000XHALF |
4156                                       ADVERTISE_1000XFULL)) {
4157                                 if (common & ADVERTISE_1000XFULL)
4158                                         current_duplex = DUPLEX_FULL;
4159                                 else
4160                                         current_duplex = DUPLEX_HALF;
4161                         }
4162                         else
4163                                 current_link_up = 0;
4164                 }
4165         }
4166
4167         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4168                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4169
4170         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4171         if (tp->link_config.active_duplex == DUPLEX_HALF)
4172                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4173
4174         tw32_f(MAC_MODE, tp->mac_mode);
4175         udelay(40);
4176
4177         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4178
4179         tp->link_config.active_speed = current_speed;
4180         tp->link_config.active_duplex = current_duplex;
4181
4182         if (current_link_up != netif_carrier_ok(tp->dev)) {
4183                 if (current_link_up)
4184                         netif_carrier_on(tp->dev);
4185                 else {
4186                         netif_carrier_off(tp->dev);
4187                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4188                 }
4189                 tg3_link_report(tp);
4190         }
4191         return err;
4192 }
4193
4194 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4195 {
4196         if (tp->serdes_counter) {
4197                 /* Give autoneg time to complete. */
4198                 tp->serdes_counter--;
4199                 return;
4200         }
4201         if (!netif_carrier_ok(tp->dev) &&
4202             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4203                 u32 bmcr;
4204
4205                 tg3_readphy(tp, MII_BMCR, &bmcr);
4206                 if (bmcr & BMCR_ANENABLE) {
4207                         u32 phy1, phy2;
4208
4209                         /* Select shadow register 0x1f */
4210                         tg3_writephy(tp, 0x1c, 0x7c00);
4211                         tg3_readphy(tp, 0x1c, &phy1);
4212
4213                         /* Select expansion interrupt status register */
4214                         tg3_writephy(tp, 0x17, 0x0f01);
4215                         tg3_readphy(tp, 0x15, &phy2);
4216                         tg3_readphy(tp, 0x15, &phy2);
4217
4218                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4219                                 /* We have signal detect and not receiving
4220                                  * config code words, link is up by parallel
4221                                  * detection.
4222                                  */
4223
4224                                 bmcr &= ~BMCR_ANENABLE;
4225                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4226                                 tg3_writephy(tp, MII_BMCR, bmcr);
4227                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4228                         }
4229                 }
4230         }
4231         else if (netif_carrier_ok(tp->dev) &&
4232                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4233                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4234                 u32 phy2;
4235
4236                 /* Select expansion interrupt status register */
4237                 tg3_writephy(tp, 0x17, 0x0f01);
4238                 tg3_readphy(tp, 0x15, &phy2);
4239                 if (phy2 & 0x20) {
4240                         u32 bmcr;
4241
4242                         /* Config code words received, turn on autoneg. */
4243                         tg3_readphy(tp, MII_BMCR, &bmcr);
4244                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4245
4246                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4247
4248                 }
4249         }
4250 }
4251
4252 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4253 {
4254         int err;
4255
4256         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4257                 err = tg3_setup_fiber_phy(tp, force_reset);
4258         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4259                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4260         } else {
4261                 err = tg3_setup_copper_phy(tp, force_reset);
4262         }
4263
4264         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4265                 u32 val, scale;
4266
4267                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4268                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4269                         scale = 65;
4270                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4271                         scale = 6;
4272                 else
4273                         scale = 12;
4274
4275                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4276                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4277                 tw32(GRC_MISC_CFG, val);
4278         }
4279
4280         if (tp->link_config.active_speed == SPEED_1000 &&
4281             tp->link_config.active_duplex == DUPLEX_HALF)
4282                 tw32(MAC_TX_LENGTHS,
4283                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4284                       (6 << TX_LENGTHS_IPG_SHIFT) |
4285                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4286         else
4287                 tw32(MAC_TX_LENGTHS,
4288                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4289                       (6 << TX_LENGTHS_IPG_SHIFT) |
4290                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4291
4292         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4293                 if (netif_carrier_ok(tp->dev)) {
4294                         tw32(HOSTCC_STAT_COAL_TICKS,
4295                              tp->coal.stats_block_coalesce_usecs);
4296                 } else {
4297                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4298                 }
4299         }
4300
4301         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4302                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4303                 if (!netif_carrier_ok(tp->dev))
4304                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4305                               tp->pwrmgmt_thresh;
4306                 else
4307                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4308                 tw32(PCIE_PWR_MGMT_THRESH, val);
4309         }
4310
4311         return err;
4312 }
4313
4314 /* This is called whenever we suspect that the system chipset is re-
4315  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4316  * is bogus tx completions. We try to recover by setting the
4317  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4318  * in the workqueue.
4319  */
4320 static void tg3_tx_recover(struct tg3 *tp)
4321 {
4322         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4323                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4324
4325         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4326                "mapped I/O cycles to the network device, attempting to "
4327                "recover. Please report the problem to the driver maintainer "
4328                "and include system chipset information.\n", tp->dev->name);
4329
4330         spin_lock(&tp->lock);
4331         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4332         spin_unlock(&tp->lock);
4333 }
4334
4335 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4336 {
4337         smp_mb();
4338         return tnapi->tx_pending -
4339                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4340 }
4341
4342 /* Tigon3 never reports partial packet sends.  So we do not
4343  * need special logic to handle SKBs that have not had all
4344  * of their frags sent yet, like SunGEM does.
4345  */
4346 static void tg3_tx(struct tg3_napi *tnapi)
4347 {
4348         struct tg3 *tp = tnapi->tp;
4349         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4350         u32 sw_idx = tnapi->tx_cons;
4351         struct netdev_queue *txq;
4352         int index = tnapi - tp->napi;
4353
4354         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4355                 index--;
4356
4357         txq = netdev_get_tx_queue(tp->dev, index);
4358
4359         while (sw_idx != hw_idx) {
4360                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4361                 struct sk_buff *skb = ri->skb;
4362                 int i, tx_bug = 0;
4363
4364                 if (unlikely(skb == NULL)) {
4365                         tg3_tx_recover(tp);
4366                         return;
4367                 }
4368
4369                 pci_unmap_single(tp->pdev,
4370                                  pci_unmap_addr(ri, mapping),
4371                                  skb_headlen(skb),
4372                                  PCI_DMA_TODEVICE);
4373
4374                 ri->skb = NULL;
4375
4376                 sw_idx = NEXT_TX(sw_idx);
4377
4378                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4379                         ri = &tnapi->tx_buffers[sw_idx];
4380                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4381                                 tx_bug = 1;
4382
4383                         pci_unmap_page(tp->pdev,
4384                                        pci_unmap_addr(ri, mapping),
4385                                        skb_shinfo(skb)->frags[i].size,
4386                                        PCI_DMA_TODEVICE);
4387                         sw_idx = NEXT_TX(sw_idx);
4388                 }
4389
4390                 dev_kfree_skb(skb);
4391
4392                 if (unlikely(tx_bug)) {
4393                         tg3_tx_recover(tp);
4394                         return;
4395                 }
4396         }
4397
4398         tnapi->tx_cons = sw_idx;
4399
4400         /* Need to make the tx_cons update visible to tg3_start_xmit()
4401          * before checking for netif_queue_stopped().  Without the
4402          * memory barrier, there is a small possibility that tg3_start_xmit()
4403          * will miss it and cause the queue to be stopped forever.
4404          */
4405         smp_mb();
4406
4407         if (unlikely(netif_tx_queue_stopped(txq) &&
4408                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4409                 __netif_tx_lock(txq, smp_processor_id());
4410                 if (netif_tx_queue_stopped(txq) &&
4411                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4412                         netif_tx_wake_queue(txq);
4413                 __netif_tx_unlock(txq);
4414         }
4415 }
4416
4417 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4418 {
4419         if (!ri->skb)
4420                 return;
4421
4422         pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4423                          map_sz, PCI_DMA_FROMDEVICE);
4424         dev_kfree_skb_any(ri->skb);
4425         ri->skb = NULL;
4426 }
4427
4428 /* Returns size of skb allocated or < 0 on error.
4429  *
4430  * We only need to fill in the address because the other members
4431  * of the RX descriptor are invariant, see tg3_init_rings.
4432  *
4433  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4434  * posting buffers we only dirty the first cache line of the RX
4435  * descriptor (containing the address).  Whereas for the RX status
4436  * buffers the cpu only reads the last cacheline of the RX descriptor
4437  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4438  */
4439 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4440                             u32 opaque_key, u32 dest_idx_unmasked)
4441 {
4442         struct tg3_rx_buffer_desc *desc;
4443         struct ring_info *map, *src_map;
4444         struct sk_buff *skb;
4445         dma_addr_t mapping;
4446         int skb_size, dest_idx;
4447
4448         src_map = NULL;
4449         switch (opaque_key) {
4450         case RXD_OPAQUE_RING_STD:
4451                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4452                 desc = &tpr->rx_std[dest_idx];
4453                 map = &tpr->rx_std_buffers[dest_idx];
4454                 skb_size = tp->rx_pkt_map_sz;
4455                 break;
4456
4457         case RXD_OPAQUE_RING_JUMBO:
4458                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4459                 desc = &tpr->rx_jmb[dest_idx].std;
4460                 map = &tpr->rx_jmb_buffers[dest_idx];
4461                 skb_size = TG3_RX_JMB_MAP_SZ;
4462                 break;
4463
4464         default:
4465                 return -EINVAL;
4466         }
4467
4468         /* Do not overwrite any of the map or rp information
4469          * until we are sure we can commit to a new buffer.
4470          *
4471          * Callers depend upon this behavior and assume that
4472          * we leave everything unchanged if we fail.
4473          */
4474         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4475         if (skb == NULL)
4476                 return -ENOMEM;
4477
4478         skb_reserve(skb, tp->rx_offset);
4479
4480         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4481                                  PCI_DMA_FROMDEVICE);
4482         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4483                 dev_kfree_skb(skb);
4484                 return -EIO;
4485         }
4486
4487         map->skb = skb;
4488         pci_unmap_addr_set(map, mapping, mapping);
4489
4490         desc->addr_hi = ((u64)mapping >> 32);
4491         desc->addr_lo = ((u64)mapping & 0xffffffff);
4492
4493         return skb_size;
4494 }
4495
4496 /* We only need to move over in the address because the other
4497  * members of the RX descriptor are invariant.  See notes above
4498  * tg3_alloc_rx_skb for full details.
4499  */
4500 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4501                            struct tg3_rx_prodring_set *dpr,
4502                            u32 opaque_key, int src_idx,
4503                            u32 dest_idx_unmasked)
4504 {
4505         struct tg3 *tp = tnapi->tp;
4506         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4507         struct ring_info *src_map, *dest_map;
4508         int dest_idx;
4509         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4510
4511         switch (opaque_key) {
4512         case RXD_OPAQUE_RING_STD:
4513                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4514                 dest_desc = &dpr->rx_std[dest_idx];
4515                 dest_map = &dpr->rx_std_buffers[dest_idx];
4516                 src_desc = &spr->rx_std[src_idx];
4517                 src_map = &spr->rx_std_buffers[src_idx];
4518                 break;
4519
4520         case RXD_OPAQUE_RING_JUMBO:
4521                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4522                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4523                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4524                 src_desc = &spr->rx_jmb[src_idx].std;
4525                 src_map = &spr->rx_jmb_buffers[src_idx];
4526                 break;
4527
4528         default:
4529                 return;
4530         }
4531
4532         dest_map->skb = src_map->skb;
4533         pci_unmap_addr_set(dest_map, mapping,
4534                            pci_unmap_addr(src_map, mapping));
4535         dest_desc->addr_hi = src_desc->addr_hi;
4536         dest_desc->addr_lo = src_desc->addr_lo;
4537         src_map->skb = NULL;
4538 }
4539
4540 /* The RX ring scheme is composed of multiple rings which post fresh
4541  * buffers to the chip, and one special ring the chip uses to report
4542  * status back to the host.
4543  *
4544  * The special ring reports the status of received packets to the
4545  * host.  The chip does not write into the original descriptor the
4546  * RX buffer was obtained from.  The chip simply takes the original
4547  * descriptor as provided by the host, updates the status and length
4548  * field, then writes this into the next status ring entry.
4549  *
4550  * Each ring the host uses to post buffers to the chip is described
4551  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4552  * it is first placed into the on-chip ram.  When the packet's length
4553  * is known, it walks down the TG3_BDINFO entries to select the ring.
4554  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4555  * which is within the range of the new packet's length is chosen.
4556  *
4557  * The "separate ring for rx status" scheme may sound queer, but it makes
4558  * sense from a cache coherency perspective.  If only the host writes
4559  * to the buffer post rings, and only the chip writes to the rx status
4560  * rings, then cache lines never move beyond shared-modified state.
4561  * If both the host and chip were to write into the same ring, cache line
4562  * eviction could occur since both entities want it in an exclusive state.
4563  */
4564 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4565 {
4566         struct tg3 *tp = tnapi->tp;
4567         u32 work_mask, rx_std_posted = 0;
4568         u32 std_prod_idx, jmb_prod_idx;
4569         u32 sw_idx = tnapi->rx_rcb_ptr;
4570         u16 hw_idx;
4571         int received;
4572         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4573
4574         hw_idx = *(tnapi->rx_rcb_prod_idx);
4575         /*
4576          * We need to order the read of hw_idx and the read of
4577          * the opaque cookie.
4578          */
4579         rmb();
4580         work_mask = 0;
4581         received = 0;
4582         std_prod_idx = tpr->rx_std_prod_idx;
4583         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4584         while (sw_idx != hw_idx && budget > 0) {
4585                 struct ring_info *ri;
4586                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4587                 unsigned int len;
4588                 struct sk_buff *skb;
4589                 dma_addr_t dma_addr;
4590                 u32 opaque_key, desc_idx, *post_ptr;
4591
4592                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4593                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4594                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4595                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4596                         dma_addr = pci_unmap_addr(ri, mapping);
4597                         skb = ri->skb;
4598                         post_ptr = &std_prod_idx;
4599                         rx_std_posted++;
4600                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4601                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4602                         dma_addr = pci_unmap_addr(ri, mapping);
4603                         skb = ri->skb;
4604                         post_ptr = &jmb_prod_idx;
4605                 } else
4606                         goto next_pkt_nopost;
4607
4608                 work_mask |= opaque_key;
4609
4610                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4611                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4612                 drop_it:
4613                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4614                                        desc_idx, *post_ptr);
4615                 drop_it_no_recycle:
4616                         /* Other statistics kept track of by card. */
4617                         tp->net_stats.rx_dropped++;
4618                         goto next_pkt;
4619                 }
4620
4621                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4622                       ETH_FCS_LEN;
4623
4624                 if (len > RX_COPY_THRESHOLD &&
4625                     tp->rx_offset == NET_IP_ALIGN) {
4626                     /* rx_offset will likely not equal NET_IP_ALIGN
4627                      * if this is a 5701 card running in PCI-X mode
4628                      * [see tg3_get_invariants()]
4629                      */
4630                         int skb_size;
4631
4632                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4633                                                     *post_ptr);
4634                         if (skb_size < 0)
4635                                 goto drop_it;
4636
4637                         ri->skb = NULL;
4638
4639                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4640                                          PCI_DMA_FROMDEVICE);
4641
4642                         skb_put(skb, len);
4643                 } else {
4644                         struct sk_buff *copy_skb;
4645
4646                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4647                                        desc_idx, *post_ptr);
4648
4649                         copy_skb = netdev_alloc_skb(tp->dev,
4650                                                     len + TG3_RAW_IP_ALIGN);
4651                         if (copy_skb == NULL)
4652                                 goto drop_it_no_recycle;
4653
4654                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4655                         skb_put(copy_skb, len);
4656                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4657                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4658                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4659
4660                         /* We'll reuse the original ring buffer. */
4661                         skb = copy_skb;
4662                 }
4663
4664                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4665                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4666                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4667                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4668                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4669                 else
4670                         skb->ip_summed = CHECKSUM_NONE;
4671
4672                 skb->protocol = eth_type_trans(skb, tp->dev);
4673
4674                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4675                     skb->protocol != htons(ETH_P_8021Q)) {
4676                         dev_kfree_skb(skb);
4677                         goto next_pkt;
4678                 }
4679
4680 #if TG3_VLAN_TAG_USED
4681                 if (tp->vlgrp != NULL &&
4682                     desc->type_flags & RXD_FLAG_VLAN) {
4683                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4684                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4685                 } else
4686 #endif
4687                         napi_gro_receive(&tnapi->napi, skb);
4688
4689                 received++;
4690                 budget--;
4691
4692 next_pkt:
4693                 (*post_ptr)++;
4694
4695                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4696                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4697                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
4698                         work_mask &= ~RXD_OPAQUE_RING_STD;
4699                         rx_std_posted = 0;
4700                 }
4701 next_pkt_nopost:
4702                 sw_idx++;
4703                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4704
4705                 /* Refresh hw_idx to see if there is new work */
4706                 if (sw_idx == hw_idx) {
4707                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4708                         rmb();
4709                 }
4710         }
4711
4712         /* ACK the status ring. */
4713         tnapi->rx_rcb_ptr = sw_idx;
4714         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4715
4716         /* Refill RX ring(s). */
4717         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4718                 if (work_mask & RXD_OPAQUE_RING_STD) {
4719                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4720                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4721                                      tpr->rx_std_prod_idx);
4722                 }
4723                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4724                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4725                                                TG3_RX_JUMBO_RING_SIZE;
4726                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4727                                      tpr->rx_jmb_prod_idx);
4728                 }
4729                 mmiowb();
4730         } else if (work_mask) {
4731                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4732                  * updated before the producer indices can be updated.
4733                  */
4734                 smp_wmb();
4735
4736                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4737                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4738
4739                 napi_schedule(&tp->napi[1].napi);
4740         }
4741
4742         return received;
4743 }
4744
4745 static void tg3_poll_link(struct tg3 *tp)
4746 {
4747         /* handle link change and other phy events */
4748         if (!(tp->tg3_flags &
4749               (TG3_FLAG_USE_LINKCHG_REG |
4750                TG3_FLAG_POLL_SERDES))) {
4751                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4752
4753                 if (sblk->status & SD_STATUS_LINK_CHG) {
4754                         sblk->status = SD_STATUS_UPDATED |
4755                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4756                         spin_lock(&tp->lock);
4757                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4758                                 tw32_f(MAC_STATUS,
4759                                      (MAC_STATUS_SYNC_CHANGED |
4760                                       MAC_STATUS_CFG_CHANGED |
4761                                       MAC_STATUS_MI_COMPLETION |
4762                                       MAC_STATUS_LNKSTATE_CHANGED));
4763                                 udelay(40);
4764                         } else
4765                                 tg3_setup_phy(tp, 0);
4766                         spin_unlock(&tp->lock);
4767                 }
4768         }
4769 }
4770
4771 static void tg3_rx_prodring_xfer(struct tg3 *tp,
4772                                  struct tg3_rx_prodring_set *dpr,
4773                                  struct tg3_rx_prodring_set *spr)
4774 {
4775         u32 si, di, cpycnt, src_prod_idx;
4776         int i;
4777
4778         while (1) {
4779                 src_prod_idx = spr->rx_std_prod_idx;
4780
4781                 /* Make sure updates to the rx_std_buffers[] entries and the
4782                  * standard producer index are seen in the correct order.
4783                  */
4784                 smp_rmb();
4785
4786                 if (spr->rx_std_cons_idx == src_prod_idx)
4787                         break;
4788
4789                 if (spr->rx_std_cons_idx < src_prod_idx)
4790                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4791                 else
4792                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4793
4794                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4795
4796                 si = spr->rx_std_cons_idx;
4797                 di = dpr->rx_std_prod_idx;
4798
4799                 memcpy(&dpr->rx_std_buffers[di],
4800                        &spr->rx_std_buffers[si],
4801                        cpycnt * sizeof(struct ring_info));
4802
4803                 for (i = 0; i < cpycnt; i++, di++, si++) {
4804                         struct tg3_rx_buffer_desc *sbd, *dbd;
4805                         sbd = &spr->rx_std[si];
4806                         dbd = &dpr->rx_std[di];
4807                         dbd->addr_hi = sbd->addr_hi;
4808                         dbd->addr_lo = sbd->addr_lo;
4809                 }
4810
4811                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4812                                        TG3_RX_RING_SIZE;
4813                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4814                                        TG3_RX_RING_SIZE;
4815         }
4816
4817         while (1) {
4818                 src_prod_idx = spr->rx_jmb_prod_idx;
4819
4820                 /* Make sure updates to the rx_jmb_buffers[] entries and
4821                  * the jumbo producer index are seen in the correct order.
4822                  */
4823                 smp_rmb();
4824
4825                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4826                         break;
4827
4828                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4829                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4830                 else
4831                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4832
4833                 cpycnt = min(cpycnt,
4834                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4835
4836                 si = spr->rx_jmb_cons_idx;
4837                 di = dpr->rx_jmb_prod_idx;
4838
4839                 memcpy(&dpr->rx_jmb_buffers[di],
4840                        &spr->rx_jmb_buffers[si],
4841                        cpycnt * sizeof(struct ring_info));
4842
4843                 for (i = 0; i < cpycnt; i++, di++, si++) {
4844                         struct tg3_rx_buffer_desc *sbd, *dbd;
4845                         sbd = &spr->rx_jmb[si].std;
4846                         dbd = &dpr->rx_jmb[di].std;
4847                         dbd->addr_hi = sbd->addr_hi;
4848                         dbd->addr_lo = sbd->addr_lo;
4849                 }
4850
4851                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4852                                        TG3_RX_JUMBO_RING_SIZE;
4853                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4854                                        TG3_RX_JUMBO_RING_SIZE;
4855         }
4856 }
4857
4858 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4859 {
4860         struct tg3 *tp = tnapi->tp;
4861
4862         /* run TX completion thread */
4863         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4864                 tg3_tx(tnapi);
4865                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4866                         return work_done;
4867         }
4868
4869         /* run RX thread, within the bounds set by NAPI.
4870          * All RX "locking" is done by ensuring outside
4871          * code synchronizes with tg3->napi.poll()
4872          */
4873         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4874                 work_done += tg3_rx(tnapi, budget - work_done);
4875
4876         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4877                 int i;
4878                 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4879                 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4880
4881                 for (i = 2; i < tp->irq_cnt; i++)
4882                         tg3_rx_prodring_xfer(tp, tnapi->prodring,
4883                                              tp->napi[i].prodring);
4884
4885                 wmb();
4886
4887                 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4888                         u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4889                         tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4890                 }
4891
4892                 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4893                         u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4894                         tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4895                 }
4896
4897                 mmiowb();
4898         }
4899
4900         return work_done;
4901 }
4902
4903 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4904 {
4905         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4906         struct tg3 *tp = tnapi->tp;
4907         int work_done = 0;
4908         struct tg3_hw_status *sblk = tnapi->hw_status;
4909
4910         while (1) {
4911                 work_done = tg3_poll_work(tnapi, work_done, budget);
4912
4913                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4914                         goto tx_recovery;
4915
4916                 if (unlikely(work_done >= budget))
4917                         break;
4918
4919                 /* tp->last_tag is used in tg3_restart_ints() below
4920                  * to tell the hw how much work has been processed,
4921                  * so we must read it before checking for more work.
4922                  */
4923                 tnapi->last_tag = sblk->status_tag;
4924                 tnapi->last_irq_tag = tnapi->last_tag;
4925                 rmb();
4926
4927                 /* check for RX/TX work to do */
4928                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4929                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4930                         napi_complete(napi);
4931                         /* Reenable interrupts. */
4932                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4933                         mmiowb();
4934                         break;
4935                 }
4936         }
4937
4938         return work_done;
4939
4940 tx_recovery:
4941         /* work_done is guaranteed to be less than budget. */
4942         napi_complete(napi);
4943         schedule_work(&tp->reset_task);
4944         return work_done;
4945 }
4946
4947 static int tg3_poll(struct napi_struct *napi, int budget)
4948 {
4949         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4950         struct tg3 *tp = tnapi->tp;
4951         int work_done = 0;
4952         struct tg3_hw_status *sblk = tnapi->hw_status;
4953
4954         while (1) {
4955                 tg3_poll_link(tp);
4956
4957                 work_done = tg3_poll_work(tnapi, work_done, budget);
4958
4959                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4960                         goto tx_recovery;
4961
4962                 if (unlikely(work_done >= budget))
4963                         break;
4964
4965                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4966                         /* tp->last_tag is used in tg3_int_reenable() below
4967                          * to tell the hw how much work has been processed,
4968                          * so we must read it before checking for more work.
4969                          */
4970                         tnapi->last_tag = sblk->status_tag;
4971                         tnapi->last_irq_tag = tnapi->last_tag;
4972                         rmb();
4973                 } else
4974                         sblk->status &= ~SD_STATUS_UPDATED;
4975
4976                 if (likely(!tg3_has_work(tnapi))) {
4977                         napi_complete(napi);
4978                         tg3_int_reenable(tnapi);
4979                         break;
4980                 }
4981         }
4982
4983         return work_done;
4984
4985 tx_recovery:
4986         /* work_done is guaranteed to be less than budget. */
4987         napi_complete(napi);
4988         schedule_work(&tp->reset_task);
4989         return work_done;
4990 }
4991
4992 static void tg3_irq_quiesce(struct tg3 *tp)
4993 {
4994         int i;
4995
4996         BUG_ON(tp->irq_sync);
4997
4998         tp->irq_sync = 1;
4999         smp_mb();
5000
5001         for (i = 0; i < tp->irq_cnt; i++)
5002                 synchronize_irq(tp->napi[i].irq_vec);
5003 }
5004
5005 static inline int tg3_irq_sync(struct tg3 *tp)
5006 {
5007         return tp->irq_sync;
5008 }
5009
5010 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5011  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5012  * with as well.  Most of the time, this is not necessary except when
5013  * shutting down the device.
5014  */
5015 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5016 {
5017         spin_lock_bh(&tp->lock);
5018         if (irq_sync)
5019                 tg3_irq_quiesce(tp);
5020 }
5021
5022 static inline void tg3_full_unlock(struct tg3 *tp)
5023 {
5024         spin_unlock_bh(&tp->lock);
5025 }
5026
5027 /* One-shot MSI handler - Chip automatically disables interrupt
5028  * after sending MSI so driver doesn't have to do it.
5029  */
5030 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5031 {
5032         struct tg3_napi *tnapi = dev_id;
5033         struct tg3 *tp = tnapi->tp;
5034
5035         prefetch(tnapi->hw_status);
5036         if (tnapi->rx_rcb)
5037                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5038
5039         if (likely(!tg3_irq_sync(tp)))
5040                 napi_schedule(&tnapi->napi);
5041
5042         return IRQ_HANDLED;
5043 }
5044
5045 /* MSI ISR - No need to check for interrupt sharing and no need to
5046  * flush status block and interrupt mailbox. PCI ordering rules
5047  * guarantee that MSI will arrive after the status block.
5048  */
5049 static irqreturn_t tg3_msi(int irq, void *dev_id)
5050 {
5051         struct tg3_napi *tnapi = dev_id;
5052         struct tg3 *tp = tnapi->tp;
5053
5054         prefetch(tnapi->hw_status);
5055         if (tnapi->rx_rcb)
5056                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5057         /*
5058          * Writing any value to intr-mbox-0 clears PCI INTA# and
5059          * chip-internal interrupt pending events.
5060          * Writing non-zero to intr-mbox-0 additional tells the
5061          * NIC to stop sending us irqs, engaging "in-intr-handler"
5062          * event coalescing.
5063          */
5064         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5065         if (likely(!tg3_irq_sync(tp)))
5066                 napi_schedule(&tnapi->napi);
5067
5068         return IRQ_RETVAL(1);
5069 }
5070
5071 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5072 {
5073         struct tg3_napi *tnapi = dev_id;
5074         struct tg3 *tp = tnapi->tp;
5075         struct tg3_hw_status *sblk = tnapi->hw_status;
5076         unsigned int handled = 1;
5077
5078         /* In INTx mode, it is possible for the interrupt to arrive at
5079          * the CPU before the status block posted prior to the interrupt.
5080          * Reading the PCI State register will confirm whether the
5081          * interrupt is ours and will flush the status block.
5082          */
5083         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5084                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5085                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5086                         handled = 0;
5087                         goto out;
5088                 }
5089         }
5090
5091         /*
5092          * Writing any value to intr-mbox-0 clears PCI INTA# and
5093          * chip-internal interrupt pending events.
5094          * Writing non-zero to intr-mbox-0 additional tells the
5095          * NIC to stop sending us irqs, engaging "in-intr-handler"
5096          * event coalescing.
5097          *
5098          * Flush the mailbox to de-assert the IRQ immediately to prevent
5099          * spurious interrupts.  The flush impacts performance but
5100          * excessive spurious interrupts can be worse in some cases.
5101          */
5102         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5103         if (tg3_irq_sync(tp))
5104                 goto out;
5105         sblk->status &= ~SD_STATUS_UPDATED;
5106         if (likely(tg3_has_work(tnapi))) {
5107                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5108                 napi_schedule(&tnapi->napi);
5109         } else {
5110                 /* No work, shared interrupt perhaps?  re-enable
5111                  * interrupts, and flush that PCI write
5112                  */
5113                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5114                                0x00000000);
5115         }
5116 out:
5117         return IRQ_RETVAL(handled);
5118 }
5119
5120 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5121 {
5122         struct tg3_napi *tnapi = dev_id;
5123         struct tg3 *tp = tnapi->tp;
5124         struct tg3_hw_status *sblk = tnapi->hw_status;
5125         unsigned int handled = 1;
5126
5127         /* In INTx mode, it is possible for the interrupt to arrive at
5128          * the CPU before the status block posted prior to the interrupt.
5129          * Reading the PCI State register will confirm whether the
5130          * interrupt is ours and will flush the status block.
5131          */
5132         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5133                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5134                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5135                         handled = 0;
5136                         goto out;
5137                 }
5138         }
5139
5140         /*
5141          * writing any value to intr-mbox-0 clears PCI INTA# and
5142          * chip-internal interrupt pending events.
5143          * writing non-zero to intr-mbox-0 additional tells the
5144          * NIC to stop sending us irqs, engaging "in-intr-handler"
5145          * event coalescing.
5146          *
5147          * Flush the mailbox to de-assert the IRQ immediately to prevent
5148          * spurious interrupts.  The flush impacts performance but
5149          * excessive spurious interrupts can be worse in some cases.
5150          */
5151         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5152
5153         /*
5154          * In a shared interrupt configuration, sometimes other devices'
5155          * interrupts will scream.  We record the current status tag here
5156          * so that the above check can report that the screaming interrupts
5157          * are unhandled.  Eventually they will be silenced.
5158          */
5159         tnapi->last_irq_tag = sblk->status_tag;
5160
5161         if (tg3_irq_sync(tp))
5162                 goto out;
5163
5164         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5165
5166         napi_schedule(&tnapi->napi);
5167
5168 out:
5169         return IRQ_RETVAL(handled);
5170 }
5171
5172 /* ISR for interrupt test */
5173 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5174 {
5175         struct tg3_napi *tnapi = dev_id;
5176         struct tg3 *tp = tnapi->tp;
5177         struct tg3_hw_status *sblk = tnapi->hw_status;
5178
5179         if ((sblk->status & SD_STATUS_UPDATED) ||
5180             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5181                 tg3_disable_ints(tp);
5182                 return IRQ_RETVAL(1);
5183         }
5184         return IRQ_RETVAL(0);
5185 }
5186
5187 static int tg3_init_hw(struct tg3 *, int);
5188 static int tg3_halt(struct tg3 *, int, int);
5189
5190 /* Restart hardware after configuration changes, self-test, etc.
5191  * Invoked with tp->lock held.
5192  */
5193 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5194         __releases(tp->lock)
5195         __acquires(tp->lock)
5196 {
5197         int err;
5198
5199         err = tg3_init_hw(tp, reset_phy);
5200         if (err) {
5201                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5202                        "aborting.\n", tp->dev->name);
5203                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5204                 tg3_full_unlock(tp);
5205                 del_timer_sync(&tp->timer);
5206                 tp->irq_sync = 0;
5207                 tg3_napi_enable(tp);
5208                 dev_close(tp->dev);
5209                 tg3_full_lock(tp, 0);
5210         }
5211         return err;
5212 }
5213
5214 #ifdef CONFIG_NET_POLL_CONTROLLER
5215 static void tg3_poll_controller(struct net_device *dev)
5216 {
5217         int i;
5218         struct tg3 *tp = netdev_priv(dev);
5219
5220         for (i = 0; i < tp->irq_cnt; i++)
5221                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5222 }
5223 #endif
5224
5225 static void tg3_reset_task(struct work_struct *work)
5226 {
5227         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5228         int err;
5229         unsigned int restart_timer;
5230
5231         tg3_full_lock(tp, 0);
5232
5233         if (!netif_running(tp->dev)) {
5234                 tg3_full_unlock(tp);
5235                 return;
5236         }
5237
5238         tg3_full_unlock(tp);
5239
5240         tg3_phy_stop(tp);
5241
5242         tg3_netif_stop(tp);
5243
5244         tg3_full_lock(tp, 1);
5245
5246         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5247         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5248
5249         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5250                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5251                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5252                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5253                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5254         }
5255
5256         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5257         err = tg3_init_hw(tp, 1);
5258         if (err)
5259                 goto out;
5260
5261         tg3_netif_start(tp);
5262
5263         if (restart_timer)
5264                 mod_timer(&tp->timer, jiffies + 1);
5265
5266 out:
5267         tg3_full_unlock(tp);
5268
5269         if (!err)
5270                 tg3_phy_start(tp);
5271 }
5272
5273 static void tg3_dump_short_state(struct tg3 *tp)
5274 {
5275         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5276                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5277         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5278                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5279 }
5280
5281 static void tg3_tx_timeout(struct net_device *dev)
5282 {
5283         struct tg3 *tp = netdev_priv(dev);
5284
5285         if (netif_msg_tx_err(tp)) {
5286                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5287                        dev->name);
5288                 tg3_dump_short_state(tp);
5289         }
5290
5291         schedule_work(&tp->reset_task);
5292 }
5293
5294 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5295 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5296 {
5297         u32 base = (u32) mapping & 0xffffffff;
5298
5299         return ((base > 0xffffdcc0) &&
5300                 (base + len + 8 < base));
5301 }
5302
5303 /* Test for DMA addresses > 40-bit */
5304 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5305                                           int len)
5306 {
5307 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5308         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5309                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5310         return 0;
5311 #else
5312         return 0;
5313 #endif
5314 }
5315
5316 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5317
5318 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5319 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5320                                        struct sk_buff *skb, u32 last_plus_one,
5321                                        u32 *start, u32 base_flags, u32 mss)
5322 {
5323         struct tg3 *tp = tnapi->tp;
5324         struct sk_buff *new_skb;
5325         dma_addr_t new_addr = 0;
5326         u32 entry = *start;
5327         int i, ret = 0;
5328
5329         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5330                 new_skb = skb_copy(skb, GFP_ATOMIC);
5331         else {
5332                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5333
5334                 new_skb = skb_copy_expand(skb,
5335                                           skb_headroom(skb) + more_headroom,
5336                                           skb_tailroom(skb), GFP_ATOMIC);
5337         }
5338
5339         if (!new_skb) {
5340                 ret = -1;
5341         } else {
5342                 /* New SKB is guaranteed to be linear. */
5343                 entry = *start;
5344                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5345                                           PCI_DMA_TODEVICE);
5346                 /* Make sure the mapping succeeded */
5347                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5348                         ret = -1;
5349                         dev_kfree_skb(new_skb);
5350                         new_skb = NULL;
5351
5352                 /* Make sure new skb does not cross any 4G boundaries.
5353                  * Drop the packet if it does.
5354                  */
5355                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5356                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5357                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5358                                          PCI_DMA_TODEVICE);
5359                         ret = -1;
5360                         dev_kfree_skb(new_skb);
5361                         new_skb = NULL;
5362                 } else {
5363                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5364                                     base_flags, 1 | (mss << 1));
5365                         *start = NEXT_TX(entry);
5366                 }
5367         }
5368
5369         /* Now clean up the sw ring entries. */
5370         i = 0;
5371         while (entry != last_plus_one) {
5372                 int len;
5373
5374                 if (i == 0)
5375                         len = skb_headlen(skb);
5376                 else
5377                         len = skb_shinfo(skb)->frags[i-1].size;
5378
5379                 pci_unmap_single(tp->pdev,
5380                                  pci_unmap_addr(&tnapi->tx_buffers[entry],
5381                                                 mapping),
5382                                  len, PCI_DMA_TODEVICE);
5383                 if (i == 0) {
5384                         tnapi->tx_buffers[entry].skb = new_skb;
5385                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5386                                            new_addr);
5387                 } else {
5388                         tnapi->tx_buffers[entry].skb = NULL;
5389                 }
5390                 entry = NEXT_TX(entry);
5391                 i++;
5392         }
5393
5394         dev_kfree_skb(skb);
5395
5396         return ret;
5397 }
5398
5399 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5400                         dma_addr_t mapping, int len, u32 flags,
5401                         u32 mss_and_is_end)
5402 {
5403         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5404         int is_end = (mss_and_is_end & 0x1);
5405         u32 mss = (mss_and_is_end >> 1);
5406         u32 vlan_tag = 0;
5407
5408         if (is_end)
5409                 flags |= TXD_FLAG_END;
5410         if (flags & TXD_FLAG_VLAN) {
5411                 vlan_tag = flags >> 16;
5412                 flags &= 0xffff;
5413         }
5414         vlan_tag |= (mss << TXD_MSS_SHIFT);
5415
5416         txd->addr_hi = ((u64) mapping >> 32);
5417         txd->addr_lo = ((u64) mapping & 0xffffffff);
5418         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5419         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5420 }
5421
5422 /* hard_start_xmit for devices that don't have any bugs and
5423  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5424  */
5425 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5426                                   struct net_device *dev)
5427 {
5428         struct tg3 *tp = netdev_priv(dev);
5429         u32 len, entry, base_flags, mss;
5430         dma_addr_t mapping;
5431         struct tg3_napi *tnapi;
5432         struct netdev_queue *txq;
5433         unsigned int i, last;
5434
5435
5436         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5437         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5438         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5439                 tnapi++;
5440
5441         /* We are running in BH disabled context with netif_tx_lock
5442          * and TX reclaim runs via tp->napi.poll inside of a software
5443          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5444          * no IRQ context deadlocks to worry about either.  Rejoice!
5445          */
5446         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5447                 if (!netif_tx_queue_stopped(txq)) {
5448                         netif_tx_stop_queue(txq);
5449
5450                         /* This is a hard error, log it. */
5451                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5452                                "queue awake!\n", dev->name);
5453                 }
5454                 return NETDEV_TX_BUSY;
5455         }
5456
5457         entry = tnapi->tx_prod;
5458         base_flags = 0;
5459         mss = 0;
5460         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5461                 int tcp_opt_len, ip_tcp_len;
5462                 u32 hdrlen;
5463
5464                 if (skb_header_cloned(skb) &&
5465                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5466                         dev_kfree_skb(skb);
5467                         goto out_unlock;
5468                 }
5469
5470                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5471                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5472                 else {
5473                         struct iphdr *iph = ip_hdr(skb);
5474
5475                         tcp_opt_len = tcp_optlen(skb);
5476                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5477
5478                         iph->check = 0;
5479                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5480                         hdrlen = ip_tcp_len + tcp_opt_len;
5481                 }
5482
5483                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5484                         mss |= (hdrlen & 0xc) << 12;
5485                         if (hdrlen & 0x10)
5486                                 base_flags |= 0x00000010;
5487                         base_flags |= (hdrlen & 0x3e0) << 5;
5488                 } else
5489                         mss |= hdrlen << 9;
5490
5491                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5492                                TXD_FLAG_CPU_POST_DMA);
5493
5494                 tcp_hdr(skb)->check = 0;
5495
5496         }
5497         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5498                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5499 #if TG3_VLAN_TAG_USED
5500         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5501                 base_flags |= (TXD_FLAG_VLAN |
5502                                (vlan_tx_tag_get(skb) << 16));
5503 #endif
5504
5505         len = skb_headlen(skb);
5506
5507         /* Queue skb data, a.k.a. the main skb fragment. */
5508         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5509         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5510                 dev_kfree_skb(skb);
5511                 goto out_unlock;
5512         }
5513
5514         tnapi->tx_buffers[entry].skb = skb;
5515         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5516
5517         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5518             !mss && skb->len > ETH_DATA_LEN)
5519                 base_flags |= TXD_FLAG_JMB_PKT;
5520
5521         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5522                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5523
5524         entry = NEXT_TX(entry);
5525
5526         /* Now loop through additional data fragments, and queue them. */
5527         if (skb_shinfo(skb)->nr_frags > 0) {
5528                 last = skb_shinfo(skb)->nr_frags - 1;
5529                 for (i = 0; i <= last; i++) {
5530                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5531
5532                         len = frag->size;
5533                         mapping = pci_map_page(tp->pdev,
5534                                                frag->page,
5535                                                frag->page_offset,
5536                                                len, PCI_DMA_TODEVICE);
5537                         if (pci_dma_mapping_error(tp->pdev, mapping))
5538                                 goto dma_error;
5539
5540                         tnapi->tx_buffers[entry].skb = NULL;
5541                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5542                                            mapping);
5543
5544                         tg3_set_txd(tnapi, entry, mapping, len,
5545                                     base_flags, (i == last) | (mss << 1));
5546
5547                         entry = NEXT_TX(entry);
5548                 }
5549         }
5550
5551         /* Packets are ready, update Tx producer idx local and on card. */
5552         tw32_tx_mbox(tnapi->prodmbox, entry);
5553
5554         tnapi->tx_prod = entry;
5555         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5556                 netif_tx_stop_queue(txq);
5557                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5558                         netif_tx_wake_queue(txq);
5559         }
5560
5561 out_unlock:
5562         mmiowb();
5563
5564         return NETDEV_TX_OK;
5565
5566 dma_error:
5567         last = i;
5568         entry = tnapi->tx_prod;
5569         tnapi->tx_buffers[entry].skb = NULL;
5570         pci_unmap_single(tp->pdev,
5571                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5572                          skb_headlen(skb),
5573                          PCI_DMA_TODEVICE);
5574         for (i = 0; i <= last; i++) {
5575                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5576                 entry = NEXT_TX(entry);
5577
5578                 pci_unmap_page(tp->pdev,
5579                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5580                                               mapping),
5581                                frag->size, PCI_DMA_TODEVICE);
5582         }
5583
5584         dev_kfree_skb(skb);
5585         return NETDEV_TX_OK;
5586 }
5587
5588 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5589                                           struct net_device *);
5590
5591 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5592  * TSO header is greater than 80 bytes.
5593  */
5594 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5595 {
5596         struct sk_buff *segs, *nskb;
5597         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5598
5599         /* Estimate the number of fragments in the worst case */
5600         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5601                 netif_stop_queue(tp->dev);
5602                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5603                         return NETDEV_TX_BUSY;
5604
5605                 netif_wake_queue(tp->dev);
5606         }
5607
5608         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5609         if (IS_ERR(segs))
5610                 goto tg3_tso_bug_end;
5611
5612         do {
5613                 nskb = segs;
5614                 segs = segs->next;
5615                 nskb->next = NULL;
5616                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5617         } while (segs);
5618
5619 tg3_tso_bug_end:
5620         dev_kfree_skb(skb);
5621
5622         return NETDEV_TX_OK;
5623 }
5624
5625 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5626  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5627  */
5628 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5629                                           struct net_device *dev)
5630 {
5631         struct tg3 *tp = netdev_priv(dev);
5632         u32 len, entry, base_flags, mss;
5633         int would_hit_hwbug;
5634         dma_addr_t mapping;
5635         struct tg3_napi *tnapi;
5636         struct netdev_queue *txq;
5637         unsigned int i, last;
5638
5639
5640         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5641         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5642         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5643                 tnapi++;
5644
5645         /* We are running in BH disabled context with netif_tx_lock
5646          * and TX reclaim runs via tp->napi.poll inside of a software
5647          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5648          * no IRQ context deadlocks to worry about either.  Rejoice!
5649          */
5650         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5651                 if (!netif_tx_queue_stopped(txq)) {
5652                         netif_tx_stop_queue(txq);
5653
5654                         /* This is a hard error, log it. */
5655                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5656                                "queue awake!\n", dev->name);
5657                 }
5658                 return NETDEV_TX_BUSY;
5659         }
5660
5661         entry = tnapi->tx_prod;
5662         base_flags = 0;
5663         if (skb->ip_summed == CHECKSUM_PARTIAL)
5664                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5665
5666         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5667                 struct iphdr *iph;
5668                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5669
5670                 if (skb_header_cloned(skb) &&
5671                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5672                         dev_kfree_skb(skb);
5673                         goto out_unlock;
5674                 }
5675
5676                 tcp_opt_len = tcp_optlen(skb);
5677                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5678
5679                 hdr_len = ip_tcp_len + tcp_opt_len;
5680                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5681                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5682                         return (tg3_tso_bug(tp, skb));
5683
5684                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5685                                TXD_FLAG_CPU_POST_DMA);
5686
5687                 iph = ip_hdr(skb);
5688                 iph->check = 0;
5689                 iph->tot_len = htons(mss + hdr_len);
5690                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5691                         tcp_hdr(skb)->check = 0;
5692                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5693                 } else
5694                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5695                                                                  iph->daddr, 0,
5696                                                                  IPPROTO_TCP,
5697                                                                  0);
5698
5699                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5700                         mss |= (hdr_len & 0xc) << 12;
5701                         if (hdr_len & 0x10)
5702                                 base_flags |= 0x00000010;
5703                         base_flags |= (hdr_len & 0x3e0) << 5;
5704                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5705                         mss |= hdr_len << 9;
5706                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5707                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5708                         if (tcp_opt_len || iph->ihl > 5) {
5709                                 int tsflags;
5710
5711                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5712                                 mss |= (tsflags << 11);
5713                         }
5714                 } else {
5715                         if (tcp_opt_len || iph->ihl > 5) {
5716                                 int tsflags;
5717
5718                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5719                                 base_flags |= tsflags << 12;
5720                         }
5721                 }
5722         }
5723 #if TG3_VLAN_TAG_USED
5724         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5725                 base_flags |= (TXD_FLAG_VLAN |
5726                                (vlan_tx_tag_get(skb) << 16));
5727 #endif
5728
5729         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5730             !mss && skb->len > ETH_DATA_LEN)
5731                 base_flags |= TXD_FLAG_JMB_PKT;
5732
5733         len = skb_headlen(skb);
5734
5735         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5736         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5737                 dev_kfree_skb(skb);
5738                 goto out_unlock;
5739         }
5740
5741         tnapi->tx_buffers[entry].skb = skb;
5742         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5743
5744         would_hit_hwbug = 0;
5745
5746         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5747                 would_hit_hwbug = 1;
5748
5749         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5750             tg3_4g_overflow_test(mapping, len))
5751                 would_hit_hwbug = 1;
5752
5753         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5754             tg3_40bit_overflow_test(tp, mapping, len))
5755                 would_hit_hwbug = 1;
5756
5757         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5758                 would_hit_hwbug = 1;
5759
5760         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5761                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5762
5763         entry = NEXT_TX(entry);
5764
5765         /* Now loop through additional data fragments, and queue them. */
5766         if (skb_shinfo(skb)->nr_frags > 0) {
5767                 last = skb_shinfo(skb)->nr_frags - 1;
5768                 for (i = 0; i <= last; i++) {
5769                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5770
5771                         len = frag->size;
5772                         mapping = pci_map_page(tp->pdev,
5773                                                frag->page,
5774                                                frag->page_offset,
5775                                                len, PCI_DMA_TODEVICE);
5776
5777                         tnapi->tx_buffers[entry].skb = NULL;
5778                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5779                                            mapping);
5780                         if (pci_dma_mapping_error(tp->pdev, mapping))
5781                                 goto dma_error;
5782
5783                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5784                             len <= 8)
5785                                 would_hit_hwbug = 1;
5786
5787                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5788                             tg3_4g_overflow_test(mapping, len))
5789                                 would_hit_hwbug = 1;
5790
5791                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5792                             tg3_40bit_overflow_test(tp, mapping, len))
5793                                 would_hit_hwbug = 1;
5794
5795                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5796                                 tg3_set_txd(tnapi, entry, mapping, len,
5797                                             base_flags, (i == last)|(mss << 1));
5798                         else
5799                                 tg3_set_txd(tnapi, entry, mapping, len,
5800                                             base_flags, (i == last));
5801
5802                         entry = NEXT_TX(entry);
5803                 }
5804         }
5805
5806         if (would_hit_hwbug) {
5807                 u32 last_plus_one = entry;
5808                 u32 start;
5809
5810                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5811                 start &= (TG3_TX_RING_SIZE - 1);
5812
5813                 /* If the workaround fails due to memory/mapping
5814                  * failure, silently drop this packet.
5815                  */
5816                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5817                                                 &start, base_flags, mss))
5818                         goto out_unlock;
5819
5820                 entry = start;
5821         }
5822
5823         /* Packets are ready, update Tx producer idx local and on card. */
5824         tw32_tx_mbox(tnapi->prodmbox, entry);
5825
5826         tnapi->tx_prod = entry;
5827         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5828                 netif_tx_stop_queue(txq);
5829                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5830                         netif_tx_wake_queue(txq);
5831         }
5832
5833 out_unlock:
5834         mmiowb();
5835
5836         return NETDEV_TX_OK;
5837
5838 dma_error:
5839         last = i;
5840         entry = tnapi->tx_prod;
5841         tnapi->tx_buffers[entry].skb = NULL;
5842         pci_unmap_single(tp->pdev,
5843                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5844                          skb_headlen(skb),
5845                          PCI_DMA_TODEVICE);
5846         for (i = 0; i <= last; i++) {
5847                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5848                 entry = NEXT_TX(entry);
5849
5850                 pci_unmap_page(tp->pdev,
5851                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5852                                               mapping),
5853                                frag->size, PCI_DMA_TODEVICE);
5854         }
5855
5856         dev_kfree_skb(skb);
5857         return NETDEV_TX_OK;
5858 }
5859
5860 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5861                                int new_mtu)
5862 {
5863         dev->mtu = new_mtu;
5864
5865         if (new_mtu > ETH_DATA_LEN) {
5866                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5867                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5868                         ethtool_op_set_tso(dev, 0);
5869                 }
5870                 else
5871                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5872         } else {
5873                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5874                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5875                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5876         }
5877 }
5878
5879 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5880 {
5881         struct tg3 *tp = netdev_priv(dev);
5882         int err;
5883
5884         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5885                 return -EINVAL;
5886
5887         if (!netif_running(dev)) {
5888                 /* We'll just catch it later when the
5889                  * device is up'd.
5890                  */
5891                 tg3_set_mtu(dev, tp, new_mtu);
5892                 return 0;
5893         }
5894
5895         tg3_phy_stop(tp);
5896
5897         tg3_netif_stop(tp);
5898
5899         tg3_full_lock(tp, 1);
5900
5901         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5902
5903         tg3_set_mtu(dev, tp, new_mtu);
5904
5905         err = tg3_restart_hw(tp, 0);
5906
5907         if (!err)
5908                 tg3_netif_start(tp);
5909
5910         tg3_full_unlock(tp);
5911
5912         if (!err)
5913                 tg3_phy_start(tp);
5914
5915         return err;
5916 }
5917
5918 static void tg3_rx_prodring_free(struct tg3 *tp,
5919                                  struct tg3_rx_prodring_set *tpr)
5920 {
5921         int i;
5922
5923         if (tpr != &tp->prodring[0]) {
5924                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5925                      i = (i + 1) % TG3_RX_RING_SIZE)
5926                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5927                                         tp->rx_pkt_map_sz);
5928
5929                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5930                         for (i = tpr->rx_jmb_cons_idx;
5931                              i != tpr->rx_jmb_prod_idx;
5932                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5933                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5934                                                 TG3_RX_JMB_MAP_SZ);
5935                         }
5936                 }
5937
5938                 return;
5939         }
5940
5941         for (i = 0; i < TG3_RX_RING_SIZE; i++)
5942                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5943                                 tp->rx_pkt_map_sz);
5944
5945         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5946                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5947                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5948                                         TG3_RX_JMB_MAP_SZ);
5949         }
5950 }
5951
5952 /* Initialize tx/rx rings for packet processing.
5953  *
5954  * The chip has been shut down and the driver detached from
5955  * the networking, so no interrupts or new tx packets will
5956  * end up in the driver.  tp->{tx,}lock are held and thus
5957  * we may not sleep.
5958  */
5959 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5960                                  struct tg3_rx_prodring_set *tpr)
5961 {
5962         u32 i, rx_pkt_dma_sz;
5963
5964         tpr->rx_std_cons_idx = 0;
5965         tpr->rx_std_prod_idx = 0;
5966         tpr->rx_jmb_cons_idx = 0;
5967         tpr->rx_jmb_prod_idx = 0;
5968
5969         if (tpr != &tp->prodring[0]) {
5970                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5971                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5972                         memset(&tpr->rx_jmb_buffers[0], 0,
5973                                TG3_RX_JMB_BUFF_RING_SIZE);
5974                 goto done;
5975         }
5976
5977         /* Zero out all descriptors. */
5978         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5979
5980         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5981         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5982             tp->dev->mtu > ETH_DATA_LEN)
5983                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5984         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5985
5986         /* Initialize invariants of the rings, we only set this
5987          * stuff once.  This works because the card does not
5988          * write into the rx buffer posting rings.
5989          */
5990         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5991                 struct tg3_rx_buffer_desc *rxd;
5992
5993                 rxd = &tpr->rx_std[i];
5994                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5995                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5996                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5997                                (i << RXD_OPAQUE_INDEX_SHIFT));
5998         }
5999
6000         /* Now allocate fresh SKBs for each rx ring. */
6001         for (i = 0; i < tp->rx_pending; i++) {
6002                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6003                         printk(KERN_WARNING PFX
6004                                "%s: Using a smaller RX standard ring, "
6005                                "only %d out of %d buffers were allocated "
6006                                "successfully.\n",
6007                                tp->dev->name, i, tp->rx_pending);
6008                         if (i == 0)
6009                                 goto initfail;
6010                         tp->rx_pending = i;
6011                         break;
6012                 }
6013         }
6014
6015         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6016                 goto done;
6017
6018         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6019
6020         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6021                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6022                         struct tg3_rx_buffer_desc *rxd;
6023
6024                         rxd = &tpr->rx_jmb[i].std;
6025                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6026                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6027                                 RXD_FLAG_JUMBO;
6028                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6029                                (i << RXD_OPAQUE_INDEX_SHIFT));
6030                 }
6031
6032                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6033                         if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6034                                              i) < 0) {
6035                                 printk(KERN_WARNING PFX
6036                                        "%s: Using a smaller RX jumbo ring, "
6037                                        "only %d out of %d buffers were "
6038                                        "allocated successfully.\n",
6039                                        tp->dev->name, i, tp->rx_jumbo_pending);
6040                                 if (i == 0)
6041                                         goto initfail;
6042                                 tp->rx_jumbo_pending = i;
6043                                 break;
6044                         }
6045                 }
6046         }
6047
6048 done:
6049         return 0;
6050
6051 initfail:
6052         tg3_rx_prodring_free(tp, tpr);
6053         return -ENOMEM;
6054 }
6055
6056 static void tg3_rx_prodring_fini(struct tg3 *tp,
6057                                  struct tg3_rx_prodring_set *tpr)
6058 {
6059         kfree(tpr->rx_std_buffers);
6060         tpr->rx_std_buffers = NULL;
6061         kfree(tpr->rx_jmb_buffers);
6062         tpr->rx_jmb_buffers = NULL;
6063         if (tpr->rx_std) {
6064                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6065                                     tpr->rx_std, tpr->rx_std_mapping);
6066                 tpr->rx_std = NULL;
6067         }
6068         if (tpr->rx_jmb) {
6069                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6070                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6071                 tpr->rx_jmb = NULL;
6072         }
6073 }
6074
6075 static int tg3_rx_prodring_init(struct tg3 *tp,
6076                                 struct tg3_rx_prodring_set *tpr)
6077 {
6078         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6079         if (!tpr->rx_std_buffers)
6080                 return -ENOMEM;
6081
6082         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6083                                            &tpr->rx_std_mapping);
6084         if (!tpr->rx_std)
6085                 goto err_out;
6086
6087         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6088                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6089                                               GFP_KERNEL);
6090                 if (!tpr->rx_jmb_buffers)
6091                         goto err_out;
6092
6093                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6094                                                    TG3_RX_JUMBO_RING_BYTES,
6095                                                    &tpr->rx_jmb_mapping);
6096                 if (!tpr->rx_jmb)
6097                         goto err_out;
6098         }
6099
6100         return 0;
6101
6102 err_out:
6103         tg3_rx_prodring_fini(tp, tpr);
6104         return -ENOMEM;
6105 }
6106
6107 /* Free up pending packets in all rx/tx rings.
6108  *
6109  * The chip has been shut down and the driver detached from
6110  * the networking, so no interrupts or new tx packets will
6111  * end up in the driver.  tp->{tx,}lock is not held and we are not
6112  * in an interrupt context and thus may sleep.
6113  */
6114 static void tg3_free_rings(struct tg3 *tp)
6115 {
6116         int i, j;
6117
6118         for (j = 0; j < tp->irq_cnt; j++) {
6119                 struct tg3_napi *tnapi = &tp->napi[j];
6120
6121                 if (!tnapi->tx_buffers)
6122                         continue;
6123
6124                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6125                         struct ring_info *txp;
6126                         struct sk_buff *skb;
6127                         unsigned int k;
6128
6129                         txp = &tnapi->tx_buffers[i];
6130                         skb = txp->skb;
6131
6132                         if (skb == NULL) {
6133                                 i++;
6134                                 continue;
6135                         }
6136
6137                         pci_unmap_single(tp->pdev,
6138                                          pci_unmap_addr(txp, mapping),
6139                                          skb_headlen(skb),
6140                                          PCI_DMA_TODEVICE);
6141                         txp->skb = NULL;
6142
6143                         i++;
6144
6145                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6146                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6147                                 pci_unmap_page(tp->pdev,
6148                                                pci_unmap_addr(txp, mapping),
6149                                                skb_shinfo(skb)->frags[k].size,
6150                                                PCI_DMA_TODEVICE);
6151                                 i++;
6152                         }
6153
6154                         dev_kfree_skb_any(skb);
6155                 }
6156
6157                 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6158                         tg3_rx_prodring_free(tp, &tp->prodring[j]);
6159         }
6160 }
6161
6162 /* Initialize tx/rx rings for packet processing.
6163  *
6164  * The chip has been shut down and the driver detached from
6165  * the networking, so no interrupts or new tx packets will
6166  * end up in the driver.  tp->{tx,}lock are held and thus
6167  * we may not sleep.
6168  */
6169 static int tg3_init_rings(struct tg3 *tp)
6170 {
6171         int i;
6172
6173         /* Free up all the SKBs. */
6174         tg3_free_rings(tp);
6175
6176         for (i = 0; i < tp->irq_cnt; i++) {
6177                 struct tg3_napi *tnapi = &tp->napi[i];
6178
6179                 tnapi->last_tag = 0;
6180                 tnapi->last_irq_tag = 0;
6181                 tnapi->hw_status->status = 0;
6182                 tnapi->hw_status->status_tag = 0;
6183                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6184
6185                 tnapi->tx_prod = 0;
6186                 tnapi->tx_cons = 0;
6187                 if (tnapi->tx_ring)
6188                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6189
6190                 tnapi->rx_rcb_ptr = 0;
6191                 if (tnapi->rx_rcb)
6192                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6193
6194                 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6195                         tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6196                         return -ENOMEM;
6197         }
6198
6199         return 0;
6200 }
6201
6202 /*
6203  * Must not be invoked with interrupt sources disabled and
6204  * the hardware shutdown down.
6205  */
6206 static void tg3_free_consistent(struct tg3 *tp)
6207 {
6208         int i;
6209
6210         for (i = 0; i < tp->irq_cnt; i++) {
6211                 struct tg3_napi *tnapi = &tp->napi[i];
6212
6213                 if (tnapi->tx_ring) {
6214                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6215                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6216                         tnapi->tx_ring = NULL;
6217                 }
6218
6219                 kfree(tnapi->tx_buffers);
6220                 tnapi->tx_buffers = NULL;
6221
6222                 if (tnapi->rx_rcb) {
6223                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6224                                             tnapi->rx_rcb,
6225                                             tnapi->rx_rcb_mapping);
6226                         tnapi->rx_rcb = NULL;
6227                 }
6228
6229                 if (tnapi->hw_status) {
6230                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6231                                             tnapi->hw_status,
6232                                             tnapi->status_mapping);
6233                         tnapi->hw_status = NULL;
6234                 }
6235         }
6236
6237         if (tp->hw_stats) {
6238                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6239                                     tp->hw_stats, tp->stats_mapping);
6240                 tp->hw_stats = NULL;
6241         }
6242
6243         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6244                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6245 }
6246
6247 /*
6248  * Must not be invoked with interrupt sources disabled and
6249  * the hardware shutdown down.  Can sleep.
6250  */
6251 static int tg3_alloc_consistent(struct tg3 *tp)
6252 {
6253         int i;
6254
6255         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6256                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6257                         goto err_out;
6258         }
6259
6260         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6261                                             sizeof(struct tg3_hw_stats),
6262                                             &tp->stats_mapping);
6263         if (!tp->hw_stats)
6264                 goto err_out;
6265
6266         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6267
6268         for (i = 0; i < tp->irq_cnt; i++) {
6269                 struct tg3_napi *tnapi = &tp->napi[i];
6270                 struct tg3_hw_status *sblk;
6271
6272                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6273                                                         TG3_HW_STATUS_SIZE,
6274                                                         &tnapi->status_mapping);
6275                 if (!tnapi->hw_status)
6276                         goto err_out;
6277
6278                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6279                 sblk = tnapi->hw_status;
6280
6281                 /* If multivector TSS is enabled, vector 0 does not handle
6282                  * tx interrupts.  Don't allocate any resources for it.
6283                  */
6284                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6285                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6286                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6287                                                     TG3_TX_RING_SIZE,
6288                                                     GFP_KERNEL);
6289                         if (!tnapi->tx_buffers)
6290                                 goto err_out;
6291
6292                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6293                                                               TG3_TX_RING_BYTES,
6294                                                        &tnapi->tx_desc_mapping);
6295                         if (!tnapi->tx_ring)
6296                                 goto err_out;
6297                 }
6298
6299                 /*
6300                  * When RSS is enabled, the status block format changes
6301                  * slightly.  The "rx_jumbo_consumer", "reserved",
6302                  * and "rx_mini_consumer" members get mapped to the
6303                  * other three rx return ring producer indexes.
6304                  */
6305                 switch (i) {
6306                 default:
6307                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6308                         break;
6309                 case 2:
6310                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6311                         break;
6312                 case 3:
6313                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6314                         break;
6315                 case 4:
6316                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6317                         break;
6318                 }
6319
6320                 if (tp->irq_cnt == 1)
6321                         tnapi->prodring = &tp->prodring[0];
6322                 else if (i)
6323                         tnapi->prodring = &tp->prodring[i - 1];
6324
6325                 /*
6326                  * If multivector RSS is enabled, vector 0 does not handle
6327                  * rx or tx interrupts.  Don't allocate any resources for it.
6328                  */
6329                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6330                         continue;
6331
6332                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6333                                                      TG3_RX_RCB_RING_BYTES(tp),
6334                                                      &tnapi->rx_rcb_mapping);
6335                 if (!tnapi->rx_rcb)
6336                         goto err_out;
6337
6338                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6339         }
6340
6341         return 0;
6342
6343 err_out:
6344         tg3_free_consistent(tp);
6345         return -ENOMEM;
6346 }
6347
6348 #define MAX_WAIT_CNT 1000
6349
6350 /* To stop a block, clear the enable bit and poll till it
6351  * clears.  tp->lock is held.
6352  */
6353 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6354 {
6355         unsigned int i;
6356         u32 val;
6357
6358         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6359                 switch (ofs) {
6360                 case RCVLSC_MODE:
6361                 case DMAC_MODE:
6362                 case MBFREE_MODE:
6363                 case BUFMGR_MODE:
6364                 case MEMARB_MODE:
6365                         /* We can't enable/disable these bits of the
6366                          * 5705/5750, just say success.
6367                          */
6368                         return 0;
6369
6370                 default:
6371                         break;
6372                 }
6373         }
6374
6375         val = tr32(ofs);
6376         val &= ~enable_bit;
6377         tw32_f(ofs, val);
6378
6379         for (i = 0; i < MAX_WAIT_CNT; i++) {
6380                 udelay(100);
6381                 val = tr32(ofs);
6382                 if ((val & enable_bit) == 0)
6383                         break;
6384         }
6385
6386         if (i == MAX_WAIT_CNT && !silent) {
6387                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6388                        "ofs=%lx enable_bit=%x\n",
6389                        ofs, enable_bit);
6390                 return -ENODEV;
6391         }
6392
6393         return 0;
6394 }
6395
6396 /* tp->lock is held. */
6397 static int tg3_abort_hw(struct tg3 *tp, int silent)
6398 {
6399         int i, err;
6400
6401         tg3_disable_ints(tp);
6402
6403         tp->rx_mode &= ~RX_MODE_ENABLE;
6404         tw32_f(MAC_RX_MODE, tp->rx_mode);
6405         udelay(10);
6406
6407         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6408         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6409         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6410         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6411         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6412         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6413
6414         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6415         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6416         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6417         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6418         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6419         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6420         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6421
6422         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6423         tw32_f(MAC_MODE, tp->mac_mode);
6424         udelay(40);
6425
6426         tp->tx_mode &= ~TX_MODE_ENABLE;
6427         tw32_f(MAC_TX_MODE, tp->tx_mode);
6428
6429         for (i = 0; i < MAX_WAIT_CNT; i++) {
6430                 udelay(100);
6431                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6432                         break;
6433         }
6434         if (i >= MAX_WAIT_CNT) {
6435                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6436                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6437                        tp->dev->name, tr32(MAC_TX_MODE));
6438                 err |= -ENODEV;
6439         }
6440
6441         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6442         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6443         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6444
6445         tw32(FTQ_RESET, 0xffffffff);
6446         tw32(FTQ_RESET, 0x00000000);
6447
6448         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6449         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6450
6451         for (i = 0; i < tp->irq_cnt; i++) {
6452                 struct tg3_napi *tnapi = &tp->napi[i];
6453                 if (tnapi->hw_status)
6454                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6455         }
6456         if (tp->hw_stats)
6457                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6458
6459         return err;
6460 }
6461
6462 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6463 {
6464         int i;
6465         u32 apedata;
6466
6467         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6468         if (apedata != APE_SEG_SIG_MAGIC)
6469                 return;
6470
6471         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6472         if (!(apedata & APE_FW_STATUS_READY))
6473                 return;
6474
6475         /* Wait for up to 1 millisecond for APE to service previous event. */
6476         for (i = 0; i < 10; i++) {
6477                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6478                         return;
6479
6480                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6481
6482                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6483                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6484                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6485
6486                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6487
6488                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6489                         break;
6490
6491                 udelay(100);
6492         }
6493
6494         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6495                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6496 }
6497
6498 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6499 {
6500         u32 event;
6501         u32 apedata;
6502
6503         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6504                 return;
6505
6506         switch (kind) {
6507                 case RESET_KIND_INIT:
6508                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6509                                         APE_HOST_SEG_SIG_MAGIC);
6510                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6511                                         APE_HOST_SEG_LEN_MAGIC);
6512                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6513                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6514                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6515                                         APE_HOST_DRIVER_ID_MAGIC);
6516                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6517                                         APE_HOST_BEHAV_NO_PHYLOCK);
6518
6519                         event = APE_EVENT_STATUS_STATE_START;
6520                         break;
6521                 case RESET_KIND_SHUTDOWN:
6522                         /* With the interface we are currently using,
6523                          * APE does not track driver state.  Wiping
6524                          * out the HOST SEGMENT SIGNATURE forces
6525                          * the APE to assume OS absent status.
6526                          */
6527                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6528
6529                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6530                         break;
6531                 case RESET_KIND_SUSPEND:
6532                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6533                         break;
6534                 default:
6535                         return;
6536         }
6537
6538         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6539
6540         tg3_ape_send_event(tp, event);
6541 }
6542
6543 /* tp->lock is held. */
6544 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6545 {
6546         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6547                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6548
6549         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6550                 switch (kind) {
6551                 case RESET_KIND_INIT:
6552                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6553                                       DRV_STATE_START);
6554                         break;
6555
6556                 case RESET_KIND_SHUTDOWN:
6557                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6558                                       DRV_STATE_UNLOAD);
6559                         break;
6560
6561                 case RESET_KIND_SUSPEND:
6562                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6563                                       DRV_STATE_SUSPEND);
6564                         break;
6565
6566                 default:
6567                         break;
6568                 }
6569         }
6570
6571         if (kind == RESET_KIND_INIT ||
6572             kind == RESET_KIND_SUSPEND)
6573                 tg3_ape_driver_state_change(tp, kind);
6574 }
6575
6576 /* tp->lock is held. */
6577 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6578 {
6579         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6580                 switch (kind) {
6581                 case RESET_KIND_INIT:
6582                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6583                                       DRV_STATE_START_DONE);
6584                         break;
6585
6586                 case RESET_KIND_SHUTDOWN:
6587                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6588                                       DRV_STATE_UNLOAD_DONE);
6589                         break;
6590
6591                 default:
6592                         break;
6593                 }
6594         }
6595
6596         if (kind == RESET_KIND_SHUTDOWN)
6597                 tg3_ape_driver_state_change(tp, kind);
6598 }
6599
6600 /* tp->lock is held. */
6601 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6602 {
6603         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6604                 switch (kind) {
6605                 case RESET_KIND_INIT:
6606                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6607                                       DRV_STATE_START);
6608                         break;
6609
6610                 case RESET_KIND_SHUTDOWN:
6611                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6612                                       DRV_STATE_UNLOAD);
6613                         break;
6614
6615                 case RESET_KIND_SUSPEND:
6616                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6617                                       DRV_STATE_SUSPEND);
6618                         break;
6619
6620                 default:
6621                         break;
6622                 }
6623         }
6624 }
6625
6626 static int tg3_poll_fw(struct tg3 *tp)
6627 {
6628         int i;
6629         u32 val;
6630
6631         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6632                 /* Wait up to 20ms for init done. */
6633                 for (i = 0; i < 200; i++) {
6634                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6635                                 return 0;
6636                         udelay(100);
6637                 }
6638                 return -ENODEV;
6639         }
6640
6641         /* Wait for firmware initialization to complete. */
6642         for (i = 0; i < 100000; i++) {
6643                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6644                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6645                         break;
6646                 udelay(10);
6647         }
6648
6649         /* Chip might not be fitted with firmware.  Some Sun onboard
6650          * parts are configured like that.  So don't signal the timeout
6651          * of the above loop as an error, but do report the lack of
6652          * running firmware once.
6653          */
6654         if (i >= 100000 &&
6655             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6656                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6657
6658                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6659                        tp->dev->name);
6660         }
6661
6662         return 0;
6663 }
6664
6665 /* Save PCI command register before chip reset */
6666 static void tg3_save_pci_state(struct tg3 *tp)
6667 {
6668         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6669 }
6670
6671 /* Restore PCI state after chip reset */
6672 static void tg3_restore_pci_state(struct tg3 *tp)
6673 {
6674         u32 val;
6675
6676         /* Re-enable indirect register accesses. */
6677         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6678                                tp->misc_host_ctrl);
6679
6680         /* Set MAX PCI retry to zero. */
6681         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6682         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6683             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6684                 val |= PCISTATE_RETRY_SAME_DMA;
6685         /* Allow reads and writes to the APE register and memory space. */
6686         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6687                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6688                        PCISTATE_ALLOW_APE_SHMEM_WR;
6689         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6690
6691         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6692
6693         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6694                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6695                         pcie_set_readrq(tp->pdev, 4096);
6696                 else {
6697                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6698                                               tp->pci_cacheline_sz);
6699                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6700                                               tp->pci_lat_timer);
6701                 }
6702         }
6703
6704         /* Make sure PCI-X relaxed ordering bit is clear. */
6705         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6706                 u16 pcix_cmd;
6707
6708                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6709                                      &pcix_cmd);
6710                 pcix_cmd &= ~PCI_X_CMD_ERO;
6711                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6712                                       pcix_cmd);
6713         }
6714
6715         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6716
6717                 /* Chip reset on 5780 will reset MSI enable bit,
6718                  * so need to restore it.
6719                  */
6720                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6721                         u16 ctrl;
6722
6723                         pci_read_config_word(tp->pdev,
6724                                              tp->msi_cap + PCI_MSI_FLAGS,
6725                                              &ctrl);
6726                         pci_write_config_word(tp->pdev,
6727                                               tp->msi_cap + PCI_MSI_FLAGS,
6728                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6729                         val = tr32(MSGINT_MODE);
6730                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6731                 }
6732         }
6733 }
6734
6735 static void tg3_stop_fw(struct tg3 *);
6736
6737 /* tp->lock is held. */
6738 static int tg3_chip_reset(struct tg3 *tp)
6739 {
6740         u32 val;
6741         void (*write_op)(struct tg3 *, u32, u32);
6742         int i, err;
6743
6744         tg3_nvram_lock(tp);
6745
6746         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6747
6748         /* No matching tg3_nvram_unlock() after this because
6749          * chip reset below will undo the nvram lock.
6750          */
6751         tp->nvram_lock_cnt = 0;
6752
6753         /* GRC_MISC_CFG core clock reset will clear the memory
6754          * enable bit in PCI register 4 and the MSI enable bit
6755          * on some chips, so we save relevant registers here.
6756          */
6757         tg3_save_pci_state(tp);
6758
6759         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6760             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6761                 tw32(GRC_FASTBOOT_PC, 0);
6762
6763         /*
6764          * We must avoid the readl() that normally takes place.
6765          * It locks machines, causes machine checks, and other
6766          * fun things.  So, temporarily disable the 5701
6767          * hardware workaround, while we do the reset.
6768          */
6769         write_op = tp->write32;
6770         if (write_op == tg3_write_flush_reg32)
6771                 tp->write32 = tg3_write32;
6772
6773         /* Prevent the irq handler from reading or writing PCI registers
6774          * during chip reset when the memory enable bit in the PCI command
6775          * register may be cleared.  The chip does not generate interrupt
6776          * at this time, but the irq handler may still be called due to irq
6777          * sharing or irqpoll.
6778          */
6779         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6780         for (i = 0; i < tp->irq_cnt; i++) {
6781                 struct tg3_napi *tnapi = &tp->napi[i];
6782                 if (tnapi->hw_status) {
6783                         tnapi->hw_status->status = 0;
6784                         tnapi->hw_status->status_tag = 0;
6785                 }
6786                 tnapi->last_tag = 0;
6787                 tnapi->last_irq_tag = 0;
6788         }
6789         smp_mb();
6790
6791         for (i = 0; i < tp->irq_cnt; i++)
6792                 synchronize_irq(tp->napi[i].irq_vec);
6793
6794         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6795                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6796                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6797         }
6798
6799         /* do the reset */
6800         val = GRC_MISC_CFG_CORECLK_RESET;
6801
6802         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6803                 if (tr32(0x7e2c) == 0x60) {
6804                         tw32(0x7e2c, 0x20);
6805                 }
6806                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6807                         tw32(GRC_MISC_CFG, (1 << 29));
6808                         val |= (1 << 29);
6809                 }
6810         }
6811
6812         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6813                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6814                 tw32(GRC_VCPU_EXT_CTRL,
6815                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6816         }
6817
6818         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6819                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6820         tw32(GRC_MISC_CFG, val);
6821
6822         /* restore 5701 hardware bug workaround write method */
6823         tp->write32 = write_op;
6824
6825         /* Unfortunately, we have to delay before the PCI read back.
6826          * Some 575X chips even will not respond to a PCI cfg access
6827          * when the reset command is given to the chip.
6828          *
6829          * How do these hardware designers expect things to work
6830          * properly if the PCI write is posted for a long period
6831          * of time?  It is always necessary to have some method by
6832          * which a register read back can occur to push the write
6833          * out which does the reset.
6834          *
6835          * For most tg3 variants the trick below was working.
6836          * Ho hum...
6837          */
6838         udelay(120);
6839
6840         /* Flush PCI posted writes.  The normal MMIO registers
6841          * are inaccessible at this time so this is the only
6842          * way to make this reliably (actually, this is no longer
6843          * the case, see above).  I tried to use indirect
6844          * register read/write but this upset some 5701 variants.
6845          */
6846         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6847
6848         udelay(120);
6849
6850         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6851                 u16 val16;
6852
6853                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6854                         int i;
6855                         u32 cfg_val;
6856
6857                         /* Wait for link training to complete.  */
6858                         for (i = 0; i < 5000; i++)
6859                                 udelay(100);
6860
6861                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6862                         pci_write_config_dword(tp->pdev, 0xc4,
6863                                                cfg_val | (1 << 15));
6864                 }
6865
6866                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6867                 pci_read_config_word(tp->pdev,
6868                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6869                                      &val16);
6870                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6871                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6872                 /*
6873                  * Older PCIe devices only support the 128 byte
6874                  * MPS setting.  Enforce the restriction.
6875                  */
6876                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6877                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6878                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6879                 pci_write_config_word(tp->pdev,
6880                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6881                                       val16);
6882
6883                 pcie_set_readrq(tp->pdev, 4096);
6884
6885                 /* Clear error status */
6886                 pci_write_config_word(tp->pdev,
6887                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6888                                       PCI_EXP_DEVSTA_CED |
6889                                       PCI_EXP_DEVSTA_NFED |
6890                                       PCI_EXP_DEVSTA_FED |
6891                                       PCI_EXP_DEVSTA_URD);
6892         }
6893
6894         tg3_restore_pci_state(tp);
6895
6896         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6897
6898         val = 0;
6899         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6900                 val = tr32(MEMARB_MODE);
6901         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6902
6903         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6904                 tg3_stop_fw(tp);
6905                 tw32(0x5000, 0x400);
6906         }
6907
6908         tw32(GRC_MODE, tp->grc_mode);
6909
6910         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6911                 val = tr32(0xc4);
6912
6913                 tw32(0xc4, val | (1 << 15));
6914         }
6915
6916         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6917             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6918                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6919                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6920                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6921                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6922         }
6923
6924         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6925                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6926                 tw32_f(MAC_MODE, tp->mac_mode);
6927         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6928                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6929                 tw32_f(MAC_MODE, tp->mac_mode);
6930         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6931                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6932                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6933                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6934                 tw32_f(MAC_MODE, tp->mac_mode);
6935         } else
6936                 tw32_f(MAC_MODE, 0);
6937         udelay(40);
6938
6939         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6940
6941         err = tg3_poll_fw(tp);
6942         if (err)
6943                 return err;
6944
6945         tg3_mdio_start(tp);
6946
6947         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6948                 u8 phy_addr;
6949
6950                 phy_addr = tp->phy_addr;
6951                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6952
6953                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6954                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6955                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6956                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6957                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6958                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6959                 udelay(10);
6960
6961                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6962                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6963                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6964                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6965                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6966                 udelay(10);
6967
6968                 tp->phy_addr = phy_addr;
6969         }
6970
6971         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6972             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6973             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6974             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
6975             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
6976                 val = tr32(0x7c00);
6977
6978                 tw32(0x7c00, val | (1 << 25));
6979         }
6980
6981         /* Reprobe ASF enable state.  */
6982         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6983         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6984         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6985         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6986                 u32 nic_cfg;
6987
6988                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6989                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6990                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6991                         tp->last_event_jiffies = jiffies;
6992                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6993                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6994                 }
6995         }
6996
6997         return 0;
6998 }
6999
7000 /* tp->lock is held. */
7001 static void tg3_stop_fw(struct tg3 *tp)
7002 {
7003         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7004            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7005                 /* Wait for RX cpu to ACK the previous event. */
7006                 tg3_wait_for_event_ack(tp);
7007
7008                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7009
7010                 tg3_generate_fw_event(tp);
7011
7012                 /* Wait for RX cpu to ACK this event. */
7013                 tg3_wait_for_event_ack(tp);
7014         }
7015 }
7016
7017 /* tp->lock is held. */
7018 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7019 {
7020         int err;
7021
7022         tg3_stop_fw(tp);
7023
7024         tg3_write_sig_pre_reset(tp, kind);
7025
7026         tg3_abort_hw(tp, silent);
7027         err = tg3_chip_reset(tp);
7028
7029         __tg3_set_mac_addr(tp, 0);
7030
7031         tg3_write_sig_legacy(tp, kind);
7032         tg3_write_sig_post_reset(tp, kind);
7033
7034         if (err)
7035                 return err;
7036
7037         return 0;
7038 }
7039
7040 #define RX_CPU_SCRATCH_BASE     0x30000
7041 #define RX_CPU_SCRATCH_SIZE     0x04000
7042 #define TX_CPU_SCRATCH_BASE     0x34000
7043 #define TX_CPU_SCRATCH_SIZE     0x04000
7044
7045 /* tp->lock is held. */
7046 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7047 {
7048         int i;
7049
7050         BUG_ON(offset == TX_CPU_BASE &&
7051             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7052
7053         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7054                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7055
7056                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7057                 return 0;
7058         }
7059         if (offset == RX_CPU_BASE) {
7060                 for (i = 0; i < 10000; i++) {
7061                         tw32(offset + CPU_STATE, 0xffffffff);
7062                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7063                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7064                                 break;
7065                 }
7066
7067                 tw32(offset + CPU_STATE, 0xffffffff);
7068                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7069                 udelay(10);
7070         } else {
7071                 for (i = 0; i < 10000; i++) {
7072                         tw32(offset + CPU_STATE, 0xffffffff);
7073                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7074                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7075                                 break;
7076                 }
7077         }
7078
7079         if (i >= 10000) {
7080                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7081                        "and %s CPU\n",
7082                        tp->dev->name,
7083                        (offset == RX_CPU_BASE ? "RX" : "TX"));
7084                 return -ENODEV;
7085         }
7086
7087         /* Clear firmware's nvram arbitration. */
7088         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7089                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7090         return 0;
7091 }
7092
7093 struct fw_info {
7094         unsigned int fw_base;
7095         unsigned int fw_len;
7096         const __be32 *fw_data;
7097 };
7098
7099 /* tp->lock is held. */
7100 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7101                                  int cpu_scratch_size, struct fw_info *info)
7102 {
7103         int err, lock_err, i;
7104         void (*write_op)(struct tg3 *, u32, u32);
7105
7106         if (cpu_base == TX_CPU_BASE &&
7107             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7108                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7109                        "TX cpu firmware on %s which is 5705.\n",
7110                        tp->dev->name);
7111                 return -EINVAL;
7112         }
7113
7114         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7115                 write_op = tg3_write_mem;
7116         else
7117                 write_op = tg3_write_indirect_reg32;
7118
7119         /* It is possible that bootcode is still loading at this point.
7120          * Get the nvram lock first before halting the cpu.
7121          */
7122         lock_err = tg3_nvram_lock(tp);
7123         err = tg3_halt_cpu(tp, cpu_base);
7124         if (!lock_err)
7125                 tg3_nvram_unlock(tp);
7126         if (err)
7127                 goto out;
7128
7129         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7130                 write_op(tp, cpu_scratch_base + i, 0);
7131         tw32(cpu_base + CPU_STATE, 0xffffffff);
7132         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7133         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7134                 write_op(tp, (cpu_scratch_base +
7135                               (info->fw_base & 0xffff) +
7136                               (i * sizeof(u32))),
7137                               be32_to_cpu(info->fw_data[i]));
7138
7139         err = 0;
7140
7141 out:
7142         return err;
7143 }
7144
7145 /* tp->lock is held. */
7146 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7147 {
7148         struct fw_info info;
7149         const __be32 *fw_data;
7150         int err, i;
7151
7152         fw_data = (void *)tp->fw->data;
7153
7154         /* Firmware blob starts with version numbers, followed by
7155            start address and length. We are setting complete length.
7156            length = end_address_of_bss - start_address_of_text.
7157            Remainder is the blob to be loaded contiguously
7158            from start address. */
7159
7160         info.fw_base = be32_to_cpu(fw_data[1]);
7161         info.fw_len = tp->fw->size - 12;
7162         info.fw_data = &fw_data[3];
7163
7164         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7165                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7166                                     &info);
7167         if (err)
7168                 return err;
7169
7170         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7171                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7172                                     &info);
7173         if (err)
7174                 return err;
7175
7176         /* Now startup only the RX cpu. */
7177         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7178         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7179
7180         for (i = 0; i < 5; i++) {
7181                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7182                         break;
7183                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7184                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7185                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7186                 udelay(1000);
7187         }
7188         if (i >= 5) {
7189                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7190                        "to set RX CPU PC, is %08x should be %08x\n",
7191                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7192                        info.fw_base);
7193                 return -ENODEV;
7194         }
7195         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7196         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7197
7198         return 0;
7199 }
7200
7201 /* 5705 needs a special version of the TSO firmware.  */
7202
7203 /* tp->lock is held. */
7204 static int tg3_load_tso_firmware(struct tg3 *tp)
7205 {
7206         struct fw_info info;
7207         const __be32 *fw_data;
7208         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7209         int err, i;
7210
7211         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7212                 return 0;
7213
7214         fw_data = (void *)tp->fw->data;
7215
7216         /* Firmware blob starts with version numbers, followed by
7217            start address and length. We are setting complete length.
7218            length = end_address_of_bss - start_address_of_text.
7219            Remainder is the blob to be loaded contiguously
7220            from start address. */
7221
7222         info.fw_base = be32_to_cpu(fw_data[1]);
7223         cpu_scratch_size = tp->fw_len;
7224         info.fw_len = tp->fw->size - 12;
7225         info.fw_data = &fw_data[3];
7226
7227         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7228                 cpu_base = RX_CPU_BASE;
7229                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7230         } else {
7231                 cpu_base = TX_CPU_BASE;
7232                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7233                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7234         }
7235
7236         err = tg3_load_firmware_cpu(tp, cpu_base,
7237                                     cpu_scratch_base, cpu_scratch_size,
7238                                     &info);
7239         if (err)
7240                 return err;
7241
7242         /* Now startup the cpu. */
7243         tw32(cpu_base + CPU_STATE, 0xffffffff);
7244         tw32_f(cpu_base + CPU_PC, info.fw_base);
7245
7246         for (i = 0; i < 5; i++) {
7247                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7248                         break;
7249                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7250                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7251                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7252                 udelay(1000);
7253         }
7254         if (i >= 5) {
7255                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7256                        "to set CPU PC, is %08x should be %08x\n",
7257                        tp->dev->name, tr32(cpu_base + CPU_PC),
7258                        info.fw_base);
7259                 return -ENODEV;
7260         }
7261         tw32(cpu_base + CPU_STATE, 0xffffffff);
7262         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7263         return 0;
7264 }
7265
7266
7267 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7268 {
7269         struct tg3 *tp = netdev_priv(dev);
7270         struct sockaddr *addr = p;
7271         int err = 0, skip_mac_1 = 0;
7272
7273         if (!is_valid_ether_addr(addr->sa_data))
7274                 return -EINVAL;
7275
7276         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7277
7278         if (!netif_running(dev))
7279                 return 0;
7280
7281         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7282                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7283
7284                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7285                 addr0_low = tr32(MAC_ADDR_0_LOW);
7286                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7287                 addr1_low = tr32(MAC_ADDR_1_LOW);
7288
7289                 /* Skip MAC addr 1 if ASF is using it. */
7290                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7291                     !(addr1_high == 0 && addr1_low == 0))
7292                         skip_mac_1 = 1;
7293         }
7294         spin_lock_bh(&tp->lock);
7295         __tg3_set_mac_addr(tp, skip_mac_1);
7296         spin_unlock_bh(&tp->lock);
7297
7298         return err;
7299 }
7300
7301 /* tp->lock is held. */
7302 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7303                            dma_addr_t mapping, u32 maxlen_flags,
7304                            u32 nic_addr)
7305 {
7306         tg3_write_mem(tp,
7307                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7308                       ((u64) mapping >> 32));
7309         tg3_write_mem(tp,
7310                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7311                       ((u64) mapping & 0xffffffff));
7312         tg3_write_mem(tp,
7313                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7314                        maxlen_flags);
7315
7316         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7317                 tg3_write_mem(tp,
7318                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7319                               nic_addr);
7320 }
7321
7322 static void __tg3_set_rx_mode(struct net_device *);
7323 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7324 {
7325         int i;
7326
7327         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7328                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7329                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7330                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7331         } else {
7332                 tw32(HOSTCC_TXCOL_TICKS, 0);
7333                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7334                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7335         }
7336
7337         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7338                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7339                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7340                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7341         } else {
7342                 tw32(HOSTCC_RXCOL_TICKS, 0);
7343                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7344                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7345         }
7346
7347         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7348                 u32 val = ec->stats_block_coalesce_usecs;
7349
7350                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7351                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7352
7353                 if (!netif_carrier_ok(tp->dev))
7354                         val = 0;
7355
7356                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7357         }
7358
7359         for (i = 0; i < tp->irq_cnt - 1; i++) {
7360                 u32 reg;
7361
7362                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7363                 tw32(reg, ec->rx_coalesce_usecs);
7364                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7365                 tw32(reg, ec->rx_max_coalesced_frames);
7366                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7367                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7368
7369                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7370                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7371                         tw32(reg, ec->tx_coalesce_usecs);
7372                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7373                         tw32(reg, ec->tx_max_coalesced_frames);
7374                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7375                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7376                 }
7377         }
7378
7379         for (; i < tp->irq_max - 1; i++) {
7380                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7381                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7382                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7383
7384                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7385                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7386                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7387                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7388                 }
7389         }
7390 }
7391
7392 /* tp->lock is held. */
7393 static void tg3_rings_reset(struct tg3 *tp)
7394 {
7395         int i;
7396         u32 stblk, txrcb, rxrcb, limit;
7397         struct tg3_napi *tnapi = &tp->napi[0];
7398
7399         /* Disable all transmit rings but the first. */
7400         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7401                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7402         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7403                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7404         else
7405                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7406
7407         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7408              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7409                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7410                               BDINFO_FLAGS_DISABLED);
7411
7412
7413         /* Disable all receive return rings but the first. */
7414         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7415                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7416         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7417                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7418         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7419                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7420                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7421         else
7422                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7423
7424         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7425              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7426                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7427                               BDINFO_FLAGS_DISABLED);
7428
7429         /* Disable interrupts */
7430         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7431
7432         /* Zero mailbox registers. */
7433         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7434                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7435                         tp->napi[i].tx_prod = 0;
7436                         tp->napi[i].tx_cons = 0;
7437                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7438                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7439                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7440                 }
7441         } else {
7442                 tp->napi[0].tx_prod = 0;
7443                 tp->napi[0].tx_cons = 0;
7444                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7445                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7446         }
7447
7448         /* Make sure the NIC-based send BD rings are disabled. */
7449         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7450                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7451                 for (i = 0; i < 16; i++)
7452                         tw32_tx_mbox(mbox + i * 8, 0);
7453         }
7454
7455         txrcb = NIC_SRAM_SEND_RCB;
7456         rxrcb = NIC_SRAM_RCV_RET_RCB;
7457
7458         /* Clear status block in ram. */
7459         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7460
7461         /* Set status block DMA address */
7462         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7463              ((u64) tnapi->status_mapping >> 32));
7464         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7465              ((u64) tnapi->status_mapping & 0xffffffff));
7466
7467         if (tnapi->tx_ring) {
7468                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7469                                (TG3_TX_RING_SIZE <<
7470                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7471                                NIC_SRAM_TX_BUFFER_DESC);
7472                 txrcb += TG3_BDINFO_SIZE;
7473         }
7474
7475         if (tnapi->rx_rcb) {
7476                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7477                                (TG3_RX_RCB_RING_SIZE(tp) <<
7478                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7479                 rxrcb += TG3_BDINFO_SIZE;
7480         }
7481
7482         stblk = HOSTCC_STATBLCK_RING1;
7483
7484         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7485                 u64 mapping = (u64)tnapi->status_mapping;
7486                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7487                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7488
7489                 /* Clear status block in ram. */
7490                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7491
7492                 if (tnapi->tx_ring) {
7493                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7494                                        (TG3_TX_RING_SIZE <<
7495                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7496                                        NIC_SRAM_TX_BUFFER_DESC);
7497                         txrcb += TG3_BDINFO_SIZE;
7498                 }
7499
7500                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7501                                (TG3_RX_RCB_RING_SIZE(tp) <<
7502                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7503
7504                 stblk += 8;
7505                 rxrcb += TG3_BDINFO_SIZE;
7506         }
7507 }
7508
7509 /* tp->lock is held. */
7510 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7511 {
7512         u32 val, rdmac_mode;
7513         int i, err, limit;
7514         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7515
7516         tg3_disable_ints(tp);
7517
7518         tg3_stop_fw(tp);
7519
7520         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7521
7522         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7523                 tg3_abort_hw(tp, 1);
7524         }
7525
7526         if (reset_phy &&
7527             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7528                 tg3_phy_reset(tp);
7529
7530         err = tg3_chip_reset(tp);
7531         if (err)
7532                 return err;
7533
7534         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7535
7536         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7537                 val = tr32(TG3_CPMU_CTRL);
7538                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7539                 tw32(TG3_CPMU_CTRL, val);
7540
7541                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7542                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7543                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7544                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7545
7546                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7547                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7548                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7549                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7550
7551                 val = tr32(TG3_CPMU_HST_ACC);
7552                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7553                 val |= CPMU_HST_ACC_MACCLK_6_25;
7554                 tw32(TG3_CPMU_HST_ACC, val);
7555         }
7556
7557         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7558                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7559                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7560                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7561                 tw32(PCIE_PWR_MGMT_THRESH, val);
7562
7563                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7564                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7565
7566                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7567
7568                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7569                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7570         }
7571
7572         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7573                 u32 grc_mode = tr32(GRC_MODE);
7574
7575                 /* Access the lower 1K of PL PCIE block registers. */
7576                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7577                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7578
7579                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7580                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7581                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7582
7583                 tw32(GRC_MODE, grc_mode);
7584         }
7585
7586         /* This works around an issue with Athlon chipsets on
7587          * B3 tigon3 silicon.  This bit has no effect on any
7588          * other revision.  But do not set this on PCI Express
7589          * chips and don't even touch the clocks if the CPMU is present.
7590          */
7591         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7592                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7593                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7594                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7595         }
7596
7597         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7598             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7599                 val = tr32(TG3PCI_PCISTATE);
7600                 val |= PCISTATE_RETRY_SAME_DMA;
7601                 tw32(TG3PCI_PCISTATE, val);
7602         }
7603
7604         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7605                 /* Allow reads and writes to the
7606                  * APE register and memory space.
7607                  */
7608                 val = tr32(TG3PCI_PCISTATE);
7609                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7610                        PCISTATE_ALLOW_APE_SHMEM_WR;
7611                 tw32(TG3PCI_PCISTATE, val);
7612         }
7613
7614         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7615                 /* Enable some hw fixes.  */
7616                 val = tr32(TG3PCI_MSI_DATA);
7617                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7618                 tw32(TG3PCI_MSI_DATA, val);
7619         }
7620
7621         /* Descriptor ring init may make accesses to the
7622          * NIC SRAM area to setup the TX descriptors, so we
7623          * can only do this after the hardware has been
7624          * successfully reset.
7625          */
7626         err = tg3_init_rings(tp);
7627         if (err)
7628                 return err;
7629
7630         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7631             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7632                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7633                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7634                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7635         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7636                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7637                 /* This value is determined during the probe time DMA
7638                  * engine test, tg3_test_dma.
7639                  */
7640                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7641         }
7642
7643         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7644                           GRC_MODE_4X_NIC_SEND_RINGS |
7645                           GRC_MODE_NO_TX_PHDR_CSUM |
7646                           GRC_MODE_NO_RX_PHDR_CSUM);
7647         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7648
7649         /* Pseudo-header checksum is done by hardware logic and not
7650          * the offload processers, so make the chip do the pseudo-
7651          * header checksums on receive.  For transmit it is more
7652          * convenient to do the pseudo-header checksum in software
7653          * as Linux does that on transmit for us in all cases.
7654          */
7655         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7656
7657         tw32(GRC_MODE,
7658              tp->grc_mode |
7659              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7660
7661         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7662         val = tr32(GRC_MISC_CFG);
7663         val &= ~0xff;
7664         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7665         tw32(GRC_MISC_CFG, val);
7666
7667         /* Initialize MBUF/DESC pool. */
7668         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7669                 /* Do nothing.  */
7670         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7671                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7672                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7673                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7674                 else
7675                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7676                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7677                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7678         }
7679         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7680                 int fw_len;
7681
7682                 fw_len = tp->fw_len;
7683                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7684                 tw32(BUFMGR_MB_POOL_ADDR,
7685                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7686                 tw32(BUFMGR_MB_POOL_SIZE,
7687                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7688         }
7689
7690         if (tp->dev->mtu <= ETH_DATA_LEN) {
7691                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7692                      tp->bufmgr_config.mbuf_read_dma_low_water);
7693                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7694                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7695                 tw32(BUFMGR_MB_HIGH_WATER,
7696                      tp->bufmgr_config.mbuf_high_water);
7697         } else {
7698                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7699                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7700                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7701                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7702                 tw32(BUFMGR_MB_HIGH_WATER,
7703                      tp->bufmgr_config.mbuf_high_water_jumbo);
7704         }
7705         tw32(BUFMGR_DMA_LOW_WATER,
7706              tp->bufmgr_config.dma_low_water);
7707         tw32(BUFMGR_DMA_HIGH_WATER,
7708              tp->bufmgr_config.dma_high_water);
7709
7710         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7711         for (i = 0; i < 2000; i++) {
7712                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7713                         break;
7714                 udelay(10);
7715         }
7716         if (i >= 2000) {
7717                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7718                        tp->dev->name);
7719                 return -ENODEV;
7720         }
7721
7722         /* Setup replenish threshold. */
7723         val = tp->rx_pending / 8;
7724         if (val == 0)
7725                 val = 1;
7726         else if (val > tp->rx_std_max_post)
7727                 val = tp->rx_std_max_post;
7728         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7729                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7730                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7731
7732                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7733                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7734         }
7735
7736         tw32(RCVBDI_STD_THRESH, val);
7737
7738         /* Initialize TG3_BDINFO's at:
7739          *  RCVDBDI_STD_BD:     standard eth size rx ring
7740          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7741          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7742          *
7743          * like so:
7744          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7745          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7746          *                              ring attribute flags
7747          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7748          *
7749          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7750          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7751          *
7752          * The size of each ring is fixed in the firmware, but the location is
7753          * configurable.
7754          */
7755         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7756              ((u64) tpr->rx_std_mapping >> 32));
7757         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7758              ((u64) tpr->rx_std_mapping & 0xffffffff));
7759         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7760                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7761                      NIC_SRAM_RX_BUFFER_DESC);
7762
7763         /* Disable the mini ring */
7764         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7765                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7766                      BDINFO_FLAGS_DISABLED);
7767
7768         /* Program the jumbo buffer descriptor ring control
7769          * blocks on those devices that have them.
7770          */
7771         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7772             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7773                 /* Setup replenish threshold. */
7774                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7775
7776                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7777                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7778                              ((u64) tpr->rx_jmb_mapping >> 32));
7779                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7780                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7781                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7782                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7783                              BDINFO_FLAGS_USE_EXT_RECV);
7784                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7785                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7786                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7787                 } else {
7788                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7789                              BDINFO_FLAGS_DISABLED);
7790                 }
7791
7792                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7793                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7794                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7795                               (RX_STD_MAX_SIZE << 2);
7796                 else
7797                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7798         } else
7799                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7800
7801         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7802
7803         tpr->rx_std_prod_idx = tp->rx_pending;
7804         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7805
7806         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7807                           tp->rx_jumbo_pending : 0;
7808         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7809
7810         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7811             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7812                 tw32(STD_REPLENISH_LWM, 32);
7813                 tw32(JMB_REPLENISH_LWM, 16);
7814         }
7815
7816         tg3_rings_reset(tp);
7817
7818         /* Initialize MAC address and backoff seed. */
7819         __tg3_set_mac_addr(tp, 0);
7820
7821         /* MTU + ethernet header + FCS + optional VLAN tag */
7822         tw32(MAC_RX_MTU_SIZE,
7823              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7824
7825         /* The slot time is changed by tg3_setup_phy if we
7826          * run at gigabit with half duplex.
7827          */
7828         tw32(MAC_TX_LENGTHS,
7829              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7830              (6 << TX_LENGTHS_IPG_SHIFT) |
7831              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7832
7833         /* Receive rules. */
7834         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7835         tw32(RCVLPC_CONFIG, 0x0181);
7836
7837         /* Calculate RDMAC_MODE setting early, we need it to determine
7838          * the RCVLPC_STATE_ENABLE mask.
7839          */
7840         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7841                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7842                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7843                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7844                       RDMAC_MODE_LNGREAD_ENAB);
7845
7846         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7847             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7848             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7849                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7850                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7851                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7852
7853         /* If statement applies to 5705 and 5750 PCI devices only */
7854         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7855              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7856             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7857                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7858                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7859                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7860                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7861                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7862                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7863                 }
7864         }
7865
7866         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7867                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7868
7869         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7870                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7871
7872         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7873             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7874             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7875                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7876
7877         /* Receive/send statistics. */
7878         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7879                 val = tr32(RCVLPC_STATS_ENABLE);
7880                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7881                 tw32(RCVLPC_STATS_ENABLE, val);
7882         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7883                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7884                 val = tr32(RCVLPC_STATS_ENABLE);
7885                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7886                 tw32(RCVLPC_STATS_ENABLE, val);
7887         } else {
7888                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7889         }
7890         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7891         tw32(SNDDATAI_STATSENAB, 0xffffff);
7892         tw32(SNDDATAI_STATSCTRL,
7893              (SNDDATAI_SCTRL_ENABLE |
7894               SNDDATAI_SCTRL_FASTUPD));
7895
7896         /* Setup host coalescing engine. */
7897         tw32(HOSTCC_MODE, 0);
7898         for (i = 0; i < 2000; i++) {
7899                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7900                         break;
7901                 udelay(10);
7902         }
7903
7904         __tg3_set_coalesce(tp, &tp->coal);
7905
7906         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7907                 /* Status/statistics block address.  See tg3_timer,
7908                  * the tg3_periodic_fetch_stats call there, and
7909                  * tg3_get_stats to see how this works for 5705/5750 chips.
7910                  */
7911                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7912                      ((u64) tp->stats_mapping >> 32));
7913                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7914                      ((u64) tp->stats_mapping & 0xffffffff));
7915                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7916
7917                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7918
7919                 /* Clear statistics and status block memory areas */
7920                 for (i = NIC_SRAM_STATS_BLK;
7921                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7922                      i += sizeof(u32)) {
7923                         tg3_write_mem(tp, i, 0);
7924                         udelay(40);
7925                 }
7926         }
7927
7928         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7929
7930         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7931         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7932         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7933                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7934
7935         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7936                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7937                 /* reset to prevent losing 1st rx packet intermittently */
7938                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7939                 udelay(10);
7940         }
7941
7942         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7943                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7944         else
7945                 tp->mac_mode = 0;
7946         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7947                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7948         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7949             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7950             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7951                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7952         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7953         udelay(40);
7954
7955         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7956          * If TG3_FLG2_IS_NIC is zero, we should read the
7957          * register to preserve the GPIO settings for LOMs. The GPIOs,
7958          * whether used as inputs or outputs, are set by boot code after
7959          * reset.
7960          */
7961         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7962                 u32 gpio_mask;
7963
7964                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7965                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7966                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7967
7968                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7969                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7970                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7971
7972                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7973                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7974
7975                 tp->grc_local_ctrl &= ~gpio_mask;
7976                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7977
7978                 /* GPIO1 must be driven high for eeprom write protect */
7979                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7980                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7981                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7982         }
7983         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7984         udelay(100);
7985
7986         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7987                 val = tr32(MSGINT_MODE);
7988                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7989                 tw32(MSGINT_MODE, val);
7990         }
7991
7992         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7993                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7994                 udelay(40);
7995         }
7996
7997         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7998                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7999                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8000                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8001                WDMAC_MODE_LNGREAD_ENAB);
8002
8003         /* If statement applies to 5705 and 5750 PCI devices only */
8004         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8005              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8006             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8007                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8008                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8009                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8010                         /* nothing */
8011                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8012                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8013                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8014                         val |= WDMAC_MODE_RX_ACCEL;
8015                 }
8016         }
8017
8018         /* Enable host coalescing bug fix */
8019         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8020                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8021
8022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8023                 val |= WDMAC_MODE_BURST_ALL_DATA;
8024
8025         tw32_f(WDMAC_MODE, val);
8026         udelay(40);
8027
8028         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8029                 u16 pcix_cmd;
8030
8031                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8032                                      &pcix_cmd);
8033                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8034                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8035                         pcix_cmd |= PCI_X_CMD_READ_2K;
8036                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8037                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8038                         pcix_cmd |= PCI_X_CMD_READ_2K;
8039                 }
8040                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8041                                       pcix_cmd);
8042         }
8043
8044         tw32_f(RDMAC_MODE, rdmac_mode);
8045         udelay(40);
8046
8047         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8048         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8049                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8050
8051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8052                 tw32(SNDDATAC_MODE,
8053                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8054         else
8055                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8056
8057         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8058         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8059         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8060         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8061         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8062                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8063         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8064         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8065                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8066         tw32(SNDBDI_MODE, val);
8067         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8068
8069         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8070                 err = tg3_load_5701_a0_firmware_fix(tp);
8071                 if (err)
8072                         return err;
8073         }
8074
8075         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8076                 err = tg3_load_tso_firmware(tp);
8077                 if (err)
8078                         return err;
8079         }
8080
8081         tp->tx_mode = TX_MODE_ENABLE;
8082         tw32_f(MAC_TX_MODE, tp->tx_mode);
8083         udelay(100);
8084
8085         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8086                 u32 reg = MAC_RSS_INDIR_TBL_0;
8087                 u8 *ent = (u8 *)&val;
8088
8089                 /* Setup the indirection table */
8090                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8091                         int idx = i % sizeof(val);
8092
8093                         ent[idx] = i % (tp->irq_cnt - 1);
8094                         if (idx == sizeof(val) - 1) {
8095                                 tw32(reg, val);
8096                                 reg += 4;
8097                         }
8098                 }
8099
8100                 /* Setup the "secret" hash key. */
8101                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8102                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8103                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8104                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8105                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8106                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8107                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8108                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8109                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8110                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8111         }
8112
8113         tp->rx_mode = RX_MODE_ENABLE;
8114         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8115                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8116
8117         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8118                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8119                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8120                                RX_MODE_RSS_IPV6_HASH_EN |
8121                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8122                                RX_MODE_RSS_IPV4_HASH_EN |
8123                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8124
8125         tw32_f(MAC_RX_MODE, tp->rx_mode);
8126         udelay(10);
8127
8128         tw32(MAC_LED_CTRL, tp->led_ctrl);
8129
8130         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8131         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8132                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8133                 udelay(10);
8134         }
8135         tw32_f(MAC_RX_MODE, tp->rx_mode);
8136         udelay(10);
8137
8138         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8139                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8140                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8141                         /* Set drive transmission level to 1.2V  */
8142                         /* only if the signal pre-emphasis bit is not set  */
8143                         val = tr32(MAC_SERDES_CFG);
8144                         val &= 0xfffff000;
8145                         val |= 0x880;
8146                         tw32(MAC_SERDES_CFG, val);
8147                 }
8148                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8149                         tw32(MAC_SERDES_CFG, 0x616000);
8150         }
8151
8152         /* Prevent chip from dropping frames when flow control
8153          * is enabled.
8154          */
8155         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8156                 val = 1;
8157         else
8158                 val = 2;
8159         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8160
8161         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8162             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8163                 /* Use hardware link auto-negotiation */
8164                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8165         }
8166
8167         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8168             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8169                 u32 tmp;
8170
8171                 tmp = tr32(SERDES_RX_CTRL);
8172                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8173                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8174                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8175                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8176         }
8177
8178         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8179                 if (tp->link_config.phy_is_low_power) {
8180                         tp->link_config.phy_is_low_power = 0;
8181                         tp->link_config.speed = tp->link_config.orig_speed;
8182                         tp->link_config.duplex = tp->link_config.orig_duplex;
8183                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8184                 }
8185
8186                 err = tg3_setup_phy(tp, 0);
8187                 if (err)
8188                         return err;
8189
8190                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8191                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8192                         u32 tmp;
8193
8194                         /* Clear CRC stats. */
8195                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8196                                 tg3_writephy(tp, MII_TG3_TEST1,
8197                                              tmp | MII_TG3_TEST1_CRC_EN);
8198                                 tg3_readphy(tp, 0x14, &tmp);
8199                         }
8200                 }
8201         }
8202
8203         __tg3_set_rx_mode(tp->dev);
8204
8205         /* Initialize receive rules. */
8206         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8207         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8208         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8209         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8210
8211         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8212             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8213                 limit = 8;
8214         else
8215                 limit = 16;
8216         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8217                 limit -= 4;
8218         switch (limit) {
8219         case 16:
8220                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8221         case 15:
8222                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8223         case 14:
8224                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8225         case 13:
8226                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8227         case 12:
8228                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8229         case 11:
8230                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8231         case 10:
8232                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8233         case 9:
8234                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8235         case 8:
8236                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8237         case 7:
8238                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8239         case 6:
8240                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8241         case 5:
8242                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8243         case 4:
8244                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8245         case 3:
8246                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8247         case 2:
8248         case 1:
8249
8250         default:
8251                 break;
8252         }
8253
8254         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8255                 /* Write our heartbeat update interval to APE. */
8256                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8257                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8258
8259         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8260
8261         return 0;
8262 }
8263
8264 /* Called at device open time to get the chip ready for
8265  * packet processing.  Invoked with tp->lock held.
8266  */
8267 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8268 {
8269         tg3_switch_clocks(tp);
8270
8271         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8272
8273         return tg3_reset_hw(tp, reset_phy);
8274 }
8275
8276 #define TG3_STAT_ADD32(PSTAT, REG) \
8277 do {    u32 __val = tr32(REG); \
8278         (PSTAT)->low += __val; \
8279         if ((PSTAT)->low < __val) \
8280                 (PSTAT)->high += 1; \
8281 } while (0)
8282
8283 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8284 {
8285         struct tg3_hw_stats *sp = tp->hw_stats;
8286
8287         if (!netif_carrier_ok(tp->dev))
8288                 return;
8289
8290         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8291         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8292         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8293         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8294         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8295         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8296         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8297         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8298         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8299         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8300         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8301         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8302         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8303
8304         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8305         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8306         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8307         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8308         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8309         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8310         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8311         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8312         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8313         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8314         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8315         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8316         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8317         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8318
8319         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8320         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8321         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8322 }
8323
8324 static void tg3_timer(unsigned long __opaque)
8325 {
8326         struct tg3 *tp = (struct tg3 *) __opaque;
8327
8328         if (tp->irq_sync)
8329                 goto restart_timer;
8330
8331         spin_lock(&tp->lock);
8332
8333         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8334                 /* All of this garbage is because when using non-tagged
8335                  * IRQ status the mailbox/status_block protocol the chip
8336                  * uses with the cpu is race prone.
8337                  */
8338                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8339                         tw32(GRC_LOCAL_CTRL,
8340                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8341                 } else {
8342                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8343                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8344                 }
8345
8346                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8347                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8348                         spin_unlock(&tp->lock);
8349                         schedule_work(&tp->reset_task);
8350                         return;
8351                 }
8352         }
8353
8354         /* This part only runs once per second. */
8355         if (!--tp->timer_counter) {
8356                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8357                         tg3_periodic_fetch_stats(tp);
8358
8359                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8360                         u32 mac_stat;
8361                         int phy_event;
8362
8363                         mac_stat = tr32(MAC_STATUS);
8364
8365                         phy_event = 0;
8366                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8367                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8368                                         phy_event = 1;
8369                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8370                                 phy_event = 1;
8371
8372                         if (phy_event)
8373                                 tg3_setup_phy(tp, 0);
8374                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8375                         u32 mac_stat = tr32(MAC_STATUS);
8376                         int need_setup = 0;
8377
8378                         if (netif_carrier_ok(tp->dev) &&
8379                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8380                                 need_setup = 1;
8381                         }
8382                         if (! netif_carrier_ok(tp->dev) &&
8383                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8384                                          MAC_STATUS_SIGNAL_DET))) {
8385                                 need_setup = 1;
8386                         }
8387                         if (need_setup) {
8388                                 if (!tp->serdes_counter) {
8389                                         tw32_f(MAC_MODE,
8390                                              (tp->mac_mode &
8391                                               ~MAC_MODE_PORT_MODE_MASK));
8392                                         udelay(40);
8393                                         tw32_f(MAC_MODE, tp->mac_mode);
8394                                         udelay(40);
8395                                 }
8396                                 tg3_setup_phy(tp, 0);
8397                         }
8398                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8399                         tg3_serdes_parallel_detect(tp);
8400
8401                 tp->timer_counter = tp->timer_multiplier;
8402         }
8403
8404         /* Heartbeat is only sent once every 2 seconds.
8405          *
8406          * The heartbeat is to tell the ASF firmware that the host
8407          * driver is still alive.  In the event that the OS crashes,
8408          * ASF needs to reset the hardware to free up the FIFO space
8409          * that may be filled with rx packets destined for the host.
8410          * If the FIFO is full, ASF will no longer function properly.
8411          *
8412          * Unintended resets have been reported on real time kernels
8413          * where the timer doesn't run on time.  Netpoll will also have
8414          * same problem.
8415          *
8416          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8417          * to check the ring condition when the heartbeat is expiring
8418          * before doing the reset.  This will prevent most unintended
8419          * resets.
8420          */
8421         if (!--tp->asf_counter) {
8422                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8423                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8424                         tg3_wait_for_event_ack(tp);
8425
8426                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8427                                       FWCMD_NICDRV_ALIVE3);
8428                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8429                         /* 5 seconds timeout */
8430                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8431
8432                         tg3_generate_fw_event(tp);
8433                 }
8434                 tp->asf_counter = tp->asf_multiplier;
8435         }
8436
8437         spin_unlock(&tp->lock);
8438
8439 restart_timer:
8440         tp->timer.expires = jiffies + tp->timer_offset;
8441         add_timer(&tp->timer);
8442 }
8443
8444 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8445 {
8446         irq_handler_t fn;
8447         unsigned long flags;
8448         char *name;
8449         struct tg3_napi *tnapi = &tp->napi[irq_num];
8450
8451         if (tp->irq_cnt == 1)
8452                 name = tp->dev->name;
8453         else {
8454                 name = &tnapi->irq_lbl[0];
8455                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8456                 name[IFNAMSIZ-1] = 0;
8457         }
8458
8459         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8460                 fn = tg3_msi;
8461                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8462                         fn = tg3_msi_1shot;
8463                 flags = IRQF_SAMPLE_RANDOM;
8464         } else {
8465                 fn = tg3_interrupt;
8466                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8467                         fn = tg3_interrupt_tagged;
8468                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8469         }
8470
8471         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8472 }
8473
8474 static int tg3_test_interrupt(struct tg3 *tp)
8475 {
8476         struct tg3_napi *tnapi = &tp->napi[0];
8477         struct net_device *dev = tp->dev;
8478         int err, i, intr_ok = 0;
8479         u32 val;
8480
8481         if (!netif_running(dev))
8482                 return -ENODEV;
8483
8484         tg3_disable_ints(tp);
8485
8486         free_irq(tnapi->irq_vec, tnapi);
8487
8488         /*
8489          * Turn off MSI one shot mode.  Otherwise this test has no
8490          * observable way to know whether the interrupt was delivered.
8491          */
8492         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8493              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8494             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8495                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8496                 tw32(MSGINT_MODE, val);
8497         }
8498
8499         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8500                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8501         if (err)
8502                 return err;
8503
8504         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8505         tg3_enable_ints(tp);
8506
8507         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8508                tnapi->coal_now);
8509
8510         for (i = 0; i < 5; i++) {
8511                 u32 int_mbox, misc_host_ctrl;
8512
8513                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8514                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8515
8516                 if ((int_mbox != 0) ||
8517                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8518                         intr_ok = 1;
8519                         break;
8520                 }
8521
8522                 msleep(10);
8523         }
8524
8525         tg3_disable_ints(tp);
8526
8527         free_irq(tnapi->irq_vec, tnapi);
8528
8529         err = tg3_request_irq(tp, 0);
8530
8531         if (err)
8532                 return err;
8533
8534         if (intr_ok) {
8535                 /* Reenable MSI one shot mode. */
8536                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8537                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8538                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8539                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8540                         tw32(MSGINT_MODE, val);
8541                 }
8542                 return 0;
8543         }
8544
8545         return -EIO;
8546 }
8547
8548 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8549  * successfully restored
8550  */
8551 static int tg3_test_msi(struct tg3 *tp)
8552 {
8553         int err;
8554         u16 pci_cmd;
8555
8556         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8557                 return 0;
8558
8559         /* Turn off SERR reporting in case MSI terminates with Master
8560          * Abort.
8561          */
8562         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8563         pci_write_config_word(tp->pdev, PCI_COMMAND,
8564                               pci_cmd & ~PCI_COMMAND_SERR);
8565
8566         err = tg3_test_interrupt(tp);
8567
8568         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8569
8570         if (!err)
8571                 return 0;
8572
8573         /* other failures */
8574         if (err != -EIO)
8575                 return err;
8576
8577         /* MSI test failed, go back to INTx mode */
8578         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8579                "switching to INTx mode. Please report this failure to "
8580                "the PCI maintainer and include system chipset information.\n",
8581                        tp->dev->name);
8582
8583         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8584
8585         pci_disable_msi(tp->pdev);
8586
8587         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8588
8589         err = tg3_request_irq(tp, 0);
8590         if (err)
8591                 return err;
8592
8593         /* Need to reset the chip because the MSI cycle may have terminated
8594          * with Master Abort.
8595          */
8596         tg3_full_lock(tp, 1);
8597
8598         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8599         err = tg3_init_hw(tp, 1);
8600
8601         tg3_full_unlock(tp);
8602
8603         if (err)
8604                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8605
8606         return err;
8607 }
8608
8609 static int tg3_request_firmware(struct tg3 *tp)
8610 {
8611         const __be32 *fw_data;
8612
8613         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8614                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8615                        tp->dev->name, tp->fw_needed);
8616                 return -ENOENT;
8617         }
8618
8619         fw_data = (void *)tp->fw->data;
8620
8621         /* Firmware blob starts with version numbers, followed by
8622          * start address and _full_ length including BSS sections
8623          * (which must be longer than the actual data, of course
8624          */
8625
8626         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8627         if (tp->fw_len < (tp->fw->size - 12)) {
8628                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8629                        tp->dev->name, tp->fw_len, tp->fw_needed);
8630                 release_firmware(tp->fw);
8631                 tp->fw = NULL;
8632                 return -EINVAL;
8633         }
8634
8635         /* We no longer need firmware; we have it. */
8636         tp->fw_needed = NULL;
8637         return 0;
8638 }
8639
8640 static bool tg3_enable_msix(struct tg3 *tp)
8641 {
8642         int i, rc, cpus = num_online_cpus();
8643         struct msix_entry msix_ent[tp->irq_max];
8644
8645         if (cpus == 1)
8646                 /* Just fallback to the simpler MSI mode. */
8647                 return false;
8648
8649         /*
8650          * We want as many rx rings enabled as there are cpus.
8651          * The first MSIX vector only deals with link interrupts, etc,
8652          * so we add one to the number of vectors we are requesting.
8653          */
8654         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8655
8656         for (i = 0; i < tp->irq_max; i++) {
8657                 msix_ent[i].entry  = i;
8658                 msix_ent[i].vector = 0;
8659         }
8660
8661         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8662         if (rc != 0) {
8663                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8664                         return false;
8665                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8666                         return false;
8667                 printk(KERN_NOTICE
8668                        "%s: Requested %d MSI-X vectors, received %d\n",
8669                        tp->dev->name, tp->irq_cnt, rc);
8670                 tp->irq_cnt = rc;
8671         }
8672
8673         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8674
8675         for (i = 0; i < tp->irq_max; i++)
8676                 tp->napi[i].irq_vec = msix_ent[i].vector;
8677
8678         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8679                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8680                 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8681         } else
8682                 tp->dev->real_num_tx_queues = 1;
8683
8684         return true;
8685 }
8686
8687 static void tg3_ints_init(struct tg3 *tp)
8688 {
8689         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8690             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8691                 /* All MSI supporting chips should support tagged
8692                  * status.  Assert that this is the case.
8693                  */
8694                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8695                        "Not using MSI.\n", tp->dev->name);
8696                 goto defcfg;
8697         }
8698
8699         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8700                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8701         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8702                  pci_enable_msi(tp->pdev) == 0)
8703                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8704
8705         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8706                 u32 msi_mode = tr32(MSGINT_MODE);
8707                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8708                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8709                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8710         }
8711 defcfg:
8712         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8713                 tp->irq_cnt = 1;
8714                 tp->napi[0].irq_vec = tp->pdev->irq;
8715                 tp->dev->real_num_tx_queues = 1;
8716         }
8717 }
8718
8719 static void tg3_ints_fini(struct tg3 *tp)
8720 {
8721         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8722                 pci_disable_msix(tp->pdev);
8723         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8724                 pci_disable_msi(tp->pdev);
8725         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8726         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8727 }
8728
8729 static int tg3_open(struct net_device *dev)
8730 {
8731         struct tg3 *tp = netdev_priv(dev);
8732         int i, err;
8733
8734         if (tp->fw_needed) {
8735                 err = tg3_request_firmware(tp);
8736                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8737                         if (err)
8738                                 return err;
8739                 } else if (err) {
8740                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8741                                tp->dev->name);
8742                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8743                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8744                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8745                                tp->dev->name);
8746                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8747                 }
8748         }
8749
8750         netif_carrier_off(tp->dev);
8751
8752         err = tg3_set_power_state(tp, PCI_D0);
8753         if (err)
8754                 return err;
8755
8756         tg3_full_lock(tp, 0);
8757
8758         tg3_disable_ints(tp);
8759         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8760
8761         tg3_full_unlock(tp);
8762
8763         /*
8764          * Setup interrupts first so we know how
8765          * many NAPI resources to allocate
8766          */
8767         tg3_ints_init(tp);
8768
8769         /* The placement of this call is tied
8770          * to the setup and use of Host TX descriptors.
8771          */
8772         err = tg3_alloc_consistent(tp);
8773         if (err)
8774                 goto err_out1;
8775
8776         tg3_napi_enable(tp);
8777
8778         for (i = 0; i < tp->irq_cnt; i++) {
8779                 struct tg3_napi *tnapi = &tp->napi[i];
8780                 err = tg3_request_irq(tp, i);
8781                 if (err) {
8782                         for (i--; i >= 0; i--)
8783                                 free_irq(tnapi->irq_vec, tnapi);
8784                         break;
8785                 }
8786         }
8787
8788         if (err)
8789                 goto err_out2;
8790
8791         tg3_full_lock(tp, 0);
8792
8793         err = tg3_init_hw(tp, 1);
8794         if (err) {
8795                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8796                 tg3_free_rings(tp);
8797         } else {
8798                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8799                         tp->timer_offset = HZ;
8800                 else
8801                         tp->timer_offset = HZ / 10;
8802
8803                 BUG_ON(tp->timer_offset > HZ);
8804                 tp->timer_counter = tp->timer_multiplier =
8805                         (HZ / tp->timer_offset);
8806                 tp->asf_counter = tp->asf_multiplier =
8807                         ((HZ / tp->timer_offset) * 2);
8808
8809                 init_timer(&tp->timer);
8810                 tp->timer.expires = jiffies + tp->timer_offset;
8811                 tp->timer.data = (unsigned long) tp;
8812                 tp->timer.function = tg3_timer;
8813         }
8814
8815         tg3_full_unlock(tp);
8816
8817         if (err)
8818                 goto err_out3;
8819
8820         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8821                 err = tg3_test_msi(tp);
8822
8823                 if (err) {
8824                         tg3_full_lock(tp, 0);
8825                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8826                         tg3_free_rings(tp);
8827                         tg3_full_unlock(tp);
8828
8829                         goto err_out2;
8830                 }
8831
8832                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8833                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8834                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8835                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8836                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8837
8838                         tw32(PCIE_TRANSACTION_CFG,
8839                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8840                 }
8841         }
8842
8843         tg3_phy_start(tp);
8844
8845         tg3_full_lock(tp, 0);
8846
8847         add_timer(&tp->timer);
8848         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8849         tg3_enable_ints(tp);
8850
8851         tg3_full_unlock(tp);
8852
8853         netif_tx_start_all_queues(dev);
8854
8855         return 0;
8856
8857 err_out3:
8858         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8859                 struct tg3_napi *tnapi = &tp->napi[i];
8860                 free_irq(tnapi->irq_vec, tnapi);
8861         }
8862
8863 err_out2:
8864         tg3_napi_disable(tp);
8865         tg3_free_consistent(tp);
8866
8867 err_out1:
8868         tg3_ints_fini(tp);
8869         return err;
8870 }
8871
8872 #if 0
8873 /*static*/ void tg3_dump_state(struct tg3 *tp)
8874 {
8875         u32 val32, val32_2, val32_3, val32_4, val32_5;
8876         u16 val16;
8877         int i;
8878         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8879
8880         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8881         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8882         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8883                val16, val32);
8884
8885         /* MAC block */
8886         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8887                tr32(MAC_MODE), tr32(MAC_STATUS));
8888         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8889                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8890         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8891                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8892         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8893                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8894
8895         /* Send data initiator control block */
8896         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8897                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8898         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8899                tr32(SNDDATAI_STATSCTRL));
8900
8901         /* Send data completion control block */
8902         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8903
8904         /* Send BD ring selector block */
8905         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8906                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8907
8908         /* Send BD initiator control block */
8909         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8910                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8911
8912         /* Send BD completion control block */
8913         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8914
8915         /* Receive list placement control block */
8916         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8917                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8918         printk("       RCVLPC_STATSCTRL[%08x]\n",
8919                tr32(RCVLPC_STATSCTRL));
8920
8921         /* Receive data and receive BD initiator control block */
8922         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8923                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8924
8925         /* Receive data completion control block */
8926         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8927                tr32(RCVDCC_MODE));
8928
8929         /* Receive BD initiator control block */
8930         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8931                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8932
8933         /* Receive BD completion control block */
8934         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8935                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8936
8937         /* Receive list selector control block */
8938         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8939                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8940
8941         /* Mbuf cluster free block */
8942         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8943                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8944
8945         /* Host coalescing control block */
8946         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8947                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8948         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8949                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8950                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8951         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8952                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8953                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8954         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8955                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8956         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8957                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8958
8959         /* Memory arbiter control block */
8960         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8961                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8962
8963         /* Buffer manager control block */
8964         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8965                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8966         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8967                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8968         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8969                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8970                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8971                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8972
8973         /* Read DMA control block */
8974         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8975                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8976
8977         /* Write DMA control block */
8978         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8979                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8980
8981         /* DMA completion block */
8982         printk("DEBUG: DMAC_MODE[%08x]\n",
8983                tr32(DMAC_MODE));
8984
8985         /* GRC block */
8986         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8987                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8988         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8989                tr32(GRC_LOCAL_CTRL));
8990
8991         /* TG3_BDINFOs */
8992         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8993                tr32(RCVDBDI_JUMBO_BD + 0x0),
8994                tr32(RCVDBDI_JUMBO_BD + 0x4),
8995                tr32(RCVDBDI_JUMBO_BD + 0x8),
8996                tr32(RCVDBDI_JUMBO_BD + 0xc));
8997         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8998                tr32(RCVDBDI_STD_BD + 0x0),
8999                tr32(RCVDBDI_STD_BD + 0x4),
9000                tr32(RCVDBDI_STD_BD + 0x8),
9001                tr32(RCVDBDI_STD_BD + 0xc));
9002         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9003                tr32(RCVDBDI_MINI_BD + 0x0),
9004                tr32(RCVDBDI_MINI_BD + 0x4),
9005                tr32(RCVDBDI_MINI_BD + 0x8),
9006                tr32(RCVDBDI_MINI_BD + 0xc));
9007
9008         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9009         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9010         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9011         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9012         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9013                val32, val32_2, val32_3, val32_4);
9014
9015         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9016         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9017         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9018         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9019         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9020                val32, val32_2, val32_3, val32_4);
9021
9022         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9023         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9024         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9025         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9026         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9027         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9028                val32, val32_2, val32_3, val32_4, val32_5);
9029
9030         /* SW status block */
9031         printk(KERN_DEBUG
9032          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9033                sblk->status,
9034                sblk->status_tag,
9035                sblk->rx_jumbo_consumer,
9036                sblk->rx_consumer,
9037                sblk->rx_mini_consumer,
9038                sblk->idx[0].rx_producer,
9039                sblk->idx[0].tx_consumer);
9040
9041         /* SW statistics block */
9042         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9043                ((u32 *)tp->hw_stats)[0],
9044                ((u32 *)tp->hw_stats)[1],
9045                ((u32 *)tp->hw_stats)[2],
9046                ((u32 *)tp->hw_stats)[3]);
9047
9048         /* Mailboxes */
9049         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9050                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9051                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9052                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9053                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9054
9055         /* NIC side send descriptors. */
9056         for (i = 0; i < 6; i++) {
9057                 unsigned long txd;
9058
9059                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9060                         + (i * sizeof(struct tg3_tx_buffer_desc));
9061                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9062                        i,
9063                        readl(txd + 0x0), readl(txd + 0x4),
9064                        readl(txd + 0x8), readl(txd + 0xc));
9065         }
9066
9067         /* NIC side RX descriptors. */
9068         for (i = 0; i < 6; i++) {
9069                 unsigned long rxd;
9070
9071                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9072                         + (i * sizeof(struct tg3_rx_buffer_desc));
9073                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9074                        i,
9075                        readl(rxd + 0x0), readl(rxd + 0x4),
9076                        readl(rxd + 0x8), readl(rxd + 0xc));
9077                 rxd += (4 * sizeof(u32));
9078                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9079                        i,
9080                        readl(rxd + 0x0), readl(rxd + 0x4),
9081                        readl(rxd + 0x8), readl(rxd + 0xc));
9082         }
9083
9084         for (i = 0; i < 6; i++) {
9085                 unsigned long rxd;
9086
9087                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9088                         + (i * sizeof(struct tg3_rx_buffer_desc));
9089                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9090                        i,
9091                        readl(rxd + 0x0), readl(rxd + 0x4),
9092                        readl(rxd + 0x8), readl(rxd + 0xc));
9093                 rxd += (4 * sizeof(u32));
9094                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9095                        i,
9096                        readl(rxd + 0x0), readl(rxd + 0x4),
9097                        readl(rxd + 0x8), readl(rxd + 0xc));
9098         }
9099 }
9100 #endif
9101
9102 static struct net_device_stats *tg3_get_stats(struct net_device *);
9103 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9104
9105 static int tg3_close(struct net_device *dev)
9106 {
9107         int i;
9108         struct tg3 *tp = netdev_priv(dev);
9109
9110         tg3_napi_disable(tp);
9111         cancel_work_sync(&tp->reset_task);
9112
9113         netif_tx_stop_all_queues(dev);
9114
9115         del_timer_sync(&tp->timer);
9116
9117         tg3_phy_stop(tp);
9118
9119         tg3_full_lock(tp, 1);
9120 #if 0
9121         tg3_dump_state(tp);
9122 #endif
9123
9124         tg3_disable_ints(tp);
9125
9126         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9127         tg3_free_rings(tp);
9128         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9129
9130         tg3_full_unlock(tp);
9131
9132         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9133                 struct tg3_napi *tnapi = &tp->napi[i];
9134                 free_irq(tnapi->irq_vec, tnapi);
9135         }
9136
9137         tg3_ints_fini(tp);
9138
9139         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9140                sizeof(tp->net_stats_prev));
9141         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9142                sizeof(tp->estats_prev));
9143
9144         tg3_free_consistent(tp);
9145
9146         tg3_set_power_state(tp, PCI_D3hot);
9147
9148         netif_carrier_off(tp->dev);
9149
9150         return 0;
9151 }
9152
9153 static inline unsigned long get_stat64(tg3_stat64_t *val)
9154 {
9155         unsigned long ret;
9156
9157 #if (BITS_PER_LONG == 32)
9158         ret = val->low;
9159 #else
9160         ret = ((u64)val->high << 32) | ((u64)val->low);
9161 #endif
9162         return ret;
9163 }
9164
9165 static inline u64 get_estat64(tg3_stat64_t *val)
9166 {
9167        return ((u64)val->high << 32) | ((u64)val->low);
9168 }
9169
9170 static unsigned long calc_crc_errors(struct tg3 *tp)
9171 {
9172         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9173
9174         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9175             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9176              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9177                 u32 val;
9178
9179                 spin_lock_bh(&tp->lock);
9180                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9181                         tg3_writephy(tp, MII_TG3_TEST1,
9182                                      val | MII_TG3_TEST1_CRC_EN);
9183                         tg3_readphy(tp, 0x14, &val);
9184                 } else
9185                         val = 0;
9186                 spin_unlock_bh(&tp->lock);
9187
9188                 tp->phy_crc_errors += val;
9189
9190                 return tp->phy_crc_errors;
9191         }
9192
9193         return get_stat64(&hw_stats->rx_fcs_errors);
9194 }
9195
9196 #define ESTAT_ADD(member) \
9197         estats->member =        old_estats->member + \
9198                                 get_estat64(&hw_stats->member)
9199
9200 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9201 {
9202         struct tg3_ethtool_stats *estats = &tp->estats;
9203         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9204         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9205
9206         if (!hw_stats)
9207                 return old_estats;
9208
9209         ESTAT_ADD(rx_octets);
9210         ESTAT_ADD(rx_fragments);
9211         ESTAT_ADD(rx_ucast_packets);
9212         ESTAT_ADD(rx_mcast_packets);
9213         ESTAT_ADD(rx_bcast_packets);
9214         ESTAT_ADD(rx_fcs_errors);
9215         ESTAT_ADD(rx_align_errors);
9216         ESTAT_ADD(rx_xon_pause_rcvd);
9217         ESTAT_ADD(rx_xoff_pause_rcvd);
9218         ESTAT_ADD(rx_mac_ctrl_rcvd);
9219         ESTAT_ADD(rx_xoff_entered);
9220         ESTAT_ADD(rx_frame_too_long_errors);
9221         ESTAT_ADD(rx_jabbers);
9222         ESTAT_ADD(rx_undersize_packets);
9223         ESTAT_ADD(rx_in_length_errors);
9224         ESTAT_ADD(rx_out_length_errors);
9225         ESTAT_ADD(rx_64_or_less_octet_packets);
9226         ESTAT_ADD(rx_65_to_127_octet_packets);
9227         ESTAT_ADD(rx_128_to_255_octet_packets);
9228         ESTAT_ADD(rx_256_to_511_octet_packets);
9229         ESTAT_ADD(rx_512_to_1023_octet_packets);
9230         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9231         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9232         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9233         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9234         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9235
9236         ESTAT_ADD(tx_octets);
9237         ESTAT_ADD(tx_collisions);
9238         ESTAT_ADD(tx_xon_sent);
9239         ESTAT_ADD(tx_xoff_sent);
9240         ESTAT_ADD(tx_flow_control);
9241         ESTAT_ADD(tx_mac_errors);
9242         ESTAT_ADD(tx_single_collisions);
9243         ESTAT_ADD(tx_mult_collisions);
9244         ESTAT_ADD(tx_deferred);
9245         ESTAT_ADD(tx_excessive_collisions);
9246         ESTAT_ADD(tx_late_collisions);
9247         ESTAT_ADD(tx_collide_2times);
9248         ESTAT_ADD(tx_collide_3times);
9249         ESTAT_ADD(tx_collide_4times);
9250         ESTAT_ADD(tx_collide_5times);
9251         ESTAT_ADD(tx_collide_6times);
9252         ESTAT_ADD(tx_collide_7times);
9253         ESTAT_ADD(tx_collide_8times);
9254         ESTAT_ADD(tx_collide_9times);
9255         ESTAT_ADD(tx_collide_10times);
9256         ESTAT_ADD(tx_collide_11times);
9257         ESTAT_ADD(tx_collide_12times);
9258         ESTAT_ADD(tx_collide_13times);
9259         ESTAT_ADD(tx_collide_14times);
9260         ESTAT_ADD(tx_collide_15times);
9261         ESTAT_ADD(tx_ucast_packets);
9262         ESTAT_ADD(tx_mcast_packets);
9263         ESTAT_ADD(tx_bcast_packets);
9264         ESTAT_ADD(tx_carrier_sense_errors);
9265         ESTAT_ADD(tx_discards);
9266         ESTAT_ADD(tx_errors);
9267
9268         ESTAT_ADD(dma_writeq_full);
9269         ESTAT_ADD(dma_write_prioq_full);
9270         ESTAT_ADD(rxbds_empty);
9271         ESTAT_ADD(rx_discards);
9272         ESTAT_ADD(rx_errors);
9273         ESTAT_ADD(rx_threshold_hit);
9274
9275         ESTAT_ADD(dma_readq_full);
9276         ESTAT_ADD(dma_read_prioq_full);
9277         ESTAT_ADD(tx_comp_queue_full);
9278
9279         ESTAT_ADD(ring_set_send_prod_index);
9280         ESTAT_ADD(ring_status_update);
9281         ESTAT_ADD(nic_irqs);
9282         ESTAT_ADD(nic_avoided_irqs);
9283         ESTAT_ADD(nic_tx_threshold_hit);
9284
9285         return estats;
9286 }
9287
9288 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9289 {
9290         struct tg3 *tp = netdev_priv(dev);
9291         struct net_device_stats *stats = &tp->net_stats;
9292         struct net_device_stats *old_stats = &tp->net_stats_prev;
9293         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9294
9295         if (!hw_stats)
9296                 return old_stats;
9297
9298         stats->rx_packets = old_stats->rx_packets +
9299                 get_stat64(&hw_stats->rx_ucast_packets) +
9300                 get_stat64(&hw_stats->rx_mcast_packets) +
9301                 get_stat64(&hw_stats->rx_bcast_packets);
9302
9303         stats->tx_packets = old_stats->tx_packets +
9304                 get_stat64(&hw_stats->tx_ucast_packets) +
9305                 get_stat64(&hw_stats->tx_mcast_packets) +
9306                 get_stat64(&hw_stats->tx_bcast_packets);
9307
9308         stats->rx_bytes = old_stats->rx_bytes +
9309                 get_stat64(&hw_stats->rx_octets);
9310         stats->tx_bytes = old_stats->tx_bytes +
9311                 get_stat64(&hw_stats->tx_octets);
9312
9313         stats->rx_errors = old_stats->rx_errors +
9314                 get_stat64(&hw_stats->rx_errors);
9315         stats->tx_errors = old_stats->tx_errors +
9316                 get_stat64(&hw_stats->tx_errors) +
9317                 get_stat64(&hw_stats->tx_mac_errors) +
9318                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9319                 get_stat64(&hw_stats->tx_discards);
9320
9321         stats->multicast = old_stats->multicast +
9322                 get_stat64(&hw_stats->rx_mcast_packets);
9323         stats->collisions = old_stats->collisions +
9324                 get_stat64(&hw_stats->tx_collisions);
9325
9326         stats->rx_length_errors = old_stats->rx_length_errors +
9327                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9328                 get_stat64(&hw_stats->rx_undersize_packets);
9329
9330         stats->rx_over_errors = old_stats->rx_over_errors +
9331                 get_stat64(&hw_stats->rxbds_empty);
9332         stats->rx_frame_errors = old_stats->rx_frame_errors +
9333                 get_stat64(&hw_stats->rx_align_errors);
9334         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9335                 get_stat64(&hw_stats->tx_discards);
9336         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9337                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9338
9339         stats->rx_crc_errors = old_stats->rx_crc_errors +
9340                 calc_crc_errors(tp);
9341
9342         stats->rx_missed_errors = old_stats->rx_missed_errors +
9343                 get_stat64(&hw_stats->rx_discards);
9344
9345         return stats;
9346 }
9347
9348 static inline u32 calc_crc(unsigned char *buf, int len)
9349 {
9350         u32 reg;
9351         u32 tmp;
9352         int j, k;
9353
9354         reg = 0xffffffff;
9355
9356         for (j = 0; j < len; j++) {
9357                 reg ^= buf[j];
9358
9359                 for (k = 0; k < 8; k++) {
9360                         tmp = reg & 0x01;
9361
9362                         reg >>= 1;
9363
9364                         if (tmp) {
9365                                 reg ^= 0xedb88320;
9366                         }
9367                 }
9368         }
9369
9370         return ~reg;
9371 }
9372
9373 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9374 {
9375         /* accept or reject all multicast frames */
9376         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9377         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9378         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9379         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9380 }
9381
9382 static void __tg3_set_rx_mode(struct net_device *dev)
9383 {
9384         struct tg3 *tp = netdev_priv(dev);
9385         u32 rx_mode;
9386
9387         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9388                                   RX_MODE_KEEP_VLAN_TAG);
9389
9390         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9391          * flag clear.
9392          */
9393 #if TG3_VLAN_TAG_USED
9394         if (!tp->vlgrp &&
9395             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9396                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9397 #else
9398         /* By definition, VLAN is disabled always in this
9399          * case.
9400          */
9401         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9402                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9403 #endif
9404
9405         if (dev->flags & IFF_PROMISC) {
9406                 /* Promiscuous mode. */
9407                 rx_mode |= RX_MODE_PROMISC;
9408         } else if (dev->flags & IFF_ALLMULTI) {
9409                 /* Accept all multicast. */
9410                 tg3_set_multi (tp, 1);
9411         } else if (dev->mc_count < 1) {
9412                 /* Reject all multicast. */
9413                 tg3_set_multi (tp, 0);
9414         } else {
9415                 /* Accept one or more multicast(s). */
9416                 struct dev_mc_list *mclist;
9417                 unsigned int i;
9418                 u32 mc_filter[4] = { 0, };
9419                 u32 regidx;
9420                 u32 bit;
9421                 u32 crc;
9422
9423                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9424                      i++, mclist = mclist->next) {
9425
9426                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9427                         bit = ~crc & 0x7f;
9428                         regidx = (bit & 0x60) >> 5;
9429                         bit &= 0x1f;
9430                         mc_filter[regidx] |= (1 << bit);
9431                 }
9432
9433                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9434                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9435                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9436                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9437         }
9438
9439         if (rx_mode != tp->rx_mode) {
9440                 tp->rx_mode = rx_mode;
9441                 tw32_f(MAC_RX_MODE, rx_mode);
9442                 udelay(10);
9443         }
9444 }
9445
9446 static void tg3_set_rx_mode(struct net_device *dev)
9447 {
9448         struct tg3 *tp = netdev_priv(dev);
9449
9450         if (!netif_running(dev))
9451                 return;
9452
9453         tg3_full_lock(tp, 0);
9454         __tg3_set_rx_mode(dev);
9455         tg3_full_unlock(tp);
9456 }
9457
9458 #define TG3_REGDUMP_LEN         (32 * 1024)
9459
9460 static int tg3_get_regs_len(struct net_device *dev)
9461 {
9462         return TG3_REGDUMP_LEN;
9463 }
9464
9465 static void tg3_get_regs(struct net_device *dev,
9466                 struct ethtool_regs *regs, void *_p)
9467 {
9468         u32 *p = _p;
9469         struct tg3 *tp = netdev_priv(dev);
9470         u8 *orig_p = _p;
9471         int i;
9472
9473         regs->version = 0;
9474
9475         memset(p, 0, TG3_REGDUMP_LEN);
9476
9477         if (tp->link_config.phy_is_low_power)
9478                 return;
9479
9480         tg3_full_lock(tp, 0);
9481
9482 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9483 #define GET_REG32_LOOP(base,len)                \
9484 do {    p = (u32 *)(orig_p + (base));           \
9485         for (i = 0; i < len; i += 4)            \
9486                 __GET_REG32((base) + i);        \
9487 } while (0)
9488 #define GET_REG32_1(reg)                        \
9489 do {    p = (u32 *)(orig_p + (reg));            \
9490         __GET_REG32((reg));                     \
9491 } while (0)
9492
9493         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9494         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9495         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9496         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9497         GET_REG32_1(SNDDATAC_MODE);
9498         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9499         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9500         GET_REG32_1(SNDBDC_MODE);
9501         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9502         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9503         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9504         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9505         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9506         GET_REG32_1(RCVDCC_MODE);
9507         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9508         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9509         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9510         GET_REG32_1(MBFREE_MODE);
9511         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9512         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9513         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9514         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9515         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9516         GET_REG32_1(RX_CPU_MODE);
9517         GET_REG32_1(RX_CPU_STATE);
9518         GET_REG32_1(RX_CPU_PGMCTR);
9519         GET_REG32_1(RX_CPU_HWBKPT);
9520         GET_REG32_1(TX_CPU_MODE);
9521         GET_REG32_1(TX_CPU_STATE);
9522         GET_REG32_1(TX_CPU_PGMCTR);
9523         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9524         GET_REG32_LOOP(FTQ_RESET, 0x120);
9525         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9526         GET_REG32_1(DMAC_MODE);
9527         GET_REG32_LOOP(GRC_MODE, 0x4c);
9528         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9529                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9530
9531 #undef __GET_REG32
9532 #undef GET_REG32_LOOP
9533 #undef GET_REG32_1
9534
9535         tg3_full_unlock(tp);
9536 }
9537
9538 static int tg3_get_eeprom_len(struct net_device *dev)
9539 {
9540         struct tg3 *tp = netdev_priv(dev);
9541
9542         return tp->nvram_size;
9543 }
9544
9545 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9546 {
9547         struct tg3 *tp = netdev_priv(dev);
9548         int ret;
9549         u8  *pd;
9550         u32 i, offset, len, b_offset, b_count;
9551         __be32 val;
9552
9553         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9554                 return -EINVAL;
9555
9556         if (tp->link_config.phy_is_low_power)
9557                 return -EAGAIN;
9558
9559         offset = eeprom->offset;
9560         len = eeprom->len;
9561         eeprom->len = 0;
9562
9563         eeprom->magic = TG3_EEPROM_MAGIC;
9564
9565         if (offset & 3) {
9566                 /* adjustments to start on required 4 byte boundary */
9567                 b_offset = offset & 3;
9568                 b_count = 4 - b_offset;
9569                 if (b_count > len) {
9570                         /* i.e. offset=1 len=2 */
9571                         b_count = len;
9572                 }
9573                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9574                 if (ret)
9575                         return ret;
9576                 memcpy(data, ((char*)&val) + b_offset, b_count);
9577                 len -= b_count;
9578                 offset += b_count;
9579                 eeprom->len += b_count;
9580         }
9581
9582         /* read bytes upto the last 4 byte boundary */
9583         pd = &data[eeprom->len];
9584         for (i = 0; i < (len - (len & 3)); i += 4) {
9585                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9586                 if (ret) {
9587                         eeprom->len += i;
9588                         return ret;
9589                 }
9590                 memcpy(pd + i, &val, 4);
9591         }
9592         eeprom->len += i;
9593
9594         if (len & 3) {
9595                 /* read last bytes not ending on 4 byte boundary */
9596                 pd = &data[eeprom->len];
9597                 b_count = len & 3;
9598                 b_offset = offset + len - b_count;
9599                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9600                 if (ret)
9601                         return ret;
9602                 memcpy(pd, &val, b_count);
9603                 eeprom->len += b_count;
9604         }
9605         return 0;
9606 }
9607
9608 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9609
9610 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9611 {
9612         struct tg3 *tp = netdev_priv(dev);
9613         int ret;
9614         u32 offset, len, b_offset, odd_len;
9615         u8 *buf;
9616         __be32 start, end;
9617
9618         if (tp->link_config.phy_is_low_power)
9619                 return -EAGAIN;
9620
9621         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9622             eeprom->magic != TG3_EEPROM_MAGIC)
9623                 return -EINVAL;
9624
9625         offset = eeprom->offset;
9626         len = eeprom->len;
9627
9628         if ((b_offset = (offset & 3))) {
9629                 /* adjustments to start on required 4 byte boundary */
9630                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9631                 if (ret)
9632                         return ret;
9633                 len += b_offset;
9634                 offset &= ~3;
9635                 if (len < 4)
9636                         len = 4;
9637         }
9638
9639         odd_len = 0;
9640         if (len & 3) {
9641                 /* adjustments to end on required 4 byte boundary */
9642                 odd_len = 1;
9643                 len = (len + 3) & ~3;
9644                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9645                 if (ret)
9646                         return ret;
9647         }
9648
9649         buf = data;
9650         if (b_offset || odd_len) {
9651                 buf = kmalloc(len, GFP_KERNEL);
9652                 if (!buf)
9653                         return -ENOMEM;
9654                 if (b_offset)
9655                         memcpy(buf, &start, 4);
9656                 if (odd_len)
9657                         memcpy(buf+len-4, &end, 4);
9658                 memcpy(buf + b_offset, data, eeprom->len);
9659         }
9660
9661         ret = tg3_nvram_write_block(tp, offset, len, buf);
9662
9663         if (buf != data)
9664                 kfree(buf);
9665
9666         return ret;
9667 }
9668
9669 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9670 {
9671         struct tg3 *tp = netdev_priv(dev);
9672
9673         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9674                 struct phy_device *phydev;
9675                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9676                         return -EAGAIN;
9677                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9678                 return phy_ethtool_gset(phydev, cmd);
9679         }
9680
9681         cmd->supported = (SUPPORTED_Autoneg);
9682
9683         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9684                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9685                                    SUPPORTED_1000baseT_Full);
9686
9687         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9688                 cmd->supported |= (SUPPORTED_100baseT_Half |
9689                                   SUPPORTED_100baseT_Full |
9690                                   SUPPORTED_10baseT_Half |
9691                                   SUPPORTED_10baseT_Full |
9692                                   SUPPORTED_TP);
9693                 cmd->port = PORT_TP;
9694         } else {
9695                 cmd->supported |= SUPPORTED_FIBRE;
9696                 cmd->port = PORT_FIBRE;
9697         }
9698
9699         cmd->advertising = tp->link_config.advertising;
9700         if (netif_running(dev)) {
9701                 cmd->speed = tp->link_config.active_speed;
9702                 cmd->duplex = tp->link_config.active_duplex;
9703         }
9704         cmd->phy_address = tp->phy_addr;
9705         cmd->transceiver = XCVR_INTERNAL;
9706         cmd->autoneg = tp->link_config.autoneg;
9707         cmd->maxtxpkt = 0;
9708         cmd->maxrxpkt = 0;
9709         return 0;
9710 }
9711
9712 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9713 {
9714         struct tg3 *tp = netdev_priv(dev);
9715
9716         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9717                 struct phy_device *phydev;
9718                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9719                         return -EAGAIN;
9720                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9721                 return phy_ethtool_sset(phydev, cmd);
9722         }
9723
9724         if (cmd->autoneg != AUTONEG_ENABLE &&
9725             cmd->autoneg != AUTONEG_DISABLE)
9726                 return -EINVAL;
9727
9728         if (cmd->autoneg == AUTONEG_DISABLE &&
9729             cmd->duplex != DUPLEX_FULL &&
9730             cmd->duplex != DUPLEX_HALF)
9731                 return -EINVAL;
9732
9733         if (cmd->autoneg == AUTONEG_ENABLE) {
9734                 u32 mask = ADVERTISED_Autoneg |
9735                            ADVERTISED_Pause |
9736                            ADVERTISED_Asym_Pause;
9737
9738                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9739                         mask |= ADVERTISED_1000baseT_Half |
9740                                 ADVERTISED_1000baseT_Full;
9741
9742                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9743                         mask |= ADVERTISED_100baseT_Half |
9744                                 ADVERTISED_100baseT_Full |
9745                                 ADVERTISED_10baseT_Half |
9746                                 ADVERTISED_10baseT_Full |
9747                                 ADVERTISED_TP;
9748                 else
9749                         mask |= ADVERTISED_FIBRE;
9750
9751                 if (cmd->advertising & ~mask)
9752                         return -EINVAL;
9753
9754                 mask &= (ADVERTISED_1000baseT_Half |
9755                          ADVERTISED_1000baseT_Full |
9756                          ADVERTISED_100baseT_Half |
9757                          ADVERTISED_100baseT_Full |
9758                          ADVERTISED_10baseT_Half |
9759                          ADVERTISED_10baseT_Full);
9760
9761                 cmd->advertising &= mask;
9762         } else {
9763                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9764                         if (cmd->speed != SPEED_1000)
9765                                 return -EINVAL;
9766
9767                         if (cmd->duplex != DUPLEX_FULL)
9768                                 return -EINVAL;
9769                 } else {
9770                         if (cmd->speed != SPEED_100 &&
9771                             cmd->speed != SPEED_10)
9772                                 return -EINVAL;
9773                 }
9774         }
9775
9776         tg3_full_lock(tp, 0);
9777
9778         tp->link_config.autoneg = cmd->autoneg;
9779         if (cmd->autoneg == AUTONEG_ENABLE) {
9780                 tp->link_config.advertising = (cmd->advertising |
9781                                               ADVERTISED_Autoneg);
9782                 tp->link_config.speed = SPEED_INVALID;
9783                 tp->link_config.duplex = DUPLEX_INVALID;
9784         } else {
9785                 tp->link_config.advertising = 0;
9786                 tp->link_config.speed = cmd->speed;
9787                 tp->link_config.duplex = cmd->duplex;
9788         }
9789
9790         tp->link_config.orig_speed = tp->link_config.speed;
9791         tp->link_config.orig_duplex = tp->link_config.duplex;
9792         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9793
9794         if (netif_running(dev))
9795                 tg3_setup_phy(tp, 1);
9796
9797         tg3_full_unlock(tp);
9798
9799         return 0;
9800 }
9801
9802 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9803 {
9804         struct tg3 *tp = netdev_priv(dev);
9805
9806         strcpy(info->driver, DRV_MODULE_NAME);
9807         strcpy(info->version, DRV_MODULE_VERSION);
9808         strcpy(info->fw_version, tp->fw_ver);
9809         strcpy(info->bus_info, pci_name(tp->pdev));
9810 }
9811
9812 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9813 {
9814         struct tg3 *tp = netdev_priv(dev);
9815
9816         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9817             device_can_wakeup(&tp->pdev->dev))
9818                 wol->supported = WAKE_MAGIC;
9819         else
9820                 wol->supported = 0;
9821         wol->wolopts = 0;
9822         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9823             device_can_wakeup(&tp->pdev->dev))
9824                 wol->wolopts = WAKE_MAGIC;
9825         memset(&wol->sopass, 0, sizeof(wol->sopass));
9826 }
9827
9828 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9829 {
9830         struct tg3 *tp = netdev_priv(dev);
9831         struct device *dp = &tp->pdev->dev;
9832
9833         if (wol->wolopts & ~WAKE_MAGIC)
9834                 return -EINVAL;
9835         if ((wol->wolopts & WAKE_MAGIC) &&
9836             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9837                 return -EINVAL;
9838
9839         spin_lock_bh(&tp->lock);
9840         if (wol->wolopts & WAKE_MAGIC) {
9841                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9842                 device_set_wakeup_enable(dp, true);
9843         } else {
9844                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9845                 device_set_wakeup_enable(dp, false);
9846         }
9847         spin_unlock_bh(&tp->lock);
9848
9849         return 0;
9850 }
9851
9852 static u32 tg3_get_msglevel(struct net_device *dev)
9853 {
9854         struct tg3 *tp = netdev_priv(dev);
9855         return tp->msg_enable;
9856 }
9857
9858 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9859 {
9860         struct tg3 *tp = netdev_priv(dev);
9861         tp->msg_enable = value;
9862 }
9863
9864 static int tg3_set_tso(struct net_device *dev, u32 value)
9865 {
9866         struct tg3 *tp = netdev_priv(dev);
9867
9868         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9869                 if (value)
9870                         return -EINVAL;
9871                 return 0;
9872         }
9873         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9874             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9875              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9876                 if (value) {
9877                         dev->features |= NETIF_F_TSO6;
9878                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9879                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9880                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9881                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9882                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9883                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9884                                 dev->features |= NETIF_F_TSO_ECN;
9885                 } else
9886                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9887         }
9888         return ethtool_op_set_tso(dev, value);
9889 }
9890
9891 static int tg3_nway_reset(struct net_device *dev)
9892 {
9893         struct tg3 *tp = netdev_priv(dev);
9894         int r;
9895
9896         if (!netif_running(dev))
9897                 return -EAGAIN;
9898
9899         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9900                 return -EINVAL;
9901
9902         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9903                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9904                         return -EAGAIN;
9905                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9906         } else {
9907                 u32 bmcr;
9908
9909                 spin_lock_bh(&tp->lock);
9910                 r = -EINVAL;
9911                 tg3_readphy(tp, MII_BMCR, &bmcr);
9912                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9913                     ((bmcr & BMCR_ANENABLE) ||
9914                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9915                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9916                                                    BMCR_ANENABLE);
9917                         r = 0;
9918                 }
9919                 spin_unlock_bh(&tp->lock);
9920         }
9921
9922         return r;
9923 }
9924
9925 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9926 {
9927         struct tg3 *tp = netdev_priv(dev);
9928
9929         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9930         ering->rx_mini_max_pending = 0;
9931         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9932                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9933         else
9934                 ering->rx_jumbo_max_pending = 0;
9935
9936         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9937
9938         ering->rx_pending = tp->rx_pending;
9939         ering->rx_mini_pending = 0;
9940         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9941                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9942         else
9943                 ering->rx_jumbo_pending = 0;
9944
9945         ering->tx_pending = tp->napi[0].tx_pending;
9946 }
9947
9948 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9949 {
9950         struct tg3 *tp = netdev_priv(dev);
9951         int i, irq_sync = 0, err = 0;
9952
9953         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9954             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9955             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9956             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9957             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9958              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9959                 return -EINVAL;
9960
9961         if (netif_running(dev)) {
9962                 tg3_phy_stop(tp);
9963                 tg3_netif_stop(tp);
9964                 irq_sync = 1;
9965         }
9966
9967         tg3_full_lock(tp, irq_sync);
9968
9969         tp->rx_pending = ering->rx_pending;
9970
9971         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9972             tp->rx_pending > 63)
9973                 tp->rx_pending = 63;
9974         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9975
9976         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9977                 tp->napi[i].tx_pending = ering->tx_pending;
9978
9979         if (netif_running(dev)) {
9980                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9981                 err = tg3_restart_hw(tp, 1);
9982                 if (!err)
9983                         tg3_netif_start(tp);
9984         }
9985
9986         tg3_full_unlock(tp);
9987
9988         if (irq_sync && !err)
9989                 tg3_phy_start(tp);
9990
9991         return err;
9992 }
9993
9994 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9995 {
9996         struct tg3 *tp = netdev_priv(dev);
9997
9998         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9999
10000         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10001                 epause->rx_pause = 1;
10002         else
10003                 epause->rx_pause = 0;
10004
10005         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10006                 epause->tx_pause = 1;
10007         else
10008                 epause->tx_pause = 0;
10009 }
10010
10011 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10012 {
10013         struct tg3 *tp = netdev_priv(dev);
10014         int err = 0;
10015
10016         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10017                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10018                         return -EAGAIN;
10019
10020                 if (epause->autoneg) {
10021                         u32 newadv;
10022                         struct phy_device *phydev;
10023
10024                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10025
10026                         if (epause->rx_pause) {
10027                                 if (epause->tx_pause)
10028                                         newadv = ADVERTISED_Pause;
10029                                 else
10030                                         newadv = ADVERTISED_Pause |
10031                                                  ADVERTISED_Asym_Pause;
10032                         } else if (epause->tx_pause) {
10033                                 newadv = ADVERTISED_Asym_Pause;
10034                         } else
10035                                 newadv = 0;
10036
10037                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10038                                 u32 oldadv = phydev->advertising &
10039                                              (ADVERTISED_Pause |
10040                                               ADVERTISED_Asym_Pause);
10041                                 if (oldadv != newadv) {
10042                                         phydev->advertising &=
10043                                                 ~(ADVERTISED_Pause |
10044                                                   ADVERTISED_Asym_Pause);
10045                                         phydev->advertising |= newadv;
10046                                         err = phy_start_aneg(phydev);
10047                                 }
10048                         } else {
10049                                 tp->link_config.advertising &=
10050                                                 ~(ADVERTISED_Pause |
10051                                                   ADVERTISED_Asym_Pause);
10052                                 tp->link_config.advertising |= newadv;
10053                         }
10054                 } else {
10055                         if (epause->rx_pause)
10056                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10057                         else
10058                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10059
10060                         if (epause->tx_pause)
10061                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10062                         else
10063                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10064
10065                         if (netif_running(dev))
10066                                 tg3_setup_flow_control(tp, 0, 0);
10067                 }
10068         } else {
10069                 int irq_sync = 0;
10070
10071                 if (netif_running(dev)) {
10072                         tg3_netif_stop(tp);
10073                         irq_sync = 1;
10074                 }
10075
10076                 tg3_full_lock(tp, irq_sync);
10077
10078                 if (epause->autoneg)
10079                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10080                 else
10081                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10082                 if (epause->rx_pause)
10083                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10084                 else
10085                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10086                 if (epause->tx_pause)
10087                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10088                 else
10089                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10090
10091                 if (netif_running(dev)) {
10092                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10093                         err = tg3_restart_hw(tp, 1);
10094                         if (!err)
10095                                 tg3_netif_start(tp);
10096                 }
10097
10098                 tg3_full_unlock(tp);
10099         }
10100
10101         return err;
10102 }
10103
10104 static u32 tg3_get_rx_csum(struct net_device *dev)
10105 {
10106         struct tg3 *tp = netdev_priv(dev);
10107         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10108 }
10109
10110 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10111 {
10112         struct tg3 *tp = netdev_priv(dev);
10113
10114         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10115                 if (data != 0)
10116                         return -EINVAL;
10117                 return 0;
10118         }
10119
10120         spin_lock_bh(&tp->lock);
10121         if (data)
10122                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10123         else
10124                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10125         spin_unlock_bh(&tp->lock);
10126
10127         return 0;
10128 }
10129
10130 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10131 {
10132         struct tg3 *tp = netdev_priv(dev);
10133
10134         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10135                 if (data != 0)
10136                         return -EINVAL;
10137                 return 0;
10138         }
10139
10140         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10141                 ethtool_op_set_tx_ipv6_csum(dev, data);
10142         else
10143                 ethtool_op_set_tx_csum(dev, data);
10144
10145         return 0;
10146 }
10147
10148 static int tg3_get_sset_count (struct net_device *dev, int sset)
10149 {
10150         switch (sset) {
10151         case ETH_SS_TEST:
10152                 return TG3_NUM_TEST;
10153         case ETH_SS_STATS:
10154                 return TG3_NUM_STATS;
10155         default:
10156                 return -EOPNOTSUPP;
10157         }
10158 }
10159
10160 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10161 {
10162         switch (stringset) {
10163         case ETH_SS_STATS:
10164                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10165                 break;
10166         case ETH_SS_TEST:
10167                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10168                 break;
10169         default:
10170                 WARN_ON(1);     /* we need a WARN() */
10171                 break;
10172         }
10173 }
10174
10175 static int tg3_phys_id(struct net_device *dev, u32 data)
10176 {
10177         struct tg3 *tp = netdev_priv(dev);
10178         int i;
10179
10180         if (!netif_running(tp->dev))
10181                 return -EAGAIN;
10182
10183         if (data == 0)
10184                 data = UINT_MAX / 2;
10185
10186         for (i = 0; i < (data * 2); i++) {
10187                 if ((i % 2) == 0)
10188                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10189                                            LED_CTRL_1000MBPS_ON |
10190                                            LED_CTRL_100MBPS_ON |
10191                                            LED_CTRL_10MBPS_ON |
10192                                            LED_CTRL_TRAFFIC_OVERRIDE |
10193                                            LED_CTRL_TRAFFIC_BLINK |
10194                                            LED_CTRL_TRAFFIC_LED);
10195
10196                 else
10197                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10198                                            LED_CTRL_TRAFFIC_OVERRIDE);
10199
10200                 if (msleep_interruptible(500))
10201                         break;
10202         }
10203         tw32(MAC_LED_CTRL, tp->led_ctrl);
10204         return 0;
10205 }
10206
10207 static void tg3_get_ethtool_stats (struct net_device *dev,
10208                                    struct ethtool_stats *estats, u64 *tmp_stats)
10209 {
10210         struct tg3 *tp = netdev_priv(dev);
10211         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10212 }
10213
10214 #define NVRAM_TEST_SIZE 0x100
10215 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10216 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10217 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10218 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10219 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10220
10221 static int tg3_test_nvram(struct tg3 *tp)
10222 {
10223         u32 csum, magic;
10224         __be32 *buf;
10225         int i, j, k, err = 0, size;
10226
10227         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10228                 return 0;
10229
10230         if (tg3_nvram_read(tp, 0, &magic) != 0)
10231                 return -EIO;
10232
10233         if (magic == TG3_EEPROM_MAGIC)
10234                 size = NVRAM_TEST_SIZE;
10235         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10236                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10237                     TG3_EEPROM_SB_FORMAT_1) {
10238                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10239                         case TG3_EEPROM_SB_REVISION_0:
10240                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10241                                 break;
10242                         case TG3_EEPROM_SB_REVISION_2:
10243                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10244                                 break;
10245                         case TG3_EEPROM_SB_REVISION_3:
10246                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10247                                 break;
10248                         default:
10249                                 return 0;
10250                         }
10251                 } else
10252                         return 0;
10253         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10254                 size = NVRAM_SELFBOOT_HW_SIZE;
10255         else
10256                 return -EIO;
10257
10258         buf = kmalloc(size, GFP_KERNEL);
10259         if (buf == NULL)
10260                 return -ENOMEM;
10261
10262         err = -EIO;
10263         for (i = 0, j = 0; i < size; i += 4, j++) {
10264                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10265                 if (err)
10266                         break;
10267         }
10268         if (i < size)
10269                 goto out;
10270
10271         /* Selfboot format */
10272         magic = be32_to_cpu(buf[0]);
10273         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10274             TG3_EEPROM_MAGIC_FW) {
10275                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10276
10277                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10278                     TG3_EEPROM_SB_REVISION_2) {
10279                         /* For rev 2, the csum doesn't include the MBA. */
10280                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10281                                 csum8 += buf8[i];
10282                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10283                                 csum8 += buf8[i];
10284                 } else {
10285                         for (i = 0; i < size; i++)
10286                                 csum8 += buf8[i];
10287                 }
10288
10289                 if (csum8 == 0) {
10290                         err = 0;
10291                         goto out;
10292                 }
10293
10294                 err = -EIO;
10295                 goto out;
10296         }
10297
10298         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10299             TG3_EEPROM_MAGIC_HW) {
10300                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10301                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10302                 u8 *buf8 = (u8 *) buf;
10303
10304                 /* Separate the parity bits and the data bytes.  */
10305                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10306                         if ((i == 0) || (i == 8)) {
10307                                 int l;
10308                                 u8 msk;
10309
10310                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10311                                         parity[k++] = buf8[i] & msk;
10312                                 i++;
10313                         }
10314                         else if (i == 16) {
10315                                 int l;
10316                                 u8 msk;
10317
10318                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10319                                         parity[k++] = buf8[i] & msk;
10320                                 i++;
10321
10322                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10323                                         parity[k++] = buf8[i] & msk;
10324                                 i++;
10325                         }
10326                         data[j++] = buf8[i];
10327                 }
10328
10329                 err = -EIO;
10330                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10331                         u8 hw8 = hweight8(data[i]);
10332
10333                         if ((hw8 & 0x1) && parity[i])
10334                                 goto out;
10335                         else if (!(hw8 & 0x1) && !parity[i])
10336                                 goto out;
10337                 }
10338                 err = 0;
10339                 goto out;
10340         }
10341
10342         /* Bootstrap checksum at offset 0x10 */
10343         csum = calc_crc((unsigned char *) buf, 0x10);
10344         if (csum != be32_to_cpu(buf[0x10/4]))
10345                 goto out;
10346
10347         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10348         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10349         if (csum != be32_to_cpu(buf[0xfc/4]))
10350                 goto out;
10351
10352         err = 0;
10353
10354 out:
10355         kfree(buf);
10356         return err;
10357 }
10358
10359 #define TG3_SERDES_TIMEOUT_SEC  2
10360 #define TG3_COPPER_TIMEOUT_SEC  6
10361
10362 static int tg3_test_link(struct tg3 *tp)
10363 {
10364         int i, max;
10365
10366         if (!netif_running(tp->dev))
10367                 return -ENODEV;
10368
10369         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10370                 max = TG3_SERDES_TIMEOUT_SEC;
10371         else
10372                 max = TG3_COPPER_TIMEOUT_SEC;
10373
10374         for (i = 0; i < max; i++) {
10375                 if (netif_carrier_ok(tp->dev))
10376                         return 0;
10377
10378                 if (msleep_interruptible(1000))
10379                         break;
10380         }
10381
10382         return -EIO;
10383 }
10384
10385 /* Only test the commonly used registers */
10386 static int tg3_test_registers(struct tg3 *tp)
10387 {
10388         int i, is_5705, is_5750;
10389         u32 offset, read_mask, write_mask, val, save_val, read_val;
10390         static struct {
10391                 u16 offset;
10392                 u16 flags;
10393 #define TG3_FL_5705     0x1
10394 #define TG3_FL_NOT_5705 0x2
10395 #define TG3_FL_NOT_5788 0x4
10396 #define TG3_FL_NOT_5750 0x8
10397                 u32 read_mask;
10398                 u32 write_mask;
10399         } reg_tbl[] = {
10400                 /* MAC Control Registers */
10401                 { MAC_MODE, TG3_FL_NOT_5705,
10402                         0x00000000, 0x00ef6f8c },
10403                 { MAC_MODE, TG3_FL_5705,
10404                         0x00000000, 0x01ef6b8c },
10405                 { MAC_STATUS, TG3_FL_NOT_5705,
10406                         0x03800107, 0x00000000 },
10407                 { MAC_STATUS, TG3_FL_5705,
10408                         0x03800100, 0x00000000 },
10409                 { MAC_ADDR_0_HIGH, 0x0000,
10410                         0x00000000, 0x0000ffff },
10411                 { MAC_ADDR_0_LOW, 0x0000,
10412                         0x00000000, 0xffffffff },
10413                 { MAC_RX_MTU_SIZE, 0x0000,
10414                         0x00000000, 0x0000ffff },
10415                 { MAC_TX_MODE, 0x0000,
10416                         0x00000000, 0x00000070 },
10417                 { MAC_TX_LENGTHS, 0x0000,
10418                         0x00000000, 0x00003fff },
10419                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10420                         0x00000000, 0x000007fc },
10421                 { MAC_RX_MODE, TG3_FL_5705,
10422                         0x00000000, 0x000007dc },
10423                 { MAC_HASH_REG_0, 0x0000,
10424                         0x00000000, 0xffffffff },
10425                 { MAC_HASH_REG_1, 0x0000,
10426                         0x00000000, 0xffffffff },
10427                 { MAC_HASH_REG_2, 0x0000,
10428                         0x00000000, 0xffffffff },
10429                 { MAC_HASH_REG_3, 0x0000,
10430                         0x00000000, 0xffffffff },
10431
10432                 /* Receive Data and Receive BD Initiator Control Registers. */
10433                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10434                         0x00000000, 0xffffffff },
10435                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10436                         0x00000000, 0xffffffff },
10437                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10438                         0x00000000, 0x00000003 },
10439                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10440                         0x00000000, 0xffffffff },
10441                 { RCVDBDI_STD_BD+0, 0x0000,
10442                         0x00000000, 0xffffffff },
10443                 { RCVDBDI_STD_BD+4, 0x0000,
10444                         0x00000000, 0xffffffff },
10445                 { RCVDBDI_STD_BD+8, 0x0000,
10446                         0x00000000, 0xffff0002 },
10447                 { RCVDBDI_STD_BD+0xc, 0x0000,
10448                         0x00000000, 0xffffffff },
10449
10450                 /* Receive BD Initiator Control Registers. */
10451                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10452                         0x00000000, 0xffffffff },
10453                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10454                         0x00000000, 0x000003ff },
10455                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10456                         0x00000000, 0xffffffff },
10457
10458                 /* Host Coalescing Control Registers. */
10459                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10460                         0x00000000, 0x00000004 },
10461                 { HOSTCC_MODE, TG3_FL_5705,
10462                         0x00000000, 0x000000f6 },
10463                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10464                         0x00000000, 0xffffffff },
10465                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10466                         0x00000000, 0x000003ff },
10467                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10468                         0x00000000, 0xffffffff },
10469                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10470                         0x00000000, 0x000003ff },
10471                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10472                         0x00000000, 0xffffffff },
10473                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10474                         0x00000000, 0x000000ff },
10475                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10476                         0x00000000, 0xffffffff },
10477                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10478                         0x00000000, 0x000000ff },
10479                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10480                         0x00000000, 0xffffffff },
10481                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10482                         0x00000000, 0xffffffff },
10483                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10484                         0x00000000, 0xffffffff },
10485                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10486                         0x00000000, 0x000000ff },
10487                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10488                         0x00000000, 0xffffffff },
10489                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10490                         0x00000000, 0x000000ff },
10491                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10492                         0x00000000, 0xffffffff },
10493                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10494                         0x00000000, 0xffffffff },
10495                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10496                         0x00000000, 0xffffffff },
10497                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10498                         0x00000000, 0xffffffff },
10499                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10500                         0x00000000, 0xffffffff },
10501                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10502                         0xffffffff, 0x00000000 },
10503                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10504                         0xffffffff, 0x00000000 },
10505
10506                 /* Buffer Manager Control Registers. */
10507                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10508                         0x00000000, 0x007fff80 },
10509                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10510                         0x00000000, 0x007fffff },
10511                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10512                         0x00000000, 0x0000003f },
10513                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10514                         0x00000000, 0x000001ff },
10515                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10516                         0x00000000, 0x000001ff },
10517                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10518                         0xffffffff, 0x00000000 },
10519                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10520                         0xffffffff, 0x00000000 },
10521
10522                 /* Mailbox Registers */
10523                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10524                         0x00000000, 0x000001ff },
10525                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10526                         0x00000000, 0x000001ff },
10527                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10528                         0x00000000, 0x000007ff },
10529                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10530                         0x00000000, 0x000001ff },
10531
10532                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10533         };
10534
10535         is_5705 = is_5750 = 0;
10536         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10537                 is_5705 = 1;
10538                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10539                         is_5750 = 1;
10540         }
10541
10542         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10543                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10544                         continue;
10545
10546                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10547                         continue;
10548
10549                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10550                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10551                         continue;
10552
10553                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10554                         continue;
10555
10556                 offset = (u32) reg_tbl[i].offset;
10557                 read_mask = reg_tbl[i].read_mask;
10558                 write_mask = reg_tbl[i].write_mask;
10559
10560                 /* Save the original register content */
10561                 save_val = tr32(offset);
10562
10563                 /* Determine the read-only value. */
10564                 read_val = save_val & read_mask;
10565
10566                 /* Write zero to the register, then make sure the read-only bits
10567                  * are not changed and the read/write bits are all zeros.
10568                  */
10569                 tw32(offset, 0);
10570
10571                 val = tr32(offset);
10572
10573                 /* Test the read-only and read/write bits. */
10574                 if (((val & read_mask) != read_val) || (val & write_mask))
10575                         goto out;
10576
10577                 /* Write ones to all the bits defined by RdMask and WrMask, then
10578                  * make sure the read-only bits are not changed and the
10579                  * read/write bits are all ones.
10580                  */
10581                 tw32(offset, read_mask | write_mask);
10582
10583                 val = tr32(offset);
10584
10585                 /* Test the read-only bits. */
10586                 if ((val & read_mask) != read_val)
10587                         goto out;
10588
10589                 /* Test the read/write bits. */
10590                 if ((val & write_mask) != write_mask)
10591                         goto out;
10592
10593                 tw32(offset, save_val);
10594         }
10595
10596         return 0;
10597
10598 out:
10599         if (netif_msg_hw(tp))
10600                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10601                        offset);
10602         tw32(offset, save_val);
10603         return -EIO;
10604 }
10605
10606 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10607 {
10608         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10609         int i;
10610         u32 j;
10611
10612         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10613                 for (j = 0; j < len; j += 4) {
10614                         u32 val;
10615
10616                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10617                         tg3_read_mem(tp, offset + j, &val);
10618                         if (val != test_pattern[i])
10619                                 return -EIO;
10620                 }
10621         }
10622         return 0;
10623 }
10624
10625 static int tg3_test_memory(struct tg3 *tp)
10626 {
10627         static struct mem_entry {
10628                 u32 offset;
10629                 u32 len;
10630         } mem_tbl_570x[] = {
10631                 { 0x00000000, 0x00b50},
10632                 { 0x00002000, 0x1c000},
10633                 { 0xffffffff, 0x00000}
10634         }, mem_tbl_5705[] = {
10635                 { 0x00000100, 0x0000c},
10636                 { 0x00000200, 0x00008},
10637                 { 0x00004000, 0x00800},
10638                 { 0x00006000, 0x01000},
10639                 { 0x00008000, 0x02000},
10640                 { 0x00010000, 0x0e000},
10641                 { 0xffffffff, 0x00000}
10642         }, mem_tbl_5755[] = {
10643                 { 0x00000200, 0x00008},
10644                 { 0x00004000, 0x00800},
10645                 { 0x00006000, 0x00800},
10646                 { 0x00008000, 0x02000},
10647                 { 0x00010000, 0x0c000},
10648                 { 0xffffffff, 0x00000}
10649         }, mem_tbl_5906[] = {
10650                 { 0x00000200, 0x00008},
10651                 { 0x00004000, 0x00400},
10652                 { 0x00006000, 0x00400},
10653                 { 0x00008000, 0x01000},
10654                 { 0x00010000, 0x01000},
10655                 { 0xffffffff, 0x00000}
10656         };
10657         struct mem_entry *mem_tbl;
10658         int err = 0;
10659         int i;
10660
10661         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10662                 mem_tbl = mem_tbl_5755;
10663         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10664                 mem_tbl = mem_tbl_5906;
10665         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10666                 mem_tbl = mem_tbl_5705;
10667         else
10668                 mem_tbl = mem_tbl_570x;
10669
10670         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10671                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10672                     mem_tbl[i].len)) != 0)
10673                         break;
10674         }
10675
10676         return err;
10677 }
10678
10679 #define TG3_MAC_LOOPBACK        0
10680 #define TG3_PHY_LOOPBACK        1
10681
10682 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10683 {
10684         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10685         u32 desc_idx, coal_now;
10686         struct sk_buff *skb, *rx_skb;
10687         u8 *tx_data;
10688         dma_addr_t map;
10689         int num_pkts, tx_len, rx_len, i, err;
10690         struct tg3_rx_buffer_desc *desc;
10691         struct tg3_napi *tnapi, *rnapi;
10692         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10693
10694         if (tp->irq_cnt > 1) {
10695                 tnapi = &tp->napi[1];
10696                 rnapi = &tp->napi[1];
10697         } else {
10698                 tnapi = &tp->napi[0];
10699                 rnapi = &tp->napi[0];
10700         }
10701         coal_now = tnapi->coal_now | rnapi->coal_now;
10702
10703         if (loopback_mode == TG3_MAC_LOOPBACK) {
10704                 /* HW errata - mac loopback fails in some cases on 5780.
10705                  * Normal traffic and PHY loopback are not affected by
10706                  * errata.
10707                  */
10708                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10709                         return 0;
10710
10711                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10712                            MAC_MODE_PORT_INT_LPBACK;
10713                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10714                         mac_mode |= MAC_MODE_LINK_POLARITY;
10715                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10716                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10717                 else
10718                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10719                 tw32(MAC_MODE, mac_mode);
10720         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10721                 u32 val;
10722
10723                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10724                         tg3_phy_fet_toggle_apd(tp, false);
10725                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10726                 } else
10727                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10728
10729                 tg3_phy_toggle_automdix(tp, 0);
10730
10731                 tg3_writephy(tp, MII_BMCR, val);
10732                 udelay(40);
10733
10734                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10735                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10736                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10737                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10738                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10739                 } else
10740                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10741
10742                 /* reset to prevent losing 1st rx packet intermittently */
10743                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10744                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10745                         udelay(10);
10746                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10747                 }
10748                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10749                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10750                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10751                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10752                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10753                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10754                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10755                 }
10756                 tw32(MAC_MODE, mac_mode);
10757         }
10758         else
10759                 return -EINVAL;
10760
10761         err = -EIO;
10762
10763         tx_len = 1514;
10764         skb = netdev_alloc_skb(tp->dev, tx_len);
10765         if (!skb)
10766                 return -ENOMEM;
10767
10768         tx_data = skb_put(skb, tx_len);
10769         memcpy(tx_data, tp->dev->dev_addr, 6);
10770         memset(tx_data + 6, 0x0, 8);
10771
10772         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10773
10774         for (i = 14; i < tx_len; i++)
10775                 tx_data[i] = (u8) (i & 0xff);
10776
10777         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10778         if (pci_dma_mapping_error(tp->pdev, map)) {
10779                 dev_kfree_skb(skb);
10780                 return -EIO;
10781         }
10782
10783         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10784                rnapi->coal_now);
10785
10786         udelay(10);
10787
10788         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10789
10790         num_pkts = 0;
10791
10792         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10793
10794         tnapi->tx_prod++;
10795         num_pkts++;
10796
10797         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10798         tr32_mailbox(tnapi->prodmbox);
10799
10800         udelay(10);
10801
10802         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10803         for (i = 0; i < 35; i++) {
10804                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10805                        coal_now);
10806
10807                 udelay(10);
10808
10809                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10810                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10811                 if ((tx_idx == tnapi->tx_prod) &&
10812                     (rx_idx == (rx_start_idx + num_pkts)))
10813                         break;
10814         }
10815
10816         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10817         dev_kfree_skb(skb);
10818
10819         if (tx_idx != tnapi->tx_prod)
10820                 goto out;
10821
10822         if (rx_idx != rx_start_idx + num_pkts)
10823                 goto out;
10824
10825         desc = &rnapi->rx_rcb[rx_start_idx];
10826         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10827         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10828         if (opaque_key != RXD_OPAQUE_RING_STD)
10829                 goto out;
10830
10831         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10832             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10833                 goto out;
10834
10835         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10836         if (rx_len != tx_len)
10837                 goto out;
10838
10839         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10840
10841         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10842         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10843
10844         for (i = 14; i < tx_len; i++) {
10845                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10846                         goto out;
10847         }
10848         err = 0;
10849
10850         /* tg3_free_rings will unmap and free the rx_skb */
10851 out:
10852         return err;
10853 }
10854
10855 #define TG3_MAC_LOOPBACK_FAILED         1
10856 #define TG3_PHY_LOOPBACK_FAILED         2
10857 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10858                                          TG3_PHY_LOOPBACK_FAILED)
10859
10860 static int tg3_test_loopback(struct tg3 *tp)
10861 {
10862         int err = 0;
10863         u32 cpmuctrl = 0;
10864
10865         if (!netif_running(tp->dev))
10866                 return TG3_LOOPBACK_FAILED;
10867
10868         err = tg3_reset_hw(tp, 1);
10869         if (err)
10870                 return TG3_LOOPBACK_FAILED;
10871
10872         /* Turn off gphy autopowerdown. */
10873         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10874                 tg3_phy_toggle_apd(tp, false);
10875
10876         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10877                 int i;
10878                 u32 status;
10879
10880                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10881
10882                 /* Wait for up to 40 microseconds to acquire lock. */
10883                 for (i = 0; i < 4; i++) {
10884                         status = tr32(TG3_CPMU_MUTEX_GNT);
10885                         if (status == CPMU_MUTEX_GNT_DRIVER)
10886                                 break;
10887                         udelay(10);
10888                 }
10889
10890                 if (status != CPMU_MUTEX_GNT_DRIVER)
10891                         return TG3_LOOPBACK_FAILED;
10892
10893                 /* Turn off link-based power management. */
10894                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10895                 tw32(TG3_CPMU_CTRL,
10896                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10897                                   CPMU_CTRL_LINK_AWARE_MODE));
10898         }
10899
10900         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10901                 err |= TG3_MAC_LOOPBACK_FAILED;
10902
10903         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10904                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10905
10906                 /* Release the mutex */
10907                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10908         }
10909
10910         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10911             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10912                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10913                         err |= TG3_PHY_LOOPBACK_FAILED;
10914         }
10915
10916         /* Re-enable gphy autopowerdown. */
10917         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10918                 tg3_phy_toggle_apd(tp, true);
10919
10920         return err;
10921 }
10922
10923 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10924                           u64 *data)
10925 {
10926         struct tg3 *tp = netdev_priv(dev);
10927
10928         if (tp->link_config.phy_is_low_power)
10929                 tg3_set_power_state(tp, PCI_D0);
10930
10931         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10932
10933         if (tg3_test_nvram(tp) != 0) {
10934                 etest->flags |= ETH_TEST_FL_FAILED;
10935                 data[0] = 1;
10936         }
10937         if (tg3_test_link(tp) != 0) {
10938                 etest->flags |= ETH_TEST_FL_FAILED;
10939                 data[1] = 1;
10940         }
10941         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10942                 int err, err2 = 0, irq_sync = 0;
10943
10944                 if (netif_running(dev)) {
10945                         tg3_phy_stop(tp);
10946                         tg3_netif_stop(tp);
10947                         irq_sync = 1;
10948                 }
10949
10950                 tg3_full_lock(tp, irq_sync);
10951
10952                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10953                 err = tg3_nvram_lock(tp);
10954                 tg3_halt_cpu(tp, RX_CPU_BASE);
10955                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10956                         tg3_halt_cpu(tp, TX_CPU_BASE);
10957                 if (!err)
10958                         tg3_nvram_unlock(tp);
10959
10960                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10961                         tg3_phy_reset(tp);
10962
10963                 if (tg3_test_registers(tp) != 0) {
10964                         etest->flags |= ETH_TEST_FL_FAILED;
10965                         data[2] = 1;
10966                 }
10967                 if (tg3_test_memory(tp) != 0) {
10968                         etest->flags |= ETH_TEST_FL_FAILED;
10969                         data[3] = 1;
10970                 }
10971                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10972                         etest->flags |= ETH_TEST_FL_FAILED;
10973
10974                 tg3_full_unlock(tp);
10975
10976                 if (tg3_test_interrupt(tp) != 0) {
10977                         etest->flags |= ETH_TEST_FL_FAILED;
10978                         data[5] = 1;
10979                 }
10980
10981                 tg3_full_lock(tp, 0);
10982
10983                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10984                 if (netif_running(dev)) {
10985                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10986                         err2 = tg3_restart_hw(tp, 1);
10987                         if (!err2)
10988                                 tg3_netif_start(tp);
10989                 }
10990
10991                 tg3_full_unlock(tp);
10992
10993                 if (irq_sync && !err2)
10994                         tg3_phy_start(tp);
10995         }
10996         if (tp->link_config.phy_is_low_power)
10997                 tg3_set_power_state(tp, PCI_D3hot);
10998
10999 }
11000
11001 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11002 {
11003         struct mii_ioctl_data *data = if_mii(ifr);
11004         struct tg3 *tp = netdev_priv(dev);
11005         int err;
11006
11007         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11008                 struct phy_device *phydev;
11009                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11010                         return -EAGAIN;
11011                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11012                 return phy_mii_ioctl(phydev, data, cmd);
11013         }
11014
11015         switch(cmd) {
11016         case SIOCGMIIPHY:
11017                 data->phy_id = tp->phy_addr;
11018
11019                 /* fallthru */
11020         case SIOCGMIIREG: {
11021                 u32 mii_regval;
11022
11023                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11024                         break;                  /* We have no PHY */
11025
11026                 if (tp->link_config.phy_is_low_power)
11027                         return -EAGAIN;
11028
11029                 spin_lock_bh(&tp->lock);
11030                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11031                 spin_unlock_bh(&tp->lock);
11032
11033                 data->val_out = mii_regval;
11034
11035                 return err;
11036         }
11037
11038         case SIOCSMIIREG:
11039                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11040                         break;                  /* We have no PHY */
11041
11042                 if (tp->link_config.phy_is_low_power)
11043                         return -EAGAIN;
11044
11045                 spin_lock_bh(&tp->lock);
11046                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11047                 spin_unlock_bh(&tp->lock);
11048
11049                 return err;
11050
11051         default:
11052                 /* do nothing */
11053                 break;
11054         }
11055         return -EOPNOTSUPP;
11056 }
11057
11058 #if TG3_VLAN_TAG_USED
11059 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11060 {
11061         struct tg3 *tp = netdev_priv(dev);
11062
11063         if (!netif_running(dev)) {
11064                 tp->vlgrp = grp;
11065                 return;
11066         }
11067
11068         tg3_netif_stop(tp);
11069
11070         tg3_full_lock(tp, 0);
11071
11072         tp->vlgrp = grp;
11073
11074         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11075         __tg3_set_rx_mode(dev);
11076
11077         tg3_netif_start(tp);
11078
11079         tg3_full_unlock(tp);
11080 }
11081 #endif
11082
11083 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11084 {
11085         struct tg3 *tp = netdev_priv(dev);
11086
11087         memcpy(ec, &tp->coal, sizeof(*ec));
11088         return 0;
11089 }
11090
11091 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11092 {
11093         struct tg3 *tp = netdev_priv(dev);
11094         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11095         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11096
11097         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11098                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11099                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11100                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11101                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11102         }
11103
11104         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11105             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11106             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11107             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11108             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11109             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11110             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11111             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11112             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11113             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11114                 return -EINVAL;
11115
11116         /* No rx interrupts will be generated if both are zero */
11117         if ((ec->rx_coalesce_usecs == 0) &&
11118             (ec->rx_max_coalesced_frames == 0))
11119                 return -EINVAL;
11120
11121         /* No tx interrupts will be generated if both are zero */
11122         if ((ec->tx_coalesce_usecs == 0) &&
11123             (ec->tx_max_coalesced_frames == 0))
11124                 return -EINVAL;
11125
11126         /* Only copy relevant parameters, ignore all others. */
11127         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11128         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11129         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11130         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11131         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11132         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11133         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11134         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11135         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11136
11137         if (netif_running(dev)) {
11138                 tg3_full_lock(tp, 0);
11139                 __tg3_set_coalesce(tp, &tp->coal);
11140                 tg3_full_unlock(tp);
11141         }
11142         return 0;
11143 }
11144
11145 static const struct ethtool_ops tg3_ethtool_ops = {
11146         .get_settings           = tg3_get_settings,
11147         .set_settings           = tg3_set_settings,
11148         .get_drvinfo            = tg3_get_drvinfo,
11149         .get_regs_len           = tg3_get_regs_len,
11150         .get_regs               = tg3_get_regs,
11151         .get_wol                = tg3_get_wol,
11152         .set_wol                = tg3_set_wol,
11153         .get_msglevel           = tg3_get_msglevel,
11154         .set_msglevel           = tg3_set_msglevel,
11155         .nway_reset             = tg3_nway_reset,
11156         .get_link               = ethtool_op_get_link,
11157         .get_eeprom_len         = tg3_get_eeprom_len,
11158         .get_eeprom             = tg3_get_eeprom,
11159         .set_eeprom             = tg3_set_eeprom,
11160         .get_ringparam          = tg3_get_ringparam,
11161         .set_ringparam          = tg3_set_ringparam,
11162         .get_pauseparam         = tg3_get_pauseparam,
11163         .set_pauseparam         = tg3_set_pauseparam,
11164         .get_rx_csum            = tg3_get_rx_csum,
11165         .set_rx_csum            = tg3_set_rx_csum,
11166         .set_tx_csum            = tg3_set_tx_csum,
11167         .set_sg                 = ethtool_op_set_sg,
11168         .set_tso                = tg3_set_tso,
11169         .self_test              = tg3_self_test,
11170         .get_strings            = tg3_get_strings,
11171         .phys_id                = tg3_phys_id,
11172         .get_ethtool_stats      = tg3_get_ethtool_stats,
11173         .get_coalesce           = tg3_get_coalesce,
11174         .set_coalesce           = tg3_set_coalesce,
11175         .get_sset_count         = tg3_get_sset_count,
11176 };
11177
11178 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11179 {
11180         u32 cursize, val, magic;
11181
11182         tp->nvram_size = EEPROM_CHIP_SIZE;
11183
11184         if (tg3_nvram_read(tp, 0, &magic) != 0)
11185                 return;
11186
11187         if ((magic != TG3_EEPROM_MAGIC) &&
11188             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11189             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11190                 return;
11191
11192         /*
11193          * Size the chip by reading offsets at increasing powers of two.
11194          * When we encounter our validation signature, we know the addressing
11195          * has wrapped around, and thus have our chip size.
11196          */
11197         cursize = 0x10;
11198
11199         while (cursize < tp->nvram_size) {
11200                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11201                         return;
11202
11203                 if (val == magic)
11204                         break;
11205
11206                 cursize <<= 1;
11207         }
11208
11209         tp->nvram_size = cursize;
11210 }
11211
11212 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11213 {
11214         u32 val;
11215
11216         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11217             tg3_nvram_read(tp, 0, &val) != 0)
11218                 return;
11219
11220         /* Selfboot format */
11221         if (val != TG3_EEPROM_MAGIC) {
11222                 tg3_get_eeprom_size(tp);
11223                 return;
11224         }
11225
11226         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11227                 if (val != 0) {
11228                         /* This is confusing.  We want to operate on the
11229                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11230                          * call will read from NVRAM and byteswap the data
11231                          * according to the byteswapping settings for all
11232                          * other register accesses.  This ensures the data we
11233                          * want will always reside in the lower 16-bits.
11234                          * However, the data in NVRAM is in LE format, which
11235                          * means the data from the NVRAM read will always be
11236                          * opposite the endianness of the CPU.  The 16-bit
11237                          * byteswap then brings the data to CPU endianness.
11238                          */
11239                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11240                         return;
11241                 }
11242         }
11243         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11244 }
11245
11246 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11247 {
11248         u32 nvcfg1;
11249
11250         nvcfg1 = tr32(NVRAM_CFG1);
11251         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11252                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11253         } else {
11254                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11255                 tw32(NVRAM_CFG1, nvcfg1);
11256         }
11257
11258         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11259             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11260                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11261                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11262                         tp->nvram_jedecnum = JEDEC_ATMEL;
11263                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11264                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11265                         break;
11266                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11267                         tp->nvram_jedecnum = JEDEC_ATMEL;
11268                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11269                         break;
11270                 case FLASH_VENDOR_ATMEL_EEPROM:
11271                         tp->nvram_jedecnum = JEDEC_ATMEL;
11272                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11273                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11274                         break;
11275                 case FLASH_VENDOR_ST:
11276                         tp->nvram_jedecnum = JEDEC_ST;
11277                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11278                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11279                         break;
11280                 case FLASH_VENDOR_SAIFUN:
11281                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11282                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11283                         break;
11284                 case FLASH_VENDOR_SST_SMALL:
11285                 case FLASH_VENDOR_SST_LARGE:
11286                         tp->nvram_jedecnum = JEDEC_SST;
11287                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11288                         break;
11289                 }
11290         } else {
11291                 tp->nvram_jedecnum = JEDEC_ATMEL;
11292                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11293                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11294         }
11295 }
11296
11297 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11298 {
11299         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11300         case FLASH_5752PAGE_SIZE_256:
11301                 tp->nvram_pagesize = 256;
11302                 break;
11303         case FLASH_5752PAGE_SIZE_512:
11304                 tp->nvram_pagesize = 512;
11305                 break;
11306         case FLASH_5752PAGE_SIZE_1K:
11307                 tp->nvram_pagesize = 1024;
11308                 break;
11309         case FLASH_5752PAGE_SIZE_2K:
11310                 tp->nvram_pagesize = 2048;
11311                 break;
11312         case FLASH_5752PAGE_SIZE_4K:
11313                 tp->nvram_pagesize = 4096;
11314                 break;
11315         case FLASH_5752PAGE_SIZE_264:
11316                 tp->nvram_pagesize = 264;
11317                 break;
11318         case FLASH_5752PAGE_SIZE_528:
11319                 tp->nvram_pagesize = 528;
11320                 break;
11321         }
11322 }
11323
11324 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11325 {
11326         u32 nvcfg1;
11327
11328         nvcfg1 = tr32(NVRAM_CFG1);
11329
11330         /* NVRAM protection for TPM */
11331         if (nvcfg1 & (1 << 27))
11332                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11333
11334         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11335         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11336         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11337                 tp->nvram_jedecnum = JEDEC_ATMEL;
11338                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11339                 break;
11340         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11341                 tp->nvram_jedecnum = JEDEC_ATMEL;
11342                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11343                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11344                 break;
11345         case FLASH_5752VENDOR_ST_M45PE10:
11346         case FLASH_5752VENDOR_ST_M45PE20:
11347         case FLASH_5752VENDOR_ST_M45PE40:
11348                 tp->nvram_jedecnum = JEDEC_ST;
11349                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11350                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11351                 break;
11352         }
11353
11354         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11355                 tg3_nvram_get_pagesize(tp, nvcfg1);
11356         } else {
11357                 /* For eeprom, set pagesize to maximum eeprom size */
11358                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11359
11360                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11361                 tw32(NVRAM_CFG1, nvcfg1);
11362         }
11363 }
11364
11365 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11366 {
11367         u32 nvcfg1, protect = 0;
11368
11369         nvcfg1 = tr32(NVRAM_CFG1);
11370
11371         /* NVRAM protection for TPM */
11372         if (nvcfg1 & (1 << 27)) {
11373                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11374                 protect = 1;
11375         }
11376
11377         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11378         switch (nvcfg1) {
11379         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11380         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11381         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11382         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11383                 tp->nvram_jedecnum = JEDEC_ATMEL;
11384                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11385                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11386                 tp->nvram_pagesize = 264;
11387                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11388                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11389                         tp->nvram_size = (protect ? 0x3e200 :
11390                                           TG3_NVRAM_SIZE_512KB);
11391                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11392                         tp->nvram_size = (protect ? 0x1f200 :
11393                                           TG3_NVRAM_SIZE_256KB);
11394                 else
11395                         tp->nvram_size = (protect ? 0x1f200 :
11396                                           TG3_NVRAM_SIZE_128KB);
11397                 break;
11398         case FLASH_5752VENDOR_ST_M45PE10:
11399         case FLASH_5752VENDOR_ST_M45PE20:
11400         case FLASH_5752VENDOR_ST_M45PE40:
11401                 tp->nvram_jedecnum = JEDEC_ST;
11402                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11403                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11404                 tp->nvram_pagesize = 256;
11405                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11406                         tp->nvram_size = (protect ?
11407                                           TG3_NVRAM_SIZE_64KB :
11408                                           TG3_NVRAM_SIZE_128KB);
11409                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11410                         tp->nvram_size = (protect ?
11411                                           TG3_NVRAM_SIZE_64KB :
11412                                           TG3_NVRAM_SIZE_256KB);
11413                 else
11414                         tp->nvram_size = (protect ?
11415                                           TG3_NVRAM_SIZE_128KB :
11416                                           TG3_NVRAM_SIZE_512KB);
11417                 break;
11418         }
11419 }
11420
11421 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11422 {
11423         u32 nvcfg1;
11424
11425         nvcfg1 = tr32(NVRAM_CFG1);
11426
11427         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11428         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11429         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11430         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11431         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11432                 tp->nvram_jedecnum = JEDEC_ATMEL;
11433                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11434                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11435
11436                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11437                 tw32(NVRAM_CFG1, nvcfg1);
11438                 break;
11439         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11440         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11441         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11442         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11443                 tp->nvram_jedecnum = JEDEC_ATMEL;
11444                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11445                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11446                 tp->nvram_pagesize = 264;
11447                 break;
11448         case FLASH_5752VENDOR_ST_M45PE10:
11449         case FLASH_5752VENDOR_ST_M45PE20:
11450         case FLASH_5752VENDOR_ST_M45PE40:
11451                 tp->nvram_jedecnum = JEDEC_ST;
11452                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11453                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11454                 tp->nvram_pagesize = 256;
11455                 break;
11456         }
11457 }
11458
11459 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11460 {
11461         u32 nvcfg1, protect = 0;
11462
11463         nvcfg1 = tr32(NVRAM_CFG1);
11464
11465         /* NVRAM protection for TPM */
11466         if (nvcfg1 & (1 << 27)) {
11467                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11468                 protect = 1;
11469         }
11470
11471         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11472         switch (nvcfg1) {
11473         case FLASH_5761VENDOR_ATMEL_ADB021D:
11474         case FLASH_5761VENDOR_ATMEL_ADB041D:
11475         case FLASH_5761VENDOR_ATMEL_ADB081D:
11476         case FLASH_5761VENDOR_ATMEL_ADB161D:
11477         case FLASH_5761VENDOR_ATMEL_MDB021D:
11478         case FLASH_5761VENDOR_ATMEL_MDB041D:
11479         case FLASH_5761VENDOR_ATMEL_MDB081D:
11480         case FLASH_5761VENDOR_ATMEL_MDB161D:
11481                 tp->nvram_jedecnum = JEDEC_ATMEL;
11482                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11483                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11484                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11485                 tp->nvram_pagesize = 256;
11486                 break;
11487         case FLASH_5761VENDOR_ST_A_M45PE20:
11488         case FLASH_5761VENDOR_ST_A_M45PE40:
11489         case FLASH_5761VENDOR_ST_A_M45PE80:
11490         case FLASH_5761VENDOR_ST_A_M45PE16:
11491         case FLASH_5761VENDOR_ST_M_M45PE20:
11492         case FLASH_5761VENDOR_ST_M_M45PE40:
11493         case FLASH_5761VENDOR_ST_M_M45PE80:
11494         case FLASH_5761VENDOR_ST_M_M45PE16:
11495                 tp->nvram_jedecnum = JEDEC_ST;
11496                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11497                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11498                 tp->nvram_pagesize = 256;
11499                 break;
11500         }
11501
11502         if (protect) {
11503                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11504         } else {
11505                 switch (nvcfg1) {
11506                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11507                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11508                 case FLASH_5761VENDOR_ST_A_M45PE16:
11509                 case FLASH_5761VENDOR_ST_M_M45PE16:
11510                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11511                         break;
11512                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11513                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11514                 case FLASH_5761VENDOR_ST_A_M45PE80:
11515                 case FLASH_5761VENDOR_ST_M_M45PE80:
11516                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11517                         break;
11518                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11519                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11520                 case FLASH_5761VENDOR_ST_A_M45PE40:
11521                 case FLASH_5761VENDOR_ST_M_M45PE40:
11522                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11523                         break;
11524                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11525                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11526                 case FLASH_5761VENDOR_ST_A_M45PE20:
11527                 case FLASH_5761VENDOR_ST_M_M45PE20:
11528                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11529                         break;
11530                 }
11531         }
11532 }
11533
11534 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11535 {
11536         tp->nvram_jedecnum = JEDEC_ATMEL;
11537         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11538         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11539 }
11540
11541 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11542 {
11543         u32 nvcfg1;
11544
11545         nvcfg1 = tr32(NVRAM_CFG1);
11546
11547         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11548         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11549         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11550                 tp->nvram_jedecnum = JEDEC_ATMEL;
11551                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11552                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11553
11554                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11555                 tw32(NVRAM_CFG1, nvcfg1);
11556                 return;
11557         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11558         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11559         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11560         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11561         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11562         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11563         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11564                 tp->nvram_jedecnum = JEDEC_ATMEL;
11565                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11566                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11567
11568                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11569                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11570                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11571                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11572                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11573                         break;
11574                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11575                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11576                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11577                         break;
11578                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11579                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11580                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11581                         break;
11582                 }
11583                 break;
11584         case FLASH_5752VENDOR_ST_M45PE10:
11585         case FLASH_5752VENDOR_ST_M45PE20:
11586         case FLASH_5752VENDOR_ST_M45PE40:
11587                 tp->nvram_jedecnum = JEDEC_ST;
11588                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11589                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11590
11591                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11592                 case FLASH_5752VENDOR_ST_M45PE10:
11593                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11594                         break;
11595                 case FLASH_5752VENDOR_ST_M45PE20:
11596                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11597                         break;
11598                 case FLASH_5752VENDOR_ST_M45PE40:
11599                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11600                         break;
11601                 }
11602                 break;
11603         default:
11604                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11605                 return;
11606         }
11607
11608         tg3_nvram_get_pagesize(tp, nvcfg1);
11609         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11610                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11611 }
11612
11613
11614 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11615 {
11616         u32 nvcfg1;
11617
11618         nvcfg1 = tr32(NVRAM_CFG1);
11619
11620         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11621         case FLASH_5717VENDOR_ATMEL_EEPROM:
11622         case FLASH_5717VENDOR_MICRO_EEPROM:
11623                 tp->nvram_jedecnum = JEDEC_ATMEL;
11624                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11625                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11626
11627                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11628                 tw32(NVRAM_CFG1, nvcfg1);
11629                 return;
11630         case FLASH_5717VENDOR_ATMEL_MDB011D:
11631         case FLASH_5717VENDOR_ATMEL_ADB011B:
11632         case FLASH_5717VENDOR_ATMEL_ADB011D:
11633         case FLASH_5717VENDOR_ATMEL_MDB021D:
11634         case FLASH_5717VENDOR_ATMEL_ADB021B:
11635         case FLASH_5717VENDOR_ATMEL_ADB021D:
11636         case FLASH_5717VENDOR_ATMEL_45USPT:
11637                 tp->nvram_jedecnum = JEDEC_ATMEL;
11638                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11639                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11640
11641                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11642                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11643                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11644                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11645                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11646                         break;
11647                 default:
11648                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11649                         break;
11650                 }
11651                 break;
11652         case FLASH_5717VENDOR_ST_M_M25PE10:
11653         case FLASH_5717VENDOR_ST_A_M25PE10:
11654         case FLASH_5717VENDOR_ST_M_M45PE10:
11655         case FLASH_5717VENDOR_ST_A_M45PE10:
11656         case FLASH_5717VENDOR_ST_M_M25PE20:
11657         case FLASH_5717VENDOR_ST_A_M25PE20:
11658         case FLASH_5717VENDOR_ST_M_M45PE20:
11659         case FLASH_5717VENDOR_ST_A_M45PE20:
11660         case FLASH_5717VENDOR_ST_25USPT:
11661         case FLASH_5717VENDOR_ST_45USPT:
11662                 tp->nvram_jedecnum = JEDEC_ST;
11663                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11664                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11665
11666                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11667                 case FLASH_5717VENDOR_ST_M_M25PE20:
11668                 case FLASH_5717VENDOR_ST_A_M25PE20:
11669                 case FLASH_5717VENDOR_ST_M_M45PE20:
11670                 case FLASH_5717VENDOR_ST_A_M45PE20:
11671                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11672                         break;
11673                 default:
11674                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11675                         break;
11676                 }
11677                 break;
11678         default:
11679                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11680                 return;
11681         }
11682
11683         tg3_nvram_get_pagesize(tp, nvcfg1);
11684         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11685                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11686 }
11687
11688 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11689 static void __devinit tg3_nvram_init(struct tg3 *tp)
11690 {
11691         tw32_f(GRC_EEPROM_ADDR,
11692              (EEPROM_ADDR_FSM_RESET |
11693               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11694                EEPROM_ADDR_CLKPERD_SHIFT)));
11695
11696         msleep(1);
11697
11698         /* Enable seeprom accesses. */
11699         tw32_f(GRC_LOCAL_CTRL,
11700              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11701         udelay(100);
11702
11703         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11704             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11705                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11706
11707                 if (tg3_nvram_lock(tp)) {
11708                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11709                                "tg3_nvram_init failed.\n", tp->dev->name);
11710                         return;
11711                 }
11712                 tg3_enable_nvram_access(tp);
11713
11714                 tp->nvram_size = 0;
11715
11716                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11717                         tg3_get_5752_nvram_info(tp);
11718                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11719                         tg3_get_5755_nvram_info(tp);
11720                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11721                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11722                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11723                         tg3_get_5787_nvram_info(tp);
11724                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11725                         tg3_get_5761_nvram_info(tp);
11726                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11727                         tg3_get_5906_nvram_info(tp);
11728                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11729                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11730                         tg3_get_57780_nvram_info(tp);
11731                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11732                         tg3_get_5717_nvram_info(tp);
11733                 else
11734                         tg3_get_nvram_info(tp);
11735
11736                 if (tp->nvram_size == 0)
11737                         tg3_get_nvram_size(tp);
11738
11739                 tg3_disable_nvram_access(tp);
11740                 tg3_nvram_unlock(tp);
11741
11742         } else {
11743                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11744
11745                 tg3_get_eeprom_size(tp);
11746         }
11747 }
11748
11749 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11750                                     u32 offset, u32 len, u8 *buf)
11751 {
11752         int i, j, rc = 0;
11753         u32 val;
11754
11755         for (i = 0; i < len; i += 4) {
11756                 u32 addr;
11757                 __be32 data;
11758
11759                 addr = offset + i;
11760
11761                 memcpy(&data, buf + i, 4);
11762
11763                 /*
11764                  * The SEEPROM interface expects the data to always be opposite
11765                  * the native endian format.  We accomplish this by reversing
11766                  * all the operations that would have been performed on the
11767                  * data from a call to tg3_nvram_read_be32().
11768                  */
11769                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11770
11771                 val = tr32(GRC_EEPROM_ADDR);
11772                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11773
11774                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11775                         EEPROM_ADDR_READ);
11776                 tw32(GRC_EEPROM_ADDR, val |
11777                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11778                         (addr & EEPROM_ADDR_ADDR_MASK) |
11779                         EEPROM_ADDR_START |
11780                         EEPROM_ADDR_WRITE);
11781
11782                 for (j = 0; j < 1000; j++) {
11783                         val = tr32(GRC_EEPROM_ADDR);
11784
11785                         if (val & EEPROM_ADDR_COMPLETE)
11786                                 break;
11787                         msleep(1);
11788                 }
11789                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11790                         rc = -EBUSY;
11791                         break;
11792                 }
11793         }
11794
11795         return rc;
11796 }
11797
11798 /* offset and length are dword aligned */
11799 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11800                 u8 *buf)
11801 {
11802         int ret = 0;
11803         u32 pagesize = tp->nvram_pagesize;
11804         u32 pagemask = pagesize - 1;
11805         u32 nvram_cmd;
11806         u8 *tmp;
11807
11808         tmp = kmalloc(pagesize, GFP_KERNEL);
11809         if (tmp == NULL)
11810                 return -ENOMEM;
11811
11812         while (len) {
11813                 int j;
11814                 u32 phy_addr, page_off, size;
11815
11816                 phy_addr = offset & ~pagemask;
11817
11818                 for (j = 0; j < pagesize; j += 4) {
11819                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11820                                                   (__be32 *) (tmp + j));
11821                         if (ret)
11822                                 break;
11823                 }
11824                 if (ret)
11825                         break;
11826
11827                 page_off = offset & pagemask;
11828                 size = pagesize;
11829                 if (len < size)
11830                         size = len;
11831
11832                 len -= size;
11833
11834                 memcpy(tmp + page_off, buf, size);
11835
11836                 offset = offset + (pagesize - page_off);
11837
11838                 tg3_enable_nvram_access(tp);
11839
11840                 /*
11841                  * Before we can erase the flash page, we need
11842                  * to issue a special "write enable" command.
11843                  */
11844                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11845
11846                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11847                         break;
11848
11849                 /* Erase the target page */
11850                 tw32(NVRAM_ADDR, phy_addr);
11851
11852                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11853                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11854
11855                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11856                         break;
11857
11858                 /* Issue another write enable to start the write. */
11859                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11860
11861                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11862                         break;
11863
11864                 for (j = 0; j < pagesize; j += 4) {
11865                         __be32 data;
11866
11867                         data = *((__be32 *) (tmp + j));
11868
11869                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11870
11871                         tw32(NVRAM_ADDR, phy_addr + j);
11872
11873                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11874                                 NVRAM_CMD_WR;
11875
11876                         if (j == 0)
11877                                 nvram_cmd |= NVRAM_CMD_FIRST;
11878                         else if (j == (pagesize - 4))
11879                                 nvram_cmd |= NVRAM_CMD_LAST;
11880
11881                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11882                                 break;
11883                 }
11884                 if (ret)
11885                         break;
11886         }
11887
11888         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11889         tg3_nvram_exec_cmd(tp, nvram_cmd);
11890
11891         kfree(tmp);
11892
11893         return ret;
11894 }
11895
11896 /* offset and length are dword aligned */
11897 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11898                 u8 *buf)
11899 {
11900         int i, ret = 0;
11901
11902         for (i = 0; i < len; i += 4, offset += 4) {
11903                 u32 page_off, phy_addr, nvram_cmd;
11904                 __be32 data;
11905
11906                 memcpy(&data, buf + i, 4);
11907                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11908
11909                 page_off = offset % tp->nvram_pagesize;
11910
11911                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11912
11913                 tw32(NVRAM_ADDR, phy_addr);
11914
11915                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11916
11917                 if ((page_off == 0) || (i == 0))
11918                         nvram_cmd |= NVRAM_CMD_FIRST;
11919                 if (page_off == (tp->nvram_pagesize - 4))
11920                         nvram_cmd |= NVRAM_CMD_LAST;
11921
11922                 if (i == (len - 4))
11923                         nvram_cmd |= NVRAM_CMD_LAST;
11924
11925                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11926                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11927                     (tp->nvram_jedecnum == JEDEC_ST) &&
11928                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11929
11930                         if ((ret = tg3_nvram_exec_cmd(tp,
11931                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11932                                 NVRAM_CMD_DONE)))
11933
11934                                 break;
11935                 }
11936                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11937                         /* We always do complete word writes to eeprom. */
11938                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11939                 }
11940
11941                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11942                         break;
11943         }
11944         return ret;
11945 }
11946
11947 /* offset and length are dword aligned */
11948 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11949 {
11950         int ret;
11951
11952         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11953                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11954                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11955                 udelay(40);
11956         }
11957
11958         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11959                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11960         }
11961         else {
11962                 u32 grc_mode;
11963
11964                 ret = tg3_nvram_lock(tp);
11965                 if (ret)
11966                         return ret;
11967
11968                 tg3_enable_nvram_access(tp);
11969                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11970                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11971                         tw32(NVRAM_WRITE1, 0x406);
11972
11973                 grc_mode = tr32(GRC_MODE);
11974                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11975
11976                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11977                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11978
11979                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11980                                 buf);
11981                 }
11982                 else {
11983                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11984                                 buf);
11985                 }
11986
11987                 grc_mode = tr32(GRC_MODE);
11988                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11989
11990                 tg3_disable_nvram_access(tp);
11991                 tg3_nvram_unlock(tp);
11992         }
11993
11994         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11995                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11996                 udelay(40);
11997         }
11998
11999         return ret;
12000 }
12001
12002 struct subsys_tbl_ent {
12003         u16 subsys_vendor, subsys_devid;
12004         u32 phy_id;
12005 };
12006
12007 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12008         /* Broadcom boards. */
12009         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12010         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12011         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12012         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
12013         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12014         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12015         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
12016         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12017         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12018         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12019         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12020
12021         /* 3com boards. */
12022         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12023         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12024         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
12025         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12026         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12027
12028         /* DELL boards. */
12029         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12030         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12031         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12032         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12033
12034         /* Compaq boards. */
12035         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12036         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12037         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
12038         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12039         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12040
12041         /* IBM boards. */
12042         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12043 };
12044
12045 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12046 {
12047         int i;
12048
12049         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12050                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12051                      tp->pdev->subsystem_vendor) &&
12052                     (subsys_id_to_phy_id[i].subsys_devid ==
12053                      tp->pdev->subsystem_device))
12054                         return &subsys_id_to_phy_id[i];
12055         }
12056         return NULL;
12057 }
12058
12059 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12060 {
12061         u32 val;
12062         u16 pmcsr;
12063
12064         /* On some early chips the SRAM cannot be accessed in D3hot state,
12065          * so need make sure we're in D0.
12066          */
12067         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12068         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12069         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12070         msleep(1);
12071
12072         /* Make sure register accesses (indirect or otherwise)
12073          * will function correctly.
12074          */
12075         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12076                                tp->misc_host_ctrl);
12077
12078         /* The memory arbiter has to be enabled in order for SRAM accesses
12079          * to succeed.  Normally on powerup the tg3 chip firmware will make
12080          * sure it is enabled, but other entities such as system netboot
12081          * code might disable it.
12082          */
12083         val = tr32(MEMARB_MODE);
12084         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12085
12086         tp->phy_id = PHY_ID_INVALID;
12087         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12088
12089         /* Assume an onboard device and WOL capable by default.  */
12090         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12091
12092         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12093                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12094                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12095                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12096                 }
12097                 val = tr32(VCPU_CFGSHDW);
12098                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12099                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12100                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12101                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12102                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12103                 goto done;
12104         }
12105
12106         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12107         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12108                 u32 nic_cfg, led_cfg;
12109                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12110                 int eeprom_phy_serdes = 0;
12111
12112                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12113                 tp->nic_sram_data_cfg = nic_cfg;
12114
12115                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12116                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12117                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12118                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12119                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12120                     (ver > 0) && (ver < 0x100))
12121                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12122
12123                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12124                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12125
12126                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12127                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12128                         eeprom_phy_serdes = 1;
12129
12130                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12131                 if (nic_phy_id != 0) {
12132                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12133                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12134
12135                         eeprom_phy_id  = (id1 >> 16) << 10;
12136                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12137                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12138                 } else
12139                         eeprom_phy_id = 0;
12140
12141                 tp->phy_id = eeprom_phy_id;
12142                 if (eeprom_phy_serdes) {
12143                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
12144                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12145                         else
12146                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12147                 }
12148
12149                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12150                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12151                                     SHASTA_EXT_LED_MODE_MASK);
12152                 else
12153                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12154
12155                 switch (led_cfg) {
12156                 default:
12157                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12158                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12159                         break;
12160
12161                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12162                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12163                         break;
12164
12165                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12166                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12167
12168                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12169                          * read on some older 5700/5701 bootcode.
12170                          */
12171                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12172                             ASIC_REV_5700 ||
12173                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12174                             ASIC_REV_5701)
12175                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12176
12177                         break;
12178
12179                 case SHASTA_EXT_LED_SHARED:
12180                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12181                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12182                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12183                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12184                                                  LED_CTRL_MODE_PHY_2);
12185                         break;
12186
12187                 case SHASTA_EXT_LED_MAC:
12188                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12189                         break;
12190
12191                 case SHASTA_EXT_LED_COMBO:
12192                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12193                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12194                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12195                                                  LED_CTRL_MODE_PHY_2);
12196                         break;
12197
12198                 }
12199
12200                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12201                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12202                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12203                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12204
12205                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12206                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12207
12208                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12209                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12210                         if ((tp->pdev->subsystem_vendor ==
12211                              PCI_VENDOR_ID_ARIMA) &&
12212                             (tp->pdev->subsystem_device == 0x205a ||
12213                              tp->pdev->subsystem_device == 0x2063))
12214                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12215                 } else {
12216                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12217                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12218                 }
12219
12220                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12221                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12222                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12223                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12224                 }
12225
12226                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12227                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12228                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12229
12230                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12231                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12232                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12233
12234                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12235                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12236                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12237
12238                 if (cfg2 & (1 << 17))
12239                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12240
12241                 /* serdes signal pre-emphasis in register 0x590 set by */
12242                 /* bootcode if bit 18 is set */
12243                 if (cfg2 & (1 << 18))
12244                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12245
12246                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12247                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12248                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12249                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12250
12251                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12252                         u32 cfg3;
12253
12254                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12255                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12256                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12257                 }
12258
12259                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12260                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12261                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12262                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12263                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12264                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12265         }
12266 done:
12267         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12268         device_set_wakeup_enable(&tp->pdev->dev,
12269                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12270 }
12271
12272 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12273 {
12274         int i;
12275         u32 val;
12276
12277         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12278         tw32(OTP_CTRL, cmd);
12279
12280         /* Wait for up to 1 ms for command to execute. */
12281         for (i = 0; i < 100; i++) {
12282                 val = tr32(OTP_STATUS);
12283                 if (val & OTP_STATUS_CMD_DONE)
12284                         break;
12285                 udelay(10);
12286         }
12287
12288         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12289 }
12290
12291 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12292  * configuration is a 32-bit value that straddles the alignment boundary.
12293  * We do two 32-bit reads and then shift and merge the results.
12294  */
12295 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12296 {
12297         u32 bhalf_otp, thalf_otp;
12298
12299         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12300
12301         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12302                 return 0;
12303
12304         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12305
12306         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12307                 return 0;
12308
12309         thalf_otp = tr32(OTP_READ_DATA);
12310
12311         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12312
12313         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12314                 return 0;
12315
12316         bhalf_otp = tr32(OTP_READ_DATA);
12317
12318         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12319 }
12320
12321 static int __devinit tg3_phy_probe(struct tg3 *tp)
12322 {
12323         u32 hw_phy_id_1, hw_phy_id_2;
12324         u32 hw_phy_id, hw_phy_id_masked;
12325         int err;
12326
12327         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12328                 return tg3_phy_init(tp);
12329
12330         /* Reading the PHY ID register can conflict with ASF
12331          * firmware access to the PHY hardware.
12332          */
12333         err = 0;
12334         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12335             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12336                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12337         } else {
12338                 /* Now read the physical PHY_ID from the chip and verify
12339                  * that it is sane.  If it doesn't look good, we fall back
12340                  * to either the hard-coded table based PHY_ID and failing
12341                  * that the value found in the eeprom area.
12342                  */
12343                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12344                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12345
12346                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12347                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12348                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12349
12350                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12351         }
12352
12353         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12354                 tp->phy_id = hw_phy_id;
12355                 if (hw_phy_id_masked == PHY_ID_BCM8002)
12356                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12357                 else
12358                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12359         } else {
12360                 if (tp->phy_id != PHY_ID_INVALID) {
12361                         /* Do nothing, phy ID already set up in
12362                          * tg3_get_eeprom_hw_cfg().
12363                          */
12364                 } else {
12365                         struct subsys_tbl_ent *p;
12366
12367                         /* No eeprom signature?  Try the hardcoded
12368                          * subsys device table.
12369                          */
12370                         p = lookup_by_subsys(tp);
12371                         if (!p)
12372                                 return -ENODEV;
12373
12374                         tp->phy_id = p->phy_id;
12375                         if (!tp->phy_id ||
12376                             tp->phy_id == PHY_ID_BCM8002)
12377                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12378                 }
12379         }
12380
12381         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12382             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12383             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12384                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12385
12386                 tg3_readphy(tp, MII_BMSR, &bmsr);
12387                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12388                     (bmsr & BMSR_LSTATUS))
12389                         goto skip_phy_reset;
12390
12391                 err = tg3_phy_reset(tp);
12392                 if (err)
12393                         return err;
12394
12395                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12396                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12397                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12398                 tg3_ctrl = 0;
12399                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12400                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12401                                     MII_TG3_CTRL_ADV_1000_FULL);
12402                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12403                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12404                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12405                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12406                 }
12407
12408                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12409                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12410                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12411                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12412                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12413
12414                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12415                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12416
12417                         tg3_writephy(tp, MII_BMCR,
12418                                      BMCR_ANENABLE | BMCR_ANRESTART);
12419                 }
12420                 tg3_phy_set_wirespeed(tp);
12421
12422                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12423                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12424                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12425         }
12426
12427 skip_phy_reset:
12428         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12429                 err = tg3_init_5401phy_dsp(tp);
12430                 if (err)
12431                         return err;
12432         }
12433
12434         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12435                 err = tg3_init_5401phy_dsp(tp);
12436         }
12437
12438         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12439                 tp->link_config.advertising =
12440                         (ADVERTISED_1000baseT_Half |
12441                          ADVERTISED_1000baseT_Full |
12442                          ADVERTISED_Autoneg |
12443                          ADVERTISED_FIBRE);
12444         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12445                 tp->link_config.advertising &=
12446                         ~(ADVERTISED_1000baseT_Half |
12447                           ADVERTISED_1000baseT_Full);
12448
12449         return err;
12450 }
12451
12452 static void __devinit tg3_read_partno(struct tg3 *tp)
12453 {
12454         unsigned char vpd_data[TG3_NVM_VPD_LEN];   /* in little-endian format */
12455         unsigned int i;
12456         u32 magic;
12457
12458         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12459             tg3_nvram_read(tp, 0x0, &magic))
12460                 goto out_not_found;
12461
12462         if (magic == TG3_EEPROM_MAGIC) {
12463                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12464                         u32 tmp;
12465
12466                         /* The data is in little-endian format in NVRAM.
12467                          * Use the big-endian read routines to preserve
12468                          * the byte order as it exists in NVRAM.
12469                          */
12470                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12471                                 goto out_not_found;
12472
12473                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12474                 }
12475         } else {
12476                 ssize_t cnt;
12477                 unsigned int pos = 0, i = 0;
12478
12479                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12480                         cnt = pci_read_vpd(tp->pdev, pos,
12481                                            TG3_NVM_VPD_LEN - pos,
12482                                            &vpd_data[pos]);
12483                         if (cnt == -ETIMEDOUT || -EINTR)
12484                                 cnt = 0;
12485                         else if (cnt < 0)
12486                                 goto out_not_found;
12487                 }
12488                 if (pos != TG3_NVM_VPD_LEN)
12489                         goto out_not_found;
12490         }
12491
12492         /* Now parse and find the part number. */
12493         for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
12494                 unsigned char val = vpd_data[i];
12495                 unsigned int block_end;
12496
12497                 if (val == 0x82 || val == 0x91) {
12498                         i = (i + 3 +
12499                              (vpd_data[i + 1] +
12500                               (vpd_data[i + 2] << 8)));
12501                         continue;
12502                 }
12503
12504                 if (val != 0x90)
12505                         goto out_not_found;
12506
12507                 block_end = (i + 3 +
12508                              (vpd_data[i + 1] +
12509                               (vpd_data[i + 2] << 8)));
12510                 i += 3;
12511
12512                 if (block_end > TG3_NVM_VPD_LEN)
12513                         goto out_not_found;
12514
12515                 while (i < (block_end - 2)) {
12516                         if (vpd_data[i + 0] == 'P' &&
12517                             vpd_data[i + 1] == 'N') {
12518                                 int partno_len = vpd_data[i + 2];
12519
12520                                 i += 3;
12521                                 if (partno_len > TG3_BPN_SIZE ||
12522                                     (partno_len + i) > TG3_NVM_VPD_LEN)
12523                                         goto out_not_found;
12524
12525                                 memcpy(tp->board_part_number,
12526                                        &vpd_data[i], partno_len);
12527
12528                                 /* Success. */
12529                                 return;
12530                         }
12531                         i += 3 + vpd_data[i + 2];
12532                 }
12533
12534                 /* Part number not found. */
12535                 goto out_not_found;
12536         }
12537
12538 out_not_found:
12539         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12540                 strcpy(tp->board_part_number, "BCM95906");
12541         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12542                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12543                 strcpy(tp->board_part_number, "BCM57780");
12544         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12545                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12546                 strcpy(tp->board_part_number, "BCM57760");
12547         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12548                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12549                 strcpy(tp->board_part_number, "BCM57790");
12550         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12551                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12552                 strcpy(tp->board_part_number, "BCM57788");
12553         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12554                 strcpy(tp->board_part_number, "BCM57765");
12555         else
12556                 strcpy(tp->board_part_number, "none");
12557 }
12558
12559 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12560 {
12561         u32 val;
12562
12563         if (tg3_nvram_read(tp, offset, &val) ||
12564             (val & 0xfc000000) != 0x0c000000 ||
12565             tg3_nvram_read(tp, offset + 4, &val) ||
12566             val != 0)
12567                 return 0;
12568
12569         return 1;
12570 }
12571
12572 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12573 {
12574         u32 val, offset, start, ver_offset;
12575         int i;
12576         bool newver = false;
12577
12578         if (tg3_nvram_read(tp, 0xc, &offset) ||
12579             tg3_nvram_read(tp, 0x4, &start))
12580                 return;
12581
12582         offset = tg3_nvram_logical_addr(tp, offset);
12583
12584         if (tg3_nvram_read(tp, offset, &val))
12585                 return;
12586
12587         if ((val & 0xfc000000) == 0x0c000000) {
12588                 if (tg3_nvram_read(tp, offset + 4, &val))
12589                         return;
12590
12591                 if (val == 0)
12592                         newver = true;
12593         }
12594
12595         if (newver) {
12596                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12597                         return;
12598
12599                 offset = offset + ver_offset - start;
12600                 for (i = 0; i < 16; i += 4) {
12601                         __be32 v;
12602                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12603                                 return;
12604
12605                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12606                 }
12607         } else {
12608                 u32 major, minor;
12609
12610                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12611                         return;
12612
12613                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12614                         TG3_NVM_BCVER_MAJSFT;
12615                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12616                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12617         }
12618 }
12619
12620 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12621 {
12622         u32 val, major, minor;
12623
12624         /* Use native endian representation */
12625         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12626                 return;
12627
12628         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12629                 TG3_NVM_HWSB_CFG1_MAJSFT;
12630         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12631                 TG3_NVM_HWSB_CFG1_MINSFT;
12632
12633         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12634 }
12635
12636 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12637 {
12638         u32 offset, major, minor, build;
12639
12640         tp->fw_ver[0] = 's';
12641         tp->fw_ver[1] = 'b';
12642         tp->fw_ver[2] = '\0';
12643
12644         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12645                 return;
12646
12647         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12648         case TG3_EEPROM_SB_REVISION_0:
12649                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12650                 break;
12651         case TG3_EEPROM_SB_REVISION_2:
12652                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12653                 break;
12654         case TG3_EEPROM_SB_REVISION_3:
12655                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12656                 break;
12657         default:
12658                 return;
12659         }
12660
12661         if (tg3_nvram_read(tp, offset, &val))
12662                 return;
12663
12664         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12665                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12666         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12667                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12668         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12669
12670         if (minor > 99 || build > 26)
12671                 return;
12672
12673         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12674
12675         if (build > 0) {
12676                 tp->fw_ver[8] = 'a' + build - 1;
12677                 tp->fw_ver[9] = '\0';
12678         }
12679 }
12680
12681 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12682 {
12683         u32 val, offset, start;
12684         int i, vlen;
12685
12686         for (offset = TG3_NVM_DIR_START;
12687              offset < TG3_NVM_DIR_END;
12688              offset += TG3_NVM_DIRENT_SIZE) {
12689                 if (tg3_nvram_read(tp, offset, &val))
12690                         return;
12691
12692                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12693                         break;
12694         }
12695
12696         if (offset == TG3_NVM_DIR_END)
12697                 return;
12698
12699         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12700                 start = 0x08000000;
12701         else if (tg3_nvram_read(tp, offset - 4, &start))
12702                 return;
12703
12704         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12705             !tg3_fw_img_is_valid(tp, offset) ||
12706             tg3_nvram_read(tp, offset + 8, &val))
12707                 return;
12708
12709         offset += val - start;
12710
12711         vlen = strlen(tp->fw_ver);
12712
12713         tp->fw_ver[vlen++] = ',';
12714         tp->fw_ver[vlen++] = ' ';
12715
12716         for (i = 0; i < 4; i++) {
12717                 __be32 v;
12718                 if (tg3_nvram_read_be32(tp, offset, &v))
12719                         return;
12720
12721                 offset += sizeof(v);
12722
12723                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12724                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12725                         break;
12726                 }
12727
12728                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12729                 vlen += sizeof(v);
12730         }
12731 }
12732
12733 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12734 {
12735         int vlen;
12736         u32 apedata;
12737
12738         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12739             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12740                 return;
12741
12742         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12743         if (apedata != APE_SEG_SIG_MAGIC)
12744                 return;
12745
12746         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12747         if (!(apedata & APE_FW_STATUS_READY))
12748                 return;
12749
12750         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12751
12752         vlen = strlen(tp->fw_ver);
12753
12754         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12755                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12756                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12757                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12758                  (apedata & APE_FW_VERSION_BLDMSK));
12759 }
12760
12761 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12762 {
12763         u32 val;
12764
12765         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12766                 tp->fw_ver[0] = 's';
12767                 tp->fw_ver[1] = 'b';
12768                 tp->fw_ver[2] = '\0';
12769
12770                 return;
12771         }
12772
12773         if (tg3_nvram_read(tp, 0, &val))
12774                 return;
12775
12776         if (val == TG3_EEPROM_MAGIC)
12777                 tg3_read_bc_ver(tp);
12778         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12779                 tg3_read_sb_ver(tp, val);
12780         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12781                 tg3_read_hwsb_ver(tp);
12782         else
12783                 return;
12784
12785         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12786              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12787                 return;
12788
12789         tg3_read_mgmtfw_ver(tp);
12790
12791         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12792 }
12793
12794 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12795
12796 static int __devinit tg3_get_invariants(struct tg3 *tp)
12797 {
12798         static struct pci_device_id write_reorder_chipsets[] = {
12799                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12800                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12801                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12802                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12803                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12804                              PCI_DEVICE_ID_VIA_8385_0) },
12805                 { },
12806         };
12807         u32 misc_ctrl_reg;
12808         u32 pci_state_reg, grc_misc_cfg;
12809         u32 val;
12810         u16 pci_cmd;
12811         int err;
12812
12813         /* Force memory write invalidate off.  If we leave it on,
12814          * then on 5700_BX chips we have to enable a workaround.
12815          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12816          * to match the cacheline size.  The Broadcom driver have this
12817          * workaround but turns MWI off all the times so never uses
12818          * it.  This seems to suggest that the workaround is insufficient.
12819          */
12820         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12821         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12822         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12823
12824         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12825          * has the register indirect write enable bit set before
12826          * we try to access any of the MMIO registers.  It is also
12827          * critical that the PCI-X hw workaround situation is decided
12828          * before that as well.
12829          */
12830         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12831                               &misc_ctrl_reg);
12832
12833         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12834                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12835         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12836                 u32 prod_id_asic_rev;
12837
12838                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12839                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12840                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12841                         pci_read_config_dword(tp->pdev,
12842                                               TG3PCI_GEN2_PRODID_ASICREV,
12843                                               &prod_id_asic_rev);
12844                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12845                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12846                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12847                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12848                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12849                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12850                         pci_read_config_dword(tp->pdev,
12851                                               TG3PCI_GEN15_PRODID_ASICREV,
12852                                               &prod_id_asic_rev);
12853                 else
12854                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12855                                               &prod_id_asic_rev);
12856
12857                 tp->pci_chip_rev_id = prod_id_asic_rev;
12858         }
12859
12860         /* Wrong chip ID in 5752 A0. This code can be removed later
12861          * as A0 is not in production.
12862          */
12863         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12864                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12865
12866         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12867          * we need to disable memory and use config. cycles
12868          * only to access all registers. The 5702/03 chips
12869          * can mistakenly decode the special cycles from the
12870          * ICH chipsets as memory write cycles, causing corruption
12871          * of register and memory space. Only certain ICH bridges
12872          * will drive special cycles with non-zero data during the
12873          * address phase which can fall within the 5703's address
12874          * range. This is not an ICH bug as the PCI spec allows
12875          * non-zero address during special cycles. However, only
12876          * these ICH bridges are known to drive non-zero addresses
12877          * during special cycles.
12878          *
12879          * Since special cycles do not cross PCI bridges, we only
12880          * enable this workaround if the 5703 is on the secondary
12881          * bus of these ICH bridges.
12882          */
12883         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12884             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12885                 static struct tg3_dev_id {
12886                         u32     vendor;
12887                         u32     device;
12888                         u32     rev;
12889                 } ich_chipsets[] = {
12890                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12891                           PCI_ANY_ID },
12892                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12893                           PCI_ANY_ID },
12894                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12895                           0xa },
12896                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12897                           PCI_ANY_ID },
12898                         { },
12899                 };
12900                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12901                 struct pci_dev *bridge = NULL;
12902
12903                 while (pci_id->vendor != 0) {
12904                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12905                                                 bridge);
12906                         if (!bridge) {
12907                                 pci_id++;
12908                                 continue;
12909                         }
12910                         if (pci_id->rev != PCI_ANY_ID) {
12911                                 if (bridge->revision > pci_id->rev)
12912                                         continue;
12913                         }
12914                         if (bridge->subordinate &&
12915                             (bridge->subordinate->number ==
12916                              tp->pdev->bus->number)) {
12917
12918                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12919                                 pci_dev_put(bridge);
12920                                 break;
12921                         }
12922                 }
12923         }
12924
12925         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12926                 static struct tg3_dev_id {
12927                         u32     vendor;
12928                         u32     device;
12929                 } bridge_chipsets[] = {
12930                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12931                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12932                         { },
12933                 };
12934                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12935                 struct pci_dev *bridge = NULL;
12936
12937                 while (pci_id->vendor != 0) {
12938                         bridge = pci_get_device(pci_id->vendor,
12939                                                 pci_id->device,
12940                                                 bridge);
12941                         if (!bridge) {
12942                                 pci_id++;
12943                                 continue;
12944                         }
12945                         if (bridge->subordinate &&
12946                             (bridge->subordinate->number <=
12947                              tp->pdev->bus->number) &&
12948                             (bridge->subordinate->subordinate >=
12949                              tp->pdev->bus->number)) {
12950                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12951                                 pci_dev_put(bridge);
12952                                 break;
12953                         }
12954                 }
12955         }
12956
12957         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12958          * DMA addresses > 40-bit. This bridge may have other additional
12959          * 57xx devices behind it in some 4-port NIC designs for example.
12960          * Any tg3 device found behind the bridge will also need the 40-bit
12961          * DMA workaround.
12962          */
12963         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12964             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12965                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12966                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12967                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12968         }
12969         else {
12970                 struct pci_dev *bridge = NULL;
12971
12972                 do {
12973                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12974                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12975                                                 bridge);
12976                         if (bridge && bridge->subordinate &&
12977                             (bridge->subordinate->number <=
12978                              tp->pdev->bus->number) &&
12979                             (bridge->subordinate->subordinate >=
12980                              tp->pdev->bus->number)) {
12981                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12982                                 pci_dev_put(bridge);
12983                                 break;
12984                         }
12985                 } while (bridge);
12986         }
12987
12988         /* Initialize misc host control in PCI block. */
12989         tp->misc_host_ctrl |= (misc_ctrl_reg &
12990                                MISC_HOST_CTRL_CHIPREV);
12991         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12992                                tp->misc_host_ctrl);
12993
12994         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12995             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12996             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12997                 tp->pdev_peer = tg3_find_peer(tp);
12998
12999         /* Intentionally exclude ASIC_REV_5906 */
13000         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13002             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13003             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13005             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13006             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13007             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13008                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13009
13010         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13012             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13013             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13014             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13015                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13016
13017         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13018             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13019                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13020
13021         /* 5700 B0 chips do not support checksumming correctly due
13022          * to hardware bugs.
13023          */
13024         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13025                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13026         else {
13027                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13028                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13029                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13030                         tp->dev->features |= NETIF_F_IPV6_CSUM;
13031         }
13032
13033         /* Determine TSO capabilities */
13034         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13036                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13037         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13038                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13039                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13040         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13041                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13042                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13043                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13044                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13045         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13046                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13047                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13048                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13049                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13050                         tp->fw_needed = FIRMWARE_TG3TSO5;
13051                 else
13052                         tp->fw_needed = FIRMWARE_TG3TSO;
13053         }
13054
13055         tp->irq_max = 1;
13056
13057         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13058                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13059                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13060                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13061                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13062                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13063                      tp->pdev_peer == tp->pdev))
13064                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13065
13066                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13067                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13068                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13069                 }
13070
13071                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13072                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13073                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13074                         tp->irq_max = TG3_IRQ_MAX_VECS;
13075                 }
13076         }
13077
13078         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13079             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13080                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13081         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13082                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13083                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13084         }
13085
13086         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13087             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13088                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13089
13090         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13091              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13092                  (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13093                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13094
13095         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13096                               &pci_state_reg);
13097
13098         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13099         if (tp->pcie_cap != 0) {
13100                 u16 lnkctl;
13101
13102                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13103
13104                 pcie_set_readrq(tp->pdev, 4096);
13105
13106                 pci_read_config_word(tp->pdev,
13107                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13108                                      &lnkctl);
13109                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13111                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13112                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13113                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13114                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13115                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13116                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13117                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13118                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13119                 }
13120         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13121                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13122         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13123                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13124                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13125                 if (!tp->pcix_cap) {
13126                         printk(KERN_ERR PFX "Cannot find PCI-X "
13127                                             "capability, aborting.\n");
13128                         return -EIO;
13129                 }
13130
13131                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13132                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13133         }
13134
13135         /* If we have an AMD 762 or VIA K8T800 chipset, write
13136          * reordering to the mailbox registers done by the host
13137          * controller can cause major troubles.  We read back from
13138          * every mailbox register write to force the writes to be
13139          * posted to the chip in order.
13140          */
13141         if (pci_dev_present(write_reorder_chipsets) &&
13142             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13143                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13144
13145         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13146                              &tp->pci_cacheline_sz);
13147         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13148                              &tp->pci_lat_timer);
13149         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13150             tp->pci_lat_timer < 64) {
13151                 tp->pci_lat_timer = 64;
13152                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13153                                       tp->pci_lat_timer);
13154         }
13155
13156         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13157                 /* 5700 BX chips need to have their TX producer index
13158                  * mailboxes written twice to workaround a bug.
13159                  */
13160                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13161
13162                 /* If we are in PCI-X mode, enable register write workaround.
13163                  *
13164                  * The workaround is to use indirect register accesses
13165                  * for all chip writes not to mailbox registers.
13166                  */
13167                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13168                         u32 pm_reg;
13169
13170                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13171
13172                         /* The chip can have it's power management PCI config
13173                          * space registers clobbered due to this bug.
13174                          * So explicitly force the chip into D0 here.
13175                          */
13176                         pci_read_config_dword(tp->pdev,
13177                                               tp->pm_cap + PCI_PM_CTRL,
13178                                               &pm_reg);
13179                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13180                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13181                         pci_write_config_dword(tp->pdev,
13182                                                tp->pm_cap + PCI_PM_CTRL,
13183                                                pm_reg);
13184
13185                         /* Also, force SERR#/PERR# in PCI command. */
13186                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13187                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13188                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13189                 }
13190         }
13191
13192         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13193                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13194         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13195                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13196
13197         /* Chip-specific fixup from Broadcom driver */
13198         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13199             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13200                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13201                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13202         }
13203
13204         /* Default fast path register access methods */
13205         tp->read32 = tg3_read32;
13206         tp->write32 = tg3_write32;
13207         tp->read32_mbox = tg3_read32;
13208         tp->write32_mbox = tg3_write32;
13209         tp->write32_tx_mbox = tg3_write32;
13210         tp->write32_rx_mbox = tg3_write32;
13211
13212         /* Various workaround register access methods */
13213         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13214                 tp->write32 = tg3_write_indirect_reg32;
13215         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13216                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13217                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13218                 /*
13219                  * Back to back register writes can cause problems on these
13220                  * chips, the workaround is to read back all reg writes
13221                  * except those to mailbox regs.
13222                  *
13223                  * See tg3_write_indirect_reg32().
13224                  */
13225                 tp->write32 = tg3_write_flush_reg32;
13226         }
13227
13228         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13229             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13230                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13231                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13232                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13233         }
13234
13235         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13236                 tp->read32 = tg3_read_indirect_reg32;
13237                 tp->write32 = tg3_write_indirect_reg32;
13238                 tp->read32_mbox = tg3_read_indirect_mbox;
13239                 tp->write32_mbox = tg3_write_indirect_mbox;
13240                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13241                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13242
13243                 iounmap(tp->regs);
13244                 tp->regs = NULL;
13245
13246                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13247                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13248                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13249         }
13250         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13251                 tp->read32_mbox = tg3_read32_mbox_5906;
13252                 tp->write32_mbox = tg3_write32_mbox_5906;
13253                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13254                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13255         }
13256
13257         if (tp->write32 == tg3_write_indirect_reg32 ||
13258             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13259              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13260               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13261                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13262
13263         /* Get eeprom hw config before calling tg3_set_power_state().
13264          * In particular, the TG3_FLG2_IS_NIC flag must be
13265          * determined before calling tg3_set_power_state() so that
13266          * we know whether or not to switch out of Vaux power.
13267          * When the flag is set, it means that GPIO1 is used for eeprom
13268          * write protect and also implies that it is a LOM where GPIOs
13269          * are not used to switch power.
13270          */
13271         tg3_get_eeprom_hw_cfg(tp);
13272
13273         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13274                 /* Allow reads and writes to the
13275                  * APE register and memory space.
13276                  */
13277                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13278                                  PCISTATE_ALLOW_APE_SHMEM_WR;
13279                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13280                                        pci_state_reg);
13281         }
13282
13283         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13284             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13285             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13286             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13287             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13288             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13289                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13290
13291         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13292          * GPIO1 driven high will bring 5700's external PHY out of reset.
13293          * It is also used as eeprom write protect on LOMs.
13294          */
13295         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13296         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13297             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13298                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13299                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13300         /* Unused GPIO3 must be driven as output on 5752 because there
13301          * are no pull-up resistors on unused GPIO pins.
13302          */
13303         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13304                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13305
13306         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13307             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13308                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13309
13310         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13311             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13312                 /* Turn off the debug UART. */
13313                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13314                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13315                         /* Keep VMain power. */
13316                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13317                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13318         }
13319
13320         /* Force the chip into D0. */
13321         err = tg3_set_power_state(tp, PCI_D0);
13322         if (err) {
13323                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13324                        pci_name(tp->pdev));
13325                 return err;
13326         }
13327
13328         /* Derive initial jumbo mode from MTU assigned in
13329          * ether_setup() via the alloc_etherdev() call
13330          */
13331         if (tp->dev->mtu > ETH_DATA_LEN &&
13332             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13333                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13334
13335         /* Determine WakeOnLan speed to use. */
13336         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13337             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13338             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13339             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13340                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13341         } else {
13342                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13343         }
13344
13345         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13346                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13347
13348         /* A few boards don't want Ethernet@WireSpeed phy feature */
13349         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13350             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13351              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13352              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13353             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13354             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13355                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13356
13357         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13358             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13359                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13360         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13361                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13362
13363         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13364             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13365             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13366             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13367             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13368             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13369                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13370                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13371                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13372                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13373                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13374                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13375                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13376                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13377                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13378                 } else
13379                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13380         }
13381
13382         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13383             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13384                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13385                 if (tp->phy_otp == 0)
13386                         tp->phy_otp = TG3_OTP_DEFAULT;
13387         }
13388
13389         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13390                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13391         else
13392                 tp->mi_mode = MAC_MI_MODE_BASE;
13393
13394         tp->coalesce_mode = 0;
13395         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13396             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13397                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13398
13399         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13400             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13401                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13402
13403         err = tg3_mdio_init(tp);
13404         if (err)
13405                 return err;
13406
13407         /* Initialize data/descriptor byte/word swapping. */
13408         val = tr32(GRC_MODE);
13409         val &= GRC_MODE_HOST_STACKUP;
13410         tw32(GRC_MODE, val | tp->grc_mode);
13411
13412         tg3_switch_clocks(tp);
13413
13414         /* Clear this out for sanity. */
13415         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13416
13417         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13418                               &pci_state_reg);
13419         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13420             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13421                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13422
13423                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13424                     chiprevid == CHIPREV_ID_5701_B0 ||
13425                     chiprevid == CHIPREV_ID_5701_B2 ||
13426                     chiprevid == CHIPREV_ID_5701_B5) {
13427                         void __iomem *sram_base;
13428
13429                         /* Write some dummy words into the SRAM status block
13430                          * area, see if it reads back correctly.  If the return
13431                          * value is bad, force enable the PCIX workaround.
13432                          */
13433                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13434
13435                         writel(0x00000000, sram_base);
13436                         writel(0x00000000, sram_base + 4);
13437                         writel(0xffffffff, sram_base + 4);
13438                         if (readl(sram_base) != 0x00000000)
13439                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13440                 }
13441         }
13442
13443         udelay(50);
13444         tg3_nvram_init(tp);
13445
13446         grc_misc_cfg = tr32(GRC_MISC_CFG);
13447         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13448
13449         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13450             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13451              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13452                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13453
13454         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13455             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13456                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13457         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13458                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13459                                       HOSTCC_MODE_CLRTICK_TXBD);
13460
13461                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13462                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13463                                        tp->misc_host_ctrl);
13464         }
13465
13466         /* Preserve the APE MAC_MODE bits */
13467         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13468                 tp->mac_mode = tr32(MAC_MODE) |
13469                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13470         else
13471                 tp->mac_mode = TG3_DEF_MAC_MODE;
13472
13473         /* these are limited to 10/100 only */
13474         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13475              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13476             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13477              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13478              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13479               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13480               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13481             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13482              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13483               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13484               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13485             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13486             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13487                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13488
13489         err = tg3_phy_probe(tp);
13490         if (err) {
13491                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13492                        pci_name(tp->pdev), err);
13493                 /* ... but do not return immediately ... */
13494                 tg3_mdio_fini(tp);
13495         }
13496
13497         tg3_read_partno(tp);
13498         tg3_read_fw_ver(tp);
13499
13500         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13501                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13502         } else {
13503                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13504                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13505                 else
13506                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13507         }
13508
13509         /* 5700 {AX,BX} chips have a broken status block link
13510          * change bit implementation, so we must use the
13511          * status register in those cases.
13512          */
13513         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13514                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13515         else
13516                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13517
13518         /* The led_ctrl is set during tg3_phy_probe, here we might
13519          * have to force the link status polling mechanism based
13520          * upon subsystem IDs.
13521          */
13522         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13523             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13524             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13525                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13526                                   TG3_FLAG_USE_LINKCHG_REG);
13527         }
13528
13529         /* For all SERDES we poll the MAC status register. */
13530         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13531                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13532         else
13533                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13534
13535         tp->rx_offset = NET_IP_ALIGN;
13536         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13537             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13538                 tp->rx_offset = 0;
13539
13540         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13541
13542         /* Increment the rx prod index on the rx std ring by at most
13543          * 8 for these chips to workaround hw errata.
13544          */
13545         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13546             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13547             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13548                 tp->rx_std_max_post = 8;
13549
13550         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13551                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13552                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13553
13554         return err;
13555 }
13556
13557 #ifdef CONFIG_SPARC
13558 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13559 {
13560         struct net_device *dev = tp->dev;
13561         struct pci_dev *pdev = tp->pdev;
13562         struct device_node *dp = pci_device_to_OF_node(pdev);
13563         const unsigned char *addr;
13564         int len;
13565
13566         addr = of_get_property(dp, "local-mac-address", &len);
13567         if (addr && len == 6) {
13568                 memcpy(dev->dev_addr, addr, 6);
13569                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13570                 return 0;
13571         }
13572         return -ENODEV;
13573 }
13574
13575 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13576 {
13577         struct net_device *dev = tp->dev;
13578
13579         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13580         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13581         return 0;
13582 }
13583 #endif
13584
13585 static int __devinit tg3_get_device_address(struct tg3 *tp)
13586 {
13587         struct net_device *dev = tp->dev;
13588         u32 hi, lo, mac_offset;
13589         int addr_ok = 0;
13590
13591 #ifdef CONFIG_SPARC
13592         if (!tg3_get_macaddr_sparc(tp))
13593                 return 0;
13594 #endif
13595
13596         mac_offset = 0x7c;
13597         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13598             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13599                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13600                         mac_offset = 0xcc;
13601                 if (tg3_nvram_lock(tp))
13602                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13603                 else
13604                         tg3_nvram_unlock(tp);
13605         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13606                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13607                         mac_offset = 0xcc;
13608         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13609                 mac_offset = 0x10;
13610
13611         /* First try to get it from MAC address mailbox. */
13612         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13613         if ((hi >> 16) == 0x484b) {
13614                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13615                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13616
13617                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13618                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13619                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13620                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13621                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13622
13623                 /* Some old bootcode may report a 0 MAC address in SRAM */
13624                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13625         }
13626         if (!addr_ok) {
13627                 /* Next, try NVRAM. */
13628                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13629                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13630                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13631                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13632                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13633                 }
13634                 /* Finally just fetch it out of the MAC control regs. */
13635                 else {
13636                         hi = tr32(MAC_ADDR_0_HIGH);
13637                         lo = tr32(MAC_ADDR_0_LOW);
13638
13639                         dev->dev_addr[5] = lo & 0xff;
13640                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13641                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13642                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13643                         dev->dev_addr[1] = hi & 0xff;
13644                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13645                 }
13646         }
13647
13648         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13649 #ifdef CONFIG_SPARC
13650                 if (!tg3_get_default_macaddr_sparc(tp))
13651                         return 0;
13652 #endif
13653                 return -EINVAL;
13654         }
13655         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13656         return 0;
13657 }
13658
13659 #define BOUNDARY_SINGLE_CACHELINE       1
13660 #define BOUNDARY_MULTI_CACHELINE        2
13661
13662 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13663 {
13664         int cacheline_size;
13665         u8 byte;
13666         int goal;
13667
13668         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13669         if (byte == 0)
13670                 cacheline_size = 1024;
13671         else
13672                 cacheline_size = (int) byte * 4;
13673
13674         /* On 5703 and later chips, the boundary bits have no
13675          * effect.
13676          */
13677         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13678             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13679             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13680                 goto out;
13681
13682 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13683         goal = BOUNDARY_MULTI_CACHELINE;
13684 #else
13685 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13686         goal = BOUNDARY_SINGLE_CACHELINE;
13687 #else
13688         goal = 0;
13689 #endif
13690 #endif
13691
13692         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13693             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13694                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13695                 goto out;
13696         }
13697
13698         if (!goal)
13699                 goto out;
13700
13701         /* PCI controllers on most RISC systems tend to disconnect
13702          * when a device tries to burst across a cache-line boundary.
13703          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13704          *
13705          * Unfortunately, for PCI-E there are only limited
13706          * write-side controls for this, and thus for reads
13707          * we will still get the disconnects.  We'll also waste
13708          * these PCI cycles for both read and write for chips
13709          * other than 5700 and 5701 which do not implement the
13710          * boundary bits.
13711          */
13712         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13713             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13714                 switch (cacheline_size) {
13715                 case 16:
13716                 case 32:
13717                 case 64:
13718                 case 128:
13719                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13720                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13721                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13722                         } else {
13723                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13724                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13725                         }
13726                         break;
13727
13728                 case 256:
13729                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13730                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13731                         break;
13732
13733                 default:
13734                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13735                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13736                         break;
13737                 }
13738         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13739                 switch (cacheline_size) {
13740                 case 16:
13741                 case 32:
13742                 case 64:
13743                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13744                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13745                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13746                                 break;
13747                         }
13748                         /* fallthrough */
13749                 case 128:
13750                 default:
13751                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13752                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13753                         break;
13754                 }
13755         } else {
13756                 switch (cacheline_size) {
13757                 case 16:
13758                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13759                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13760                                         DMA_RWCTRL_WRITE_BNDRY_16);
13761                                 break;
13762                         }
13763                         /* fallthrough */
13764                 case 32:
13765                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13766                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13767                                         DMA_RWCTRL_WRITE_BNDRY_32);
13768                                 break;
13769                         }
13770                         /* fallthrough */
13771                 case 64:
13772                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13773                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13774                                         DMA_RWCTRL_WRITE_BNDRY_64);
13775                                 break;
13776                         }
13777                         /* fallthrough */
13778                 case 128:
13779                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13780                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13781                                         DMA_RWCTRL_WRITE_BNDRY_128);
13782                                 break;
13783                         }
13784                         /* fallthrough */
13785                 case 256:
13786                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13787                                 DMA_RWCTRL_WRITE_BNDRY_256);
13788                         break;
13789                 case 512:
13790                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13791                                 DMA_RWCTRL_WRITE_BNDRY_512);
13792                         break;
13793                 case 1024:
13794                 default:
13795                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13796                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13797                         break;
13798                 }
13799         }
13800
13801 out:
13802         return val;
13803 }
13804
13805 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13806 {
13807         struct tg3_internal_buffer_desc test_desc;
13808         u32 sram_dma_descs;
13809         int i, ret;
13810
13811         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13812
13813         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13814         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13815         tw32(RDMAC_STATUS, 0);
13816         tw32(WDMAC_STATUS, 0);
13817
13818         tw32(BUFMGR_MODE, 0);
13819         tw32(FTQ_RESET, 0);
13820
13821         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13822         test_desc.addr_lo = buf_dma & 0xffffffff;
13823         test_desc.nic_mbuf = 0x00002100;
13824         test_desc.len = size;
13825
13826         /*
13827          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13828          * the *second* time the tg3 driver was getting loaded after an
13829          * initial scan.
13830          *
13831          * Broadcom tells me:
13832          *   ...the DMA engine is connected to the GRC block and a DMA
13833          *   reset may affect the GRC block in some unpredictable way...
13834          *   The behavior of resets to individual blocks has not been tested.
13835          *
13836          * Broadcom noted the GRC reset will also reset all sub-components.
13837          */
13838         if (to_device) {
13839                 test_desc.cqid_sqid = (13 << 8) | 2;
13840
13841                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13842                 udelay(40);
13843         } else {
13844                 test_desc.cqid_sqid = (16 << 8) | 7;
13845
13846                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13847                 udelay(40);
13848         }
13849         test_desc.flags = 0x00000005;
13850
13851         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13852                 u32 val;
13853
13854                 val = *(((u32 *)&test_desc) + i);
13855                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13856                                        sram_dma_descs + (i * sizeof(u32)));
13857                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13858         }
13859         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13860
13861         if (to_device) {
13862                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13863         } else {
13864                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13865         }
13866
13867         ret = -ENODEV;
13868         for (i = 0; i < 40; i++) {
13869                 u32 val;
13870
13871                 if (to_device)
13872                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13873                 else
13874                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13875                 if ((val & 0xffff) == sram_dma_descs) {
13876                         ret = 0;
13877                         break;
13878                 }
13879
13880                 udelay(100);
13881         }
13882
13883         return ret;
13884 }
13885
13886 #define TEST_BUFFER_SIZE        0x2000
13887
13888 static int __devinit tg3_test_dma(struct tg3 *tp)
13889 {
13890         dma_addr_t buf_dma;
13891         u32 *buf, saved_dma_rwctrl;
13892         int ret = 0;
13893
13894         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13895         if (!buf) {
13896                 ret = -ENOMEM;
13897                 goto out_nofree;
13898         }
13899
13900         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13901                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13902
13903         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13904
13905         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13906             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13907                 goto out;
13908
13909         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13910                 /* DMA read watermark not used on PCIE */
13911                 tp->dma_rwctrl |= 0x00180000;
13912         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13913                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13914                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13915                         tp->dma_rwctrl |= 0x003f0000;
13916                 else
13917                         tp->dma_rwctrl |= 0x003f000f;
13918         } else {
13919                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13920                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13921                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13922                         u32 read_water = 0x7;
13923
13924                         /* If the 5704 is behind the EPB bridge, we can
13925                          * do the less restrictive ONE_DMA workaround for
13926                          * better performance.
13927                          */
13928                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13929                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13930                                 tp->dma_rwctrl |= 0x8000;
13931                         else if (ccval == 0x6 || ccval == 0x7)
13932                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13933
13934                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13935                                 read_water = 4;
13936                         /* Set bit 23 to enable PCIX hw bug fix */
13937                         tp->dma_rwctrl |=
13938                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13939                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13940                                 (1 << 23);
13941                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13942                         /* 5780 always in PCIX mode */
13943                         tp->dma_rwctrl |= 0x00144000;
13944                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13945                         /* 5714 always in PCIX mode */
13946                         tp->dma_rwctrl |= 0x00148000;
13947                 } else {
13948                         tp->dma_rwctrl |= 0x001b000f;
13949                 }
13950         }
13951
13952         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13953             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13954                 tp->dma_rwctrl &= 0xfffffff0;
13955
13956         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13957             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13958                 /* Remove this if it causes problems for some boards. */
13959                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13960
13961                 /* On 5700/5701 chips, we need to set this bit.
13962                  * Otherwise the chip will issue cacheline transactions
13963                  * to streamable DMA memory with not all the byte
13964                  * enables turned on.  This is an error on several
13965                  * RISC PCI controllers, in particular sparc64.
13966                  *
13967                  * On 5703/5704 chips, this bit has been reassigned
13968                  * a different meaning.  In particular, it is used
13969                  * on those chips to enable a PCI-X workaround.
13970                  */
13971                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13972         }
13973
13974         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13975
13976 #if 0
13977         /* Unneeded, already done by tg3_get_invariants.  */
13978         tg3_switch_clocks(tp);
13979 #endif
13980
13981         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13982             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13983                 goto out;
13984
13985         /* It is best to perform DMA test with maximum write burst size
13986          * to expose the 5700/5701 write DMA bug.
13987          */
13988         saved_dma_rwctrl = tp->dma_rwctrl;
13989         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13990         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13991
13992         while (1) {
13993                 u32 *p = buf, i;
13994
13995                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13996                         p[i] = i;
13997
13998                 /* Send the buffer to the chip. */
13999                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14000                 if (ret) {
14001                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14002                         break;
14003                 }
14004
14005 #if 0
14006                 /* validate data reached card RAM correctly. */
14007                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14008                         u32 val;
14009                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14010                         if (le32_to_cpu(val) != p[i]) {
14011                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
14012                                 /* ret = -ENODEV here? */
14013                         }
14014                         p[i] = 0;
14015                 }
14016 #endif
14017                 /* Now read it back. */
14018                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14019                 if (ret) {
14020                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14021
14022                         break;
14023                 }
14024
14025                 /* Verify it. */
14026                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14027                         if (p[i] == i)
14028                                 continue;
14029
14030                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14031                             DMA_RWCTRL_WRITE_BNDRY_16) {
14032                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14033                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14034                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14035                                 break;
14036                         } else {
14037                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14038                                 ret = -ENODEV;
14039                                 goto out;
14040                         }
14041                 }
14042
14043                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14044                         /* Success. */
14045                         ret = 0;
14046                         break;
14047                 }
14048         }
14049         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14050             DMA_RWCTRL_WRITE_BNDRY_16) {
14051                 static struct pci_device_id dma_wait_state_chipsets[] = {
14052                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14053                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14054                         { },
14055                 };
14056
14057                 /* DMA test passed without adjusting DMA boundary,
14058                  * now look for chipsets that are known to expose the
14059                  * DMA bug without failing the test.
14060                  */
14061                 if (pci_dev_present(dma_wait_state_chipsets)) {
14062                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14063                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14064                 }
14065                 else
14066                         /* Safe to use the calculated DMA boundary. */
14067                         tp->dma_rwctrl = saved_dma_rwctrl;
14068
14069                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14070         }
14071
14072 out:
14073         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14074 out_nofree:
14075         return ret;
14076 }
14077
14078 static void __devinit tg3_init_link_config(struct tg3 *tp)
14079 {
14080         tp->link_config.advertising =
14081                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14082                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14083                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14084                  ADVERTISED_Autoneg | ADVERTISED_MII);
14085         tp->link_config.speed = SPEED_INVALID;
14086         tp->link_config.duplex = DUPLEX_INVALID;
14087         tp->link_config.autoneg = AUTONEG_ENABLE;
14088         tp->link_config.active_speed = SPEED_INVALID;
14089         tp->link_config.active_duplex = DUPLEX_INVALID;
14090         tp->link_config.phy_is_low_power = 0;
14091         tp->link_config.orig_speed = SPEED_INVALID;
14092         tp->link_config.orig_duplex = DUPLEX_INVALID;
14093         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14094 }
14095
14096 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14097 {
14098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14099             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14100                 tp->bufmgr_config.mbuf_read_dma_low_water =
14101                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14102                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14103                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14104                 tp->bufmgr_config.mbuf_high_water =
14105                         DEFAULT_MB_HIGH_WATER_57765;
14106
14107                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14108                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14109                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14110                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14111                 tp->bufmgr_config.mbuf_high_water_jumbo =
14112                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14113         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14114                 tp->bufmgr_config.mbuf_read_dma_low_water =
14115                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14116                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14117                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14118                 tp->bufmgr_config.mbuf_high_water =
14119                         DEFAULT_MB_HIGH_WATER_5705;
14120                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14121                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14122                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14123                         tp->bufmgr_config.mbuf_high_water =
14124                                 DEFAULT_MB_HIGH_WATER_5906;
14125                 }
14126
14127                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14128                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14129                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14130                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14131                 tp->bufmgr_config.mbuf_high_water_jumbo =
14132                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14133         } else {
14134                 tp->bufmgr_config.mbuf_read_dma_low_water =
14135                         DEFAULT_MB_RDMA_LOW_WATER;
14136                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14137                         DEFAULT_MB_MACRX_LOW_WATER;
14138                 tp->bufmgr_config.mbuf_high_water =
14139                         DEFAULT_MB_HIGH_WATER;
14140
14141                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14142                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14143                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14144                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14145                 tp->bufmgr_config.mbuf_high_water_jumbo =
14146                         DEFAULT_MB_HIGH_WATER_JUMBO;
14147         }
14148
14149         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14150         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14151 }
14152
14153 static char * __devinit tg3_phy_string(struct tg3 *tp)
14154 {
14155         switch (tp->phy_id & PHY_ID_MASK) {
14156         case PHY_ID_BCM5400:    return "5400";
14157         case PHY_ID_BCM5401:    return "5401";
14158         case PHY_ID_BCM5411:    return "5411";
14159         case PHY_ID_BCM5701:    return "5701";
14160         case PHY_ID_BCM5703:    return "5703";
14161         case PHY_ID_BCM5704:    return "5704";
14162         case PHY_ID_BCM5705:    return "5705";
14163         case PHY_ID_BCM5750:    return "5750";
14164         case PHY_ID_BCM5752:    return "5752";
14165         case PHY_ID_BCM5714:    return "5714";
14166         case PHY_ID_BCM5780:    return "5780";
14167         case PHY_ID_BCM5755:    return "5755";
14168         case PHY_ID_BCM5787:    return "5787";
14169         case PHY_ID_BCM5784:    return "5784";
14170         case PHY_ID_BCM5756:    return "5722/5756";
14171         case PHY_ID_BCM5906:    return "5906";
14172         case PHY_ID_BCM5761:    return "5761";
14173         case PHY_ID_BCM5717:    return "5717";
14174         case PHY_ID_BCM8002:    return "8002/serdes";
14175         case 0:                 return "serdes";
14176         default:                return "unknown";
14177         }
14178 }
14179
14180 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14181 {
14182         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14183                 strcpy(str, "PCI Express");
14184                 return str;
14185         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14186                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14187
14188                 strcpy(str, "PCIX:");
14189
14190                 if ((clock_ctrl == 7) ||
14191                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14192                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14193                         strcat(str, "133MHz");
14194                 else if (clock_ctrl == 0)
14195                         strcat(str, "33MHz");
14196                 else if (clock_ctrl == 2)
14197                         strcat(str, "50MHz");
14198                 else if (clock_ctrl == 4)
14199                         strcat(str, "66MHz");
14200                 else if (clock_ctrl == 6)
14201                         strcat(str, "100MHz");
14202         } else {
14203                 strcpy(str, "PCI:");
14204                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14205                         strcat(str, "66MHz");
14206                 else
14207                         strcat(str, "33MHz");
14208         }
14209         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14210                 strcat(str, ":32-bit");
14211         else
14212                 strcat(str, ":64-bit");
14213         return str;
14214 }
14215
14216 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14217 {
14218         struct pci_dev *peer;
14219         unsigned int func, devnr = tp->pdev->devfn & ~7;
14220
14221         for (func = 0; func < 8; func++) {
14222                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14223                 if (peer && peer != tp->pdev)
14224                         break;
14225                 pci_dev_put(peer);
14226         }
14227         /* 5704 can be configured in single-port mode, set peer to
14228          * tp->pdev in that case.
14229          */
14230         if (!peer) {
14231                 peer = tp->pdev;
14232                 return peer;
14233         }
14234
14235         /*
14236          * We don't need to keep the refcount elevated; there's no way
14237          * to remove one half of this device without removing the other
14238          */
14239         pci_dev_put(peer);
14240
14241         return peer;
14242 }
14243
14244 static void __devinit tg3_init_coal(struct tg3 *tp)
14245 {
14246         struct ethtool_coalesce *ec = &tp->coal;
14247
14248         memset(ec, 0, sizeof(*ec));
14249         ec->cmd = ETHTOOL_GCOALESCE;
14250         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14251         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14252         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14253         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14254         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14255         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14256         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14257         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14258         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14259
14260         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14261                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14262                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14263                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14264                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14265                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14266         }
14267
14268         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14269                 ec->rx_coalesce_usecs_irq = 0;
14270                 ec->tx_coalesce_usecs_irq = 0;
14271                 ec->stats_block_coalesce_usecs = 0;
14272         }
14273 }
14274
14275 static const struct net_device_ops tg3_netdev_ops = {
14276         .ndo_open               = tg3_open,
14277         .ndo_stop               = tg3_close,
14278         .ndo_start_xmit         = tg3_start_xmit,
14279         .ndo_get_stats          = tg3_get_stats,
14280         .ndo_validate_addr      = eth_validate_addr,
14281         .ndo_set_multicast_list = tg3_set_rx_mode,
14282         .ndo_set_mac_address    = tg3_set_mac_addr,
14283         .ndo_do_ioctl           = tg3_ioctl,
14284         .ndo_tx_timeout         = tg3_tx_timeout,
14285         .ndo_change_mtu         = tg3_change_mtu,
14286 #if TG3_VLAN_TAG_USED
14287         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14288 #endif
14289 #ifdef CONFIG_NET_POLL_CONTROLLER
14290         .ndo_poll_controller    = tg3_poll_controller,
14291 #endif
14292 };
14293
14294 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14295         .ndo_open               = tg3_open,
14296         .ndo_stop               = tg3_close,
14297         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14298         .ndo_get_stats          = tg3_get_stats,
14299         .ndo_validate_addr      = eth_validate_addr,
14300         .ndo_set_multicast_list = tg3_set_rx_mode,
14301         .ndo_set_mac_address    = tg3_set_mac_addr,
14302         .ndo_do_ioctl           = tg3_ioctl,
14303         .ndo_tx_timeout         = tg3_tx_timeout,
14304         .ndo_change_mtu         = tg3_change_mtu,
14305 #if TG3_VLAN_TAG_USED
14306         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14307 #endif
14308 #ifdef CONFIG_NET_POLL_CONTROLLER
14309         .ndo_poll_controller    = tg3_poll_controller,
14310 #endif
14311 };
14312
14313 static int __devinit tg3_init_one(struct pci_dev *pdev,
14314                                   const struct pci_device_id *ent)
14315 {
14316         static int tg3_version_printed = 0;
14317         struct net_device *dev;
14318         struct tg3 *tp;
14319         int i, err, pm_cap;
14320         u32 sndmbx, rcvmbx, intmbx;
14321         char str[40];
14322         u64 dma_mask, persist_dma_mask;
14323
14324         if (tg3_version_printed++ == 0)
14325                 printk(KERN_INFO "%s", version);
14326
14327         err = pci_enable_device(pdev);
14328         if (err) {
14329                 printk(KERN_ERR PFX "Cannot enable PCI device, "
14330                        "aborting.\n");
14331                 return err;
14332         }
14333
14334         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14335         if (err) {
14336                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14337                        "aborting.\n");
14338                 goto err_out_disable_pdev;
14339         }
14340
14341         pci_set_master(pdev);
14342
14343         /* Find power-management capability. */
14344         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14345         if (pm_cap == 0) {
14346                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14347                        "aborting.\n");
14348                 err = -EIO;
14349                 goto err_out_free_res;
14350         }
14351
14352         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14353         if (!dev) {
14354                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14355                 err = -ENOMEM;
14356                 goto err_out_free_res;
14357         }
14358
14359         SET_NETDEV_DEV(dev, &pdev->dev);
14360
14361 #if TG3_VLAN_TAG_USED
14362         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14363 #endif
14364
14365         tp = netdev_priv(dev);
14366         tp->pdev = pdev;
14367         tp->dev = dev;
14368         tp->pm_cap = pm_cap;
14369         tp->rx_mode = TG3_DEF_RX_MODE;
14370         tp->tx_mode = TG3_DEF_TX_MODE;
14371
14372         if (tg3_debug > 0)
14373                 tp->msg_enable = tg3_debug;
14374         else
14375                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14376
14377         /* The word/byte swap controls here control register access byte
14378          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14379          * setting below.
14380          */
14381         tp->misc_host_ctrl =
14382                 MISC_HOST_CTRL_MASK_PCI_INT |
14383                 MISC_HOST_CTRL_WORD_SWAP |
14384                 MISC_HOST_CTRL_INDIR_ACCESS |
14385                 MISC_HOST_CTRL_PCISTATE_RW;
14386
14387         /* The NONFRM (non-frame) byte/word swap controls take effect
14388          * on descriptor entries, anything which isn't packet data.
14389          *
14390          * The StrongARM chips on the board (one for tx, one for rx)
14391          * are running in big-endian mode.
14392          */
14393         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14394                         GRC_MODE_WSWAP_NONFRM_DATA);
14395 #ifdef __BIG_ENDIAN
14396         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14397 #endif
14398         spin_lock_init(&tp->lock);
14399         spin_lock_init(&tp->indirect_lock);
14400         INIT_WORK(&tp->reset_task, tg3_reset_task);
14401
14402         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14403         if (!tp->regs) {
14404                 printk(KERN_ERR PFX "Cannot map device registers, "
14405                        "aborting.\n");
14406                 err = -ENOMEM;
14407                 goto err_out_free_dev;
14408         }
14409
14410         tg3_init_link_config(tp);
14411
14412         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14413         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14414
14415         dev->ethtool_ops = &tg3_ethtool_ops;
14416         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14417         dev->irq = pdev->irq;
14418
14419         err = tg3_get_invariants(tp);
14420         if (err) {
14421                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14422                        "aborting.\n");
14423                 goto err_out_iounmap;
14424         }
14425
14426         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14427             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14428                 dev->netdev_ops = &tg3_netdev_ops;
14429         else
14430                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14431
14432
14433         /* The EPB bridge inside 5714, 5715, and 5780 and any
14434          * device behind the EPB cannot support DMA addresses > 40-bit.
14435          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14436          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14437          * do DMA address check in tg3_start_xmit().
14438          */
14439         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14440                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14441         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14442                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14443 #ifdef CONFIG_HIGHMEM
14444                 dma_mask = DMA_BIT_MASK(64);
14445 #endif
14446         } else
14447                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14448
14449         /* Configure DMA attributes. */
14450         if (dma_mask > DMA_BIT_MASK(32)) {
14451                 err = pci_set_dma_mask(pdev, dma_mask);
14452                 if (!err) {
14453                         dev->features |= NETIF_F_HIGHDMA;
14454                         err = pci_set_consistent_dma_mask(pdev,
14455                                                           persist_dma_mask);
14456                         if (err < 0) {
14457                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14458                                        "DMA for consistent allocations\n");
14459                                 goto err_out_iounmap;
14460                         }
14461                 }
14462         }
14463         if (err || dma_mask == DMA_BIT_MASK(32)) {
14464                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14465                 if (err) {
14466                         printk(KERN_ERR PFX "No usable DMA configuration, "
14467                                "aborting.\n");
14468                         goto err_out_iounmap;
14469                 }
14470         }
14471
14472         tg3_init_bufmgr_config(tp);
14473
14474         /* Selectively allow TSO based on operating conditions */
14475         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14476             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14477                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14478         else {
14479                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14480                 tp->fw_needed = NULL;
14481         }
14482
14483         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14484                 tp->fw_needed = FIRMWARE_TG3;
14485
14486         /* TSO is on by default on chips that support hardware TSO.
14487          * Firmware TSO on older chips gives lower performance, so it
14488          * is off by default, but can be enabled using ethtool.
14489          */
14490         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14491             (dev->features & NETIF_F_IP_CSUM))
14492                 dev->features |= NETIF_F_TSO;
14493
14494         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14495             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14496                 if (dev->features & NETIF_F_IPV6_CSUM)
14497                         dev->features |= NETIF_F_TSO6;
14498                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14499                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14500                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14501                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14502                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14503                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14504                         dev->features |= NETIF_F_TSO_ECN;
14505         }
14506
14507         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14508             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14509             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14510                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14511                 tp->rx_pending = 63;
14512         }
14513
14514         err = tg3_get_device_address(tp);
14515         if (err) {
14516                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14517                        "aborting.\n");
14518                 goto err_out_iounmap;
14519         }
14520
14521         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14522                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14523                 if (!tp->aperegs) {
14524                         printk(KERN_ERR PFX "Cannot map APE registers, "
14525                                "aborting.\n");
14526                         err = -ENOMEM;
14527                         goto err_out_iounmap;
14528                 }
14529
14530                 tg3_ape_lock_init(tp);
14531
14532                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14533                         tg3_read_dash_ver(tp);
14534         }
14535
14536         /*
14537          * Reset chip in case UNDI or EFI driver did not shutdown
14538          * DMA self test will enable WDMAC and we'll see (spurious)
14539          * pending DMA on the PCI bus at that point.
14540          */
14541         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14542             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14543                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14544                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14545         }
14546
14547         err = tg3_test_dma(tp);
14548         if (err) {
14549                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14550                 goto err_out_apeunmap;
14551         }
14552
14553         /* flow control autonegotiation is default behavior */
14554         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14555         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14556
14557         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14558         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14559         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14560         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14561                 struct tg3_napi *tnapi = &tp->napi[i];
14562
14563                 tnapi->tp = tp;
14564                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14565
14566                 tnapi->int_mbox = intmbx;
14567                 if (i < 4)
14568                         intmbx += 0x8;
14569                 else
14570                         intmbx += 0x4;
14571
14572                 tnapi->consmbox = rcvmbx;
14573                 tnapi->prodmbox = sndmbx;
14574
14575                 if (i) {
14576                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14577                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14578                 } else {
14579                         tnapi->coal_now = HOSTCC_MODE_NOW;
14580                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14581                 }
14582
14583                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14584                         break;
14585
14586                 /*
14587                  * If we support MSIX, we'll be using RSS.  If we're using
14588                  * RSS, the first vector only handles link interrupts and the
14589                  * remaining vectors handle rx and tx interrupts.  Reuse the
14590                  * mailbox values for the next iteration.  The values we setup
14591                  * above are still useful for the single vectored mode.
14592                  */
14593                 if (!i)
14594                         continue;
14595
14596                 rcvmbx += 0x8;
14597
14598                 if (sndmbx & 0x4)
14599                         sndmbx -= 0x4;
14600                 else
14601                         sndmbx += 0xc;
14602         }
14603
14604         tg3_init_coal(tp);
14605
14606         pci_set_drvdata(pdev, dev);
14607
14608         err = register_netdev(dev);
14609         if (err) {
14610                 printk(KERN_ERR PFX "Cannot register net device, "
14611                        "aborting.\n");
14612                 goto err_out_apeunmap;
14613         }
14614
14615         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14616                dev->name,
14617                tp->board_part_number,
14618                tp->pci_chip_rev_id,
14619                tg3_bus_string(tp, str),
14620                dev->dev_addr);
14621
14622         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14623                 struct phy_device *phydev;
14624                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14625                 printk(KERN_INFO
14626                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14627                        tp->dev->name, phydev->drv->name,
14628                        dev_name(&phydev->dev));
14629         } else
14630                 printk(KERN_INFO
14631                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14632                        tp->dev->name, tg3_phy_string(tp),
14633                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14634                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14635                          "10/100/1000Base-T")),
14636                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14637
14638         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14639                dev->name,
14640                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14641                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14642                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14643                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14644                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14645         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14646                dev->name, tp->dma_rwctrl,
14647                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14648                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14649
14650         return 0;
14651
14652 err_out_apeunmap:
14653         if (tp->aperegs) {
14654                 iounmap(tp->aperegs);
14655                 tp->aperegs = NULL;
14656         }
14657
14658 err_out_iounmap:
14659         if (tp->regs) {
14660                 iounmap(tp->regs);
14661                 tp->regs = NULL;
14662         }
14663
14664 err_out_free_dev:
14665         free_netdev(dev);
14666
14667 err_out_free_res:
14668         pci_release_regions(pdev);
14669
14670 err_out_disable_pdev:
14671         pci_disable_device(pdev);
14672         pci_set_drvdata(pdev, NULL);
14673         return err;
14674 }
14675
14676 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14677 {
14678         struct net_device *dev = pci_get_drvdata(pdev);
14679
14680         if (dev) {
14681                 struct tg3 *tp = netdev_priv(dev);
14682
14683                 if (tp->fw)
14684                         release_firmware(tp->fw);
14685
14686                 flush_scheduled_work();
14687
14688                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14689                         tg3_phy_fini(tp);
14690                         tg3_mdio_fini(tp);
14691                 }
14692
14693                 unregister_netdev(dev);
14694                 if (tp->aperegs) {
14695                         iounmap(tp->aperegs);
14696                         tp->aperegs = NULL;
14697                 }
14698                 if (tp->regs) {
14699                         iounmap(tp->regs);
14700                         tp->regs = NULL;
14701                 }
14702                 free_netdev(dev);
14703                 pci_release_regions(pdev);
14704                 pci_disable_device(pdev);
14705                 pci_set_drvdata(pdev, NULL);
14706         }
14707 }
14708
14709 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14710 {
14711         struct net_device *dev = pci_get_drvdata(pdev);
14712         struct tg3 *tp = netdev_priv(dev);
14713         pci_power_t target_state;
14714         int err;
14715
14716         /* PCI register 4 needs to be saved whether netif_running() or not.
14717          * MSI address and data need to be saved if using MSI and
14718          * netif_running().
14719          */
14720         pci_save_state(pdev);
14721
14722         if (!netif_running(dev))
14723                 return 0;
14724
14725         flush_scheduled_work();
14726         tg3_phy_stop(tp);
14727         tg3_netif_stop(tp);
14728
14729         del_timer_sync(&tp->timer);
14730
14731         tg3_full_lock(tp, 1);
14732         tg3_disable_ints(tp);
14733         tg3_full_unlock(tp);
14734
14735         netif_device_detach(dev);
14736
14737         tg3_full_lock(tp, 0);
14738         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14739         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14740         tg3_full_unlock(tp);
14741
14742         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14743
14744         err = tg3_set_power_state(tp, target_state);
14745         if (err) {
14746                 int err2;
14747
14748                 tg3_full_lock(tp, 0);
14749
14750                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14751                 err2 = tg3_restart_hw(tp, 1);
14752                 if (err2)
14753                         goto out;
14754
14755                 tp->timer.expires = jiffies + tp->timer_offset;
14756                 add_timer(&tp->timer);
14757
14758                 netif_device_attach(dev);
14759                 tg3_netif_start(tp);
14760
14761 out:
14762                 tg3_full_unlock(tp);
14763
14764                 if (!err2)
14765                         tg3_phy_start(tp);
14766         }
14767
14768         return err;
14769 }
14770
14771 static int tg3_resume(struct pci_dev *pdev)
14772 {
14773         struct net_device *dev = pci_get_drvdata(pdev);
14774         struct tg3 *tp = netdev_priv(dev);
14775         int err;
14776
14777         pci_restore_state(tp->pdev);
14778
14779         if (!netif_running(dev))
14780                 return 0;
14781
14782         err = tg3_set_power_state(tp, PCI_D0);
14783         if (err)
14784                 return err;
14785
14786         netif_device_attach(dev);
14787
14788         tg3_full_lock(tp, 0);
14789
14790         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14791         err = tg3_restart_hw(tp, 1);
14792         if (err)
14793                 goto out;
14794
14795         tp->timer.expires = jiffies + tp->timer_offset;
14796         add_timer(&tp->timer);
14797
14798         tg3_netif_start(tp);
14799
14800 out:
14801         tg3_full_unlock(tp);
14802
14803         if (!err)
14804                 tg3_phy_start(tp);
14805
14806         return err;
14807 }
14808
14809 static struct pci_driver tg3_driver = {
14810         .name           = DRV_MODULE_NAME,
14811         .id_table       = tg3_pci_tbl,
14812         .probe          = tg3_init_one,
14813         .remove         = __devexit_p(tg3_remove_one),
14814         .suspend        = tg3_suspend,
14815         .resume         = tg3_resume
14816 };
14817
14818 static int __init tg3_init(void)
14819 {
14820         return pci_register_driver(&tg3_driver);
14821 }
14822
14823 static void __exit tg3_cleanup(void)
14824 {
14825         pci_unregister_driver(&tg3_driver);
14826 }
14827
14828 module_init(tg3_init);
14829 module_exit(tg3_cleanup);