drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.103"
  72 #define DRV_MODULE_RELDATE      "November 2, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 /* minimum number of free TX descriptors required to wake up TX process */
 141 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 142
 143 #define TG3_RAW_IP_ALIGN 2
 144
 145 /* number of ETHTOOL_GSTATS u64's */
 146 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 147
 148 #define TG3_NUM_TEST            6
 149
 150 #define FIRMWARE_TG3            "tigon/tg3.bin"
 151 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 152 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 153
 154 static char version[] __devinitdata =
 155         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 156
 157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_MODULE_VERSION);
 161 MODULE_FIRMWARE(FIRMWARE_TG3);
 162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 164
 165 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 166
 167 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 168 module_param(tg3_debug, int, 0);
 169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 170
 171 static struct pci_device_id tg3_pci_tbl[] = {
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 245         {}
 246 };
 247
 248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 249
 250 static const struct {
 251         const char string[ETH_GSTRING_LEN];
 252 } ethtool_stats_keys[TG3_NUM_STATS] = {
 253         { "rx_octets" },
 254         { "rx_fragments" },
 255         { "rx_ucast_packets" },
 256         { "rx_mcast_packets" },
 257         { "rx_bcast_packets" },
 258         { "rx_fcs_errors" },
 259         { "rx_align_errors" },
 260         { "rx_xon_pause_rcvd" },
 261         { "rx_xoff_pause_rcvd" },
 262         { "rx_mac_ctrl_rcvd" },
 263         { "rx_xoff_entered" },
 264         { "rx_frame_too_long_errors" },
 265         { "rx_jabbers" },
 266         { "rx_undersize_packets" },
 267         { "rx_in_length_errors" },
 268         { "rx_out_length_errors" },
 269         { "rx_64_or_less_octet_packets" },
 270         { "rx_65_to_127_octet_packets" },
 271         { "rx_128_to_255_octet_packets" },
 272         { "rx_256_to_511_octet_packets" },
 273         { "rx_512_to_1023_octet_packets" },
 274         { "rx_1024_to_1522_octet_packets" },
 275         { "rx_1523_to_2047_octet_packets" },
 276         { "rx_2048_to_4095_octet_packets" },
 277         { "rx_4096_to_8191_octet_packets" },
 278         { "rx_8192_to_9022_octet_packets" },
 279
 280         { "tx_octets" },
 281         { "tx_collisions" },
 282
 283         { "tx_xon_sent" },
 284         { "tx_xoff_sent" },
 285         { "tx_flow_control" },
 286         { "tx_mac_errors" },
 287         { "tx_single_collisions" },
 288         { "tx_mult_collisions" },
 289         { "tx_deferred" },
 290         { "tx_excessive_collisions" },
 291         { "tx_late_collisions" },
 292         { "tx_collide_2times" },
 293         { "tx_collide_3times" },
 294         { "tx_collide_4times" },
 295         { "tx_collide_5times" },
 296         { "tx_collide_6times" },
 297         { "tx_collide_7times" },
 298         { "tx_collide_8times" },
 299         { "tx_collide_9times" },
 300         { "tx_collide_10times" },
 301         { "tx_collide_11times" },
 302         { "tx_collide_12times" },
 303         { "tx_collide_13times" },
 304         { "tx_collide_14times" },
 305         { "tx_collide_15times" },
 306         { "tx_ucast_packets" },
 307         { "tx_mcast_packets" },
 308         { "tx_bcast_packets" },
 309         { "tx_carrier_sense_errors" },
 310         { "tx_discards" },
 311         { "tx_errors" },
 312
 313         { "dma_writeq_full" },
 314         { "dma_write_prioq_full" },
 315         { "rxbds_empty" },
 316         { "rx_discards" },
 317         { "rx_errors" },
 318         { "rx_threshold_hit" },
 319
 320         { "dma_readq_full" },
 321         { "dma_read_prioq_full" },
 322         { "tx_comp_queue_full" },
 323
 324         { "ring_set_send_prod_index" },
 325         { "ring_status_update" },
 326         { "nic_irqs" },
 327         { "nic_avoided_irqs" },
 328         { "nic_tx_threshold_hit" }
 329 };
 330
 331 static const struct {
 332         const char string[ETH_GSTRING_LEN];
 333 } ethtool_test_keys[TG3_NUM_TEST] = {
 334         { "nvram test     (online) " },
 335         { "link test      (online) " },
 336         { "register test  (offline)" },
 337         { "memory test    (offline)" },
 338         { "loopback test  (offline)" },
 339         { "interrupt test (offline)" },
 340 };
 341
 342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 343 {
 344         writel(val, tp->regs + off);
 345 }
 346
 347 static u32 tg3_read32(struct tg3 *tp, u32 off)
 348 {
 349         return (readl(tp->regs + off));
 350 }
 351
 352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 353 {
 354         writel(val, tp->aperegs + off);
 355 }
 356
 357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 358 {
 359         return (readl(tp->aperegs + off));
 360 }
 361
 362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 363 {
 364         unsigned long flags;
 365
 366         spin_lock_irqsave(&tp->indirect_lock, flags);
 367         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 368         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 369         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 370 }
 371
 372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         writel(val, tp->regs + off);
 375         readl(tp->regs + off);
 376 }
 377
 378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 379 {
 380         unsigned long flags;
 381         u32 val;
 382
 383         spin_lock_irqsave(&tp->indirect_lock, flags);
 384         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 385         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 386         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 387         return val;
 388 }
 389
 390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 391 {
 392         unsigned long flags;
 393
 394         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 395                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 396                                        TG3_64BIT_REG_LOW, val);
 397                 return;
 398         }
 399         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 400                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 401                                        TG3_64BIT_REG_LOW, val);
 402                 return;
 403         }
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409
 410         /* In indirect mode when disabling interrupts, we also need
 411          * to clear the interrupt bit in the GRC local ctrl register.
 412          */
 413         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 414             (val == 0x1)) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 416                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 417         }
 418 }
 419
 420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 421 {
 422         unsigned long flags;
 423         u32 val;
 424
 425         spin_lock_irqsave(&tp->indirect_lock, flags);
 426         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 427         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 428         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 429         return val;
 430 }
 431
 432 /* usec_wait specifies the wait time in usec when writing to certain registers
 433  * where it is unsafe to read back the register without some delay.
 434  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 435  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 436  */
 437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 438 {
 439         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 440             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 441                 /* Non-posted methods */
 442                 tp->write32(tp, off, val);
 443         else {
 444                 /* Posted method */
 445                 tg3_write32(tp, off, val);
 446                 if (usec_wait)
 447                         udelay(usec_wait);
 448                 tp->read32(tp, off);
 449         }
 450         /* Wait again after the read for the posted method to guarantee that
 451          * the wait time is met.
 452          */
 453         if (usec_wait)
 454                 udelay(usec_wait);
 455 }
 456
 457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 458 {
 459         tp->write32_mbox(tp, off, val);
 460         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 461             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 462                 tp->read32_mbox(tp, off);
 463 }
 464
 465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 466 {
 467         void __iomem *mbox = tp->regs + off;
 468         writel(val, mbox);
 469         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 470                 writel(val, mbox);
 471         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 472                 readl(mbox);
 473 }
 474
 475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 476 {
 477         return (readl(tp->regs + off + GRCMBOX_BASE));
 478 }
 479
 480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         writel(val, tp->regs + off + GRCMBOX_BASE);
 483 }
 484
 485 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 486 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 487 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 488 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 489 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 490
 491 #define tw32(reg,val)           tp->write32(tp, reg, val)
 492 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 494 #define tr32(reg)               tp->read32(tp, reg)
 495
 496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         unsigned long flags;
 499
 500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 501             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 502                 return;
 503
 504         spin_lock_irqsave(&tp->indirect_lock, flags);
 505         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 508
 509                 /* Always leave this as zero. */
 510                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 511         } else {
 512                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 513                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 514
 515                 /* Always leave this as zero. */
 516                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 517         }
 518         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 519 }
 520
 521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 522 {
 523         unsigned long flags;
 524
 525         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 526             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 527                 *val = 0;
 528                 return;
 529         }
 530
 531         spin_lock_irqsave(&tp->indirect_lock, flags);
 532         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 533                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 534                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 535
 536                 /* Always leave this as zero. */
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 538         } else {
 539                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 540                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 541
 542                 /* Always leave this as zero. */
 543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 544         }
 545         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 546 }
 547
 548 static void tg3_ape_lock_init(struct tg3 *tp)
 549 {
 550         int i;
 551
 552         /* Make sure the driver hasn't any stale locks. */
 553         for (i = 0; i < 8; i++)
 554                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 555                                 APE_LOCK_GRANT_DRIVER);
 556 }
 557
 558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 559 {
 560         int i, off;
 561         int ret = 0;
 562         u32 status;
 563
 564         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 565                 return 0;
 566
 567         switch (locknum) {
 568                 case TG3_APE_LOCK_GRC:
 569                 case TG3_APE_LOCK_MEM:
 570                         break;
 571                 default:
 572                         return -EINVAL;
 573         }
 574
 575         off = 4 * locknum;
 576
 577         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 578
 579         /* Wait for up to 1 millisecond to acquire lock. */
 580         for (i = 0; i < 100; i++) {
 581                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 582                 if (status == APE_LOCK_GRANT_DRIVER)
 583                         break;
 584                 udelay(10);
 585         }
 586
 587         if (status != APE_LOCK_GRANT_DRIVER) {
 588                 /* Revoke the lock request. */
 589                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 590                                 APE_LOCK_GRANT_DRIVER);
 591
 592                 ret = -EBUSY;
 593         }
 594
 595         return ret;
 596 }
 597
 598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 599 {
 600         int off;
 601
 602         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 603                 return;
 604
 605         switch (locknum) {
 606                 case TG3_APE_LOCK_GRC:
 607                 case TG3_APE_LOCK_MEM:
 608                         break;
 609                 default:
 610                         return;
 611         }
 612
 613         off = 4 * locknum;
 614         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 615 }
 616
 617 static void tg3_disable_ints(struct tg3 *tp)
 618 {
 619         int i;
 620
 621         tw32(TG3PCI_MISC_HOST_CTRL,
 622              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 623         for (i = 0; i < tp->irq_max; i++)
 624                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 625 }
 626
 627 static void tg3_enable_ints(struct tg3 *tp)
 628 {
 629         int i;
 630         u32 coal_now = 0;
 631
 632         tp->irq_sync = 0;
 633         wmb();
 634
 635         tw32(TG3PCI_MISC_HOST_CTRL,
 636              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 637
 638         for (i = 0; i < tp->irq_cnt; i++) {
 639                 struct tg3_napi *tnapi = &tp->napi[i];
 640                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 641                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 642                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 643
 644                 coal_now |= tnapi->coal_now;
 645         }
 646
 647         /* Force an initial interrupt */
 648         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 649             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 650                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 651         else
 652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 653                      HOSTCC_MODE_ENABLE | coal_now);
 654 }
 655
 656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 657 {
 658         struct tg3 *tp = tnapi->tp;
 659         struct tg3_hw_status *sblk = tnapi->hw_status;
 660         unsigned int work_exists = 0;
 661
 662         /* check for phy events */
 663         if (!(tp->tg3_flags &
 664               (TG3_FLAG_USE_LINKCHG_REG |
 665                TG3_FLAG_POLL_SERDES))) {
 666                 if (sblk->status & SD_STATUS_LINK_CHG)
 667                         work_exists = 1;
 668         }
 669         /* check for RX/TX work to do */
 670         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 671             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 672                 work_exists = 1;
 673
 674         return work_exists;
 675 }
 676
 677 /* tg3_int_reenable
 678  *  similar to tg3_enable_ints, but it accurately determines whether there
 679  *  is new work pending and can return without flushing the PIO write
 680  *  which reenables interrupts
 681  */
 682 static void tg3_int_reenable(struct tg3_napi *tnapi)
 683 {
 684         struct tg3 *tp = tnapi->tp;
 685
 686         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 687         mmiowb();
 688
 689         /* When doing tagged status, this work check is unnecessary.
 690          * The last_tag we write above tells the chip which piece of
 691          * work we've completed.
 692          */
 693         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 694             tg3_has_work(tnapi))
 695                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 696                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 697 }
 698
 699 static void tg3_napi_disable(struct tg3 *tp)
 700 {
 701         int i;
 702
 703         for (i = tp->irq_cnt - 1; i >= 0; i--)
 704                 napi_disable(&tp->napi[i].napi);
 705 }
 706
 707 static void tg3_napi_enable(struct tg3 *tp)
 708 {
 709         int i;
 710
 711         for (i = 0; i < tp->irq_cnt; i++)
 712                 napi_enable(&tp->napi[i].napi);
 713 }
 714
 715 static inline void tg3_netif_stop(struct tg3 *tp)
 716 {
 717         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 718         tg3_napi_disable(tp);
 719         netif_tx_disable(tp->dev);
 720 }
 721
 722 static inline void tg3_netif_start(struct tg3 *tp)
 723 {
 724         /* NOTE: unconditional netif_tx_wake_all_queues is only
 725          * appropriate so long as all callers are assured to
 726          * have free tx slots (such as after tg3_init_hw)
 727          */
 728         netif_tx_wake_all_queues(tp->dev);
 729
 730         tg3_napi_enable(tp);
 731         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 732         tg3_enable_ints(tp);
 733 }
 734
 735 static void tg3_switch_clocks(struct tg3 *tp)
 736 {
 737         u32 clock_ctrl;
 738         u32 orig_clock_ctrl;
 739
 740         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 741             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 742                 return;
 743
 744         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 745
 746         orig_clock_ctrl = clock_ctrl;
 747         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 748                        CLOCK_CTRL_CLKRUN_OENABLE |
 749                        0x1f);
 750         tp->pci_clock_ctrl = clock_ctrl;
 751
 752         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 753                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 754                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 755                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 756                 }
 757         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 758                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 759                             clock_ctrl |
 760                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 761                             40);
 762                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 763                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 764                             40);
 765         }
 766         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 767 }
 768
 769 #define PHY_BUSY_LOOPS  5000
 770
 771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 772 {
 773         u32 frame_val;
 774         unsigned int loops;
 775         int ret;
 776
 777         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 778                 tw32_f(MAC_MI_MODE,
 779                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 780                 udelay(80);
 781         }
 782
 783         *val = 0x0;
 784
 785         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 786                       MI_COM_PHY_ADDR_MASK);
 787         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 788                       MI_COM_REG_ADDR_MASK);
 789         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 790
 791         tw32_f(MAC_MI_COM, frame_val);
 792
 793         loops = PHY_BUSY_LOOPS;
 794         while (loops != 0) {
 795                 udelay(10);
 796                 frame_val = tr32(MAC_MI_COM);
 797
 798                 if ((frame_val & MI_COM_BUSY) == 0) {
 799                         udelay(5);
 800                         frame_val = tr32(MAC_MI_COM);
 801                         break;
 802                 }
 803                 loops -= 1;
 804         }
 805
 806         ret = -EBUSY;
 807         if (loops != 0) {
 808                 *val = frame_val & MI_COM_DATA_MASK;
 809                 ret = 0;
 810         }
 811
 812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 813                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 814                 udelay(80);
 815         }
 816
 817         return ret;
 818 }
 819
 820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 821 {
 822         u32 frame_val;
 823         unsigned int loops;
 824         int ret;
 825
 826         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 827             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 828                 return 0;
 829
 830         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 831                 tw32_f(MAC_MI_MODE,
 832                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 833                 udelay(80);
 834         }
 835
 836         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 837                       MI_COM_PHY_ADDR_MASK);
 838         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 839                       MI_COM_REG_ADDR_MASK);
 840         frame_val |= (val & MI_COM_DATA_MASK);
 841         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 842
 843         tw32_f(MAC_MI_COM, frame_val);
 844
 845         loops = PHY_BUSY_LOOPS;
 846         while (loops != 0) {
 847                 udelay(10);
 848                 frame_val = tr32(MAC_MI_COM);
 849                 if ((frame_val & MI_COM_BUSY) == 0) {
 850                         udelay(5);
 851                         frame_val = tr32(MAC_MI_COM);
 852                         break;
 853                 }
 854                 loops -= 1;
 855         }
 856
 857         ret = -EBUSY;
 858         if (loops != 0)
 859                 ret = 0;
 860
 861         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 862                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 863                 udelay(80);
 864         }
 865
 866         return ret;
 867 }
 868
 869 static int tg3_bmcr_reset(struct tg3 *tp)
 870 {
 871         u32 phy_control;
 872         int limit, err;
 873
 874         /* OK, reset it, and poll the BMCR_RESET bit until it
 875          * clears or we time out.
 876          */
 877         phy_control = BMCR_RESET;
 878         err = tg3_writephy(tp, MII_BMCR, phy_control);
 879         if (err != 0)
 880                 return -EBUSY;
 881
 882         limit = 5000;
 883         while (limit--) {
 884                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 885                 if (err != 0)
 886                         return -EBUSY;
 887
 888                 if ((phy_control & BMCR_RESET) == 0) {
 889                         udelay(40);
 890                         break;
 891                 }
 892                 udelay(10);
 893         }
 894         if (limit < 0)
 895                 return -EBUSY;
 896
 897         return 0;
 898 }
 899
 900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 901 {
 902         struct tg3 *tp = bp->priv;
 903         u32 val;
 904
 905         spin_lock_bh(&tp->lock);
 906
 907         if (tg3_readphy(tp, reg, &val))
 908                 val = -EIO;
 909
 910         spin_unlock_bh(&tp->lock);
 911
 912         return val;
 913 }
 914
 915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 ret = 0;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_writephy(tp, reg, val))
 923                 ret = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return ret;
 928 }
 929
 930 static int tg3_mdio_reset(struct mii_bus *bp)
 931 {
 932         return 0;
 933 }
 934
 935 static void tg3_mdio_config_5785(struct tg3 *tp)
 936 {
 937         u32 val;
 938         struct phy_device *phydev;
 939
 940         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 941         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 942         case TG3_PHY_ID_BCM50610:
 943         case TG3_PHY_ID_BCM50610M:
 944                 val = MAC_PHYCFG2_50610_LED_MODES;
 945                 break;
 946         case TG3_PHY_ID_BCMAC131:
 947                 val = MAC_PHYCFG2_AC131_LED_MODES;
 948                 break;
 949         case TG3_PHY_ID_RTL8211C:
 950                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 951                 break;
 952         case TG3_PHY_ID_RTL8201E:
 953                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 954                 break;
 955         default:
 956                 return;
 957         }
 958
 959         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 960                 tw32(MAC_PHYCFG2, val);
 961
 962                 val = tr32(MAC_PHYCFG1);
 963                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 964                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 965                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 966                 tw32(MAC_PHYCFG1, val);
 967
 968                 return;
 969         }
 970
 971         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 972                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 973                        MAC_PHYCFG2_FMODE_MASK_MASK |
 974                        MAC_PHYCFG2_GMODE_MASK_MASK |
 975                        MAC_PHYCFG2_ACT_MASK_MASK   |
 976                        MAC_PHYCFG2_QUAL_MASK_MASK |
 977                        MAC_PHYCFG2_INBAND_ENABLE;
 978
 979         tw32(MAC_PHYCFG2, val);
 980
 981         val = tr32(MAC_PHYCFG1);
 982         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 983                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 984         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 985                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 986                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 987                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 988                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 989         }
 990         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 991                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 992         tw32(MAC_PHYCFG1, val);
 993
 994         val = tr32(MAC_EXT_RGMII_MODE);
 995         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 996                  MAC_RGMII_MODE_RX_QUALITY |
 997                  MAC_RGMII_MODE_RX_ACTIVITY |
 998                  MAC_RGMII_MODE_RX_ENG_DET |
 999                  MAC_RGMII_MODE_TX_ENABLE |
1000                  MAC_RGMII_MODE_TX_LOWPWR |
1001                  MAC_RGMII_MODE_TX_RESET);
1002         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1003                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004                         val |= MAC_RGMII_MODE_RX_INT_B |
1005                                MAC_RGMII_MODE_RX_QUALITY |
1006                                MAC_RGMII_MODE_RX_ACTIVITY |
1007                                MAC_RGMII_MODE_RX_ENG_DET;
1008                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009                         val |= MAC_RGMII_MODE_TX_ENABLE |
1010                                MAC_RGMII_MODE_TX_LOWPWR |
1011                                MAC_RGMII_MODE_TX_RESET;
1012         }
1013         tw32(MAC_EXT_RGMII_MODE, val);
1014 }
1015
1016 static void tg3_mdio_start(struct tg3 *tp)
1017 {
1018         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019         tw32_f(MAC_MI_MODE, tp->mi_mode);
1020         udelay(80);
1021
1022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023                 u32 funcnum, is_serdes;
1024
1025                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026                 if (funcnum)
1027                         tp->phy_addr = 2;
1028                 else
1029                         tp->phy_addr = 1;
1030
1031                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032                 if (is_serdes)
1033                         tp->phy_addr += 7;
1034         } else
1035                 tp->phy_addr = TG3_PHY_MII_ADDR;
1036
1037         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039                 tg3_mdio_config_5785(tp);
1040 }
1041
1042 static int tg3_mdio_init(struct tg3 *tp)
1043 {
1044         int i;
1045         u32 reg;
1046         struct phy_device *phydev;
1047
1048         tg3_mdio_start(tp);
1049
1050         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052                 return 0;
1053
1054         tp->mdio_bus = mdiobus_alloc();
1055         if (tp->mdio_bus == NULL)
1056                 return -ENOMEM;
1057
1058         tp->mdio_bus->name     = "tg3 mdio bus";
1059         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1060                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1061         tp->mdio_bus->priv     = tp;
1062         tp->mdio_bus->parent   = &tp->pdev->dev;
1063         tp->mdio_bus->read     = &tg3_mdio_read;
1064         tp->mdio_bus->write    = &tg3_mdio_write;
1065         tp->mdio_bus->reset    = &tg3_mdio_reset;
1066         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1067         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1068
1069         for (i = 0; i < PHY_MAX_ADDR; i++)
1070                 tp->mdio_bus->irq[i] = PHY_POLL;
1071
1072         /* The bus registration will look for all the PHYs on the mdio bus.
1073          * Unfortunately, it does not ensure the PHY is powered up before
1074          * accessing the PHY ID registers.  A chip reset is the
1075          * quickest way to bring the device back to an operational state..
1076          */
1077         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078                 tg3_bmcr_reset(tp);
1079
1080         i = mdiobus_register(tp->mdio_bus);
1081         if (i) {
1082                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083                         tp->dev->name, i);
1084                 mdiobus_free(tp->mdio_bus);
1085                 return i;
1086         }
1087
1088         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1089
1090         if (!phydev || !phydev->drv) {
1091                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092                 mdiobus_unregister(tp->mdio_bus);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return -ENODEV;
1095         }
1096
1097         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1098         case TG3_PHY_ID_BCM57780:
1099                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1100                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1101                 break;
1102         case TG3_PHY_ID_BCM50610:
1103         case TG3_PHY_ID_BCM50610M:
1104                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1105                                      PHY_BRCM_RX_REFCLK_UNUSED |
1106                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1107                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1108                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1109                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1110                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1111                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1112                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1113                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1114                 /* fallthru */
1115         case TG3_PHY_ID_RTL8211C:
1116                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1117                 break;
1118         case TG3_PHY_ID_RTL8201E:
1119         case TG3_PHY_ID_BCMAC131:
1120                 phydev->interface = PHY_INTERFACE_MODE_MII;
1121                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1122                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1123                 break;
1124         }
1125
1126         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1127
1128         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1129                 tg3_mdio_config_5785(tp);
1130
1131         return 0;
1132 }
1133
1134 static void tg3_mdio_fini(struct tg3 *tp)
1135 {
1136         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1137                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1138                 mdiobus_unregister(tp->mdio_bus);
1139                 mdiobus_free(tp->mdio_bus);
1140         }
1141 }
1142
1143 /* tp->lock is held. */
1144 static inline void tg3_generate_fw_event(struct tg3 *tp)
1145 {
1146         u32 val;
1147
1148         val = tr32(GRC_RX_CPU_EVENT);
1149         val |= GRC_RX_CPU_DRIVER_EVENT;
1150         tw32_f(GRC_RX_CPU_EVENT, val);
1151
1152         tp->last_event_jiffies = jiffies;
1153 }
1154
1155 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1156
1157 /* tp->lock is held. */
1158 static void tg3_wait_for_event_ack(struct tg3 *tp)
1159 {
1160         int i;
1161         unsigned int delay_cnt;
1162         long time_remain;
1163
1164         /* If enough time has passed, no wait is necessary. */
1165         time_remain = (long)(tp->last_event_jiffies + 1 +
1166                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1167                       (long)jiffies;
1168         if (time_remain < 0)
1169                 return;
1170
1171         /* Check if we can shorten the wait time. */
1172         delay_cnt = jiffies_to_usecs(time_remain);
1173         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1174                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1175         delay_cnt = (delay_cnt >> 3) + 1;
1176
1177         for (i = 0; i < delay_cnt; i++) {
1178                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1179                         break;
1180                 udelay(8);
1181         }
1182 }
1183
1184 /* tp->lock is held. */
1185 static void tg3_ump_link_report(struct tg3 *tp)
1186 {
1187         u32 reg;
1188         u32 val;
1189
1190         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1191             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1192                 return;
1193
1194         tg3_wait_for_event_ack(tp);
1195
1196         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1197
1198         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1199
1200         val = 0;
1201         if (!tg3_readphy(tp, MII_BMCR, &reg))
1202                 val = reg << 16;
1203         if (!tg3_readphy(tp, MII_BMSR, &reg))
1204                 val |= (reg & 0xffff);
1205         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1206
1207         val = 0;
1208         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1209                 val = reg << 16;
1210         if (!tg3_readphy(tp, MII_LPA, &reg))
1211                 val |= (reg & 0xffff);
1212         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1213
1214         val = 0;
1215         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1216                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1217                         val = reg << 16;
1218                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1219                         val |= (reg & 0xffff);
1220         }
1221         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1222
1223         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1224                 val = reg << 16;
1225         else
1226                 val = 0;
1227         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1228
1229         tg3_generate_fw_event(tp);
1230 }
1231
1232 static void tg3_link_report(struct tg3 *tp)
1233 {
1234         if (!netif_carrier_ok(tp->dev)) {
1235                 if (netif_msg_link(tp))
1236                         printk(KERN_INFO PFX "%s: Link is down.\n",
1237                                tp->dev->name);
1238                 tg3_ump_link_report(tp);
1239         } else if (netif_msg_link(tp)) {
1240                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1241                        tp->dev->name,
1242                        (tp->link_config.active_speed == SPEED_1000 ?
1243                         1000 :
1244                         (tp->link_config.active_speed == SPEED_100 ?
1245                          100 : 10)),
1246                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1247                         "full" : "half"));
1248
1249                 printk(KERN_INFO PFX
1250                        "%s: Flow control is %s for TX and %s for RX.\n",
1251                        tp->dev->name,
1252                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1253                        "on" : "off",
1254                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1255                        "on" : "off");
1256                 tg3_ump_link_report(tp);
1257         }
1258 }
1259
1260 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1261 {
1262         u16 miireg;
1263
1264         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1265                 miireg = ADVERTISE_PAUSE_CAP;
1266         else if (flow_ctrl & FLOW_CTRL_TX)
1267                 miireg = ADVERTISE_PAUSE_ASYM;
1268         else if (flow_ctrl & FLOW_CTRL_RX)
1269                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1270         else
1271                 miireg = 0;
1272
1273         return miireg;
1274 }
1275
1276 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1277 {
1278         u16 miireg;
1279
1280         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1281                 miireg = ADVERTISE_1000XPAUSE;
1282         else if (flow_ctrl & FLOW_CTRL_TX)
1283                 miireg = ADVERTISE_1000XPSE_ASYM;
1284         else if (flow_ctrl & FLOW_CTRL_RX)
1285                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1286         else
1287                 miireg = 0;
1288
1289         return miireg;
1290 }
1291
1292 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1293 {
1294         u8 cap = 0;
1295
1296         if (lcladv & ADVERTISE_1000XPAUSE) {
1297                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1298                         if (rmtadv & LPA_1000XPAUSE)
1299                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1300                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1301                                 cap = FLOW_CTRL_RX;
1302                 } else {
1303                         if (rmtadv & LPA_1000XPAUSE)
1304                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1305                 }
1306         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1308                         cap = FLOW_CTRL_TX;
1309         }
1310
1311         return cap;
1312 }
1313
1314 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1315 {
1316         u8 autoneg;
1317         u8 flowctrl = 0;
1318         u32 old_rx_mode = tp->rx_mode;
1319         u32 old_tx_mode = tp->tx_mode;
1320
1321         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1322                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1323         else
1324                 autoneg = tp->link_config.autoneg;
1325
1326         if (autoneg == AUTONEG_ENABLE &&
1327             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1328                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1329                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1330                 else
1331                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1332         } else
1333                 flowctrl = tp->link_config.flowctrl;
1334
1335         tp->link_config.active_flowctrl = flowctrl;
1336
1337         if (flowctrl & FLOW_CTRL_RX)
1338                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1339         else
1340                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1341
1342         if (old_rx_mode != tp->rx_mode)
1343                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1344
1345         if (flowctrl & FLOW_CTRL_TX)
1346                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1347         else
1348                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1349
1350         if (old_tx_mode != tp->tx_mode)
1351                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1352 }
1353
1354 static void tg3_adjust_link(struct net_device *dev)
1355 {
1356         u8 oldflowctrl, linkmesg = 0;
1357         u32 mac_mode, lcl_adv, rmt_adv;
1358         struct tg3 *tp = netdev_priv(dev);
1359         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1360
1361         spin_lock_bh(&tp->lock);
1362
1363         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1364                                     MAC_MODE_HALF_DUPLEX);
1365
1366         oldflowctrl = tp->link_config.active_flowctrl;
1367
1368         if (phydev->link) {
1369                 lcl_adv = 0;
1370                 rmt_adv = 0;
1371
1372                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1373                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1374                 else if (phydev->speed == SPEED_1000 ||
1375                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1376                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1377                 else
1378                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1379
1380                 if (phydev->duplex == DUPLEX_HALF)
1381                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1382                 else {
1383                         lcl_adv = tg3_advert_flowctrl_1000T(
1384                                   tp->link_config.flowctrl);
1385
1386                         if (phydev->pause)
1387                                 rmt_adv = LPA_PAUSE_CAP;
1388                         if (phydev->asym_pause)
1389                                 rmt_adv |= LPA_PAUSE_ASYM;
1390                 }
1391
1392                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1393         } else
1394                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1395
1396         if (mac_mode != tp->mac_mode) {
1397                 tp->mac_mode = mac_mode;
1398                 tw32_f(MAC_MODE, tp->mac_mode);
1399                 udelay(40);
1400         }
1401
1402         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1403                 if (phydev->speed == SPEED_10)
1404                         tw32(MAC_MI_STAT,
1405                              MAC_MI_STAT_10MBPS_MODE |
1406                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1407                 else
1408                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1409         }
1410
1411         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1412                 tw32(MAC_TX_LENGTHS,
1413                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1414                       (6 << TX_LENGTHS_IPG_SHIFT) |
1415                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1416         else
1417                 tw32(MAC_TX_LENGTHS,
1418                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1419                       (6 << TX_LENGTHS_IPG_SHIFT) |
1420                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1421
1422         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1423             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1424             phydev->speed != tp->link_config.active_speed ||
1425             phydev->duplex != tp->link_config.active_duplex ||
1426             oldflowctrl != tp->link_config.active_flowctrl)
1427             linkmesg = 1;
1428
1429         tp->link_config.active_speed = phydev->speed;
1430         tp->link_config.active_duplex = phydev->duplex;
1431
1432         spin_unlock_bh(&tp->lock);
1433
1434         if (linkmesg)
1435                 tg3_link_report(tp);
1436 }
1437
1438 static int tg3_phy_init(struct tg3 *tp)
1439 {
1440         struct phy_device *phydev;
1441
1442         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1443                 return 0;
1444
1445         /* Bring the PHY back to a known state. */
1446         tg3_bmcr_reset(tp);
1447
1448         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1449
1450         /* Attach the MAC to the PHY. */
1451         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1452                              phydev->dev_flags, phydev->interface);
1453         if (IS_ERR(phydev)) {
1454                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1455                 return PTR_ERR(phydev);
1456         }
1457
1458         /* Mask with MAC supported features. */
1459         switch (phydev->interface) {
1460         case PHY_INTERFACE_MODE_GMII:
1461         case PHY_INTERFACE_MODE_RGMII:
1462                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1463                         phydev->supported &= (PHY_GBIT_FEATURES |
1464                                               SUPPORTED_Pause |
1465                                               SUPPORTED_Asym_Pause);
1466                         break;
1467                 }
1468                 /* fallthru */
1469         case PHY_INTERFACE_MODE_MII:
1470                 phydev->supported &= (PHY_BASIC_FEATURES |
1471                                       SUPPORTED_Pause |
1472                                       SUPPORTED_Asym_Pause);
1473                 break;
1474         default:
1475                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1476                 return -EINVAL;
1477         }
1478
1479         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1480
1481         phydev->advertising = phydev->supported;
1482
1483         return 0;
1484 }
1485
1486 static void tg3_phy_start(struct tg3 *tp)
1487 {
1488         struct phy_device *phydev;
1489
1490         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1491                 return;
1492
1493         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1494
1495         if (tp->link_config.phy_is_low_power) {
1496                 tp->link_config.phy_is_low_power = 0;
1497                 phydev->speed = tp->link_config.orig_speed;
1498                 phydev->duplex = tp->link_config.orig_duplex;
1499                 phydev->autoneg = tp->link_config.orig_autoneg;
1500                 phydev->advertising = tp->link_config.orig_advertising;
1501         }
1502
1503         phy_start(phydev);
1504
1505         phy_start_aneg(phydev);
1506 }
1507
1508 static void tg3_phy_stop(struct tg3 *tp)
1509 {
1510         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511                 return;
1512
1513         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1514 }
1515
1516 static void tg3_phy_fini(struct tg3 *tp)
1517 {
1518         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1519                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1520                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1521         }
1522 }
1523
1524 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1525 {
1526         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1527         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1528 }
1529
1530 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1531 {
1532         u32 phytest;
1533
1534         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1535                 u32 phy;
1536
1537                 tg3_writephy(tp, MII_TG3_FET_TEST,
1538                              phytest | MII_TG3_FET_SHADOW_EN);
1539                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1540                         if (enable)
1541                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1542                         else
1543                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1544                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1545                 }
1546                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1547         }
1548 }
1549
1550 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1551 {
1552         u32 reg;
1553
1554         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1555                 return;
1556
1557         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1558                 tg3_phy_fet_toggle_apd(tp, enable);
1559                 return;
1560         }
1561
1562         reg = MII_TG3_MISC_SHDW_WREN |
1563               MII_TG3_MISC_SHDW_SCR5_SEL |
1564               MII_TG3_MISC_SHDW_SCR5_LPED |
1565               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1566               MII_TG3_MISC_SHDW_SCR5_SDTL |
1567               MII_TG3_MISC_SHDW_SCR5_C125OE;
1568         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1569                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1570
1571         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1572
1573
1574         reg = MII_TG3_MISC_SHDW_WREN |
1575               MII_TG3_MISC_SHDW_APD_SEL |
1576               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1577         if (enable)
1578                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1579
1580         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581 }
1582
1583 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1584 {
1585         u32 phy;
1586
1587         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1588             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1589                 return;
1590
1591         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1592                 u32 ephy;
1593
1594                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1595                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1596
1597                         tg3_writephy(tp, MII_TG3_FET_TEST,
1598                                      ephy | MII_TG3_FET_SHADOW_EN);
1599                         if (!tg3_readphy(tp, reg, &phy)) {
1600                                 if (enable)
1601                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1602                                 else
1603                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1604                                 tg3_writephy(tp, reg, phy);
1605                         }
1606                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1607                 }
1608         } else {
1609                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1610                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1611                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1612                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1613                         if (enable)
1614                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1615                         else
1616                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1617                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1618                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1619                 }
1620         }
1621 }
1622
1623 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1624 {
1625         u32 val;
1626
1627         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1628                 return;
1629
1630         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1631             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1632                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1633                              (val | (1 << 15) | (1 << 4)));
1634 }
1635
1636 static void tg3_phy_apply_otp(struct tg3 *tp)
1637 {
1638         u32 otp, phy;
1639
1640         if (!tp->phy_otp)
1641                 return;
1642
1643         otp = tp->phy_otp;
1644
1645         /* Enable SM_DSP clock and tx 6dB coding. */
1646         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1647               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1648               MII_TG3_AUXCTL_ACTL_TX_6DB;
1649         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1650
1651         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1652         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1653         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1654
1655         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1656               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1657         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1658
1659         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1660         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1661         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1662
1663         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1664         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1665
1666         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1667         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1668
1669         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1670               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1671         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1672
1673         /* Turn off SM_DSP clock. */
1674         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1675               MII_TG3_AUXCTL_ACTL_TX_6DB;
1676         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1677 }
1678
1679 static int tg3_wait_macro_done(struct tg3 *tp)
1680 {
1681         int limit = 100;
1682
1683         while (limit--) {
1684                 u32 tmp32;
1685
1686                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1687                         if ((tmp32 & 0x1000) == 0)
1688                                 break;
1689                 }
1690         }
1691         if (limit < 0)
1692                 return -EBUSY;
1693
1694         return 0;
1695 }
1696
1697 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1698 {
1699         static const u32 test_pat[4][6] = {
1700         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1701         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1702         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1703         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1704         };
1705         int chan;
1706
1707         for (chan = 0; chan < 4; chan++) {
1708                 int i;
1709
1710                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1711                              (chan * 0x2000) | 0x0200);
1712                 tg3_writephy(tp, 0x16, 0x0002);
1713
1714                 for (i = 0; i < 6; i++)
1715                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1716                                      test_pat[chan][i]);
1717
1718                 tg3_writephy(tp, 0x16, 0x0202);
1719                 if (tg3_wait_macro_done(tp)) {
1720                         *resetp = 1;
1721                         return -EBUSY;
1722                 }
1723
1724                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1725                              (chan * 0x2000) | 0x0200);
1726                 tg3_writephy(tp, 0x16, 0x0082);
1727                 if (tg3_wait_macro_done(tp)) {
1728                         *resetp = 1;
1729                         return -EBUSY;
1730                 }
1731
1732                 tg3_writephy(tp, 0x16, 0x0802);
1733                 if (tg3_wait_macro_done(tp)) {
1734                         *resetp = 1;
1735                         return -EBUSY;
1736                 }
1737
1738                 for (i = 0; i < 6; i += 2) {
1739                         u32 low, high;
1740
1741                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1742                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1743                             tg3_wait_macro_done(tp)) {
1744                                 *resetp = 1;
1745                                 return -EBUSY;
1746                         }
1747                         low &= 0x7fff;
1748                         high &= 0x000f;
1749                         if (low != test_pat[chan][i] ||
1750                             high != test_pat[chan][i+1]) {
1751                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1752                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1753                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1754
1755                                 return -EBUSY;
1756                         }
1757                 }
1758         }
1759
1760         return 0;
1761 }
1762
1763 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1764 {
1765         int chan;
1766
1767         for (chan = 0; chan < 4; chan++) {
1768                 int i;
1769
1770                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1771                              (chan * 0x2000) | 0x0200);
1772                 tg3_writephy(tp, 0x16, 0x0002);
1773                 for (i = 0; i < 6; i++)
1774                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1775                 tg3_writephy(tp, 0x16, 0x0202);
1776                 if (tg3_wait_macro_done(tp))
1777                         return -EBUSY;
1778         }
1779
1780         return 0;
1781 }
1782
1783 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1784 {
1785         u32 reg32, phy9_orig;
1786         int retries, do_phy_reset, err;
1787
1788         retries = 10;
1789         do_phy_reset = 1;
1790         do {
1791                 if (do_phy_reset) {
1792                         err = tg3_bmcr_reset(tp);
1793                         if (err)
1794                                 return err;
1795                         do_phy_reset = 0;
1796                 }
1797
1798                 /* Disable transmitter and interrupt.  */
1799                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1800                         continue;
1801
1802                 reg32 |= 0x3000;
1803                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1804
1805                 /* Set full-duplex, 1000 mbps.  */
1806                 tg3_writephy(tp, MII_BMCR,
1807                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1808
1809                 /* Set to master mode.  */
1810                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1811                         continue;
1812
1813                 tg3_writephy(tp, MII_TG3_CTRL,
1814                              (MII_TG3_CTRL_AS_MASTER |
1815                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1816
1817                 /* Enable SM_DSP_CLOCK and 6dB.  */
1818                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1819
1820                 /* Block the PHY control access.  */
1821                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1822                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1823
1824                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1825                 if (!err)
1826                         break;
1827         } while (--retries);
1828
1829         err = tg3_phy_reset_chanpat(tp);
1830         if (err)
1831                 return err;
1832
1833         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1834         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1835
1836         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1837         tg3_writephy(tp, 0x16, 0x0000);
1838
1839         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1840             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1841                 /* Set Extended packet length bit for jumbo frames */
1842                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1843         }
1844         else {
1845                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1846         }
1847
1848         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1849
1850         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1851                 reg32 &= ~0x3000;
1852                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1853         } else if (!err)
1854                 err = -EBUSY;
1855
1856         return err;
1857 }
1858
1859 /* This will reset the tigon3 PHY if there is no valid
1860  * link unless the FORCE argument is non-zero.
1861  */
1862 static int tg3_phy_reset(struct tg3 *tp)
1863 {
1864         u32 cpmuctrl;
1865         u32 phy_status;
1866         int err;
1867
1868         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1869                 u32 val;
1870
1871                 val = tr32(GRC_MISC_CFG);
1872                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1873                 udelay(40);
1874         }
1875         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1876         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1877         if (err != 0)
1878                 return -EBUSY;
1879
1880         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1881                 netif_carrier_off(tp->dev);
1882                 tg3_link_report(tp);
1883         }
1884
1885         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1886             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1887             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1888                 err = tg3_phy_reset_5703_4_5(tp);
1889                 if (err)
1890                         return err;
1891                 goto out;
1892         }
1893
1894         cpmuctrl = 0;
1895         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1896             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1897                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1898                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1899                         tw32(TG3_CPMU_CTRL,
1900                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1901         }
1902
1903         err = tg3_bmcr_reset(tp);
1904         if (err)
1905                 return err;
1906
1907         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1908                 u32 phy;
1909
1910                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1911                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1912
1913                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1914         }
1915
1916         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1917             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1918                 u32 val;
1919
1920                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1921                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1922                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1923                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1924                         udelay(40);
1925                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1926                 }
1927         }
1928
1929         tg3_phy_apply_otp(tp);
1930
1931         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1932                 tg3_phy_toggle_apd(tp, true);
1933         else
1934                 tg3_phy_toggle_apd(tp, false);
1935
1936 out:
1937         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1939                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1940                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1941                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1942                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1943                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1944         }
1945         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1946                 tg3_writephy(tp, 0x1c, 0x8d68);
1947                 tg3_writephy(tp, 0x1c, 0x8d68);
1948         }
1949         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1950                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1951                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1952                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1953                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1954                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1955                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1956                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1957                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958         }
1959         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1961                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1962                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1963                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1964                         tg3_writephy(tp, MII_TG3_TEST1,
1965                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1966                 } else
1967                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1969         }
1970         /* Set Extended packet length bit (bit 14) on all chips that */
1971         /* support jumbo frames */
1972         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1973                 /* Cannot do read-modify-write on 5401 */
1974                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1975         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1976                 u32 phy_reg;
1977
1978                 /* Set bit 14 with read-modify-write to preserve other bits */
1979                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1980                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1981                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1982         }
1983
1984         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1985          * jumbo frames transmission.
1986          */
1987         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1988                 u32 phy_reg;
1989
1990                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1991                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1992                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1993         }
1994
1995         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1996                 /* adjust output voltage */
1997                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1998         }
1999
2000         tg3_phy_toggle_automdix(tp, 1);
2001         tg3_phy_set_wirespeed(tp);
2002         return 0;
2003 }
2004
2005 static void tg3_frob_aux_power(struct tg3 *tp)
2006 {
2007         struct tg3 *tp_peer = tp;
2008
2009         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2010                 return;
2011
2012         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2013             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2015                 struct net_device *dev_peer;
2016
2017                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2018                 /* remove_one() may have been run on the peer. */
2019                 if (!dev_peer)
2020                         tp_peer = tp;
2021                 else
2022                         tp_peer = netdev_priv(dev_peer);
2023         }
2024
2025         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2026             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2027             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2028             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2029                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2030                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2031                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2032                                     (GRC_LCLCTRL_GPIO_OE0 |
2033                                      GRC_LCLCTRL_GPIO_OE1 |
2034                                      GRC_LCLCTRL_GPIO_OE2 |
2035                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2036                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2037                                     100);
2038                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2039                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2040                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2041                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2042                                              GRC_LCLCTRL_GPIO_OE1 |
2043                                              GRC_LCLCTRL_GPIO_OE2 |
2044                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2045                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2046                                              tp->grc_local_ctrl;
2047                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2048
2049                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2050                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2051
2052                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2053                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2054                 } else {
2055                         u32 no_gpio2;
2056                         u32 grc_local_ctrl = 0;
2057
2058                         if (tp_peer != tp &&
2059                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2060                                 return;
2061
2062                         /* Workaround to prevent overdrawing Amps. */
2063                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2064                             ASIC_REV_5714) {
2065                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2066                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067                                             grc_local_ctrl, 100);
2068                         }
2069
2070                         /* On 5753 and variants, GPIO2 cannot be used. */
2071                         no_gpio2 = tp->nic_sram_data_cfg &
2072                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2073
2074                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2075                                          GRC_LCLCTRL_GPIO_OE1 |
2076                                          GRC_LCLCTRL_GPIO_OE2 |
2077                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2078                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2079                         if (no_gpio2) {
2080                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2081                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2082                         }
2083                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2084                                                     grc_local_ctrl, 100);
2085
2086                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2087
2088                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089                                                     grc_local_ctrl, 100);
2090
2091                         if (!no_gpio2) {
2092                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2093                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094                                             grc_local_ctrl, 100);
2095                         }
2096                 }
2097         } else {
2098                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2099                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2100                         if (tp_peer != tp &&
2101                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2102                                 return;
2103
2104                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105                                     (GRC_LCLCTRL_GPIO_OE1 |
2106                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2107
2108                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109                                     GRC_LCLCTRL_GPIO_OE1, 100);
2110
2111                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112                                     (GRC_LCLCTRL_GPIO_OE1 |
2113                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2114                 }
2115         }
2116 }
2117
2118 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2119 {
2120         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2121                 return 1;
2122         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2123                 if (speed != SPEED_10)
2124                         return 1;
2125         } else if (speed == SPEED_10)
2126                 return 1;
2127
2128         return 0;
2129 }
2130
2131 static int tg3_setup_phy(struct tg3 *, int);
2132
2133 #define RESET_KIND_SHUTDOWN     0
2134 #define RESET_KIND_INIT         1
2135 #define RESET_KIND_SUSPEND      2
2136
2137 static void tg3_write_sig_post_reset(struct tg3 *, int);
2138 static int tg3_halt_cpu(struct tg3 *, u32);
2139
2140 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2141 {
2142         u32 val;
2143
2144         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2146                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2147                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2148
2149                         sg_dig_ctrl |=
2150                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2151                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2152                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2153                 }
2154                 return;
2155         }
2156
2157         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2158                 tg3_bmcr_reset(tp);
2159                 val = tr32(GRC_MISC_CFG);
2160                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2161                 udelay(40);
2162                 return;
2163         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2164                 u32 phytest;
2165                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2166                         u32 phy;
2167
2168                         tg3_writephy(tp, MII_ADVERTISE, 0);
2169                         tg3_writephy(tp, MII_BMCR,
2170                                      BMCR_ANENABLE | BMCR_ANRESTART);
2171
2172                         tg3_writephy(tp, MII_TG3_FET_TEST,
2173                                      phytest | MII_TG3_FET_SHADOW_EN);
2174                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2175                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2176                                 tg3_writephy(tp,
2177                                              MII_TG3_FET_SHDW_AUXMODE4,
2178                                              phy);
2179                         }
2180                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2181                 }
2182                 return;
2183         } else if (do_low_power) {
2184                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2185                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2186
2187                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2188                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2189                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2190                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2191                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2192         }
2193
2194         /* The PHY should not be powered down on some chips because
2195          * of bugs.
2196          */
2197         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2198             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2199             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2200              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2201                 return;
2202
2203         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2204             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2205                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2206                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2207                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2208                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2209         }
2210
2211         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2212 }
2213
2214 /* tp->lock is held. */
2215 static int tg3_nvram_lock(struct tg3 *tp)
2216 {
2217         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2218                 int i;
2219
2220                 if (tp->nvram_lock_cnt == 0) {
2221                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2222                         for (i = 0; i < 8000; i++) {
2223                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2224                                         break;
2225                                 udelay(20);
2226                         }
2227                         if (i == 8000) {
2228                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2229                                 return -ENODEV;
2230                         }
2231                 }
2232                 tp->nvram_lock_cnt++;
2233         }
2234         return 0;
2235 }
2236
2237 /* tp->lock is held. */
2238 static void tg3_nvram_unlock(struct tg3 *tp)
2239 {
2240         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2241                 if (tp->nvram_lock_cnt > 0)
2242                         tp->nvram_lock_cnt--;
2243                 if (tp->nvram_lock_cnt == 0)
2244                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2245         }
2246 }
2247
2248 /* tp->lock is held. */
2249 static void tg3_enable_nvram_access(struct tg3 *tp)
2250 {
2251         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2252             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2253                 u32 nvaccess = tr32(NVRAM_ACCESS);
2254
2255                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2256         }
2257 }
2258
2259 /* tp->lock is held. */
2260 static void tg3_disable_nvram_access(struct tg3 *tp)
2261 {
2262         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2263             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2264                 u32 nvaccess = tr32(NVRAM_ACCESS);
2265
2266                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2267         }
2268 }
2269
2270 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2271                                         u32 offset, u32 *val)
2272 {
2273         u32 tmp;
2274         int i;
2275
2276         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2277                 return -EINVAL;
2278
2279         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2280                                         EEPROM_ADDR_DEVID_MASK |
2281                                         EEPROM_ADDR_READ);
2282         tw32(GRC_EEPROM_ADDR,
2283              tmp |
2284              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2285              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2286               EEPROM_ADDR_ADDR_MASK) |
2287              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2288
2289         for (i = 0; i < 1000; i++) {
2290                 tmp = tr32(GRC_EEPROM_ADDR);
2291
2292                 if (tmp & EEPROM_ADDR_COMPLETE)
2293                         break;
2294                 msleep(1);
2295         }
2296         if (!(tmp & EEPROM_ADDR_COMPLETE))
2297                 return -EBUSY;
2298
2299         tmp = tr32(GRC_EEPROM_DATA);
2300
2301         /*
2302          * The data will always be opposite the native endian
2303          * format.  Perform a blind byteswap to compensate.
2304          */
2305         *val = swab32(tmp);
2306
2307         return 0;
2308 }
2309
2310 #define NVRAM_CMD_TIMEOUT 10000
2311
2312 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2313 {
2314         int i;
2315
2316         tw32(NVRAM_CMD, nvram_cmd);
2317         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2318                 udelay(10);
2319                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2320                         udelay(10);
2321                         break;
2322                 }
2323         }
2324
2325         if (i == NVRAM_CMD_TIMEOUT)
2326                 return -EBUSY;
2327
2328         return 0;
2329 }
2330
2331 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2332 {
2333         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2334             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2335             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2336            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2337             (tp->nvram_jedecnum == JEDEC_ATMEL))
2338
2339                 addr = ((addr / tp->nvram_pagesize) <<
2340                         ATMEL_AT45DB0X1B_PAGE_POS) +
2341                        (addr % tp->nvram_pagesize);
2342
2343         return addr;
2344 }
2345
2346 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2347 {
2348         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352             (tp->nvram_jedecnum == JEDEC_ATMEL))
2353
2354                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2355                         tp->nvram_pagesize) +
2356                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2357
2358         return addr;
2359 }
2360
2361 /* NOTE: Data read in from NVRAM is byteswapped according to
2362  * the byteswapping settings for all other register accesses.
2363  * tg3 devices are BE devices, so on a BE machine, the data
2364  * returned will be exactly as it is seen in NVRAM.  On a LE
2365  * machine, the 32-bit value will be byteswapped.
2366  */
2367 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2368 {
2369         int ret;
2370
2371         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2372                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2373
2374         offset = tg3_nvram_phys_addr(tp, offset);
2375
2376         if (offset > NVRAM_ADDR_MSK)
2377                 return -EINVAL;
2378
2379         ret = tg3_nvram_lock(tp);
2380         if (ret)
2381                 return ret;
2382
2383         tg3_enable_nvram_access(tp);
2384
2385         tw32(NVRAM_ADDR, offset);
2386         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2387                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2388
2389         if (ret == 0)
2390                 *val = tr32(NVRAM_RDDATA);
2391
2392         tg3_disable_nvram_access(tp);
2393
2394         tg3_nvram_unlock(tp);
2395
2396         return ret;
2397 }
2398
2399 /* Ensures NVRAM data is in bytestream format. */
2400 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2401 {
2402         u32 v;
2403         int res = tg3_nvram_read(tp, offset, &v);
2404         if (!res)
2405                 *val = cpu_to_be32(v);
2406         return res;
2407 }
2408
2409 /* tp->lock is held. */
2410 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2411 {
2412         u32 addr_high, addr_low;
2413         int i;
2414
2415         addr_high = ((tp->dev->dev_addr[0] << 8) |
2416                      tp->dev->dev_addr[1]);
2417         addr_low = ((tp->dev->dev_addr[2] << 24) |
2418                     (tp->dev->dev_addr[3] << 16) |
2419                     (tp->dev->dev_addr[4] <<  8) |
2420                     (tp->dev->dev_addr[5] <<  0));
2421         for (i = 0; i < 4; i++) {
2422                 if (i == 1 && skip_mac_1)
2423                         continue;
2424                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2425                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2426         }
2427
2428         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2429             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2430                 for (i = 0; i < 12; i++) {
2431                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2432                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2433                 }
2434         }
2435
2436         addr_high = (tp->dev->dev_addr[0] +
2437                      tp->dev->dev_addr[1] +
2438                      tp->dev->dev_addr[2] +
2439                      tp->dev->dev_addr[3] +
2440                      tp->dev->dev_addr[4] +
2441                      tp->dev->dev_addr[5]) &
2442                 TX_BACKOFF_SEED_MASK;
2443         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2444 }
2445
2446 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2447 {
2448         u32 misc_host_ctrl;
2449         bool device_should_wake, do_low_power;
2450
2451         /* Make sure register accesses (indirect or otherwise)
2452          * will function correctly.
2453          */
2454         pci_write_config_dword(tp->pdev,
2455                                TG3PCI_MISC_HOST_CTRL,
2456                                tp->misc_host_ctrl);
2457
2458         switch (state) {
2459         case PCI_D0:
2460                 pci_enable_wake(tp->pdev, state, false);
2461                 pci_set_power_state(tp->pdev, PCI_D0);
2462
2463                 /* Switch out of Vaux if it is a NIC */
2464                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2465                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2466
2467                 return 0;
2468
2469         case PCI_D1:
2470         case PCI_D2:
2471         case PCI_D3hot:
2472                 break;
2473
2474         default:
2475                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2476                         tp->dev->name, state);
2477                 return -EINVAL;
2478         }
2479
2480         /* Restore the CLKREQ setting. */
2481         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2482                 u16 lnkctl;
2483
2484                 pci_read_config_word(tp->pdev,
2485                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2486                                      &lnkctl);
2487                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2488                 pci_write_config_word(tp->pdev,
2489                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2490                                       lnkctl);
2491         }
2492
2493         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2494         tw32(TG3PCI_MISC_HOST_CTRL,
2495              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2496
2497         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2498                              device_may_wakeup(&tp->pdev->dev) &&
2499                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2500
2501         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2502                 do_low_power = false;
2503                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2504                     !tp->link_config.phy_is_low_power) {
2505                         struct phy_device *phydev;
2506                         u32 phyid, advertising;
2507
2508                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2509
2510                         tp->link_config.phy_is_low_power = 1;
2511
2512                         tp->link_config.orig_speed = phydev->speed;
2513                         tp->link_config.orig_duplex = phydev->duplex;
2514                         tp->link_config.orig_autoneg = phydev->autoneg;
2515                         tp->link_config.orig_advertising = phydev->advertising;
2516
2517                         advertising = ADVERTISED_TP |
2518                                       ADVERTISED_Pause |
2519                                       ADVERTISED_Autoneg |
2520                                       ADVERTISED_10baseT_Half;
2521
2522                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2523                             device_should_wake) {
2524                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2525                                         advertising |=
2526                                                 ADVERTISED_100baseT_Half |
2527                                                 ADVERTISED_100baseT_Full |
2528                                                 ADVERTISED_10baseT_Full;
2529                                 else
2530                                         advertising |= ADVERTISED_10baseT_Full;
2531                         }
2532
2533                         phydev->advertising = advertising;
2534
2535                         phy_start_aneg(phydev);
2536
2537                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2538                         if (phyid != TG3_PHY_ID_BCMAC131) {
2539                                 phyid &= TG3_PHY_OUI_MASK;
2540                                 if (phyid == TG3_PHY_OUI_1 ||
2541                                     phyid == TG3_PHY_OUI_2 ||
2542                                     phyid == TG3_PHY_OUI_3)
2543                                         do_low_power = true;
2544                         }
2545                 }
2546         } else {
2547                 do_low_power = true;
2548
2549                 if (tp->link_config.phy_is_low_power == 0) {
2550                         tp->link_config.phy_is_low_power = 1;
2551                         tp->link_config.orig_speed = tp->link_config.speed;
2552                         tp->link_config.orig_duplex = tp->link_config.duplex;
2553                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2554                 }
2555
2556                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2557                         tp->link_config.speed = SPEED_10;
2558                         tp->link_config.duplex = DUPLEX_HALF;
2559                         tp->link_config.autoneg = AUTONEG_ENABLE;
2560                         tg3_setup_phy(tp, 0);
2561                 }
2562         }
2563
2564         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2565                 u32 val;
2566
2567                 val = tr32(GRC_VCPU_EXT_CTRL);
2568                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2569         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2570                 int i;
2571                 u32 val;
2572
2573                 for (i = 0; i < 200; i++) {
2574                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2575                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2576                                 break;
2577                         msleep(1);
2578                 }
2579         }
2580         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2581                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2582                                                      WOL_DRV_STATE_SHUTDOWN |
2583                                                      WOL_DRV_WOL |
2584                                                      WOL_SET_MAGIC_PKT);
2585
2586         if (device_should_wake) {
2587                 u32 mac_mode;
2588
2589                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2590                         if (do_low_power) {
2591                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2592                                 udelay(40);
2593                         }
2594
2595                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2596                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2597                         else
2598                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2599
2600                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2601                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2602                             ASIC_REV_5700) {
2603                                 u32 speed = (tp->tg3_flags &
2604                                              TG3_FLAG_WOL_SPEED_100MB) ?
2605                                              SPEED_100 : SPEED_10;
2606                                 if (tg3_5700_link_polarity(tp, speed))
2607                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2608                                 else
2609                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2610                         }
2611                 } else {
2612                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2613                 }
2614
2615                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2616                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2617
2618                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2619                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2620                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2621                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2622                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2623                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2624
2625                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2626                         mac_mode |= tp->mac_mode &
2627                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2628                         if (mac_mode & MAC_MODE_APE_TX_EN)
2629                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2630                 }
2631
2632                 tw32_f(MAC_MODE, mac_mode);
2633                 udelay(100);
2634
2635                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2636                 udelay(10);
2637         }
2638
2639         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2640             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2641              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2642                 u32 base_val;
2643
2644                 base_val = tp->pci_clock_ctrl;
2645                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2646                              CLOCK_CTRL_TXCLK_DISABLE);
2647
2648                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2649                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2650         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2651                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2652                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2653                 /* do nothing */
2654         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2655                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2656                 u32 newbits1, newbits2;
2657
2658                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2659                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2660                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2661                                     CLOCK_CTRL_TXCLK_DISABLE |
2662                                     CLOCK_CTRL_ALTCLK);
2663                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2664                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2665                         newbits1 = CLOCK_CTRL_625_CORE;
2666                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2667                 } else {
2668                         newbits1 = CLOCK_CTRL_ALTCLK;
2669                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2670                 }
2671
2672                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2673                             40);
2674
2675                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2676                             40);
2677
2678                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2679                         u32 newbits3;
2680
2681                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2682                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2683                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2684                                             CLOCK_CTRL_TXCLK_DISABLE |
2685                                             CLOCK_CTRL_44MHZ_CORE);
2686                         } else {
2687                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2688                         }
2689
2690                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2691                                     tp->pci_clock_ctrl | newbits3, 40);
2692                 }
2693         }
2694
2695         if (!(device_should_wake) &&
2696             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2697                 tg3_power_down_phy(tp, do_low_power);
2698
2699         tg3_frob_aux_power(tp);
2700
2701         /* Workaround for unstable PLL clock */
2702         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2703             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2704                 u32 val = tr32(0x7d00);
2705
2706                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2707                 tw32(0x7d00, val);
2708                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2709                         int err;
2710
2711                         err = tg3_nvram_lock(tp);
2712                         tg3_halt_cpu(tp, RX_CPU_BASE);
2713                         if (!err)
2714                                 tg3_nvram_unlock(tp);
2715                 }
2716         }
2717
2718         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2719
2720         if (device_should_wake)
2721                 pci_enable_wake(tp->pdev, state, true);
2722
2723         /* Finally, set the new power state. */
2724         pci_set_power_state(tp->pdev, state);
2725
2726         return 0;
2727 }
2728
2729 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2730 {
2731         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2732         case MII_TG3_AUX_STAT_10HALF:
2733                 *speed = SPEED_10;
2734                 *duplex = DUPLEX_HALF;
2735                 break;
2736
2737         case MII_TG3_AUX_STAT_10FULL:
2738                 *speed = SPEED_10;
2739                 *duplex = DUPLEX_FULL;
2740                 break;
2741
2742         case MII_TG3_AUX_STAT_100HALF:
2743                 *speed = SPEED_100;
2744                 *duplex = DUPLEX_HALF;
2745                 break;
2746
2747         case MII_TG3_AUX_STAT_100FULL:
2748                 *speed = SPEED_100;
2749                 *duplex = DUPLEX_FULL;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_1000HALF:
2753                 *speed = SPEED_1000;
2754                 *duplex = DUPLEX_HALF;
2755                 break;
2756
2757         case MII_TG3_AUX_STAT_1000FULL:
2758                 *speed = SPEED_1000;
2759                 *duplex = DUPLEX_FULL;
2760                 break;
2761
2762         default:
2763                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2764                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2765                                  SPEED_10;
2766                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2767                                   DUPLEX_HALF;
2768                         break;
2769                 }
2770                 *speed = SPEED_INVALID;
2771                 *duplex = DUPLEX_INVALID;
2772                 break;
2773         }
2774 }
2775
2776 static void tg3_phy_copper_begin(struct tg3 *tp)
2777 {
2778         u32 new_adv;
2779         int i;
2780
2781         if (tp->link_config.phy_is_low_power) {
2782                 /* Entering low power mode.  Disable gigabit and
2783                  * 100baseT advertisements.
2784                  */
2785                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2786
2787                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2788                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2789                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2790                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2791
2792                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2793         } else if (tp->link_config.speed == SPEED_INVALID) {
2794                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2795                         tp->link_config.advertising &=
2796                                 ~(ADVERTISED_1000baseT_Half |
2797                                   ADVERTISED_1000baseT_Full);
2798
2799                 new_adv = ADVERTISE_CSMA;
2800                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2801                         new_adv |= ADVERTISE_10HALF;
2802                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2803                         new_adv |= ADVERTISE_10FULL;
2804                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2805                         new_adv |= ADVERTISE_100HALF;
2806                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2807                         new_adv |= ADVERTISE_100FULL;
2808
2809                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2810
2811                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2812
2813                 if (tp->link_config.advertising &
2814                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2815                         new_adv = 0;
2816                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2817                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2818                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2819                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2820                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2821                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2822                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2823                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2824                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2825                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2826                 } else {
2827                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2828                 }
2829         } else {
2830                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2831                 new_adv |= ADVERTISE_CSMA;
2832
2833                 /* Asking for a specific link mode. */
2834                 if (tp->link_config.speed == SPEED_1000) {
2835                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2836
2837                         if (tp->link_config.duplex == DUPLEX_FULL)
2838                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2839                         else
2840                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2841                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2842                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2843                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2844                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2845                 } else {
2846                         if (tp->link_config.speed == SPEED_100) {
2847                                 if (tp->link_config.duplex == DUPLEX_FULL)
2848                                         new_adv |= ADVERTISE_100FULL;
2849                                 else
2850                                         new_adv |= ADVERTISE_100HALF;
2851                         } else {
2852                                 if (tp->link_config.duplex == DUPLEX_FULL)
2853                                         new_adv |= ADVERTISE_10FULL;
2854                                 else
2855                                         new_adv |= ADVERTISE_10HALF;
2856                         }
2857                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2858
2859                         new_adv = 0;
2860                 }
2861
2862                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2863         }
2864
2865         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2866             tp->link_config.speed != SPEED_INVALID) {
2867                 u32 bmcr, orig_bmcr;
2868
2869                 tp->link_config.active_speed = tp->link_config.speed;
2870                 tp->link_config.active_duplex = tp->link_config.duplex;
2871
2872                 bmcr = 0;
2873                 switch (tp->link_config.speed) {
2874                 default:
2875                 case SPEED_10:
2876                         break;
2877
2878                 case SPEED_100:
2879                         bmcr |= BMCR_SPEED100;
2880                         break;
2881
2882                 case SPEED_1000:
2883                         bmcr |= TG3_BMCR_SPEED1000;
2884                         break;
2885                 }
2886
2887                 if (tp->link_config.duplex == DUPLEX_FULL)
2888                         bmcr |= BMCR_FULLDPLX;
2889
2890                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2891                     (bmcr != orig_bmcr)) {
2892                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2893                         for (i = 0; i < 1500; i++) {
2894                                 u32 tmp;
2895
2896                                 udelay(10);
2897                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2898                                     tg3_readphy(tp, MII_BMSR, &tmp))
2899                                         continue;
2900                                 if (!(tmp & BMSR_LSTATUS)) {
2901                                         udelay(40);
2902                                         break;
2903                                 }
2904                         }
2905                         tg3_writephy(tp, MII_BMCR, bmcr);
2906                         udelay(40);
2907                 }
2908         } else {
2909                 tg3_writephy(tp, MII_BMCR,
2910                              BMCR_ANENABLE | BMCR_ANRESTART);
2911         }
2912 }
2913
2914 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2915 {
2916         int err;
2917
2918         /* Turn off tap power management. */
2919         /* Set Extended packet length bit */
2920         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2921
2922         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2923         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2924
2925         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2926         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2927
2928         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2929         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2930
2931         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2932         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2933
2934         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2935         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2936
2937         udelay(40);
2938
2939         return err;
2940 }
2941
2942 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2943 {
2944         u32 adv_reg, all_mask = 0;
2945
2946         if (mask & ADVERTISED_10baseT_Half)
2947                 all_mask |= ADVERTISE_10HALF;
2948         if (mask & ADVERTISED_10baseT_Full)
2949                 all_mask |= ADVERTISE_10FULL;
2950         if (mask & ADVERTISED_100baseT_Half)
2951                 all_mask |= ADVERTISE_100HALF;
2952         if (mask & ADVERTISED_100baseT_Full)
2953                 all_mask |= ADVERTISE_100FULL;
2954
2955         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2956                 return 0;
2957
2958         if ((adv_reg & all_mask) != all_mask)
2959                 return 0;
2960         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2961                 u32 tg3_ctrl;
2962
2963                 all_mask = 0;
2964                 if (mask & ADVERTISED_1000baseT_Half)
2965                         all_mask |= ADVERTISE_1000HALF;
2966                 if (mask & ADVERTISED_1000baseT_Full)
2967                         all_mask |= ADVERTISE_1000FULL;
2968
2969                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2970                         return 0;
2971
2972                 if ((tg3_ctrl & all_mask) != all_mask)
2973                         return 0;
2974         }
2975         return 1;
2976 }
2977
2978 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2979 {
2980         u32 curadv, reqadv;
2981
2982         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2983                 return 1;
2984
2985         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2986         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2987
2988         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2989                 if (curadv != reqadv)
2990                         return 0;
2991
2992                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2993                         tg3_readphy(tp, MII_LPA, rmtadv);
2994         } else {
2995                 /* Reprogram the advertisement register, even if it
2996                  * does not affect the current link.  If the link
2997                  * gets renegotiated in the future, we can save an
2998                  * additional renegotiation cycle by advertising
2999                  * it correctly in the first place.
3000                  */
3001                 if (curadv != reqadv) {
3002                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3003                                      ADVERTISE_PAUSE_ASYM);
3004                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3005                 }
3006         }
3007
3008         return 1;
3009 }
3010
3011 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3012 {
3013         int current_link_up;
3014         u32 bmsr, dummy;
3015         u32 lcl_adv, rmt_adv;
3016         u16 current_speed;
3017         u8 current_duplex;
3018         int i, err;
3019
3020         tw32(MAC_EVENT, 0);
3021
3022         tw32_f(MAC_STATUS,
3023              (MAC_STATUS_SYNC_CHANGED |
3024               MAC_STATUS_CFG_CHANGED |
3025               MAC_STATUS_MI_COMPLETION |
3026               MAC_STATUS_LNKSTATE_CHANGED));
3027         udelay(40);
3028
3029         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3030                 tw32_f(MAC_MI_MODE,
3031                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3032                 udelay(80);
3033         }
3034
3035         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3036
3037         /* Some third-party PHYs need to be reset on link going
3038          * down.
3039          */
3040         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3041              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3042              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3043             netif_carrier_ok(tp->dev)) {
3044                 tg3_readphy(tp, MII_BMSR, &bmsr);
3045                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3046                     !(bmsr & BMSR_LSTATUS))
3047                         force_reset = 1;
3048         }
3049         if (force_reset)
3050                 tg3_phy_reset(tp);
3051
3052         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3053                 tg3_readphy(tp, MII_BMSR, &bmsr);
3054                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3055                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3056                         bmsr = 0;
3057
3058                 if (!(bmsr & BMSR_LSTATUS)) {
3059                         err = tg3_init_5401phy_dsp(tp);
3060                         if (err)
3061                                 return err;
3062
3063                         tg3_readphy(tp, MII_BMSR, &bmsr);
3064                         for (i = 0; i < 1000; i++) {
3065                                 udelay(10);
3066                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067                                     (bmsr & BMSR_LSTATUS)) {
3068                                         udelay(40);
3069                                         break;
3070                                 }
3071                         }
3072
3073                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3074                             !(bmsr & BMSR_LSTATUS) &&
3075                             tp->link_config.active_speed == SPEED_1000) {
3076                                 err = tg3_phy_reset(tp);
3077                                 if (!err)
3078                                         err = tg3_init_5401phy_dsp(tp);
3079                                 if (err)
3080                                         return err;
3081                         }
3082                 }
3083         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3084                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3085                 /* 5701 {A0,B0} CRC bug workaround */
3086                 tg3_writephy(tp, 0x15, 0x0a75);
3087                 tg3_writephy(tp, 0x1c, 0x8c68);
3088                 tg3_writephy(tp, 0x1c, 0x8d68);
3089                 tg3_writephy(tp, 0x1c, 0x8c68);
3090         }
3091
3092         /* Clear pending interrupts... */
3093         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3094         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3095
3096         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3097                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3098         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3099                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3100
3101         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3102             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3103                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3104                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3105                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3106                 else
3107                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3108         }
3109
3110         current_link_up = 0;
3111         current_speed = SPEED_INVALID;
3112         current_duplex = DUPLEX_INVALID;
3113
3114         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3115                 u32 val;
3116
3117                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119                 if (!(val & (1 << 10))) {
3120                         val |= (1 << 10);
3121                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3122                         goto relink;
3123                 }
3124         }
3125
3126         bmsr = 0;
3127         for (i = 0; i < 100; i++) {
3128                 tg3_readphy(tp, MII_BMSR, &bmsr);
3129                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130                     (bmsr & BMSR_LSTATUS))
3131                         break;
3132                 udelay(40);
3133         }
3134
3135         if (bmsr & BMSR_LSTATUS) {
3136                 u32 aux_stat, bmcr;
3137
3138                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139                 for (i = 0; i < 2000; i++) {
3140                         udelay(10);
3141                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3142                             aux_stat)
3143                                 break;
3144                 }
3145
3146                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3147                                              &current_speed,
3148                                              &current_duplex);
3149
3150                 bmcr = 0;
3151                 for (i = 0; i < 200; i++) {
3152                         tg3_readphy(tp, MII_BMCR, &bmcr);
3153                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3154                                 continue;
3155                         if (bmcr && bmcr != 0x7fff)
3156                                 break;
3157                         udelay(10);
3158                 }
3159
3160                 lcl_adv = 0;
3161                 rmt_adv = 0;
3162
3163                 tp->link_config.active_speed = current_speed;
3164                 tp->link_config.active_duplex = current_duplex;
3165
3166                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167                         if ((bmcr & BMCR_ANENABLE) &&
3168                             tg3_copper_is_advertising_all(tp,
3169                                                 tp->link_config.advertising)) {
3170                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3171                                                                   &rmt_adv))
3172                                         current_link_up = 1;
3173                         }
3174                 } else {
3175                         if (!(bmcr & BMCR_ANENABLE) &&
3176                             tp->link_config.speed == current_speed &&
3177                             tp->link_config.duplex == current_duplex &&
3178                             tp->link_config.flowctrl ==
3179                             tp->link_config.active_flowctrl) {
3180                                 current_link_up = 1;
3181                         }
3182                 }
3183
3184                 if (current_link_up == 1 &&
3185                     tp->link_config.active_duplex == DUPLEX_FULL)
3186                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3187         }
3188
3189 relink:
3190         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3191                 u32 tmp;
3192
3193                 tg3_phy_copper_begin(tp);
3194
3195                 tg3_readphy(tp, MII_BMSR, &tmp);
3196                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3197                     (tmp & BMSR_LSTATUS))
3198                         current_link_up = 1;
3199         }
3200
3201         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3202         if (current_link_up == 1) {
3203                 if (tp->link_config.active_speed == SPEED_100 ||
3204                     tp->link_config.active_speed == SPEED_10)
3205                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3206                 else
3207                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3208         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3209                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3210         else
3211                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3212
3213         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3214         if (tp->link_config.active_duplex == DUPLEX_HALF)
3215                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3216
3217         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3218                 if (current_link_up == 1 &&
3219                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3220                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3221                 else
3222                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3223         }
3224
3225         /* ??? Without this setting Netgear GA302T PHY does not
3226          * ??? send/receive packets...
3227          */
3228         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3229             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3230                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3231                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3232                 udelay(80);
3233         }
3234
3235         tw32_f(MAC_MODE, tp->mac_mode);
3236         udelay(40);
3237
3238         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3239                 /* Polled via timer. */
3240                 tw32_f(MAC_EVENT, 0);
3241         } else {
3242                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3243         }
3244         udelay(40);
3245
3246         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3247             current_link_up == 1 &&
3248             tp->link_config.active_speed == SPEED_1000 &&
3249             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3250              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3251                 udelay(120);
3252                 tw32_f(MAC_STATUS,
3253                      (MAC_STATUS_SYNC_CHANGED |
3254                       MAC_STATUS_CFG_CHANGED));
3255                 udelay(40);
3256                 tg3_write_mem(tp,
3257                               NIC_SRAM_FIRMWARE_MBOX,
3258                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3259         }
3260
3261         /* Prevent send BD corruption. */
3262         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3263                 u16 oldlnkctl, newlnkctl;
3264
3265                 pci_read_config_word(tp->pdev,
3266                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3267                                      &oldlnkctl);
3268                 if (tp->link_config.active_speed == SPEED_100 ||
3269                     tp->link_config.active_speed == SPEED_10)
3270                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3271                 else
3272                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3273                 if (newlnkctl != oldlnkctl)
3274                         pci_write_config_word(tp->pdev,
3275                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3276                                               newlnkctl);
3277         }
3278
3279         if (current_link_up != netif_carrier_ok(tp->dev)) {
3280                 if (current_link_up)
3281                         netif_carrier_on(tp->dev);
3282                 else
3283                         netif_carrier_off(tp->dev);
3284                 tg3_link_report(tp);
3285         }
3286
3287         return 0;
3288 }
3289
3290 struct tg3_fiber_aneginfo {
3291         int state;
3292 #define ANEG_STATE_UNKNOWN              0
3293 #define ANEG_STATE_AN_ENABLE            1
3294 #define ANEG_STATE_RESTART_INIT         2
3295 #define ANEG_STATE_RESTART              3
3296 #define ANEG_STATE_DISABLE_LINK_OK      4
3297 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3298 #define ANEG_STATE_ABILITY_DETECT       6
3299 #define ANEG_STATE_ACK_DETECT_INIT      7
3300 #define ANEG_STATE_ACK_DETECT           8
3301 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3302 #define ANEG_STATE_COMPLETE_ACK         10
3303 #define ANEG_STATE_IDLE_DETECT_INIT     11
3304 #define ANEG_STATE_IDLE_DETECT          12
3305 #define ANEG_STATE_LINK_OK              13
3306 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3307 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3308
3309         u32 flags;
3310 #define MR_AN_ENABLE            0x00000001
3311 #define MR_RESTART_AN           0x00000002
3312 #define MR_AN_COMPLETE          0x00000004
3313 #define MR_PAGE_RX              0x00000008
3314 #define MR_NP_LOADED            0x00000010
3315 #define MR_TOGGLE_TX            0x00000020
3316 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3317 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3318 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3319 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3320 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3321 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3322 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3323 #define MR_TOGGLE_RX            0x00002000
3324 #define MR_NP_RX                0x00004000
3325
3326 #define MR_LINK_OK              0x80000000
3327
3328         unsigned long link_time, cur_time;
3329
3330         u32 ability_match_cfg;
3331         int ability_match_count;
3332
3333         char ability_match, idle_match, ack_match;
3334
3335         u32 txconfig, rxconfig;
3336 #define ANEG_CFG_NP             0x00000080
3337 #define ANEG_CFG_ACK            0x00000040
3338 #define ANEG_CFG_RF2            0x00000020
3339 #define ANEG_CFG_RF1            0x00000010
3340 #define ANEG_CFG_PS2            0x00000001
3341 #define ANEG_CFG_PS1            0x00008000
3342 #define ANEG_CFG_HD             0x00004000
3343 #define ANEG_CFG_FD             0x00002000
3344 #define ANEG_CFG_INVAL          0x00001f06
3345
3346 };
3347 #define ANEG_OK         0
3348 #define ANEG_DONE       1
3349 #define ANEG_TIMER_ENAB 2
3350 #define ANEG_FAILED     -1
3351
3352 #define ANEG_STATE_SETTLE_TIME  10000
3353
3354 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3355                                    struct tg3_fiber_aneginfo *ap)
3356 {
3357         u16 flowctrl;
3358         unsigned long delta;
3359         u32 rx_cfg_reg;
3360         int ret;
3361
3362         if (ap->state == ANEG_STATE_UNKNOWN) {
3363                 ap->rxconfig = 0;
3364                 ap->link_time = 0;
3365                 ap->cur_time = 0;
3366                 ap->ability_match_cfg = 0;
3367                 ap->ability_match_count = 0;
3368                 ap->ability_match = 0;
3369                 ap->idle_match = 0;
3370                 ap->ack_match = 0;
3371         }
3372         ap->cur_time++;
3373
3374         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3375                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3376
3377                 if (rx_cfg_reg != ap->ability_match_cfg) {
3378                         ap->ability_match_cfg = rx_cfg_reg;
3379                         ap->ability_match = 0;
3380                         ap->ability_match_count = 0;
3381                 } else {
3382                         if (++ap->ability_match_count > 1) {
3383                                 ap->ability_match = 1;
3384                                 ap->ability_match_cfg = rx_cfg_reg;
3385                         }
3386                 }
3387                 if (rx_cfg_reg & ANEG_CFG_ACK)
3388                         ap->ack_match = 1;
3389                 else
3390                         ap->ack_match = 0;
3391
3392                 ap->idle_match = 0;
3393         } else {
3394                 ap->idle_match = 1;
3395                 ap->ability_match_cfg = 0;
3396                 ap->ability_match_count = 0;
3397                 ap->ability_match = 0;
3398                 ap->ack_match = 0;
3399
3400                 rx_cfg_reg = 0;
3401         }
3402
3403         ap->rxconfig = rx_cfg_reg;
3404         ret = ANEG_OK;
3405
3406         switch(ap->state) {
3407         case ANEG_STATE_UNKNOWN:
3408                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3409                         ap->state = ANEG_STATE_AN_ENABLE;
3410
3411                 /* fallthru */
3412         case ANEG_STATE_AN_ENABLE:
3413                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3414                 if (ap->flags & MR_AN_ENABLE) {
3415                         ap->link_time = 0;
3416                         ap->cur_time = 0;
3417                         ap->ability_match_cfg = 0;
3418                         ap->ability_match_count = 0;
3419                         ap->ability_match = 0;
3420                         ap->idle_match = 0;
3421                         ap->ack_match = 0;
3422
3423                         ap->state = ANEG_STATE_RESTART_INIT;
3424                 } else {
3425                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3426                 }
3427                 break;
3428
3429         case ANEG_STATE_RESTART_INIT:
3430                 ap->link_time = ap->cur_time;
3431                 ap->flags &= ~(MR_NP_LOADED);
3432                 ap->txconfig = 0;
3433                 tw32(MAC_TX_AUTO_NEG, 0);
3434                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3435                 tw32_f(MAC_MODE, tp->mac_mode);
3436                 udelay(40);
3437
3438                 ret = ANEG_TIMER_ENAB;
3439                 ap->state = ANEG_STATE_RESTART;
3440
3441                 /* fallthru */
3442         case ANEG_STATE_RESTART:
3443                 delta = ap->cur_time - ap->link_time;
3444                 if (delta > ANEG_STATE_SETTLE_TIME) {
3445                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3446                 } else {
3447                         ret = ANEG_TIMER_ENAB;
3448                 }
3449                 break;
3450
3451         case ANEG_STATE_DISABLE_LINK_OK:
3452                 ret = ANEG_DONE;
3453                 break;
3454
3455         case ANEG_STATE_ABILITY_DETECT_INIT:
3456                 ap->flags &= ~(MR_TOGGLE_TX);
3457                 ap->txconfig = ANEG_CFG_FD;
3458                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3459                 if (flowctrl & ADVERTISE_1000XPAUSE)
3460                         ap->txconfig |= ANEG_CFG_PS1;
3461                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3462                         ap->txconfig |= ANEG_CFG_PS2;
3463                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3464                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3465                 tw32_f(MAC_MODE, tp->mac_mode);
3466                 udelay(40);
3467
3468                 ap->state = ANEG_STATE_ABILITY_DETECT;
3469                 break;
3470
3471         case ANEG_STATE_ABILITY_DETECT:
3472                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3473                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3474                 }
3475                 break;
3476
3477         case ANEG_STATE_ACK_DETECT_INIT:
3478                 ap->txconfig |= ANEG_CFG_ACK;
3479                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3480                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3481                 tw32_f(MAC_MODE, tp->mac_mode);
3482                 udelay(40);
3483
3484                 ap->state = ANEG_STATE_ACK_DETECT;
3485
3486                 /* fallthru */
3487         case ANEG_STATE_ACK_DETECT:
3488                 if (ap->ack_match != 0) {
3489                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3490                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3491                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3492                         } else {
3493                                 ap->state = ANEG_STATE_AN_ENABLE;
3494                         }
3495                 } else if (ap->ability_match != 0 &&
3496                            ap->rxconfig == 0) {
3497                         ap->state = ANEG_STATE_AN_ENABLE;
3498                 }
3499                 break;
3500
3501         case ANEG_STATE_COMPLETE_ACK_INIT:
3502                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3503                         ret = ANEG_FAILED;
3504                         break;
3505                 }
3506                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3507                                MR_LP_ADV_HALF_DUPLEX |
3508                                MR_LP_ADV_SYM_PAUSE |
3509                                MR_LP_ADV_ASYM_PAUSE |
3510                                MR_LP_ADV_REMOTE_FAULT1 |
3511                                MR_LP_ADV_REMOTE_FAULT2 |
3512                                MR_LP_ADV_NEXT_PAGE |
3513                                MR_TOGGLE_RX |
3514                                MR_NP_RX);
3515                 if (ap->rxconfig & ANEG_CFG_FD)
3516                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3517                 if (ap->rxconfig & ANEG_CFG_HD)
3518                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3519                 if (ap->rxconfig & ANEG_CFG_PS1)
3520                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3521                 if (ap->rxconfig & ANEG_CFG_PS2)
3522                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3523                 if (ap->rxconfig & ANEG_CFG_RF1)
3524                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3525                 if (ap->rxconfig & ANEG_CFG_RF2)
3526                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3527                 if (ap->rxconfig & ANEG_CFG_NP)
3528                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3529
3530                 ap->link_time = ap->cur_time;
3531
3532                 ap->flags ^= (MR_TOGGLE_TX);
3533                 if (ap->rxconfig & 0x0008)
3534                         ap->flags |= MR_TOGGLE_RX;
3535                 if (ap->rxconfig & ANEG_CFG_NP)
3536                         ap->flags |= MR_NP_RX;
3537                 ap->flags |= MR_PAGE_RX;
3538
3539                 ap->state = ANEG_STATE_COMPLETE_ACK;
3540                 ret = ANEG_TIMER_ENAB;
3541                 break;
3542
3543         case ANEG_STATE_COMPLETE_ACK:
3544                 if (ap->ability_match != 0 &&
3545                     ap->rxconfig == 0) {
3546                         ap->state = ANEG_STATE_AN_ENABLE;
3547                         break;
3548                 }
3549                 delta = ap->cur_time - ap->link_time;
3550                 if (delta > ANEG_STATE_SETTLE_TIME) {
3551                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3552                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553                         } else {
3554                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3555                                     !(ap->flags & MR_NP_RX)) {
3556                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3557                                 } else {
3558                                         ret = ANEG_FAILED;
3559                                 }
3560                         }
3561                 }
3562                 break;
3563
3564         case ANEG_STATE_IDLE_DETECT_INIT:
3565                 ap->link_time = ap->cur_time;
3566                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3567                 tw32_f(MAC_MODE, tp->mac_mode);
3568                 udelay(40);
3569
3570                 ap->state = ANEG_STATE_IDLE_DETECT;
3571                 ret = ANEG_TIMER_ENAB;
3572                 break;
3573
3574         case ANEG_STATE_IDLE_DETECT:
3575                 if (ap->ability_match != 0 &&
3576                     ap->rxconfig == 0) {
3577                         ap->state = ANEG_STATE_AN_ENABLE;
3578                         break;
3579                 }
3580                 delta = ap->cur_time - ap->link_time;
3581                 if (delta > ANEG_STATE_SETTLE_TIME) {
3582                         /* XXX another gem from the Broadcom driver :( */
3583                         ap->state = ANEG_STATE_LINK_OK;
3584                 }
3585                 break;
3586
3587         case ANEG_STATE_LINK_OK:
3588                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3589                 ret = ANEG_DONE;
3590                 break;
3591
3592         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3593                 /* ??? unimplemented */
3594                 break;
3595
3596         case ANEG_STATE_NEXT_PAGE_WAIT:
3597                 /* ??? unimplemented */
3598                 break;
3599
3600         default:
3601                 ret = ANEG_FAILED;
3602                 break;
3603         }
3604
3605         return ret;
3606 }
3607
3608 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3609 {
3610         int res = 0;
3611         struct tg3_fiber_aneginfo aninfo;
3612         int status = ANEG_FAILED;
3613         unsigned int tick;
3614         u32 tmp;
3615
3616         tw32_f(MAC_TX_AUTO_NEG, 0);
3617
3618         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3619         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3620         udelay(40);
3621
3622         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3623         udelay(40);
3624
3625         memset(&aninfo, 0, sizeof(aninfo));
3626         aninfo.flags |= MR_AN_ENABLE;
3627         aninfo.state = ANEG_STATE_UNKNOWN;
3628         aninfo.cur_time = 0;
3629         tick = 0;
3630         while (++tick < 195000) {
3631                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3632                 if (status == ANEG_DONE || status == ANEG_FAILED)
3633                         break;
3634
3635                 udelay(1);
3636         }
3637
3638         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3639         tw32_f(MAC_MODE, tp->mac_mode);
3640         udelay(40);
3641
3642         *txflags = aninfo.txconfig;
3643         *rxflags = aninfo.flags;
3644
3645         if (status == ANEG_DONE &&
3646             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3647                              MR_LP_ADV_FULL_DUPLEX)))
3648                 res = 1;
3649
3650         return res;
3651 }
3652
3653 static void tg3_init_bcm8002(struct tg3 *tp)
3654 {
3655         u32 mac_status = tr32(MAC_STATUS);
3656         int i;
3657
3658         /* Reset when initting first time or we have a link. */
3659         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3660             !(mac_status & MAC_STATUS_PCS_SYNCED))
3661                 return;
3662
3663         /* Set PLL lock range. */
3664         tg3_writephy(tp, 0x16, 0x8007);
3665
3666         /* SW reset */
3667         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3668
3669         /* Wait for reset to complete. */
3670         /* XXX schedule_timeout() ... */
3671         for (i = 0; i < 500; i++)
3672                 udelay(10);
3673
3674         /* Config mode; select PMA/Ch 1 regs. */
3675         tg3_writephy(tp, 0x10, 0x8411);
3676
3677         /* Enable auto-lock and comdet, select txclk for tx. */
3678         tg3_writephy(tp, 0x11, 0x0a10);
3679
3680         tg3_writephy(tp, 0x18, 0x00a0);
3681         tg3_writephy(tp, 0x16, 0x41ff);
3682
3683         /* Assert and deassert POR. */
3684         tg3_writephy(tp, 0x13, 0x0400);
3685         udelay(40);
3686         tg3_writephy(tp, 0x13, 0x0000);
3687
3688         tg3_writephy(tp, 0x11, 0x0a50);
3689         udelay(40);
3690         tg3_writephy(tp, 0x11, 0x0a10);
3691
3692         /* Wait for signal to stabilize */
3693         /* XXX schedule_timeout() ... */
3694         for (i = 0; i < 15000; i++)
3695                 udelay(10);
3696
3697         /* Deselect the channel register so we can read the PHYID
3698          * later.
3699          */
3700         tg3_writephy(tp, 0x10, 0x8011);
3701 }
3702
3703 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3704 {
3705         u16 flowctrl;
3706         u32 sg_dig_ctrl, sg_dig_status;
3707         u32 serdes_cfg, expected_sg_dig_ctrl;
3708         int workaround, port_a;
3709         int current_link_up;
3710
3711         serdes_cfg = 0;
3712         expected_sg_dig_ctrl = 0;
3713         workaround = 0;
3714         port_a = 1;
3715         current_link_up = 0;
3716
3717         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3718             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3719                 workaround = 1;
3720                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3721                         port_a = 0;
3722
3723                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3724                 /* preserve bits 20-23 for voltage regulator */
3725                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3726         }
3727
3728         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3729
3730         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3731                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3732                         if (workaround) {
3733                                 u32 val = serdes_cfg;
3734
3735                                 if (port_a)
3736                                         val |= 0xc010000;
3737                                 else
3738                                         val |= 0x4010000;
3739                                 tw32_f(MAC_SERDES_CFG, val);
3740                         }
3741
3742                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3743                 }
3744                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3745                         tg3_setup_flow_control(tp, 0, 0);
3746                         current_link_up = 1;
3747                 }
3748                 goto out;
3749         }
3750
3751         /* Want auto-negotiation.  */
3752         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3753
3754         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3755         if (flowctrl & ADVERTISE_1000XPAUSE)
3756                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3757         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3758                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3759
3760         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3761                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3762                     tp->serdes_counter &&
3763                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3764                                     MAC_STATUS_RCVD_CFG)) ==
3765                      MAC_STATUS_PCS_SYNCED)) {
3766                         tp->serdes_counter--;
3767                         current_link_up = 1;
3768                         goto out;
3769                 }
3770 restart_autoneg:
3771                 if (workaround)
3772                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3773                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3774                 udelay(5);
3775                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3776
3777                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3778                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3779         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3780                                  MAC_STATUS_SIGNAL_DET)) {
3781                 sg_dig_status = tr32(SG_DIG_STATUS);
3782                 mac_status = tr32(MAC_STATUS);
3783
3784                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3785                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3786                         u32 local_adv = 0, remote_adv = 0;
3787
3788                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3789                                 local_adv |= ADVERTISE_1000XPAUSE;
3790                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3791                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3792
3793                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3794                                 remote_adv |= LPA_1000XPAUSE;
3795                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3796                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3797
3798                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3799                         current_link_up = 1;
3800                         tp->serdes_counter = 0;
3801                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3802                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3803                         if (tp->serdes_counter)
3804                                 tp->serdes_counter--;
3805                         else {
3806                                 if (workaround) {
3807                                         u32 val = serdes_cfg;
3808
3809                                         if (port_a)
3810                                                 val |= 0xc010000;
3811                                         else
3812                                                 val |= 0x4010000;
3813
3814                                         tw32_f(MAC_SERDES_CFG, val);
3815                                 }
3816
3817                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3818                                 udelay(40);
3819
3820                                 /* Link parallel detection - link is up */
3821                                 /* only if we have PCS_SYNC and not */
3822                                 /* receiving config code words */
3823                                 mac_status = tr32(MAC_STATUS);
3824                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3825                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3826                                         tg3_setup_flow_control(tp, 0, 0);
3827                                         current_link_up = 1;
3828                                         tp->tg3_flags2 |=
3829                                                 TG3_FLG2_PARALLEL_DETECT;
3830                                         tp->serdes_counter =
3831                                                 SERDES_PARALLEL_DET_TIMEOUT;
3832                                 } else
3833                                         goto restart_autoneg;
3834                         }
3835                 }
3836         } else {
3837                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3838                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3839         }
3840
3841 out:
3842         return current_link_up;
3843 }
3844
3845 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3846 {
3847         int current_link_up = 0;
3848
3849         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3850                 goto out;
3851
3852         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3853                 u32 txflags, rxflags;
3854                 int i;
3855
3856                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3857                         u32 local_adv = 0, remote_adv = 0;
3858
3859                         if (txflags & ANEG_CFG_PS1)
3860                                 local_adv |= ADVERTISE_1000XPAUSE;
3861                         if (txflags & ANEG_CFG_PS2)
3862                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3863
3864                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3865                                 remote_adv |= LPA_1000XPAUSE;
3866                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3867                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3868
3869                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3870
3871                         current_link_up = 1;
3872                 }
3873                 for (i = 0; i < 30; i++) {
3874                         udelay(20);
3875                         tw32_f(MAC_STATUS,
3876                                (MAC_STATUS_SYNC_CHANGED |
3877                                 MAC_STATUS_CFG_CHANGED));
3878                         udelay(40);
3879                         if ((tr32(MAC_STATUS) &
3880                              (MAC_STATUS_SYNC_CHANGED |
3881                               MAC_STATUS_CFG_CHANGED)) == 0)
3882                                 break;
3883                 }
3884
3885                 mac_status = tr32(MAC_STATUS);
3886                 if (current_link_up == 0 &&
3887                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3888                     !(mac_status & MAC_STATUS_RCVD_CFG))
3889                         current_link_up = 1;
3890         } else {
3891                 tg3_setup_flow_control(tp, 0, 0);
3892
3893                 /* Forcing 1000FD link up. */
3894                 current_link_up = 1;
3895
3896                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3897                 udelay(40);
3898
3899                 tw32_f(MAC_MODE, tp->mac_mode);
3900                 udelay(40);
3901         }
3902
3903 out:
3904         return current_link_up;
3905 }
3906
3907 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3908 {
3909         u32 orig_pause_cfg;
3910         u16 orig_active_speed;
3911         u8 orig_active_duplex;
3912         u32 mac_status;
3913         int current_link_up;
3914         int i;
3915
3916         orig_pause_cfg = tp->link_config.active_flowctrl;
3917         orig_active_speed = tp->link_config.active_speed;
3918         orig_active_duplex = tp->link_config.active_duplex;
3919
3920         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3921             netif_carrier_ok(tp->dev) &&
3922             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3923                 mac_status = tr32(MAC_STATUS);
3924                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3925                                MAC_STATUS_SIGNAL_DET |
3926                                MAC_STATUS_CFG_CHANGED |
3927                                MAC_STATUS_RCVD_CFG);
3928                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3929                                    MAC_STATUS_SIGNAL_DET)) {
3930                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3931                                             MAC_STATUS_CFG_CHANGED));
3932                         return 0;
3933                 }
3934         }
3935
3936         tw32_f(MAC_TX_AUTO_NEG, 0);
3937
3938         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3939         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3940         tw32_f(MAC_MODE, tp->mac_mode);
3941         udelay(40);
3942
3943         if (tp->phy_id == PHY_ID_BCM8002)
3944                 tg3_init_bcm8002(tp);
3945
3946         /* Enable link change event even when serdes polling.  */
3947         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3948         udelay(40);
3949
3950         current_link_up = 0;
3951         mac_status = tr32(MAC_STATUS);
3952
3953         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3954                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3955         else
3956                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3957
3958         tp->napi[0].hw_status->status =
3959                 (SD_STATUS_UPDATED |
3960                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3961
3962         for (i = 0; i < 100; i++) {
3963                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3964                                     MAC_STATUS_CFG_CHANGED));
3965                 udelay(5);
3966                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3967                                          MAC_STATUS_CFG_CHANGED |
3968                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3969                         break;
3970         }
3971
3972         mac_status = tr32(MAC_STATUS);
3973         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3974                 current_link_up = 0;
3975                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3976                     tp->serdes_counter == 0) {
3977                         tw32_f(MAC_MODE, (tp->mac_mode |
3978                                           MAC_MODE_SEND_CONFIGS));
3979                         udelay(1);
3980                         tw32_f(MAC_MODE, tp->mac_mode);
3981                 }
3982         }
3983
3984         if (current_link_up == 1) {
3985                 tp->link_config.active_speed = SPEED_1000;
3986                 tp->link_config.active_duplex = DUPLEX_FULL;
3987                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3988                                     LED_CTRL_LNKLED_OVERRIDE |
3989                                     LED_CTRL_1000MBPS_ON));
3990         } else {
3991                 tp->link_config.active_speed = SPEED_INVALID;
3992                 tp->link_config.active_duplex = DUPLEX_INVALID;
3993                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3994                                     LED_CTRL_LNKLED_OVERRIDE |
3995                                     LED_CTRL_TRAFFIC_OVERRIDE));
3996         }
3997
3998         if (current_link_up != netif_carrier_ok(tp->dev)) {
3999                 if (current_link_up)
4000                         netif_carrier_on(tp->dev);
4001                 else
4002                         netif_carrier_off(tp->dev);
4003                 tg3_link_report(tp);
4004         } else {
4005                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4006                 if (orig_pause_cfg != now_pause_cfg ||
4007                     orig_active_speed != tp->link_config.active_speed ||
4008                     orig_active_duplex != tp->link_config.active_duplex)
4009                         tg3_link_report(tp);
4010         }
4011
4012         return 0;
4013 }
4014
4015 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4016 {
4017         int current_link_up, err = 0;
4018         u32 bmsr, bmcr;
4019         u16 current_speed;
4020         u8 current_duplex;
4021         u32 local_adv, remote_adv;
4022
4023         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4024         tw32_f(MAC_MODE, tp->mac_mode);
4025         udelay(40);
4026
4027         tw32(MAC_EVENT, 0);
4028
4029         tw32_f(MAC_STATUS,
4030              (MAC_STATUS_SYNC_CHANGED |
4031               MAC_STATUS_CFG_CHANGED |
4032               MAC_STATUS_MI_COMPLETION |
4033               MAC_STATUS_LNKSTATE_CHANGED));
4034         udelay(40);
4035
4036         if (force_reset)
4037                 tg3_phy_reset(tp);
4038
4039         current_link_up = 0;
4040         current_speed = SPEED_INVALID;
4041         current_duplex = DUPLEX_INVALID;
4042
4043         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4044         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4045         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4046                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4047                         bmsr |= BMSR_LSTATUS;
4048                 else
4049                         bmsr &= ~BMSR_LSTATUS;
4050         }
4051
4052         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4053
4054         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4055             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4056                 /* do nothing, just check for link up at the end */
4057         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4058                 u32 adv, new_adv;
4059
4060                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4061                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4062                                   ADVERTISE_1000XPAUSE |
4063                                   ADVERTISE_1000XPSE_ASYM |
4064                                   ADVERTISE_SLCT);
4065
4066                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4067
4068                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4069                         new_adv |= ADVERTISE_1000XHALF;
4070                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4071                         new_adv |= ADVERTISE_1000XFULL;
4072
4073                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4074                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4075                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4076                         tg3_writephy(tp, MII_BMCR, bmcr);
4077
4078                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4079                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4080                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4081
4082                         return err;
4083                 }
4084         } else {
4085                 u32 new_bmcr;
4086
4087                 bmcr &= ~BMCR_SPEED1000;
4088                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4089
4090                 if (tp->link_config.duplex == DUPLEX_FULL)
4091                         new_bmcr |= BMCR_FULLDPLX;
4092
4093                 if (new_bmcr != bmcr) {
4094                         /* BMCR_SPEED1000 is a reserved bit that needs
4095                          * to be set on write.
4096                          */
4097                         new_bmcr |= BMCR_SPEED1000;
4098
4099                         /* Force a linkdown */
4100                         if (netif_carrier_ok(tp->dev)) {
4101                                 u32 adv;
4102
4103                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4104                                 adv &= ~(ADVERTISE_1000XFULL |
4105                                          ADVERTISE_1000XHALF |
4106                                          ADVERTISE_SLCT);
4107                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4108                                 tg3_writephy(tp, MII_BMCR, bmcr |
4109                                                            BMCR_ANRESTART |
4110                                                            BMCR_ANENABLE);
4111                                 udelay(10);
4112                                 netif_carrier_off(tp->dev);
4113                         }
4114                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4115                         bmcr = new_bmcr;
4116                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4117                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4118                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4119                             ASIC_REV_5714) {
4120                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4121                                         bmsr |= BMSR_LSTATUS;
4122                                 else
4123                                         bmsr &= ~BMSR_LSTATUS;
4124                         }
4125                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126                 }
4127         }
4128
4129         if (bmsr & BMSR_LSTATUS) {
4130                 current_speed = SPEED_1000;
4131                 current_link_up = 1;
4132                 if (bmcr & BMCR_FULLDPLX)
4133                         current_duplex = DUPLEX_FULL;
4134                 else
4135                         current_duplex = DUPLEX_HALF;
4136
4137                 local_adv = 0;
4138                 remote_adv = 0;
4139
4140                 if (bmcr & BMCR_ANENABLE) {
4141                         u32 common;
4142
4143                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4144                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4145                         common = local_adv & remote_adv;
4146                         if (common & (ADVERTISE_1000XHALF |
4147                                       ADVERTISE_1000XFULL)) {
4148                                 if (common & ADVERTISE_1000XFULL)
4149                                         current_duplex = DUPLEX_FULL;
4150                                 else
4151                                         current_duplex = DUPLEX_HALF;
4152                         }
4153                         else
4154                                 current_link_up = 0;
4155                 }
4156         }
4157
4158         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4159                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4160
4161         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4162         if (tp->link_config.active_duplex == DUPLEX_HALF)
4163                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4164
4165         tw32_f(MAC_MODE, tp->mac_mode);
4166         udelay(40);
4167
4168         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4169
4170         tp->link_config.active_speed = current_speed;
4171         tp->link_config.active_duplex = current_duplex;
4172
4173         if (current_link_up != netif_carrier_ok(tp->dev)) {
4174                 if (current_link_up)
4175                         netif_carrier_on(tp->dev);
4176                 else {
4177                         netif_carrier_off(tp->dev);
4178                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4179                 }
4180                 tg3_link_report(tp);
4181         }
4182         return err;
4183 }
4184
4185 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4186 {
4187         if (tp->serdes_counter) {
4188                 /* Give autoneg time to complete. */
4189                 tp->serdes_counter--;
4190                 return;
4191         }
4192         if (!netif_carrier_ok(tp->dev) &&
4193             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4194                 u32 bmcr;
4195
4196                 tg3_readphy(tp, MII_BMCR, &bmcr);
4197                 if (bmcr & BMCR_ANENABLE) {
4198                         u32 phy1, phy2;
4199
4200                         /* Select shadow register 0x1f */
4201                         tg3_writephy(tp, 0x1c, 0x7c00);
4202                         tg3_readphy(tp, 0x1c, &phy1);
4203
4204                         /* Select expansion interrupt status register */
4205                         tg3_writephy(tp, 0x17, 0x0f01);
4206                         tg3_readphy(tp, 0x15, &phy2);
4207                         tg3_readphy(tp, 0x15, &phy2);
4208
4209                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210                                 /* We have signal detect and not receiving
4211                                  * config code words, link is up by parallel
4212                                  * detection.
4213                                  */
4214
4215                                 bmcr &= ~BMCR_ANENABLE;
4216                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217                                 tg3_writephy(tp, MII_BMCR, bmcr);
4218                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4219                         }
4220                 }
4221         }
4222         else if (netif_carrier_ok(tp->dev) &&
4223                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4224                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4225                 u32 phy2;
4226
4227                 /* Select expansion interrupt status register */
4228                 tg3_writephy(tp, 0x17, 0x0f01);
4229                 tg3_readphy(tp, 0x15, &phy2);
4230                 if (phy2 & 0x20) {
4231                         u32 bmcr;
4232
4233                         /* Config code words received, turn on autoneg. */
4234                         tg3_readphy(tp, MII_BMCR, &bmcr);
4235                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4236
4237                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4238
4239                 }
4240         }
4241 }
4242
4243 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4244 {
4245         int err;
4246
4247         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4248                 err = tg3_setup_fiber_phy(tp, force_reset);
4249         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4250                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4251         } else {
4252                 err = tg3_setup_copper_phy(tp, force_reset);
4253         }
4254
4255         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4256                 u32 val, scale;
4257
4258                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4259                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4260                         scale = 65;
4261                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4262                         scale = 6;
4263                 else
4264                         scale = 12;
4265
4266                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4267                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4268                 tw32(GRC_MISC_CFG, val);
4269         }
4270
4271         if (tp->link_config.active_speed == SPEED_1000 &&
4272             tp->link_config.active_duplex == DUPLEX_HALF)
4273                 tw32(MAC_TX_LENGTHS,
4274                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275                       (6 << TX_LENGTHS_IPG_SHIFT) |
4276                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277         else
4278                 tw32(MAC_TX_LENGTHS,
4279                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4280                       (6 << TX_LENGTHS_IPG_SHIFT) |
4281                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4282
4283         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4284                 if (netif_carrier_ok(tp->dev)) {
4285                         tw32(HOSTCC_STAT_COAL_TICKS,
4286                              tp->coal.stats_block_coalesce_usecs);
4287                 } else {
4288                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4289                 }
4290         }
4291
4292         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4293                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4294                 if (!netif_carrier_ok(tp->dev))
4295                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4296                               tp->pwrmgmt_thresh;
4297                 else
4298                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4299                 tw32(PCIE_PWR_MGMT_THRESH, val);
4300         }
4301
4302         return err;
4303 }
4304
4305 /* This is called whenever we suspect that the system chipset is re-
4306  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4307  * is bogus tx completions. We try to recover by setting the
4308  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4309  * in the workqueue.
4310  */
4311 static void tg3_tx_recover(struct tg3 *tp)
4312 {
4313         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4314                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4315
4316         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4317                "mapped I/O cycles to the network device, attempting to "
4318                "recover. Please report the problem to the driver maintainer "
4319                "and include system chipset information.\n", tp->dev->name);
4320
4321         spin_lock(&tp->lock);
4322         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4323         spin_unlock(&tp->lock);
4324 }
4325
4326 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4327 {
4328         smp_mb();
4329         return tnapi->tx_pending -
4330                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4331 }
4332
4333 /* Tigon3 never reports partial packet sends.  So we do not
4334  * need special logic to handle SKBs that have not had all
4335  * of their frags sent yet, like SunGEM does.
4336  */
4337 static void tg3_tx(struct tg3_napi *tnapi)
4338 {
4339         struct tg3 *tp = tnapi->tp;
4340         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4341         u32 sw_idx = tnapi->tx_cons;
4342         struct netdev_queue *txq;
4343         int index = tnapi - tp->napi;
4344
4345         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4346                 index--;
4347
4348         txq = netdev_get_tx_queue(tp->dev, index);
4349
4350         while (sw_idx != hw_idx) {
4351                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4352                 struct sk_buff *skb = ri->skb;
4353                 int i, tx_bug = 0;
4354
4355                 if (unlikely(skb == NULL)) {
4356                         tg3_tx_recover(tp);
4357                         return;
4358                 }
4359
4360                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4361
4362                 ri->skb = NULL;
4363
4364                 sw_idx = NEXT_TX(sw_idx);
4365
4366                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4367                         ri = &tnapi->tx_buffers[sw_idx];
4368                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4369                                 tx_bug = 1;
4370                         sw_idx = NEXT_TX(sw_idx);
4371                 }
4372
4373                 dev_kfree_skb(skb);
4374
4375                 if (unlikely(tx_bug)) {
4376                         tg3_tx_recover(tp);
4377                         return;
4378                 }
4379         }
4380
4381         tnapi->tx_cons = sw_idx;
4382
4383         /* Need to make the tx_cons update visible to tg3_start_xmit()
4384          * before checking for netif_queue_stopped().  Without the
4385          * memory barrier, there is a small possibility that tg3_start_xmit()
4386          * will miss it and cause the queue to be stopped forever.
4387          */
4388         smp_mb();
4389
4390         if (unlikely(netif_tx_queue_stopped(txq) &&
4391                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4392                 __netif_tx_lock(txq, smp_processor_id());
4393                 if (netif_tx_queue_stopped(txq) &&
4394                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4395                         netif_tx_wake_queue(txq);
4396                 __netif_tx_unlock(txq);
4397         }
4398 }
4399
4400 /* Returns size of skb allocated or < 0 on error.
4401  *
4402  * We only need to fill in the address because the other members
4403  * of the RX descriptor are invariant, see tg3_init_rings.
4404  *
4405  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4406  * posting buffers we only dirty the first cache line of the RX
4407  * descriptor (containing the address).  Whereas for the RX status
4408  * buffers the cpu only reads the last cacheline of the RX descriptor
4409  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4410  */
4411 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi,
4412                             struct tg3_rx_prodring_set *tpr,
4413                             u32 opaque_key, u32 dest_idx_unmasked)
4414 {
4415         struct tg3 *tp = tnapi->tp;
4416         struct tg3_rx_buffer_desc *desc;
4417         struct ring_info *map, *src_map;
4418         struct sk_buff *skb;
4419         dma_addr_t mapping;
4420         int skb_size, dest_idx;
4421
4422         src_map = NULL;
4423         switch (opaque_key) {
4424         case RXD_OPAQUE_RING_STD:
4425                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4426                 desc = &tpr->rx_std[dest_idx];
4427                 map = &tpr->rx_std_buffers[dest_idx];
4428                 skb_size = tp->rx_pkt_map_sz;
4429                 break;
4430
4431         case RXD_OPAQUE_RING_JUMBO:
4432                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4433                 desc = &tpr->rx_jmb[dest_idx].std;
4434                 map = &tpr->rx_jmb_buffers[dest_idx];
4435                 skb_size = TG3_RX_JMB_MAP_SZ;
4436                 break;
4437
4438         default:
4439                 return -EINVAL;
4440         }
4441
4442         /* Do not overwrite any of the map or rp information
4443          * until we are sure we can commit to a new buffer.
4444          *
4445          * Callers depend upon this behavior and assume that
4446          * we leave everything unchanged if we fail.
4447          */
4448         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4449         if (skb == NULL)
4450                 return -ENOMEM;
4451
4452         skb_reserve(skb, tp->rx_offset);
4453
4454         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4455                                  PCI_DMA_FROMDEVICE);
4456         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4457                 dev_kfree_skb(skb);
4458                 return -EIO;
4459         }
4460
4461         map->skb = skb;
4462         pci_unmap_addr_set(map, mapping, mapping);
4463
4464         desc->addr_hi = ((u64)mapping >> 32);
4465         desc->addr_lo = ((u64)mapping & 0xffffffff);
4466
4467         return skb_size;
4468 }
4469
4470 /* We only need to move over in the address because the other
4471  * members of the RX descriptor are invariant.  See notes above
4472  * tg3_alloc_rx_skb for full details.
4473  */
4474 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4475                            struct tg3_rx_prodring_set *dpr,
4476                            u32 opaque_key, int src_idx,
4477                            u32 dest_idx_unmasked)
4478 {
4479         struct tg3 *tp = tnapi->tp;
4480         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4481         struct ring_info *src_map, *dest_map;
4482         int dest_idx;
4483         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4484
4485         switch (opaque_key) {
4486         case RXD_OPAQUE_RING_STD:
4487                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4488                 dest_desc = &dpr->rx_std[dest_idx];
4489                 dest_map = &dpr->rx_std_buffers[dest_idx];
4490                 src_desc = &spr->rx_std[src_idx];
4491                 src_map = &spr->rx_std_buffers[src_idx];
4492                 break;
4493
4494         case RXD_OPAQUE_RING_JUMBO:
4495                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4496                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4497                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4498                 src_desc = &spr->rx_jmb[src_idx].std;
4499                 src_map = &spr->rx_jmb_buffers[src_idx];
4500                 break;
4501
4502         default:
4503                 return;
4504         }
4505
4506         dest_map->skb = src_map->skb;
4507         pci_unmap_addr_set(dest_map, mapping,
4508                            pci_unmap_addr(src_map, mapping));
4509         dest_desc->addr_hi = src_desc->addr_hi;
4510         dest_desc->addr_lo = src_desc->addr_lo;
4511         src_map->skb = NULL;
4512 }
4513
4514 /* The RX ring scheme is composed of multiple rings which post fresh
4515  * buffers to the chip, and one special ring the chip uses to report
4516  * status back to the host.
4517  *
4518  * The special ring reports the status of received packets to the
4519  * host.  The chip does not write into the original descriptor the
4520  * RX buffer was obtained from.  The chip simply takes the original
4521  * descriptor as provided by the host, updates the status and length
4522  * field, then writes this into the next status ring entry.
4523  *
4524  * Each ring the host uses to post buffers to the chip is described
4525  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4526  * it is first placed into the on-chip ram.  When the packet's length
4527  * is known, it walks down the TG3_BDINFO entries to select the ring.
4528  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4529  * which is within the range of the new packet's length is chosen.
4530  *
4531  * The "separate ring for rx status" scheme may sound queer, but it makes
4532  * sense from a cache coherency perspective.  If only the host writes
4533  * to the buffer post rings, and only the chip writes to the rx status
4534  * rings, then cache lines never move beyond shared-modified state.
4535  * If both the host and chip were to write into the same ring, cache line
4536  * eviction could occur since both entities want it in an exclusive state.
4537  */
4538 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4539 {
4540         struct tg3 *tp = tnapi->tp;
4541         u32 work_mask, rx_std_posted = 0;
4542         u32 sw_idx = tnapi->rx_rcb_ptr;
4543         u16 hw_idx;
4544         int received;
4545         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4546
4547         hw_idx = *(tnapi->rx_rcb_prod_idx);
4548         /*
4549          * We need to order the read of hw_idx and the read of
4550          * the opaque cookie.
4551          */
4552         rmb();
4553         work_mask = 0;
4554         received = 0;
4555         while (sw_idx != hw_idx && budget > 0) {
4556                 struct ring_info *ri;
4557                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4558                 unsigned int len;
4559                 struct sk_buff *skb;
4560                 dma_addr_t dma_addr;
4561                 u32 opaque_key, desc_idx, *post_ptr;
4562
4563                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4564                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4565                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4566                         ri = &tpr->rx_std_buffers[desc_idx];
4567                         dma_addr = pci_unmap_addr(ri, mapping);
4568                         skb = ri->skb;
4569                         post_ptr = &tpr->rx_std_ptr;
4570                         rx_std_posted++;
4571                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4572                         ri = &tpr->rx_jmb_buffers[desc_idx];
4573                         dma_addr = pci_unmap_addr(ri, mapping);
4574                         skb = ri->skb;
4575                         post_ptr = &tpr->rx_jmb_ptr;
4576                 } else
4577                         goto next_pkt_nopost;
4578
4579                 work_mask |= opaque_key;
4580
4581                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4582                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4583                 drop_it:
4584                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4585                                        desc_idx, *post_ptr);
4586                 drop_it_no_recycle:
4587                         /* Other statistics kept track of by card. */
4588                         tp->net_stats.rx_dropped++;
4589                         goto next_pkt;
4590                 }
4591
4592                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4593                       ETH_FCS_LEN;
4594
4595                 if (len > RX_COPY_THRESHOLD
4596                         && tp->rx_offset == NET_IP_ALIGN
4597                         /* rx_offset will likely not equal NET_IP_ALIGN
4598                          * if this is a 5701 card running in PCI-X mode
4599                          * [see tg3_get_invariants()]
4600                          */
4601                 ) {
4602                         int skb_size;
4603
4604                         skb_size = tg3_alloc_rx_skb(tnapi, tpr, opaque_key,
4605                                                     *post_ptr);
4606                         if (skb_size < 0)
4607                                 goto drop_it;
4608
4609                         ri->skb = NULL;
4610
4611                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4612                                          PCI_DMA_FROMDEVICE);
4613
4614                         skb_put(skb, len);
4615                 } else {
4616                         struct sk_buff *copy_skb;
4617
4618                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4619                                        desc_idx, *post_ptr);
4620
4621                         copy_skb = netdev_alloc_skb(tp->dev,
4622                                                     len + TG3_RAW_IP_ALIGN);
4623                         if (copy_skb == NULL)
4624                                 goto drop_it_no_recycle;
4625
4626                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4627                         skb_put(copy_skb, len);
4628                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4629                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4630                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4631
4632                         /* We'll reuse the original ring buffer. */
4633                         skb = copy_skb;
4634                 }
4635
4636                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4637                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4638                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4639                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4640                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4641                 else
4642                         skb->ip_summed = CHECKSUM_NONE;
4643
4644                 skb->protocol = eth_type_trans(skb, tp->dev);
4645
4646                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4647                     skb->protocol != htons(ETH_P_8021Q)) {
4648                         dev_kfree_skb(skb);
4649                         goto next_pkt;
4650                 }
4651
4652 #if TG3_VLAN_TAG_USED
4653                 if (tp->vlgrp != NULL &&
4654                     desc->type_flags & RXD_FLAG_VLAN) {
4655                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4656                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4657                 } else
4658 #endif
4659                         napi_gro_receive(&tnapi->napi, skb);
4660
4661                 received++;
4662                 budget--;
4663
4664 next_pkt:
4665                 (*post_ptr)++;
4666
4667                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4668                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4669
4670                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4671                                      TG3_64BIT_REG_LOW, idx);
4672                         work_mask &= ~RXD_OPAQUE_RING_STD;
4673                         rx_std_posted = 0;
4674                 }
4675 next_pkt_nopost:
4676                 sw_idx++;
4677                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4678
4679                 /* Refresh hw_idx to see if there is new work */
4680                 if (sw_idx == hw_idx) {
4681                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4682                         rmb();
4683                 }
4684         }
4685
4686         /* ACK the status ring. */
4687         tnapi->rx_rcb_ptr = sw_idx;
4688         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4689
4690         /* Refill RX ring(s). */
4691         if (work_mask & RXD_OPAQUE_RING_STD) {
4692                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4693                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4694                              sw_idx);
4695         }
4696         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4697                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4698                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4699                              sw_idx);
4700         }
4701         mmiowb();
4702
4703         return received;
4704 }
4705
4706 static void tg3_poll_link(struct tg3 *tp)
4707 {
4708         /* handle link change and other phy events */
4709         if (!(tp->tg3_flags &
4710               (TG3_FLAG_USE_LINKCHG_REG |
4711                TG3_FLAG_POLL_SERDES))) {
4712                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4713
4714                 if (sblk->status & SD_STATUS_LINK_CHG) {
4715                         sblk->status = SD_STATUS_UPDATED |
4716                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4717                         spin_lock(&tp->lock);
4718                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4719                                 tw32_f(MAC_STATUS,
4720                                      (MAC_STATUS_SYNC_CHANGED |
4721                                       MAC_STATUS_CFG_CHANGED |
4722                                       MAC_STATUS_MI_COMPLETION |
4723                                       MAC_STATUS_LNKSTATE_CHANGED));
4724                                 udelay(40);
4725                         } else
4726                                 tg3_setup_phy(tp, 0);
4727                         spin_unlock(&tp->lock);
4728                 }
4729         }
4730 }
4731
4732 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4733 {
4734         struct tg3 *tp = tnapi->tp;
4735
4736         /* run TX completion thread */
4737         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4738                 tg3_tx(tnapi);
4739                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4740                         return work_done;
4741         }
4742
4743         /* run RX thread, within the bounds set by NAPI.
4744          * All RX "locking" is done by ensuring outside
4745          * code synchronizes with tg3->napi.poll()
4746          */
4747         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4748                 work_done += tg3_rx(tnapi, budget - work_done);
4749
4750         return work_done;
4751 }
4752
4753 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4754 {
4755         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4756         struct tg3 *tp = tnapi->tp;
4757         int work_done = 0;
4758         struct tg3_hw_status *sblk = tnapi->hw_status;
4759
4760         while (1) {
4761                 work_done = tg3_poll_work(tnapi, work_done, budget);
4762
4763                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4764                         goto tx_recovery;
4765
4766                 if (unlikely(work_done >= budget))
4767                         break;
4768
4769                 /* tp->last_tag is used in tg3_restart_ints() below
4770                  * to tell the hw how much work has been processed,
4771                  * so we must read it before checking for more work.
4772                  */
4773                 tnapi->last_tag = sblk->status_tag;
4774                 tnapi->last_irq_tag = tnapi->last_tag;
4775                 rmb();
4776
4777                 /* check for RX/TX work to do */
4778                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4779                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4780                         napi_complete(napi);
4781                         /* Reenable interrupts. */
4782                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4783                         mmiowb();
4784                         break;
4785                 }
4786         }
4787
4788         return work_done;
4789
4790 tx_recovery:
4791         /* work_done is guaranteed to be less than budget. */
4792         napi_complete(napi);
4793         schedule_work(&tp->reset_task);
4794         return work_done;
4795 }
4796
4797 static int tg3_poll(struct napi_struct *napi, int budget)
4798 {
4799         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4800         struct tg3 *tp = tnapi->tp;
4801         int work_done = 0;
4802         struct tg3_hw_status *sblk = tnapi->hw_status;
4803
4804         while (1) {
4805                 tg3_poll_link(tp);
4806
4807                 work_done = tg3_poll_work(tnapi, work_done, budget);
4808
4809                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4810                         goto tx_recovery;
4811
4812                 if (unlikely(work_done >= budget))
4813                         break;
4814
4815                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4816                         /* tp->last_tag is used in tg3_int_reenable() below
4817                          * to tell the hw how much work has been processed,
4818                          * so we must read it before checking for more work.
4819                          */
4820                         tnapi->last_tag = sblk->status_tag;
4821                         tnapi->last_irq_tag = tnapi->last_tag;
4822                         rmb();
4823                 } else
4824                         sblk->status &= ~SD_STATUS_UPDATED;
4825
4826                 if (likely(!tg3_has_work(tnapi))) {
4827                         napi_complete(napi);
4828                         tg3_int_reenable(tnapi);
4829                         break;
4830                 }
4831         }
4832
4833         return work_done;
4834
4835 tx_recovery:
4836         /* work_done is guaranteed to be less than budget. */
4837         napi_complete(napi);
4838         schedule_work(&tp->reset_task);
4839         return work_done;
4840 }
4841
4842 static void tg3_irq_quiesce(struct tg3 *tp)
4843 {
4844         int i;
4845
4846         BUG_ON(tp->irq_sync);
4847
4848         tp->irq_sync = 1;
4849         smp_mb();
4850
4851         for (i = 0; i < tp->irq_cnt; i++)
4852                 synchronize_irq(tp->napi[i].irq_vec);
4853 }
4854
4855 static inline int tg3_irq_sync(struct tg3 *tp)
4856 {
4857         return tp->irq_sync;
4858 }
4859
4860 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4861  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4862  * with as well.  Most of the time, this is not necessary except when
4863  * shutting down the device.
4864  */
4865 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4866 {
4867         spin_lock_bh(&tp->lock);
4868         if (irq_sync)
4869                 tg3_irq_quiesce(tp);
4870 }
4871
4872 static inline void tg3_full_unlock(struct tg3 *tp)
4873 {
4874         spin_unlock_bh(&tp->lock);
4875 }
4876
4877 /* One-shot MSI handler - Chip automatically disables interrupt
4878  * after sending MSI so driver doesn't have to do it.
4879  */
4880 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4881 {
4882         struct tg3_napi *tnapi = dev_id;
4883         struct tg3 *tp = tnapi->tp;
4884
4885         prefetch(tnapi->hw_status);
4886         if (tnapi->rx_rcb)
4887                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4888
4889         if (likely(!tg3_irq_sync(tp)))
4890                 napi_schedule(&tnapi->napi);
4891
4892         return IRQ_HANDLED;
4893 }
4894
4895 /* MSI ISR - No need to check for interrupt sharing and no need to
4896  * flush status block and interrupt mailbox. PCI ordering rules
4897  * guarantee that MSI will arrive after the status block.
4898  */
4899 static irqreturn_t tg3_msi(int irq, void *dev_id)
4900 {
4901         struct tg3_napi *tnapi = dev_id;
4902         struct tg3 *tp = tnapi->tp;
4903
4904         prefetch(tnapi->hw_status);
4905         if (tnapi->rx_rcb)
4906                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4907         /*
4908          * Writing any value to intr-mbox-0 clears PCI INTA# and
4909          * chip-internal interrupt pending events.
4910          * Writing non-zero to intr-mbox-0 additional tells the
4911          * NIC to stop sending us irqs, engaging "in-intr-handler"
4912          * event coalescing.
4913          */
4914         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4915         if (likely(!tg3_irq_sync(tp)))
4916                 napi_schedule(&tnapi->napi);
4917
4918         return IRQ_RETVAL(1);
4919 }
4920
4921 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4922 {
4923         struct tg3_napi *tnapi = dev_id;
4924         struct tg3 *tp = tnapi->tp;
4925         struct tg3_hw_status *sblk = tnapi->hw_status;
4926         unsigned int handled = 1;
4927
4928         /* In INTx mode, it is possible for the interrupt to arrive at
4929          * the CPU before the status block posted prior to the interrupt.
4930          * Reading the PCI State register will confirm whether the
4931          * interrupt is ours and will flush the status block.
4932          */
4933         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4934                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4935                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4936                         handled = 0;
4937                         goto out;
4938                 }
4939         }
4940
4941         /*
4942          * Writing any value to intr-mbox-0 clears PCI INTA# and
4943          * chip-internal interrupt pending events.
4944          * Writing non-zero to intr-mbox-0 additional tells the
4945          * NIC to stop sending us irqs, engaging "in-intr-handler"
4946          * event coalescing.
4947          *
4948          * Flush the mailbox to de-assert the IRQ immediately to prevent
4949          * spurious interrupts.  The flush impacts performance but
4950          * excessive spurious interrupts can be worse in some cases.
4951          */
4952         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4953         if (tg3_irq_sync(tp))
4954                 goto out;
4955         sblk->status &= ~SD_STATUS_UPDATED;
4956         if (likely(tg3_has_work(tnapi))) {
4957                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4958                 napi_schedule(&tnapi->napi);
4959         } else {
4960                 /* No work, shared interrupt perhaps?  re-enable
4961                  * interrupts, and flush that PCI write
4962                  */
4963                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4964                                0x00000000);
4965         }
4966 out:
4967         return IRQ_RETVAL(handled);
4968 }
4969
4970 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4971 {
4972         struct tg3_napi *tnapi = dev_id;
4973         struct tg3 *tp = tnapi->tp;
4974         struct tg3_hw_status *sblk = tnapi->hw_status;
4975         unsigned int handled = 1;
4976
4977         /* In INTx mode, it is possible for the interrupt to arrive at
4978          * the CPU before the status block posted prior to the interrupt.
4979          * Reading the PCI State register will confirm whether the
4980          * interrupt is ours and will flush the status block.
4981          */
4982         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4983                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4984                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4985                         handled = 0;
4986                         goto out;
4987                 }
4988         }
4989
4990         /*
4991          * writing any value to intr-mbox-0 clears PCI INTA# and
4992          * chip-internal interrupt pending events.
4993          * writing non-zero to intr-mbox-0 additional tells the
4994          * NIC to stop sending us irqs, engaging "in-intr-handler"
4995          * event coalescing.
4996          *
4997          * Flush the mailbox to de-assert the IRQ immediately to prevent
4998          * spurious interrupts.  The flush impacts performance but
4999          * excessive spurious interrupts can be worse in some cases.
5000          */
5001         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5002
5003         /*
5004          * In a shared interrupt configuration, sometimes other devices'
5005          * interrupts will scream.  We record the current status tag here
5006          * so that the above check can report that the screaming interrupts
5007          * are unhandled.  Eventually they will be silenced.
5008          */
5009         tnapi->last_irq_tag = sblk->status_tag;
5010
5011         if (tg3_irq_sync(tp))
5012                 goto out;
5013
5014         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5015
5016         napi_schedule(&tnapi->napi);
5017
5018 out:
5019         return IRQ_RETVAL(handled);
5020 }
5021
5022 /* ISR for interrupt test */
5023 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5024 {
5025         struct tg3_napi *tnapi = dev_id;
5026         struct tg3 *tp = tnapi->tp;
5027         struct tg3_hw_status *sblk = tnapi->hw_status;
5028
5029         if ((sblk->status & SD_STATUS_UPDATED) ||
5030             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5031                 tg3_disable_ints(tp);
5032                 return IRQ_RETVAL(1);
5033         }
5034         return IRQ_RETVAL(0);
5035 }
5036
5037 static int tg3_init_hw(struct tg3 *, int);
5038 static int tg3_halt(struct tg3 *, int, int);
5039
5040 /* Restart hardware after configuration changes, self-test, etc.
5041  * Invoked with tp->lock held.
5042  */
5043 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5044         __releases(tp->lock)
5045         __acquires(tp->lock)
5046 {
5047         int err;
5048
5049         err = tg3_init_hw(tp, reset_phy);
5050         if (err) {
5051                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5052                        "aborting.\n", tp->dev->name);
5053                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5054                 tg3_full_unlock(tp);
5055                 del_timer_sync(&tp->timer);
5056                 tp->irq_sync = 0;
5057                 tg3_napi_enable(tp);
5058                 dev_close(tp->dev);
5059                 tg3_full_lock(tp, 0);
5060         }
5061         return err;
5062 }
5063
5064 #ifdef CONFIG_NET_POLL_CONTROLLER
5065 static void tg3_poll_controller(struct net_device *dev)
5066 {
5067         int i;
5068         struct tg3 *tp = netdev_priv(dev);
5069
5070         for (i = 0; i < tp->irq_cnt; i++)
5071                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5072 }
5073 #endif
5074
5075 static void tg3_reset_task(struct work_struct *work)
5076 {
5077         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5078         int err;
5079         unsigned int restart_timer;
5080
5081         tg3_full_lock(tp, 0);
5082
5083         if (!netif_running(tp->dev)) {
5084                 tg3_full_unlock(tp);
5085                 return;
5086         }
5087
5088         tg3_full_unlock(tp);
5089
5090         tg3_phy_stop(tp);
5091
5092         tg3_netif_stop(tp);
5093
5094         tg3_full_lock(tp, 1);
5095
5096         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5097         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5098
5099         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5100                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5101                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5102                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5103                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5104         }
5105
5106         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5107         err = tg3_init_hw(tp, 1);
5108         if (err)
5109                 goto out;
5110
5111         tg3_netif_start(tp);
5112
5113         if (restart_timer)
5114                 mod_timer(&tp->timer, jiffies + 1);
5115
5116 out:
5117         tg3_full_unlock(tp);
5118
5119         if (!err)
5120                 tg3_phy_start(tp);
5121 }
5122
5123 static void tg3_dump_short_state(struct tg3 *tp)
5124 {
5125         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5126                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5127         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5128                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5129 }
5130
5131 static void tg3_tx_timeout(struct net_device *dev)
5132 {
5133         struct tg3 *tp = netdev_priv(dev);
5134
5135         if (netif_msg_tx_err(tp)) {
5136                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5137                        dev->name);
5138                 tg3_dump_short_state(tp);
5139         }
5140
5141         schedule_work(&tp->reset_task);
5142 }
5143
5144 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5145 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5146 {
5147         u32 base = (u32) mapping & 0xffffffff;
5148
5149         return ((base > 0xffffdcc0) &&
5150                 (base + len + 8 < base));
5151 }
5152
5153 /* Test for DMA addresses > 40-bit */
5154 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5155                                           int len)
5156 {
5157 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5158         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5159                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5160         return 0;
5161 #else
5162         return 0;
5163 #endif
5164 }
5165
5166 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5167
5168 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5169 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5170                                        struct sk_buff *skb, u32 last_plus_one,
5171                                        u32 *start, u32 base_flags, u32 mss)
5172 {
5173         struct tg3 *tp = tnapi->tp;
5174         struct sk_buff *new_skb;
5175         dma_addr_t new_addr = 0;
5176         u32 entry = *start;
5177         int i, ret = 0;
5178
5179         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5180                 new_skb = skb_copy(skb, GFP_ATOMIC);
5181         else {
5182                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5183
5184                 new_skb = skb_copy_expand(skb,
5185                                           skb_headroom(skb) + more_headroom,
5186                                           skb_tailroom(skb), GFP_ATOMIC);
5187         }
5188
5189         if (!new_skb) {
5190                 ret = -1;
5191         } else {
5192                 /* New SKB is guaranteed to be linear. */
5193                 entry = *start;
5194                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5195                 new_addr = skb_shinfo(new_skb)->dma_head;
5196
5197                 /* Make sure new skb does not cross any 4G boundaries.
5198                  * Drop the packet if it does.
5199                  */
5200                 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5201                             tg3_4g_overflow_test(new_addr, new_skb->len))) {
5202                         if (!ret)
5203                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5204                                               DMA_TO_DEVICE);
5205                         ret = -1;
5206                         dev_kfree_skb(new_skb);
5207                         new_skb = NULL;
5208                 } else {
5209                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5210                                     base_flags, 1 | (mss << 1));
5211                         *start = NEXT_TX(entry);
5212                 }
5213         }
5214
5215         /* Now clean up the sw ring entries. */
5216         i = 0;
5217         while (entry != last_plus_one) {
5218                 if (i == 0)
5219                         tnapi->tx_buffers[entry].skb = new_skb;
5220                 else
5221                         tnapi->tx_buffers[entry].skb = NULL;
5222                 entry = NEXT_TX(entry);
5223                 i++;
5224         }
5225
5226         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5227         dev_kfree_skb(skb);
5228
5229         return ret;
5230 }
5231
5232 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5233                         dma_addr_t mapping, int len, u32 flags,
5234                         u32 mss_and_is_end)
5235 {
5236         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5237         int is_end = (mss_and_is_end & 0x1);
5238         u32 mss = (mss_and_is_end >> 1);
5239         u32 vlan_tag = 0;
5240
5241         if (is_end)
5242                 flags |= TXD_FLAG_END;
5243         if (flags & TXD_FLAG_VLAN) {
5244                 vlan_tag = flags >> 16;
5245                 flags &= 0xffff;
5246         }
5247         vlan_tag |= (mss << TXD_MSS_SHIFT);
5248
5249         txd->addr_hi = ((u64) mapping >> 32);
5250         txd->addr_lo = ((u64) mapping & 0xffffffff);
5251         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5252         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5253 }
5254
5255 /* hard_start_xmit for devices that don't have any bugs and
5256  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5257  */
5258 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5259                                   struct net_device *dev)
5260 {
5261         struct tg3 *tp = netdev_priv(dev);
5262         u32 len, entry, base_flags, mss;
5263         struct skb_shared_info *sp;
5264         dma_addr_t mapping;
5265         struct tg3_napi *tnapi;
5266         struct netdev_queue *txq;
5267
5268         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5269         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5270         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5271                 tnapi++;
5272
5273         /* We are running in BH disabled context with netif_tx_lock
5274          * and TX reclaim runs via tp->napi.poll inside of a software
5275          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5276          * no IRQ context deadlocks to worry about either.  Rejoice!
5277          */
5278         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5279                 if (!netif_tx_queue_stopped(txq)) {
5280                         netif_tx_stop_queue(txq);
5281
5282                         /* This is a hard error, log it. */
5283                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5284                                "queue awake!\n", dev->name);
5285                 }
5286                 return NETDEV_TX_BUSY;
5287         }
5288
5289         entry = tnapi->tx_prod;
5290         base_flags = 0;
5291         mss = 0;
5292         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5293                 int tcp_opt_len, ip_tcp_len;
5294                 u32 hdrlen;
5295
5296                 if (skb_header_cloned(skb) &&
5297                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5298                         dev_kfree_skb(skb);
5299                         goto out_unlock;
5300                 }
5301
5302                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5303                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5304                 else {
5305                         struct iphdr *iph = ip_hdr(skb);
5306
5307                         tcp_opt_len = tcp_optlen(skb);
5308                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5309
5310                         iph->check = 0;
5311                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5312                         hdrlen = ip_tcp_len + tcp_opt_len;
5313                 }
5314
5315                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5316                         mss |= (hdrlen & 0xc) << 12;
5317                         if (hdrlen & 0x10)
5318                                 base_flags |= 0x00000010;
5319                         base_flags |= (hdrlen & 0x3e0) << 5;
5320                 } else
5321                         mss |= hdrlen << 9;
5322
5323                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5324                                TXD_FLAG_CPU_POST_DMA);
5325
5326                 tcp_hdr(skb)->check = 0;
5327
5328         }
5329         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5330                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5331 #if TG3_VLAN_TAG_USED
5332         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5333                 base_flags |= (TXD_FLAG_VLAN |
5334                                (vlan_tx_tag_get(skb) << 16));
5335 #endif
5336
5337         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5338                 dev_kfree_skb(skb);
5339                 goto out_unlock;
5340         }
5341
5342         sp = skb_shinfo(skb);
5343
5344         mapping = sp->dma_head;
5345
5346         tnapi->tx_buffers[entry].skb = skb;
5347
5348         len = skb_headlen(skb);
5349
5350         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5351             !mss && skb->len > ETH_DATA_LEN)
5352                 base_flags |= TXD_FLAG_JMB_PKT;
5353
5354         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5355                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5356
5357         entry = NEXT_TX(entry);
5358
5359         /* Now loop through additional data fragments, and queue them. */
5360         if (skb_shinfo(skb)->nr_frags > 0) {
5361                 unsigned int i, last;
5362
5363                 last = skb_shinfo(skb)->nr_frags - 1;
5364                 for (i = 0; i <= last; i++) {
5365                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5366
5367                         len = frag->size;
5368                         mapping = sp->dma_maps[i];
5369                         tnapi->tx_buffers[entry].skb = NULL;
5370
5371                         tg3_set_txd(tnapi, entry, mapping, len,
5372                                     base_flags, (i == last) | (mss << 1));
5373
5374                         entry = NEXT_TX(entry);
5375                 }
5376         }
5377
5378         /* Packets are ready, update Tx producer idx local and on card. */
5379         tw32_tx_mbox(tnapi->prodmbox, entry);
5380
5381         tnapi->tx_prod = entry;
5382         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5383                 netif_tx_stop_queue(txq);
5384                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5385                         netif_tx_wake_queue(txq);
5386         }
5387
5388 out_unlock:
5389         mmiowb();
5390
5391         return NETDEV_TX_OK;
5392 }
5393
5394 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5395                                           struct net_device *);
5396
5397 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5398  * TSO header is greater than 80 bytes.
5399  */
5400 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5401 {
5402         struct sk_buff *segs, *nskb;
5403         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5404
5405         /* Estimate the number of fragments in the worst case */
5406         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5407                 netif_stop_queue(tp->dev);
5408                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5409                         return NETDEV_TX_BUSY;
5410
5411                 netif_wake_queue(tp->dev);
5412         }
5413
5414         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5415         if (IS_ERR(segs))
5416                 goto tg3_tso_bug_end;
5417
5418         do {
5419                 nskb = segs;
5420                 segs = segs->next;
5421                 nskb->next = NULL;
5422                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5423         } while (segs);
5424
5425 tg3_tso_bug_end:
5426         dev_kfree_skb(skb);
5427
5428         return NETDEV_TX_OK;
5429 }
5430
5431 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5432  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5433  */
5434 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5435                                           struct net_device *dev)
5436 {
5437         struct tg3 *tp = netdev_priv(dev);
5438         u32 len, entry, base_flags, mss;
5439         struct skb_shared_info *sp;
5440         int would_hit_hwbug;
5441         dma_addr_t mapping;
5442         struct tg3_napi *tnapi;
5443         struct netdev_queue *txq;
5444
5445         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5446         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5447         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5448                 tnapi++;
5449
5450         /* We are running in BH disabled context with netif_tx_lock
5451          * and TX reclaim runs via tp->napi.poll inside of a software
5452          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5453          * no IRQ context deadlocks to worry about either.  Rejoice!
5454          */
5455         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5456                 if (!netif_tx_queue_stopped(txq)) {
5457                         netif_tx_stop_queue(txq);
5458
5459                         /* This is a hard error, log it. */
5460                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5461                                "queue awake!\n", dev->name);
5462                 }
5463                 return NETDEV_TX_BUSY;
5464         }
5465
5466         entry = tnapi->tx_prod;
5467         base_flags = 0;
5468         if (skb->ip_summed == CHECKSUM_PARTIAL)
5469                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5470
5471         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5472                 struct iphdr *iph;
5473                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5474
5475                 if (skb_header_cloned(skb) &&
5476                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5477                         dev_kfree_skb(skb);
5478                         goto out_unlock;
5479                 }
5480
5481                 tcp_opt_len = tcp_optlen(skb);
5482                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5483
5484                 hdr_len = ip_tcp_len + tcp_opt_len;
5485                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5486                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5487                         return (tg3_tso_bug(tp, skb));
5488
5489                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5490                                TXD_FLAG_CPU_POST_DMA);
5491
5492                 iph = ip_hdr(skb);
5493                 iph->check = 0;
5494                 iph->tot_len = htons(mss + hdr_len);
5495                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5496                         tcp_hdr(skb)->check = 0;
5497                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5498                 } else
5499                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5500                                                                  iph->daddr, 0,
5501                                                                  IPPROTO_TCP,
5502                                                                  0);
5503
5504                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5505                         mss |= (hdr_len & 0xc) << 12;
5506                         if (hdr_len & 0x10)
5507                                 base_flags |= 0x00000010;
5508                         base_flags |= (hdr_len & 0x3e0) << 5;
5509                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5510                         mss |= hdr_len << 9;
5511                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5512                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5513                         if (tcp_opt_len || iph->ihl > 5) {
5514                                 int tsflags;
5515
5516                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5517                                 mss |= (tsflags << 11);
5518                         }
5519                 } else {
5520                         if (tcp_opt_len || iph->ihl > 5) {
5521                                 int tsflags;
5522
5523                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5524                                 base_flags |= tsflags << 12;
5525                         }
5526                 }
5527         }
5528 #if TG3_VLAN_TAG_USED
5529         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5530                 base_flags |= (TXD_FLAG_VLAN |
5531                                (vlan_tx_tag_get(skb) << 16));
5532 #endif
5533
5534         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5535             !mss && skb->len > ETH_DATA_LEN)
5536                 base_flags |= TXD_FLAG_JMB_PKT;
5537
5538         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5539                 dev_kfree_skb(skb);
5540                 goto out_unlock;
5541         }
5542
5543         sp = skb_shinfo(skb);
5544
5545         mapping = sp->dma_head;
5546
5547         tnapi->tx_buffers[entry].skb = skb;
5548
5549         would_hit_hwbug = 0;
5550
5551         len = skb_headlen(skb);
5552
5553         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5554                 would_hit_hwbug = 1;
5555
5556         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5557             tg3_4g_overflow_test(mapping, len))
5558                 would_hit_hwbug = 1;
5559
5560         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5561             tg3_40bit_overflow_test(tp, mapping, len))
5562                 would_hit_hwbug = 1;
5563
5564         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5565                 would_hit_hwbug = 1;
5566
5567         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5568                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5569
5570         entry = NEXT_TX(entry);
5571
5572         /* Now loop through additional data fragments, and queue them. */
5573         if (skb_shinfo(skb)->nr_frags > 0) {
5574                 unsigned int i, last;
5575
5576                 last = skb_shinfo(skb)->nr_frags - 1;
5577                 for (i = 0; i <= last; i++) {
5578                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5579
5580                         len = frag->size;
5581                         mapping = sp->dma_maps[i];
5582
5583                         tnapi->tx_buffers[entry].skb = NULL;
5584
5585                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5586                             len <= 8)
5587                                 would_hit_hwbug = 1;
5588
5589                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5590                             tg3_4g_overflow_test(mapping, len))
5591                                 would_hit_hwbug = 1;
5592
5593                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5594                             tg3_40bit_overflow_test(tp, mapping, len))
5595                                 would_hit_hwbug = 1;
5596
5597                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5598                                 tg3_set_txd(tnapi, entry, mapping, len,
5599                                             base_flags, (i == last)|(mss << 1));
5600                         else
5601                                 tg3_set_txd(tnapi, entry, mapping, len,
5602                                             base_flags, (i == last));
5603
5604                         entry = NEXT_TX(entry);
5605                 }
5606         }
5607
5608         if (would_hit_hwbug) {
5609                 u32 last_plus_one = entry;
5610                 u32 start;
5611
5612                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5613                 start &= (TG3_TX_RING_SIZE - 1);
5614
5615                 /* If the workaround fails due to memory/mapping
5616                  * failure, silently drop this packet.
5617                  */
5618                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5619                                                 &start, base_flags, mss))
5620                         goto out_unlock;
5621
5622                 entry = start;
5623         }
5624
5625         /* Packets are ready, update Tx producer idx local and on card. */
5626         tw32_tx_mbox(tnapi->prodmbox, entry);
5627
5628         tnapi->tx_prod = entry;
5629         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5630                 netif_tx_stop_queue(txq);
5631                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5632                         netif_tx_wake_queue(txq);
5633         }
5634
5635 out_unlock:
5636         mmiowb();
5637
5638         return NETDEV_TX_OK;
5639 }
5640
5641 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5642                                int new_mtu)
5643 {
5644         dev->mtu = new_mtu;
5645
5646         if (new_mtu > ETH_DATA_LEN) {
5647                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5648                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5649                         ethtool_op_set_tso(dev, 0);
5650                 }
5651                 else
5652                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5653         } else {
5654                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5655                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5656                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5657         }
5658 }
5659
5660 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5661 {
5662         struct tg3 *tp = netdev_priv(dev);
5663         int err;
5664
5665         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5666                 return -EINVAL;
5667
5668         if (!netif_running(dev)) {
5669                 /* We'll just catch it later when the
5670                  * device is up'd.
5671                  */
5672                 tg3_set_mtu(dev, tp, new_mtu);
5673                 return 0;
5674         }
5675
5676         tg3_phy_stop(tp);
5677
5678         tg3_netif_stop(tp);
5679
5680         tg3_full_lock(tp, 1);
5681
5682         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5683
5684         tg3_set_mtu(dev, tp, new_mtu);
5685
5686         err = tg3_restart_hw(tp, 0);
5687
5688         if (!err)
5689                 tg3_netif_start(tp);
5690
5691         tg3_full_unlock(tp);
5692
5693         if (!err)
5694                 tg3_phy_start(tp);
5695
5696         return err;
5697 }
5698
5699 static void tg3_rx_prodring_free(struct tg3 *tp,
5700                                  struct tg3_rx_prodring_set *tpr)
5701 {
5702         int i;
5703         struct ring_info *rxp;
5704
5705         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5706                 rxp = &tpr->rx_std_buffers[i];
5707
5708                 if (rxp->skb == NULL)
5709                         continue;
5710
5711                 pci_unmap_single(tp->pdev,
5712                                  pci_unmap_addr(rxp, mapping),
5713                                  tp->rx_pkt_map_sz,
5714                                  PCI_DMA_FROMDEVICE);
5715                 dev_kfree_skb_any(rxp->skb);
5716                 rxp->skb = NULL;
5717         }
5718
5719         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5720                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5721                         rxp = &tpr->rx_jmb_buffers[i];
5722
5723                         if (rxp->skb == NULL)
5724                                 continue;
5725
5726                         pci_unmap_single(tp->pdev,
5727                                          pci_unmap_addr(rxp, mapping),
5728                                          TG3_RX_JMB_MAP_SZ,
5729                                          PCI_DMA_FROMDEVICE);
5730                         dev_kfree_skb_any(rxp->skb);
5731                         rxp->skb = NULL;
5732                 }
5733         }
5734 }
5735
5736 /* Initialize tx/rx rings for packet processing.
5737  *
5738  * The chip has been shut down and the driver detached from
5739  * the networking, so no interrupts or new tx packets will
5740  * end up in the driver.  tp->{tx,}lock are held and thus
5741  * we may not sleep.
5742  */
5743 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5744                                  struct tg3_rx_prodring_set *tpr)
5745 {
5746         u32 i, rx_pkt_dma_sz;
5747         struct tg3_napi *tnapi = &tp->napi[0];
5748
5749         /* Zero out all descriptors. */
5750         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5751
5752         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5753         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5754             tp->dev->mtu > ETH_DATA_LEN)
5755                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5756         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5757
5758         /* Initialize invariants of the rings, we only set this
5759          * stuff once.  This works because the card does not
5760          * write into the rx buffer posting rings.
5761          */
5762         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5763                 struct tg3_rx_buffer_desc *rxd;
5764
5765                 rxd = &tpr->rx_std[i];
5766                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5767                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5768                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5769                                (i << RXD_OPAQUE_INDEX_SHIFT));
5770         }
5771
5772         /* Now allocate fresh SKBs for each rx ring. */
5773         for (i = 0; i < tp->rx_pending; i++) {
5774                 if (tg3_alloc_rx_skb(tnapi, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
5775                         printk(KERN_WARNING PFX
5776                                "%s: Using a smaller RX standard ring, "
5777                                "only %d out of %d buffers were allocated "
5778                                "successfully.\n",
5779                                tp->dev->name, i, tp->rx_pending);
5780                         if (i == 0)
5781                                 goto initfail;
5782                         tp->rx_pending = i;
5783                         break;
5784                 }
5785         }
5786
5787         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5788                 goto done;
5789
5790         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5791
5792         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5793                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5794                         struct tg3_rx_buffer_desc *rxd;
5795
5796                         rxd = &tpr->rx_jmb[i].std;
5797                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5798                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5799                                 RXD_FLAG_JUMBO;
5800                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5801                                (i << RXD_OPAQUE_INDEX_SHIFT));
5802                 }
5803
5804                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5805                         if (tg3_alloc_rx_skb(tnapi, tpr, RXD_OPAQUE_RING_JUMBO,
5806                                              i) < 0) {
5807                                 printk(KERN_WARNING PFX
5808                                        "%s: Using a smaller RX jumbo ring, "
5809                                        "only %d out of %d buffers were "
5810                                        "allocated successfully.\n",
5811                                        tp->dev->name, i, tp->rx_jumbo_pending);
5812                                 if (i == 0)
5813                                         goto initfail;
5814                                 tp->rx_jumbo_pending = i;
5815                                 break;
5816                         }
5817                 }
5818         }
5819
5820 done:
5821         return 0;
5822
5823 initfail:
5824         tg3_rx_prodring_free(tp, tpr);
5825         return -ENOMEM;
5826 }
5827
5828 static void tg3_rx_prodring_fini(struct tg3 *tp,
5829                                  struct tg3_rx_prodring_set *tpr)
5830 {
5831         kfree(tpr->rx_std_buffers);
5832         tpr->rx_std_buffers = NULL;
5833         kfree(tpr->rx_jmb_buffers);
5834         tpr->rx_jmb_buffers = NULL;
5835         if (tpr->rx_std) {
5836                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5837                                     tpr->rx_std, tpr->rx_std_mapping);
5838                 tpr->rx_std = NULL;
5839         }
5840         if (tpr->rx_jmb) {
5841                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5842                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5843                 tpr->rx_jmb = NULL;
5844         }
5845 }
5846
5847 static int tg3_rx_prodring_init(struct tg3 *tp,
5848                                 struct tg3_rx_prodring_set *tpr)
5849 {
5850         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5851                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5852         if (!tpr->rx_std_buffers)
5853                 return -ENOMEM;
5854
5855         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5856                                            &tpr->rx_std_mapping);
5857         if (!tpr->rx_std)
5858                 goto err_out;
5859
5860         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5861                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5862                                               TG3_RX_JUMBO_RING_SIZE,
5863                                               GFP_KERNEL);
5864                 if (!tpr->rx_jmb_buffers)
5865                         goto err_out;
5866
5867                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5868                                                    TG3_RX_JUMBO_RING_BYTES,
5869                                                    &tpr->rx_jmb_mapping);
5870                 if (!tpr->rx_jmb)
5871                         goto err_out;
5872         }
5873
5874         return 0;
5875
5876 err_out:
5877         tg3_rx_prodring_fini(tp, tpr);
5878         return -ENOMEM;
5879 }
5880
5881 /* Free up pending packets in all rx/tx rings.
5882  *
5883  * The chip has been shut down and the driver detached from
5884  * the networking, so no interrupts or new tx packets will
5885  * end up in the driver.  tp->{tx,}lock is not held and we are not
5886  * in an interrupt context and thus may sleep.
5887  */
5888 static void tg3_free_rings(struct tg3 *tp)
5889 {
5890         int i, j;
5891
5892         for (j = 0; j < tp->irq_cnt; j++) {
5893                 struct tg3_napi *tnapi = &tp->napi[j];
5894
5895                 if (!tnapi->tx_buffers)
5896                         continue;
5897
5898                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5899                         struct tx_ring_info *txp;
5900                         struct sk_buff *skb;
5901
5902                         txp = &tnapi->tx_buffers[i];
5903                         skb = txp->skb;
5904
5905                         if (skb == NULL) {
5906                                 i++;
5907                                 continue;
5908                         }
5909
5910                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5911
5912                         txp->skb = NULL;
5913
5914                         i += skb_shinfo(skb)->nr_frags + 1;
5915
5916                         dev_kfree_skb_any(skb);
5917                 }
5918         }
5919
5920         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5921 }
5922
5923 /* Initialize tx/rx rings for packet processing.
5924  *
5925  * The chip has been shut down and the driver detached from
5926  * the networking, so no interrupts or new tx packets will
5927  * end up in the driver.  tp->{tx,}lock are held and thus
5928  * we may not sleep.
5929  */
5930 static int tg3_init_rings(struct tg3 *tp)
5931 {
5932         int i;
5933
5934         /* Free up all the SKBs. */
5935         tg3_free_rings(tp);
5936
5937         for (i = 0; i < tp->irq_cnt; i++) {
5938                 struct tg3_napi *tnapi = &tp->napi[i];
5939
5940                 tnapi->last_tag = 0;
5941                 tnapi->last_irq_tag = 0;
5942                 tnapi->hw_status->status = 0;
5943                 tnapi->hw_status->status_tag = 0;
5944                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5945
5946                 tnapi->tx_prod = 0;
5947                 tnapi->tx_cons = 0;
5948                 if (tnapi->tx_ring)
5949                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5950
5951                 tnapi->rx_rcb_ptr = 0;
5952                 if (tnapi->rx_rcb)
5953                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5954         }
5955
5956         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5957 }
5958
5959 /*
5960  * Must not be invoked with interrupt sources disabled and
5961  * the hardware shutdown down.
5962  */
5963 static void tg3_free_consistent(struct tg3 *tp)
5964 {
5965         int i;
5966
5967         for (i = 0; i < tp->irq_cnt; i++) {
5968                 struct tg3_napi *tnapi = &tp->napi[i];
5969
5970                 if (tnapi->tx_ring) {
5971                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5972                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5973                         tnapi->tx_ring = NULL;
5974                 }
5975
5976                 kfree(tnapi->tx_buffers);
5977                 tnapi->tx_buffers = NULL;
5978
5979                 if (tnapi->rx_rcb) {
5980                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5981                                             tnapi->rx_rcb,
5982                                             tnapi->rx_rcb_mapping);
5983                         tnapi->rx_rcb = NULL;
5984                 }
5985
5986                 if (tnapi->hw_status) {
5987                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5988                                             tnapi->hw_status,
5989                                             tnapi->status_mapping);
5990                         tnapi->hw_status = NULL;
5991                 }
5992         }
5993
5994         if (tp->hw_stats) {
5995                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5996                                     tp->hw_stats, tp->stats_mapping);
5997                 tp->hw_stats = NULL;
5998         }
5999
6000         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
6001 }
6002
6003 /*
6004  * Must not be invoked with interrupt sources disabled and
6005  * the hardware shutdown down.  Can sleep.
6006  */
6007 static int tg3_alloc_consistent(struct tg3 *tp)
6008 {
6009         int i;
6010
6011         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
6012                 return -ENOMEM;
6013
6014         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6015                                             sizeof(struct tg3_hw_stats),
6016                                             &tp->stats_mapping);
6017         if (!tp->hw_stats)
6018                 goto err_out;
6019
6020         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6021
6022         for (i = 0; i < tp->irq_cnt; i++) {
6023                 struct tg3_napi *tnapi = &tp->napi[i];
6024                 struct tg3_hw_status *sblk;
6025
6026                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6027                                                         TG3_HW_STATUS_SIZE,
6028                                                         &tnapi->status_mapping);
6029                 if (!tnapi->hw_status)
6030                         goto err_out;
6031
6032                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6033                 sblk = tnapi->hw_status;
6034
6035                 /*
6036                  * When RSS is enabled, the status block format changes
6037                  * slightly.  The "rx_jumbo_consumer", "reserved",
6038                  * and "rx_mini_consumer" members get mapped to the
6039                  * other three rx return ring producer indexes.
6040                  */
6041                 switch (i) {
6042                 default:
6043                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6044                         break;
6045                 case 2:
6046                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6047                         break;
6048                 case 3:
6049                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6050                         break;
6051                 case 4:
6052                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6053                         break;
6054                 }
6055
6056                 /*
6057                  * If multivector RSS is enabled, vector 0 does not handle
6058                  * rx or tx interrupts.  Don't allocate any resources for it.
6059                  */
6060                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6061                         continue;
6062
6063                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6064                                                      TG3_RX_RCB_RING_BYTES(tp),
6065                                                      &tnapi->rx_rcb_mapping);
6066                 if (!tnapi->rx_rcb)
6067                         goto err_out;
6068
6069                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6070
6071                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6072                                             TG3_TX_RING_SIZE, GFP_KERNEL);
6073                 if (!tnapi->tx_buffers)
6074                         goto err_out;
6075
6076                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6077                                                       TG3_TX_RING_BYTES,
6078                                                       &tnapi->tx_desc_mapping);
6079                 if (!tnapi->tx_ring)
6080                         goto err_out;
6081         }
6082
6083         return 0;
6084
6085 err_out:
6086         tg3_free_consistent(tp);
6087         return -ENOMEM;
6088 }
6089
6090 #define MAX_WAIT_CNT 1000
6091
6092 /* To stop a block, clear the enable bit and poll till it
6093  * clears.  tp->lock is held.
6094  */
6095 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6096 {
6097         unsigned int i;
6098         u32 val;
6099
6100         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6101                 switch (ofs) {
6102                 case RCVLSC_MODE:
6103                 case DMAC_MODE:
6104                 case MBFREE_MODE:
6105                 case BUFMGR_MODE:
6106                 case MEMARB_MODE:
6107                         /* We can't enable/disable these bits of the
6108                          * 5705/5750, just say success.
6109                          */
6110                         return 0;
6111
6112                 default:
6113                         break;
6114                 }
6115         }
6116
6117         val = tr32(ofs);
6118         val &= ~enable_bit;
6119         tw32_f(ofs, val);
6120
6121         for (i = 0; i < MAX_WAIT_CNT; i++) {
6122                 udelay(100);
6123                 val = tr32(ofs);
6124                 if ((val & enable_bit) == 0)
6125                         break;
6126         }
6127
6128         if (i == MAX_WAIT_CNT && !silent) {
6129                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6130                        "ofs=%lx enable_bit=%x\n",
6131                        ofs, enable_bit);
6132                 return -ENODEV;
6133         }
6134
6135         return 0;
6136 }
6137
6138 /* tp->lock is held. */
6139 static int tg3_abort_hw(struct tg3 *tp, int silent)
6140 {
6141         int i, err;
6142
6143         tg3_disable_ints(tp);
6144
6145         tp->rx_mode &= ~RX_MODE_ENABLE;
6146         tw32_f(MAC_RX_MODE, tp->rx_mode);
6147         udelay(10);
6148
6149         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6150         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6151         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6152         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6153         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6154         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6155
6156         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6157         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6158         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6159         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6160         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6161         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6162         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6163
6164         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6165         tw32_f(MAC_MODE, tp->mac_mode);
6166         udelay(40);
6167
6168         tp->tx_mode &= ~TX_MODE_ENABLE;
6169         tw32_f(MAC_TX_MODE, tp->tx_mode);
6170
6171         for (i = 0; i < MAX_WAIT_CNT; i++) {
6172                 udelay(100);
6173                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6174                         break;
6175         }
6176         if (i >= MAX_WAIT_CNT) {
6177                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6178                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6179                        tp->dev->name, tr32(MAC_TX_MODE));
6180                 err |= -ENODEV;
6181         }
6182
6183         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6184         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6185         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6186
6187         tw32(FTQ_RESET, 0xffffffff);
6188         tw32(FTQ_RESET, 0x00000000);
6189
6190         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6191         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6192
6193         for (i = 0; i < tp->irq_cnt; i++) {
6194                 struct tg3_napi *tnapi = &tp->napi[i];
6195                 if (tnapi->hw_status)
6196                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6197         }
6198         if (tp->hw_stats)
6199                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6200
6201         return err;
6202 }
6203
6204 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6205 {
6206         int i;
6207         u32 apedata;
6208
6209         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6210         if (apedata != APE_SEG_SIG_MAGIC)
6211                 return;
6212
6213         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6214         if (!(apedata & APE_FW_STATUS_READY))
6215                 return;
6216
6217         /* Wait for up to 1 millisecond for APE to service previous event. */
6218         for (i = 0; i < 10; i++) {
6219                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6220                         return;
6221
6222                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6223
6224                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6225                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6226                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6227
6228                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6229
6230                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6231                         break;
6232
6233                 udelay(100);
6234         }
6235
6236         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6237                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6238 }
6239
6240 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6241 {
6242         u32 event;
6243         u32 apedata;
6244
6245         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6246                 return;
6247
6248         switch (kind) {
6249                 case RESET_KIND_INIT:
6250                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6251                                         APE_HOST_SEG_SIG_MAGIC);
6252                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6253                                         APE_HOST_SEG_LEN_MAGIC);
6254                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6255                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6256                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6257                                         APE_HOST_DRIVER_ID_MAGIC);
6258                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6259                                         APE_HOST_BEHAV_NO_PHYLOCK);
6260
6261                         event = APE_EVENT_STATUS_STATE_START;
6262                         break;
6263                 case RESET_KIND_SHUTDOWN:
6264                         /* With the interface we are currently using,
6265                          * APE does not track driver state.  Wiping
6266                          * out the HOST SEGMENT SIGNATURE forces
6267                          * the APE to assume OS absent status.
6268                          */
6269                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6270
6271                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6272                         break;
6273                 case RESET_KIND_SUSPEND:
6274                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6275                         break;
6276                 default:
6277                         return;
6278         }
6279
6280         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6281
6282         tg3_ape_send_event(tp, event);
6283 }
6284
6285 /* tp->lock is held. */
6286 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6287 {
6288         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6289                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6290
6291         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6292                 switch (kind) {
6293                 case RESET_KIND_INIT:
6294                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6295                                       DRV_STATE_START);
6296                         break;
6297
6298                 case RESET_KIND_SHUTDOWN:
6299                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6300                                       DRV_STATE_UNLOAD);
6301                         break;
6302
6303                 case RESET_KIND_SUSPEND:
6304                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6305                                       DRV_STATE_SUSPEND);
6306                         break;
6307
6308                 default:
6309                         break;
6310                 }
6311         }
6312
6313         if (kind == RESET_KIND_INIT ||
6314             kind == RESET_KIND_SUSPEND)
6315                 tg3_ape_driver_state_change(tp, kind);
6316 }
6317
6318 /* tp->lock is held. */
6319 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6320 {
6321         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6322                 switch (kind) {
6323                 case RESET_KIND_INIT:
6324                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6325                                       DRV_STATE_START_DONE);
6326                         break;
6327
6328                 case RESET_KIND_SHUTDOWN:
6329                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6330                                       DRV_STATE_UNLOAD_DONE);
6331                         break;
6332
6333                 default:
6334                         break;
6335                 }
6336         }
6337
6338         if (kind == RESET_KIND_SHUTDOWN)
6339                 tg3_ape_driver_state_change(tp, kind);
6340 }
6341
6342 /* tp->lock is held. */
6343 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6344 {
6345         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6346                 switch (kind) {
6347                 case RESET_KIND_INIT:
6348                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6349                                       DRV_STATE_START);
6350                         break;
6351
6352                 case RESET_KIND_SHUTDOWN:
6353                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6354                                       DRV_STATE_UNLOAD);
6355                         break;
6356
6357                 case RESET_KIND_SUSPEND:
6358                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6359                                       DRV_STATE_SUSPEND);
6360                         break;
6361
6362                 default:
6363                         break;
6364                 }
6365         }
6366 }
6367
6368 static int tg3_poll_fw(struct tg3 *tp)
6369 {
6370         int i;
6371         u32 val;
6372
6373         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6374                 /* Wait up to 20ms for init done. */
6375                 for (i = 0; i < 200; i++) {
6376                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6377                                 return 0;
6378                         udelay(100);
6379                 }
6380                 return -ENODEV;
6381         }
6382
6383         /* Wait for firmware initialization to complete. */
6384         for (i = 0; i < 100000; i++) {
6385                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6386                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6387                         break;
6388                 udelay(10);
6389         }
6390
6391         /* Chip might not be fitted with firmware.  Some Sun onboard
6392          * parts are configured like that.  So don't signal the timeout
6393          * of the above loop as an error, but do report the lack of
6394          * running firmware once.
6395          */
6396         if (i >= 100000 &&
6397             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6398                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6399
6400                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6401                        tp->dev->name);
6402         }
6403
6404         return 0;
6405 }
6406
6407 /* Save PCI command register before chip reset */
6408 static void tg3_save_pci_state(struct tg3 *tp)
6409 {
6410         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6411 }
6412
6413 /* Restore PCI state after chip reset */
6414 static void tg3_restore_pci_state(struct tg3 *tp)
6415 {
6416         u32 val;
6417
6418         /* Re-enable indirect register accesses. */
6419         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6420                                tp->misc_host_ctrl);
6421
6422         /* Set MAX PCI retry to zero. */
6423         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6424         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6425             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6426                 val |= PCISTATE_RETRY_SAME_DMA;
6427         /* Allow reads and writes to the APE register and memory space. */
6428         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6429                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6430                        PCISTATE_ALLOW_APE_SHMEM_WR;
6431         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6432
6433         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6434
6435         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6436                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6437                         pcie_set_readrq(tp->pdev, 4096);
6438                 else {
6439                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6440                                               tp->pci_cacheline_sz);
6441                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6442                                               tp->pci_lat_timer);
6443                 }
6444         }
6445
6446         /* Make sure PCI-X relaxed ordering bit is clear. */
6447         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6448                 u16 pcix_cmd;
6449
6450                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6451                                      &pcix_cmd);
6452                 pcix_cmd &= ~PCI_X_CMD_ERO;
6453                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6454                                       pcix_cmd);
6455         }
6456
6457         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6458
6459                 /* Chip reset on 5780 will reset MSI enable bit,
6460                  * so need to restore it.
6461                  */
6462                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6463                         u16 ctrl;
6464
6465                         pci_read_config_word(tp->pdev,
6466                                              tp->msi_cap + PCI_MSI_FLAGS,
6467                                              &ctrl);
6468                         pci_write_config_word(tp->pdev,
6469                                               tp->msi_cap + PCI_MSI_FLAGS,
6470                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6471                         val = tr32(MSGINT_MODE);
6472                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6473                 }
6474         }
6475 }
6476
6477 static void tg3_stop_fw(struct tg3 *);
6478
6479 /* tp->lock is held. */
6480 static int tg3_chip_reset(struct tg3 *tp)
6481 {
6482         u32 val;
6483         void (*write_op)(struct tg3 *, u32, u32);
6484         int i, err;
6485
6486         tg3_nvram_lock(tp);
6487
6488         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6489
6490         /* No matching tg3_nvram_unlock() after this because
6491          * chip reset below will undo the nvram lock.
6492          */
6493         tp->nvram_lock_cnt = 0;
6494
6495         /* GRC_MISC_CFG core clock reset will clear the memory
6496          * enable bit in PCI register 4 and the MSI enable bit
6497          * on some chips, so we save relevant registers here.
6498          */
6499         tg3_save_pci_state(tp);
6500
6501         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6502             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6503                 tw32(GRC_FASTBOOT_PC, 0);
6504
6505         /*
6506          * We must avoid the readl() that normally takes place.
6507          * It locks machines, causes machine checks, and other
6508          * fun things.  So, temporarily disable the 5701
6509          * hardware workaround, while we do the reset.
6510          */
6511         write_op = tp->write32;
6512         if (write_op == tg3_write_flush_reg32)
6513                 tp->write32 = tg3_write32;
6514
6515         /* Prevent the irq handler from reading or writing PCI registers
6516          * during chip reset when the memory enable bit in the PCI command
6517          * register may be cleared.  The chip does not generate interrupt
6518          * at this time, but the irq handler may still be called due to irq
6519          * sharing or irqpoll.
6520          */
6521         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6522         for (i = 0; i < tp->irq_cnt; i++) {
6523                 struct tg3_napi *tnapi = &tp->napi[i];
6524                 if (tnapi->hw_status) {
6525                         tnapi->hw_status->status = 0;
6526                         tnapi->hw_status->status_tag = 0;
6527                 }
6528                 tnapi->last_tag = 0;
6529                 tnapi->last_irq_tag = 0;
6530         }
6531         smp_mb();
6532
6533         for (i = 0; i < tp->irq_cnt; i++)
6534                 synchronize_irq(tp->napi[i].irq_vec);
6535
6536         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6537                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6538                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6539         }
6540
6541         /* do the reset */
6542         val = GRC_MISC_CFG_CORECLK_RESET;
6543
6544         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6545                 if (tr32(0x7e2c) == 0x60) {
6546                         tw32(0x7e2c, 0x20);
6547                 }
6548                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6549                         tw32(GRC_MISC_CFG, (1 << 29));
6550                         val |= (1 << 29);
6551                 }
6552         }
6553
6554         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6555                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6556                 tw32(GRC_VCPU_EXT_CTRL,
6557                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6558         }
6559
6560         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6561                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6562         tw32(GRC_MISC_CFG, val);
6563
6564         /* restore 5701 hardware bug workaround write method */
6565         tp->write32 = write_op;
6566
6567         /* Unfortunately, we have to delay before the PCI read back.
6568          * Some 575X chips even will not respond to a PCI cfg access
6569          * when the reset command is given to the chip.
6570          *
6571          * How do these hardware designers expect things to work
6572          * properly if the PCI write is posted for a long period
6573          * of time?  It is always necessary to have some method by
6574          * which a register read back can occur to push the write
6575          * out which does the reset.
6576          *
6577          * For most tg3 variants the trick below was working.
6578          * Ho hum...
6579          */
6580         udelay(120);
6581
6582         /* Flush PCI posted writes.  The normal MMIO registers
6583          * are inaccessible at this time so this is the only
6584          * way to make this reliably (actually, this is no longer
6585          * the case, see above).  I tried to use indirect
6586          * register read/write but this upset some 5701 variants.
6587          */
6588         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6589
6590         udelay(120);
6591
6592         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6593                 u16 val16;
6594
6595                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6596                         int i;
6597                         u32 cfg_val;
6598
6599                         /* Wait for link training to complete.  */
6600                         for (i = 0; i < 5000; i++)
6601                                 udelay(100);
6602
6603                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6604                         pci_write_config_dword(tp->pdev, 0xc4,
6605                                                cfg_val | (1 << 15));
6606                 }
6607
6608                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6609                 pci_read_config_word(tp->pdev,
6610                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6611                                      &val16);
6612                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6613                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6614                 /*
6615                  * Older PCIe devices only support the 128 byte
6616                  * MPS setting.  Enforce the restriction.
6617                  */
6618                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6619                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6620                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6621                 pci_write_config_word(tp->pdev,
6622                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6623                                       val16);
6624
6625                 pcie_set_readrq(tp->pdev, 4096);
6626
6627                 /* Clear error status */
6628                 pci_write_config_word(tp->pdev,
6629                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6630                                       PCI_EXP_DEVSTA_CED |
6631                                       PCI_EXP_DEVSTA_NFED |
6632                                       PCI_EXP_DEVSTA_FED |
6633                                       PCI_EXP_DEVSTA_URD);
6634         }
6635
6636         tg3_restore_pci_state(tp);
6637
6638         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6639
6640         val = 0;
6641         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6642                 val = tr32(MEMARB_MODE);
6643         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6644
6645         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6646                 tg3_stop_fw(tp);
6647                 tw32(0x5000, 0x400);
6648         }
6649
6650         tw32(GRC_MODE, tp->grc_mode);
6651
6652         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6653                 val = tr32(0xc4);
6654
6655                 tw32(0xc4, val | (1 << 15));
6656         }
6657
6658         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6659             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6660                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6661                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6662                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6663                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6664         }
6665
6666         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6667                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6668                 tw32_f(MAC_MODE, tp->mac_mode);
6669         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6670                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6671                 tw32_f(MAC_MODE, tp->mac_mode);
6672         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6673                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6674                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6675                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6676                 tw32_f(MAC_MODE, tp->mac_mode);
6677         } else
6678                 tw32_f(MAC_MODE, 0);
6679         udelay(40);
6680
6681         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6682
6683         err = tg3_poll_fw(tp);
6684         if (err)
6685                 return err;
6686
6687         tg3_mdio_start(tp);
6688
6689         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6690                 u8 phy_addr;
6691
6692                 phy_addr = tp->phy_addr;
6693                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6694
6695                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6696                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6697                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6698                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6699                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6700                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6701                 udelay(10);
6702
6703                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6704                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6705                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6706                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6707                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6708                 udelay(10);
6709
6710                 tp->phy_addr = phy_addr;
6711         }
6712
6713         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6714             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6715             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6716             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6717                 val = tr32(0x7c00);
6718
6719                 tw32(0x7c00, val | (1 << 25));
6720         }
6721
6722         /* Reprobe ASF enable state.  */
6723         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6724         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6725         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6726         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6727                 u32 nic_cfg;
6728
6729                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6730                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6731                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6732                         tp->last_event_jiffies = jiffies;
6733                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6734                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6735                 }
6736         }
6737
6738         return 0;
6739 }
6740
6741 /* tp->lock is held. */
6742 static void tg3_stop_fw(struct tg3 *tp)
6743 {
6744         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6745            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6746                 /* Wait for RX cpu to ACK the previous event. */
6747                 tg3_wait_for_event_ack(tp);
6748
6749                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6750
6751                 tg3_generate_fw_event(tp);
6752
6753                 /* Wait for RX cpu to ACK this event. */
6754                 tg3_wait_for_event_ack(tp);
6755         }
6756 }
6757
6758 /* tp->lock is held. */
6759 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6760 {
6761         int err;
6762
6763         tg3_stop_fw(tp);
6764
6765         tg3_write_sig_pre_reset(tp, kind);
6766
6767         tg3_abort_hw(tp, silent);
6768         err = tg3_chip_reset(tp);
6769
6770         __tg3_set_mac_addr(tp, 0);
6771
6772         tg3_write_sig_legacy(tp, kind);
6773         tg3_write_sig_post_reset(tp, kind);
6774
6775         if (err)
6776                 return err;
6777
6778         return 0;
6779 }
6780
6781 #define RX_CPU_SCRATCH_BASE     0x30000
6782 #define RX_CPU_SCRATCH_SIZE     0x04000
6783 #define TX_CPU_SCRATCH_BASE     0x34000
6784 #define TX_CPU_SCRATCH_SIZE     0x04000
6785
6786 /* tp->lock is held. */
6787 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6788 {
6789         int i;
6790
6791         BUG_ON(offset == TX_CPU_BASE &&
6792             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6793
6794         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6795                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6796
6797                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6798                 return 0;
6799         }
6800         if (offset == RX_CPU_BASE) {
6801                 for (i = 0; i < 10000; i++) {
6802                         tw32(offset + CPU_STATE, 0xffffffff);
6803                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6804                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6805                                 break;
6806                 }
6807
6808                 tw32(offset + CPU_STATE, 0xffffffff);
6809                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6810                 udelay(10);
6811         } else {
6812                 for (i = 0; i < 10000; i++) {
6813                         tw32(offset + CPU_STATE, 0xffffffff);
6814                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6815                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6816                                 break;
6817                 }
6818         }
6819
6820         if (i >= 10000) {
6821                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6822                        "and %s CPU\n",
6823                        tp->dev->name,
6824                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6825                 return -ENODEV;
6826         }
6827
6828         /* Clear firmware's nvram arbitration. */
6829         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6830                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6831         return 0;
6832 }
6833
6834 struct fw_info {
6835         unsigned int fw_base;
6836         unsigned int fw_len;
6837         const __be32 *fw_data;
6838 };
6839
6840 /* tp->lock is held. */
6841 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6842                                  int cpu_scratch_size, struct fw_info *info)
6843 {
6844         int err, lock_err, i;
6845         void (*write_op)(struct tg3 *, u32, u32);
6846
6847         if (cpu_base == TX_CPU_BASE &&
6848             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6849                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6850                        "TX cpu firmware on %s which is 5705.\n",
6851                        tp->dev->name);
6852                 return -EINVAL;
6853         }
6854
6855         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6856                 write_op = tg3_write_mem;
6857         else
6858                 write_op = tg3_write_indirect_reg32;
6859
6860         /* It is possible that bootcode is still loading at this point.
6861          * Get the nvram lock first before halting the cpu.
6862          */
6863         lock_err = tg3_nvram_lock(tp);
6864         err = tg3_halt_cpu(tp, cpu_base);
6865         if (!lock_err)
6866                 tg3_nvram_unlock(tp);
6867         if (err)
6868                 goto out;
6869
6870         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6871                 write_op(tp, cpu_scratch_base + i, 0);
6872         tw32(cpu_base + CPU_STATE, 0xffffffff);
6873         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6874         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6875                 write_op(tp, (cpu_scratch_base +
6876                               (info->fw_base & 0xffff) +
6877                               (i * sizeof(u32))),
6878                               be32_to_cpu(info->fw_data[i]));
6879
6880         err = 0;
6881
6882 out:
6883         return err;
6884 }
6885
6886 /* tp->lock is held. */
6887 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6888 {
6889         struct fw_info info;
6890         const __be32 *fw_data;
6891         int err, i;
6892
6893         fw_data = (void *)tp->fw->data;
6894
6895         /* Firmware blob starts with version numbers, followed by
6896            start address and length. We are setting complete length.
6897            length = end_address_of_bss - start_address_of_text.
6898            Remainder is the blob to be loaded contiguously
6899            from start address. */
6900
6901         info.fw_base = be32_to_cpu(fw_data[1]);
6902         info.fw_len = tp->fw->size - 12;
6903         info.fw_data = &fw_data[3];
6904
6905         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6906                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6907                                     &info);
6908         if (err)
6909                 return err;
6910
6911         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6912                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6913                                     &info);
6914         if (err)
6915                 return err;
6916
6917         /* Now startup only the RX cpu. */
6918         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6919         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6920
6921         for (i = 0; i < 5; i++) {
6922                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6923                         break;
6924                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6925                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6926                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6927                 udelay(1000);
6928         }
6929         if (i >= 5) {
6930                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6931                        "to set RX CPU PC, is %08x should be %08x\n",
6932                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6933                        info.fw_base);
6934                 return -ENODEV;
6935         }
6936         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6937         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6938
6939         return 0;
6940 }
6941
6942 /* 5705 needs a special version of the TSO firmware.  */
6943
6944 /* tp->lock is held. */
6945 static int tg3_load_tso_firmware(struct tg3 *tp)
6946 {
6947         struct fw_info info;
6948         const __be32 *fw_data;
6949         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6950         int err, i;
6951
6952         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6953                 return 0;
6954
6955         fw_data = (void *)tp->fw->data;
6956
6957         /* Firmware blob starts with version numbers, followed by
6958            start address and length. We are setting complete length.
6959            length = end_address_of_bss - start_address_of_text.
6960            Remainder is the blob to be loaded contiguously
6961            from start address. */
6962
6963         info.fw_base = be32_to_cpu(fw_data[1]);
6964         cpu_scratch_size = tp->fw_len;
6965         info.fw_len = tp->fw->size - 12;
6966         info.fw_data = &fw_data[3];
6967
6968         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6969                 cpu_base = RX_CPU_BASE;
6970                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6971         } else {
6972                 cpu_base = TX_CPU_BASE;
6973                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6974                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6975         }
6976
6977         err = tg3_load_firmware_cpu(tp, cpu_base,
6978                                     cpu_scratch_base, cpu_scratch_size,
6979                                     &info);
6980         if (err)
6981                 return err;
6982
6983         /* Now startup the cpu. */
6984         tw32(cpu_base + CPU_STATE, 0xffffffff);
6985         tw32_f(cpu_base + CPU_PC, info.fw_base);
6986
6987         for (i = 0; i < 5; i++) {
6988                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6989                         break;
6990                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6991                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6992                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6993                 udelay(1000);
6994         }
6995         if (i >= 5) {
6996                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6997                        "to set CPU PC, is %08x should be %08x\n",
6998                        tp->dev->name, tr32(cpu_base + CPU_PC),
6999                        info.fw_base);
7000                 return -ENODEV;
7001         }
7002         tw32(cpu_base + CPU_STATE, 0xffffffff);
7003         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7004         return 0;
7005 }
7006
7007
7008 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7009 {
7010         struct tg3 *tp = netdev_priv(dev);
7011         struct sockaddr *addr = p;
7012         int err = 0, skip_mac_1 = 0;
7013
7014         if (!is_valid_ether_addr(addr->sa_data))
7015                 return -EINVAL;
7016
7017         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7018
7019         if (!netif_running(dev))
7020                 return 0;
7021
7022         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7023                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7024
7025                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7026                 addr0_low = tr32(MAC_ADDR_0_LOW);
7027                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7028                 addr1_low = tr32(MAC_ADDR_1_LOW);
7029
7030                 /* Skip MAC addr 1 if ASF is using it. */
7031                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7032                     !(addr1_high == 0 && addr1_low == 0))
7033                         skip_mac_1 = 1;
7034         }
7035         spin_lock_bh(&tp->lock);
7036         __tg3_set_mac_addr(tp, skip_mac_1);
7037         spin_unlock_bh(&tp->lock);
7038
7039         return err;
7040 }
7041
7042 /* tp->lock is held. */
7043 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7044                            dma_addr_t mapping, u32 maxlen_flags,
7045                            u32 nic_addr)
7046 {
7047         tg3_write_mem(tp,
7048                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7049                       ((u64) mapping >> 32));
7050         tg3_write_mem(tp,
7051                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7052                       ((u64) mapping & 0xffffffff));
7053         tg3_write_mem(tp,
7054                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7055                        maxlen_flags);
7056
7057         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7058                 tg3_write_mem(tp,
7059                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7060                               nic_addr);
7061 }
7062
7063 static void __tg3_set_rx_mode(struct net_device *);
7064 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7065 {
7066         int i;
7067
7068         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7069                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7070                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7071                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7072
7073                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7074                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7075                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7076         } else {
7077                 tw32(HOSTCC_TXCOL_TICKS, 0);
7078                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7079                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7080
7081                 tw32(HOSTCC_RXCOL_TICKS, 0);
7082                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7083                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7084         }
7085
7086         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7087                 u32 val = ec->stats_block_coalesce_usecs;
7088
7089                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7090                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7091
7092                 if (!netif_carrier_ok(tp->dev))
7093                         val = 0;
7094
7095                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7096         }
7097
7098         for (i = 0; i < tp->irq_cnt - 1; i++) {
7099                 u32 reg;
7100
7101                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7102                 tw32(reg, ec->rx_coalesce_usecs);
7103                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7104                 tw32(reg, ec->tx_coalesce_usecs);
7105                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7106                 tw32(reg, ec->rx_max_coalesced_frames);
7107                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7108                 tw32(reg, ec->tx_max_coalesced_frames);
7109                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7110                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7111                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7112                 tw32(reg, ec->tx_max_coalesced_frames_irq);
7113         }
7114
7115         for (; i < tp->irq_max - 1; i++) {
7116                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7117                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7118                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7119                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7120                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7121                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7122         }
7123 }
7124
7125 /* tp->lock is held. */
7126 static void tg3_rings_reset(struct tg3 *tp)
7127 {
7128         int i;
7129         u32 stblk, txrcb, rxrcb, limit;
7130         struct tg3_napi *tnapi = &tp->napi[0];
7131
7132         /* Disable all transmit rings but the first. */
7133         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7134                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7135         else
7136                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7137
7138         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7139              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7140                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7141                               BDINFO_FLAGS_DISABLED);
7142
7143
7144         /* Disable all receive return rings but the first. */
7145         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7146                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7147         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7148                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7149         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7150                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7151         else
7152                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7153
7154         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7155              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7156                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7157                               BDINFO_FLAGS_DISABLED);
7158
7159         /* Disable interrupts */
7160         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7161
7162         /* Zero mailbox registers. */
7163         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7164                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7165                         tp->napi[i].tx_prod = 0;
7166                         tp->napi[i].tx_cons = 0;
7167                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7168                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7169                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7170                 }
7171         } else {
7172                 tp->napi[0].tx_prod = 0;
7173                 tp->napi[0].tx_cons = 0;
7174                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7175                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7176         }
7177
7178         /* Make sure the NIC-based send BD rings are disabled. */
7179         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7180                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7181                 for (i = 0; i < 16; i++)
7182                         tw32_tx_mbox(mbox + i * 8, 0);
7183         }
7184
7185         txrcb = NIC_SRAM_SEND_RCB;
7186         rxrcb = NIC_SRAM_RCV_RET_RCB;
7187
7188         /* Clear status block in ram. */
7189         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7190
7191         /* Set status block DMA address */
7192         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7193              ((u64) tnapi->status_mapping >> 32));
7194         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7195              ((u64) tnapi->status_mapping & 0xffffffff));
7196
7197         if (tnapi->tx_ring) {
7198                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7199                                (TG3_TX_RING_SIZE <<
7200                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7201                                NIC_SRAM_TX_BUFFER_DESC);
7202                 txrcb += TG3_BDINFO_SIZE;
7203         }
7204
7205         if (tnapi->rx_rcb) {
7206                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7207                                (TG3_RX_RCB_RING_SIZE(tp) <<
7208                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7209                 rxrcb += TG3_BDINFO_SIZE;
7210         }
7211
7212         stblk = HOSTCC_STATBLCK_RING1;
7213
7214         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7215                 u64 mapping = (u64)tnapi->status_mapping;
7216                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7217                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7218
7219                 /* Clear status block in ram. */
7220                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7221
7222                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7223                                (TG3_TX_RING_SIZE <<
7224                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7225                                NIC_SRAM_TX_BUFFER_DESC);
7226
7227                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7228                                (TG3_RX_RCB_RING_SIZE(tp) <<
7229                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7230
7231                 stblk += 8;
7232                 txrcb += TG3_BDINFO_SIZE;
7233                 rxrcb += TG3_BDINFO_SIZE;
7234         }
7235 }
7236
7237 /* tp->lock is held. */
7238 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7239 {
7240         u32 val, rdmac_mode;
7241         int i, err, limit;
7242         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7243
7244         tg3_disable_ints(tp);
7245
7246         tg3_stop_fw(tp);
7247
7248         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7249
7250         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7251                 tg3_abort_hw(tp, 1);
7252         }
7253
7254         if (reset_phy &&
7255             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7256                 tg3_phy_reset(tp);
7257
7258         err = tg3_chip_reset(tp);
7259         if (err)
7260                 return err;
7261
7262         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7263
7264         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7265                 val = tr32(TG3_CPMU_CTRL);
7266                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7267                 tw32(TG3_CPMU_CTRL, val);
7268
7269                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7270                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7271                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7272                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7273
7274                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7275                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7276                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7277                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7278
7279                 val = tr32(TG3_CPMU_HST_ACC);
7280                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7281                 val |= CPMU_HST_ACC_MACCLK_6_25;
7282                 tw32(TG3_CPMU_HST_ACC, val);
7283         }
7284
7285         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7286                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7287                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7288                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7289                 tw32(PCIE_PWR_MGMT_THRESH, val);
7290
7291                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7292                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7293
7294                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7295
7296                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7297                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7298         }
7299
7300         /* This works around an issue with Athlon chipsets on
7301          * B3 tigon3 silicon.  This bit has no effect on any
7302          * other revision.  But do not set this on PCI Express
7303          * chips and don't even touch the clocks if the CPMU is present.
7304          */
7305         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7306                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7307                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7308                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7309         }
7310
7311         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7312             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7313                 val = tr32(TG3PCI_PCISTATE);
7314                 val |= PCISTATE_RETRY_SAME_DMA;
7315                 tw32(TG3PCI_PCISTATE, val);
7316         }
7317
7318         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7319                 /* Allow reads and writes to the
7320                  * APE register and memory space.
7321                  */
7322                 val = tr32(TG3PCI_PCISTATE);
7323                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7324                        PCISTATE_ALLOW_APE_SHMEM_WR;
7325                 tw32(TG3PCI_PCISTATE, val);
7326         }
7327
7328         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7329                 /* Enable some hw fixes.  */
7330                 val = tr32(TG3PCI_MSI_DATA);
7331                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7332                 tw32(TG3PCI_MSI_DATA, val);
7333         }
7334
7335         /* Descriptor ring init may make accesses to the
7336          * NIC SRAM area to setup the TX descriptors, so we
7337          * can only do this after the hardware has been
7338          * successfully reset.
7339          */
7340         err = tg3_init_rings(tp);
7341         if (err)
7342                 return err;
7343
7344         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7345                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7346                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7347                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7348         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7349                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7350                 /* This value is determined during the probe time DMA
7351                  * engine test, tg3_test_dma.
7352                  */
7353                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7354         }
7355
7356         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7357                           GRC_MODE_4X_NIC_SEND_RINGS |
7358                           GRC_MODE_NO_TX_PHDR_CSUM |
7359                           GRC_MODE_NO_RX_PHDR_CSUM);
7360         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7361
7362         /* Pseudo-header checksum is done by hardware logic and not
7363          * the offload processers, so make the chip do the pseudo-
7364          * header checksums on receive.  For transmit it is more
7365          * convenient to do the pseudo-header checksum in software
7366          * as Linux does that on transmit for us in all cases.
7367          */
7368         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7369
7370         tw32(GRC_MODE,
7371              tp->grc_mode |
7372              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7373
7374         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7375         val = tr32(GRC_MISC_CFG);
7376         val &= ~0xff;
7377         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7378         tw32(GRC_MISC_CFG, val);
7379
7380         /* Initialize MBUF/DESC pool. */
7381         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7382                 /* Do nothing.  */
7383         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7384                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7385                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7386                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7387                 else
7388                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7389                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7390                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7391         }
7392         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7393                 int fw_len;
7394
7395                 fw_len = tp->fw_len;
7396                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7397                 tw32(BUFMGR_MB_POOL_ADDR,
7398                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7399                 tw32(BUFMGR_MB_POOL_SIZE,
7400                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7401         }
7402
7403         if (tp->dev->mtu <= ETH_DATA_LEN) {
7404                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7405                      tp->bufmgr_config.mbuf_read_dma_low_water);
7406                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7407                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7408                 tw32(BUFMGR_MB_HIGH_WATER,
7409                      tp->bufmgr_config.mbuf_high_water);
7410         } else {
7411                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7412                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7413                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7414                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7415                 tw32(BUFMGR_MB_HIGH_WATER,
7416                      tp->bufmgr_config.mbuf_high_water_jumbo);
7417         }
7418         tw32(BUFMGR_DMA_LOW_WATER,
7419              tp->bufmgr_config.dma_low_water);
7420         tw32(BUFMGR_DMA_HIGH_WATER,
7421              tp->bufmgr_config.dma_high_water);
7422
7423         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7424         for (i = 0; i < 2000; i++) {
7425                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7426                         break;
7427                 udelay(10);
7428         }
7429         if (i >= 2000) {
7430                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7431                        tp->dev->name);
7432                 return -ENODEV;
7433         }
7434
7435         /* Setup replenish threshold. */
7436         val = tp->rx_pending / 8;
7437         if (val == 0)
7438                 val = 1;
7439         else if (val > tp->rx_std_max_post)
7440                 val = tp->rx_std_max_post;
7441         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7442                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7443                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7444
7445                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7446                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7447         }
7448
7449         tw32(RCVBDI_STD_THRESH, val);
7450
7451         /* Initialize TG3_BDINFO's at:
7452          *  RCVDBDI_STD_BD:     standard eth size rx ring
7453          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7454          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7455          *
7456          * like so:
7457          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7458          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7459          *                              ring attribute flags
7460          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7461          *
7462          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7463          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7464          *
7465          * The size of each ring is fixed in the firmware, but the location is
7466          * configurable.
7467          */
7468         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7469              ((u64) tpr->rx_std_mapping >> 32));
7470         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7471              ((u64) tpr->rx_std_mapping & 0xffffffff));
7472         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7473                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7474                      NIC_SRAM_RX_BUFFER_DESC);
7475
7476         /* Disable the mini ring */
7477         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7478                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7479                      BDINFO_FLAGS_DISABLED);
7480
7481         /* Program the jumbo buffer descriptor ring control
7482          * blocks on those devices that have them.
7483          */
7484         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7485             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7486                 /* Setup replenish threshold. */
7487                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7488
7489                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7490                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7491                              ((u64) tpr->rx_jmb_mapping >> 32));
7492                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7493                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7494                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7495                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7496                              BDINFO_FLAGS_USE_EXT_RECV);
7497                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7498                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7499                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7500                 } else {
7501                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7502                              BDINFO_FLAGS_DISABLED);
7503                 }
7504
7505                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7506                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7507                               (RX_STD_MAX_SIZE << 2);
7508                 else
7509                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7510         } else
7511                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7512
7513         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7514
7515         tpr->rx_std_ptr = tp->rx_pending;
7516         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7517                      tpr->rx_std_ptr);
7518
7519         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7520                           tp->rx_jumbo_pending : 0;
7521         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7522                      tpr->rx_jmb_ptr);
7523
7524         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7525                 tw32(STD_REPLENISH_LWM, 32);
7526                 tw32(JMB_REPLENISH_LWM, 16);
7527         }
7528
7529         tg3_rings_reset(tp);
7530
7531         /* Initialize MAC address and backoff seed. */
7532         __tg3_set_mac_addr(tp, 0);
7533
7534         /* MTU + ethernet header + FCS + optional VLAN tag */
7535         tw32(MAC_RX_MTU_SIZE,
7536              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7537
7538         /* The slot time is changed by tg3_setup_phy if we
7539          * run at gigabit with half duplex.
7540          */
7541         tw32(MAC_TX_LENGTHS,
7542              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7543              (6 << TX_LENGTHS_IPG_SHIFT) |
7544              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7545
7546         /* Receive rules. */
7547         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7548         tw32(RCVLPC_CONFIG, 0x0181);
7549
7550         /* Calculate RDMAC_MODE setting early, we need it to determine
7551          * the RCVLPC_STATE_ENABLE mask.
7552          */
7553         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7554                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7555                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7556                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7557                       RDMAC_MODE_LNGREAD_ENAB);
7558
7559         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7560             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7561             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7562                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7563                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7564                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7565
7566         /* If statement applies to 5705 and 5750 PCI devices only */
7567         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7568              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7569             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7570                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7571                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7572                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7573                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7574                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7575                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7576                 }
7577         }
7578
7579         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7580                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7581
7582         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7583                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7584
7585         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7586             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7587             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7588                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7589
7590         /* Receive/send statistics. */
7591         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7592                 val = tr32(RCVLPC_STATS_ENABLE);
7593                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7594                 tw32(RCVLPC_STATS_ENABLE, val);
7595         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7596                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7597                 val = tr32(RCVLPC_STATS_ENABLE);
7598                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7599                 tw32(RCVLPC_STATS_ENABLE, val);
7600         } else {
7601                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7602         }
7603         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7604         tw32(SNDDATAI_STATSENAB, 0xffffff);
7605         tw32(SNDDATAI_STATSCTRL,
7606              (SNDDATAI_SCTRL_ENABLE |
7607               SNDDATAI_SCTRL_FASTUPD));
7608
7609         /* Setup host coalescing engine. */
7610         tw32(HOSTCC_MODE, 0);
7611         for (i = 0; i < 2000; i++) {
7612                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7613                         break;
7614                 udelay(10);
7615         }
7616
7617         __tg3_set_coalesce(tp, &tp->coal);
7618
7619         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7620                 /* Status/statistics block address.  See tg3_timer,
7621                  * the tg3_periodic_fetch_stats call there, and
7622                  * tg3_get_stats to see how this works for 5705/5750 chips.
7623                  */
7624                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7625                      ((u64) tp->stats_mapping >> 32));
7626                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7627                      ((u64) tp->stats_mapping & 0xffffffff));
7628                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7629
7630                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7631
7632                 /* Clear statistics and status block memory areas */
7633                 for (i = NIC_SRAM_STATS_BLK;
7634                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7635                      i += sizeof(u32)) {
7636                         tg3_write_mem(tp, i, 0);
7637                         udelay(40);
7638                 }
7639         }
7640
7641         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7642
7643         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7644         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7645         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7646                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7647
7648         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7649                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7650                 /* reset to prevent losing 1st rx packet intermittently */
7651                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7652                 udelay(10);
7653         }
7654
7655         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7656                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7657         else
7658                 tp->mac_mode = 0;
7659         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7660                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7661         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7662             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7663             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7664                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7665         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7666         udelay(40);
7667
7668         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7669          * If TG3_FLG2_IS_NIC is zero, we should read the
7670          * register to preserve the GPIO settings for LOMs. The GPIOs,
7671          * whether used as inputs or outputs, are set by boot code after
7672          * reset.
7673          */
7674         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7675                 u32 gpio_mask;
7676
7677                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7678                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7679                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7680
7681                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7682                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7683                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7684
7685                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7686                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7687
7688                 tp->grc_local_ctrl &= ~gpio_mask;
7689                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7690
7691                 /* GPIO1 must be driven high for eeprom write protect */
7692                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7693                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7694                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7695         }
7696         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7697         udelay(100);
7698
7699         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7700                 val = tr32(MSGINT_MODE);
7701                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7702                 tw32(MSGINT_MODE, val);
7703         }
7704
7705         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7706                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7707                 udelay(40);
7708         }
7709
7710         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7711                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7712                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7713                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7714                WDMAC_MODE_LNGREAD_ENAB);
7715
7716         /* If statement applies to 5705 and 5750 PCI devices only */
7717         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7718              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7719             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7720                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7721                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7722                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7723                         /* nothing */
7724                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7725                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7726                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7727                         val |= WDMAC_MODE_RX_ACCEL;
7728                 }
7729         }
7730
7731         /* Enable host coalescing bug fix */
7732         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7733                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7734
7735         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7736                 val |= WDMAC_MODE_BURST_ALL_DATA;
7737
7738         tw32_f(WDMAC_MODE, val);
7739         udelay(40);
7740
7741         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7742                 u16 pcix_cmd;
7743
7744                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7745                                      &pcix_cmd);
7746                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7747                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7748                         pcix_cmd |= PCI_X_CMD_READ_2K;
7749                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7750                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7751                         pcix_cmd |= PCI_X_CMD_READ_2K;
7752                 }
7753                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7754                                       pcix_cmd);
7755         }
7756
7757         tw32_f(RDMAC_MODE, rdmac_mode);
7758         udelay(40);
7759
7760         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7761         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7762                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7763
7764         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7765                 tw32(SNDDATAC_MODE,
7766                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7767         else
7768                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7769
7770         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7771         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7772         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7773         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7774         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7775                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7776         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7777         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7778                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7779         tw32(SNDBDI_MODE, val);
7780         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7781
7782         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7783                 err = tg3_load_5701_a0_firmware_fix(tp);
7784                 if (err)
7785                         return err;
7786         }
7787
7788         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7789                 err = tg3_load_tso_firmware(tp);
7790                 if (err)
7791                         return err;
7792         }
7793
7794         tp->tx_mode = TX_MODE_ENABLE;
7795         tw32_f(MAC_TX_MODE, tp->tx_mode);
7796         udelay(100);
7797
7798         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7799                 u32 reg = MAC_RSS_INDIR_TBL_0;
7800                 u8 *ent = (u8 *)&val;
7801
7802                 /* Setup the indirection table */
7803                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7804                         int idx = i % sizeof(val);
7805
7806                         ent[idx] = i % (tp->irq_cnt - 1);
7807                         if (idx == sizeof(val) - 1) {
7808                                 tw32(reg, val);
7809                                 reg += 4;
7810                         }
7811                 }
7812
7813                 /* Setup the "secret" hash key. */
7814                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7815                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7816                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7817                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7818                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7819                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7820                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7821                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7822                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7823                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7824         }
7825
7826         tp->rx_mode = RX_MODE_ENABLE;
7827         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7828                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7829
7830         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7831                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7832                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7833                                RX_MODE_RSS_IPV6_HASH_EN |
7834                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7835                                RX_MODE_RSS_IPV4_HASH_EN |
7836                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7837
7838         tw32_f(MAC_RX_MODE, tp->rx_mode);
7839         udelay(10);
7840
7841         tw32(MAC_LED_CTRL, tp->led_ctrl);
7842
7843         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7844         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7845                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7846                 udelay(10);
7847         }
7848         tw32_f(MAC_RX_MODE, tp->rx_mode);
7849         udelay(10);
7850
7851         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7852                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7853                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7854                         /* Set drive transmission level to 1.2V  */
7855                         /* only if the signal pre-emphasis bit is not set  */
7856                         val = tr32(MAC_SERDES_CFG);
7857                         val &= 0xfffff000;
7858                         val |= 0x880;
7859                         tw32(MAC_SERDES_CFG, val);
7860                 }
7861                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7862                         tw32(MAC_SERDES_CFG, 0x616000);
7863         }
7864
7865         /* Prevent chip from dropping frames when flow control
7866          * is enabled.
7867          */
7868         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7869
7870         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7871             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7872                 /* Use hardware link auto-negotiation */
7873                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7874         }
7875
7876         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7877             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7878                 u32 tmp;
7879
7880                 tmp = tr32(SERDES_RX_CTRL);
7881                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7882                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7883                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7884                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7885         }
7886
7887         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7888                 if (tp->link_config.phy_is_low_power) {
7889                         tp->link_config.phy_is_low_power = 0;
7890                         tp->link_config.speed = tp->link_config.orig_speed;
7891                         tp->link_config.duplex = tp->link_config.orig_duplex;
7892                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7893                 }
7894
7895                 err = tg3_setup_phy(tp, 0);
7896                 if (err)
7897                         return err;
7898
7899                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7900                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7901                         u32 tmp;
7902
7903                         /* Clear CRC stats. */
7904                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7905                                 tg3_writephy(tp, MII_TG3_TEST1,
7906                                              tmp | MII_TG3_TEST1_CRC_EN);
7907                                 tg3_readphy(tp, 0x14, &tmp);
7908                         }
7909                 }
7910         }
7911
7912         __tg3_set_rx_mode(tp->dev);
7913
7914         /* Initialize receive rules. */
7915         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7916         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7917         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7918         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7919
7920         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7921             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7922                 limit = 8;
7923         else
7924                 limit = 16;
7925         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7926                 limit -= 4;
7927         switch (limit) {
7928         case 16:
7929                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7930         case 15:
7931                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7932         case 14:
7933                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7934         case 13:
7935                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7936         case 12:
7937                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7938         case 11:
7939                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7940         case 10:
7941                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7942         case 9:
7943                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7944         case 8:
7945                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7946         case 7:
7947                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7948         case 6:
7949                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7950         case 5:
7951                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7952         case 4:
7953                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7954         case 3:
7955                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7956         case 2:
7957         case 1:
7958
7959         default:
7960                 break;
7961         }
7962
7963         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7964                 /* Write our heartbeat update interval to APE. */
7965                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7966                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7967
7968         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7969
7970         return 0;
7971 }
7972
7973 /* Called at device open time to get the chip ready for
7974  * packet processing.  Invoked with tp->lock held.
7975  */
7976 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7977 {
7978         tg3_switch_clocks(tp);
7979
7980         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7981
7982         return tg3_reset_hw(tp, reset_phy);
7983 }
7984
7985 #define TG3_STAT_ADD32(PSTAT, REG) \
7986 do {    u32 __val = tr32(REG); \
7987         (PSTAT)->low += __val; \
7988         if ((PSTAT)->low < __val) \
7989                 (PSTAT)->high += 1; \
7990 } while (0)
7991
7992 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7993 {
7994         struct tg3_hw_stats *sp = tp->hw_stats;
7995
7996         if (!netif_carrier_ok(tp->dev))
7997                 return;
7998
7999         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8000         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8001         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8002         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8003         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8004         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8005         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8006         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8007         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8008         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8009         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8010         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8011         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8012
8013         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8014         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8015         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8016         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8017         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8018         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8019         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8020         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8021         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8022         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8023         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8024         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8025         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8026         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8027
8028         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8029         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8030         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8031 }
8032
8033 static void tg3_timer(unsigned long __opaque)
8034 {
8035         struct tg3 *tp = (struct tg3 *) __opaque;
8036
8037         if (tp->irq_sync)
8038                 goto restart_timer;
8039
8040         spin_lock(&tp->lock);
8041
8042         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8043                 /* All of this garbage is because when using non-tagged
8044                  * IRQ status the mailbox/status_block protocol the chip
8045                  * uses with the cpu is race prone.
8046                  */
8047                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8048                         tw32(GRC_LOCAL_CTRL,
8049                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8050                 } else {
8051                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8052                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8053                 }
8054
8055                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8056                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8057                         spin_unlock(&tp->lock);
8058                         schedule_work(&tp->reset_task);
8059                         return;
8060                 }
8061         }
8062
8063         /* This part only runs once per second. */
8064         if (!--tp->timer_counter) {
8065                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8066                         tg3_periodic_fetch_stats(tp);
8067
8068                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8069                         u32 mac_stat;
8070                         int phy_event;
8071
8072                         mac_stat = tr32(MAC_STATUS);
8073
8074                         phy_event = 0;
8075                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8076                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8077                                         phy_event = 1;
8078                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8079                                 phy_event = 1;
8080
8081                         if (phy_event)
8082                                 tg3_setup_phy(tp, 0);
8083                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8084                         u32 mac_stat = tr32(MAC_STATUS);
8085                         int need_setup = 0;
8086
8087                         if (netif_carrier_ok(tp->dev) &&
8088                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8089                                 need_setup = 1;
8090                         }
8091                         if (! netif_carrier_ok(tp->dev) &&
8092                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8093                                          MAC_STATUS_SIGNAL_DET))) {
8094                                 need_setup = 1;
8095                         }
8096                         if (need_setup) {
8097                                 if (!tp->serdes_counter) {
8098                                         tw32_f(MAC_MODE,
8099                                              (tp->mac_mode &
8100                                               ~MAC_MODE_PORT_MODE_MASK));
8101                                         udelay(40);
8102                                         tw32_f(MAC_MODE, tp->mac_mode);
8103                                         udelay(40);
8104                                 }
8105                                 tg3_setup_phy(tp, 0);
8106                         }
8107                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8108                         tg3_serdes_parallel_detect(tp);
8109
8110                 tp->timer_counter = tp->timer_multiplier;
8111         }
8112
8113         /* Heartbeat is only sent once every 2 seconds.
8114          *
8115          * The heartbeat is to tell the ASF firmware that the host
8116          * driver is still alive.  In the event that the OS crashes,
8117          * ASF needs to reset the hardware to free up the FIFO space
8118          * that may be filled with rx packets destined for the host.
8119          * If the FIFO is full, ASF will no longer function properly.
8120          *
8121          * Unintended resets have been reported on real time kernels
8122          * where the timer doesn't run on time.  Netpoll will also have
8123          * same problem.
8124          *
8125          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8126          * to check the ring condition when the heartbeat is expiring
8127          * before doing the reset.  This will prevent most unintended
8128          * resets.
8129          */
8130         if (!--tp->asf_counter) {
8131                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8132                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8133                         tg3_wait_for_event_ack(tp);
8134
8135                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8136                                       FWCMD_NICDRV_ALIVE3);
8137                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8138                         /* 5 seconds timeout */
8139                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8140
8141                         tg3_generate_fw_event(tp);
8142                 }
8143                 tp->asf_counter = tp->asf_multiplier;
8144         }
8145
8146         spin_unlock(&tp->lock);
8147
8148 restart_timer:
8149         tp->timer.expires = jiffies + tp->timer_offset;
8150         add_timer(&tp->timer);
8151 }
8152
8153 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8154 {
8155         irq_handler_t fn;
8156         unsigned long flags;
8157         char *name;
8158         struct tg3_napi *tnapi = &tp->napi[irq_num];
8159
8160         if (tp->irq_cnt == 1)
8161                 name = tp->dev->name;
8162         else {
8163                 name = &tnapi->irq_lbl[0];
8164                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8165                 name[IFNAMSIZ-1] = 0;
8166         }
8167
8168         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8169                 fn = tg3_msi;
8170                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8171                         fn = tg3_msi_1shot;
8172                 flags = IRQF_SAMPLE_RANDOM;
8173         } else {
8174                 fn = tg3_interrupt;
8175                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8176                         fn = tg3_interrupt_tagged;
8177                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8178         }
8179
8180         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8181 }
8182
8183 static int tg3_test_interrupt(struct tg3 *tp)
8184 {
8185         struct tg3_napi *tnapi = &tp->napi[0];
8186         struct net_device *dev = tp->dev;
8187         int err, i, intr_ok = 0;
8188         u32 val;
8189
8190         if (!netif_running(dev))
8191                 return -ENODEV;
8192
8193         tg3_disable_ints(tp);
8194
8195         free_irq(tnapi->irq_vec, tnapi);
8196
8197         /*
8198          * Turn off MSI one shot mode.  Otherwise this test has no
8199          * observable way to know whether the interrupt was delivered.
8200          */
8201         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8202             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8203                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8204                 tw32(MSGINT_MODE, val);
8205         }
8206
8207         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8208                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8209         if (err)
8210                 return err;
8211
8212         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8213         tg3_enable_ints(tp);
8214
8215         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8216                tnapi->coal_now);
8217
8218         for (i = 0; i < 5; i++) {
8219                 u32 int_mbox, misc_host_ctrl;
8220
8221                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8222                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8223
8224                 if ((int_mbox != 0) ||
8225                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8226                         intr_ok = 1;
8227                         break;
8228                 }
8229
8230                 msleep(10);
8231         }
8232
8233         tg3_disable_ints(tp);
8234
8235         free_irq(tnapi->irq_vec, tnapi);
8236
8237         err = tg3_request_irq(tp, 0);
8238
8239         if (err)
8240                 return err;
8241
8242         if (intr_ok) {
8243                 /* Reenable MSI one shot mode. */
8244                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8245                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8246                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8247                         tw32(MSGINT_MODE, val);
8248                 }
8249                 return 0;
8250         }
8251
8252         return -EIO;
8253 }
8254
8255 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8256  * successfully restored
8257  */
8258 static int tg3_test_msi(struct tg3 *tp)
8259 {
8260         int err;
8261         u16 pci_cmd;
8262
8263         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8264                 return 0;
8265
8266         /* Turn off SERR reporting in case MSI terminates with Master
8267          * Abort.
8268          */
8269         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8270         pci_write_config_word(tp->pdev, PCI_COMMAND,
8271                               pci_cmd & ~PCI_COMMAND_SERR);
8272
8273         err = tg3_test_interrupt(tp);
8274
8275         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8276
8277         if (!err)
8278                 return 0;
8279
8280         /* other failures */
8281         if (err != -EIO)
8282                 return err;
8283
8284         /* MSI test failed, go back to INTx mode */
8285         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8286                "switching to INTx mode. Please report this failure to "
8287                "the PCI maintainer and include system chipset information.\n",
8288                        tp->dev->name);
8289
8290         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8291
8292         pci_disable_msi(tp->pdev);
8293
8294         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8295
8296         err = tg3_request_irq(tp, 0);
8297         if (err)
8298                 return err;
8299
8300         /* Need to reset the chip because the MSI cycle may have terminated
8301          * with Master Abort.
8302          */
8303         tg3_full_lock(tp, 1);
8304
8305         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8306         err = tg3_init_hw(tp, 1);
8307
8308         tg3_full_unlock(tp);
8309
8310         if (err)
8311                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8312
8313         return err;
8314 }
8315
8316 static int tg3_request_firmware(struct tg3 *tp)
8317 {
8318         const __be32 *fw_data;
8319
8320         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8321                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8322                        tp->dev->name, tp->fw_needed);
8323                 return -ENOENT;
8324         }
8325
8326         fw_data = (void *)tp->fw->data;
8327
8328         /* Firmware blob starts with version numbers, followed by
8329          * start address and _full_ length including BSS sections
8330          * (which must be longer than the actual data, of course
8331          */
8332
8333         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8334         if (tp->fw_len < (tp->fw->size - 12)) {
8335                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8336                        tp->dev->name, tp->fw_len, tp->fw_needed);
8337                 release_firmware(tp->fw);
8338                 tp->fw = NULL;
8339                 return -EINVAL;
8340         }
8341
8342         /* We no longer need firmware; we have it. */
8343         tp->fw_needed = NULL;
8344         return 0;
8345 }
8346
8347 static bool tg3_enable_msix(struct tg3 *tp)
8348 {
8349         int i, rc, cpus = num_online_cpus();
8350         struct msix_entry msix_ent[tp->irq_max];
8351
8352         if (cpus == 1)
8353                 /* Just fallback to the simpler MSI mode. */
8354                 return false;
8355
8356         /*
8357          * We want as many rx rings enabled as there are cpus.
8358          * The first MSIX vector only deals with link interrupts, etc,
8359          * so we add one to the number of vectors we are requesting.
8360          */
8361         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8362
8363         for (i = 0; i < tp->irq_max; i++) {
8364                 msix_ent[i].entry  = i;
8365                 msix_ent[i].vector = 0;
8366         }
8367
8368         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8369         if (rc != 0) {
8370                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8371                         return false;
8372                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8373                         return false;
8374                 printk(KERN_NOTICE
8375                        "%s: Requested %d MSI-X vectors, received %d\n",
8376                        tp->dev->name, tp->irq_cnt, rc);
8377                 tp->irq_cnt = rc;
8378         }
8379
8380         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8381
8382         for (i = 0; i < tp->irq_max; i++)
8383                 tp->napi[i].irq_vec = msix_ent[i].vector;
8384
8385         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8386
8387         return true;
8388 }
8389
8390 static void tg3_ints_init(struct tg3 *tp)
8391 {
8392         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8393             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8394                 /* All MSI supporting chips should support tagged
8395                  * status.  Assert that this is the case.
8396                  */
8397                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8398                        "Not using MSI.\n", tp->dev->name);
8399                 goto defcfg;
8400         }
8401
8402         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8403                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8404         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8405                  pci_enable_msi(tp->pdev) == 0)
8406                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8407
8408         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8409                 u32 msi_mode = tr32(MSGINT_MODE);
8410                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8411                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8412                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8413         }
8414 defcfg:
8415         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8416                 tp->irq_cnt = 1;
8417                 tp->napi[0].irq_vec = tp->pdev->irq;
8418                 tp->dev->real_num_tx_queues = 1;
8419         }
8420 }
8421
8422 static void tg3_ints_fini(struct tg3 *tp)
8423 {
8424         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8425                 pci_disable_msix(tp->pdev);
8426         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8427                 pci_disable_msi(tp->pdev);
8428         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8429         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8430 }
8431
8432 static int tg3_open(struct net_device *dev)
8433 {
8434         struct tg3 *tp = netdev_priv(dev);
8435         int i, err;
8436
8437         if (tp->fw_needed) {
8438                 err = tg3_request_firmware(tp);
8439                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8440                         if (err)
8441                                 return err;
8442                 } else if (err) {
8443                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8444                                tp->dev->name);
8445                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8446                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8447                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8448                                tp->dev->name);
8449                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8450                 }
8451         }
8452
8453         netif_carrier_off(tp->dev);
8454
8455         err = tg3_set_power_state(tp, PCI_D0);
8456         if (err)
8457                 return err;
8458
8459         tg3_full_lock(tp, 0);
8460
8461         tg3_disable_ints(tp);
8462         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8463
8464         tg3_full_unlock(tp);
8465
8466         /*
8467          * Setup interrupts first so we know how
8468          * many NAPI resources to allocate
8469          */
8470         tg3_ints_init(tp);
8471
8472         /* The placement of this call is tied
8473          * to the setup and use of Host TX descriptors.
8474          */
8475         err = tg3_alloc_consistent(tp);
8476         if (err)
8477                 goto err_out1;
8478
8479         tg3_napi_enable(tp);
8480
8481         for (i = 0; i < tp->irq_cnt; i++) {
8482                 struct tg3_napi *tnapi = &tp->napi[i];
8483                 err = tg3_request_irq(tp, i);
8484                 if (err) {
8485                         for (i--; i >= 0; i--)
8486                                 free_irq(tnapi->irq_vec, tnapi);
8487                         break;
8488                 }
8489         }
8490
8491         if (err)
8492                 goto err_out2;
8493
8494         tg3_full_lock(tp, 0);
8495
8496         err = tg3_init_hw(tp, 1);
8497         if (err) {
8498                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8499                 tg3_free_rings(tp);
8500         } else {
8501                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8502                         tp->timer_offset = HZ;
8503                 else
8504                         tp->timer_offset = HZ / 10;
8505
8506                 BUG_ON(tp->timer_offset > HZ);
8507                 tp->timer_counter = tp->timer_multiplier =
8508                         (HZ / tp->timer_offset);
8509                 tp->asf_counter = tp->asf_multiplier =
8510                         ((HZ / tp->timer_offset) * 2);
8511
8512                 init_timer(&tp->timer);
8513                 tp->timer.expires = jiffies + tp->timer_offset;
8514                 tp->timer.data = (unsigned long) tp;
8515                 tp->timer.function = tg3_timer;
8516         }
8517
8518         tg3_full_unlock(tp);
8519
8520         if (err)
8521                 goto err_out3;
8522
8523         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8524                 err = tg3_test_msi(tp);
8525
8526                 if (err) {
8527                         tg3_full_lock(tp, 0);
8528                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8529                         tg3_free_rings(tp);
8530                         tg3_full_unlock(tp);
8531
8532                         goto err_out2;
8533                 }
8534
8535                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8536                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8537                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8538                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8539
8540                         tw32(PCIE_TRANSACTION_CFG,
8541                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8542                 }
8543         }
8544
8545         tg3_phy_start(tp);
8546
8547         tg3_full_lock(tp, 0);
8548
8549         add_timer(&tp->timer);
8550         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8551         tg3_enable_ints(tp);
8552
8553         tg3_full_unlock(tp);
8554
8555         netif_tx_start_all_queues(dev);
8556
8557         return 0;
8558
8559 err_out3:
8560         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8561                 struct tg3_napi *tnapi = &tp->napi[i];
8562                 free_irq(tnapi->irq_vec, tnapi);
8563         }
8564
8565 err_out2:
8566         tg3_napi_disable(tp);
8567         tg3_free_consistent(tp);
8568
8569 err_out1:
8570         tg3_ints_fini(tp);
8571         return err;
8572 }
8573
8574 #if 0
8575 /*static*/ void tg3_dump_state(struct tg3 *tp)
8576 {
8577         u32 val32, val32_2, val32_3, val32_4, val32_5;
8578         u16 val16;
8579         int i;
8580         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8581
8582         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8583         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8584         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8585                val16, val32);
8586
8587         /* MAC block */
8588         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8589                tr32(MAC_MODE), tr32(MAC_STATUS));
8590         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8591                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8592         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8593                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8594         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8595                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8596
8597         /* Send data initiator control block */
8598         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8599                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8600         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8601                tr32(SNDDATAI_STATSCTRL));
8602
8603         /* Send data completion control block */
8604         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8605
8606         /* Send BD ring selector block */
8607         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8608                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8609
8610         /* Send BD initiator control block */
8611         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8612                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8613
8614         /* Send BD completion control block */
8615         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8616
8617         /* Receive list placement control block */
8618         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8619                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8620         printk("       RCVLPC_STATSCTRL[%08x]\n",
8621                tr32(RCVLPC_STATSCTRL));
8622
8623         /* Receive data and receive BD initiator control block */
8624         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8625                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8626
8627         /* Receive data completion control block */
8628         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8629                tr32(RCVDCC_MODE));
8630
8631         /* Receive BD initiator control block */
8632         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8633                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8634
8635         /* Receive BD completion control block */
8636         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8637                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8638
8639         /* Receive list selector control block */
8640         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8641                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8642
8643         /* Mbuf cluster free block */
8644         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8645                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8646
8647         /* Host coalescing control block */
8648         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8649                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8650         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8651                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8652                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8653         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8654                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8655                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8656         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8657                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8658         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8659                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8660
8661         /* Memory arbiter control block */
8662         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8663                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8664
8665         /* Buffer manager control block */
8666         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8667                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8668         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8669                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8670         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8671                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8672                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8673                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8674
8675         /* Read DMA control block */
8676         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8677                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8678
8679         /* Write DMA control block */
8680         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8681                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8682
8683         /* DMA completion block */
8684         printk("DEBUG: DMAC_MODE[%08x]\n",
8685                tr32(DMAC_MODE));
8686
8687         /* GRC block */
8688         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8689                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8690         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8691                tr32(GRC_LOCAL_CTRL));
8692
8693         /* TG3_BDINFOs */
8694         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8695                tr32(RCVDBDI_JUMBO_BD + 0x0),
8696                tr32(RCVDBDI_JUMBO_BD + 0x4),
8697                tr32(RCVDBDI_JUMBO_BD + 0x8),
8698                tr32(RCVDBDI_JUMBO_BD + 0xc));
8699         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8700                tr32(RCVDBDI_STD_BD + 0x0),
8701                tr32(RCVDBDI_STD_BD + 0x4),
8702                tr32(RCVDBDI_STD_BD + 0x8),
8703                tr32(RCVDBDI_STD_BD + 0xc));
8704         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8705                tr32(RCVDBDI_MINI_BD + 0x0),
8706                tr32(RCVDBDI_MINI_BD + 0x4),
8707                tr32(RCVDBDI_MINI_BD + 0x8),
8708                tr32(RCVDBDI_MINI_BD + 0xc));
8709
8710         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8711         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8712         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8713         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8714         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8715                val32, val32_2, val32_3, val32_4);
8716
8717         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8718         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8719         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8720         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8721         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8722                val32, val32_2, val32_3, val32_4);
8723
8724         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8725         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8726         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8727         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8728         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8729         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8730                val32, val32_2, val32_3, val32_4, val32_5);
8731
8732         /* SW status block */
8733         printk(KERN_DEBUG
8734          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8735                sblk->status,
8736                sblk->status_tag,
8737                sblk->rx_jumbo_consumer,
8738                sblk->rx_consumer,
8739                sblk->rx_mini_consumer,
8740                sblk->idx[0].rx_producer,
8741                sblk->idx[0].tx_consumer);
8742
8743         /* SW statistics block */
8744         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8745                ((u32 *)tp->hw_stats)[0],
8746                ((u32 *)tp->hw_stats)[1],
8747                ((u32 *)tp->hw_stats)[2],
8748                ((u32 *)tp->hw_stats)[3]);
8749
8750         /* Mailboxes */
8751         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8752                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8753                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8754                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8755                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8756
8757         /* NIC side send descriptors. */
8758         for (i = 0; i < 6; i++) {
8759                 unsigned long txd;
8760
8761                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8762                         + (i * sizeof(struct tg3_tx_buffer_desc));
8763                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8764                        i,
8765                        readl(txd + 0x0), readl(txd + 0x4),
8766                        readl(txd + 0x8), readl(txd + 0xc));
8767         }
8768
8769         /* NIC side RX descriptors. */
8770         for (i = 0; i < 6; i++) {
8771                 unsigned long rxd;
8772
8773                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8774                         + (i * sizeof(struct tg3_rx_buffer_desc));
8775                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8776                        i,
8777                        readl(rxd + 0x0), readl(rxd + 0x4),
8778                        readl(rxd + 0x8), readl(rxd + 0xc));
8779                 rxd += (4 * sizeof(u32));
8780                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8781                        i,
8782                        readl(rxd + 0x0), readl(rxd + 0x4),
8783                        readl(rxd + 0x8), readl(rxd + 0xc));
8784         }
8785
8786         for (i = 0; i < 6; i++) {
8787                 unsigned long rxd;
8788
8789                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8790                         + (i * sizeof(struct tg3_rx_buffer_desc));
8791                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8792                        i,
8793                        readl(rxd + 0x0), readl(rxd + 0x4),
8794                        readl(rxd + 0x8), readl(rxd + 0xc));
8795                 rxd += (4 * sizeof(u32));
8796                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8797                        i,
8798                        readl(rxd + 0x0), readl(rxd + 0x4),
8799                        readl(rxd + 0x8), readl(rxd + 0xc));
8800         }
8801 }
8802 #endif
8803
8804 static struct net_device_stats *tg3_get_stats(struct net_device *);
8805 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8806
8807 static int tg3_close(struct net_device *dev)
8808 {
8809         int i;
8810         struct tg3 *tp = netdev_priv(dev);
8811
8812         tg3_napi_disable(tp);
8813         cancel_work_sync(&tp->reset_task);
8814
8815         netif_tx_stop_all_queues(dev);
8816
8817         del_timer_sync(&tp->timer);
8818
8819         tg3_phy_stop(tp);
8820
8821         tg3_full_lock(tp, 1);
8822 #if 0
8823         tg3_dump_state(tp);
8824 #endif
8825
8826         tg3_disable_ints(tp);
8827
8828         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8829         tg3_free_rings(tp);
8830         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8831
8832         tg3_full_unlock(tp);
8833
8834         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8835                 struct tg3_napi *tnapi = &tp->napi[i];
8836                 free_irq(tnapi->irq_vec, tnapi);
8837         }
8838
8839         tg3_ints_fini(tp);
8840
8841         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8842                sizeof(tp->net_stats_prev));
8843         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8844                sizeof(tp->estats_prev));
8845
8846         tg3_free_consistent(tp);
8847
8848         tg3_set_power_state(tp, PCI_D3hot);
8849
8850         netif_carrier_off(tp->dev);
8851
8852         return 0;
8853 }
8854
8855 static inline unsigned long get_stat64(tg3_stat64_t *val)
8856 {
8857         unsigned long ret;
8858
8859 #if (BITS_PER_LONG == 32)
8860         ret = val->low;
8861 #else
8862         ret = ((u64)val->high << 32) | ((u64)val->low);
8863 #endif
8864         return ret;
8865 }
8866
8867 static inline u64 get_estat64(tg3_stat64_t *val)
8868 {
8869        return ((u64)val->high << 32) | ((u64)val->low);
8870 }
8871
8872 static unsigned long calc_crc_errors(struct tg3 *tp)
8873 {
8874         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8875
8876         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8877             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8878              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8879                 u32 val;
8880
8881                 spin_lock_bh(&tp->lock);
8882                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8883                         tg3_writephy(tp, MII_TG3_TEST1,
8884                                      val | MII_TG3_TEST1_CRC_EN);
8885                         tg3_readphy(tp, 0x14, &val);
8886                 } else
8887                         val = 0;
8888                 spin_unlock_bh(&tp->lock);
8889
8890                 tp->phy_crc_errors += val;
8891
8892                 return tp->phy_crc_errors;
8893         }
8894
8895         return get_stat64(&hw_stats->rx_fcs_errors);
8896 }
8897
8898 #define ESTAT_ADD(member) \
8899         estats->member =        old_estats->member + \
8900                                 get_estat64(&hw_stats->member)
8901
8902 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8903 {
8904         struct tg3_ethtool_stats *estats = &tp->estats;
8905         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8906         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8907
8908         if (!hw_stats)
8909                 return old_estats;
8910
8911         ESTAT_ADD(rx_octets);
8912         ESTAT_ADD(rx_fragments);
8913         ESTAT_ADD(rx_ucast_packets);
8914         ESTAT_ADD(rx_mcast_packets);
8915         ESTAT_ADD(rx_bcast_packets);
8916         ESTAT_ADD(rx_fcs_errors);
8917         ESTAT_ADD(rx_align_errors);
8918         ESTAT_ADD(rx_xon_pause_rcvd);
8919         ESTAT_ADD(rx_xoff_pause_rcvd);
8920         ESTAT_ADD(rx_mac_ctrl_rcvd);
8921         ESTAT_ADD(rx_xoff_entered);
8922         ESTAT_ADD(rx_frame_too_long_errors);
8923         ESTAT_ADD(rx_jabbers);
8924         ESTAT_ADD(rx_undersize_packets);
8925         ESTAT_ADD(rx_in_length_errors);
8926         ESTAT_ADD(rx_out_length_errors);
8927         ESTAT_ADD(rx_64_or_less_octet_packets);
8928         ESTAT_ADD(rx_65_to_127_octet_packets);
8929         ESTAT_ADD(rx_128_to_255_octet_packets);
8930         ESTAT_ADD(rx_256_to_511_octet_packets);
8931         ESTAT_ADD(rx_512_to_1023_octet_packets);
8932         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8933         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8934         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8935         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8936         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8937
8938         ESTAT_ADD(tx_octets);
8939         ESTAT_ADD(tx_collisions);
8940         ESTAT_ADD(tx_xon_sent);
8941         ESTAT_ADD(tx_xoff_sent);
8942         ESTAT_ADD(tx_flow_control);
8943         ESTAT_ADD(tx_mac_errors);
8944         ESTAT_ADD(tx_single_collisions);
8945         ESTAT_ADD(tx_mult_collisions);
8946         ESTAT_ADD(tx_deferred);
8947         ESTAT_ADD(tx_excessive_collisions);
8948         ESTAT_ADD(tx_late_collisions);
8949         ESTAT_ADD(tx_collide_2times);
8950         ESTAT_ADD(tx_collide_3times);
8951         ESTAT_ADD(tx_collide_4times);
8952         ESTAT_ADD(tx_collide_5times);
8953         ESTAT_ADD(tx_collide_6times);
8954         ESTAT_ADD(tx_collide_7times);
8955         ESTAT_ADD(tx_collide_8times);
8956         ESTAT_ADD(tx_collide_9times);
8957         ESTAT_ADD(tx_collide_10times);
8958         ESTAT_ADD(tx_collide_11times);
8959         ESTAT_ADD(tx_collide_12times);
8960         ESTAT_ADD(tx_collide_13times);
8961         ESTAT_ADD(tx_collide_14times);
8962         ESTAT_ADD(tx_collide_15times);
8963         ESTAT_ADD(tx_ucast_packets);
8964         ESTAT_ADD(tx_mcast_packets);
8965         ESTAT_ADD(tx_bcast_packets);
8966         ESTAT_ADD(tx_carrier_sense_errors);
8967         ESTAT_ADD(tx_discards);
8968         ESTAT_ADD(tx_errors);
8969
8970         ESTAT_ADD(dma_writeq_full);
8971         ESTAT_ADD(dma_write_prioq_full);
8972         ESTAT_ADD(rxbds_empty);
8973         ESTAT_ADD(rx_discards);
8974         ESTAT_ADD(rx_errors);
8975         ESTAT_ADD(rx_threshold_hit);
8976
8977         ESTAT_ADD(dma_readq_full);
8978         ESTAT_ADD(dma_read_prioq_full);
8979         ESTAT_ADD(tx_comp_queue_full);
8980
8981         ESTAT_ADD(ring_set_send_prod_index);
8982         ESTAT_ADD(ring_status_update);
8983         ESTAT_ADD(nic_irqs);
8984         ESTAT_ADD(nic_avoided_irqs);
8985         ESTAT_ADD(nic_tx_threshold_hit);
8986
8987         return estats;
8988 }
8989
8990 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8991 {
8992         struct tg3 *tp = netdev_priv(dev);
8993         struct net_device_stats *stats = &tp->net_stats;
8994         struct net_device_stats *old_stats = &tp->net_stats_prev;
8995         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8996
8997         if (!hw_stats)
8998                 return old_stats;
8999
9000         stats->rx_packets = old_stats->rx_packets +
9001                 get_stat64(&hw_stats->rx_ucast_packets) +
9002                 get_stat64(&hw_stats->rx_mcast_packets) +
9003                 get_stat64(&hw_stats->rx_bcast_packets);
9004
9005         stats->tx_packets = old_stats->tx_packets +
9006                 get_stat64(&hw_stats->tx_ucast_packets) +
9007                 get_stat64(&hw_stats->tx_mcast_packets) +
9008                 get_stat64(&hw_stats->tx_bcast_packets);
9009
9010         stats->rx_bytes = old_stats->rx_bytes +
9011                 get_stat64(&hw_stats->rx_octets);
9012         stats->tx_bytes = old_stats->tx_bytes +
9013                 get_stat64(&hw_stats->tx_octets);
9014
9015         stats->rx_errors = old_stats->rx_errors +
9016                 get_stat64(&hw_stats->rx_errors);
9017         stats->tx_errors = old_stats->tx_errors +
9018                 get_stat64(&hw_stats->tx_errors) +
9019                 get_stat64(&hw_stats->tx_mac_errors) +
9020                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9021                 get_stat64(&hw_stats->tx_discards);
9022
9023         stats->multicast = old_stats->multicast +
9024                 get_stat64(&hw_stats->rx_mcast_packets);
9025         stats->collisions = old_stats->collisions +
9026                 get_stat64(&hw_stats->tx_collisions);
9027
9028         stats->rx_length_errors = old_stats->rx_length_errors +
9029                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9030                 get_stat64(&hw_stats->rx_undersize_packets);
9031
9032         stats->rx_over_errors = old_stats->rx_over_errors +
9033                 get_stat64(&hw_stats->rxbds_empty);
9034         stats->rx_frame_errors = old_stats->rx_frame_errors +
9035                 get_stat64(&hw_stats->rx_align_errors);
9036         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9037                 get_stat64(&hw_stats->tx_discards);
9038         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9039                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9040
9041         stats->rx_crc_errors = old_stats->rx_crc_errors +
9042                 calc_crc_errors(tp);
9043
9044         stats->rx_missed_errors = old_stats->rx_missed_errors +
9045                 get_stat64(&hw_stats->rx_discards);
9046
9047         return stats;
9048 }
9049
9050 static inline u32 calc_crc(unsigned char *buf, int len)
9051 {
9052         u32 reg;
9053         u32 tmp;
9054         int j, k;
9055
9056         reg = 0xffffffff;
9057
9058         for (j = 0; j < len; j++) {
9059                 reg ^= buf[j];
9060
9061                 for (k = 0; k < 8; k++) {
9062                         tmp = reg & 0x01;
9063
9064                         reg >>= 1;
9065
9066                         if (tmp) {
9067                                 reg ^= 0xedb88320;
9068                         }
9069                 }
9070         }
9071
9072         return ~reg;
9073 }
9074
9075 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9076 {
9077         /* accept or reject all multicast frames */
9078         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9079         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9080         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9081         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9082 }
9083
9084 static void __tg3_set_rx_mode(struct net_device *dev)
9085 {
9086         struct tg3 *tp = netdev_priv(dev);
9087         u32 rx_mode;
9088
9089         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9090                                   RX_MODE_KEEP_VLAN_TAG);
9091
9092         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9093          * flag clear.
9094          */
9095 #if TG3_VLAN_TAG_USED
9096         if (!tp->vlgrp &&
9097             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9098                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9099 #else
9100         /* By definition, VLAN is disabled always in this
9101          * case.
9102          */
9103         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9104                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9105 #endif
9106
9107         if (dev->flags & IFF_PROMISC) {
9108                 /* Promiscuous mode. */
9109                 rx_mode |= RX_MODE_PROMISC;
9110         } else if (dev->flags & IFF_ALLMULTI) {
9111                 /* Accept all multicast. */
9112                 tg3_set_multi (tp, 1);
9113         } else if (dev->mc_count < 1) {
9114                 /* Reject all multicast. */
9115                 tg3_set_multi (tp, 0);
9116         } else {
9117                 /* Accept one or more multicast(s). */
9118                 struct dev_mc_list *mclist;
9119                 unsigned int i;
9120                 u32 mc_filter[4] = { 0, };
9121                 u32 regidx;
9122                 u32 bit;
9123                 u32 crc;
9124
9125                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9126                      i++, mclist = mclist->next) {
9127
9128                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9129                         bit = ~crc & 0x7f;
9130                         regidx = (bit & 0x60) >> 5;
9131                         bit &= 0x1f;
9132                         mc_filter[regidx] |= (1 << bit);
9133                 }
9134
9135                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9136                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9137                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9138                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9139         }
9140
9141         if (rx_mode != tp->rx_mode) {
9142                 tp->rx_mode = rx_mode;
9143                 tw32_f(MAC_RX_MODE, rx_mode);
9144                 udelay(10);
9145         }
9146 }
9147
9148 static void tg3_set_rx_mode(struct net_device *dev)
9149 {
9150         struct tg3 *tp = netdev_priv(dev);
9151
9152         if (!netif_running(dev))
9153                 return;
9154
9155         tg3_full_lock(tp, 0);
9156         __tg3_set_rx_mode(dev);
9157         tg3_full_unlock(tp);
9158 }
9159
9160 #define TG3_REGDUMP_LEN         (32 * 1024)
9161
9162 static int tg3_get_regs_len(struct net_device *dev)
9163 {
9164         return TG3_REGDUMP_LEN;
9165 }
9166
9167 static void tg3_get_regs(struct net_device *dev,
9168                 struct ethtool_regs *regs, void *_p)
9169 {
9170         u32 *p = _p;
9171         struct tg3 *tp = netdev_priv(dev);
9172         u8 *orig_p = _p;
9173         int i;
9174
9175         regs->version = 0;
9176
9177         memset(p, 0, TG3_REGDUMP_LEN);
9178
9179         if (tp->link_config.phy_is_low_power)
9180                 return;
9181
9182         tg3_full_lock(tp, 0);
9183
9184 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9185 #define GET_REG32_LOOP(base,len)                \
9186 do {    p = (u32 *)(orig_p + (base));           \
9187         for (i = 0; i < len; i += 4)            \
9188                 __GET_REG32((base) + i);        \
9189 } while (0)
9190 #define GET_REG32_1(reg)                        \
9191 do {    p = (u32 *)(orig_p + (reg));            \
9192         __GET_REG32((reg));                     \
9193 } while (0)
9194
9195         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9196         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9197         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9198         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9199         GET_REG32_1(SNDDATAC_MODE);
9200         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9201         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9202         GET_REG32_1(SNDBDC_MODE);
9203         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9204         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9205         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9206         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9207         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9208         GET_REG32_1(RCVDCC_MODE);
9209         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9210         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9211         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9212         GET_REG32_1(MBFREE_MODE);
9213         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9214         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9215         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9216         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9217         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9218         GET_REG32_1(RX_CPU_MODE);
9219         GET_REG32_1(RX_CPU_STATE);
9220         GET_REG32_1(RX_CPU_PGMCTR);
9221         GET_REG32_1(RX_CPU_HWBKPT);
9222         GET_REG32_1(TX_CPU_MODE);
9223         GET_REG32_1(TX_CPU_STATE);
9224         GET_REG32_1(TX_CPU_PGMCTR);
9225         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9226         GET_REG32_LOOP(FTQ_RESET, 0x120);
9227         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9228         GET_REG32_1(DMAC_MODE);
9229         GET_REG32_LOOP(GRC_MODE, 0x4c);
9230         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9231                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9232
9233 #undef __GET_REG32
9234 #undef GET_REG32_LOOP
9235 #undef GET_REG32_1
9236
9237         tg3_full_unlock(tp);
9238 }
9239
9240 static int tg3_get_eeprom_len(struct net_device *dev)
9241 {
9242         struct tg3 *tp = netdev_priv(dev);
9243
9244         return tp->nvram_size;
9245 }
9246
9247 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9248 {
9249         struct tg3 *tp = netdev_priv(dev);
9250         int ret;
9251         u8  *pd;
9252         u32 i, offset, len, b_offset, b_count;
9253         __be32 val;
9254
9255         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9256                 return -EINVAL;
9257
9258         if (tp->link_config.phy_is_low_power)
9259                 return -EAGAIN;
9260
9261         offset = eeprom->offset;
9262         len = eeprom->len;
9263         eeprom->len = 0;
9264
9265         eeprom->magic = TG3_EEPROM_MAGIC;
9266
9267         if (offset & 3) {
9268                 /* adjustments to start on required 4 byte boundary */
9269                 b_offset = offset & 3;
9270                 b_count = 4 - b_offset;
9271                 if (b_count > len) {
9272                         /* i.e. offset=1 len=2 */
9273                         b_count = len;
9274                 }
9275                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9276                 if (ret)
9277                         return ret;
9278                 memcpy(data, ((char*)&val) + b_offset, b_count);
9279                 len -= b_count;
9280                 offset += b_count;
9281                 eeprom->len += b_count;
9282         }
9283
9284         /* read bytes upto the last 4 byte boundary */
9285         pd = &data[eeprom->len];
9286         for (i = 0; i < (len - (len & 3)); i += 4) {
9287                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9288                 if (ret) {
9289                         eeprom->len += i;
9290                         return ret;
9291                 }
9292                 memcpy(pd + i, &val, 4);
9293         }
9294         eeprom->len += i;
9295
9296         if (len & 3) {
9297                 /* read last bytes not ending on 4 byte boundary */
9298                 pd = &data[eeprom->len];
9299                 b_count = len & 3;
9300                 b_offset = offset + len - b_count;
9301                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9302                 if (ret)
9303                         return ret;
9304                 memcpy(pd, &val, b_count);
9305                 eeprom->len += b_count;
9306         }
9307         return 0;
9308 }
9309
9310 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9311
9312 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9313 {
9314         struct tg3 *tp = netdev_priv(dev);
9315         int ret;
9316         u32 offset, len, b_offset, odd_len;
9317         u8 *buf;
9318         __be32 start, end;
9319
9320         if (tp->link_config.phy_is_low_power)
9321                 return -EAGAIN;
9322
9323         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9324             eeprom->magic != TG3_EEPROM_MAGIC)
9325                 return -EINVAL;
9326
9327         offset = eeprom->offset;
9328         len = eeprom->len;
9329
9330         if ((b_offset = (offset & 3))) {
9331                 /* adjustments to start on required 4 byte boundary */
9332                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9333                 if (ret)
9334                         return ret;
9335                 len += b_offset;
9336                 offset &= ~3;
9337                 if (len < 4)
9338                         len = 4;
9339         }
9340
9341         odd_len = 0;
9342         if (len & 3) {
9343                 /* adjustments to end on required 4 byte boundary */
9344                 odd_len = 1;
9345                 len = (len + 3) & ~3;
9346                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9347                 if (ret)
9348                         return ret;
9349         }
9350
9351         buf = data;
9352         if (b_offset || odd_len) {
9353                 buf = kmalloc(len, GFP_KERNEL);
9354                 if (!buf)
9355                         return -ENOMEM;
9356                 if (b_offset)
9357                         memcpy(buf, &start, 4);
9358                 if (odd_len)
9359                         memcpy(buf+len-4, &end, 4);
9360                 memcpy(buf + b_offset, data, eeprom->len);
9361         }
9362
9363         ret = tg3_nvram_write_block(tp, offset, len, buf);
9364
9365         if (buf != data)
9366                 kfree(buf);
9367
9368         return ret;
9369 }
9370
9371 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9372 {
9373         struct tg3 *tp = netdev_priv(dev);
9374
9375         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9376                 struct phy_device *phydev;
9377                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9378                         return -EAGAIN;
9379                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9380                 return phy_ethtool_gset(phydev, cmd);
9381         }
9382
9383         cmd->supported = (SUPPORTED_Autoneg);
9384
9385         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9386                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9387                                    SUPPORTED_1000baseT_Full);
9388
9389         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9390                 cmd->supported |= (SUPPORTED_100baseT_Half |
9391                                   SUPPORTED_100baseT_Full |
9392                                   SUPPORTED_10baseT_Half |
9393                                   SUPPORTED_10baseT_Full |
9394                                   SUPPORTED_TP);
9395                 cmd->port = PORT_TP;
9396         } else {
9397                 cmd->supported |= SUPPORTED_FIBRE;
9398                 cmd->port = PORT_FIBRE;
9399         }
9400
9401         cmd->advertising = tp->link_config.advertising;
9402         if (netif_running(dev)) {
9403                 cmd->speed = tp->link_config.active_speed;
9404                 cmd->duplex = tp->link_config.active_duplex;
9405         }
9406         cmd->phy_address = tp->phy_addr;
9407         cmd->transceiver = XCVR_INTERNAL;
9408         cmd->autoneg = tp->link_config.autoneg;
9409         cmd->maxtxpkt = 0;
9410         cmd->maxrxpkt = 0;
9411         return 0;
9412 }
9413
9414 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9415 {
9416         struct tg3 *tp = netdev_priv(dev);
9417
9418         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9419                 struct phy_device *phydev;
9420                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9421                         return -EAGAIN;
9422                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9423                 return phy_ethtool_sset(phydev, cmd);
9424         }
9425
9426         if (cmd->autoneg != AUTONEG_ENABLE &&
9427             cmd->autoneg != AUTONEG_DISABLE)
9428                 return -EINVAL;
9429
9430         if (cmd->autoneg == AUTONEG_DISABLE &&
9431             cmd->duplex != DUPLEX_FULL &&
9432             cmd->duplex != DUPLEX_HALF)
9433                 return -EINVAL;
9434
9435         if (cmd->autoneg == AUTONEG_ENABLE) {
9436                 u32 mask = ADVERTISED_Autoneg |
9437                            ADVERTISED_Pause |
9438                            ADVERTISED_Asym_Pause;
9439
9440                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9441                         mask |= ADVERTISED_1000baseT_Half |
9442                                 ADVERTISED_1000baseT_Full;
9443
9444                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9445                         mask |= ADVERTISED_100baseT_Half |
9446                                 ADVERTISED_100baseT_Full |
9447                                 ADVERTISED_10baseT_Half |
9448                                 ADVERTISED_10baseT_Full |
9449                                 ADVERTISED_TP;
9450                 else
9451                         mask |= ADVERTISED_FIBRE;
9452
9453                 if (cmd->advertising & ~mask)
9454                         return -EINVAL;
9455
9456                 mask &= (ADVERTISED_1000baseT_Half |
9457                          ADVERTISED_1000baseT_Full |
9458                          ADVERTISED_100baseT_Half |
9459                          ADVERTISED_100baseT_Full |
9460                          ADVERTISED_10baseT_Half |
9461                          ADVERTISED_10baseT_Full);
9462
9463                 cmd->advertising &= mask;
9464         } else {
9465                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9466                         if (cmd->speed != SPEED_1000)
9467                                 return -EINVAL;
9468
9469                         if (cmd->duplex != DUPLEX_FULL)
9470                                 return -EINVAL;
9471                 } else {
9472                         if (cmd->speed != SPEED_100 &&
9473                             cmd->speed != SPEED_10)
9474                                 return -EINVAL;
9475                 }
9476         }
9477
9478         tg3_full_lock(tp, 0);
9479
9480         tp->link_config.autoneg = cmd->autoneg;
9481         if (cmd->autoneg == AUTONEG_ENABLE) {
9482                 tp->link_config.advertising = (cmd->advertising |
9483                                               ADVERTISED_Autoneg);
9484                 tp->link_config.speed = SPEED_INVALID;
9485                 tp->link_config.duplex = DUPLEX_INVALID;
9486         } else {
9487                 tp->link_config.advertising = 0;
9488                 tp->link_config.speed = cmd->speed;
9489                 tp->link_config.duplex = cmd->duplex;
9490         }
9491
9492         tp->link_config.orig_speed = tp->link_config.speed;
9493         tp->link_config.orig_duplex = tp->link_config.duplex;
9494         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9495
9496         if (netif_running(dev))
9497                 tg3_setup_phy(tp, 1);
9498
9499         tg3_full_unlock(tp);
9500
9501         return 0;
9502 }
9503
9504 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9505 {
9506         struct tg3 *tp = netdev_priv(dev);
9507
9508         strcpy(info->driver, DRV_MODULE_NAME);
9509         strcpy(info->version, DRV_MODULE_VERSION);
9510         strcpy(info->fw_version, tp->fw_ver);
9511         strcpy(info->bus_info, pci_name(tp->pdev));
9512 }
9513
9514 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9515 {
9516         struct tg3 *tp = netdev_priv(dev);
9517
9518         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9519             device_can_wakeup(&tp->pdev->dev))
9520                 wol->supported = WAKE_MAGIC;
9521         else
9522                 wol->supported = 0;
9523         wol->wolopts = 0;
9524         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9525             device_can_wakeup(&tp->pdev->dev))
9526                 wol->wolopts = WAKE_MAGIC;
9527         memset(&wol->sopass, 0, sizeof(wol->sopass));
9528 }
9529
9530 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9531 {
9532         struct tg3 *tp = netdev_priv(dev);
9533         struct device *dp = &tp->pdev->dev;
9534
9535         if (wol->wolopts & ~WAKE_MAGIC)
9536                 return -EINVAL;
9537         if ((wol->wolopts & WAKE_MAGIC) &&
9538             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9539                 return -EINVAL;
9540
9541         spin_lock_bh(&tp->lock);
9542         if (wol->wolopts & WAKE_MAGIC) {
9543                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9544                 device_set_wakeup_enable(dp, true);
9545         } else {
9546                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9547                 device_set_wakeup_enable(dp, false);
9548         }
9549         spin_unlock_bh(&tp->lock);
9550
9551         return 0;
9552 }
9553
9554 static u32 tg3_get_msglevel(struct net_device *dev)
9555 {
9556         struct tg3 *tp = netdev_priv(dev);
9557         return tp->msg_enable;
9558 }
9559
9560 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9561 {
9562         struct tg3 *tp = netdev_priv(dev);
9563         tp->msg_enable = value;
9564 }
9565
9566 static int tg3_set_tso(struct net_device *dev, u32 value)
9567 {
9568         struct tg3 *tp = netdev_priv(dev);
9569
9570         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9571                 if (value)
9572                         return -EINVAL;
9573                 return 0;
9574         }
9575         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9576             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9577              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9578                 if (value) {
9579                         dev->features |= NETIF_F_TSO6;
9580                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9581                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9582                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9583                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9584                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9585                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9586                                 dev->features |= NETIF_F_TSO_ECN;
9587                 } else
9588                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9589         }
9590         return ethtool_op_set_tso(dev, value);
9591 }
9592
9593 static int tg3_nway_reset(struct net_device *dev)
9594 {
9595         struct tg3 *tp = netdev_priv(dev);
9596         int r;
9597
9598         if (!netif_running(dev))
9599                 return -EAGAIN;
9600
9601         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9602                 return -EINVAL;
9603
9604         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9605                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9606                         return -EAGAIN;
9607                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9608         } else {
9609                 u32 bmcr;
9610
9611                 spin_lock_bh(&tp->lock);
9612                 r = -EINVAL;
9613                 tg3_readphy(tp, MII_BMCR, &bmcr);
9614                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9615                     ((bmcr & BMCR_ANENABLE) ||
9616                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9617                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9618                                                    BMCR_ANENABLE);
9619                         r = 0;
9620                 }
9621                 spin_unlock_bh(&tp->lock);
9622         }
9623
9624         return r;
9625 }
9626
9627 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9628 {
9629         struct tg3 *tp = netdev_priv(dev);
9630
9631         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9632         ering->rx_mini_max_pending = 0;
9633         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9634                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9635         else
9636                 ering->rx_jumbo_max_pending = 0;
9637
9638         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9639
9640         ering->rx_pending = tp->rx_pending;
9641         ering->rx_mini_pending = 0;
9642         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9643                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9644         else
9645                 ering->rx_jumbo_pending = 0;
9646
9647         ering->tx_pending = tp->napi[0].tx_pending;
9648 }
9649
9650 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9651 {
9652         struct tg3 *tp = netdev_priv(dev);
9653         int i, irq_sync = 0, err = 0;
9654
9655         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9656             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9657             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9658             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9659             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9660              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9661                 return -EINVAL;
9662
9663         if (netif_running(dev)) {
9664                 tg3_phy_stop(tp);
9665                 tg3_netif_stop(tp);
9666                 irq_sync = 1;
9667         }
9668
9669         tg3_full_lock(tp, irq_sync);
9670
9671         tp->rx_pending = ering->rx_pending;
9672
9673         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9674             tp->rx_pending > 63)
9675                 tp->rx_pending = 63;
9676         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9677
9678         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9679                 tp->napi[i].tx_pending = ering->tx_pending;
9680
9681         if (netif_running(dev)) {
9682                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9683                 err = tg3_restart_hw(tp, 1);
9684                 if (!err)
9685                         tg3_netif_start(tp);
9686         }
9687
9688         tg3_full_unlock(tp);
9689
9690         if (irq_sync && !err)
9691                 tg3_phy_start(tp);
9692
9693         return err;
9694 }
9695
9696 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9697 {
9698         struct tg3 *tp = netdev_priv(dev);
9699
9700         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9701
9702         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9703                 epause->rx_pause = 1;
9704         else
9705                 epause->rx_pause = 0;
9706
9707         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9708                 epause->tx_pause = 1;
9709         else
9710                 epause->tx_pause = 0;
9711 }
9712
9713 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9714 {
9715         struct tg3 *tp = netdev_priv(dev);
9716         int err = 0;
9717
9718         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9719                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9720                         return -EAGAIN;
9721
9722                 if (epause->autoneg) {
9723                         u32 newadv;
9724                         struct phy_device *phydev;
9725
9726                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9727
9728                         if (epause->rx_pause) {
9729                                 if (epause->tx_pause)
9730                                         newadv = ADVERTISED_Pause;
9731                                 else
9732                                         newadv = ADVERTISED_Pause |
9733                                                  ADVERTISED_Asym_Pause;
9734                         } else if (epause->tx_pause) {
9735                                 newadv = ADVERTISED_Asym_Pause;
9736                         } else
9737                                 newadv = 0;
9738
9739                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9740                                 u32 oldadv = phydev->advertising &
9741                                              (ADVERTISED_Pause |
9742                                               ADVERTISED_Asym_Pause);
9743                                 if (oldadv != newadv) {
9744                                         phydev->advertising &=
9745                                                 ~(ADVERTISED_Pause |
9746                                                   ADVERTISED_Asym_Pause);
9747                                         phydev->advertising |= newadv;
9748                                         err = phy_start_aneg(phydev);
9749                                 }
9750                         } else {
9751                                 tp->link_config.advertising &=
9752                                                 ~(ADVERTISED_Pause |
9753                                                   ADVERTISED_Asym_Pause);
9754                                 tp->link_config.advertising |= newadv;
9755                         }
9756                 } else {
9757                         if (epause->rx_pause)
9758                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9759                         else
9760                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9761
9762                         if (epause->tx_pause)
9763                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9764                         else
9765                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9766
9767                         if (netif_running(dev))
9768                                 tg3_setup_flow_control(tp, 0, 0);
9769                 }
9770         } else {
9771                 int irq_sync = 0;
9772
9773                 if (netif_running(dev)) {
9774                         tg3_netif_stop(tp);
9775                         irq_sync = 1;
9776                 }
9777
9778                 tg3_full_lock(tp, irq_sync);
9779
9780                 if (epause->autoneg)
9781                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9782                 else
9783                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9784                 if (epause->rx_pause)
9785                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9786                 else
9787                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9788                 if (epause->tx_pause)
9789                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9790                 else
9791                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9792
9793                 if (netif_running(dev)) {
9794                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9795                         err = tg3_restart_hw(tp, 1);
9796                         if (!err)
9797                                 tg3_netif_start(tp);
9798                 }
9799
9800                 tg3_full_unlock(tp);
9801         }
9802
9803         return err;
9804 }
9805
9806 static u32 tg3_get_rx_csum(struct net_device *dev)
9807 {
9808         struct tg3 *tp = netdev_priv(dev);
9809         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9810 }
9811
9812 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9813 {
9814         struct tg3 *tp = netdev_priv(dev);
9815
9816         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9817                 if (data != 0)
9818                         return -EINVAL;
9819                 return 0;
9820         }
9821
9822         spin_lock_bh(&tp->lock);
9823         if (data)
9824                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9825         else
9826                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9827         spin_unlock_bh(&tp->lock);
9828
9829         return 0;
9830 }
9831
9832 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9833 {
9834         struct tg3 *tp = netdev_priv(dev);
9835
9836         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9837                 if (data != 0)
9838                         return -EINVAL;
9839                 return 0;
9840         }
9841
9842         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9843                 ethtool_op_set_tx_ipv6_csum(dev, data);
9844         else
9845                 ethtool_op_set_tx_csum(dev, data);
9846
9847         return 0;
9848 }
9849
9850 static int tg3_get_sset_count (struct net_device *dev, int sset)
9851 {
9852         switch (sset) {
9853         case ETH_SS_TEST:
9854                 return TG3_NUM_TEST;
9855         case ETH_SS_STATS:
9856                 return TG3_NUM_STATS;
9857         default:
9858                 return -EOPNOTSUPP;
9859         }
9860 }
9861
9862 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9863 {
9864         switch (stringset) {
9865         case ETH_SS_STATS:
9866                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9867                 break;
9868         case ETH_SS_TEST:
9869                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9870                 break;
9871         default:
9872                 WARN_ON(1);     /* we need a WARN() */
9873                 break;
9874         }
9875 }
9876
9877 static int tg3_phys_id(struct net_device *dev, u32 data)
9878 {
9879         struct tg3 *tp = netdev_priv(dev);
9880         int i;
9881
9882         if (!netif_running(tp->dev))
9883                 return -EAGAIN;
9884
9885         if (data == 0)
9886                 data = UINT_MAX / 2;
9887
9888         for (i = 0; i < (data * 2); i++) {
9889                 if ((i % 2) == 0)
9890                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9891                                            LED_CTRL_1000MBPS_ON |
9892                                            LED_CTRL_100MBPS_ON |
9893                                            LED_CTRL_10MBPS_ON |
9894                                            LED_CTRL_TRAFFIC_OVERRIDE |
9895                                            LED_CTRL_TRAFFIC_BLINK |
9896                                            LED_CTRL_TRAFFIC_LED);
9897
9898                 else
9899                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9900                                            LED_CTRL_TRAFFIC_OVERRIDE);
9901
9902                 if (msleep_interruptible(500))
9903                         break;
9904         }
9905         tw32(MAC_LED_CTRL, tp->led_ctrl);
9906         return 0;
9907 }
9908
9909 static void tg3_get_ethtool_stats (struct net_device *dev,
9910                                    struct ethtool_stats *estats, u64 *tmp_stats)
9911 {
9912         struct tg3 *tp = netdev_priv(dev);
9913         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9914 }
9915
9916 #define NVRAM_TEST_SIZE 0x100
9917 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9918 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9919 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9920 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9921 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9922
9923 static int tg3_test_nvram(struct tg3 *tp)
9924 {
9925         u32 csum, magic;
9926         __be32 *buf;
9927         int i, j, k, err = 0, size;
9928
9929         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9930                 return 0;
9931
9932         if (tg3_nvram_read(tp, 0, &magic) != 0)
9933                 return -EIO;
9934
9935         if (magic == TG3_EEPROM_MAGIC)
9936                 size = NVRAM_TEST_SIZE;
9937         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9938                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9939                     TG3_EEPROM_SB_FORMAT_1) {
9940                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9941                         case TG3_EEPROM_SB_REVISION_0:
9942                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9943                                 break;
9944                         case TG3_EEPROM_SB_REVISION_2:
9945                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9946                                 break;
9947                         case TG3_EEPROM_SB_REVISION_3:
9948                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9949                                 break;
9950                         default:
9951                                 return 0;
9952                         }
9953                 } else
9954                         return 0;
9955         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9956                 size = NVRAM_SELFBOOT_HW_SIZE;
9957         else
9958                 return -EIO;
9959
9960         buf = kmalloc(size, GFP_KERNEL);
9961         if (buf == NULL)
9962                 return -ENOMEM;
9963
9964         err = -EIO;
9965         for (i = 0, j = 0; i < size; i += 4, j++) {
9966                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9967                 if (err)
9968                         break;
9969         }
9970         if (i < size)
9971                 goto out;
9972
9973         /* Selfboot format */
9974         magic = be32_to_cpu(buf[0]);
9975         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9976             TG3_EEPROM_MAGIC_FW) {
9977                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9978
9979                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9980                     TG3_EEPROM_SB_REVISION_2) {
9981                         /* For rev 2, the csum doesn't include the MBA. */
9982                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9983                                 csum8 += buf8[i];
9984                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9985                                 csum8 += buf8[i];
9986                 } else {
9987                         for (i = 0; i < size; i++)
9988                                 csum8 += buf8[i];
9989                 }
9990
9991                 if (csum8 == 0) {
9992                         err = 0;
9993                         goto out;
9994                 }
9995
9996                 err = -EIO;
9997                 goto out;
9998         }
9999
10000         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10001             TG3_EEPROM_MAGIC_HW) {
10002                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10003                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10004                 u8 *buf8 = (u8 *) buf;
10005
10006                 /* Separate the parity bits and the data bytes.  */
10007                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10008                         if ((i == 0) || (i == 8)) {
10009                                 int l;
10010                                 u8 msk;
10011
10012                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10013                                         parity[k++] = buf8[i] & msk;
10014                                 i++;
10015                         }
10016                         else if (i == 16) {
10017                                 int l;
10018                                 u8 msk;
10019
10020                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10021                                         parity[k++] = buf8[i] & msk;
10022                                 i++;
10023
10024                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10025                                         parity[k++] = buf8[i] & msk;
10026                                 i++;
10027                         }
10028                         data[j++] = buf8[i];
10029                 }
10030
10031                 err = -EIO;
10032                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10033                         u8 hw8 = hweight8(data[i]);
10034
10035                         if ((hw8 & 0x1) && parity[i])
10036                                 goto out;
10037                         else if (!(hw8 & 0x1) && !parity[i])
10038                                 goto out;
10039                 }
10040                 err = 0;
10041                 goto out;
10042         }
10043
10044         /* Bootstrap checksum at offset 0x10 */
10045         csum = calc_crc((unsigned char *) buf, 0x10);
10046         if (csum != be32_to_cpu(buf[0x10/4]))
10047                 goto out;
10048
10049         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10050         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10051         if (csum != be32_to_cpu(buf[0xfc/4]))
10052                 goto out;
10053
10054         err = 0;
10055
10056 out:
10057         kfree(buf);
10058         return err;
10059 }
10060
10061 #define TG3_SERDES_TIMEOUT_SEC  2
10062 #define TG3_COPPER_TIMEOUT_SEC  6
10063
10064 static int tg3_test_link(struct tg3 *tp)
10065 {
10066         int i, max;
10067
10068         if (!netif_running(tp->dev))
10069                 return -ENODEV;
10070
10071         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10072                 max = TG3_SERDES_TIMEOUT_SEC;
10073         else
10074                 max = TG3_COPPER_TIMEOUT_SEC;
10075
10076         for (i = 0; i < max; i++) {
10077                 if (netif_carrier_ok(tp->dev))
10078                         return 0;
10079
10080                 if (msleep_interruptible(1000))
10081                         break;
10082         }
10083
10084         return -EIO;
10085 }
10086
10087 /* Only test the commonly used registers */
10088 static int tg3_test_registers(struct tg3 *tp)
10089 {
10090         int i, is_5705, is_5750;
10091         u32 offset, read_mask, write_mask, val, save_val, read_val;
10092         static struct {
10093                 u16 offset;
10094                 u16 flags;
10095 #define TG3_FL_5705     0x1
10096 #define TG3_FL_NOT_5705 0x2
10097 #define TG3_FL_NOT_5788 0x4
10098 #define TG3_FL_NOT_5750 0x8
10099                 u32 read_mask;
10100                 u32 write_mask;
10101         } reg_tbl[] = {
10102                 /* MAC Control Registers */
10103                 { MAC_MODE, TG3_FL_NOT_5705,
10104                         0x00000000, 0x00ef6f8c },
10105                 { MAC_MODE, TG3_FL_5705,
10106                         0x00000000, 0x01ef6b8c },
10107                 { MAC_STATUS, TG3_FL_NOT_5705,
10108                         0x03800107, 0x00000000 },
10109                 { MAC_STATUS, TG3_FL_5705,
10110                         0x03800100, 0x00000000 },
10111                 { MAC_ADDR_0_HIGH, 0x0000,
10112                         0x00000000, 0x0000ffff },
10113                 { MAC_ADDR_0_LOW, 0x0000,
10114                         0x00000000, 0xffffffff },
10115                 { MAC_RX_MTU_SIZE, 0x0000,
10116                         0x00000000, 0x0000ffff },
10117                 { MAC_TX_MODE, 0x0000,
10118                         0x00000000, 0x00000070 },
10119                 { MAC_TX_LENGTHS, 0x0000,
10120                         0x00000000, 0x00003fff },
10121                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10122                         0x00000000, 0x000007fc },
10123                 { MAC_RX_MODE, TG3_FL_5705,
10124                         0x00000000, 0x000007dc },
10125                 { MAC_HASH_REG_0, 0x0000,
10126                         0x00000000, 0xffffffff },
10127                 { MAC_HASH_REG_1, 0x0000,
10128                         0x00000000, 0xffffffff },
10129                 { MAC_HASH_REG_2, 0x0000,
10130                         0x00000000, 0xffffffff },
10131                 { MAC_HASH_REG_3, 0x0000,
10132                         0x00000000, 0xffffffff },
10133
10134                 /* Receive Data and Receive BD Initiator Control Registers. */
10135                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10136                         0x00000000, 0xffffffff },
10137                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10138                         0x00000000, 0xffffffff },
10139                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10140                         0x00000000, 0x00000003 },
10141                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10142                         0x00000000, 0xffffffff },
10143                 { RCVDBDI_STD_BD+0, 0x0000,
10144                         0x00000000, 0xffffffff },
10145                 { RCVDBDI_STD_BD+4, 0x0000,
10146                         0x00000000, 0xffffffff },
10147                 { RCVDBDI_STD_BD+8, 0x0000,
10148                         0x00000000, 0xffff0002 },
10149                 { RCVDBDI_STD_BD+0xc, 0x0000,
10150                         0x00000000, 0xffffffff },
10151
10152                 /* Receive BD Initiator Control Registers. */
10153                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10154                         0x00000000, 0xffffffff },
10155                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10156                         0x00000000, 0x000003ff },
10157                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10158                         0x00000000, 0xffffffff },
10159
10160                 /* Host Coalescing Control Registers. */
10161                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10162                         0x00000000, 0x00000004 },
10163                 { HOSTCC_MODE, TG3_FL_5705,
10164                         0x00000000, 0x000000f6 },
10165                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10166                         0x00000000, 0xffffffff },
10167                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10168                         0x00000000, 0x000003ff },
10169                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10170                         0x00000000, 0xffffffff },
10171                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10172                         0x00000000, 0x000003ff },
10173                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10174                         0x00000000, 0xffffffff },
10175                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10176                         0x00000000, 0x000000ff },
10177                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10178                         0x00000000, 0xffffffff },
10179                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10180                         0x00000000, 0x000000ff },
10181                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10182                         0x00000000, 0xffffffff },
10183                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10184                         0x00000000, 0xffffffff },
10185                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10186                         0x00000000, 0xffffffff },
10187                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10188                         0x00000000, 0x000000ff },
10189                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10190                         0x00000000, 0xffffffff },
10191                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10192                         0x00000000, 0x000000ff },
10193                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10194                         0x00000000, 0xffffffff },
10195                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10196                         0x00000000, 0xffffffff },
10197                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10198                         0x00000000, 0xffffffff },
10199                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10200                         0x00000000, 0xffffffff },
10201                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10202                         0x00000000, 0xffffffff },
10203                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10204                         0xffffffff, 0x00000000 },
10205                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10206                         0xffffffff, 0x00000000 },
10207
10208                 /* Buffer Manager Control Registers. */
10209                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10210                         0x00000000, 0x007fff80 },
10211                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10212                         0x00000000, 0x007fffff },
10213                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10214                         0x00000000, 0x0000003f },
10215                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10216                         0x00000000, 0x000001ff },
10217                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10218                         0x00000000, 0x000001ff },
10219                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10220                         0xffffffff, 0x00000000 },
10221                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10222                         0xffffffff, 0x00000000 },
10223
10224                 /* Mailbox Registers */
10225                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10226                         0x00000000, 0x000001ff },
10227                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10228                         0x00000000, 0x000001ff },
10229                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10230                         0x00000000, 0x000007ff },
10231                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10232                         0x00000000, 0x000001ff },
10233
10234                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10235         };
10236
10237         is_5705 = is_5750 = 0;
10238         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10239                 is_5705 = 1;
10240                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10241                         is_5750 = 1;
10242         }
10243
10244         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10245                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10246                         continue;
10247
10248                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10249                         continue;
10250
10251                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10252                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10253                         continue;
10254
10255                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10256                         continue;
10257
10258                 offset = (u32) reg_tbl[i].offset;
10259                 read_mask = reg_tbl[i].read_mask;
10260                 write_mask = reg_tbl[i].write_mask;
10261
10262                 /* Save the original register content */
10263                 save_val = tr32(offset);
10264
10265                 /* Determine the read-only value. */
10266                 read_val = save_val & read_mask;
10267
10268                 /* Write zero to the register, then make sure the read-only bits
10269                  * are not changed and the read/write bits are all zeros.
10270                  */
10271                 tw32(offset, 0);
10272
10273                 val = tr32(offset);
10274
10275                 /* Test the read-only and read/write bits. */
10276                 if (((val & read_mask) != read_val) || (val & write_mask))
10277                         goto out;
10278
10279                 /* Write ones to all the bits defined by RdMask and WrMask, then
10280                  * make sure the read-only bits are not changed and the
10281                  * read/write bits are all ones.
10282                  */
10283                 tw32(offset, read_mask | write_mask);
10284
10285                 val = tr32(offset);
10286
10287                 /* Test the read-only bits. */
10288                 if ((val & read_mask) != read_val)
10289                         goto out;
10290
10291                 /* Test the read/write bits. */
10292                 if ((val & write_mask) != write_mask)
10293                         goto out;
10294
10295                 tw32(offset, save_val);
10296         }
10297
10298         return 0;
10299
10300 out:
10301         if (netif_msg_hw(tp))
10302                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10303                        offset);
10304         tw32(offset, save_val);
10305         return -EIO;
10306 }
10307
10308 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10309 {
10310         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10311         int i;
10312         u32 j;
10313
10314         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10315                 for (j = 0; j < len; j += 4) {
10316                         u32 val;
10317
10318                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10319                         tg3_read_mem(tp, offset + j, &val);
10320                         if (val != test_pattern[i])
10321                                 return -EIO;
10322                 }
10323         }
10324         return 0;
10325 }
10326
10327 static int tg3_test_memory(struct tg3 *tp)
10328 {
10329         static struct mem_entry {
10330                 u32 offset;
10331                 u32 len;
10332         } mem_tbl_570x[] = {
10333                 { 0x00000000, 0x00b50},
10334                 { 0x00002000, 0x1c000},
10335                 { 0xffffffff, 0x00000}
10336         }, mem_tbl_5705[] = {
10337                 { 0x00000100, 0x0000c},
10338                 { 0x00000200, 0x00008},
10339                 { 0x00004000, 0x00800},
10340                 { 0x00006000, 0x01000},
10341                 { 0x00008000, 0x02000},
10342                 { 0x00010000, 0x0e000},
10343                 { 0xffffffff, 0x00000}
10344         }, mem_tbl_5755[] = {
10345                 { 0x00000200, 0x00008},
10346                 { 0x00004000, 0x00800},
10347                 { 0x00006000, 0x00800},
10348                 { 0x00008000, 0x02000},
10349                 { 0x00010000, 0x0c000},
10350                 { 0xffffffff, 0x00000}
10351         }, mem_tbl_5906[] = {
10352                 { 0x00000200, 0x00008},
10353                 { 0x00004000, 0x00400},
10354                 { 0x00006000, 0x00400},
10355                 { 0x00008000, 0x01000},
10356                 { 0x00010000, 0x01000},
10357                 { 0xffffffff, 0x00000}
10358         };
10359         struct mem_entry *mem_tbl;
10360         int err = 0;
10361         int i;
10362
10363         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10364                 mem_tbl = mem_tbl_5755;
10365         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10366                 mem_tbl = mem_tbl_5906;
10367         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10368                 mem_tbl = mem_tbl_5705;
10369         else
10370                 mem_tbl = mem_tbl_570x;
10371
10372         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10373                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10374                     mem_tbl[i].len)) != 0)
10375                         break;
10376         }
10377
10378         return err;
10379 }
10380
10381 #define TG3_MAC_LOOPBACK        0
10382 #define TG3_PHY_LOOPBACK        1
10383
10384 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10385 {
10386         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10387         u32 desc_idx, coal_now;
10388         struct sk_buff *skb, *rx_skb;
10389         u8 *tx_data;
10390         dma_addr_t map;
10391         int num_pkts, tx_len, rx_len, i, err;
10392         struct tg3_rx_buffer_desc *desc;
10393         struct tg3_napi *tnapi, *rnapi;
10394         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10395
10396         if (tp->irq_cnt > 1) {
10397                 tnapi = &tp->napi[1];
10398                 rnapi = &tp->napi[1];
10399         } else {
10400                 tnapi = &tp->napi[0];
10401                 rnapi = &tp->napi[0];
10402         }
10403         coal_now = tnapi->coal_now | rnapi->coal_now;
10404
10405         if (loopback_mode == TG3_MAC_LOOPBACK) {
10406                 /* HW errata - mac loopback fails in some cases on 5780.
10407                  * Normal traffic and PHY loopback are not affected by
10408                  * errata.
10409                  */
10410                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10411                         return 0;
10412
10413                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10414                            MAC_MODE_PORT_INT_LPBACK;
10415                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10416                         mac_mode |= MAC_MODE_LINK_POLARITY;
10417                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10418                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10419                 else
10420                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10421                 tw32(MAC_MODE, mac_mode);
10422         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10423                 u32 val;
10424
10425                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10426                         tg3_phy_fet_toggle_apd(tp, false);
10427                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10428                 } else
10429                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10430
10431                 tg3_phy_toggle_automdix(tp, 0);
10432
10433                 tg3_writephy(tp, MII_BMCR, val);
10434                 udelay(40);
10435
10436                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10437                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10438                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10439                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10440                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10441                 } else
10442                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10443
10444                 /* reset to prevent losing 1st rx packet intermittently */
10445                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10446                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10447                         udelay(10);
10448                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10449                 }
10450                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10451                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10452                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10453                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10454                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10455                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10456                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10457                 }
10458                 tw32(MAC_MODE, mac_mode);
10459         }
10460         else
10461                 return -EINVAL;
10462
10463         err = -EIO;
10464
10465         tx_len = 1514;
10466         skb = netdev_alloc_skb(tp->dev, tx_len);
10467         if (!skb)
10468                 return -ENOMEM;
10469
10470         tx_data = skb_put(skb, tx_len);
10471         memcpy(tx_data, tp->dev->dev_addr, 6);
10472         memset(tx_data + 6, 0x0, 8);
10473
10474         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10475
10476         for (i = 14; i < tx_len; i++)
10477                 tx_data[i] = (u8) (i & 0xff);
10478
10479         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10480                 dev_kfree_skb(skb);
10481                 return -EIO;
10482         }
10483
10484         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10485                rnapi->coal_now);
10486
10487         udelay(10);
10488
10489         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10490
10491         num_pkts = 0;
10492
10493         tg3_set_txd(tnapi, tnapi->tx_prod,
10494                     skb_shinfo(skb)->dma_head, tx_len, 0, 1);
10495
10496         tnapi->tx_prod++;
10497         num_pkts++;
10498
10499         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10500         tr32_mailbox(tnapi->prodmbox);
10501
10502         udelay(10);
10503
10504         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10505         for (i = 0; i < 35; i++) {
10506                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10507                        coal_now);
10508
10509                 udelay(10);
10510
10511                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10512                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10513                 if ((tx_idx == tnapi->tx_prod) &&
10514                     (rx_idx == (rx_start_idx + num_pkts)))
10515                         break;
10516         }
10517
10518         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
10519         dev_kfree_skb(skb);
10520
10521         if (tx_idx != tnapi->tx_prod)
10522                 goto out;
10523
10524         if (rx_idx != rx_start_idx + num_pkts)
10525                 goto out;
10526
10527         desc = &rnapi->rx_rcb[rx_start_idx];
10528         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10529         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10530         if (opaque_key != RXD_OPAQUE_RING_STD)
10531                 goto out;
10532
10533         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10534             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10535                 goto out;
10536
10537         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10538         if (rx_len != tx_len)
10539                 goto out;
10540
10541         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10542
10543         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10544         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10545
10546         for (i = 14; i < tx_len; i++) {
10547                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10548                         goto out;
10549         }
10550         err = 0;
10551
10552         /* tg3_free_rings will unmap and free the rx_skb */
10553 out:
10554         return err;
10555 }
10556
10557 #define TG3_MAC_LOOPBACK_FAILED         1
10558 #define TG3_PHY_LOOPBACK_FAILED         2
10559 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10560                                          TG3_PHY_LOOPBACK_FAILED)
10561
10562 static int tg3_test_loopback(struct tg3 *tp)
10563 {
10564         int err = 0;
10565         u32 cpmuctrl = 0;
10566
10567         if (!netif_running(tp->dev))
10568                 return TG3_LOOPBACK_FAILED;
10569
10570         err = tg3_reset_hw(tp, 1);
10571         if (err)
10572                 return TG3_LOOPBACK_FAILED;
10573
10574         /* Turn off gphy autopowerdown. */
10575         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10576                 tg3_phy_toggle_apd(tp, false);
10577
10578         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10579                 int i;
10580                 u32 status;
10581
10582                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10583
10584                 /* Wait for up to 40 microseconds to acquire lock. */
10585                 for (i = 0; i < 4; i++) {
10586                         status = tr32(TG3_CPMU_MUTEX_GNT);
10587                         if (status == CPMU_MUTEX_GNT_DRIVER)
10588                                 break;
10589                         udelay(10);
10590                 }
10591
10592                 if (status != CPMU_MUTEX_GNT_DRIVER)
10593                         return TG3_LOOPBACK_FAILED;
10594
10595                 /* Turn off link-based power management. */
10596                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10597                 tw32(TG3_CPMU_CTRL,
10598                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10599                                   CPMU_CTRL_LINK_AWARE_MODE));
10600         }
10601
10602         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10603                 err |= TG3_MAC_LOOPBACK_FAILED;
10604
10605         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10606                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10607
10608                 /* Release the mutex */
10609                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10610         }
10611
10612         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10613             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10614                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10615                         err |= TG3_PHY_LOOPBACK_FAILED;
10616         }
10617
10618         /* Re-enable gphy autopowerdown. */
10619         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10620                 tg3_phy_toggle_apd(tp, true);
10621
10622         return err;
10623 }
10624
10625 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10626                           u64 *data)
10627 {
10628         struct tg3 *tp = netdev_priv(dev);
10629
10630         if (tp->link_config.phy_is_low_power)
10631                 tg3_set_power_state(tp, PCI_D0);
10632
10633         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10634
10635         if (tg3_test_nvram(tp) != 0) {
10636                 etest->flags |= ETH_TEST_FL_FAILED;
10637                 data[0] = 1;
10638         }
10639         if (tg3_test_link(tp) != 0) {
10640                 etest->flags |= ETH_TEST_FL_FAILED;
10641                 data[1] = 1;
10642         }
10643         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10644                 int err, err2 = 0, irq_sync = 0;
10645
10646                 if (netif_running(dev)) {
10647                         tg3_phy_stop(tp);
10648                         tg3_netif_stop(tp);
10649                         irq_sync = 1;
10650                 }
10651
10652                 tg3_full_lock(tp, irq_sync);
10653
10654                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10655                 err = tg3_nvram_lock(tp);
10656                 tg3_halt_cpu(tp, RX_CPU_BASE);
10657                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10658                         tg3_halt_cpu(tp, TX_CPU_BASE);
10659                 if (!err)
10660                         tg3_nvram_unlock(tp);
10661
10662                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10663                         tg3_phy_reset(tp);
10664
10665                 if (tg3_test_registers(tp) != 0) {
10666                         etest->flags |= ETH_TEST_FL_FAILED;
10667                         data[2] = 1;
10668                 }
10669                 if (tg3_test_memory(tp) != 0) {
10670                         etest->flags |= ETH_TEST_FL_FAILED;
10671                         data[3] = 1;
10672                 }
10673                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10674                         etest->flags |= ETH_TEST_FL_FAILED;
10675
10676                 tg3_full_unlock(tp);
10677
10678                 if (tg3_test_interrupt(tp) != 0) {
10679                         etest->flags |= ETH_TEST_FL_FAILED;
10680                         data[5] = 1;
10681                 }
10682
10683                 tg3_full_lock(tp, 0);
10684
10685                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10686                 if (netif_running(dev)) {
10687                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10688                         err2 = tg3_restart_hw(tp, 1);
10689                         if (!err2)
10690                                 tg3_netif_start(tp);
10691                 }
10692
10693                 tg3_full_unlock(tp);
10694
10695                 if (irq_sync && !err2)
10696                         tg3_phy_start(tp);
10697         }
10698         if (tp->link_config.phy_is_low_power)
10699                 tg3_set_power_state(tp, PCI_D3hot);
10700
10701 }
10702
10703 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10704 {
10705         struct mii_ioctl_data *data = if_mii(ifr);
10706         struct tg3 *tp = netdev_priv(dev);
10707         int err;
10708
10709         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10710                 struct phy_device *phydev;
10711                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10712                         return -EAGAIN;
10713                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10714                 return phy_mii_ioctl(phydev, data, cmd);
10715         }
10716
10717         switch(cmd) {
10718         case SIOCGMIIPHY:
10719                 data->phy_id = tp->phy_addr;
10720
10721                 /* fallthru */
10722         case SIOCGMIIREG: {
10723                 u32 mii_regval;
10724
10725                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10726                         break;                  /* We have no PHY */
10727
10728                 if (tp->link_config.phy_is_low_power)
10729                         return -EAGAIN;
10730
10731                 spin_lock_bh(&tp->lock);
10732                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10733                 spin_unlock_bh(&tp->lock);
10734
10735                 data->val_out = mii_regval;
10736
10737                 return err;
10738         }
10739
10740         case SIOCSMIIREG:
10741                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10742                         break;                  /* We have no PHY */
10743
10744                 if (tp->link_config.phy_is_low_power)
10745                         return -EAGAIN;
10746
10747                 spin_lock_bh(&tp->lock);
10748                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10749                 spin_unlock_bh(&tp->lock);
10750
10751                 return err;
10752
10753         default:
10754                 /* do nothing */
10755                 break;
10756         }
10757         return -EOPNOTSUPP;
10758 }
10759
10760 #if TG3_VLAN_TAG_USED
10761 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10762 {
10763         struct tg3 *tp = netdev_priv(dev);
10764
10765         if (!netif_running(dev)) {
10766                 tp->vlgrp = grp;
10767                 return;
10768         }
10769
10770         tg3_netif_stop(tp);
10771
10772         tg3_full_lock(tp, 0);
10773
10774         tp->vlgrp = grp;
10775
10776         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10777         __tg3_set_rx_mode(dev);
10778
10779         tg3_netif_start(tp);
10780
10781         tg3_full_unlock(tp);
10782 }
10783 #endif
10784
10785 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10786 {
10787         struct tg3 *tp = netdev_priv(dev);
10788
10789         memcpy(ec, &tp->coal, sizeof(*ec));
10790         return 0;
10791 }
10792
10793 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10794 {
10795         struct tg3 *tp = netdev_priv(dev);
10796         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10797         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10798
10799         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10800                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10801                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10802                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10803                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10804         }
10805
10806         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10807             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10808             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10809             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10810             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10811             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10812             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10813             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10814             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10815             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10816                 return -EINVAL;
10817
10818         /* No rx interrupts will be generated if both are zero */
10819         if ((ec->rx_coalesce_usecs == 0) &&
10820             (ec->rx_max_coalesced_frames == 0))
10821                 return -EINVAL;
10822
10823         /* No tx interrupts will be generated if both are zero */
10824         if ((ec->tx_coalesce_usecs == 0) &&
10825             (ec->tx_max_coalesced_frames == 0))
10826                 return -EINVAL;
10827
10828         /* Only copy relevant parameters, ignore all others. */
10829         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10830         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10831         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10832         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10833         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10834         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10835         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10836         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10837         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10838
10839         if (netif_running(dev)) {
10840                 tg3_full_lock(tp, 0);
10841                 __tg3_set_coalesce(tp, &tp->coal);
10842                 tg3_full_unlock(tp);
10843         }
10844         return 0;
10845 }
10846
10847 static const struct ethtool_ops tg3_ethtool_ops = {
10848         .get_settings           = tg3_get_settings,
10849         .set_settings           = tg3_set_settings,
10850         .get_drvinfo            = tg3_get_drvinfo,
10851         .get_regs_len           = tg3_get_regs_len,
10852         .get_regs               = tg3_get_regs,
10853         .get_wol                = tg3_get_wol,
10854         .set_wol                = tg3_set_wol,
10855         .get_msglevel           = tg3_get_msglevel,
10856         .set_msglevel           = tg3_set_msglevel,
10857         .nway_reset             = tg3_nway_reset,
10858         .get_link               = ethtool_op_get_link,
10859         .get_eeprom_len         = tg3_get_eeprom_len,
10860         .get_eeprom             = tg3_get_eeprom,
10861         .set_eeprom             = tg3_set_eeprom,
10862         .get_ringparam          = tg3_get_ringparam,
10863         .set_ringparam          = tg3_set_ringparam,
10864         .get_pauseparam         = tg3_get_pauseparam,
10865         .set_pauseparam         = tg3_set_pauseparam,
10866         .get_rx_csum            = tg3_get_rx_csum,
10867         .set_rx_csum            = tg3_set_rx_csum,
10868         .set_tx_csum            = tg3_set_tx_csum,
10869         .set_sg                 = ethtool_op_set_sg,
10870         .set_tso                = tg3_set_tso,
10871         .self_test              = tg3_self_test,
10872         .get_strings            = tg3_get_strings,
10873         .phys_id                = tg3_phys_id,
10874         .get_ethtool_stats      = tg3_get_ethtool_stats,
10875         .get_coalesce           = tg3_get_coalesce,
10876         .set_coalesce           = tg3_set_coalesce,
10877         .get_sset_count         = tg3_get_sset_count,
10878 };
10879
10880 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10881 {
10882         u32 cursize, val, magic;
10883
10884         tp->nvram_size = EEPROM_CHIP_SIZE;
10885
10886         if (tg3_nvram_read(tp, 0, &magic) != 0)
10887                 return;
10888
10889         if ((magic != TG3_EEPROM_MAGIC) &&
10890             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10891             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10892                 return;
10893
10894         /*
10895          * Size the chip by reading offsets at increasing powers of two.
10896          * When we encounter our validation signature, we know the addressing
10897          * has wrapped around, and thus have our chip size.
10898          */
10899         cursize = 0x10;
10900
10901         while (cursize < tp->nvram_size) {
10902                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10903                         return;
10904
10905                 if (val == magic)
10906                         break;
10907
10908                 cursize <<= 1;
10909         }
10910
10911         tp->nvram_size = cursize;
10912 }
10913
10914 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10915 {
10916         u32 val;
10917
10918         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10919             tg3_nvram_read(tp, 0, &val) != 0)
10920                 return;
10921
10922         /* Selfboot format */
10923         if (val != TG3_EEPROM_MAGIC) {
10924                 tg3_get_eeprom_size(tp);
10925                 return;
10926         }
10927
10928         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10929                 if (val != 0) {
10930                         /* This is confusing.  We want to operate on the
10931                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10932                          * call will read from NVRAM and byteswap the data
10933                          * according to the byteswapping settings for all
10934                          * other register accesses.  This ensures the data we
10935                          * want will always reside in the lower 16-bits.
10936                          * However, the data in NVRAM is in LE format, which
10937                          * means the data from the NVRAM read will always be
10938                          * opposite the endianness of the CPU.  The 16-bit
10939                          * byteswap then brings the data to CPU endianness.
10940                          */
10941                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10942                         return;
10943                 }
10944         }
10945         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10946 }
10947
10948 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10949 {
10950         u32 nvcfg1;
10951
10952         nvcfg1 = tr32(NVRAM_CFG1);
10953         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10954                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10955         } else {
10956                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10957                 tw32(NVRAM_CFG1, nvcfg1);
10958         }
10959
10960         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10961             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10962                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10963                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10964                         tp->nvram_jedecnum = JEDEC_ATMEL;
10965                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10966                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10967                         break;
10968                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10969                         tp->nvram_jedecnum = JEDEC_ATMEL;
10970                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10971                         break;
10972                 case FLASH_VENDOR_ATMEL_EEPROM:
10973                         tp->nvram_jedecnum = JEDEC_ATMEL;
10974                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10975                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10976                         break;
10977                 case FLASH_VENDOR_ST:
10978                         tp->nvram_jedecnum = JEDEC_ST;
10979                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10980                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10981                         break;
10982                 case FLASH_VENDOR_SAIFUN:
10983                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10984                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10985                         break;
10986                 case FLASH_VENDOR_SST_SMALL:
10987                 case FLASH_VENDOR_SST_LARGE:
10988                         tp->nvram_jedecnum = JEDEC_SST;
10989                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10990                         break;
10991                 }
10992         } else {
10993                 tp->nvram_jedecnum = JEDEC_ATMEL;
10994                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10995                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10996         }
10997 }
10998
10999 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11000 {
11001         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11002         case FLASH_5752PAGE_SIZE_256:
11003                 tp->nvram_pagesize = 256;
11004                 break;
11005         case FLASH_5752PAGE_SIZE_512:
11006                 tp->nvram_pagesize = 512;
11007                 break;
11008         case FLASH_5752PAGE_SIZE_1K:
11009                 tp->nvram_pagesize = 1024;
11010                 break;
11011         case FLASH_5752PAGE_SIZE_2K:
11012                 tp->nvram_pagesize = 2048;
11013                 break;
11014         case FLASH_5752PAGE_SIZE_4K:
11015                 tp->nvram_pagesize = 4096;
11016                 break;
11017         case FLASH_5752PAGE_SIZE_264:
11018                 tp->nvram_pagesize = 264;
11019                 break;
11020         case FLASH_5752PAGE_SIZE_528:
11021                 tp->nvram_pagesize = 528;
11022                 break;
11023         }
11024 }
11025
11026 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11027 {
11028         u32 nvcfg1;
11029
11030         nvcfg1 = tr32(NVRAM_CFG1);
11031
11032         /* NVRAM protection for TPM */
11033         if (nvcfg1 & (1 << 27))
11034                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11035
11036         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11037         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11038         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11039                 tp->nvram_jedecnum = JEDEC_ATMEL;
11040                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11041                 break;
11042         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11043                 tp->nvram_jedecnum = JEDEC_ATMEL;
11044                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11045                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11046                 break;
11047         case FLASH_5752VENDOR_ST_M45PE10:
11048         case FLASH_5752VENDOR_ST_M45PE20:
11049         case FLASH_5752VENDOR_ST_M45PE40:
11050                 tp->nvram_jedecnum = JEDEC_ST;
11051                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11052                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11053                 break;
11054         }
11055
11056         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11057                 tg3_nvram_get_pagesize(tp, nvcfg1);
11058         } else {
11059                 /* For eeprom, set pagesize to maximum eeprom size */
11060                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11061
11062                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11063                 tw32(NVRAM_CFG1, nvcfg1);
11064         }
11065 }
11066
11067 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11068 {
11069         u32 nvcfg1, protect = 0;
11070
11071         nvcfg1 = tr32(NVRAM_CFG1);
11072
11073         /* NVRAM protection for TPM */
11074         if (nvcfg1 & (1 << 27)) {
11075                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11076                 protect = 1;
11077         }
11078
11079         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11080         switch (nvcfg1) {
11081         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11082         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11083         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11084         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11085                 tp->nvram_jedecnum = JEDEC_ATMEL;
11086                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11087                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11088                 tp->nvram_pagesize = 264;
11089                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11090                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11091                         tp->nvram_size = (protect ? 0x3e200 :
11092                                           TG3_NVRAM_SIZE_512KB);
11093                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11094                         tp->nvram_size = (protect ? 0x1f200 :
11095                                           TG3_NVRAM_SIZE_256KB);
11096                 else
11097                         tp->nvram_size = (protect ? 0x1f200 :
11098                                           TG3_NVRAM_SIZE_128KB);
11099                 break;
11100         case FLASH_5752VENDOR_ST_M45PE10:
11101         case FLASH_5752VENDOR_ST_M45PE20:
11102         case FLASH_5752VENDOR_ST_M45PE40:
11103                 tp->nvram_jedecnum = JEDEC_ST;
11104                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11105                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11106                 tp->nvram_pagesize = 256;
11107                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11108                         tp->nvram_size = (protect ?
11109                                           TG3_NVRAM_SIZE_64KB :
11110                                           TG3_NVRAM_SIZE_128KB);
11111                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11112                         tp->nvram_size = (protect ?
11113                                           TG3_NVRAM_SIZE_64KB :
11114                                           TG3_NVRAM_SIZE_256KB);
11115                 else
11116                         tp->nvram_size = (protect ?
11117                                           TG3_NVRAM_SIZE_128KB :
11118                                           TG3_NVRAM_SIZE_512KB);
11119                 break;
11120         }
11121 }
11122
11123 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11124 {
11125         u32 nvcfg1;
11126
11127         nvcfg1 = tr32(NVRAM_CFG1);
11128
11129         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11130         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11131         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11132         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11133         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11134                 tp->nvram_jedecnum = JEDEC_ATMEL;
11135                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11136                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11137
11138                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11139                 tw32(NVRAM_CFG1, nvcfg1);
11140                 break;
11141         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11142         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11143         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11144         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11145                 tp->nvram_jedecnum = JEDEC_ATMEL;
11146                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11147                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11148                 tp->nvram_pagesize = 264;
11149                 break;
11150         case FLASH_5752VENDOR_ST_M45PE10:
11151         case FLASH_5752VENDOR_ST_M45PE20:
11152         case FLASH_5752VENDOR_ST_M45PE40:
11153                 tp->nvram_jedecnum = JEDEC_ST;
11154                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11155                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11156                 tp->nvram_pagesize = 256;
11157                 break;
11158         }
11159 }
11160
11161 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11162 {
11163         u32 nvcfg1, protect = 0;
11164
11165         nvcfg1 = tr32(NVRAM_CFG1);
11166
11167         /* NVRAM protection for TPM */
11168         if (nvcfg1 & (1 << 27)) {
11169                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11170                 protect = 1;
11171         }
11172
11173         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11174         switch (nvcfg1) {
11175         case FLASH_5761VENDOR_ATMEL_ADB021D:
11176         case FLASH_5761VENDOR_ATMEL_ADB041D:
11177         case FLASH_5761VENDOR_ATMEL_ADB081D:
11178         case FLASH_5761VENDOR_ATMEL_ADB161D:
11179         case FLASH_5761VENDOR_ATMEL_MDB021D:
11180         case FLASH_5761VENDOR_ATMEL_MDB041D:
11181         case FLASH_5761VENDOR_ATMEL_MDB081D:
11182         case FLASH_5761VENDOR_ATMEL_MDB161D:
11183                 tp->nvram_jedecnum = JEDEC_ATMEL;
11184                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11185                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11186                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11187                 tp->nvram_pagesize = 256;
11188                 break;
11189         case FLASH_5761VENDOR_ST_A_M45PE20:
11190         case FLASH_5761VENDOR_ST_A_M45PE40:
11191         case FLASH_5761VENDOR_ST_A_M45PE80:
11192         case FLASH_5761VENDOR_ST_A_M45PE16:
11193         case FLASH_5761VENDOR_ST_M_M45PE20:
11194         case FLASH_5761VENDOR_ST_M_M45PE40:
11195         case FLASH_5761VENDOR_ST_M_M45PE80:
11196         case FLASH_5761VENDOR_ST_M_M45PE16:
11197                 tp->nvram_jedecnum = JEDEC_ST;
11198                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11199                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11200                 tp->nvram_pagesize = 256;
11201                 break;
11202         }
11203
11204         if (protect) {
11205                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11206         } else {
11207                 switch (nvcfg1) {
11208                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11209                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11210                 case FLASH_5761VENDOR_ST_A_M45PE16:
11211                 case FLASH_5761VENDOR_ST_M_M45PE16:
11212                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11213                         break;
11214                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11215                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11216                 case FLASH_5761VENDOR_ST_A_M45PE80:
11217                 case FLASH_5761VENDOR_ST_M_M45PE80:
11218                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11219                         break;
11220                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11221                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11222                 case FLASH_5761VENDOR_ST_A_M45PE40:
11223                 case FLASH_5761VENDOR_ST_M_M45PE40:
11224                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11225                         break;
11226                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11227                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11228                 case FLASH_5761VENDOR_ST_A_M45PE20:
11229                 case FLASH_5761VENDOR_ST_M_M45PE20:
11230                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11231                         break;
11232                 }
11233         }
11234 }
11235
11236 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11237 {
11238         tp->nvram_jedecnum = JEDEC_ATMEL;
11239         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11240         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11241 }
11242
11243 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11244 {
11245         u32 nvcfg1;
11246
11247         nvcfg1 = tr32(NVRAM_CFG1);
11248
11249         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11250         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11251         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11252                 tp->nvram_jedecnum = JEDEC_ATMEL;
11253                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11254                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11255
11256                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11257                 tw32(NVRAM_CFG1, nvcfg1);
11258                 return;
11259         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11260         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11261         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11262         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11263         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11264         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11265         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11266                 tp->nvram_jedecnum = JEDEC_ATMEL;
11267                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11268                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11269
11270                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11271                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11272                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11273                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11274                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11275                         break;
11276                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11277                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11278                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11279                         break;
11280                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11281                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11282                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11283                         break;
11284                 }
11285                 break;
11286         case FLASH_5752VENDOR_ST_M45PE10:
11287         case FLASH_5752VENDOR_ST_M45PE20:
11288         case FLASH_5752VENDOR_ST_M45PE40:
11289                 tp->nvram_jedecnum = JEDEC_ST;
11290                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11291                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11292
11293                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11294                 case FLASH_5752VENDOR_ST_M45PE10:
11295                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11296                         break;
11297                 case FLASH_5752VENDOR_ST_M45PE20:
11298                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11299                         break;
11300                 case FLASH_5752VENDOR_ST_M45PE40:
11301                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11302                         break;
11303                 }
11304                 break;
11305         default:
11306                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11307                 return;
11308         }
11309
11310         tg3_nvram_get_pagesize(tp, nvcfg1);
11311         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11312                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11313 }
11314
11315
11316 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11317 {
11318         u32 nvcfg1;
11319
11320         nvcfg1 = tr32(NVRAM_CFG1);
11321
11322         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11323         case FLASH_5717VENDOR_ATMEL_EEPROM:
11324         case FLASH_5717VENDOR_MICRO_EEPROM:
11325                 tp->nvram_jedecnum = JEDEC_ATMEL;
11326                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11327                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11328
11329                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11330                 tw32(NVRAM_CFG1, nvcfg1);
11331                 return;
11332         case FLASH_5717VENDOR_ATMEL_MDB011D:
11333         case FLASH_5717VENDOR_ATMEL_ADB011B:
11334         case FLASH_5717VENDOR_ATMEL_ADB011D:
11335         case FLASH_5717VENDOR_ATMEL_MDB021D:
11336         case FLASH_5717VENDOR_ATMEL_ADB021B:
11337         case FLASH_5717VENDOR_ATMEL_ADB021D:
11338         case FLASH_5717VENDOR_ATMEL_45USPT:
11339                 tp->nvram_jedecnum = JEDEC_ATMEL;
11340                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11341                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11342
11343                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11344                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11345                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11346                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11347                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11348                         break;
11349                 default:
11350                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11351                         break;
11352                 }
11353                 break;
11354         case FLASH_5717VENDOR_ST_M_M25PE10:
11355         case FLASH_5717VENDOR_ST_A_M25PE10:
11356         case FLASH_5717VENDOR_ST_M_M45PE10:
11357         case FLASH_5717VENDOR_ST_A_M45PE10:
11358         case FLASH_5717VENDOR_ST_M_M25PE20:
11359         case FLASH_5717VENDOR_ST_A_M25PE20:
11360         case FLASH_5717VENDOR_ST_M_M45PE20:
11361         case FLASH_5717VENDOR_ST_A_M45PE20:
11362         case FLASH_5717VENDOR_ST_25USPT:
11363         case FLASH_5717VENDOR_ST_45USPT:
11364                 tp->nvram_jedecnum = JEDEC_ST;
11365                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11366                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11367
11368                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11369                 case FLASH_5717VENDOR_ST_M_M25PE20:
11370                 case FLASH_5717VENDOR_ST_A_M25PE20:
11371                 case FLASH_5717VENDOR_ST_M_M45PE20:
11372                 case FLASH_5717VENDOR_ST_A_M45PE20:
11373                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11374                         break;
11375                 default:
11376                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11377                         break;
11378                 }
11379                 break;
11380         default:
11381                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11382                 return;
11383         }
11384
11385         tg3_nvram_get_pagesize(tp, nvcfg1);
11386         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11387                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11388 }
11389
11390 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11391 static void __devinit tg3_nvram_init(struct tg3 *tp)
11392 {
11393         tw32_f(GRC_EEPROM_ADDR,
11394              (EEPROM_ADDR_FSM_RESET |
11395               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11396                EEPROM_ADDR_CLKPERD_SHIFT)));
11397
11398         msleep(1);
11399
11400         /* Enable seeprom accesses. */
11401         tw32_f(GRC_LOCAL_CTRL,
11402              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11403         udelay(100);
11404
11405         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11406             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11407                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11408
11409                 if (tg3_nvram_lock(tp)) {
11410                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11411                                "tg3_nvram_init failed.\n", tp->dev->name);
11412                         return;
11413                 }
11414                 tg3_enable_nvram_access(tp);
11415
11416                 tp->nvram_size = 0;
11417
11418                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11419                         tg3_get_5752_nvram_info(tp);
11420                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11421                         tg3_get_5755_nvram_info(tp);
11422                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11423                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11424                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11425                         tg3_get_5787_nvram_info(tp);
11426                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11427                         tg3_get_5761_nvram_info(tp);
11428                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11429                         tg3_get_5906_nvram_info(tp);
11430                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11431                         tg3_get_57780_nvram_info(tp);
11432                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11433                         tg3_get_5717_nvram_info(tp);
11434                 else
11435                         tg3_get_nvram_info(tp);
11436
11437                 if (tp->nvram_size == 0)
11438                         tg3_get_nvram_size(tp);
11439
11440                 tg3_disable_nvram_access(tp);
11441                 tg3_nvram_unlock(tp);
11442
11443         } else {
11444                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11445
11446                 tg3_get_eeprom_size(tp);
11447         }
11448 }
11449
11450 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11451                                     u32 offset, u32 len, u8 *buf)
11452 {
11453         int i, j, rc = 0;
11454         u32 val;
11455
11456         for (i = 0; i < len; i += 4) {
11457                 u32 addr;
11458                 __be32 data;
11459
11460                 addr = offset + i;
11461
11462                 memcpy(&data, buf + i, 4);
11463
11464                 /*
11465                  * The SEEPROM interface expects the data to always be opposite
11466                  * the native endian format.  We accomplish this by reversing
11467                  * all the operations that would have been performed on the
11468                  * data from a call to tg3_nvram_read_be32().
11469                  */
11470                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11471
11472                 val = tr32(GRC_EEPROM_ADDR);
11473                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11474
11475                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11476                         EEPROM_ADDR_READ);
11477                 tw32(GRC_EEPROM_ADDR, val |
11478                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11479                         (addr & EEPROM_ADDR_ADDR_MASK) |
11480                         EEPROM_ADDR_START |
11481                         EEPROM_ADDR_WRITE);
11482
11483                 for (j = 0; j < 1000; j++) {
11484                         val = tr32(GRC_EEPROM_ADDR);
11485
11486                         if (val & EEPROM_ADDR_COMPLETE)
11487                                 break;
11488                         msleep(1);
11489                 }
11490                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11491                         rc = -EBUSY;
11492                         break;
11493                 }
11494         }
11495
11496         return rc;
11497 }
11498
11499 /* offset and length are dword aligned */
11500 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11501                 u8 *buf)
11502 {
11503         int ret = 0;
11504         u32 pagesize = tp->nvram_pagesize;
11505         u32 pagemask = pagesize - 1;
11506         u32 nvram_cmd;
11507         u8 *tmp;
11508
11509         tmp = kmalloc(pagesize, GFP_KERNEL);
11510         if (tmp == NULL)
11511                 return -ENOMEM;
11512
11513         while (len) {
11514                 int j;
11515                 u32 phy_addr, page_off, size;
11516
11517                 phy_addr = offset & ~pagemask;
11518
11519                 for (j = 0; j < pagesize; j += 4) {
11520                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11521                                                   (__be32 *) (tmp + j));
11522                         if (ret)
11523                                 break;
11524                 }
11525                 if (ret)
11526                         break;
11527
11528                 page_off = offset & pagemask;
11529                 size = pagesize;
11530                 if (len < size)
11531                         size = len;
11532
11533                 len -= size;
11534
11535                 memcpy(tmp + page_off, buf, size);
11536
11537                 offset = offset + (pagesize - page_off);
11538
11539                 tg3_enable_nvram_access(tp);
11540
11541                 /*
11542                  * Before we can erase the flash page, we need
11543                  * to issue a special "write enable" command.
11544                  */
11545                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11546
11547                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11548                         break;
11549
11550                 /* Erase the target page */
11551                 tw32(NVRAM_ADDR, phy_addr);
11552
11553                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11554                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11555
11556                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11557                         break;
11558
11559                 /* Issue another write enable to start the write. */
11560                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11561
11562                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11563                         break;
11564
11565                 for (j = 0; j < pagesize; j += 4) {
11566                         __be32 data;
11567
11568                         data = *((__be32 *) (tmp + j));
11569
11570                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11571
11572                         tw32(NVRAM_ADDR, phy_addr + j);
11573
11574                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11575                                 NVRAM_CMD_WR;
11576
11577                         if (j == 0)
11578                                 nvram_cmd |= NVRAM_CMD_FIRST;
11579                         else if (j == (pagesize - 4))
11580                                 nvram_cmd |= NVRAM_CMD_LAST;
11581
11582                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11583                                 break;
11584                 }
11585                 if (ret)
11586                         break;
11587         }
11588
11589         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11590         tg3_nvram_exec_cmd(tp, nvram_cmd);
11591
11592         kfree(tmp);
11593
11594         return ret;
11595 }
11596
11597 /* offset and length are dword aligned */
11598 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11599                 u8 *buf)
11600 {
11601         int i, ret = 0;
11602
11603         for (i = 0; i < len; i += 4, offset += 4) {
11604                 u32 page_off, phy_addr, nvram_cmd;
11605                 __be32 data;
11606
11607                 memcpy(&data, buf + i, 4);
11608                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11609
11610                 page_off = offset % tp->nvram_pagesize;
11611
11612                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11613
11614                 tw32(NVRAM_ADDR, phy_addr);
11615
11616                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11617
11618                 if ((page_off == 0) || (i == 0))
11619                         nvram_cmd |= NVRAM_CMD_FIRST;
11620                 if (page_off == (tp->nvram_pagesize - 4))
11621                         nvram_cmd |= NVRAM_CMD_LAST;
11622
11623                 if (i == (len - 4))
11624                         nvram_cmd |= NVRAM_CMD_LAST;
11625
11626                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11627                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11628                     (tp->nvram_jedecnum == JEDEC_ST) &&
11629                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11630
11631                         if ((ret = tg3_nvram_exec_cmd(tp,
11632                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11633                                 NVRAM_CMD_DONE)))
11634
11635                                 break;
11636                 }
11637                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11638                         /* We always do complete word writes to eeprom. */
11639                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11640                 }
11641
11642                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11643                         break;
11644         }
11645         return ret;
11646 }
11647
11648 /* offset and length are dword aligned */
11649 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11650 {
11651         int ret;
11652
11653         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11654                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11655                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11656                 udelay(40);
11657         }
11658
11659         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11660                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11661         }
11662         else {
11663                 u32 grc_mode;
11664
11665                 ret = tg3_nvram_lock(tp);
11666                 if (ret)
11667                         return ret;
11668
11669                 tg3_enable_nvram_access(tp);
11670                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11671                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11672                         tw32(NVRAM_WRITE1, 0x406);
11673
11674                 grc_mode = tr32(GRC_MODE);
11675                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11676
11677                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11678                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11679
11680                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11681                                 buf);
11682                 }
11683                 else {
11684                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11685                                 buf);
11686                 }
11687
11688                 grc_mode = tr32(GRC_MODE);
11689                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11690
11691                 tg3_disable_nvram_access(tp);
11692                 tg3_nvram_unlock(tp);
11693         }
11694
11695         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11696                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11697                 udelay(40);
11698         }
11699
11700         return ret;
11701 }
11702
11703 struct subsys_tbl_ent {
11704         u16 subsys_vendor, subsys_devid;
11705         u32 phy_id;
11706 };
11707
11708 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11709         /* Broadcom boards. */
11710         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11711         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11712         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11713         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11714         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11715         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11716         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11717         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11718         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11719         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11720         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11721
11722         /* 3com boards. */
11723         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11724         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11725         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11726         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11727         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11728
11729         /* DELL boards. */
11730         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11731         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11732         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11733         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11734
11735         /* Compaq boards. */
11736         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11737         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11738         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11739         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11740         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11741
11742         /* IBM boards. */
11743         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11744 };
11745
11746 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11747 {
11748         int i;
11749
11750         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11751                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11752                      tp->pdev->subsystem_vendor) &&
11753                     (subsys_id_to_phy_id[i].subsys_devid ==
11754                      tp->pdev->subsystem_device))
11755                         return &subsys_id_to_phy_id[i];
11756         }
11757         return NULL;
11758 }
11759
11760 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11761 {
11762         u32 val;
11763         u16 pmcsr;
11764
11765         /* On some early chips the SRAM cannot be accessed in D3hot state,
11766          * so need make sure we're in D0.
11767          */
11768         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11769         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11770         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11771         msleep(1);
11772
11773         /* Make sure register accesses (indirect or otherwise)
11774          * will function correctly.
11775          */
11776         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11777                                tp->misc_host_ctrl);
11778
11779         /* The memory arbiter has to be enabled in order for SRAM accesses
11780          * to succeed.  Normally on powerup the tg3 chip firmware will make
11781          * sure it is enabled, but other entities such as system netboot
11782          * code might disable it.
11783          */
11784         val = tr32(MEMARB_MODE);
11785         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11786
11787         tp->phy_id = PHY_ID_INVALID;
11788         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11789
11790         /* Assume an onboard device and WOL capable by default.  */
11791         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11792
11793         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11794                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11795                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11796                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11797                 }
11798                 val = tr32(VCPU_CFGSHDW);
11799                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11800                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11801                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11802                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11803                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11804                 goto done;
11805         }
11806
11807         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11808         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11809                 u32 nic_cfg, led_cfg;
11810                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11811                 int eeprom_phy_serdes = 0;
11812
11813                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11814                 tp->nic_sram_data_cfg = nic_cfg;
11815
11816                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11817                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11818                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11819                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11820                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11821                     (ver > 0) && (ver < 0x100))
11822                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11823
11824                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11825                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11826
11827                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11828                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11829                         eeprom_phy_serdes = 1;
11830
11831                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11832                 if (nic_phy_id != 0) {
11833                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11834                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11835
11836                         eeprom_phy_id  = (id1 >> 16) << 10;
11837                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11838                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11839                 } else
11840                         eeprom_phy_id = 0;
11841
11842                 tp->phy_id = eeprom_phy_id;
11843                 if (eeprom_phy_serdes) {
11844                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11845                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11846                         else
11847                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11848                 }
11849
11850                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11851                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11852                                     SHASTA_EXT_LED_MODE_MASK);
11853                 else
11854                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11855
11856                 switch (led_cfg) {
11857                 default:
11858                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11859                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11860                         break;
11861
11862                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11863                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11864                         break;
11865
11866                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11867                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11868
11869                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11870                          * read on some older 5700/5701 bootcode.
11871                          */
11872                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11873                             ASIC_REV_5700 ||
11874                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11875                             ASIC_REV_5701)
11876                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11877
11878                         break;
11879
11880                 case SHASTA_EXT_LED_SHARED:
11881                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11882                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11883                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11884                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11885                                                  LED_CTRL_MODE_PHY_2);
11886                         break;
11887
11888                 case SHASTA_EXT_LED_MAC:
11889                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11890                         break;
11891
11892                 case SHASTA_EXT_LED_COMBO:
11893                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11894                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11895                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11896                                                  LED_CTRL_MODE_PHY_2);
11897                         break;
11898
11899                 }
11900
11901                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11902                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11903                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11904                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11905
11906                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11907                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11908
11909                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11910                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11911                         if ((tp->pdev->subsystem_vendor ==
11912                              PCI_VENDOR_ID_ARIMA) &&
11913                             (tp->pdev->subsystem_device == 0x205a ||
11914                              tp->pdev->subsystem_device == 0x2063))
11915                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11916                 } else {
11917                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11918                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11919                 }
11920
11921                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11922                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11923                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11924                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11925                 }
11926
11927                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11928                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11929                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11930
11931                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11932                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11933                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11934
11935                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11936                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11937                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11938
11939                 if (cfg2 & (1 << 17))
11940                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11941
11942                 /* serdes signal pre-emphasis in register 0x590 set by */
11943                 /* bootcode if bit 18 is set */
11944                 if (cfg2 & (1 << 18))
11945                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11946
11947                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11948                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11949                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11950                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11951
11952                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11953                         u32 cfg3;
11954
11955                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11956                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11957                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11958                 }
11959
11960                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11961                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11962                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11963                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11964                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11965                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11966         }
11967 done:
11968         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11969         device_set_wakeup_enable(&tp->pdev->dev,
11970                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11971 }
11972
11973 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11974 {
11975         int i;
11976         u32 val;
11977
11978         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11979         tw32(OTP_CTRL, cmd);
11980
11981         /* Wait for up to 1 ms for command to execute. */
11982         for (i = 0; i < 100; i++) {
11983                 val = tr32(OTP_STATUS);
11984                 if (val & OTP_STATUS_CMD_DONE)
11985                         break;
11986                 udelay(10);
11987         }
11988
11989         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11990 }
11991
11992 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11993  * configuration is a 32-bit value that straddles the alignment boundary.
11994  * We do two 32-bit reads and then shift and merge the results.
11995  */
11996 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11997 {
11998         u32 bhalf_otp, thalf_otp;
11999
12000         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12001
12002         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12003                 return 0;
12004
12005         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12006
12007         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12008                 return 0;
12009
12010         thalf_otp = tr32(OTP_READ_DATA);
12011
12012         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12013
12014         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12015                 return 0;
12016
12017         bhalf_otp = tr32(OTP_READ_DATA);
12018
12019         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12020 }
12021
12022 static int __devinit tg3_phy_probe(struct tg3 *tp)
12023 {
12024         u32 hw_phy_id_1, hw_phy_id_2;
12025         u32 hw_phy_id, hw_phy_id_masked;
12026         int err;
12027
12028         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12029                 return tg3_phy_init(tp);
12030
12031         /* Reading the PHY ID register can conflict with ASF
12032          * firmware access to the PHY hardware.
12033          */
12034         err = 0;
12035         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12036             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12037                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12038         } else {
12039                 /* Now read the physical PHY_ID from the chip and verify
12040                  * that it is sane.  If it doesn't look good, we fall back
12041                  * to either the hard-coded table based PHY_ID and failing
12042                  * that the value found in the eeprom area.
12043                  */
12044                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12045                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12046
12047                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12048                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12049                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12050
12051                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12052         }
12053
12054         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12055                 tp->phy_id = hw_phy_id;
12056                 if (hw_phy_id_masked == PHY_ID_BCM8002)
12057                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12058                 else
12059                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12060         } else {
12061                 if (tp->phy_id != PHY_ID_INVALID) {
12062                         /* Do nothing, phy ID already set up in
12063                          * tg3_get_eeprom_hw_cfg().
12064                          */
12065                 } else {
12066                         struct subsys_tbl_ent *p;
12067
12068                         /* No eeprom signature?  Try the hardcoded
12069                          * subsys device table.
12070                          */
12071                         p = lookup_by_subsys(tp);
12072                         if (!p)
12073                                 return -ENODEV;
12074
12075                         tp->phy_id = p->phy_id;
12076                         if (!tp->phy_id ||
12077                             tp->phy_id == PHY_ID_BCM8002)
12078                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12079                 }
12080         }
12081
12082         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12083             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12084             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12085                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12086
12087                 tg3_readphy(tp, MII_BMSR, &bmsr);
12088                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12089                     (bmsr & BMSR_LSTATUS))
12090                         goto skip_phy_reset;
12091
12092                 err = tg3_phy_reset(tp);
12093                 if (err)
12094                         return err;
12095
12096                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12097                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12098                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12099                 tg3_ctrl = 0;
12100                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12101                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12102                                     MII_TG3_CTRL_ADV_1000_FULL);
12103                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12104                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12105                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12106                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12107                 }
12108
12109                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12110                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12111                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12112                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12113                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12114
12115                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12116                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12117
12118                         tg3_writephy(tp, MII_BMCR,
12119                                      BMCR_ANENABLE | BMCR_ANRESTART);
12120                 }
12121                 tg3_phy_set_wirespeed(tp);
12122
12123                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12124                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12125                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12126         }
12127
12128 skip_phy_reset:
12129         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12130                 err = tg3_init_5401phy_dsp(tp);
12131                 if (err)
12132                         return err;
12133         }
12134
12135         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12136                 err = tg3_init_5401phy_dsp(tp);
12137         }
12138
12139         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12140                 tp->link_config.advertising =
12141                         (ADVERTISED_1000baseT_Half |
12142                          ADVERTISED_1000baseT_Full |
12143                          ADVERTISED_Autoneg |
12144                          ADVERTISED_FIBRE);
12145         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12146                 tp->link_config.advertising &=
12147                         ~(ADVERTISED_1000baseT_Half |
12148                           ADVERTISED_1000baseT_Full);
12149
12150         return err;
12151 }
12152
12153 static void __devinit tg3_read_partno(struct tg3 *tp)
12154 {
12155         unsigned char vpd_data[256];   /* in little-endian format */
12156         unsigned int i;
12157         u32 magic;
12158
12159         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12160             tg3_nvram_read(tp, 0x0, &magic))
12161                 goto out_not_found;
12162
12163         if (magic == TG3_EEPROM_MAGIC) {
12164                 for (i = 0; i < 256; i += 4) {
12165                         u32 tmp;
12166
12167                         /* The data is in little-endian format in NVRAM.
12168                          * Use the big-endian read routines to preserve
12169                          * the byte order as it exists in NVRAM.
12170                          */
12171                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12172                                 goto out_not_found;
12173
12174                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12175                 }
12176         } else {
12177                 int vpd_cap;
12178
12179                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12180                 for (i = 0; i < 256; i += 4) {
12181                         u32 tmp, j = 0;
12182                         __le32 v;
12183                         u16 tmp16;
12184
12185                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12186                                               i);
12187                         while (j++ < 100) {
12188                                 pci_read_config_word(tp->pdev, vpd_cap +
12189                                                      PCI_VPD_ADDR, &tmp16);
12190                                 if (tmp16 & 0x8000)
12191                                         break;
12192                                 msleep(1);
12193                         }
12194                         if (!(tmp16 & 0x8000))
12195                                 goto out_not_found;
12196
12197                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12198                                               &tmp);
12199                         v = cpu_to_le32(tmp);
12200                         memcpy(&vpd_data[i], &v, sizeof(v));
12201                 }
12202         }
12203
12204         /* Now parse and find the part number. */
12205         for (i = 0; i < 254; ) {
12206                 unsigned char val = vpd_data[i];
12207                 unsigned int block_end;
12208
12209                 if (val == 0x82 || val == 0x91) {
12210                         i = (i + 3 +
12211                              (vpd_data[i + 1] +
12212                               (vpd_data[i + 2] << 8)));
12213                         continue;
12214                 }
12215
12216                 if (val != 0x90)
12217                         goto out_not_found;
12218
12219                 block_end = (i + 3 +
12220                              (vpd_data[i + 1] +
12221                               (vpd_data[i + 2] << 8)));
12222                 i += 3;
12223
12224                 if (block_end > 256)
12225                         goto out_not_found;
12226
12227                 while (i < (block_end - 2)) {
12228                         if (vpd_data[i + 0] == 'P' &&
12229                             vpd_data[i + 1] == 'N') {
12230                                 int partno_len = vpd_data[i + 2];
12231
12232                                 i += 3;
12233                                 if (partno_len > 24 || (partno_len + i) > 256)
12234                                         goto out_not_found;
12235
12236                                 memcpy(tp->board_part_number,
12237                                        &vpd_data[i], partno_len);
12238
12239                                 /* Success. */
12240                                 return;
12241                         }
12242                         i += 3 + vpd_data[i + 2];
12243                 }
12244
12245                 /* Part number not found. */
12246                 goto out_not_found;
12247         }
12248
12249 out_not_found:
12250         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12251                 strcpy(tp->board_part_number, "BCM95906");
12252         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12253                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12254                 strcpy(tp->board_part_number, "BCM57780");
12255         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12256                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12257                 strcpy(tp->board_part_number, "BCM57760");
12258         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12259                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12260                 strcpy(tp->board_part_number, "BCM57790");
12261         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12262                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12263                 strcpy(tp->board_part_number, "BCM57788");
12264         else
12265                 strcpy(tp->board_part_number, "none");
12266 }
12267
12268 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12269 {
12270         u32 val;
12271
12272         if (tg3_nvram_read(tp, offset, &val) ||
12273             (val & 0xfc000000) != 0x0c000000 ||
12274             tg3_nvram_read(tp, offset + 4, &val) ||
12275             val != 0)
12276                 return 0;
12277
12278         return 1;
12279 }
12280
12281 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12282 {
12283         u32 val, offset, start, ver_offset;
12284         int i;
12285         bool newver = false;
12286
12287         if (tg3_nvram_read(tp, 0xc, &offset) ||
12288             tg3_nvram_read(tp, 0x4, &start))
12289                 return;
12290
12291         offset = tg3_nvram_logical_addr(tp, offset);
12292
12293         if (tg3_nvram_read(tp, offset, &val))
12294                 return;
12295
12296         if ((val & 0xfc000000) == 0x0c000000) {
12297                 if (tg3_nvram_read(tp, offset + 4, &val))
12298                         return;
12299
12300                 if (val == 0)
12301                         newver = true;
12302         }
12303
12304         if (newver) {
12305                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12306                         return;
12307
12308                 offset = offset + ver_offset - start;
12309                 for (i = 0; i < 16; i += 4) {
12310                         __be32 v;
12311                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12312                                 return;
12313
12314                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12315                 }
12316         } else {
12317                 u32 major, minor;
12318
12319                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12320                         return;
12321
12322                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12323                         TG3_NVM_BCVER_MAJSFT;
12324                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12325                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12326         }
12327 }
12328
12329 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12330 {
12331         u32 val, major, minor;
12332
12333         /* Use native endian representation */
12334         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12335                 return;
12336
12337         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12338                 TG3_NVM_HWSB_CFG1_MAJSFT;
12339         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12340                 TG3_NVM_HWSB_CFG1_MINSFT;
12341
12342         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12343 }
12344
12345 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12346 {
12347         u32 offset, major, minor, build;
12348
12349         tp->fw_ver[0] = 's';
12350         tp->fw_ver[1] = 'b';
12351         tp->fw_ver[2] = '\0';
12352
12353         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12354                 return;
12355
12356         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12357         case TG3_EEPROM_SB_REVISION_0:
12358                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12359                 break;
12360         case TG3_EEPROM_SB_REVISION_2:
12361                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12362                 break;
12363         case TG3_EEPROM_SB_REVISION_3:
12364                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12365                 break;
12366         default:
12367                 return;
12368         }
12369
12370         if (tg3_nvram_read(tp, offset, &val))
12371                 return;
12372
12373         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12374                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12375         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12376                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12377         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12378
12379         if (minor > 99 || build > 26)
12380                 return;
12381
12382         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12383
12384         if (build > 0) {
12385                 tp->fw_ver[8] = 'a' + build - 1;
12386                 tp->fw_ver[9] = '\0';
12387         }
12388 }
12389
12390 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12391 {
12392         u32 val, offset, start;
12393         int i, vlen;
12394
12395         for (offset = TG3_NVM_DIR_START;
12396              offset < TG3_NVM_DIR_END;
12397              offset += TG3_NVM_DIRENT_SIZE) {
12398                 if (tg3_nvram_read(tp, offset, &val))
12399                         return;
12400
12401                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12402                         break;
12403         }
12404
12405         if (offset == TG3_NVM_DIR_END)
12406                 return;
12407
12408         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12409                 start = 0x08000000;
12410         else if (tg3_nvram_read(tp, offset - 4, &start))
12411                 return;
12412
12413         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12414             !tg3_fw_img_is_valid(tp, offset) ||
12415             tg3_nvram_read(tp, offset + 8, &val))
12416                 return;
12417
12418         offset += val - start;
12419
12420         vlen = strlen(tp->fw_ver);
12421
12422         tp->fw_ver[vlen++] = ',';
12423         tp->fw_ver[vlen++] = ' ';
12424
12425         for (i = 0; i < 4; i++) {
12426                 __be32 v;
12427                 if (tg3_nvram_read_be32(tp, offset, &v))
12428                         return;
12429
12430                 offset += sizeof(v);
12431
12432                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12433                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12434                         break;
12435                 }
12436
12437                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12438                 vlen += sizeof(v);
12439         }
12440 }
12441
12442 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12443 {
12444         int vlen;
12445         u32 apedata;
12446
12447         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12448             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12449                 return;
12450
12451         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12452         if (apedata != APE_SEG_SIG_MAGIC)
12453                 return;
12454
12455         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12456         if (!(apedata & APE_FW_STATUS_READY))
12457                 return;
12458
12459         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12460
12461         vlen = strlen(tp->fw_ver);
12462
12463         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12464                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12465                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12466                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12467                  (apedata & APE_FW_VERSION_BLDMSK));
12468 }
12469
12470 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12471 {
12472         u32 val;
12473
12474         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12475                 tp->fw_ver[0] = 's';
12476                 tp->fw_ver[1] = 'b';
12477                 tp->fw_ver[2] = '\0';
12478
12479                 return;
12480         }
12481
12482         if (tg3_nvram_read(tp, 0, &val))
12483                 return;
12484
12485         if (val == TG3_EEPROM_MAGIC)
12486                 tg3_read_bc_ver(tp);
12487         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12488                 tg3_read_sb_ver(tp, val);
12489         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12490                 tg3_read_hwsb_ver(tp);
12491         else
12492                 return;
12493
12494         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12495              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12496                 return;
12497
12498         tg3_read_mgmtfw_ver(tp);
12499
12500         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12501 }
12502
12503 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12504
12505 static int __devinit tg3_get_invariants(struct tg3 *tp)
12506 {
12507         static struct pci_device_id write_reorder_chipsets[] = {
12508                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12509                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12510                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12511                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12512                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12513                              PCI_DEVICE_ID_VIA_8385_0) },
12514                 { },
12515         };
12516         u32 misc_ctrl_reg;
12517         u32 pci_state_reg, grc_misc_cfg;
12518         u32 val;
12519         u16 pci_cmd;
12520         int err;
12521
12522         /* Force memory write invalidate off.  If we leave it on,
12523          * then on 5700_BX chips we have to enable a workaround.
12524          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12525          * to match the cacheline size.  The Broadcom driver have this
12526          * workaround but turns MWI off all the times so never uses
12527          * it.  This seems to suggest that the workaround is insufficient.
12528          */
12529         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12530         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12531         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12532
12533         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12534          * has the register indirect write enable bit set before
12535          * we try to access any of the MMIO registers.  It is also
12536          * critical that the PCI-X hw workaround situation is decided
12537          * before that as well.
12538          */
12539         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12540                               &misc_ctrl_reg);
12541
12542         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12543                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12544         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12545                 u32 prod_id_asic_rev;
12546
12547                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12548                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12549                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12550                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12551                         pci_read_config_dword(tp->pdev,
12552                                               TG3PCI_GEN2_PRODID_ASICREV,
12553                                               &prod_id_asic_rev);
12554                 else
12555                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12556                                               &prod_id_asic_rev);
12557
12558                 tp->pci_chip_rev_id = prod_id_asic_rev;
12559         }
12560
12561         /* Wrong chip ID in 5752 A0. This code can be removed later
12562          * as A0 is not in production.
12563          */
12564         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12565                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12566
12567         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12568          * we need to disable memory and use config. cycles
12569          * only to access all registers. The 5702/03 chips
12570          * can mistakenly decode the special cycles from the
12571          * ICH chipsets as memory write cycles, causing corruption
12572          * of register and memory space. Only certain ICH bridges
12573          * will drive special cycles with non-zero data during the
12574          * address phase which can fall within the 5703's address
12575          * range. This is not an ICH bug as the PCI spec allows
12576          * non-zero address during special cycles. However, only
12577          * these ICH bridges are known to drive non-zero addresses
12578          * during special cycles.
12579          *
12580          * Since special cycles do not cross PCI bridges, we only
12581          * enable this workaround if the 5703 is on the secondary
12582          * bus of these ICH bridges.
12583          */
12584         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12585             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12586                 static struct tg3_dev_id {
12587                         u32     vendor;
12588                         u32     device;
12589                         u32     rev;
12590                 } ich_chipsets[] = {
12591                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12592                           PCI_ANY_ID },
12593                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12594                           PCI_ANY_ID },
12595                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12596                           0xa },
12597                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12598                           PCI_ANY_ID },
12599                         { },
12600                 };
12601                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12602                 struct pci_dev *bridge = NULL;
12603
12604                 while (pci_id->vendor != 0) {
12605                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12606                                                 bridge);
12607                         if (!bridge) {
12608                                 pci_id++;
12609                                 continue;
12610                         }
12611                         if (pci_id->rev != PCI_ANY_ID) {
12612                                 if (bridge->revision > pci_id->rev)
12613                                         continue;
12614                         }
12615                         if (bridge->subordinate &&
12616                             (bridge->subordinate->number ==
12617                              tp->pdev->bus->number)) {
12618
12619                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12620                                 pci_dev_put(bridge);
12621                                 break;
12622                         }
12623                 }
12624         }
12625
12626         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12627                 static struct tg3_dev_id {
12628                         u32     vendor;
12629                         u32     device;
12630                 } bridge_chipsets[] = {
12631                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12632                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12633                         { },
12634                 };
12635                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12636                 struct pci_dev *bridge = NULL;
12637
12638                 while (pci_id->vendor != 0) {
12639                         bridge = pci_get_device(pci_id->vendor,
12640                                                 pci_id->device,
12641                                                 bridge);
12642                         if (!bridge) {
12643                                 pci_id++;
12644                                 continue;
12645                         }
12646                         if (bridge->subordinate &&
12647                             (bridge->subordinate->number <=
12648                              tp->pdev->bus->number) &&
12649                             (bridge->subordinate->subordinate >=
12650                              tp->pdev->bus->number)) {
12651                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12652                                 pci_dev_put(bridge);
12653                                 break;
12654                         }
12655                 }
12656         }
12657
12658         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12659          * DMA addresses > 40-bit. This bridge may have other additional
12660          * 57xx devices behind it in some 4-port NIC designs for example.
12661          * Any tg3 device found behind the bridge will also need the 40-bit
12662          * DMA workaround.
12663          */
12664         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12665             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12666                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12667                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12668                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12669         }
12670         else {
12671                 struct pci_dev *bridge = NULL;
12672
12673                 do {
12674                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12675                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12676                                                 bridge);
12677                         if (bridge && bridge->subordinate &&
12678                             (bridge->subordinate->number <=
12679                              tp->pdev->bus->number) &&
12680                             (bridge->subordinate->subordinate >=
12681                              tp->pdev->bus->number)) {
12682                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12683                                 pci_dev_put(bridge);
12684                                 break;
12685                         }
12686                 } while (bridge);
12687         }
12688
12689         /* Initialize misc host control in PCI block. */
12690         tp->misc_host_ctrl |= (misc_ctrl_reg &
12691                                MISC_HOST_CTRL_CHIPREV);
12692         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12693                                tp->misc_host_ctrl);
12694
12695         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12696             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12697             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12698                 tp->pdev_peer = tg3_find_peer(tp);
12699
12700         /* Intentionally exclude ASIC_REV_5906 */
12701         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12702             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12703             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12704             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12705             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12706             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12707             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12708                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12709
12710         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12711             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12712             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12713             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12714             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12715                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12716
12717         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12718             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12719                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12720
12721         /* 5700 B0 chips do not support checksumming correctly due
12722          * to hardware bugs.
12723          */
12724         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12725                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12726         else {
12727                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12728                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12729                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12730                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12731         }
12732
12733         /* Determine TSO capabilities */
12734         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12735                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12736         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12737                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12738                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12739         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12740                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12741                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12742                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12743                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12744         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12745                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12746                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12747                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12748                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12749                         tp->fw_needed = FIRMWARE_TG3TSO5;
12750                 else
12751                         tp->fw_needed = FIRMWARE_TG3TSO;
12752         }
12753
12754         tp->irq_max = 1;
12755
12756         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12757                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12758                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12759                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12760                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12761                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12762                      tp->pdev_peer == tp->pdev))
12763                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12764
12765                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12766                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12767                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12768                 }
12769
12770                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12771                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12772                         tp->irq_max = TG3_IRQ_MAX_VECS;
12773                 }
12774         }
12775
12776         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12777             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12778                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12779         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12780                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12781                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12782         }
12783
12784         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12785              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12786             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12787                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12788
12789         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12790                               &pci_state_reg);
12791
12792         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12793         if (tp->pcie_cap != 0) {
12794                 u16 lnkctl;
12795
12796                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12797
12798                 pcie_set_readrq(tp->pdev, 4096);
12799
12800                 pci_read_config_word(tp->pdev,
12801                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12802                                      &lnkctl);
12803                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12804                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12805                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12806                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12807                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12808                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12809                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12810                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12811                 }
12812         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12813                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12814         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12815                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12816                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12817                 if (!tp->pcix_cap) {
12818                         printk(KERN_ERR PFX "Cannot find PCI-X "
12819                                             "capability, aborting.\n");
12820                         return -EIO;
12821                 }
12822
12823                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12824                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12825         }
12826
12827         /* If we have an AMD 762 or VIA K8T800 chipset, write
12828          * reordering to the mailbox registers done by the host
12829          * controller can cause major troubles.  We read back from
12830          * every mailbox register write to force the writes to be
12831          * posted to the chip in order.
12832          */
12833         if (pci_dev_present(write_reorder_chipsets) &&
12834             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12835                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12836
12837         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12838                              &tp->pci_cacheline_sz);
12839         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12840                              &tp->pci_lat_timer);
12841         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12842             tp->pci_lat_timer < 64) {
12843                 tp->pci_lat_timer = 64;
12844                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12845                                       tp->pci_lat_timer);
12846         }
12847
12848         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12849                 /* 5700 BX chips need to have their TX producer index
12850                  * mailboxes written twice to workaround a bug.
12851                  */
12852                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12853
12854                 /* If we are in PCI-X mode, enable register write workaround.
12855                  *
12856                  * The workaround is to use indirect register accesses
12857                  * for all chip writes not to mailbox registers.
12858                  */
12859                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12860                         u32 pm_reg;
12861
12862                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12863
12864                         /* The chip can have it's power management PCI config
12865                          * space registers clobbered due to this bug.
12866                          * So explicitly force the chip into D0 here.
12867                          */
12868                         pci_read_config_dword(tp->pdev,
12869                                               tp->pm_cap + PCI_PM_CTRL,
12870                                               &pm_reg);
12871                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12872                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12873                         pci_write_config_dword(tp->pdev,
12874                                                tp->pm_cap + PCI_PM_CTRL,
12875                                                pm_reg);
12876
12877                         /* Also, force SERR#/PERR# in PCI command. */
12878                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12879                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12880                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12881                 }
12882         }
12883
12884         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12885                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12886         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12887                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12888
12889         /* Chip-specific fixup from Broadcom driver */
12890         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12891             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12892                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12893                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12894         }
12895
12896         /* Default fast path register access methods */
12897         tp->read32 = tg3_read32;
12898         tp->write32 = tg3_write32;
12899         tp->read32_mbox = tg3_read32;
12900         tp->write32_mbox = tg3_write32;
12901         tp->write32_tx_mbox = tg3_write32;
12902         tp->write32_rx_mbox = tg3_write32;
12903
12904         /* Various workaround register access methods */
12905         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12906                 tp->write32 = tg3_write_indirect_reg32;
12907         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12908                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12909                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12910                 /*
12911                  * Back to back register writes can cause problems on these
12912                  * chips, the workaround is to read back all reg writes
12913                  * except those to mailbox regs.
12914                  *
12915                  * See tg3_write_indirect_reg32().
12916                  */
12917                 tp->write32 = tg3_write_flush_reg32;
12918         }
12919
12920         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12921             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12922                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12923                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12924                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12925         }
12926
12927         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12928                 tp->read32 = tg3_read_indirect_reg32;
12929                 tp->write32 = tg3_write_indirect_reg32;
12930                 tp->read32_mbox = tg3_read_indirect_mbox;
12931                 tp->write32_mbox = tg3_write_indirect_mbox;
12932                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12933                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12934
12935                 iounmap(tp->regs);
12936                 tp->regs = NULL;
12937
12938                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12939                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12940                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12941         }
12942         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12943                 tp->read32_mbox = tg3_read32_mbox_5906;
12944                 tp->write32_mbox = tg3_write32_mbox_5906;
12945                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12946                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12947         }
12948
12949         if (tp->write32 == tg3_write_indirect_reg32 ||
12950             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12951              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12952               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12953                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12954
12955         /* Get eeprom hw config before calling tg3_set_power_state().
12956          * In particular, the TG3_FLG2_IS_NIC flag must be
12957          * determined before calling tg3_set_power_state() so that
12958          * we know whether or not to switch out of Vaux power.
12959          * When the flag is set, it means that GPIO1 is used for eeprom
12960          * write protect and also implies that it is a LOM where GPIOs
12961          * are not used to switch power.
12962          */
12963         tg3_get_eeprom_hw_cfg(tp);
12964
12965         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12966                 /* Allow reads and writes to the
12967                  * APE register and memory space.
12968                  */
12969                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12970                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12971                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12972                                        pci_state_reg);
12973         }
12974
12975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12978             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12979             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12980                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12981
12982         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12983          * GPIO1 driven high will bring 5700's external PHY out of reset.
12984          * It is also used as eeprom write protect on LOMs.
12985          */
12986         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12987         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12988             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12989                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12990                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12991         /* Unused GPIO3 must be driven as output on 5752 because there
12992          * are no pull-up resistors on unused GPIO pins.
12993          */
12994         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12995                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12996
12997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12999                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13000
13001         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13002             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13003                 /* Turn off the debug UART. */
13004                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13005                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13006                         /* Keep VMain power. */
13007                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13008                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13009         }
13010
13011         /* Force the chip into D0. */
13012         err = tg3_set_power_state(tp, PCI_D0);
13013         if (err) {
13014                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13015                        pci_name(tp->pdev));
13016                 return err;
13017         }
13018
13019         /* Derive initial jumbo mode from MTU assigned in
13020          * ether_setup() via the alloc_etherdev() call
13021          */
13022         if (tp->dev->mtu > ETH_DATA_LEN &&
13023             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13024                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13025
13026         /* Determine WakeOnLan speed to use. */
13027         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13028             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13029             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13030             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13031                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13032         } else {
13033                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13034         }
13035
13036         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13037                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13038
13039         /* A few boards don't want Ethernet@WireSpeed phy feature */
13040         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13041             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13042              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13043              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13044             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13045             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13046                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13047
13048         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13049             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13050                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13051         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13052                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13053
13054         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13055             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13056             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13057             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13058             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13059                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13060                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13061                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13062                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13063                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13064                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13065                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13066                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13067                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13068                 } else
13069                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13070         }
13071
13072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13073             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13074                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13075                 if (tp->phy_otp == 0)
13076                         tp->phy_otp = TG3_OTP_DEFAULT;
13077         }
13078
13079         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13080                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13081         else
13082                 tp->mi_mode = MAC_MI_MODE_BASE;
13083
13084         tp->coalesce_mode = 0;
13085         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13086             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13087                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13088
13089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13091                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13092
13093         err = tg3_mdio_init(tp);
13094         if (err)
13095                 return err;
13096
13097         /* Initialize data/descriptor byte/word swapping. */
13098         val = tr32(GRC_MODE);
13099         val &= GRC_MODE_HOST_STACKUP;
13100         tw32(GRC_MODE, val | tp->grc_mode);
13101
13102         tg3_switch_clocks(tp);
13103
13104         /* Clear this out for sanity. */
13105         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13106
13107         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13108                               &pci_state_reg);
13109         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13110             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13111                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13112
13113                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13114                     chiprevid == CHIPREV_ID_5701_B0 ||
13115                     chiprevid == CHIPREV_ID_5701_B2 ||
13116                     chiprevid == CHIPREV_ID_5701_B5) {
13117                         void __iomem *sram_base;
13118
13119                         /* Write some dummy words into the SRAM status block
13120                          * area, see if it reads back correctly.  If the return
13121                          * value is bad, force enable the PCIX workaround.
13122                          */
13123                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13124
13125                         writel(0x00000000, sram_base);
13126                         writel(0x00000000, sram_base + 4);
13127                         writel(0xffffffff, sram_base + 4);
13128                         if (readl(sram_base) != 0x00000000)
13129                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13130                 }
13131         }
13132
13133         udelay(50);
13134         tg3_nvram_init(tp);
13135
13136         grc_misc_cfg = tr32(GRC_MISC_CFG);
13137         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13138
13139         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13140             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13141              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13142                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13143
13144         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13145             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13146                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13147         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13148                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13149                                       HOSTCC_MODE_CLRTICK_TXBD);
13150
13151                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13152                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13153                                        tp->misc_host_ctrl);
13154         }
13155
13156         /* Preserve the APE MAC_MODE bits */
13157         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13158                 tp->mac_mode = tr32(MAC_MODE) |
13159                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13160         else
13161                 tp->mac_mode = TG3_DEF_MAC_MODE;
13162
13163         /* these are limited to 10/100 only */
13164         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13165              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13166             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13167              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13168              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13169               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13170               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13171             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13172              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13173               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13174               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13175             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13176             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13177                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13178
13179         err = tg3_phy_probe(tp);
13180         if (err) {
13181                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13182                        pci_name(tp->pdev), err);
13183                 /* ... but do not return immediately ... */
13184                 tg3_mdio_fini(tp);
13185         }
13186
13187         tg3_read_partno(tp);
13188         tg3_read_fw_ver(tp);
13189
13190         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13191                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13192         } else {
13193                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13194                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13195                 else
13196                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13197         }
13198
13199         /* 5700 {AX,BX} chips have a broken status block link
13200          * change bit implementation, so we must use the
13201          * status register in those cases.
13202          */
13203         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13204                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13205         else
13206                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13207
13208         /* The led_ctrl is set during tg3_phy_probe, here we might
13209          * have to force the link status polling mechanism based
13210          * upon subsystem IDs.
13211          */
13212         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13213             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13214             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13215                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13216                                   TG3_FLAG_USE_LINKCHG_REG);
13217         }
13218
13219         /* For all SERDES we poll the MAC status register. */
13220         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13221                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13222         else
13223                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13224
13225         tp->rx_offset = NET_IP_ALIGN;
13226         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13227             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13228                 tp->rx_offset = 0;
13229
13230         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13231
13232         /* Increment the rx prod index on the rx std ring by at most
13233          * 8 for these chips to workaround hw errata.
13234          */
13235         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13236             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13237             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13238                 tp->rx_std_max_post = 8;
13239
13240         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13241                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13242                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13243
13244         return err;
13245 }
13246
13247 #ifdef CONFIG_SPARC
13248 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13249 {
13250         struct net_device *dev = tp->dev;
13251         struct pci_dev *pdev = tp->pdev;
13252         struct device_node *dp = pci_device_to_OF_node(pdev);
13253         const unsigned char *addr;
13254         int len;
13255
13256         addr = of_get_property(dp, "local-mac-address", &len);
13257         if (addr && len == 6) {
13258                 memcpy(dev->dev_addr, addr, 6);
13259                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13260                 return 0;
13261         }
13262         return -ENODEV;
13263 }
13264
13265 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13266 {
13267         struct net_device *dev = tp->dev;
13268
13269         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13270         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13271         return 0;
13272 }
13273 #endif
13274
13275 static int __devinit tg3_get_device_address(struct tg3 *tp)
13276 {
13277         struct net_device *dev = tp->dev;
13278         u32 hi, lo, mac_offset;
13279         int addr_ok = 0;
13280
13281 #ifdef CONFIG_SPARC
13282         if (!tg3_get_macaddr_sparc(tp))
13283                 return 0;
13284 #endif
13285
13286         mac_offset = 0x7c;
13287         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13288             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13289                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13290                         mac_offset = 0xcc;
13291                 if (tg3_nvram_lock(tp))
13292                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13293                 else
13294                         tg3_nvram_unlock(tp);
13295         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13296                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13297                         mac_offset = 0xcc;
13298         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13299                 mac_offset = 0x10;
13300
13301         /* First try to get it from MAC address mailbox. */
13302         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13303         if ((hi >> 16) == 0x484b) {
13304                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13305                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13306
13307                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13308                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13309                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13310                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13311                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13312
13313                 /* Some old bootcode may report a 0 MAC address in SRAM */
13314                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13315         }
13316         if (!addr_ok) {
13317                 /* Next, try NVRAM. */
13318                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13319                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13320                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13321                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13322                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13323                 }
13324                 /* Finally just fetch it out of the MAC control regs. */
13325                 else {
13326                         hi = tr32(MAC_ADDR_0_HIGH);
13327                         lo = tr32(MAC_ADDR_0_LOW);
13328
13329                         dev->dev_addr[5] = lo & 0xff;
13330                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13331                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13332                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13333                         dev->dev_addr[1] = hi & 0xff;
13334                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13335                 }
13336         }
13337
13338         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13339 #ifdef CONFIG_SPARC
13340                 if (!tg3_get_default_macaddr_sparc(tp))
13341                         return 0;
13342 #endif
13343                 return -EINVAL;
13344         }
13345         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13346         return 0;
13347 }
13348
13349 #define BOUNDARY_SINGLE_CACHELINE       1
13350 #define BOUNDARY_MULTI_CACHELINE        2
13351
13352 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13353 {
13354         int cacheline_size;
13355         u8 byte;
13356         int goal;
13357
13358         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13359         if (byte == 0)
13360                 cacheline_size = 1024;
13361         else
13362                 cacheline_size = (int) byte * 4;
13363
13364         /* On 5703 and later chips, the boundary bits have no
13365          * effect.
13366          */
13367         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13368             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13369             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13370                 goto out;
13371
13372 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13373         goal = BOUNDARY_MULTI_CACHELINE;
13374 #else
13375 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13376         goal = BOUNDARY_SINGLE_CACHELINE;
13377 #else
13378         goal = 0;
13379 #endif
13380 #endif
13381
13382         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13383                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13384                 goto out;
13385         }
13386
13387         if (!goal)
13388                 goto out;
13389
13390         /* PCI controllers on most RISC systems tend to disconnect
13391          * when a device tries to burst across a cache-line boundary.
13392          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13393          *
13394          * Unfortunately, for PCI-E there are only limited
13395          * write-side controls for this, and thus for reads
13396          * we will still get the disconnects.  We'll also waste
13397          * these PCI cycles for both read and write for chips
13398          * other than 5700 and 5701 which do not implement the
13399          * boundary bits.
13400          */
13401         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13402             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13403                 switch (cacheline_size) {
13404                 case 16:
13405                 case 32:
13406                 case 64:
13407                 case 128:
13408                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13409                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13410                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13411                         } else {
13412                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13413                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13414                         }
13415                         break;
13416
13417                 case 256:
13418                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13419                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13420                         break;
13421
13422                 default:
13423                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13424                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13425                         break;
13426                 }
13427         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13428                 switch (cacheline_size) {
13429                 case 16:
13430                 case 32:
13431                 case 64:
13432                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13433                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13434                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13435                                 break;
13436                         }
13437                         /* fallthrough */
13438                 case 128:
13439                 default:
13440                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13441                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13442                         break;
13443                 }
13444         } else {
13445                 switch (cacheline_size) {
13446                 case 16:
13447                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13448                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13449                                         DMA_RWCTRL_WRITE_BNDRY_16);
13450                                 break;
13451                         }
13452                         /* fallthrough */
13453                 case 32:
13454                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13455                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13456                                         DMA_RWCTRL_WRITE_BNDRY_32);
13457                                 break;
13458                         }
13459                         /* fallthrough */
13460                 case 64:
13461                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13462                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13463                                         DMA_RWCTRL_WRITE_BNDRY_64);
13464                                 break;
13465                         }
13466                         /* fallthrough */
13467                 case 128:
13468                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13469                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13470                                         DMA_RWCTRL_WRITE_BNDRY_128);
13471                                 break;
13472                         }
13473                         /* fallthrough */
13474                 case 256:
13475                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13476                                 DMA_RWCTRL_WRITE_BNDRY_256);
13477                         break;
13478                 case 512:
13479                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13480                                 DMA_RWCTRL_WRITE_BNDRY_512);
13481                         break;
13482                 case 1024:
13483                 default:
13484                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13485                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13486                         break;
13487                 }
13488         }
13489
13490 out:
13491         return val;
13492 }
13493
13494 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13495 {
13496         struct tg3_internal_buffer_desc test_desc;
13497         u32 sram_dma_descs;
13498         int i, ret;
13499
13500         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13501
13502         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13503         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13504         tw32(RDMAC_STATUS, 0);
13505         tw32(WDMAC_STATUS, 0);
13506
13507         tw32(BUFMGR_MODE, 0);
13508         tw32(FTQ_RESET, 0);
13509
13510         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13511         test_desc.addr_lo = buf_dma & 0xffffffff;
13512         test_desc.nic_mbuf = 0x00002100;
13513         test_desc.len = size;
13514
13515         /*
13516          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13517          * the *second* time the tg3 driver was getting loaded after an
13518          * initial scan.
13519          *
13520          * Broadcom tells me:
13521          *   ...the DMA engine is connected to the GRC block and a DMA
13522          *   reset may affect the GRC block in some unpredictable way...
13523          *   The behavior of resets to individual blocks has not been tested.
13524          *
13525          * Broadcom noted the GRC reset will also reset all sub-components.
13526          */
13527         if (to_device) {
13528                 test_desc.cqid_sqid = (13 << 8) | 2;
13529
13530                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13531                 udelay(40);
13532         } else {
13533                 test_desc.cqid_sqid = (16 << 8) | 7;
13534
13535                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13536                 udelay(40);
13537         }
13538         test_desc.flags = 0x00000005;
13539
13540         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13541                 u32 val;
13542
13543                 val = *(((u32 *)&test_desc) + i);
13544                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13545                                        sram_dma_descs + (i * sizeof(u32)));
13546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13547         }
13548         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13549
13550         if (to_device) {
13551                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13552         } else {
13553                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13554         }
13555
13556         ret = -ENODEV;
13557         for (i = 0; i < 40; i++) {
13558                 u32 val;
13559
13560                 if (to_device)
13561                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13562                 else
13563                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13564                 if ((val & 0xffff) == sram_dma_descs) {
13565                         ret = 0;
13566                         break;
13567                 }
13568
13569                 udelay(100);
13570         }
13571
13572         return ret;
13573 }
13574
13575 #define TEST_BUFFER_SIZE        0x2000
13576
13577 static int __devinit tg3_test_dma(struct tg3 *tp)
13578 {
13579         dma_addr_t buf_dma;
13580         u32 *buf, saved_dma_rwctrl;
13581         int ret = 0;
13582
13583         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13584         if (!buf) {
13585                 ret = -ENOMEM;
13586                 goto out_nofree;
13587         }
13588
13589         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13590                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13591
13592         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13593
13594         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13595                 goto out;
13596
13597         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13598                 /* DMA read watermark not used on PCIE */
13599                 tp->dma_rwctrl |= 0x00180000;
13600         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13601                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13602                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13603                         tp->dma_rwctrl |= 0x003f0000;
13604                 else
13605                         tp->dma_rwctrl |= 0x003f000f;
13606         } else {
13607                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13608                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13609                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13610                         u32 read_water = 0x7;
13611
13612                         /* If the 5704 is behind the EPB bridge, we can
13613                          * do the less restrictive ONE_DMA workaround for
13614                          * better performance.
13615                          */
13616                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13617                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13618                                 tp->dma_rwctrl |= 0x8000;
13619                         else if (ccval == 0x6 || ccval == 0x7)
13620                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13621
13622                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13623                                 read_water = 4;
13624                         /* Set bit 23 to enable PCIX hw bug fix */
13625                         tp->dma_rwctrl |=
13626                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13627                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13628                                 (1 << 23);
13629                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13630                         /* 5780 always in PCIX mode */
13631                         tp->dma_rwctrl |= 0x00144000;
13632                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13633                         /* 5714 always in PCIX mode */
13634                         tp->dma_rwctrl |= 0x00148000;
13635                 } else {
13636                         tp->dma_rwctrl |= 0x001b000f;
13637                 }
13638         }
13639
13640         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13641             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13642                 tp->dma_rwctrl &= 0xfffffff0;
13643
13644         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13645             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13646                 /* Remove this if it causes problems for some boards. */
13647                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13648
13649                 /* On 5700/5701 chips, we need to set this bit.
13650                  * Otherwise the chip will issue cacheline transactions
13651                  * to streamable DMA memory with not all the byte
13652                  * enables turned on.  This is an error on several
13653                  * RISC PCI controllers, in particular sparc64.
13654                  *
13655                  * On 5703/5704 chips, this bit has been reassigned
13656                  * a different meaning.  In particular, it is used
13657                  * on those chips to enable a PCI-X workaround.
13658                  */
13659                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13660         }
13661
13662         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13663
13664 #if 0
13665         /* Unneeded, already done by tg3_get_invariants.  */
13666         tg3_switch_clocks(tp);
13667 #endif
13668
13669         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13670             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13671                 goto out;
13672
13673         /* It is best to perform DMA test with maximum write burst size
13674          * to expose the 5700/5701 write DMA bug.
13675          */
13676         saved_dma_rwctrl = tp->dma_rwctrl;
13677         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13678         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13679
13680         while (1) {
13681                 u32 *p = buf, i;
13682
13683                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13684                         p[i] = i;
13685
13686                 /* Send the buffer to the chip. */
13687                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13688                 if (ret) {
13689                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13690                         break;
13691                 }
13692
13693 #if 0
13694                 /* validate data reached card RAM correctly. */
13695                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13696                         u32 val;
13697                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13698                         if (le32_to_cpu(val) != p[i]) {
13699                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13700                                 /* ret = -ENODEV here? */
13701                         }
13702                         p[i] = 0;
13703                 }
13704 #endif
13705                 /* Now read it back. */
13706                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13707                 if (ret) {
13708                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13709
13710                         break;
13711                 }
13712
13713                 /* Verify it. */
13714                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13715                         if (p[i] == i)
13716                                 continue;
13717
13718                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13719                             DMA_RWCTRL_WRITE_BNDRY_16) {
13720                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13721                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13722                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13723                                 break;
13724                         } else {
13725                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13726                                 ret = -ENODEV;
13727                                 goto out;
13728                         }
13729                 }
13730
13731                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13732                         /* Success. */
13733                         ret = 0;
13734                         break;
13735                 }
13736         }
13737         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13738             DMA_RWCTRL_WRITE_BNDRY_16) {
13739                 static struct pci_device_id dma_wait_state_chipsets[] = {
13740                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13741                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13742                         { },
13743                 };
13744
13745                 /* DMA test passed without adjusting DMA boundary,
13746                  * now look for chipsets that are known to expose the
13747                  * DMA bug without failing the test.
13748                  */
13749                 if (pci_dev_present(dma_wait_state_chipsets)) {
13750                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13751                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13752                 }
13753                 else
13754                         /* Safe to use the calculated DMA boundary. */
13755                         tp->dma_rwctrl = saved_dma_rwctrl;
13756
13757                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13758         }
13759
13760 out:
13761         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13762 out_nofree:
13763         return ret;
13764 }
13765
13766 static void __devinit tg3_init_link_config(struct tg3 *tp)
13767 {
13768         tp->link_config.advertising =
13769                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13770                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13771                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13772                  ADVERTISED_Autoneg | ADVERTISED_MII);
13773         tp->link_config.speed = SPEED_INVALID;
13774         tp->link_config.duplex = DUPLEX_INVALID;
13775         tp->link_config.autoneg = AUTONEG_ENABLE;
13776         tp->link_config.active_speed = SPEED_INVALID;
13777         tp->link_config.active_duplex = DUPLEX_INVALID;
13778         tp->link_config.phy_is_low_power = 0;
13779         tp->link_config.orig_speed = SPEED_INVALID;
13780         tp->link_config.orig_duplex = DUPLEX_INVALID;
13781         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13782 }
13783
13784 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13785 {
13786         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13787             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13788                 tp->bufmgr_config.mbuf_read_dma_low_water =
13789                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13790                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13791                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13792                 tp->bufmgr_config.mbuf_high_water =
13793                         DEFAULT_MB_HIGH_WATER_5705;
13794                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13795                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13796                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13797                         tp->bufmgr_config.mbuf_high_water =
13798                                 DEFAULT_MB_HIGH_WATER_5906;
13799                 }
13800
13801                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13802                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13803                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13804                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13805                 tp->bufmgr_config.mbuf_high_water_jumbo =
13806                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13807         } else {
13808                 tp->bufmgr_config.mbuf_read_dma_low_water =
13809                         DEFAULT_MB_RDMA_LOW_WATER;
13810                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13811                         DEFAULT_MB_MACRX_LOW_WATER;
13812                 tp->bufmgr_config.mbuf_high_water =
13813                         DEFAULT_MB_HIGH_WATER;
13814
13815                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13816                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13817                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13818                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13819                 tp->bufmgr_config.mbuf_high_water_jumbo =
13820                         DEFAULT_MB_HIGH_WATER_JUMBO;
13821         }
13822
13823         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13824         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13825 }
13826
13827 static char * __devinit tg3_phy_string(struct tg3 *tp)
13828 {
13829         switch (tp->phy_id & PHY_ID_MASK) {
13830         case PHY_ID_BCM5400:    return "5400";
13831         case PHY_ID_BCM5401:    return "5401";
13832         case PHY_ID_BCM5411:    return "5411";
13833         case PHY_ID_BCM5701:    return "5701";
13834         case PHY_ID_BCM5703:    return "5703";
13835         case PHY_ID_BCM5704:    return "5704";
13836         case PHY_ID_BCM5705:    return "5705";
13837         case PHY_ID_BCM5750:    return "5750";
13838         case PHY_ID_BCM5752:    return "5752";
13839         case PHY_ID_BCM5714:    return "5714";
13840         case PHY_ID_BCM5780:    return "5780";
13841         case PHY_ID_BCM5755:    return "5755";
13842         case PHY_ID_BCM5787:    return "5787";
13843         case PHY_ID_BCM5784:    return "5784";
13844         case PHY_ID_BCM5756:    return "5722/5756";
13845         case PHY_ID_BCM5906:    return "5906";
13846         case PHY_ID_BCM5761:    return "5761";
13847         case PHY_ID_BCM5717:    return "5717";
13848         case PHY_ID_BCM8002:    return "8002/serdes";
13849         case 0:                 return "serdes";
13850         default:                return "unknown";
13851         }
13852 }
13853
13854 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13855 {
13856         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13857                 strcpy(str, "PCI Express");
13858                 return str;
13859         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13860                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13861
13862                 strcpy(str, "PCIX:");
13863
13864                 if ((clock_ctrl == 7) ||
13865                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13866                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13867                         strcat(str, "133MHz");
13868                 else if (clock_ctrl == 0)
13869                         strcat(str, "33MHz");
13870                 else if (clock_ctrl == 2)
13871                         strcat(str, "50MHz");
13872                 else if (clock_ctrl == 4)
13873                         strcat(str, "66MHz");
13874                 else if (clock_ctrl == 6)
13875                         strcat(str, "100MHz");
13876         } else {
13877                 strcpy(str, "PCI:");
13878                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13879                         strcat(str, "66MHz");
13880                 else
13881                         strcat(str, "33MHz");
13882         }
13883         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13884                 strcat(str, ":32-bit");
13885         else
13886                 strcat(str, ":64-bit");
13887         return str;
13888 }
13889
13890 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13891 {
13892         struct pci_dev *peer;
13893         unsigned int func, devnr = tp->pdev->devfn & ~7;
13894
13895         for (func = 0; func < 8; func++) {
13896                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13897                 if (peer && peer != tp->pdev)
13898                         break;
13899                 pci_dev_put(peer);
13900         }
13901         /* 5704 can be configured in single-port mode, set peer to
13902          * tp->pdev in that case.
13903          */
13904         if (!peer) {
13905                 peer = tp->pdev;
13906                 return peer;
13907         }
13908
13909         /*
13910          * We don't need to keep the refcount elevated; there's no way
13911          * to remove one half of this device without removing the other
13912          */
13913         pci_dev_put(peer);
13914
13915         return peer;
13916 }
13917
13918 static void __devinit tg3_init_coal(struct tg3 *tp)
13919 {
13920         struct ethtool_coalesce *ec = &tp->coal;
13921
13922         memset(ec, 0, sizeof(*ec));
13923         ec->cmd = ETHTOOL_GCOALESCE;
13924         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13925         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13926         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13927         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13928         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13929         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13930         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13931         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13932         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13933
13934         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13935                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13936                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13937                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13938                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13939                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13940         }
13941
13942         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13943                 ec->rx_coalesce_usecs_irq = 0;
13944                 ec->tx_coalesce_usecs_irq = 0;
13945                 ec->stats_block_coalesce_usecs = 0;
13946         }
13947 }
13948
13949 static const struct net_device_ops tg3_netdev_ops = {
13950         .ndo_open               = tg3_open,
13951         .ndo_stop               = tg3_close,
13952         .ndo_start_xmit         = tg3_start_xmit,
13953         .ndo_get_stats          = tg3_get_stats,
13954         .ndo_validate_addr      = eth_validate_addr,
13955         .ndo_set_multicast_list = tg3_set_rx_mode,
13956         .ndo_set_mac_address    = tg3_set_mac_addr,
13957         .ndo_do_ioctl           = tg3_ioctl,
13958         .ndo_tx_timeout         = tg3_tx_timeout,
13959         .ndo_change_mtu         = tg3_change_mtu,
13960 #if TG3_VLAN_TAG_USED
13961         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13962 #endif
13963 #ifdef CONFIG_NET_POLL_CONTROLLER
13964         .ndo_poll_controller    = tg3_poll_controller,
13965 #endif
13966 };
13967
13968 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13969         .ndo_open               = tg3_open,
13970         .ndo_stop               = tg3_close,
13971         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13972         .ndo_get_stats          = tg3_get_stats,
13973         .ndo_validate_addr      = eth_validate_addr,
13974         .ndo_set_multicast_list = tg3_set_rx_mode,
13975         .ndo_set_mac_address    = tg3_set_mac_addr,
13976         .ndo_do_ioctl           = tg3_ioctl,
13977         .ndo_tx_timeout         = tg3_tx_timeout,
13978         .ndo_change_mtu         = tg3_change_mtu,
13979 #if TG3_VLAN_TAG_USED
13980         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13981 #endif
13982 #ifdef CONFIG_NET_POLL_CONTROLLER
13983         .ndo_poll_controller    = tg3_poll_controller,
13984 #endif
13985 };
13986
13987 static int __devinit tg3_init_one(struct pci_dev *pdev,
13988                                   const struct pci_device_id *ent)
13989 {
13990         static int tg3_version_printed = 0;
13991         struct net_device *dev;
13992         struct tg3 *tp;
13993         int i, err, pm_cap;
13994         u32 sndmbx, rcvmbx, intmbx;
13995         char str[40];
13996         u64 dma_mask, persist_dma_mask;
13997
13998         if (tg3_version_printed++ == 0)
13999                 printk(KERN_INFO "%s", version);
14000
14001         err = pci_enable_device(pdev);
14002         if (err) {
14003                 printk(KERN_ERR PFX "Cannot enable PCI device, "
14004                        "aborting.\n");
14005                 return err;
14006         }
14007
14008         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14009         if (err) {
14010                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14011                        "aborting.\n");
14012                 goto err_out_disable_pdev;
14013         }
14014
14015         pci_set_master(pdev);
14016
14017         /* Find power-management capability. */
14018         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14019         if (pm_cap == 0) {
14020                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14021                        "aborting.\n");
14022                 err = -EIO;
14023                 goto err_out_free_res;
14024         }
14025
14026         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14027         if (!dev) {
14028                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14029                 err = -ENOMEM;
14030                 goto err_out_free_res;
14031         }
14032
14033         SET_NETDEV_DEV(dev, &pdev->dev);
14034
14035 #if TG3_VLAN_TAG_USED
14036         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14037 #endif
14038
14039         tp = netdev_priv(dev);
14040         tp->pdev = pdev;
14041         tp->dev = dev;
14042         tp->pm_cap = pm_cap;
14043         tp->rx_mode = TG3_DEF_RX_MODE;
14044         tp->tx_mode = TG3_DEF_TX_MODE;
14045
14046         if (tg3_debug > 0)
14047                 tp->msg_enable = tg3_debug;
14048         else
14049                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14050
14051         /* The word/byte swap controls here control register access byte
14052          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14053          * setting below.
14054          */
14055         tp->misc_host_ctrl =
14056                 MISC_HOST_CTRL_MASK_PCI_INT |
14057                 MISC_HOST_CTRL_WORD_SWAP |
14058                 MISC_HOST_CTRL_INDIR_ACCESS |
14059                 MISC_HOST_CTRL_PCISTATE_RW;
14060
14061         /* The NONFRM (non-frame) byte/word swap controls take effect
14062          * on descriptor entries, anything which isn't packet data.
14063          *
14064          * The StrongARM chips on the board (one for tx, one for rx)
14065          * are running in big-endian mode.
14066          */
14067         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14068                         GRC_MODE_WSWAP_NONFRM_DATA);
14069 #ifdef __BIG_ENDIAN
14070         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14071 #endif
14072         spin_lock_init(&tp->lock);
14073         spin_lock_init(&tp->indirect_lock);
14074         INIT_WORK(&tp->reset_task, tg3_reset_task);
14075
14076         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14077         if (!tp->regs) {
14078                 printk(KERN_ERR PFX "Cannot map device registers, "
14079                        "aborting.\n");
14080                 err = -ENOMEM;
14081                 goto err_out_free_dev;
14082         }
14083
14084         tg3_init_link_config(tp);
14085
14086         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14087         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14088
14089         dev->ethtool_ops = &tg3_ethtool_ops;
14090         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14091         dev->irq = pdev->irq;
14092
14093         err = tg3_get_invariants(tp);
14094         if (err) {
14095                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14096                        "aborting.\n");
14097                 goto err_out_iounmap;
14098         }
14099
14100         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14101             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14102                 dev->netdev_ops = &tg3_netdev_ops;
14103         else
14104                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14105
14106
14107         /* The EPB bridge inside 5714, 5715, and 5780 and any
14108          * device behind the EPB cannot support DMA addresses > 40-bit.
14109          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14110          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14111          * do DMA address check in tg3_start_xmit().
14112          */
14113         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14114                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14115         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14116                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14117 #ifdef CONFIG_HIGHMEM
14118                 dma_mask = DMA_BIT_MASK(64);
14119 #endif
14120         } else
14121                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14122
14123         /* Configure DMA attributes. */
14124         if (dma_mask > DMA_BIT_MASK(32)) {
14125                 err = pci_set_dma_mask(pdev, dma_mask);
14126                 if (!err) {
14127                         dev->features |= NETIF_F_HIGHDMA;
14128                         err = pci_set_consistent_dma_mask(pdev,
14129                                                           persist_dma_mask);
14130                         if (err < 0) {
14131                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14132                                        "DMA for consistent allocations\n");
14133                                 goto err_out_iounmap;
14134                         }
14135                 }
14136         }
14137         if (err || dma_mask == DMA_BIT_MASK(32)) {
14138                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14139                 if (err) {
14140                         printk(KERN_ERR PFX "No usable DMA configuration, "
14141                                "aborting.\n");
14142                         goto err_out_iounmap;
14143                 }
14144         }
14145
14146         tg3_init_bufmgr_config(tp);
14147
14148         /* Selectively allow TSO based on operating conditions */
14149         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14150             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14151                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14152         else {
14153                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14154                 tp->fw_needed = NULL;
14155         }
14156
14157         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14158                 tp->fw_needed = FIRMWARE_TG3;
14159
14160         /* TSO is on by default on chips that support hardware TSO.
14161          * Firmware TSO on older chips gives lower performance, so it
14162          * is off by default, but can be enabled using ethtool.
14163          */
14164         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14165             (dev->features & NETIF_F_IP_CSUM))
14166                 dev->features |= NETIF_F_TSO;
14167
14168         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14169             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14170                 if (dev->features & NETIF_F_IPV6_CSUM)
14171                         dev->features |= NETIF_F_TSO6;
14172                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14173                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14174                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14175                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14176                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14177                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14178                         dev->features |= NETIF_F_TSO_ECN;
14179         }
14180
14181         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14182             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14183             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14184                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14185                 tp->rx_pending = 63;
14186         }
14187
14188         err = tg3_get_device_address(tp);
14189         if (err) {
14190                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14191                        "aborting.\n");
14192                 goto err_out_fw;
14193         }
14194
14195         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14196                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14197                 if (!tp->aperegs) {
14198                         printk(KERN_ERR PFX "Cannot map APE registers, "
14199                                "aborting.\n");
14200                         err = -ENOMEM;
14201                         goto err_out_fw;
14202                 }
14203
14204                 tg3_ape_lock_init(tp);
14205
14206                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14207                         tg3_read_dash_ver(tp);
14208         }
14209
14210         /*
14211          * Reset chip in case UNDI or EFI driver did not shutdown
14212          * DMA self test will enable WDMAC and we'll see (spurious)
14213          * pending DMA on the PCI bus at that point.
14214          */
14215         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14216             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14217                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14218                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14219         }
14220
14221         err = tg3_test_dma(tp);
14222         if (err) {
14223                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14224                 goto err_out_apeunmap;
14225         }
14226
14227         /* flow control autonegotiation is default behavior */
14228         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14229         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14230
14231         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14232         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14233         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14234         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14235                 struct tg3_napi *tnapi = &tp->napi[i];
14236
14237                 tnapi->tp = tp;
14238                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14239
14240                 tnapi->int_mbox = intmbx;
14241                 if (i < 4)
14242                         intmbx += 0x8;
14243                 else
14244                         intmbx += 0x4;
14245
14246                 tnapi->consmbox = rcvmbx;
14247                 tnapi->prodmbox = sndmbx;
14248
14249                 if (i) {
14250                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14251                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14252                 } else {
14253                         tnapi->coal_now = HOSTCC_MODE_NOW;
14254                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14255                 }
14256
14257                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14258                         break;
14259
14260                 /*
14261                  * If we support MSIX, we'll be using RSS.  If we're using
14262                  * RSS, the first vector only handles link interrupts and the
14263                  * remaining vectors handle rx and tx interrupts.  Reuse the
14264                  * mailbox values for the next iteration.  The values we setup
14265                  * above are still useful for the single vectored mode.
14266                  */
14267                 if (!i)
14268                         continue;
14269
14270                 rcvmbx += 0x8;
14271
14272                 if (sndmbx & 0x4)
14273                         sndmbx -= 0x4;
14274                 else
14275                         sndmbx += 0xc;
14276         }
14277
14278         tg3_init_coal(tp);
14279
14280         pci_set_drvdata(pdev, dev);
14281
14282         err = register_netdev(dev);
14283         if (err) {
14284                 printk(KERN_ERR PFX "Cannot register net device, "
14285                        "aborting.\n");
14286                 goto err_out_apeunmap;
14287         }
14288
14289         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14290                dev->name,
14291                tp->board_part_number,
14292                tp->pci_chip_rev_id,
14293                tg3_bus_string(tp, str),
14294                dev->dev_addr);
14295
14296         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14297                 struct phy_device *phydev;
14298                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14299                 printk(KERN_INFO
14300                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14301                        tp->dev->name, phydev->drv->name,
14302                        dev_name(&phydev->dev));
14303         } else
14304                 printk(KERN_INFO
14305                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14306                        tp->dev->name, tg3_phy_string(tp),
14307                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14308                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14309                          "10/100/1000Base-T")),
14310                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14311
14312         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14313                dev->name,
14314                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14315                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14316                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14317                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14318                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14319         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14320                dev->name, tp->dma_rwctrl,
14321                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14322                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14323
14324         return 0;
14325
14326 err_out_apeunmap:
14327         if (tp->aperegs) {
14328                 iounmap(tp->aperegs);
14329                 tp->aperegs = NULL;
14330         }
14331
14332 err_out_fw:
14333         if (tp->fw)
14334                 release_firmware(tp->fw);
14335
14336 err_out_iounmap:
14337         if (tp->regs) {
14338                 iounmap(tp->regs);
14339                 tp->regs = NULL;
14340         }
14341
14342 err_out_free_dev:
14343         free_netdev(dev);
14344
14345 err_out_free_res:
14346         pci_release_regions(pdev);
14347
14348 err_out_disable_pdev:
14349         pci_disable_device(pdev);
14350         pci_set_drvdata(pdev, NULL);
14351         return err;
14352 }
14353
14354 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14355 {
14356         struct net_device *dev = pci_get_drvdata(pdev);
14357
14358         if (dev) {
14359                 struct tg3 *tp = netdev_priv(dev);
14360
14361                 if (tp->fw)
14362                         release_firmware(tp->fw);
14363
14364                 flush_scheduled_work();
14365
14366                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14367                         tg3_phy_fini(tp);
14368                         tg3_mdio_fini(tp);
14369                 }
14370
14371                 unregister_netdev(dev);
14372                 if (tp->aperegs) {
14373                         iounmap(tp->aperegs);
14374                         tp->aperegs = NULL;
14375                 }
14376                 if (tp->regs) {
14377                         iounmap(tp->regs);
14378                         tp->regs = NULL;
14379                 }
14380                 free_netdev(dev);
14381                 pci_release_regions(pdev);
14382                 pci_disable_device(pdev);
14383                 pci_set_drvdata(pdev, NULL);
14384         }
14385 }
14386
14387 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14388 {
14389         struct net_device *dev = pci_get_drvdata(pdev);
14390         struct tg3 *tp = netdev_priv(dev);
14391         pci_power_t target_state;
14392         int err;
14393
14394         /* PCI register 4 needs to be saved whether netif_running() or not.
14395          * MSI address and data need to be saved if using MSI and
14396          * netif_running().
14397          */
14398         pci_save_state(pdev);
14399
14400         if (!netif_running(dev))
14401                 return 0;
14402
14403         flush_scheduled_work();
14404         tg3_phy_stop(tp);
14405         tg3_netif_stop(tp);
14406
14407         del_timer_sync(&tp->timer);
14408
14409         tg3_full_lock(tp, 1);
14410         tg3_disable_ints(tp);
14411         tg3_full_unlock(tp);
14412
14413         netif_device_detach(dev);
14414
14415         tg3_full_lock(tp, 0);
14416         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14417         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14418         tg3_full_unlock(tp);
14419
14420         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14421
14422         err = tg3_set_power_state(tp, target_state);
14423         if (err) {
14424                 int err2;
14425
14426                 tg3_full_lock(tp, 0);
14427
14428                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14429                 err2 = tg3_restart_hw(tp, 1);
14430                 if (err2)
14431                         goto out;
14432
14433                 tp->timer.expires = jiffies + tp->timer_offset;
14434                 add_timer(&tp->timer);
14435
14436                 netif_device_attach(dev);
14437                 tg3_netif_start(tp);
14438
14439 out:
14440                 tg3_full_unlock(tp);
14441
14442                 if (!err2)
14443                         tg3_phy_start(tp);
14444         }
14445
14446         return err;
14447 }
14448
14449 static int tg3_resume(struct pci_dev *pdev)
14450 {
14451         struct net_device *dev = pci_get_drvdata(pdev);
14452         struct tg3 *tp = netdev_priv(dev);
14453         int err;
14454
14455         pci_restore_state(tp->pdev);
14456
14457         if (!netif_running(dev))
14458                 return 0;
14459
14460         err = tg3_set_power_state(tp, PCI_D0);
14461         if (err)
14462                 return err;
14463
14464         netif_device_attach(dev);
14465
14466         tg3_full_lock(tp, 0);
14467
14468         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14469         err = tg3_restart_hw(tp, 1);
14470         if (err)
14471                 goto out;
14472
14473         tp->timer.expires = jiffies + tp->timer_offset;
14474         add_timer(&tp->timer);
14475
14476         tg3_netif_start(tp);
14477
14478 out:
14479         tg3_full_unlock(tp);
14480
14481         if (!err)
14482                 tg3_phy_start(tp);
14483
14484         return err;
14485 }
14486
14487 static struct pci_driver tg3_driver = {
14488         .name           = DRV_MODULE_NAME,
14489         .id_table       = tg3_pci_tbl,
14490         .probe          = tg3_init_one,
14491         .remove         = __devexit_p(tg3_remove_one),
14492         .suspend        = tg3_suspend,
14493         .resume         = tg3_resume
14494 };
14495
14496 static int __init tg3_init(void)
14497 {
14498         return pci_register_driver(&tg3_driver);
14499 }
14500
14501 static void __exit tg3_cleanup(void)
14502 {
14503         pci_unregister_driver(&tg3_driver);
14504 }
14505
14506 module_init(tg3_init);
14507 module_exit(tg3_cleanup);