drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.101"
  72 #define DRV_MODULE_RELDATE      "August 28, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 120                                  TG3_RX_RING_SIZE)
 121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 122                                  TG3_RX_JUMBO_RING_SIZE)
 123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RCB_RING_SIZE(tp))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define TG3_DMA_BYTE_ENAB               64
 130
 131 #define TG3_RX_STD_DMA_SZ               1536
 132 #define TG3_RX_JMB_DMA_SZ               9046
 133
 134 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 135
 136 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 137 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 138
 139 /* minimum number of free TX descriptors required to wake up TX process */
 140 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 141
 142 #define TG3_RAW_IP_ALIGN 2
 143
 144 /* number of ETHTOOL_GSTATS u64's */
 145 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 146
 147 #define TG3_NUM_TEST            6
 148
 149 #define FIRMWARE_TG3            "tigon/tg3.bin"
 150 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 151 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 152
 153 static char version[] __devinitdata =
 154         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 155
 156 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 157 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 158 MODULE_LICENSE("GPL");
 159 MODULE_VERSION(DRV_MODULE_VERSION);
 160 MODULE_FIRMWARE(FIRMWARE_TG3);
 161 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 162 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 163
 164 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 165
 166 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 167 module_param(tg3_debug, int, 0);
 168 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 169
 170 static struct pci_device_id tg3_pci_tbl[] = {
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 244         {}
 245 };
 246
 247 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 248
 249 static const struct {
 250         const char string[ETH_GSTRING_LEN];
 251 } ethtool_stats_keys[TG3_NUM_STATS] = {
 252         { "rx_octets" },
 253         { "rx_fragments" },
 254         { "rx_ucast_packets" },
 255         { "rx_mcast_packets" },
 256         { "rx_bcast_packets" },
 257         { "rx_fcs_errors" },
 258         { "rx_align_errors" },
 259         { "rx_xon_pause_rcvd" },
 260         { "rx_xoff_pause_rcvd" },
 261         { "rx_mac_ctrl_rcvd" },
 262         { "rx_xoff_entered" },
 263         { "rx_frame_too_long_errors" },
 264         { "rx_jabbers" },
 265         { "rx_undersize_packets" },
 266         { "rx_in_length_errors" },
 267         { "rx_out_length_errors" },
 268         { "rx_64_or_less_octet_packets" },
 269         { "rx_65_to_127_octet_packets" },
 270         { "rx_128_to_255_octet_packets" },
 271         { "rx_256_to_511_octet_packets" },
 272         { "rx_512_to_1023_octet_packets" },
 273         { "rx_1024_to_1522_octet_packets" },
 274         { "rx_1523_to_2047_octet_packets" },
 275         { "rx_2048_to_4095_octet_packets" },
 276         { "rx_4096_to_8191_octet_packets" },
 277         { "rx_8192_to_9022_octet_packets" },
 278
 279         { "tx_octets" },
 280         { "tx_collisions" },
 281
 282         { "tx_xon_sent" },
 283         { "tx_xoff_sent" },
 284         { "tx_flow_control" },
 285         { "tx_mac_errors" },
 286         { "tx_single_collisions" },
 287         { "tx_mult_collisions" },
 288         { "tx_deferred" },
 289         { "tx_excessive_collisions" },
 290         { "tx_late_collisions" },
 291         { "tx_collide_2times" },
 292         { "tx_collide_3times" },
 293         { "tx_collide_4times" },
 294         { "tx_collide_5times" },
 295         { "tx_collide_6times" },
 296         { "tx_collide_7times" },
 297         { "tx_collide_8times" },
 298         { "tx_collide_9times" },
 299         { "tx_collide_10times" },
 300         { "tx_collide_11times" },
 301         { "tx_collide_12times" },
 302         { "tx_collide_13times" },
 303         { "tx_collide_14times" },
 304         { "tx_collide_15times" },
 305         { "tx_ucast_packets" },
 306         { "tx_mcast_packets" },
 307         { "tx_bcast_packets" },
 308         { "tx_carrier_sense_errors" },
 309         { "tx_discards" },
 310         { "tx_errors" },
 311
 312         { "dma_writeq_full" },
 313         { "dma_write_prioq_full" },
 314         { "rxbds_empty" },
 315         { "rx_discards" },
 316         { "rx_errors" },
 317         { "rx_threshold_hit" },
 318
 319         { "dma_readq_full" },
 320         { "dma_read_prioq_full" },
 321         { "tx_comp_queue_full" },
 322
 323         { "ring_set_send_prod_index" },
 324         { "ring_status_update" },
 325         { "nic_irqs" },
 326         { "nic_avoided_irqs" },
 327         { "nic_tx_threshold_hit" }
 328 };
 329
 330 static const struct {
 331         const char string[ETH_GSTRING_LEN];
 332 } ethtool_test_keys[TG3_NUM_TEST] = {
 333         { "nvram test     (online) " },
 334         { "link test      (online) " },
 335         { "register test  (offline)" },
 336         { "memory test    (offline)" },
 337         { "loopback test  (offline)" },
 338         { "interrupt test (offline)" },
 339 };
 340
 341 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 342 {
 343         writel(val, tp->regs + off);
 344 }
 345
 346 static u32 tg3_read32(struct tg3 *tp, u32 off)
 347 {
 348         return (readl(tp->regs + off));
 349 }
 350
 351 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         writel(val, tp->aperegs + off);
 354 }
 355
 356 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 357 {
 358         return (readl(tp->aperegs + off));
 359 }
 360
 361 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         unsigned long flags;
 364
 365         spin_lock_irqsave(&tp->indirect_lock, flags);
 366         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 367         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 368         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 369 }
 370
 371 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 372 {
 373         writel(val, tp->regs + off);
 374         readl(tp->regs + off);
 375 }
 376
 377 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 378 {
 379         unsigned long flags;
 380         u32 val;
 381
 382         spin_lock_irqsave(&tp->indirect_lock, flags);
 383         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 384         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 385         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 386         return val;
 387 }
 388
 389 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 390 {
 391         unsigned long flags;
 392
 393         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 394                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 395                                        TG3_64BIT_REG_LOW, val);
 396                 return;
 397         }
 398         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 399                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 400                                        TG3_64BIT_REG_LOW, val);
 401                 return;
 402         }
 403
 404         spin_lock_irqsave(&tp->indirect_lock, flags);
 405         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 407         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 408
 409         /* In indirect mode when disabling interrupts, we also need
 410          * to clear the interrupt bit in the GRC local ctrl register.
 411          */
 412         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 413             (val == 0x1)) {
 414                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 415                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 416         }
 417 }
 418
 419 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 420 {
 421         unsigned long flags;
 422         u32 val;
 423
 424         spin_lock_irqsave(&tp->indirect_lock, flags);
 425         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 426         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 427         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 428         return val;
 429 }
 430
 431 /* usec_wait specifies the wait time in usec when writing to certain registers
 432  * where it is unsafe to read back the register without some delay.
 433  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 434  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 435  */
 436 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 437 {
 438         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 439             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 440                 /* Non-posted methods */
 441                 tp->write32(tp, off, val);
 442         else {
 443                 /* Posted method */
 444                 tg3_write32(tp, off, val);
 445                 if (usec_wait)
 446                         udelay(usec_wait);
 447                 tp->read32(tp, off);
 448         }
 449         /* Wait again after the read for the posted method to guarantee that
 450          * the wait time is met.
 451          */
 452         if (usec_wait)
 453                 udelay(usec_wait);
 454 }
 455
 456 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 457 {
 458         tp->write32_mbox(tp, off, val);
 459         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 460             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 461                 tp->read32_mbox(tp, off);
 462 }
 463
 464 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 465 {
 466         void __iomem *mbox = tp->regs + off;
 467         writel(val, mbox);
 468         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 469                 writel(val, mbox);
 470         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 471                 readl(mbox);
 472 }
 473
 474 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 475 {
 476         return (readl(tp->regs + off + GRCMBOX_BASE));
 477 }
 478
 479 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 480 {
 481         writel(val, tp->regs + off + GRCMBOX_BASE);
 482 }
 483
 484 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 485 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 486 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 487 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 488 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 489
 490 #define tw32(reg,val)           tp->write32(tp, reg, val)
 491 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 492 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 493 #define tr32(reg)               tp->read32(tp, reg)
 494
 495 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 496 {
 497         unsigned long flags;
 498
 499         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 500             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 501                 return;
 502
 503         spin_lock_irqsave(&tp->indirect_lock, flags);
 504         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 505                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 507
 508                 /* Always leave this as zero. */
 509                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 510         } else {
 511                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 512                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 513
 514                 /* Always leave this as zero. */
 515                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 516         }
 517         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 518 }
 519
 520 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 521 {
 522         unsigned long flags;
 523
 524         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 525             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 526                 *val = 0;
 527                 return;
 528         }
 529
 530         spin_lock_irqsave(&tp->indirect_lock, flags);
 531         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 532                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 533                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 534
 535                 /* Always leave this as zero. */
 536                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 537         } else {
 538                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 539                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 540
 541                 /* Always leave this as zero. */
 542                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 543         }
 544         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 545 }
 546
 547 static void tg3_ape_lock_init(struct tg3 *tp)
 548 {
 549         int i;
 550
 551         /* Make sure the driver hasn't any stale locks. */
 552         for (i = 0; i < 8; i++)
 553                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 554                                 APE_LOCK_GRANT_DRIVER);
 555 }
 556
 557 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 558 {
 559         int i, off;
 560         int ret = 0;
 561         u32 status;
 562
 563         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 564                 return 0;
 565
 566         switch (locknum) {
 567                 case TG3_APE_LOCK_GRC:
 568                 case TG3_APE_LOCK_MEM:
 569                         break;
 570                 default:
 571                         return -EINVAL;
 572         }
 573
 574         off = 4 * locknum;
 575
 576         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 577
 578         /* Wait for up to 1 millisecond to acquire lock. */
 579         for (i = 0; i < 100; i++) {
 580                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 581                 if (status == APE_LOCK_GRANT_DRIVER)
 582                         break;
 583                 udelay(10);
 584         }
 585
 586         if (status != APE_LOCK_GRANT_DRIVER) {
 587                 /* Revoke the lock request. */
 588                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 589                                 APE_LOCK_GRANT_DRIVER);
 590
 591                 ret = -EBUSY;
 592         }
 593
 594         return ret;
 595 }
 596
 597 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 598 {
 599         int off;
 600
 601         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 602                 return;
 603
 604         switch (locknum) {
 605                 case TG3_APE_LOCK_GRC:
 606                 case TG3_APE_LOCK_MEM:
 607                         break;
 608                 default:
 609                         return;
 610         }
 611
 612         off = 4 * locknum;
 613         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 614 }
 615
 616 static void tg3_disable_ints(struct tg3 *tp)
 617 {
 618         int i;
 619
 620         tw32(TG3PCI_MISC_HOST_CTRL,
 621              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 622         for (i = 0; i < tp->irq_max; i++)
 623                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 624 }
 625
 626 static void tg3_enable_ints(struct tg3 *tp)
 627 {
 628         int i;
 629         u32 coal_now = 0;
 630
 631         tp->irq_sync = 0;
 632         wmb();
 633
 634         tw32(TG3PCI_MISC_HOST_CTRL,
 635              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 636
 637         for (i = 0; i < tp->irq_cnt; i++) {
 638                 struct tg3_napi *tnapi = &tp->napi[i];
 639                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 640                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 641                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 642
 643                 coal_now |= tnapi->coal_now;
 644         }
 645
 646         /* Force an initial interrupt */
 647         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 648             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 649                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 650         else
 651                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 652                      HOSTCC_MODE_ENABLE | coal_now);
 653 }
 654
 655 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 656 {
 657         struct tg3 *tp = tnapi->tp;
 658         struct tg3_hw_status *sblk = tnapi->hw_status;
 659         unsigned int work_exists = 0;
 660
 661         /* check for phy events */
 662         if (!(tp->tg3_flags &
 663               (TG3_FLAG_USE_LINKCHG_REG |
 664                TG3_FLAG_POLL_SERDES))) {
 665                 if (sblk->status & SD_STATUS_LINK_CHG)
 666                         work_exists = 1;
 667         }
 668         /* check for RX/TX work to do */
 669         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 670             sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
 671                 work_exists = 1;
 672
 673         return work_exists;
 674 }
 675
 676 /* tg3_int_reenable
 677  *  similar to tg3_enable_ints, but it accurately determines whether there
 678  *  is new work pending and can return without flushing the PIO write
 679  *  which reenables interrupts
 680  */
 681 static void tg3_int_reenable(struct tg3_napi *tnapi)
 682 {
 683         struct tg3 *tp = tnapi->tp;
 684
 685         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 686         mmiowb();
 687
 688         /* When doing tagged status, this work check is unnecessary.
 689          * The last_tag we write above tells the chip which piece of
 690          * work we've completed.
 691          */
 692         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 693             tg3_has_work(tnapi))
 694                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 695                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 696 }
 697
 698 static void tg3_napi_disable(struct tg3 *tp)
 699 {
 700         int i;
 701
 702         for (i = tp->irq_cnt - 1; i >= 0; i--)
 703                 napi_disable(&tp->napi[i].napi);
 704 }
 705
 706 static void tg3_napi_enable(struct tg3 *tp)
 707 {
 708         int i;
 709
 710         for (i = 0; i < tp->irq_cnt; i++)
 711                 napi_enable(&tp->napi[i].napi);
 712 }
 713
 714 static inline void tg3_netif_stop(struct tg3 *tp)
 715 {
 716         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 717         tg3_napi_disable(tp);
 718         netif_tx_disable(tp->dev);
 719 }
 720
 721 static inline void tg3_netif_start(struct tg3 *tp)
 722 {
 723         /* NOTE: unconditional netif_tx_wake_all_queues is only
 724          * appropriate so long as all callers are assured to
 725          * have free tx slots (such as after tg3_init_hw)
 726          */
 727         netif_tx_wake_all_queues(tp->dev);
 728
 729         tg3_napi_enable(tp);
 730         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 731         tg3_enable_ints(tp);
 732 }
 733
 734 static void tg3_switch_clocks(struct tg3 *tp)
 735 {
 736         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 737         u32 orig_clock_ctrl;
 738
 739         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 740             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 741                 return;
 742
 743         orig_clock_ctrl = clock_ctrl;
 744         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 745                        CLOCK_CTRL_CLKRUN_OENABLE |
 746                        0x1f);
 747         tp->pci_clock_ctrl = clock_ctrl;
 748
 749         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 750                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 751                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 752                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 753                 }
 754         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 755                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 756                             clock_ctrl |
 757                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 758                             40);
 759                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 760                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 761                             40);
 762         }
 763         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 764 }
 765
 766 #define PHY_BUSY_LOOPS  5000
 767
 768 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 769 {
 770         u32 frame_val;
 771         unsigned int loops;
 772         int ret;
 773
 774         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 775                 tw32_f(MAC_MI_MODE,
 776                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 777                 udelay(80);
 778         }
 779
 780         *val = 0x0;
 781
 782         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 783                       MI_COM_PHY_ADDR_MASK);
 784         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 785                       MI_COM_REG_ADDR_MASK);
 786         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 787
 788         tw32_f(MAC_MI_COM, frame_val);
 789
 790         loops = PHY_BUSY_LOOPS;
 791         while (loops != 0) {
 792                 udelay(10);
 793                 frame_val = tr32(MAC_MI_COM);
 794
 795                 if ((frame_val & MI_COM_BUSY) == 0) {
 796                         udelay(5);
 797                         frame_val = tr32(MAC_MI_COM);
 798                         break;
 799                 }
 800                 loops -= 1;
 801         }
 802
 803         ret = -EBUSY;
 804         if (loops != 0) {
 805                 *val = frame_val & MI_COM_DATA_MASK;
 806                 ret = 0;
 807         }
 808
 809         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 810                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 811                 udelay(80);
 812         }
 813
 814         return ret;
 815 }
 816
 817 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 818 {
 819         u32 frame_val;
 820         unsigned int loops;
 821         int ret;
 822
 823         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 824             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 825                 return 0;
 826
 827         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 828                 tw32_f(MAC_MI_MODE,
 829                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 830                 udelay(80);
 831         }
 832
 833         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 834                       MI_COM_PHY_ADDR_MASK);
 835         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 836                       MI_COM_REG_ADDR_MASK);
 837         frame_val |= (val & MI_COM_DATA_MASK);
 838         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 839
 840         tw32_f(MAC_MI_COM, frame_val);
 841
 842         loops = PHY_BUSY_LOOPS;
 843         while (loops != 0) {
 844                 udelay(10);
 845                 frame_val = tr32(MAC_MI_COM);
 846                 if ((frame_val & MI_COM_BUSY) == 0) {
 847                         udelay(5);
 848                         frame_val = tr32(MAC_MI_COM);
 849                         break;
 850                 }
 851                 loops -= 1;
 852         }
 853
 854         ret = -EBUSY;
 855         if (loops != 0)
 856                 ret = 0;
 857
 858         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 859                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 860                 udelay(80);
 861         }
 862
 863         return ret;
 864 }
 865
 866 static int tg3_bmcr_reset(struct tg3 *tp)
 867 {
 868         u32 phy_control;
 869         int limit, err;
 870
 871         /* OK, reset it, and poll the BMCR_RESET bit until it
 872          * clears or we time out.
 873          */
 874         phy_control = BMCR_RESET;
 875         err = tg3_writephy(tp, MII_BMCR, phy_control);
 876         if (err != 0)
 877                 return -EBUSY;
 878
 879         limit = 5000;
 880         while (limit--) {
 881                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 882                 if (err != 0)
 883                         return -EBUSY;
 884
 885                 if ((phy_control & BMCR_RESET) == 0) {
 886                         udelay(40);
 887                         break;
 888                 }
 889                 udelay(10);
 890         }
 891         if (limit < 0)
 892                 return -EBUSY;
 893
 894         return 0;
 895 }
 896
 897 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 898 {
 899         struct tg3 *tp = bp->priv;
 900         u32 val;
 901
 902         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 903                 return -EAGAIN;
 904
 905         if (tg3_readphy(tp, reg, &val))
 906                 return -EIO;
 907
 908         return val;
 909 }
 910
 911 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 912 {
 913         struct tg3 *tp = bp->priv;
 914
 915         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 916                 return -EAGAIN;
 917
 918         if (tg3_writephy(tp, reg, val))
 919                 return -EIO;
 920
 921         return 0;
 922 }
 923
 924 static int tg3_mdio_reset(struct mii_bus *bp)
 925 {
 926         return 0;
 927 }
 928
 929 static void tg3_mdio_config_5785(struct tg3 *tp)
 930 {
 931         u32 val;
 932         struct phy_device *phydev;
 933
 934         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 935         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 936         case TG3_PHY_ID_BCM50610:
 937                 val = MAC_PHYCFG2_50610_LED_MODES;
 938                 break;
 939         case TG3_PHY_ID_BCMAC131:
 940                 val = MAC_PHYCFG2_AC131_LED_MODES;
 941                 break;
 942         case TG3_PHY_ID_RTL8211C:
 943                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 944                 break;
 945         case TG3_PHY_ID_RTL8201E:
 946                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 947                 break;
 948         default:
 949                 return;
 950         }
 951
 952         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 953                 tw32(MAC_PHYCFG2, val);
 954
 955                 val = tr32(MAC_PHYCFG1);
 956                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 957                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 958                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 959                 tw32(MAC_PHYCFG1, val);
 960
 961                 return;
 962         }
 963
 964         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 965                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 966                        MAC_PHYCFG2_FMODE_MASK_MASK |
 967                        MAC_PHYCFG2_GMODE_MASK_MASK |
 968                        MAC_PHYCFG2_ACT_MASK_MASK   |
 969                        MAC_PHYCFG2_QUAL_MASK_MASK |
 970                        MAC_PHYCFG2_INBAND_ENABLE;
 971
 972         tw32(MAC_PHYCFG2, val);
 973
 974         val = tr32(MAC_PHYCFG1);
 975         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 976                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 977         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 978                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 979                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 980                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 981                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 982         }
 983         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 984                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 985         tw32(MAC_PHYCFG1, val);
 986
 987         val = tr32(MAC_EXT_RGMII_MODE);
 988         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 989                  MAC_RGMII_MODE_RX_QUALITY |
 990                  MAC_RGMII_MODE_RX_ACTIVITY |
 991                  MAC_RGMII_MODE_RX_ENG_DET |
 992                  MAC_RGMII_MODE_TX_ENABLE |
 993                  MAC_RGMII_MODE_TX_LOWPWR |
 994                  MAC_RGMII_MODE_TX_RESET);
 995         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 996                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 997                         val |= MAC_RGMII_MODE_RX_INT_B |
 998                                MAC_RGMII_MODE_RX_QUALITY |
 999                                MAC_RGMII_MODE_RX_ACTIVITY |
1000                                MAC_RGMII_MODE_RX_ENG_DET;
1001                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1002                         val |= MAC_RGMII_MODE_TX_ENABLE |
1003                                MAC_RGMII_MODE_TX_LOWPWR |
1004                                MAC_RGMII_MODE_TX_RESET;
1005         }
1006         tw32(MAC_EXT_RGMII_MODE, val);
1007 }
1008
1009 static void tg3_mdio_start(struct tg3 *tp)
1010 {
1011         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1012                 mutex_lock(&tp->mdio_bus->mdio_lock);
1013                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1014                 mutex_unlock(&tp->mdio_bus->mdio_lock);
1015         }
1016
1017         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1018         tw32_f(MAC_MI_MODE, tp->mi_mode);
1019         udelay(80);
1020
1021         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1022             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1023                 tg3_mdio_config_5785(tp);
1024 }
1025
1026 static void tg3_mdio_stop(struct tg3 *tp)
1027 {
1028         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1029                 mutex_lock(&tp->mdio_bus->mdio_lock);
1030                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
1031                 mutex_unlock(&tp->mdio_bus->mdio_lock);
1032         }
1033 }
1034
1035 static int tg3_mdio_init(struct tg3 *tp)
1036 {
1037         int i;
1038         u32 reg;
1039         struct phy_device *phydev;
1040
1041         tg3_mdio_start(tp);
1042
1043         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1044             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1045                 return 0;
1046
1047         tp->mdio_bus = mdiobus_alloc();
1048         if (tp->mdio_bus == NULL)
1049                 return -ENOMEM;
1050
1051         tp->mdio_bus->name     = "tg3 mdio bus";
1052         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1053                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1054         tp->mdio_bus->priv     = tp;
1055         tp->mdio_bus->parent   = &tp->pdev->dev;
1056         tp->mdio_bus->read     = &tg3_mdio_read;
1057         tp->mdio_bus->write    = &tg3_mdio_write;
1058         tp->mdio_bus->reset    = &tg3_mdio_reset;
1059         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1060         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1061
1062         for (i = 0; i < PHY_MAX_ADDR; i++)
1063                 tp->mdio_bus->irq[i] = PHY_POLL;
1064
1065         /* The bus registration will look for all the PHYs on the mdio bus.
1066          * Unfortunately, it does not ensure the PHY is powered up before
1067          * accessing the PHY ID registers.  A chip reset is the
1068          * quickest way to bring the device back to an operational state..
1069          */
1070         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1071                 tg3_bmcr_reset(tp);
1072
1073         i = mdiobus_register(tp->mdio_bus);
1074         if (i) {
1075                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1076                         tp->dev->name, i);
1077                 mdiobus_free(tp->mdio_bus);
1078                 return i;
1079         }
1080
1081         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1082
1083         if (!phydev || !phydev->drv) {
1084                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1085                 mdiobus_unregister(tp->mdio_bus);
1086                 mdiobus_free(tp->mdio_bus);
1087                 return -ENODEV;
1088         }
1089
1090         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1091         case TG3_PHY_ID_BCM57780:
1092                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1093                 break;
1094         case TG3_PHY_ID_BCM50610:
1095                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1096                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1097                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1098                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1099                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1100                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1101                 /* fallthru */
1102         case TG3_PHY_ID_RTL8211C:
1103                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1104                 break;
1105         case TG3_PHY_ID_RTL8201E:
1106         case TG3_PHY_ID_BCMAC131:
1107                 phydev->interface = PHY_INTERFACE_MODE_MII;
1108                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1109                 break;
1110         }
1111
1112         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1113
1114         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1115                 tg3_mdio_config_5785(tp);
1116
1117         return 0;
1118 }
1119
1120 static void tg3_mdio_fini(struct tg3 *tp)
1121 {
1122         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1123                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1124                 mdiobus_unregister(tp->mdio_bus);
1125                 mdiobus_free(tp->mdio_bus);
1126                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1127         }
1128 }
1129
1130 /* tp->lock is held. */
1131 static inline void tg3_generate_fw_event(struct tg3 *tp)
1132 {
1133         u32 val;
1134
1135         val = tr32(GRC_RX_CPU_EVENT);
1136         val |= GRC_RX_CPU_DRIVER_EVENT;
1137         tw32_f(GRC_RX_CPU_EVENT, val);
1138
1139         tp->last_event_jiffies = jiffies;
1140 }
1141
1142 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1143
1144 /* tp->lock is held. */
1145 static void tg3_wait_for_event_ack(struct tg3 *tp)
1146 {
1147         int i;
1148         unsigned int delay_cnt;
1149         long time_remain;
1150
1151         /* If enough time has passed, no wait is necessary. */
1152         time_remain = (long)(tp->last_event_jiffies + 1 +
1153                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1154                       (long)jiffies;
1155         if (time_remain < 0)
1156                 return;
1157
1158         /* Check if we can shorten the wait time. */
1159         delay_cnt = jiffies_to_usecs(time_remain);
1160         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1161                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1162         delay_cnt = (delay_cnt >> 3) + 1;
1163
1164         for (i = 0; i < delay_cnt; i++) {
1165                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1166                         break;
1167                 udelay(8);
1168         }
1169 }
1170
1171 /* tp->lock is held. */
1172 static void tg3_ump_link_report(struct tg3 *tp)
1173 {
1174         u32 reg;
1175         u32 val;
1176
1177         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1178             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1179                 return;
1180
1181         tg3_wait_for_event_ack(tp);
1182
1183         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1184
1185         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1186
1187         val = 0;
1188         if (!tg3_readphy(tp, MII_BMCR, &reg))
1189                 val = reg << 16;
1190         if (!tg3_readphy(tp, MII_BMSR, &reg))
1191                 val |= (reg & 0xffff);
1192         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1193
1194         val = 0;
1195         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1196                 val = reg << 16;
1197         if (!tg3_readphy(tp, MII_LPA, &reg))
1198                 val |= (reg & 0xffff);
1199         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1200
1201         val = 0;
1202         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1203                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1204                         val = reg << 16;
1205                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1206                         val |= (reg & 0xffff);
1207         }
1208         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1209
1210         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1211                 val = reg << 16;
1212         else
1213                 val = 0;
1214         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1215
1216         tg3_generate_fw_event(tp);
1217 }
1218
1219 static void tg3_link_report(struct tg3 *tp)
1220 {
1221         if (!netif_carrier_ok(tp->dev)) {
1222                 if (netif_msg_link(tp))
1223                         printk(KERN_INFO PFX "%s: Link is down.\n",
1224                                tp->dev->name);
1225                 tg3_ump_link_report(tp);
1226         } else if (netif_msg_link(tp)) {
1227                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1228                        tp->dev->name,
1229                        (tp->link_config.active_speed == SPEED_1000 ?
1230                         1000 :
1231                         (tp->link_config.active_speed == SPEED_100 ?
1232                          100 : 10)),
1233                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1234                         "full" : "half"));
1235
1236                 printk(KERN_INFO PFX
1237                        "%s: Flow control is %s for TX and %s for RX.\n",
1238                        tp->dev->name,
1239                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1240                        "on" : "off",
1241                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1242                        "on" : "off");
1243                 tg3_ump_link_report(tp);
1244         }
1245 }
1246
1247 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1248 {
1249         u16 miireg;
1250
1251         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1252                 miireg = ADVERTISE_PAUSE_CAP;
1253         else if (flow_ctrl & FLOW_CTRL_TX)
1254                 miireg = ADVERTISE_PAUSE_ASYM;
1255         else if (flow_ctrl & FLOW_CTRL_RX)
1256                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1257         else
1258                 miireg = 0;
1259
1260         return miireg;
1261 }
1262
1263 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1264 {
1265         u16 miireg;
1266
1267         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1268                 miireg = ADVERTISE_1000XPAUSE;
1269         else if (flow_ctrl & FLOW_CTRL_TX)
1270                 miireg = ADVERTISE_1000XPSE_ASYM;
1271         else if (flow_ctrl & FLOW_CTRL_RX)
1272                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1273         else
1274                 miireg = 0;
1275
1276         return miireg;
1277 }
1278
1279 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1280 {
1281         u8 cap = 0;
1282
1283         if (lcladv & ADVERTISE_1000XPAUSE) {
1284                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1285                         if (rmtadv & LPA_1000XPAUSE)
1286                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1287                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1288                                 cap = FLOW_CTRL_RX;
1289                 } else {
1290                         if (rmtadv & LPA_1000XPAUSE)
1291                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1292                 }
1293         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1294                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1295                         cap = FLOW_CTRL_TX;
1296         }
1297
1298         return cap;
1299 }
1300
1301 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1302 {
1303         u8 autoneg;
1304         u8 flowctrl = 0;
1305         u32 old_rx_mode = tp->rx_mode;
1306         u32 old_tx_mode = tp->tx_mode;
1307
1308         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1309                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1310         else
1311                 autoneg = tp->link_config.autoneg;
1312
1313         if (autoneg == AUTONEG_ENABLE &&
1314             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1315                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1316                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1317                 else
1318                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1319         } else
1320                 flowctrl = tp->link_config.flowctrl;
1321
1322         tp->link_config.active_flowctrl = flowctrl;
1323
1324         if (flowctrl & FLOW_CTRL_RX)
1325                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1326         else
1327                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1328
1329         if (old_rx_mode != tp->rx_mode)
1330                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1331
1332         if (flowctrl & FLOW_CTRL_TX)
1333                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1334         else
1335                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1336
1337         if (old_tx_mode != tp->tx_mode)
1338                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1339 }
1340
1341 static void tg3_adjust_link(struct net_device *dev)
1342 {
1343         u8 oldflowctrl, linkmesg = 0;
1344         u32 mac_mode, lcl_adv, rmt_adv;
1345         struct tg3 *tp = netdev_priv(dev);
1346         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1347
1348         spin_lock(&tp->lock);
1349
1350         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1351                                     MAC_MODE_HALF_DUPLEX);
1352
1353         oldflowctrl = tp->link_config.active_flowctrl;
1354
1355         if (phydev->link) {
1356                 lcl_adv = 0;
1357                 rmt_adv = 0;
1358
1359                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1360                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1361                 else
1362                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1363
1364                 if (phydev->duplex == DUPLEX_HALF)
1365                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1366                 else {
1367                         lcl_adv = tg3_advert_flowctrl_1000T(
1368                                   tp->link_config.flowctrl);
1369
1370                         if (phydev->pause)
1371                                 rmt_adv = LPA_PAUSE_CAP;
1372                         if (phydev->asym_pause)
1373                                 rmt_adv |= LPA_PAUSE_ASYM;
1374                 }
1375
1376                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1377         } else
1378                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1379
1380         if (mac_mode != tp->mac_mode) {
1381                 tp->mac_mode = mac_mode;
1382                 tw32_f(MAC_MODE, tp->mac_mode);
1383                 udelay(40);
1384         }
1385
1386         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1387                 if (phydev->speed == SPEED_10)
1388                         tw32(MAC_MI_STAT,
1389                              MAC_MI_STAT_10MBPS_MODE |
1390                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1391                 else
1392                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1393         }
1394
1395         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1396                 tw32(MAC_TX_LENGTHS,
1397                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1398                       (6 << TX_LENGTHS_IPG_SHIFT) |
1399                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1400         else
1401                 tw32(MAC_TX_LENGTHS,
1402                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1403                       (6 << TX_LENGTHS_IPG_SHIFT) |
1404                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1405
1406         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1407             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1408             phydev->speed != tp->link_config.active_speed ||
1409             phydev->duplex != tp->link_config.active_duplex ||
1410             oldflowctrl != tp->link_config.active_flowctrl)
1411             linkmesg = 1;
1412
1413         tp->link_config.active_speed = phydev->speed;
1414         tp->link_config.active_duplex = phydev->duplex;
1415
1416         spin_unlock(&tp->lock);
1417
1418         if (linkmesg)
1419                 tg3_link_report(tp);
1420 }
1421
1422 static int tg3_phy_init(struct tg3 *tp)
1423 {
1424         struct phy_device *phydev;
1425
1426         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1427                 return 0;
1428
1429         /* Bring the PHY back to a known state. */
1430         tg3_bmcr_reset(tp);
1431
1432         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1433
1434         /* Attach the MAC to the PHY. */
1435         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1436                              phydev->dev_flags, phydev->interface);
1437         if (IS_ERR(phydev)) {
1438                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1439                 return PTR_ERR(phydev);
1440         }
1441
1442         /* Mask with MAC supported features. */
1443         switch (phydev->interface) {
1444         case PHY_INTERFACE_MODE_GMII:
1445         case PHY_INTERFACE_MODE_RGMII:
1446                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1447                         phydev->supported &= (PHY_GBIT_FEATURES |
1448                                               SUPPORTED_Pause |
1449                                               SUPPORTED_Asym_Pause);
1450                         break;
1451                 }
1452                 /* fallthru */
1453         case PHY_INTERFACE_MODE_MII:
1454                 phydev->supported &= (PHY_BASIC_FEATURES |
1455                                       SUPPORTED_Pause |
1456                                       SUPPORTED_Asym_Pause);
1457                 break;
1458         default:
1459                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1460                 return -EINVAL;
1461         }
1462
1463         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1464
1465         phydev->advertising = phydev->supported;
1466
1467         return 0;
1468 }
1469
1470 static void tg3_phy_start(struct tg3 *tp)
1471 {
1472         struct phy_device *phydev;
1473
1474         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1475                 return;
1476
1477         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1478
1479         if (tp->link_config.phy_is_low_power) {
1480                 tp->link_config.phy_is_low_power = 0;
1481                 phydev->speed = tp->link_config.orig_speed;
1482                 phydev->duplex = tp->link_config.orig_duplex;
1483                 phydev->autoneg = tp->link_config.orig_autoneg;
1484                 phydev->advertising = tp->link_config.orig_advertising;
1485         }
1486
1487         phy_start(phydev);
1488
1489         phy_start_aneg(phydev);
1490 }
1491
1492 static void tg3_phy_stop(struct tg3 *tp)
1493 {
1494         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1495                 return;
1496
1497         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1498 }
1499
1500 static void tg3_phy_fini(struct tg3 *tp)
1501 {
1502         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1503                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1504                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1505         }
1506 }
1507
1508 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1509 {
1510         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1511         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1512 }
1513
1514 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1515 {
1516         u32 phytest;
1517
1518         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1519                 u32 phy;
1520
1521                 tg3_writephy(tp, MII_TG3_FET_TEST,
1522                              phytest | MII_TG3_FET_SHADOW_EN);
1523                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1524                         if (enable)
1525                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1526                         else
1527                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1528                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1529                 }
1530                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1531         }
1532 }
1533
1534 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1535 {
1536         u32 reg;
1537
1538         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1539                 return;
1540
1541         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1542                 tg3_phy_fet_toggle_apd(tp, enable);
1543                 return;
1544         }
1545
1546         reg = MII_TG3_MISC_SHDW_WREN |
1547               MII_TG3_MISC_SHDW_SCR5_SEL |
1548               MII_TG3_MISC_SHDW_SCR5_LPED |
1549               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1550               MII_TG3_MISC_SHDW_SCR5_SDTL |
1551               MII_TG3_MISC_SHDW_SCR5_C125OE;
1552         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1553                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1554
1555         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1556
1557
1558         reg = MII_TG3_MISC_SHDW_WREN |
1559               MII_TG3_MISC_SHDW_APD_SEL |
1560               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1561         if (enable)
1562                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1563
1564         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1565 }
1566
1567 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1568 {
1569         u32 phy;
1570
1571         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1572             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1573                 return;
1574
1575         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1576                 u32 ephy;
1577
1578                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1579                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1580
1581                         tg3_writephy(tp, MII_TG3_FET_TEST,
1582                                      ephy | MII_TG3_FET_SHADOW_EN);
1583                         if (!tg3_readphy(tp, reg, &phy)) {
1584                                 if (enable)
1585                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1586                                 else
1587                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1588                                 tg3_writephy(tp, reg, phy);
1589                         }
1590                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1591                 }
1592         } else {
1593                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1594                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1595                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1596                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1597                         if (enable)
1598                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1599                         else
1600                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1601                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1602                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1603                 }
1604         }
1605 }
1606
1607 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1608 {
1609         u32 val;
1610
1611         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1612                 return;
1613
1614         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1615             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1616                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1617                              (val | (1 << 15) | (1 << 4)));
1618 }
1619
1620 static void tg3_phy_apply_otp(struct tg3 *tp)
1621 {
1622         u32 otp, phy;
1623
1624         if (!tp->phy_otp)
1625                 return;
1626
1627         otp = tp->phy_otp;
1628
1629         /* Enable SM_DSP clock and tx 6dB coding. */
1630         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1631               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1632               MII_TG3_AUXCTL_ACTL_TX_6DB;
1633         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1634
1635         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1636         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1637         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1638
1639         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1640               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1641         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1642
1643         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1644         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1645         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1646
1647         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1648         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1649
1650         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1651         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1652
1653         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1654               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1655         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1656
1657         /* Turn off SM_DSP clock. */
1658         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1659               MII_TG3_AUXCTL_ACTL_TX_6DB;
1660         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1661 }
1662
1663 static int tg3_wait_macro_done(struct tg3 *tp)
1664 {
1665         int limit = 100;
1666
1667         while (limit--) {
1668                 u32 tmp32;
1669
1670                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1671                         if ((tmp32 & 0x1000) == 0)
1672                                 break;
1673                 }
1674         }
1675         if (limit < 0)
1676                 return -EBUSY;
1677
1678         return 0;
1679 }
1680
1681 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1682 {
1683         static const u32 test_pat[4][6] = {
1684         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1685         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1686         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1687         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1688         };
1689         int chan;
1690
1691         for (chan = 0; chan < 4; chan++) {
1692                 int i;
1693
1694                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1695                              (chan * 0x2000) | 0x0200);
1696                 tg3_writephy(tp, 0x16, 0x0002);
1697
1698                 for (i = 0; i < 6; i++)
1699                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1700                                      test_pat[chan][i]);
1701
1702                 tg3_writephy(tp, 0x16, 0x0202);
1703                 if (tg3_wait_macro_done(tp)) {
1704                         *resetp = 1;
1705                         return -EBUSY;
1706                 }
1707
1708                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1709                              (chan * 0x2000) | 0x0200);
1710                 tg3_writephy(tp, 0x16, 0x0082);
1711                 if (tg3_wait_macro_done(tp)) {
1712                         *resetp = 1;
1713                         return -EBUSY;
1714                 }
1715
1716                 tg3_writephy(tp, 0x16, 0x0802);
1717                 if (tg3_wait_macro_done(tp)) {
1718                         *resetp = 1;
1719                         return -EBUSY;
1720                 }
1721
1722                 for (i = 0; i < 6; i += 2) {
1723                         u32 low, high;
1724
1725                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1726                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1727                             tg3_wait_macro_done(tp)) {
1728                                 *resetp = 1;
1729                                 return -EBUSY;
1730                         }
1731                         low &= 0x7fff;
1732                         high &= 0x000f;
1733                         if (low != test_pat[chan][i] ||
1734                             high != test_pat[chan][i+1]) {
1735                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1736                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1737                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1738
1739                                 return -EBUSY;
1740                         }
1741                 }
1742         }
1743
1744         return 0;
1745 }
1746
1747 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1748 {
1749         int chan;
1750
1751         for (chan = 0; chan < 4; chan++) {
1752                 int i;
1753
1754                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1755                              (chan * 0x2000) | 0x0200);
1756                 tg3_writephy(tp, 0x16, 0x0002);
1757                 for (i = 0; i < 6; i++)
1758                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1759                 tg3_writephy(tp, 0x16, 0x0202);
1760                 if (tg3_wait_macro_done(tp))
1761                         return -EBUSY;
1762         }
1763
1764         return 0;
1765 }
1766
1767 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1768 {
1769         u32 reg32, phy9_orig;
1770         int retries, do_phy_reset, err;
1771
1772         retries = 10;
1773         do_phy_reset = 1;
1774         do {
1775                 if (do_phy_reset) {
1776                         err = tg3_bmcr_reset(tp);
1777                         if (err)
1778                                 return err;
1779                         do_phy_reset = 0;
1780                 }
1781
1782                 /* Disable transmitter and interrupt.  */
1783                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1784                         continue;
1785
1786                 reg32 |= 0x3000;
1787                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1788
1789                 /* Set full-duplex, 1000 mbps.  */
1790                 tg3_writephy(tp, MII_BMCR,
1791                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1792
1793                 /* Set to master mode.  */
1794                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1795                         continue;
1796
1797                 tg3_writephy(tp, MII_TG3_CTRL,
1798                              (MII_TG3_CTRL_AS_MASTER |
1799                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1800
1801                 /* Enable SM_DSP_CLOCK and 6dB.  */
1802                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1803
1804                 /* Block the PHY control access.  */
1805                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1806                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1807
1808                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1809                 if (!err)
1810                         break;
1811         } while (--retries);
1812
1813         err = tg3_phy_reset_chanpat(tp);
1814         if (err)
1815                 return err;
1816
1817         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1818         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1819
1820         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1821         tg3_writephy(tp, 0x16, 0x0000);
1822
1823         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1824             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1825                 /* Set Extended packet length bit for jumbo frames */
1826                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1827         }
1828         else {
1829                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1830         }
1831
1832         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1833
1834         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1835                 reg32 &= ~0x3000;
1836                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1837         } else if (!err)
1838                 err = -EBUSY;
1839
1840         return err;
1841 }
1842
1843 /* This will reset the tigon3 PHY if there is no valid
1844  * link unless the FORCE argument is non-zero.
1845  */
1846 static int tg3_phy_reset(struct tg3 *tp)
1847 {
1848         u32 cpmuctrl;
1849         u32 phy_status;
1850         int err;
1851
1852         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1853                 u32 val;
1854
1855                 val = tr32(GRC_MISC_CFG);
1856                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1857                 udelay(40);
1858         }
1859         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1860         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1861         if (err != 0)
1862                 return -EBUSY;
1863
1864         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1865                 netif_carrier_off(tp->dev);
1866                 tg3_link_report(tp);
1867         }
1868
1869         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1870             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1871             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1872                 err = tg3_phy_reset_5703_4_5(tp);
1873                 if (err)
1874                         return err;
1875                 goto out;
1876         }
1877
1878         cpmuctrl = 0;
1879         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1880             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1881                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1882                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1883                         tw32(TG3_CPMU_CTRL,
1884                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1885         }
1886
1887         err = tg3_bmcr_reset(tp);
1888         if (err)
1889                 return err;
1890
1891         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1892                 u32 phy;
1893
1894                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1895                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1896
1897                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1898         }
1899
1900         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1901             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1902                 u32 val;
1903
1904                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1905                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1906                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1907                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1908                         udelay(40);
1909                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1910                 }
1911         }
1912
1913         tg3_phy_apply_otp(tp);
1914
1915         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1916                 tg3_phy_toggle_apd(tp, true);
1917         else
1918                 tg3_phy_toggle_apd(tp, false);
1919
1920 out:
1921         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1922                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1923                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1924                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1925                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1926                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1927                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1928         }
1929         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1930                 tg3_writephy(tp, 0x1c, 0x8d68);
1931                 tg3_writephy(tp, 0x1c, 0x8d68);
1932         }
1933         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1934                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1935                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1936                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1937                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1938                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1939                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1940                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1941                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1942         }
1943         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1944                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1945                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1946                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1947                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1948                         tg3_writephy(tp, MII_TG3_TEST1,
1949                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1950                 } else
1951                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1952                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1953         }
1954         /* Set Extended packet length bit (bit 14) on all chips that */
1955         /* support jumbo frames */
1956         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1957                 /* Cannot do read-modify-write on 5401 */
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1959         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1960                 u32 phy_reg;
1961
1962                 /* Set bit 14 with read-modify-write to preserve other bits */
1963                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1964                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1965                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1966         }
1967
1968         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1969          * jumbo frames transmission.
1970          */
1971         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1972                 u32 phy_reg;
1973
1974                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1975                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1976                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1977         }
1978
1979         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1980                 /* adjust output voltage */
1981                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1982         }
1983
1984         tg3_phy_toggle_automdix(tp, 1);
1985         tg3_phy_set_wirespeed(tp);
1986         return 0;
1987 }
1988
1989 static void tg3_frob_aux_power(struct tg3 *tp)
1990 {
1991         struct tg3 *tp_peer = tp;
1992
1993         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1994                 return;
1995
1996         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1997             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1998                 struct net_device *dev_peer;
1999
2000                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2001                 /* remove_one() may have been run on the peer. */
2002                 if (!dev_peer)
2003                         tp_peer = tp;
2004                 else
2005                         tp_peer = netdev_priv(dev_peer);
2006         }
2007
2008         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2009             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2010             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2011             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2012                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2013                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2014                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2015                                     (GRC_LCLCTRL_GPIO_OE0 |
2016                                      GRC_LCLCTRL_GPIO_OE1 |
2017                                      GRC_LCLCTRL_GPIO_OE2 |
2018                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2019                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2020                                     100);
2021                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2022                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2023                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2024                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2025                                              GRC_LCLCTRL_GPIO_OE1 |
2026                                              GRC_LCLCTRL_GPIO_OE2 |
2027                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2028                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2029                                              tp->grc_local_ctrl;
2030                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2031
2032                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2033                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2034
2035                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2036                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2037                 } else {
2038                         u32 no_gpio2;
2039                         u32 grc_local_ctrl = 0;
2040
2041                         if (tp_peer != tp &&
2042                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2043                                 return;
2044
2045                         /* Workaround to prevent overdrawing Amps. */
2046                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2047                             ASIC_REV_5714) {
2048                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2049                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2050                                             grc_local_ctrl, 100);
2051                         }
2052
2053                         /* On 5753 and variants, GPIO2 cannot be used. */
2054                         no_gpio2 = tp->nic_sram_data_cfg &
2055                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2056
2057                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2058                                          GRC_LCLCTRL_GPIO_OE1 |
2059                                          GRC_LCLCTRL_GPIO_OE2 |
2060                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2061                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2062                         if (no_gpio2) {
2063                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2064                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2065                         }
2066                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067                                                     grc_local_ctrl, 100);
2068
2069                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2070
2071                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2072                                                     grc_local_ctrl, 100);
2073
2074                         if (!no_gpio2) {
2075                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2076                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2077                                             grc_local_ctrl, 100);
2078                         }
2079                 }
2080         } else {
2081                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2082                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2083                         if (tp_peer != tp &&
2084                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2085                                 return;
2086
2087                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2088                                     (GRC_LCLCTRL_GPIO_OE1 |
2089                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2090
2091                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2092                                     GRC_LCLCTRL_GPIO_OE1, 100);
2093
2094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095                                     (GRC_LCLCTRL_GPIO_OE1 |
2096                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2097                 }
2098         }
2099 }
2100
2101 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2102 {
2103         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2104                 return 1;
2105         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2106                 if (speed != SPEED_10)
2107                         return 1;
2108         } else if (speed == SPEED_10)
2109                 return 1;
2110
2111         return 0;
2112 }
2113
2114 static int tg3_setup_phy(struct tg3 *, int);
2115
2116 #define RESET_KIND_SHUTDOWN     0
2117 #define RESET_KIND_INIT         1
2118 #define RESET_KIND_SUSPEND      2
2119
2120 static void tg3_write_sig_post_reset(struct tg3 *, int);
2121 static int tg3_halt_cpu(struct tg3 *, u32);
2122
2123 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2124 {
2125         u32 val;
2126
2127         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2128                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2129                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2130                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2131
2132                         sg_dig_ctrl |=
2133                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2134                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2135                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2136                 }
2137                 return;
2138         }
2139
2140         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2141                 tg3_bmcr_reset(tp);
2142                 val = tr32(GRC_MISC_CFG);
2143                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2144                 udelay(40);
2145                 return;
2146         } else if (do_low_power) {
2147                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2148                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2149
2150                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2151                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2152                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2153                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2154                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2155         }
2156
2157         /* The PHY should not be powered down on some chips because
2158          * of bugs.
2159          */
2160         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2161             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2162             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2163              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2164                 return;
2165
2166         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2167             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2168                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2169                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2170                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2171                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2172         }
2173
2174         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2175 }
2176
2177 /* tp->lock is held. */
2178 static int tg3_nvram_lock(struct tg3 *tp)
2179 {
2180         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2181                 int i;
2182
2183                 if (tp->nvram_lock_cnt == 0) {
2184                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2185                         for (i = 0; i < 8000; i++) {
2186                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2187                                         break;
2188                                 udelay(20);
2189                         }
2190                         if (i == 8000) {
2191                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2192                                 return -ENODEV;
2193                         }
2194                 }
2195                 tp->nvram_lock_cnt++;
2196         }
2197         return 0;
2198 }
2199
2200 /* tp->lock is held. */
2201 static void tg3_nvram_unlock(struct tg3 *tp)
2202 {
2203         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2204                 if (tp->nvram_lock_cnt > 0)
2205                         tp->nvram_lock_cnt--;
2206                 if (tp->nvram_lock_cnt == 0)
2207                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2208         }
2209 }
2210
2211 /* tp->lock is held. */
2212 static void tg3_enable_nvram_access(struct tg3 *tp)
2213 {
2214         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2215             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2216                 u32 nvaccess = tr32(NVRAM_ACCESS);
2217
2218                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2219         }
2220 }
2221
2222 /* tp->lock is held. */
2223 static void tg3_disable_nvram_access(struct tg3 *tp)
2224 {
2225         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2226             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2227                 u32 nvaccess = tr32(NVRAM_ACCESS);
2228
2229                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2230         }
2231 }
2232
2233 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2234                                         u32 offset, u32 *val)
2235 {
2236         u32 tmp;
2237         int i;
2238
2239         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2240                 return -EINVAL;
2241
2242         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2243                                         EEPROM_ADDR_DEVID_MASK |
2244                                         EEPROM_ADDR_READ);
2245         tw32(GRC_EEPROM_ADDR,
2246              tmp |
2247              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2248              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2249               EEPROM_ADDR_ADDR_MASK) |
2250              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2251
2252         for (i = 0; i < 1000; i++) {
2253                 tmp = tr32(GRC_EEPROM_ADDR);
2254
2255                 if (tmp & EEPROM_ADDR_COMPLETE)
2256                         break;
2257                 msleep(1);
2258         }
2259         if (!(tmp & EEPROM_ADDR_COMPLETE))
2260                 return -EBUSY;
2261
2262         tmp = tr32(GRC_EEPROM_DATA);
2263
2264         /*
2265          * The data will always be opposite the native endian
2266          * format.  Perform a blind byteswap to compensate.
2267          */
2268         *val = swab32(tmp);
2269
2270         return 0;
2271 }
2272
2273 #define NVRAM_CMD_TIMEOUT 10000
2274
2275 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2276 {
2277         int i;
2278
2279         tw32(NVRAM_CMD, nvram_cmd);
2280         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2281                 udelay(10);
2282                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2283                         udelay(10);
2284                         break;
2285                 }
2286         }
2287
2288         if (i == NVRAM_CMD_TIMEOUT)
2289                 return -EBUSY;
2290
2291         return 0;
2292 }
2293
2294 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2295 {
2296         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2297             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2298             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2299            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2300             (tp->nvram_jedecnum == JEDEC_ATMEL))
2301
2302                 addr = ((addr / tp->nvram_pagesize) <<
2303                         ATMEL_AT45DB0X1B_PAGE_POS) +
2304                        (addr % tp->nvram_pagesize);
2305
2306         return addr;
2307 }
2308
2309 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2310 {
2311         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2312             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2313             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2314            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2315             (tp->nvram_jedecnum == JEDEC_ATMEL))
2316
2317                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2318                         tp->nvram_pagesize) +
2319                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2320
2321         return addr;
2322 }
2323
2324 /* NOTE: Data read in from NVRAM is byteswapped according to
2325  * the byteswapping settings for all other register accesses.
2326  * tg3 devices are BE devices, so on a BE machine, the data
2327  * returned will be exactly as it is seen in NVRAM.  On a LE
2328  * machine, the 32-bit value will be byteswapped.
2329  */
2330 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2331 {
2332         int ret;
2333
2334         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2335                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2336
2337         offset = tg3_nvram_phys_addr(tp, offset);
2338
2339         if (offset > NVRAM_ADDR_MSK)
2340                 return -EINVAL;
2341
2342         ret = tg3_nvram_lock(tp);
2343         if (ret)
2344                 return ret;
2345
2346         tg3_enable_nvram_access(tp);
2347
2348         tw32(NVRAM_ADDR, offset);
2349         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2350                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2351
2352         if (ret == 0)
2353                 *val = tr32(NVRAM_RDDATA);
2354
2355         tg3_disable_nvram_access(tp);
2356
2357         tg3_nvram_unlock(tp);
2358
2359         return ret;
2360 }
2361
2362 /* Ensures NVRAM data is in bytestream format. */
2363 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2364 {
2365         u32 v;
2366         int res = tg3_nvram_read(tp, offset, &v);
2367         if (!res)
2368                 *val = cpu_to_be32(v);
2369         return res;
2370 }
2371
2372 /* tp->lock is held. */
2373 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2374 {
2375         u32 addr_high, addr_low;
2376         int i;
2377
2378         addr_high = ((tp->dev->dev_addr[0] << 8) |
2379                      tp->dev->dev_addr[1]);
2380         addr_low = ((tp->dev->dev_addr[2] << 24) |
2381                     (tp->dev->dev_addr[3] << 16) |
2382                     (tp->dev->dev_addr[4] <<  8) |
2383                     (tp->dev->dev_addr[5] <<  0));
2384         for (i = 0; i < 4; i++) {
2385                 if (i == 1 && skip_mac_1)
2386                         continue;
2387                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2388                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2389         }
2390
2391         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2392             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2393                 for (i = 0; i < 12; i++) {
2394                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2395                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2396                 }
2397         }
2398
2399         addr_high = (tp->dev->dev_addr[0] +
2400                      tp->dev->dev_addr[1] +
2401                      tp->dev->dev_addr[2] +
2402                      tp->dev->dev_addr[3] +
2403                      tp->dev->dev_addr[4] +
2404                      tp->dev->dev_addr[5]) &
2405                 TX_BACKOFF_SEED_MASK;
2406         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2407 }
2408
2409 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2410 {
2411         u32 misc_host_ctrl;
2412         bool device_should_wake, do_low_power;
2413
2414         /* Make sure register accesses (indirect or otherwise)
2415          * will function correctly.
2416          */
2417         pci_write_config_dword(tp->pdev,
2418                                TG3PCI_MISC_HOST_CTRL,
2419                                tp->misc_host_ctrl);
2420
2421         switch (state) {
2422         case PCI_D0:
2423                 pci_enable_wake(tp->pdev, state, false);
2424                 pci_set_power_state(tp->pdev, PCI_D0);
2425
2426                 /* Switch out of Vaux if it is a NIC */
2427                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2428                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2429
2430                 return 0;
2431
2432         case PCI_D1:
2433         case PCI_D2:
2434         case PCI_D3hot:
2435                 break;
2436
2437         default:
2438                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2439                         tp->dev->name, state);
2440                 return -EINVAL;
2441         }
2442
2443         /* Restore the CLKREQ setting. */
2444         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2445                 u16 lnkctl;
2446
2447                 pci_read_config_word(tp->pdev,
2448                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2449                                      &lnkctl);
2450                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2451                 pci_write_config_word(tp->pdev,
2452                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2453                                       lnkctl);
2454         }
2455
2456         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2457         tw32(TG3PCI_MISC_HOST_CTRL,
2458              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2459
2460         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2461                              device_may_wakeup(&tp->pdev->dev) &&
2462                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2463
2464         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2465                 do_low_power = false;
2466                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2467                     !tp->link_config.phy_is_low_power) {
2468                         struct phy_device *phydev;
2469                         u32 phyid, advertising;
2470
2471                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2472
2473                         tp->link_config.phy_is_low_power = 1;
2474
2475                         tp->link_config.orig_speed = phydev->speed;
2476                         tp->link_config.orig_duplex = phydev->duplex;
2477                         tp->link_config.orig_autoneg = phydev->autoneg;
2478                         tp->link_config.orig_advertising = phydev->advertising;
2479
2480                         advertising = ADVERTISED_TP |
2481                                       ADVERTISED_Pause |
2482                                       ADVERTISED_Autoneg |
2483                                       ADVERTISED_10baseT_Half;
2484
2485                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2486                             device_should_wake) {
2487                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2488                                         advertising |=
2489                                                 ADVERTISED_100baseT_Half |
2490                                                 ADVERTISED_100baseT_Full |
2491                                                 ADVERTISED_10baseT_Full;
2492                                 else
2493                                         advertising |= ADVERTISED_10baseT_Full;
2494                         }
2495
2496                         phydev->advertising = advertising;
2497
2498                         phy_start_aneg(phydev);
2499
2500                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2501                         if (phyid != TG3_PHY_ID_BCMAC131) {
2502                                 phyid &= TG3_PHY_OUI_MASK;
2503                                 if (phyid == TG3_PHY_OUI_1 ||
2504                                     phyid == TG3_PHY_OUI_2 ||
2505                                     phyid == TG3_PHY_OUI_3)
2506                                         do_low_power = true;
2507                         }
2508                 }
2509         } else {
2510                 do_low_power = true;
2511
2512                 if (tp->link_config.phy_is_low_power == 0) {
2513                         tp->link_config.phy_is_low_power = 1;
2514                         tp->link_config.orig_speed = tp->link_config.speed;
2515                         tp->link_config.orig_duplex = tp->link_config.duplex;
2516                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2517                 }
2518
2519                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2520                         tp->link_config.speed = SPEED_10;
2521                         tp->link_config.duplex = DUPLEX_HALF;
2522                         tp->link_config.autoneg = AUTONEG_ENABLE;
2523                         tg3_setup_phy(tp, 0);
2524                 }
2525         }
2526
2527         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2528                 u32 val;
2529
2530                 val = tr32(GRC_VCPU_EXT_CTRL);
2531                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2532         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2533                 int i;
2534                 u32 val;
2535
2536                 for (i = 0; i < 200; i++) {
2537                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2538                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2539                                 break;
2540                         msleep(1);
2541                 }
2542         }
2543         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2544                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2545                                                      WOL_DRV_STATE_SHUTDOWN |
2546                                                      WOL_DRV_WOL |
2547                                                      WOL_SET_MAGIC_PKT);
2548
2549         if (device_should_wake) {
2550                 u32 mac_mode;
2551
2552                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2553                         if (do_low_power) {
2554                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2555                                 udelay(40);
2556                         }
2557
2558                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2559                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2560                         else
2561                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2562
2563                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2564                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2565                             ASIC_REV_5700) {
2566                                 u32 speed = (tp->tg3_flags &
2567                                              TG3_FLAG_WOL_SPEED_100MB) ?
2568                                              SPEED_100 : SPEED_10;
2569                                 if (tg3_5700_link_polarity(tp, speed))
2570                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2571                                 else
2572                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2573                         }
2574                 } else {
2575                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2576                 }
2577
2578                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2579                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2580
2581                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2582                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2583                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2584                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2585                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2586                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2587
2588                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2589                         mac_mode |= tp->mac_mode &
2590                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2591                         if (mac_mode & MAC_MODE_APE_TX_EN)
2592                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2593                 }
2594
2595                 tw32_f(MAC_MODE, mac_mode);
2596                 udelay(100);
2597
2598                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2599                 udelay(10);
2600         }
2601
2602         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2603             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2604              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2605                 u32 base_val;
2606
2607                 base_val = tp->pci_clock_ctrl;
2608                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2609                              CLOCK_CTRL_TXCLK_DISABLE);
2610
2611                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2612                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2613         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2614                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2615                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2616                 /* do nothing */
2617         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2618                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2619                 u32 newbits1, newbits2;
2620
2621                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2622                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2623                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2624                                     CLOCK_CTRL_TXCLK_DISABLE |
2625                                     CLOCK_CTRL_ALTCLK);
2626                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2627                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2628                         newbits1 = CLOCK_CTRL_625_CORE;
2629                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2630                 } else {
2631                         newbits1 = CLOCK_CTRL_ALTCLK;
2632                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2633                 }
2634
2635                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2636                             40);
2637
2638                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2639                             40);
2640
2641                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2642                         u32 newbits3;
2643
2644                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2645                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2646                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2647                                             CLOCK_CTRL_TXCLK_DISABLE |
2648                                             CLOCK_CTRL_44MHZ_CORE);
2649                         } else {
2650                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2651                         }
2652
2653                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2654                                     tp->pci_clock_ctrl | newbits3, 40);
2655                 }
2656         }
2657
2658         if (!(device_should_wake) &&
2659             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2660                 tg3_power_down_phy(tp, do_low_power);
2661
2662         tg3_frob_aux_power(tp);
2663
2664         /* Workaround for unstable PLL clock */
2665         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2666             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2667                 u32 val = tr32(0x7d00);
2668
2669                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2670                 tw32(0x7d00, val);
2671                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2672                         int err;
2673
2674                         err = tg3_nvram_lock(tp);
2675                         tg3_halt_cpu(tp, RX_CPU_BASE);
2676                         if (!err)
2677                                 tg3_nvram_unlock(tp);
2678                 }
2679         }
2680
2681         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2682
2683         if (device_should_wake)
2684                 pci_enable_wake(tp->pdev, state, true);
2685
2686         /* Finally, set the new power state. */
2687         pci_set_power_state(tp->pdev, state);
2688
2689         return 0;
2690 }
2691
2692 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2693 {
2694         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2695         case MII_TG3_AUX_STAT_10HALF:
2696                 *speed = SPEED_10;
2697                 *duplex = DUPLEX_HALF;
2698                 break;
2699
2700         case MII_TG3_AUX_STAT_10FULL:
2701                 *speed = SPEED_10;
2702                 *duplex = DUPLEX_FULL;
2703                 break;
2704
2705         case MII_TG3_AUX_STAT_100HALF:
2706                 *speed = SPEED_100;
2707                 *duplex = DUPLEX_HALF;
2708                 break;
2709
2710         case MII_TG3_AUX_STAT_100FULL:
2711                 *speed = SPEED_100;
2712                 *duplex = DUPLEX_FULL;
2713                 break;
2714
2715         case MII_TG3_AUX_STAT_1000HALF:
2716                 *speed = SPEED_1000;
2717                 *duplex = DUPLEX_HALF;
2718                 break;
2719
2720         case MII_TG3_AUX_STAT_1000FULL:
2721                 *speed = SPEED_1000;
2722                 *duplex = DUPLEX_FULL;
2723                 break;
2724
2725         default:
2726                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2727                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2728                                  SPEED_10;
2729                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2730                                   DUPLEX_HALF;
2731                         break;
2732                 }
2733                 *speed = SPEED_INVALID;
2734                 *duplex = DUPLEX_INVALID;
2735                 break;
2736         }
2737 }
2738
2739 static void tg3_phy_copper_begin(struct tg3 *tp)
2740 {
2741         u32 new_adv;
2742         int i;
2743
2744         if (tp->link_config.phy_is_low_power) {
2745                 /* Entering low power mode.  Disable gigabit and
2746                  * 100baseT advertisements.
2747                  */
2748                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2749
2750                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2751                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2752                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2753                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2754
2755                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2756         } else if (tp->link_config.speed == SPEED_INVALID) {
2757                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2758                         tp->link_config.advertising &=
2759                                 ~(ADVERTISED_1000baseT_Half |
2760                                   ADVERTISED_1000baseT_Full);
2761
2762                 new_adv = ADVERTISE_CSMA;
2763                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2764                         new_adv |= ADVERTISE_10HALF;
2765                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2766                         new_adv |= ADVERTISE_10FULL;
2767                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2768                         new_adv |= ADVERTISE_100HALF;
2769                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2770                         new_adv |= ADVERTISE_100FULL;
2771
2772                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2773
2774                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2775
2776                 if (tp->link_config.advertising &
2777                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2778                         new_adv = 0;
2779                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2780                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2781                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2782                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2783                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2784                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2785                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2786                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2787                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2788                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2789                 } else {
2790                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2791                 }
2792         } else {
2793                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2794                 new_adv |= ADVERTISE_CSMA;
2795
2796                 /* Asking for a specific link mode. */
2797                 if (tp->link_config.speed == SPEED_1000) {
2798                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2799
2800                         if (tp->link_config.duplex == DUPLEX_FULL)
2801                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2802                         else
2803                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2804                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2805                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2806                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2807                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2808                 } else {
2809                         if (tp->link_config.speed == SPEED_100) {
2810                                 if (tp->link_config.duplex == DUPLEX_FULL)
2811                                         new_adv |= ADVERTISE_100FULL;
2812                                 else
2813                                         new_adv |= ADVERTISE_100HALF;
2814                         } else {
2815                                 if (tp->link_config.duplex == DUPLEX_FULL)
2816                                         new_adv |= ADVERTISE_10FULL;
2817                                 else
2818                                         new_adv |= ADVERTISE_10HALF;
2819                         }
2820                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821
2822                         new_adv = 0;
2823                 }
2824
2825                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2826         }
2827
2828         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2829             tp->link_config.speed != SPEED_INVALID) {
2830                 u32 bmcr, orig_bmcr;
2831
2832                 tp->link_config.active_speed = tp->link_config.speed;
2833                 tp->link_config.active_duplex = tp->link_config.duplex;
2834
2835                 bmcr = 0;
2836                 switch (tp->link_config.speed) {
2837                 default:
2838                 case SPEED_10:
2839                         break;
2840
2841                 case SPEED_100:
2842                         bmcr |= BMCR_SPEED100;
2843                         break;
2844
2845                 case SPEED_1000:
2846                         bmcr |= TG3_BMCR_SPEED1000;
2847                         break;
2848                 }
2849
2850                 if (tp->link_config.duplex == DUPLEX_FULL)
2851                         bmcr |= BMCR_FULLDPLX;
2852
2853                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2854                     (bmcr != orig_bmcr)) {
2855                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2856                         for (i = 0; i < 1500; i++) {
2857                                 u32 tmp;
2858
2859                                 udelay(10);
2860                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2861                                     tg3_readphy(tp, MII_BMSR, &tmp))
2862                                         continue;
2863                                 if (!(tmp & BMSR_LSTATUS)) {
2864                                         udelay(40);
2865                                         break;
2866                                 }
2867                         }
2868                         tg3_writephy(tp, MII_BMCR, bmcr);
2869                         udelay(40);
2870                 }
2871         } else {
2872                 tg3_writephy(tp, MII_BMCR,
2873                              BMCR_ANENABLE | BMCR_ANRESTART);
2874         }
2875 }
2876
2877 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2878 {
2879         int err;
2880
2881         /* Turn off tap power management. */
2882         /* Set Extended packet length bit */
2883         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2884
2885         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2886         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2887
2888         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2889         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2890
2891         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2892         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2893
2894         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2895         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2896
2897         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2898         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2899
2900         udelay(40);
2901
2902         return err;
2903 }
2904
2905 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2906 {
2907         u32 adv_reg, all_mask = 0;
2908
2909         if (mask & ADVERTISED_10baseT_Half)
2910                 all_mask |= ADVERTISE_10HALF;
2911         if (mask & ADVERTISED_10baseT_Full)
2912                 all_mask |= ADVERTISE_10FULL;
2913         if (mask & ADVERTISED_100baseT_Half)
2914                 all_mask |= ADVERTISE_100HALF;
2915         if (mask & ADVERTISED_100baseT_Full)
2916                 all_mask |= ADVERTISE_100FULL;
2917
2918         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2919                 return 0;
2920
2921         if ((adv_reg & all_mask) != all_mask)
2922                 return 0;
2923         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2924                 u32 tg3_ctrl;
2925
2926                 all_mask = 0;
2927                 if (mask & ADVERTISED_1000baseT_Half)
2928                         all_mask |= ADVERTISE_1000HALF;
2929                 if (mask & ADVERTISED_1000baseT_Full)
2930                         all_mask |= ADVERTISE_1000FULL;
2931
2932                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2933                         return 0;
2934
2935                 if ((tg3_ctrl & all_mask) != all_mask)
2936                         return 0;
2937         }
2938         return 1;
2939 }
2940
2941 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2942 {
2943         u32 curadv, reqadv;
2944
2945         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2946                 return 1;
2947
2948         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2949         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2950
2951         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2952                 if (curadv != reqadv)
2953                         return 0;
2954
2955                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2956                         tg3_readphy(tp, MII_LPA, rmtadv);
2957         } else {
2958                 /* Reprogram the advertisement register, even if it
2959                  * does not affect the current link.  If the link
2960                  * gets renegotiated in the future, we can save an
2961                  * additional renegotiation cycle by advertising
2962                  * it correctly in the first place.
2963                  */
2964                 if (curadv != reqadv) {
2965                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2966                                      ADVERTISE_PAUSE_ASYM);
2967                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2968                 }
2969         }
2970
2971         return 1;
2972 }
2973
2974 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2975 {
2976         int current_link_up;
2977         u32 bmsr, dummy;
2978         u32 lcl_adv, rmt_adv;
2979         u16 current_speed;
2980         u8 current_duplex;
2981         int i, err;
2982
2983         tw32(MAC_EVENT, 0);
2984
2985         tw32_f(MAC_STATUS,
2986              (MAC_STATUS_SYNC_CHANGED |
2987               MAC_STATUS_CFG_CHANGED |
2988               MAC_STATUS_MI_COMPLETION |
2989               MAC_STATUS_LNKSTATE_CHANGED));
2990         udelay(40);
2991
2992         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2993                 tw32_f(MAC_MI_MODE,
2994                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2995                 udelay(80);
2996         }
2997
2998         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2999
3000         /* Some third-party PHYs need to be reset on link going
3001          * down.
3002          */
3003         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3004              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3005              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3006             netif_carrier_ok(tp->dev)) {
3007                 tg3_readphy(tp, MII_BMSR, &bmsr);
3008                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3009                     !(bmsr & BMSR_LSTATUS))
3010                         force_reset = 1;
3011         }
3012         if (force_reset)
3013                 tg3_phy_reset(tp);
3014
3015         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3016                 tg3_readphy(tp, MII_BMSR, &bmsr);
3017                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3018                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3019                         bmsr = 0;
3020
3021                 if (!(bmsr & BMSR_LSTATUS)) {
3022                         err = tg3_init_5401phy_dsp(tp);
3023                         if (err)
3024                                 return err;
3025
3026                         tg3_readphy(tp, MII_BMSR, &bmsr);
3027                         for (i = 0; i < 1000; i++) {
3028                                 udelay(10);
3029                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3030                                     (bmsr & BMSR_LSTATUS)) {
3031                                         udelay(40);
3032                                         break;
3033                                 }
3034                         }
3035
3036                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3037                             !(bmsr & BMSR_LSTATUS) &&
3038                             tp->link_config.active_speed == SPEED_1000) {
3039                                 err = tg3_phy_reset(tp);
3040                                 if (!err)
3041                                         err = tg3_init_5401phy_dsp(tp);
3042                                 if (err)
3043                                         return err;
3044                         }
3045                 }
3046         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3047                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3048                 /* 5701 {A0,B0} CRC bug workaround */
3049                 tg3_writephy(tp, 0x15, 0x0a75);
3050                 tg3_writephy(tp, 0x1c, 0x8c68);
3051                 tg3_writephy(tp, 0x1c, 0x8d68);
3052                 tg3_writephy(tp, 0x1c, 0x8c68);
3053         }
3054
3055         /* Clear pending interrupts... */
3056         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3057         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3058
3059         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3060                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3061         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3062                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3063
3064         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3065             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3066                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3067                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3068                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3069                 else
3070                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3071         }
3072
3073         current_link_up = 0;
3074         current_speed = SPEED_INVALID;
3075         current_duplex = DUPLEX_INVALID;
3076
3077         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3078                 u32 val;
3079
3080                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3081                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3082                 if (!(val & (1 << 10))) {
3083                         val |= (1 << 10);
3084                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3085                         goto relink;
3086                 }
3087         }
3088
3089         bmsr = 0;
3090         for (i = 0; i < 100; i++) {
3091                 tg3_readphy(tp, MII_BMSR, &bmsr);
3092                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3093                     (bmsr & BMSR_LSTATUS))
3094                         break;
3095                 udelay(40);
3096         }
3097
3098         if (bmsr & BMSR_LSTATUS) {
3099                 u32 aux_stat, bmcr;
3100
3101                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3102                 for (i = 0; i < 2000; i++) {
3103                         udelay(10);
3104                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3105                             aux_stat)
3106                                 break;
3107                 }
3108
3109                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3110                                              &current_speed,
3111                                              &current_duplex);
3112
3113                 bmcr = 0;
3114                 for (i = 0; i < 200; i++) {
3115                         tg3_readphy(tp, MII_BMCR, &bmcr);
3116                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3117                                 continue;
3118                         if (bmcr && bmcr != 0x7fff)
3119                                 break;
3120                         udelay(10);
3121                 }
3122
3123                 lcl_adv = 0;
3124                 rmt_adv = 0;
3125
3126                 tp->link_config.active_speed = current_speed;
3127                 tp->link_config.active_duplex = current_duplex;
3128
3129                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3130                         if ((bmcr & BMCR_ANENABLE) &&
3131                             tg3_copper_is_advertising_all(tp,
3132                                                 tp->link_config.advertising)) {
3133                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3134                                                                   &rmt_adv))
3135                                         current_link_up = 1;
3136                         }
3137                 } else {
3138                         if (!(bmcr & BMCR_ANENABLE) &&
3139                             tp->link_config.speed == current_speed &&
3140                             tp->link_config.duplex == current_duplex &&
3141                             tp->link_config.flowctrl ==
3142                             tp->link_config.active_flowctrl) {
3143                                 current_link_up = 1;
3144                         }
3145                 }
3146
3147                 if (current_link_up == 1 &&
3148                     tp->link_config.active_duplex == DUPLEX_FULL)
3149                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3150         }
3151
3152 relink:
3153         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3154                 u32 tmp;
3155
3156                 tg3_phy_copper_begin(tp);
3157
3158                 tg3_readphy(tp, MII_BMSR, &tmp);
3159                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3160                     (tmp & BMSR_LSTATUS))
3161                         current_link_up = 1;
3162         }
3163
3164         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3165         if (current_link_up == 1) {
3166                 if (tp->link_config.active_speed == SPEED_100 ||
3167                     tp->link_config.active_speed == SPEED_10)
3168                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3169                 else
3170                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3171         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3172                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3173         else
3174                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3175
3176         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3177         if (tp->link_config.active_duplex == DUPLEX_HALF)
3178                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3179
3180         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3181                 if (current_link_up == 1 &&
3182                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3183                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3184                 else
3185                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3186         }
3187
3188         /* ??? Without this setting Netgear GA302T PHY does not
3189          * ??? send/receive packets...
3190          */
3191         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3192             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3193                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3194                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3195                 udelay(80);
3196         }
3197
3198         tw32_f(MAC_MODE, tp->mac_mode);
3199         udelay(40);
3200
3201         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3202                 /* Polled via timer. */
3203                 tw32_f(MAC_EVENT, 0);
3204         } else {
3205                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3206         }
3207         udelay(40);
3208
3209         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3210             current_link_up == 1 &&
3211             tp->link_config.active_speed == SPEED_1000 &&
3212             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3213              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3214                 udelay(120);
3215                 tw32_f(MAC_STATUS,
3216                      (MAC_STATUS_SYNC_CHANGED |
3217                       MAC_STATUS_CFG_CHANGED));
3218                 udelay(40);
3219                 tg3_write_mem(tp,
3220                               NIC_SRAM_FIRMWARE_MBOX,
3221                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3222         }
3223
3224         /* Prevent send BD corruption. */
3225         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3226                 u16 oldlnkctl, newlnkctl;
3227
3228                 pci_read_config_word(tp->pdev,
3229                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3230                                      &oldlnkctl);
3231                 if (tp->link_config.active_speed == SPEED_100 ||
3232                     tp->link_config.active_speed == SPEED_10)
3233                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3234                 else
3235                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3236                 if (newlnkctl != oldlnkctl)
3237                         pci_write_config_word(tp->pdev,
3238                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3239                                               newlnkctl);
3240         } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3241                 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3242                 if (tp->link_config.active_speed == SPEED_100 ||
3243                     tp->link_config.active_speed == SPEED_10)
3244                         newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3245                 else
3246                         newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3247                 if (newreg != oldreg)
3248                         tw32(TG3_PCIE_LNKCTL, newreg);
3249         }
3250
3251         if (current_link_up != netif_carrier_ok(tp->dev)) {
3252                 if (current_link_up)
3253                         netif_carrier_on(tp->dev);
3254                 else
3255                         netif_carrier_off(tp->dev);
3256                 tg3_link_report(tp);
3257         }
3258
3259         return 0;
3260 }
3261
3262 struct tg3_fiber_aneginfo {
3263         int state;
3264 #define ANEG_STATE_UNKNOWN              0
3265 #define ANEG_STATE_AN_ENABLE            1
3266 #define ANEG_STATE_RESTART_INIT         2
3267 #define ANEG_STATE_RESTART              3
3268 #define ANEG_STATE_DISABLE_LINK_OK      4
3269 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3270 #define ANEG_STATE_ABILITY_DETECT       6
3271 #define ANEG_STATE_ACK_DETECT_INIT      7
3272 #define ANEG_STATE_ACK_DETECT           8
3273 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3274 #define ANEG_STATE_COMPLETE_ACK         10
3275 #define ANEG_STATE_IDLE_DETECT_INIT     11
3276 #define ANEG_STATE_IDLE_DETECT          12
3277 #define ANEG_STATE_LINK_OK              13
3278 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3279 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3280
3281         u32 flags;
3282 #define MR_AN_ENABLE            0x00000001
3283 #define MR_RESTART_AN           0x00000002
3284 #define MR_AN_COMPLETE          0x00000004
3285 #define MR_PAGE_RX              0x00000008
3286 #define MR_NP_LOADED            0x00000010
3287 #define MR_TOGGLE_TX            0x00000020
3288 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3289 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3290 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3291 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3292 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3293 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3294 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3295 #define MR_TOGGLE_RX            0x00002000
3296 #define MR_NP_RX                0x00004000
3297
3298 #define MR_LINK_OK              0x80000000
3299
3300         unsigned long link_time, cur_time;
3301
3302         u32 ability_match_cfg;
3303         int ability_match_count;
3304
3305         char ability_match, idle_match, ack_match;
3306
3307         u32 txconfig, rxconfig;
3308 #define ANEG_CFG_NP             0x00000080
3309 #define ANEG_CFG_ACK            0x00000040
3310 #define ANEG_CFG_RF2            0x00000020
3311 #define ANEG_CFG_RF1            0x00000010
3312 #define ANEG_CFG_PS2            0x00000001
3313 #define ANEG_CFG_PS1            0x00008000
3314 #define ANEG_CFG_HD             0x00004000
3315 #define ANEG_CFG_FD             0x00002000
3316 #define ANEG_CFG_INVAL          0x00001f06
3317
3318 };
3319 #define ANEG_OK         0
3320 #define ANEG_DONE       1
3321 #define ANEG_TIMER_ENAB 2
3322 #define ANEG_FAILED     -1
3323
3324 #define ANEG_STATE_SETTLE_TIME  10000
3325
3326 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3327                                    struct tg3_fiber_aneginfo *ap)
3328 {
3329         u16 flowctrl;
3330         unsigned long delta;
3331         u32 rx_cfg_reg;
3332         int ret;
3333
3334         if (ap->state == ANEG_STATE_UNKNOWN) {
3335                 ap->rxconfig = 0;
3336                 ap->link_time = 0;
3337                 ap->cur_time = 0;
3338                 ap->ability_match_cfg = 0;
3339                 ap->ability_match_count = 0;
3340                 ap->ability_match = 0;
3341                 ap->idle_match = 0;
3342                 ap->ack_match = 0;
3343         }
3344         ap->cur_time++;
3345
3346         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3347                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3348
3349                 if (rx_cfg_reg != ap->ability_match_cfg) {
3350                         ap->ability_match_cfg = rx_cfg_reg;
3351                         ap->ability_match = 0;
3352                         ap->ability_match_count = 0;
3353                 } else {
3354                         if (++ap->ability_match_count > 1) {
3355                                 ap->ability_match = 1;
3356                                 ap->ability_match_cfg = rx_cfg_reg;
3357                         }
3358                 }
3359                 if (rx_cfg_reg & ANEG_CFG_ACK)
3360                         ap->ack_match = 1;
3361                 else
3362                         ap->ack_match = 0;
3363
3364                 ap->idle_match = 0;
3365         } else {
3366                 ap->idle_match = 1;
3367                 ap->ability_match_cfg = 0;
3368                 ap->ability_match_count = 0;
3369                 ap->ability_match = 0;
3370                 ap->ack_match = 0;
3371
3372                 rx_cfg_reg = 0;
3373         }
3374
3375         ap->rxconfig = rx_cfg_reg;
3376         ret = ANEG_OK;
3377
3378         switch(ap->state) {
3379         case ANEG_STATE_UNKNOWN:
3380                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3381                         ap->state = ANEG_STATE_AN_ENABLE;
3382
3383                 /* fallthru */
3384         case ANEG_STATE_AN_ENABLE:
3385                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3386                 if (ap->flags & MR_AN_ENABLE) {
3387                         ap->link_time = 0;
3388                         ap->cur_time = 0;
3389                         ap->ability_match_cfg = 0;
3390                         ap->ability_match_count = 0;
3391                         ap->ability_match = 0;
3392                         ap->idle_match = 0;
3393                         ap->ack_match = 0;
3394
3395                         ap->state = ANEG_STATE_RESTART_INIT;
3396                 } else {
3397                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3398                 }
3399                 break;
3400
3401         case ANEG_STATE_RESTART_INIT:
3402                 ap->link_time = ap->cur_time;
3403                 ap->flags &= ~(MR_NP_LOADED);
3404                 ap->txconfig = 0;
3405                 tw32(MAC_TX_AUTO_NEG, 0);
3406                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3407                 tw32_f(MAC_MODE, tp->mac_mode);
3408                 udelay(40);
3409
3410                 ret = ANEG_TIMER_ENAB;
3411                 ap->state = ANEG_STATE_RESTART;
3412
3413                 /* fallthru */
3414         case ANEG_STATE_RESTART:
3415                 delta = ap->cur_time - ap->link_time;
3416                 if (delta > ANEG_STATE_SETTLE_TIME) {
3417                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3418                 } else {
3419                         ret = ANEG_TIMER_ENAB;
3420                 }
3421                 break;
3422
3423         case ANEG_STATE_DISABLE_LINK_OK:
3424                 ret = ANEG_DONE;
3425                 break;
3426
3427         case ANEG_STATE_ABILITY_DETECT_INIT:
3428                 ap->flags &= ~(MR_TOGGLE_TX);
3429                 ap->txconfig = ANEG_CFG_FD;
3430                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3431                 if (flowctrl & ADVERTISE_1000XPAUSE)
3432                         ap->txconfig |= ANEG_CFG_PS1;
3433                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3434                         ap->txconfig |= ANEG_CFG_PS2;
3435                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3436                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3437                 tw32_f(MAC_MODE, tp->mac_mode);
3438                 udelay(40);
3439
3440                 ap->state = ANEG_STATE_ABILITY_DETECT;
3441                 break;
3442
3443         case ANEG_STATE_ABILITY_DETECT:
3444                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3445                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3446                 }
3447                 break;
3448
3449         case ANEG_STATE_ACK_DETECT_INIT:
3450                 ap->txconfig |= ANEG_CFG_ACK;
3451                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3452                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3453                 tw32_f(MAC_MODE, tp->mac_mode);
3454                 udelay(40);
3455
3456                 ap->state = ANEG_STATE_ACK_DETECT;
3457
3458                 /* fallthru */
3459         case ANEG_STATE_ACK_DETECT:
3460                 if (ap->ack_match != 0) {
3461                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3462                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3463                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3464                         } else {
3465                                 ap->state = ANEG_STATE_AN_ENABLE;
3466                         }
3467                 } else if (ap->ability_match != 0 &&
3468                            ap->rxconfig == 0) {
3469                         ap->state = ANEG_STATE_AN_ENABLE;
3470                 }
3471                 break;
3472
3473         case ANEG_STATE_COMPLETE_ACK_INIT:
3474                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3475                         ret = ANEG_FAILED;
3476                         break;
3477                 }
3478                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3479                                MR_LP_ADV_HALF_DUPLEX |
3480                                MR_LP_ADV_SYM_PAUSE |
3481                                MR_LP_ADV_ASYM_PAUSE |
3482                                MR_LP_ADV_REMOTE_FAULT1 |
3483                                MR_LP_ADV_REMOTE_FAULT2 |
3484                                MR_LP_ADV_NEXT_PAGE |
3485                                MR_TOGGLE_RX |
3486                                MR_NP_RX);
3487                 if (ap->rxconfig & ANEG_CFG_FD)
3488                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3489                 if (ap->rxconfig & ANEG_CFG_HD)
3490                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3491                 if (ap->rxconfig & ANEG_CFG_PS1)
3492                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3493                 if (ap->rxconfig & ANEG_CFG_PS2)
3494                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3495                 if (ap->rxconfig & ANEG_CFG_RF1)
3496                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3497                 if (ap->rxconfig & ANEG_CFG_RF2)
3498                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3499                 if (ap->rxconfig & ANEG_CFG_NP)
3500                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3501
3502                 ap->link_time = ap->cur_time;
3503
3504                 ap->flags ^= (MR_TOGGLE_TX);
3505                 if (ap->rxconfig & 0x0008)
3506                         ap->flags |= MR_TOGGLE_RX;
3507                 if (ap->rxconfig & ANEG_CFG_NP)
3508                         ap->flags |= MR_NP_RX;
3509                 ap->flags |= MR_PAGE_RX;
3510
3511                 ap->state = ANEG_STATE_COMPLETE_ACK;
3512                 ret = ANEG_TIMER_ENAB;
3513                 break;
3514
3515         case ANEG_STATE_COMPLETE_ACK:
3516                 if (ap->ability_match != 0 &&
3517                     ap->rxconfig == 0) {
3518                         ap->state = ANEG_STATE_AN_ENABLE;
3519                         break;
3520                 }
3521                 delta = ap->cur_time - ap->link_time;
3522                 if (delta > ANEG_STATE_SETTLE_TIME) {
3523                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3524                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3525                         } else {
3526                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3527                                     !(ap->flags & MR_NP_RX)) {
3528                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3529                                 } else {
3530                                         ret = ANEG_FAILED;
3531                                 }
3532                         }
3533                 }
3534                 break;
3535
3536         case ANEG_STATE_IDLE_DETECT_INIT:
3537                 ap->link_time = ap->cur_time;
3538                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3539                 tw32_f(MAC_MODE, tp->mac_mode);
3540                 udelay(40);
3541
3542                 ap->state = ANEG_STATE_IDLE_DETECT;
3543                 ret = ANEG_TIMER_ENAB;
3544                 break;
3545
3546         case ANEG_STATE_IDLE_DETECT:
3547                 if (ap->ability_match != 0 &&
3548                     ap->rxconfig == 0) {
3549                         ap->state = ANEG_STATE_AN_ENABLE;
3550                         break;
3551                 }
3552                 delta = ap->cur_time - ap->link_time;
3553                 if (delta > ANEG_STATE_SETTLE_TIME) {
3554                         /* XXX another gem from the Broadcom driver :( */
3555                         ap->state = ANEG_STATE_LINK_OK;
3556                 }
3557                 break;
3558
3559         case ANEG_STATE_LINK_OK:
3560                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3561                 ret = ANEG_DONE;
3562                 break;
3563
3564         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3565                 /* ??? unimplemented */
3566                 break;
3567
3568         case ANEG_STATE_NEXT_PAGE_WAIT:
3569                 /* ??? unimplemented */
3570                 break;
3571
3572         default:
3573                 ret = ANEG_FAILED;
3574                 break;
3575         }
3576
3577         return ret;
3578 }
3579
3580 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3581 {
3582         int res = 0;
3583         struct tg3_fiber_aneginfo aninfo;
3584         int status = ANEG_FAILED;
3585         unsigned int tick;
3586         u32 tmp;
3587
3588         tw32_f(MAC_TX_AUTO_NEG, 0);
3589
3590         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3591         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3592         udelay(40);
3593
3594         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3595         udelay(40);
3596
3597         memset(&aninfo, 0, sizeof(aninfo));
3598         aninfo.flags |= MR_AN_ENABLE;
3599         aninfo.state = ANEG_STATE_UNKNOWN;
3600         aninfo.cur_time = 0;
3601         tick = 0;
3602         while (++tick < 195000) {
3603                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3604                 if (status == ANEG_DONE || status == ANEG_FAILED)
3605                         break;
3606
3607                 udelay(1);
3608         }
3609
3610         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3611         tw32_f(MAC_MODE, tp->mac_mode);
3612         udelay(40);
3613
3614         *txflags = aninfo.txconfig;
3615         *rxflags = aninfo.flags;
3616
3617         if (status == ANEG_DONE &&
3618             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3619                              MR_LP_ADV_FULL_DUPLEX)))
3620                 res = 1;
3621
3622         return res;
3623 }
3624
3625 static void tg3_init_bcm8002(struct tg3 *tp)
3626 {
3627         u32 mac_status = tr32(MAC_STATUS);
3628         int i;
3629
3630         /* Reset when initting first time or we have a link. */
3631         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3632             !(mac_status & MAC_STATUS_PCS_SYNCED))
3633                 return;
3634
3635         /* Set PLL lock range. */
3636         tg3_writephy(tp, 0x16, 0x8007);
3637
3638         /* SW reset */
3639         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3640
3641         /* Wait for reset to complete. */
3642         /* XXX schedule_timeout() ... */
3643         for (i = 0; i < 500; i++)
3644                 udelay(10);
3645
3646         /* Config mode; select PMA/Ch 1 regs. */
3647         tg3_writephy(tp, 0x10, 0x8411);
3648
3649         /* Enable auto-lock and comdet, select txclk for tx. */
3650         tg3_writephy(tp, 0x11, 0x0a10);
3651
3652         tg3_writephy(tp, 0x18, 0x00a0);
3653         tg3_writephy(tp, 0x16, 0x41ff);
3654
3655         /* Assert and deassert POR. */
3656         tg3_writephy(tp, 0x13, 0x0400);
3657         udelay(40);
3658         tg3_writephy(tp, 0x13, 0x0000);
3659
3660         tg3_writephy(tp, 0x11, 0x0a50);
3661         udelay(40);
3662         tg3_writephy(tp, 0x11, 0x0a10);
3663
3664         /* Wait for signal to stabilize */
3665         /* XXX schedule_timeout() ... */
3666         for (i = 0; i < 15000; i++)
3667                 udelay(10);
3668
3669         /* Deselect the channel register so we can read the PHYID
3670          * later.
3671          */
3672         tg3_writephy(tp, 0x10, 0x8011);
3673 }
3674
3675 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3676 {
3677         u16 flowctrl;
3678         u32 sg_dig_ctrl, sg_dig_status;
3679         u32 serdes_cfg, expected_sg_dig_ctrl;
3680         int workaround, port_a;
3681         int current_link_up;
3682
3683         serdes_cfg = 0;
3684         expected_sg_dig_ctrl = 0;
3685         workaround = 0;
3686         port_a = 1;
3687         current_link_up = 0;
3688
3689         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3690             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3691                 workaround = 1;
3692                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3693                         port_a = 0;
3694
3695                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3696                 /* preserve bits 20-23 for voltage regulator */
3697                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3698         }
3699
3700         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3701
3702         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3703                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3704                         if (workaround) {
3705                                 u32 val = serdes_cfg;
3706
3707                                 if (port_a)
3708                                         val |= 0xc010000;
3709                                 else
3710                                         val |= 0x4010000;
3711                                 tw32_f(MAC_SERDES_CFG, val);
3712                         }
3713
3714                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3715                 }
3716                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3717                         tg3_setup_flow_control(tp, 0, 0);
3718                         current_link_up = 1;
3719                 }
3720                 goto out;
3721         }
3722
3723         /* Want auto-negotiation.  */
3724         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3725
3726         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3727         if (flowctrl & ADVERTISE_1000XPAUSE)
3728                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3729         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3730                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3731
3732         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3733                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3734                     tp->serdes_counter &&
3735                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3736                                     MAC_STATUS_RCVD_CFG)) ==
3737                      MAC_STATUS_PCS_SYNCED)) {
3738                         tp->serdes_counter--;
3739                         current_link_up = 1;
3740                         goto out;
3741                 }
3742 restart_autoneg:
3743                 if (workaround)
3744                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3745                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3746                 udelay(5);
3747                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3748
3749                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3750                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3751         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3752                                  MAC_STATUS_SIGNAL_DET)) {
3753                 sg_dig_status = tr32(SG_DIG_STATUS);
3754                 mac_status = tr32(MAC_STATUS);
3755
3756                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3757                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3758                         u32 local_adv = 0, remote_adv = 0;
3759
3760                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3761                                 local_adv |= ADVERTISE_1000XPAUSE;
3762                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3763                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3764
3765                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3766                                 remote_adv |= LPA_1000XPAUSE;
3767                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3768                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3769
3770                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3771                         current_link_up = 1;
3772                         tp->serdes_counter = 0;
3773                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3774                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3775                         if (tp->serdes_counter)
3776                                 tp->serdes_counter--;
3777                         else {
3778                                 if (workaround) {
3779                                         u32 val = serdes_cfg;
3780
3781                                         if (port_a)
3782                                                 val |= 0xc010000;
3783                                         else
3784                                                 val |= 0x4010000;
3785
3786                                         tw32_f(MAC_SERDES_CFG, val);
3787                                 }
3788
3789                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3790                                 udelay(40);
3791
3792                                 /* Link parallel detection - link is up */
3793                                 /* only if we have PCS_SYNC and not */
3794                                 /* receiving config code words */
3795                                 mac_status = tr32(MAC_STATUS);
3796                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3797                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3798                                         tg3_setup_flow_control(tp, 0, 0);
3799                                         current_link_up = 1;
3800                                         tp->tg3_flags2 |=
3801                                                 TG3_FLG2_PARALLEL_DETECT;
3802                                         tp->serdes_counter =
3803                                                 SERDES_PARALLEL_DET_TIMEOUT;
3804                                 } else
3805                                         goto restart_autoneg;
3806                         }
3807                 }
3808         } else {
3809                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3810                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3811         }
3812
3813 out:
3814         return current_link_up;
3815 }
3816
3817 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3818 {
3819         int current_link_up = 0;
3820
3821         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3822                 goto out;
3823
3824         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3825                 u32 txflags, rxflags;
3826                 int i;
3827
3828                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3829                         u32 local_adv = 0, remote_adv = 0;
3830
3831                         if (txflags & ANEG_CFG_PS1)
3832                                 local_adv |= ADVERTISE_1000XPAUSE;
3833                         if (txflags & ANEG_CFG_PS2)
3834                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3835
3836                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3837                                 remote_adv |= LPA_1000XPAUSE;
3838                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3839                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3840
3841                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3842
3843                         current_link_up = 1;
3844                 }
3845                 for (i = 0; i < 30; i++) {
3846                         udelay(20);
3847                         tw32_f(MAC_STATUS,
3848                                (MAC_STATUS_SYNC_CHANGED |
3849                                 MAC_STATUS_CFG_CHANGED));
3850                         udelay(40);
3851                         if ((tr32(MAC_STATUS) &
3852                              (MAC_STATUS_SYNC_CHANGED |
3853                               MAC_STATUS_CFG_CHANGED)) == 0)
3854                                 break;
3855                 }
3856
3857                 mac_status = tr32(MAC_STATUS);
3858                 if (current_link_up == 0 &&
3859                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3860                     !(mac_status & MAC_STATUS_RCVD_CFG))
3861                         current_link_up = 1;
3862         } else {
3863                 tg3_setup_flow_control(tp, 0, 0);
3864
3865                 /* Forcing 1000FD link up. */
3866                 current_link_up = 1;
3867
3868                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3869                 udelay(40);
3870
3871                 tw32_f(MAC_MODE, tp->mac_mode);
3872                 udelay(40);
3873         }
3874
3875 out:
3876         return current_link_up;
3877 }
3878
3879 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3880 {
3881         u32 orig_pause_cfg;
3882         u16 orig_active_speed;
3883         u8 orig_active_duplex;
3884         u32 mac_status;
3885         int current_link_up;
3886         int i;
3887
3888         orig_pause_cfg = tp->link_config.active_flowctrl;
3889         orig_active_speed = tp->link_config.active_speed;
3890         orig_active_duplex = tp->link_config.active_duplex;
3891
3892         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3893             netif_carrier_ok(tp->dev) &&
3894             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3895                 mac_status = tr32(MAC_STATUS);
3896                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3897                                MAC_STATUS_SIGNAL_DET |
3898                                MAC_STATUS_CFG_CHANGED |
3899                                MAC_STATUS_RCVD_CFG);
3900                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3901                                    MAC_STATUS_SIGNAL_DET)) {
3902                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3903                                             MAC_STATUS_CFG_CHANGED));
3904                         return 0;
3905                 }
3906         }
3907
3908         tw32_f(MAC_TX_AUTO_NEG, 0);
3909
3910         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3911         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3912         tw32_f(MAC_MODE, tp->mac_mode);
3913         udelay(40);
3914
3915         if (tp->phy_id == PHY_ID_BCM8002)
3916                 tg3_init_bcm8002(tp);
3917
3918         /* Enable link change event even when serdes polling.  */
3919         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3920         udelay(40);
3921
3922         current_link_up = 0;
3923         mac_status = tr32(MAC_STATUS);
3924
3925         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3926                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3927         else
3928                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3929
3930         tp->napi[0].hw_status->status =
3931                 (SD_STATUS_UPDATED |
3932                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3933
3934         for (i = 0; i < 100; i++) {
3935                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3936                                     MAC_STATUS_CFG_CHANGED));
3937                 udelay(5);
3938                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3939                                          MAC_STATUS_CFG_CHANGED |
3940                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3941                         break;
3942         }
3943
3944         mac_status = tr32(MAC_STATUS);
3945         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3946                 current_link_up = 0;
3947                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3948                     tp->serdes_counter == 0) {
3949                         tw32_f(MAC_MODE, (tp->mac_mode |
3950                                           MAC_MODE_SEND_CONFIGS));
3951                         udelay(1);
3952                         tw32_f(MAC_MODE, tp->mac_mode);
3953                 }
3954         }
3955
3956         if (current_link_up == 1) {
3957                 tp->link_config.active_speed = SPEED_1000;
3958                 tp->link_config.active_duplex = DUPLEX_FULL;
3959                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3960                                     LED_CTRL_LNKLED_OVERRIDE |
3961                                     LED_CTRL_1000MBPS_ON));
3962         } else {
3963                 tp->link_config.active_speed = SPEED_INVALID;
3964                 tp->link_config.active_duplex = DUPLEX_INVALID;
3965                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3966                                     LED_CTRL_LNKLED_OVERRIDE |
3967                                     LED_CTRL_TRAFFIC_OVERRIDE));
3968         }
3969
3970         if (current_link_up != netif_carrier_ok(tp->dev)) {
3971                 if (current_link_up)
3972                         netif_carrier_on(tp->dev);
3973                 else
3974                         netif_carrier_off(tp->dev);
3975                 tg3_link_report(tp);
3976         } else {
3977                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3978                 if (orig_pause_cfg != now_pause_cfg ||
3979                     orig_active_speed != tp->link_config.active_speed ||
3980                     orig_active_duplex != tp->link_config.active_duplex)
3981                         tg3_link_report(tp);
3982         }
3983
3984         return 0;
3985 }
3986
3987 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3988 {
3989         int current_link_up, err = 0;
3990         u32 bmsr, bmcr;
3991         u16 current_speed;
3992         u8 current_duplex;
3993         u32 local_adv, remote_adv;
3994
3995         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3996         tw32_f(MAC_MODE, tp->mac_mode);
3997         udelay(40);
3998
3999         tw32(MAC_EVENT, 0);
4000
4001         tw32_f(MAC_STATUS,
4002              (MAC_STATUS_SYNC_CHANGED |
4003               MAC_STATUS_CFG_CHANGED |
4004               MAC_STATUS_MI_COMPLETION |
4005               MAC_STATUS_LNKSTATE_CHANGED));
4006         udelay(40);
4007
4008         if (force_reset)
4009                 tg3_phy_reset(tp);
4010
4011         current_link_up = 0;
4012         current_speed = SPEED_INVALID;
4013         current_duplex = DUPLEX_INVALID;
4014
4015         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4016         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4017         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4018                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4019                         bmsr |= BMSR_LSTATUS;
4020                 else
4021                         bmsr &= ~BMSR_LSTATUS;
4022         }
4023
4024         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4025
4026         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4027             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4028                 /* do nothing, just check for link up at the end */
4029         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4030                 u32 adv, new_adv;
4031
4032                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4033                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4034                                   ADVERTISE_1000XPAUSE |
4035                                   ADVERTISE_1000XPSE_ASYM |
4036                                   ADVERTISE_SLCT);
4037
4038                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4039
4040                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4041                         new_adv |= ADVERTISE_1000XHALF;
4042                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4043                         new_adv |= ADVERTISE_1000XFULL;
4044
4045                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4046                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4047                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4048                         tg3_writephy(tp, MII_BMCR, bmcr);
4049
4050                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4051                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4052                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4053
4054                         return err;
4055                 }
4056         } else {
4057                 u32 new_bmcr;
4058
4059                 bmcr &= ~BMCR_SPEED1000;
4060                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4061
4062                 if (tp->link_config.duplex == DUPLEX_FULL)
4063                         new_bmcr |= BMCR_FULLDPLX;
4064
4065                 if (new_bmcr != bmcr) {
4066                         /* BMCR_SPEED1000 is a reserved bit that needs
4067                          * to be set on write.
4068                          */
4069                         new_bmcr |= BMCR_SPEED1000;
4070
4071                         /* Force a linkdown */
4072                         if (netif_carrier_ok(tp->dev)) {
4073                                 u32 adv;
4074
4075                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4076                                 adv &= ~(ADVERTISE_1000XFULL |
4077                                          ADVERTISE_1000XHALF |
4078                                          ADVERTISE_SLCT);
4079                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4080                                 tg3_writephy(tp, MII_BMCR, bmcr |
4081                                                            BMCR_ANRESTART |
4082                                                            BMCR_ANENABLE);
4083                                 udelay(10);
4084                                 netif_carrier_off(tp->dev);
4085                         }
4086                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4087                         bmcr = new_bmcr;
4088                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4089                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4090                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4091                             ASIC_REV_5714) {
4092                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4093                                         bmsr |= BMSR_LSTATUS;
4094                                 else
4095                                         bmsr &= ~BMSR_LSTATUS;
4096                         }
4097                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4098                 }
4099         }
4100
4101         if (bmsr & BMSR_LSTATUS) {
4102                 current_speed = SPEED_1000;
4103                 current_link_up = 1;
4104                 if (bmcr & BMCR_FULLDPLX)
4105                         current_duplex = DUPLEX_FULL;
4106                 else
4107                         current_duplex = DUPLEX_HALF;
4108
4109                 local_adv = 0;
4110                 remote_adv = 0;
4111
4112                 if (bmcr & BMCR_ANENABLE) {
4113                         u32 common;
4114
4115                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4116                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4117                         common = local_adv & remote_adv;
4118                         if (common & (ADVERTISE_1000XHALF |
4119                                       ADVERTISE_1000XFULL)) {
4120                                 if (common & ADVERTISE_1000XFULL)
4121                                         current_duplex = DUPLEX_FULL;
4122                                 else
4123                                         current_duplex = DUPLEX_HALF;
4124                         }
4125                         else
4126                                 current_link_up = 0;
4127                 }
4128         }
4129
4130         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4131                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4132
4133         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4134         if (tp->link_config.active_duplex == DUPLEX_HALF)
4135                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4136
4137         tw32_f(MAC_MODE, tp->mac_mode);
4138         udelay(40);
4139
4140         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4141
4142         tp->link_config.active_speed = current_speed;
4143         tp->link_config.active_duplex = current_duplex;
4144
4145         if (current_link_up != netif_carrier_ok(tp->dev)) {
4146                 if (current_link_up)
4147                         netif_carrier_on(tp->dev);
4148                 else {
4149                         netif_carrier_off(tp->dev);
4150                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4151                 }
4152                 tg3_link_report(tp);
4153         }
4154         return err;
4155 }
4156
4157 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4158 {
4159         if (tp->serdes_counter) {
4160                 /* Give autoneg time to complete. */
4161                 tp->serdes_counter--;
4162                 return;
4163         }
4164         if (!netif_carrier_ok(tp->dev) &&
4165             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4166                 u32 bmcr;
4167
4168                 tg3_readphy(tp, MII_BMCR, &bmcr);
4169                 if (bmcr & BMCR_ANENABLE) {
4170                         u32 phy1, phy2;
4171
4172                         /* Select shadow register 0x1f */
4173                         tg3_writephy(tp, 0x1c, 0x7c00);
4174                         tg3_readphy(tp, 0x1c, &phy1);
4175
4176                         /* Select expansion interrupt status register */
4177                         tg3_writephy(tp, 0x17, 0x0f01);
4178                         tg3_readphy(tp, 0x15, &phy2);
4179                         tg3_readphy(tp, 0x15, &phy2);
4180
4181                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4182                                 /* We have signal detect and not receiving
4183                                  * config code words, link is up by parallel
4184                                  * detection.
4185                                  */
4186
4187                                 bmcr &= ~BMCR_ANENABLE;
4188                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4189                                 tg3_writephy(tp, MII_BMCR, bmcr);
4190                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4191                         }
4192                 }
4193         }
4194         else if (netif_carrier_ok(tp->dev) &&
4195                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4196                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4197                 u32 phy2;
4198
4199                 /* Select expansion interrupt status register */
4200                 tg3_writephy(tp, 0x17, 0x0f01);
4201                 tg3_readphy(tp, 0x15, &phy2);
4202                 if (phy2 & 0x20) {
4203                         u32 bmcr;
4204
4205                         /* Config code words received, turn on autoneg. */
4206                         tg3_readphy(tp, MII_BMCR, &bmcr);
4207                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4208
4209                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4210
4211                 }
4212         }
4213 }
4214
4215 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4216 {
4217         int err;
4218
4219         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4220                 err = tg3_setup_fiber_phy(tp, force_reset);
4221         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4222                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4223         } else {
4224                 err = tg3_setup_copper_phy(tp, force_reset);
4225         }
4226
4227         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4228                 u32 val, scale;
4229
4230                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4231                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4232                         scale = 65;
4233                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4234                         scale = 6;
4235                 else
4236                         scale = 12;
4237
4238                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4239                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4240                 tw32(GRC_MISC_CFG, val);
4241         }
4242
4243         if (tp->link_config.active_speed == SPEED_1000 &&
4244             tp->link_config.active_duplex == DUPLEX_HALF)
4245                 tw32(MAC_TX_LENGTHS,
4246                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4247                       (6 << TX_LENGTHS_IPG_SHIFT) |
4248                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4249         else
4250                 tw32(MAC_TX_LENGTHS,
4251                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4252                       (6 << TX_LENGTHS_IPG_SHIFT) |
4253                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4254
4255         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4256                 if (netif_carrier_ok(tp->dev)) {
4257                         tw32(HOSTCC_STAT_COAL_TICKS,
4258                              tp->coal.stats_block_coalesce_usecs);
4259                 } else {
4260                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4261                 }
4262         }
4263
4264         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4265                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4266                 if (!netif_carrier_ok(tp->dev))
4267                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4268                               tp->pwrmgmt_thresh;
4269                 else
4270                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4271                 tw32(PCIE_PWR_MGMT_THRESH, val);
4272         }
4273
4274         return err;
4275 }
4276
4277 /* This is called whenever we suspect that the system chipset is re-
4278  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4279  * is bogus tx completions. We try to recover by setting the
4280  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4281  * in the workqueue.
4282  */
4283 static void tg3_tx_recover(struct tg3 *tp)
4284 {
4285         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4286                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4287
4288         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4289                "mapped I/O cycles to the network device, attempting to "
4290                "recover. Please report the problem to the driver maintainer "
4291                "and include system chipset information.\n", tp->dev->name);
4292
4293         spin_lock(&tp->lock);
4294         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4295         spin_unlock(&tp->lock);
4296 }
4297
4298 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4299 {
4300         smp_mb();
4301         return tnapi->tx_pending -
4302                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4303 }
4304
4305 /* Tigon3 never reports partial packet sends.  So we do not
4306  * need special logic to handle SKBs that have not had all
4307  * of their frags sent yet, like SunGEM does.
4308  */
4309 static void tg3_tx(struct tg3_napi *tnapi)
4310 {
4311         struct tg3 *tp = tnapi->tp;
4312         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4313         u32 sw_idx = tnapi->tx_cons;
4314         struct netdev_queue *txq;
4315         int index = tnapi - tp->napi;
4316
4317         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4318                 index--;
4319
4320         txq = netdev_get_tx_queue(tp->dev, index);
4321
4322         while (sw_idx != hw_idx) {
4323                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4324                 struct sk_buff *skb = ri->skb;
4325                 int i, tx_bug = 0;
4326
4327                 if (unlikely(skb == NULL)) {
4328                         tg3_tx_recover(tp);
4329                         return;
4330                 }
4331
4332                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4333
4334                 ri->skb = NULL;
4335
4336                 sw_idx = NEXT_TX(sw_idx);
4337
4338                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4339                         ri = &tnapi->tx_buffers[sw_idx];
4340                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4341                                 tx_bug = 1;
4342                         sw_idx = NEXT_TX(sw_idx);
4343                 }
4344
4345                 dev_kfree_skb(skb);
4346
4347                 if (unlikely(tx_bug)) {
4348                         tg3_tx_recover(tp);
4349                         return;
4350                 }
4351         }
4352
4353         tnapi->tx_cons = sw_idx;
4354
4355         /* Need to make the tx_cons update visible to tg3_start_xmit()
4356          * before checking for netif_queue_stopped().  Without the
4357          * memory barrier, there is a small possibility that tg3_start_xmit()
4358          * will miss it and cause the queue to be stopped forever.
4359          */
4360         smp_mb();
4361
4362         if (unlikely(netif_tx_queue_stopped(txq) &&
4363                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4364                 __netif_tx_lock(txq, smp_processor_id());
4365                 if (netif_tx_queue_stopped(txq) &&
4366                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4367                         netif_tx_wake_queue(txq);
4368                 __netif_tx_unlock(txq);
4369         }
4370 }
4371
4372 /* Returns size of skb allocated or < 0 on error.
4373  *
4374  * We only need to fill in the address because the other members
4375  * of the RX descriptor are invariant, see tg3_init_rings.
4376  *
4377  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4378  * posting buffers we only dirty the first cache line of the RX
4379  * descriptor (containing the address).  Whereas for the RX status
4380  * buffers the cpu only reads the last cacheline of the RX descriptor
4381  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4382  */
4383 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4384                             int src_idx, u32 dest_idx_unmasked)
4385 {
4386         struct tg3 *tp = tnapi->tp;
4387         struct tg3_rx_buffer_desc *desc;
4388         struct ring_info *map, *src_map;
4389         struct sk_buff *skb;
4390         dma_addr_t mapping;
4391         int skb_size, dest_idx;
4392         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4393
4394         src_map = NULL;
4395         switch (opaque_key) {
4396         case RXD_OPAQUE_RING_STD:
4397                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4398                 desc = &tpr->rx_std[dest_idx];
4399                 map = &tpr->rx_std_buffers[dest_idx];
4400                 if (src_idx >= 0)
4401                         src_map = &tpr->rx_std_buffers[src_idx];
4402                 skb_size = tp->rx_pkt_map_sz;
4403                 break;
4404
4405         case RXD_OPAQUE_RING_JUMBO:
4406                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4407                 desc = &tpr->rx_jmb[dest_idx].std;
4408                 map = &tpr->rx_jmb_buffers[dest_idx];
4409                 if (src_idx >= 0)
4410                         src_map = &tpr->rx_jmb_buffers[src_idx];
4411                 skb_size = TG3_RX_JMB_MAP_SZ;
4412                 break;
4413
4414         default:
4415                 return -EINVAL;
4416         }
4417
4418         /* Do not overwrite any of the map or rp information
4419          * until we are sure we can commit to a new buffer.
4420          *
4421          * Callers depend upon this behavior and assume that
4422          * we leave everything unchanged if we fail.
4423          */
4424         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4425         if (skb == NULL)
4426                 return -ENOMEM;
4427
4428         skb_reserve(skb, tp->rx_offset);
4429
4430         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4431                                  PCI_DMA_FROMDEVICE);
4432
4433         map->skb = skb;
4434         pci_unmap_addr_set(map, mapping, mapping);
4435
4436         if (src_map != NULL)
4437                 src_map->skb = NULL;
4438
4439         desc->addr_hi = ((u64)mapping >> 32);
4440         desc->addr_lo = ((u64)mapping & 0xffffffff);
4441
4442         return skb_size;
4443 }
4444
4445 /* We only need to move over in the address because the other
4446  * members of the RX descriptor are invariant.  See notes above
4447  * tg3_alloc_rx_skb for full details.
4448  */
4449 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4450                            int src_idx, u32 dest_idx_unmasked)
4451 {
4452         struct tg3 *tp = tnapi->tp;
4453         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4454         struct ring_info *src_map, *dest_map;
4455         int dest_idx;
4456         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4457
4458         switch (opaque_key) {
4459         case RXD_OPAQUE_RING_STD:
4460                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4461                 dest_desc = &tpr->rx_std[dest_idx];
4462                 dest_map = &tpr->rx_std_buffers[dest_idx];
4463                 src_desc = &tpr->rx_std[src_idx];
4464                 src_map = &tpr->rx_std_buffers[src_idx];
4465                 break;
4466
4467         case RXD_OPAQUE_RING_JUMBO:
4468                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4469                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4470                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4471                 src_desc = &tpr->rx_jmb[src_idx].std;
4472                 src_map = &tpr->rx_jmb_buffers[src_idx];
4473                 break;
4474
4475         default:
4476                 return;
4477         }
4478
4479         dest_map->skb = src_map->skb;
4480         pci_unmap_addr_set(dest_map, mapping,
4481                            pci_unmap_addr(src_map, mapping));
4482         dest_desc->addr_hi = src_desc->addr_hi;
4483         dest_desc->addr_lo = src_desc->addr_lo;
4484
4485         src_map->skb = NULL;
4486 }
4487
4488 /* The RX ring scheme is composed of multiple rings which post fresh
4489  * buffers to the chip, and one special ring the chip uses to report
4490  * status back to the host.
4491  *
4492  * The special ring reports the status of received packets to the
4493  * host.  The chip does not write into the original descriptor the
4494  * RX buffer was obtained from.  The chip simply takes the original
4495  * descriptor as provided by the host, updates the status and length
4496  * field, then writes this into the next status ring entry.
4497  *
4498  * Each ring the host uses to post buffers to the chip is described
4499  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4500  * it is first placed into the on-chip ram.  When the packet's length
4501  * is known, it walks down the TG3_BDINFO entries to select the ring.
4502  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4503  * which is within the range of the new packet's length is chosen.
4504  *
4505  * The "separate ring for rx status" scheme may sound queer, but it makes
4506  * sense from a cache coherency perspective.  If only the host writes
4507  * to the buffer post rings, and only the chip writes to the rx status
4508  * rings, then cache lines never move beyond shared-modified state.
4509  * If both the host and chip were to write into the same ring, cache line
4510  * eviction could occur since both entities want it in an exclusive state.
4511  */
4512 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4513 {
4514         struct tg3 *tp = tnapi->tp;
4515         u32 work_mask, rx_std_posted = 0;
4516         u32 sw_idx = tnapi->rx_rcb_ptr;
4517         u16 hw_idx;
4518         int received;
4519         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4520
4521         hw_idx = tnapi->hw_status->idx[0].rx_producer;
4522         /*
4523          * We need to order the read of hw_idx and the read of
4524          * the opaque cookie.
4525          */
4526         rmb();
4527         work_mask = 0;
4528         received = 0;
4529         while (sw_idx != hw_idx && budget > 0) {
4530                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4531                 unsigned int len;
4532                 struct sk_buff *skb;
4533                 dma_addr_t dma_addr;
4534                 u32 opaque_key, desc_idx, *post_ptr;
4535
4536                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4537                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4538                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4539                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4540                         dma_addr = pci_unmap_addr(ri, mapping);
4541                         skb = ri->skb;
4542                         post_ptr = &tpr->rx_std_ptr;
4543                         rx_std_posted++;
4544                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4545                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4546                         dma_addr = pci_unmap_addr(ri, mapping);
4547                         skb = ri->skb;
4548                         post_ptr = &tpr->rx_jmb_ptr;
4549                 } else
4550                         goto next_pkt_nopost;
4551
4552                 work_mask |= opaque_key;
4553
4554                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4555                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4556                 drop_it:
4557                         tg3_recycle_rx(tnapi, opaque_key,
4558                                        desc_idx, *post_ptr);
4559                 drop_it_no_recycle:
4560                         /* Other statistics kept track of by card. */
4561                         tp->net_stats.rx_dropped++;
4562                         goto next_pkt;
4563                 }
4564
4565                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4566                       ETH_FCS_LEN;
4567
4568                 if (len > RX_COPY_THRESHOLD
4569                         && tp->rx_offset == NET_IP_ALIGN
4570                         /* rx_offset will likely not equal NET_IP_ALIGN
4571                          * if this is a 5701 card running in PCI-X mode
4572                          * [see tg3_get_invariants()]
4573                          */
4574                 ) {
4575                         int skb_size;
4576
4577                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4578                                                     desc_idx, *post_ptr);
4579                         if (skb_size < 0)
4580                                 goto drop_it;
4581
4582                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4583                                          PCI_DMA_FROMDEVICE);
4584
4585                         skb_put(skb, len);
4586                 } else {
4587                         struct sk_buff *copy_skb;
4588
4589                         tg3_recycle_rx(tnapi, opaque_key,
4590                                        desc_idx, *post_ptr);
4591
4592                         copy_skb = netdev_alloc_skb(tp->dev,
4593                                                     len + TG3_RAW_IP_ALIGN);
4594                         if (copy_skb == NULL)
4595                                 goto drop_it_no_recycle;
4596
4597                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4598                         skb_put(copy_skb, len);
4599                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4600                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4601                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4602
4603                         /* We'll reuse the original ring buffer. */
4604                         skb = copy_skb;
4605                 }
4606
4607                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4608                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4609                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4610                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4611                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4612                 else
4613                         skb->ip_summed = CHECKSUM_NONE;
4614
4615                 skb->protocol = eth_type_trans(skb, tp->dev);
4616
4617                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4618                     skb->protocol != htons(ETH_P_8021Q)) {
4619                         dev_kfree_skb(skb);
4620                         goto next_pkt;
4621                 }
4622
4623 #if TG3_VLAN_TAG_USED
4624                 if (tp->vlgrp != NULL &&
4625                     desc->type_flags & RXD_FLAG_VLAN) {
4626                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4627                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4628                 } else
4629 #endif
4630                         napi_gro_receive(&tnapi->napi, skb);
4631
4632                 received++;
4633                 budget--;
4634
4635 next_pkt:
4636                 (*post_ptr)++;
4637
4638                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4639                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4640
4641                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4642                                      TG3_64BIT_REG_LOW, idx);
4643                         work_mask &= ~RXD_OPAQUE_RING_STD;
4644                         rx_std_posted = 0;
4645                 }
4646 next_pkt_nopost:
4647                 sw_idx++;
4648                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4649
4650                 /* Refresh hw_idx to see if there is new work */
4651                 if (sw_idx == hw_idx) {
4652                         hw_idx = tnapi->hw_status->idx[0].rx_producer;
4653                         rmb();
4654                 }
4655         }
4656
4657         /* ACK the status ring. */
4658         tnapi->rx_rcb_ptr = sw_idx;
4659         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4660
4661         /* Refill RX ring(s). */
4662         if (work_mask & RXD_OPAQUE_RING_STD) {
4663                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4664                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4665                              sw_idx);
4666         }
4667         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4668                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4669                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4670                              sw_idx);
4671         }
4672         mmiowb();
4673
4674         return received;
4675 }
4676
4677 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4678 {
4679         struct tg3 *tp = tnapi->tp;
4680         struct tg3_hw_status *sblk = tnapi->hw_status;
4681
4682         /* handle link change and other phy events */
4683         if (!(tp->tg3_flags &
4684               (TG3_FLAG_USE_LINKCHG_REG |
4685                TG3_FLAG_POLL_SERDES))) {
4686                 if (sblk->status & SD_STATUS_LINK_CHG) {
4687                         sblk->status = SD_STATUS_UPDATED |
4688                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4689                         spin_lock(&tp->lock);
4690                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4691                                 tw32_f(MAC_STATUS,
4692                                      (MAC_STATUS_SYNC_CHANGED |
4693                                       MAC_STATUS_CFG_CHANGED |
4694                                       MAC_STATUS_MI_COMPLETION |
4695                                       MAC_STATUS_LNKSTATE_CHANGED));
4696                                 udelay(40);
4697                         } else
4698                                 tg3_setup_phy(tp, 0);
4699                         spin_unlock(&tp->lock);
4700                 }
4701         }
4702
4703         /* run TX completion thread */
4704         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4705                 tg3_tx(tnapi);
4706                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4707                         return work_done;
4708         }
4709
4710         /* run RX thread, within the bounds set by NAPI.
4711          * All RX "locking" is done by ensuring outside
4712          * code synchronizes with tg3->napi.poll()
4713          */
4714         if (sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
4715                 work_done += tg3_rx(tnapi, budget - work_done);
4716
4717         return work_done;
4718 }
4719
4720 static int tg3_poll(struct napi_struct *napi, int budget)
4721 {
4722         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4723         struct tg3 *tp = tnapi->tp;
4724         int work_done = 0;
4725         struct tg3_hw_status *sblk = tnapi->hw_status;
4726
4727         while (1) {
4728                 work_done = tg3_poll_work(tnapi, work_done, budget);
4729
4730                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4731                         goto tx_recovery;
4732
4733                 if (unlikely(work_done >= budget))
4734                         break;
4735
4736                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4737                         /* tp->last_tag is used in tg3_int_reenable() below
4738                          * to tell the hw how much work has been processed,
4739                          * so we must read it before checking for more work.
4740                          */
4741                         tnapi->last_tag = sblk->status_tag;
4742                         tnapi->last_irq_tag = tnapi->last_tag;
4743                         rmb();
4744                 } else
4745                         sblk->status &= ~SD_STATUS_UPDATED;
4746
4747                 if (likely(!tg3_has_work(tnapi))) {
4748                         napi_complete(napi);
4749                         tg3_int_reenable(tnapi);
4750                         break;
4751                 }
4752         }
4753
4754         return work_done;
4755
4756 tx_recovery:
4757         /* work_done is guaranteed to be less than budget. */
4758         napi_complete(napi);
4759         schedule_work(&tp->reset_task);
4760         return work_done;
4761 }
4762
4763 static void tg3_irq_quiesce(struct tg3 *tp)
4764 {
4765         int i;
4766
4767         BUG_ON(tp->irq_sync);
4768
4769         tp->irq_sync = 1;
4770         smp_mb();
4771
4772         for (i = 0; i < tp->irq_cnt; i++)
4773                 synchronize_irq(tp->napi[i].irq_vec);
4774 }
4775
4776 static inline int tg3_irq_sync(struct tg3 *tp)
4777 {
4778         return tp->irq_sync;
4779 }
4780
4781 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4782  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4783  * with as well.  Most of the time, this is not necessary except when
4784  * shutting down the device.
4785  */
4786 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4787 {
4788         spin_lock_bh(&tp->lock);
4789         if (irq_sync)
4790                 tg3_irq_quiesce(tp);
4791 }
4792
4793 static inline void tg3_full_unlock(struct tg3 *tp)
4794 {
4795         spin_unlock_bh(&tp->lock);
4796 }
4797
4798 /* One-shot MSI handler - Chip automatically disables interrupt
4799  * after sending MSI so driver doesn't have to do it.
4800  */
4801 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4802 {
4803         struct tg3_napi *tnapi = dev_id;
4804         struct tg3 *tp = tnapi->tp;
4805
4806         prefetch(tnapi->hw_status);
4807         if (tnapi->rx_rcb)
4808                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4809
4810         if (likely(!tg3_irq_sync(tp)))
4811                 napi_schedule(&tnapi->napi);
4812
4813         return IRQ_HANDLED;
4814 }
4815
4816 /* MSI ISR - No need to check for interrupt sharing and no need to
4817  * flush status block and interrupt mailbox. PCI ordering rules
4818  * guarantee that MSI will arrive after the status block.
4819  */
4820 static irqreturn_t tg3_msi(int irq, void *dev_id)
4821 {
4822         struct tg3_napi *tnapi = dev_id;
4823         struct tg3 *tp = tnapi->tp;
4824
4825         prefetch(tnapi->hw_status);
4826         if (tnapi->rx_rcb)
4827                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4828         /*
4829          * Writing any value to intr-mbox-0 clears PCI INTA# and
4830          * chip-internal interrupt pending events.
4831          * Writing non-zero to intr-mbox-0 additional tells the
4832          * NIC to stop sending us irqs, engaging "in-intr-handler"
4833          * event coalescing.
4834          */
4835         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4836         if (likely(!tg3_irq_sync(tp)))
4837                 napi_schedule(&tnapi->napi);
4838
4839         return IRQ_RETVAL(1);
4840 }
4841
4842 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4843 {
4844         struct tg3_napi *tnapi = dev_id;
4845         struct tg3 *tp = tnapi->tp;
4846         struct tg3_hw_status *sblk = tnapi->hw_status;
4847         unsigned int handled = 1;
4848
4849         /* In INTx mode, it is possible for the interrupt to arrive at
4850          * the CPU before the status block posted prior to the interrupt.
4851          * Reading the PCI State register will confirm whether the
4852          * interrupt is ours and will flush the status block.
4853          */
4854         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4855                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4856                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4857                         handled = 0;
4858                         goto out;
4859                 }
4860         }
4861
4862         /*
4863          * Writing any value to intr-mbox-0 clears PCI INTA# and
4864          * chip-internal interrupt pending events.
4865          * Writing non-zero to intr-mbox-0 additional tells the
4866          * NIC to stop sending us irqs, engaging "in-intr-handler"
4867          * event coalescing.
4868          *
4869          * Flush the mailbox to de-assert the IRQ immediately to prevent
4870          * spurious interrupts.  The flush impacts performance but
4871          * excessive spurious interrupts can be worse in some cases.
4872          */
4873         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4874         if (tg3_irq_sync(tp))
4875                 goto out;
4876         sblk->status &= ~SD_STATUS_UPDATED;
4877         if (likely(tg3_has_work(tnapi))) {
4878                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4879                 napi_schedule(&tnapi->napi);
4880         } else {
4881                 /* No work, shared interrupt perhaps?  re-enable
4882                  * interrupts, and flush that PCI write
4883                  */
4884                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4885                                0x00000000);
4886         }
4887 out:
4888         return IRQ_RETVAL(handled);
4889 }
4890
4891 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4892 {
4893         struct tg3_napi *tnapi = dev_id;
4894         struct tg3 *tp = tnapi->tp;
4895         struct tg3_hw_status *sblk = tnapi->hw_status;
4896         unsigned int handled = 1;
4897
4898         /* In INTx mode, it is possible for the interrupt to arrive at
4899          * the CPU before the status block posted prior to the interrupt.
4900          * Reading the PCI State register will confirm whether the
4901          * interrupt is ours and will flush the status block.
4902          */
4903         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4904                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4905                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4906                         handled = 0;
4907                         goto out;
4908                 }
4909         }
4910
4911         /*
4912          * writing any value to intr-mbox-0 clears PCI INTA# and
4913          * chip-internal interrupt pending events.
4914          * writing non-zero to intr-mbox-0 additional tells the
4915          * NIC to stop sending us irqs, engaging "in-intr-handler"
4916          * event coalescing.
4917          *
4918          * Flush the mailbox to de-assert the IRQ immediately to prevent
4919          * spurious interrupts.  The flush impacts performance but
4920          * excessive spurious interrupts can be worse in some cases.
4921          */
4922         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4923
4924         /*
4925          * In a shared interrupt configuration, sometimes other devices'
4926          * interrupts will scream.  We record the current status tag here
4927          * so that the above check can report that the screaming interrupts
4928          * are unhandled.  Eventually they will be silenced.
4929          */
4930         tnapi->last_irq_tag = sblk->status_tag;
4931
4932         if (tg3_irq_sync(tp))
4933                 goto out;
4934
4935         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4936
4937         napi_schedule(&tnapi->napi);
4938
4939 out:
4940         return IRQ_RETVAL(handled);
4941 }
4942
4943 /* ISR for interrupt test */
4944 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4945 {
4946         struct tg3_napi *tnapi = dev_id;
4947         struct tg3 *tp = tnapi->tp;
4948         struct tg3_hw_status *sblk = tnapi->hw_status;
4949
4950         if ((sblk->status & SD_STATUS_UPDATED) ||
4951             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4952                 tg3_disable_ints(tp);
4953                 return IRQ_RETVAL(1);
4954         }
4955         return IRQ_RETVAL(0);
4956 }
4957
4958 static int tg3_init_hw(struct tg3 *, int);
4959 static int tg3_halt(struct tg3 *, int, int);
4960
4961 /* Restart hardware after configuration changes, self-test, etc.
4962  * Invoked with tp->lock held.
4963  */
4964 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4965         __releases(tp->lock)
4966         __acquires(tp->lock)
4967 {
4968         int err;
4969
4970         err = tg3_init_hw(tp, reset_phy);
4971         if (err) {
4972                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4973                        "aborting.\n", tp->dev->name);
4974                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4975                 tg3_full_unlock(tp);
4976                 del_timer_sync(&tp->timer);
4977                 tp->irq_sync = 0;
4978                 tg3_napi_enable(tp);
4979                 dev_close(tp->dev);
4980                 tg3_full_lock(tp, 0);
4981         }
4982         return err;
4983 }
4984
4985 #ifdef CONFIG_NET_POLL_CONTROLLER
4986 static void tg3_poll_controller(struct net_device *dev)
4987 {
4988         int i;
4989         struct tg3 *tp = netdev_priv(dev);
4990
4991         for (i = 0; i < tp->irq_cnt; i++)
4992                 tg3_interrupt(tp->napi[i].irq_vec, dev);
4993 }
4994 #endif
4995
4996 static void tg3_reset_task(struct work_struct *work)
4997 {
4998         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4999         int err;
5000         unsigned int restart_timer;
5001
5002         tg3_full_lock(tp, 0);
5003
5004         if (!netif_running(tp->dev)) {
5005                 tg3_full_unlock(tp);
5006                 return;
5007         }
5008
5009         tg3_full_unlock(tp);
5010
5011         tg3_phy_stop(tp);
5012
5013         tg3_netif_stop(tp);
5014
5015         tg3_full_lock(tp, 1);
5016
5017         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5018         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5019
5020         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5021                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5022                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5023                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5024                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5025         }
5026
5027         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5028         err = tg3_init_hw(tp, 1);
5029         if (err)
5030                 goto out;
5031
5032         tg3_netif_start(tp);
5033
5034         if (restart_timer)
5035                 mod_timer(&tp->timer, jiffies + 1);
5036
5037 out:
5038         tg3_full_unlock(tp);
5039
5040         if (!err)
5041                 tg3_phy_start(tp);
5042 }
5043
5044 static void tg3_dump_short_state(struct tg3 *tp)
5045 {
5046         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5047                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5048         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5049                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5050 }
5051
5052 static void tg3_tx_timeout(struct net_device *dev)
5053 {
5054         struct tg3 *tp = netdev_priv(dev);
5055
5056         if (netif_msg_tx_err(tp)) {
5057                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5058                        dev->name);
5059                 tg3_dump_short_state(tp);
5060         }
5061
5062         schedule_work(&tp->reset_task);
5063 }
5064
5065 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5066 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5067 {
5068         u32 base = (u32) mapping & 0xffffffff;
5069
5070         return ((base > 0xffffdcc0) &&
5071                 (base + len + 8 < base));
5072 }
5073
5074 /* Test for DMA addresses > 40-bit */
5075 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5076                                           int len)
5077 {
5078 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5079         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5080                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5081         return 0;
5082 #else
5083         return 0;
5084 #endif
5085 }
5086
5087 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5088
5089 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5090 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5091                                        u32 last_plus_one, u32 *start,
5092                                        u32 base_flags, u32 mss)
5093 {
5094         struct tg3_napi *tnapi = &tp->napi[0];
5095         struct sk_buff *new_skb;
5096         dma_addr_t new_addr = 0;
5097         u32 entry = *start;
5098         int i, ret = 0;
5099
5100         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5101                 new_skb = skb_copy(skb, GFP_ATOMIC);
5102         else {
5103                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5104
5105                 new_skb = skb_copy_expand(skb,
5106                                           skb_headroom(skb) + more_headroom,
5107                                           skb_tailroom(skb), GFP_ATOMIC);
5108         }
5109
5110         if (!new_skb) {
5111                 ret = -1;
5112         } else {
5113                 /* New SKB is guaranteed to be linear. */
5114                 entry = *start;
5115                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5116                 new_addr = skb_shinfo(new_skb)->dma_head;
5117
5118                 /* Make sure new skb does not cross any 4G boundaries.
5119                  * Drop the packet if it does.
5120                  */
5121                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5122                         if (!ret)
5123                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5124                                               DMA_TO_DEVICE);
5125                         ret = -1;
5126                         dev_kfree_skb(new_skb);
5127                         new_skb = NULL;
5128                 } else {
5129                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5130                                     base_flags, 1 | (mss << 1));
5131                         *start = NEXT_TX(entry);
5132                 }
5133         }
5134
5135         /* Now clean up the sw ring entries. */
5136         i = 0;
5137         while (entry != last_plus_one) {
5138                 if (i == 0)
5139                         tnapi->tx_buffers[entry].skb = new_skb;
5140                 else
5141                         tnapi->tx_buffers[entry].skb = NULL;
5142                 entry = NEXT_TX(entry);
5143                 i++;
5144         }
5145
5146         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5147         dev_kfree_skb(skb);
5148
5149         return ret;
5150 }
5151
5152 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5153                         dma_addr_t mapping, int len, u32 flags,
5154                         u32 mss_and_is_end)
5155 {
5156         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5157         int is_end = (mss_and_is_end & 0x1);
5158         u32 mss = (mss_and_is_end >> 1);
5159         u32 vlan_tag = 0;
5160
5161         if (is_end)
5162                 flags |= TXD_FLAG_END;
5163         if (flags & TXD_FLAG_VLAN) {
5164                 vlan_tag = flags >> 16;
5165                 flags &= 0xffff;
5166         }
5167         vlan_tag |= (mss << TXD_MSS_SHIFT);
5168
5169         txd->addr_hi = ((u64) mapping >> 32);
5170         txd->addr_lo = ((u64) mapping & 0xffffffff);
5171         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5172         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5173 }
5174
5175 /* hard_start_xmit for devices that don't have any bugs and
5176  * support TG3_FLG2_HW_TSO_2 only.
5177  */
5178 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5179                                   struct net_device *dev)
5180 {
5181         struct tg3 *tp = netdev_priv(dev);
5182         u32 len, entry, base_flags, mss;
5183         struct skb_shared_info *sp;
5184         dma_addr_t mapping;
5185         struct tg3_napi *tnapi;
5186         struct netdev_queue *txq;
5187
5188         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5189         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5190         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5191                 tnapi++;
5192
5193         /* We are running in BH disabled context with netif_tx_lock
5194          * and TX reclaim runs via tp->napi.poll inside of a software
5195          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5196          * no IRQ context deadlocks to worry about either.  Rejoice!
5197          */
5198         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5199                 if (!netif_tx_queue_stopped(txq)) {
5200                         netif_tx_stop_queue(txq);
5201
5202                         /* This is a hard error, log it. */
5203                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5204                                "queue awake!\n", dev->name);
5205                 }
5206                 return NETDEV_TX_BUSY;
5207         }
5208
5209         entry = tnapi->tx_prod;
5210         base_flags = 0;
5211         mss = 0;
5212         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5213                 int tcp_opt_len, ip_tcp_len;
5214
5215                 if (skb_header_cloned(skb) &&
5216                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5217                         dev_kfree_skb(skb);
5218                         goto out_unlock;
5219                 }
5220
5221                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5222                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5223                 else {
5224                         struct iphdr *iph = ip_hdr(skb);
5225
5226                         tcp_opt_len = tcp_optlen(skb);
5227                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5228
5229                         iph->check = 0;
5230                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5231                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
5232                 }
5233
5234                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5235                                TXD_FLAG_CPU_POST_DMA);
5236
5237                 tcp_hdr(skb)->check = 0;
5238
5239         }
5240         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5241                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5242 #if TG3_VLAN_TAG_USED
5243         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5244                 base_flags |= (TXD_FLAG_VLAN |
5245                                (vlan_tx_tag_get(skb) << 16));
5246 #endif
5247
5248         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5249                 dev_kfree_skb(skb);
5250                 goto out_unlock;
5251         }
5252
5253         sp = skb_shinfo(skb);
5254
5255         mapping = sp->dma_head;
5256
5257         tnapi->tx_buffers[entry].skb = skb;
5258
5259         len = skb_headlen(skb);
5260
5261         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5262                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5263
5264         entry = NEXT_TX(entry);
5265
5266         /* Now loop through additional data fragments, and queue them. */
5267         if (skb_shinfo(skb)->nr_frags > 0) {
5268                 unsigned int i, last;
5269
5270                 last = skb_shinfo(skb)->nr_frags - 1;
5271                 for (i = 0; i <= last; i++) {
5272                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5273
5274                         len = frag->size;
5275                         mapping = sp->dma_maps[i];
5276                         tnapi->tx_buffers[entry].skb = NULL;
5277
5278                         tg3_set_txd(tnapi, entry, mapping, len,
5279                                     base_flags, (i == last) | (mss << 1));
5280
5281                         entry = NEXT_TX(entry);
5282                 }
5283         }
5284
5285         /* Packets are ready, update Tx producer idx local and on card. */
5286         tw32_tx_mbox(tnapi->prodmbox, entry);
5287
5288         tnapi->tx_prod = entry;
5289         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5290                 netif_tx_stop_queue(txq);
5291                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5292                         netif_tx_wake_queue(txq);
5293         }
5294
5295 out_unlock:
5296         mmiowb();
5297
5298         return NETDEV_TX_OK;
5299 }
5300
5301 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5302                                           struct net_device *);
5303
5304 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5305  * TSO header is greater than 80 bytes.
5306  */
5307 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5308 {
5309         struct sk_buff *segs, *nskb;
5310         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5311
5312         /* Estimate the number of fragments in the worst case */
5313         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5314                 netif_stop_queue(tp->dev);
5315                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5316                         return NETDEV_TX_BUSY;
5317
5318                 netif_wake_queue(tp->dev);
5319         }
5320
5321         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5322         if (IS_ERR(segs))
5323                 goto tg3_tso_bug_end;
5324
5325         do {
5326                 nskb = segs;
5327                 segs = segs->next;
5328                 nskb->next = NULL;
5329                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5330         } while (segs);
5331
5332 tg3_tso_bug_end:
5333         dev_kfree_skb(skb);
5334
5335         return NETDEV_TX_OK;
5336 }
5337
5338 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5339  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5340  */
5341 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5342                                           struct net_device *dev)
5343 {
5344         struct tg3 *tp = netdev_priv(dev);
5345         u32 len, entry, base_flags, mss;
5346         struct skb_shared_info *sp;
5347         int would_hit_hwbug;
5348         dma_addr_t mapping;
5349         struct tg3_napi *tnapi = &tp->napi[0];
5350
5351         len = skb_headlen(skb);
5352
5353         /* We are running in BH disabled context with netif_tx_lock
5354          * and TX reclaim runs via tp->napi.poll inside of a software
5355          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5356          * no IRQ context deadlocks to worry about either.  Rejoice!
5357          */
5358         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5359                 if (!netif_queue_stopped(dev)) {
5360                         netif_stop_queue(dev);
5361
5362                         /* This is a hard error, log it. */
5363                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5364                                "queue awake!\n", dev->name);
5365                 }
5366                 return NETDEV_TX_BUSY;
5367         }
5368
5369         entry = tnapi->tx_prod;
5370         base_flags = 0;
5371         if (skb->ip_summed == CHECKSUM_PARTIAL)
5372                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5373         mss = 0;
5374         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5375                 struct iphdr *iph;
5376                 int tcp_opt_len, ip_tcp_len, hdr_len;
5377
5378                 if (skb_header_cloned(skb) &&
5379                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5380                         dev_kfree_skb(skb);
5381                         goto out_unlock;
5382                 }
5383
5384                 tcp_opt_len = tcp_optlen(skb);
5385                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5386
5387                 hdr_len = ip_tcp_len + tcp_opt_len;
5388                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5389                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5390                         return (tg3_tso_bug(tp, skb));
5391
5392                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5393                                TXD_FLAG_CPU_POST_DMA);
5394
5395                 iph = ip_hdr(skb);
5396                 iph->check = 0;
5397                 iph->tot_len = htons(mss + hdr_len);
5398                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5399                         tcp_hdr(skb)->check = 0;
5400                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5401                 } else
5402                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5403                                                                  iph->daddr, 0,
5404                                                                  IPPROTO_TCP,
5405                                                                  0);
5406
5407                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5408                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5409                         if (tcp_opt_len || iph->ihl > 5) {
5410                                 int tsflags;
5411
5412                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5413                                 mss |= (tsflags << 11);
5414                         }
5415                 } else {
5416                         if (tcp_opt_len || iph->ihl > 5) {
5417                                 int tsflags;
5418
5419                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5420                                 base_flags |= tsflags << 12;
5421                         }
5422                 }
5423         }
5424 #if TG3_VLAN_TAG_USED
5425         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5426                 base_flags |= (TXD_FLAG_VLAN |
5427                                (vlan_tx_tag_get(skb) << 16));
5428 #endif
5429
5430         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5431                 dev_kfree_skb(skb);
5432                 goto out_unlock;
5433         }
5434
5435         sp = skb_shinfo(skb);
5436
5437         mapping = sp->dma_head;
5438
5439         tnapi->tx_buffers[entry].skb = skb;
5440
5441         would_hit_hwbug = 0;
5442
5443         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5444                 would_hit_hwbug = 1;
5445         else if (tg3_4g_overflow_test(mapping, len))
5446                 would_hit_hwbug = 1;
5447
5448         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5449                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5450
5451         entry = NEXT_TX(entry);
5452
5453         /* Now loop through additional data fragments, and queue them. */
5454         if (skb_shinfo(skb)->nr_frags > 0) {
5455                 unsigned int i, last;
5456
5457                 last = skb_shinfo(skb)->nr_frags - 1;
5458                 for (i = 0; i <= last; i++) {
5459                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5460
5461                         len = frag->size;
5462                         mapping = sp->dma_maps[i];
5463
5464                         tnapi->tx_buffers[entry].skb = NULL;
5465
5466                         if (tg3_4g_overflow_test(mapping, len))
5467                                 would_hit_hwbug = 1;
5468
5469                         if (tg3_40bit_overflow_test(tp, mapping, len))
5470                                 would_hit_hwbug = 1;
5471
5472                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5473                                 tg3_set_txd(tnapi, entry, mapping, len,
5474                                             base_flags, (i == last)|(mss << 1));
5475                         else
5476                                 tg3_set_txd(tnapi, entry, mapping, len,
5477                                             base_flags, (i == last));
5478
5479                         entry = NEXT_TX(entry);
5480                 }
5481         }
5482
5483         if (would_hit_hwbug) {
5484                 u32 last_plus_one = entry;
5485                 u32 start;
5486
5487                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5488                 start &= (TG3_TX_RING_SIZE - 1);
5489
5490                 /* If the workaround fails due to memory/mapping
5491                  * failure, silently drop this packet.
5492                  */
5493                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5494                                                 &start, base_flags, mss))
5495                         goto out_unlock;
5496
5497                 entry = start;
5498         }
5499
5500         /* Packets are ready, update Tx producer idx local and on card. */
5501         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5502
5503         tnapi->tx_prod = entry;
5504         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5505                 netif_stop_queue(dev);
5506                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5507                         netif_wake_queue(tp->dev);
5508         }
5509
5510 out_unlock:
5511         mmiowb();
5512
5513         return NETDEV_TX_OK;
5514 }
5515
5516 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5517                                int new_mtu)
5518 {
5519         dev->mtu = new_mtu;
5520
5521         if (new_mtu > ETH_DATA_LEN) {
5522                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5523                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5524                         ethtool_op_set_tso(dev, 0);
5525                 }
5526                 else
5527                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5528         } else {
5529                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5530                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5531                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5532         }
5533 }
5534
5535 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5536 {
5537         struct tg3 *tp = netdev_priv(dev);
5538         int err;
5539
5540         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5541                 return -EINVAL;
5542
5543         if (!netif_running(dev)) {
5544                 /* We'll just catch it later when the
5545                  * device is up'd.
5546                  */
5547                 tg3_set_mtu(dev, tp, new_mtu);
5548                 return 0;
5549         }
5550
5551         tg3_phy_stop(tp);
5552
5553         tg3_netif_stop(tp);
5554
5555         tg3_full_lock(tp, 1);
5556
5557         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5558
5559         tg3_set_mtu(dev, tp, new_mtu);
5560
5561         err = tg3_restart_hw(tp, 0);
5562
5563         if (!err)
5564                 tg3_netif_start(tp);
5565
5566         tg3_full_unlock(tp);
5567
5568         if (!err)
5569                 tg3_phy_start(tp);
5570
5571         return err;
5572 }
5573
5574 static void tg3_rx_prodring_free(struct tg3 *tp,
5575                                  struct tg3_rx_prodring_set *tpr)
5576 {
5577         int i;
5578         struct ring_info *rxp;
5579
5580         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5581                 rxp = &tpr->rx_std_buffers[i];
5582
5583                 if (rxp->skb == NULL)
5584                         continue;
5585
5586                 pci_unmap_single(tp->pdev,
5587                                  pci_unmap_addr(rxp, mapping),
5588                                  tp->rx_pkt_map_sz,
5589                                  PCI_DMA_FROMDEVICE);
5590                 dev_kfree_skb_any(rxp->skb);
5591                 rxp->skb = NULL;
5592         }
5593
5594         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5595                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5596                         rxp = &tpr->rx_jmb_buffers[i];
5597
5598                         if (rxp->skb == NULL)
5599                                 continue;
5600
5601                         pci_unmap_single(tp->pdev,
5602                                          pci_unmap_addr(rxp, mapping),
5603                                          TG3_RX_JMB_MAP_SZ,
5604                                          PCI_DMA_FROMDEVICE);
5605                         dev_kfree_skb_any(rxp->skb);
5606                         rxp->skb = NULL;
5607                 }
5608         }
5609 }
5610
5611 /* Initialize tx/rx rings for packet processing.
5612  *
5613  * The chip has been shut down and the driver detached from
5614  * the networking, so no interrupts or new tx packets will
5615  * end up in the driver.  tp->{tx,}lock are held and thus
5616  * we may not sleep.
5617  */
5618 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5619                                  struct tg3_rx_prodring_set *tpr)
5620 {
5621         u32 i, rx_pkt_dma_sz;
5622         struct tg3_napi *tnapi = &tp->napi[0];
5623
5624         /* Zero out all descriptors. */
5625         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5626
5627         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5628         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5629             tp->dev->mtu > ETH_DATA_LEN)
5630                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5631         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5632
5633         /* Initialize invariants of the rings, we only set this
5634          * stuff once.  This works because the card does not
5635          * write into the rx buffer posting rings.
5636          */
5637         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5638                 struct tg3_rx_buffer_desc *rxd;
5639
5640                 rxd = &tpr->rx_std[i];
5641                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5642                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5643                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5644                                (i << RXD_OPAQUE_INDEX_SHIFT));
5645         }
5646
5647         /* Now allocate fresh SKBs for each rx ring. */
5648         for (i = 0; i < tp->rx_pending; i++) {
5649                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5650                         printk(KERN_WARNING PFX
5651                                "%s: Using a smaller RX standard ring, "
5652                                "only %d out of %d buffers were allocated "
5653                                "successfully.\n",
5654                                tp->dev->name, i, tp->rx_pending);
5655                         if (i == 0)
5656                                 goto initfail;
5657                         tp->rx_pending = i;
5658                         break;
5659                 }
5660         }
5661
5662         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5663                 goto done;
5664
5665         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5666
5667         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5668                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5669                         struct tg3_rx_buffer_desc *rxd;
5670
5671                         rxd = &tpr->rx_jmb[i].std;
5672                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5673                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5674                                 RXD_FLAG_JUMBO;
5675                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5676                                (i << RXD_OPAQUE_INDEX_SHIFT));
5677                 }
5678
5679                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5680                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5681                                              -1, i) < 0) {
5682                                 printk(KERN_WARNING PFX
5683                                        "%s: Using a smaller RX jumbo ring, "
5684                                        "only %d out of %d buffers were "
5685                                        "allocated successfully.\n",
5686                                        tp->dev->name, i, tp->rx_jumbo_pending);
5687                                 if (i == 0)
5688                                         goto initfail;
5689                                 tp->rx_jumbo_pending = i;
5690                                 break;
5691                         }
5692                 }
5693         }
5694
5695 done:
5696         return 0;
5697
5698 initfail:
5699         tg3_rx_prodring_free(tp, tpr);
5700         return -ENOMEM;
5701 }
5702
5703 static void tg3_rx_prodring_fini(struct tg3 *tp,
5704                                  struct tg3_rx_prodring_set *tpr)
5705 {
5706         kfree(tpr->rx_std_buffers);
5707         tpr->rx_std_buffers = NULL;
5708         kfree(tpr->rx_jmb_buffers);
5709         tpr->rx_jmb_buffers = NULL;
5710         if (tpr->rx_std) {
5711                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5712                                     tpr->rx_std, tpr->rx_std_mapping);
5713                 tpr->rx_std = NULL;
5714         }
5715         if (tpr->rx_jmb) {
5716                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5717                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5718                 tpr->rx_jmb = NULL;
5719         }
5720 }
5721
5722 static int tg3_rx_prodring_init(struct tg3 *tp,
5723                                 struct tg3_rx_prodring_set *tpr)
5724 {
5725         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5726                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5727         if (!tpr->rx_std_buffers)
5728                 return -ENOMEM;
5729
5730         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5731                                            &tpr->rx_std_mapping);
5732         if (!tpr->rx_std)
5733                 goto err_out;
5734
5735         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5736                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5737                                               TG3_RX_JUMBO_RING_SIZE,
5738                                               GFP_KERNEL);
5739                 if (!tpr->rx_jmb_buffers)
5740                         goto err_out;
5741
5742                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5743                                                    TG3_RX_JUMBO_RING_BYTES,
5744                                                    &tpr->rx_jmb_mapping);
5745                 if (!tpr->rx_jmb)
5746                         goto err_out;
5747         }
5748
5749         return 0;
5750
5751 err_out:
5752         tg3_rx_prodring_fini(tp, tpr);
5753         return -ENOMEM;
5754 }
5755
5756 /* Free up pending packets in all rx/tx rings.
5757  *
5758  * The chip has been shut down and the driver detached from
5759  * the networking, so no interrupts or new tx packets will
5760  * end up in the driver.  tp->{tx,}lock is not held and we are not
5761  * in an interrupt context and thus may sleep.
5762  */
5763 static void tg3_free_rings(struct tg3 *tp)
5764 {
5765         int i, j;
5766
5767         for (j = 0; j < tp->irq_cnt; j++) {
5768                 struct tg3_napi *tnapi = &tp->napi[j];
5769
5770                 if (!tnapi->tx_buffers)
5771                         continue;
5772
5773                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5774                         struct tx_ring_info *txp;
5775                         struct sk_buff *skb;
5776
5777                         txp = &tnapi->tx_buffers[i];
5778                         skb = txp->skb;
5779
5780                         if (skb == NULL) {
5781                                 i++;
5782                                 continue;
5783                         }
5784
5785                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5786
5787                         txp->skb = NULL;
5788
5789                         i += skb_shinfo(skb)->nr_frags + 1;
5790
5791                         dev_kfree_skb_any(skb);
5792                 }
5793         }
5794
5795         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5796 }
5797
5798 /* Initialize tx/rx rings for packet processing.
5799  *
5800  * The chip has been shut down and the driver detached from
5801  * the networking, so no interrupts or new tx packets will
5802  * end up in the driver.  tp->{tx,}lock are held and thus
5803  * we may not sleep.
5804  */
5805 static int tg3_init_rings(struct tg3 *tp)
5806 {
5807         int i;
5808
5809         /* Free up all the SKBs. */
5810         tg3_free_rings(tp);
5811
5812         for (i = 0; i < tp->irq_cnt; i++) {
5813                 struct tg3_napi *tnapi = &tp->napi[i];
5814
5815                 tnapi->last_tag = 0;
5816                 tnapi->last_irq_tag = 0;
5817                 tnapi->hw_status->status = 0;
5818                 tnapi->hw_status->status_tag = 0;
5819                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5820
5821                 tnapi->tx_prod = 0;
5822                 tnapi->tx_cons = 0;
5823                 if (tnapi->tx_ring)
5824                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5825
5826                 tnapi->rx_rcb_ptr = 0;
5827                 if (tnapi->rx_rcb)
5828                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5829         }
5830
5831         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5832 }
5833
5834 /*
5835  * Must not be invoked with interrupt sources disabled and
5836  * the hardware shutdown down.
5837  */
5838 static void tg3_free_consistent(struct tg3 *tp)
5839 {
5840         int i;
5841
5842         for (i = 0; i < tp->irq_cnt; i++) {
5843                 struct tg3_napi *tnapi = &tp->napi[i];
5844
5845                 if (tnapi->tx_ring) {
5846                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5847                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5848                         tnapi->tx_ring = NULL;
5849                 }
5850
5851                 kfree(tnapi->tx_buffers);
5852                 tnapi->tx_buffers = NULL;
5853
5854                 if (tnapi->rx_rcb) {
5855                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5856                                             tnapi->rx_rcb,
5857                                             tnapi->rx_rcb_mapping);
5858                         tnapi->rx_rcb = NULL;
5859                 }
5860
5861                 if (tnapi->hw_status) {
5862                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5863                                             tnapi->hw_status,
5864                                             tnapi->status_mapping);
5865                         tnapi->hw_status = NULL;
5866                 }
5867         }
5868
5869         if (tp->hw_stats) {
5870                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5871                                     tp->hw_stats, tp->stats_mapping);
5872                 tp->hw_stats = NULL;
5873         }
5874
5875         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5876 }
5877
5878 /*
5879  * Must not be invoked with interrupt sources disabled and
5880  * the hardware shutdown down.  Can sleep.
5881  */
5882 static int tg3_alloc_consistent(struct tg3 *tp)
5883 {
5884         int i;
5885
5886         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5887                 return -ENOMEM;
5888
5889         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5890                                             sizeof(struct tg3_hw_stats),
5891                                             &tp->stats_mapping);
5892         if (!tp->hw_stats)
5893                 goto err_out;
5894
5895         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5896
5897         for (i = 0; i < tp->irq_cnt; i++) {
5898                 struct tg3_napi *tnapi = &tp->napi[i];
5899
5900                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5901                                                         TG3_HW_STATUS_SIZE,
5902                                                         &tnapi->status_mapping);
5903                 if (!tnapi->hw_status)
5904                         goto err_out;
5905
5906                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5907
5908                 /*
5909                  * If multivector RSS is enabled, vector 0 does not handle
5910                  * rx or tx interrupts.  Don't allocate any resources for it.
5911                  */
5912                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5913                         continue;
5914
5915                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5916                                                      TG3_RX_RCB_RING_BYTES(tp),
5917                                                      &tnapi->rx_rcb_mapping);
5918                 if (!tnapi->rx_rcb)
5919                         goto err_out;
5920
5921                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5922
5923                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5924                                             TG3_TX_RING_SIZE, GFP_KERNEL);
5925                 if (!tnapi->tx_buffers)
5926                         goto err_out;
5927
5928                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
5929                                                       TG3_TX_RING_BYTES,
5930                                                       &tnapi->tx_desc_mapping);
5931                 if (!tnapi->tx_ring)
5932                         goto err_out;
5933         }
5934
5935         return 0;
5936
5937 err_out:
5938         tg3_free_consistent(tp);
5939         return -ENOMEM;
5940 }
5941
5942 #define MAX_WAIT_CNT 1000
5943
5944 /* To stop a block, clear the enable bit and poll till it
5945  * clears.  tp->lock is held.
5946  */
5947 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5948 {
5949         unsigned int i;
5950         u32 val;
5951
5952         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5953                 switch (ofs) {
5954                 case RCVLSC_MODE:
5955                 case DMAC_MODE:
5956                 case MBFREE_MODE:
5957                 case BUFMGR_MODE:
5958                 case MEMARB_MODE:
5959                         /* We can't enable/disable these bits of the
5960                          * 5705/5750, just say success.
5961                          */
5962                         return 0;
5963
5964                 default:
5965                         break;
5966                 }
5967         }
5968
5969         val = tr32(ofs);
5970         val &= ~enable_bit;
5971         tw32_f(ofs, val);
5972
5973         for (i = 0; i < MAX_WAIT_CNT; i++) {
5974                 udelay(100);
5975                 val = tr32(ofs);
5976                 if ((val & enable_bit) == 0)
5977                         break;
5978         }
5979
5980         if (i == MAX_WAIT_CNT && !silent) {
5981                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5982                        "ofs=%lx enable_bit=%x\n",
5983                        ofs, enable_bit);
5984                 return -ENODEV;
5985         }
5986
5987         return 0;
5988 }
5989
5990 /* tp->lock is held. */
5991 static int tg3_abort_hw(struct tg3 *tp, int silent)
5992 {
5993         int i, err;
5994
5995         tg3_disable_ints(tp);
5996
5997         tp->rx_mode &= ~RX_MODE_ENABLE;
5998         tw32_f(MAC_RX_MODE, tp->rx_mode);
5999         udelay(10);
6000
6001         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6002         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6003         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6004         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6005         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6006         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6007
6008         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6009         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6010         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6011         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6012         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6013         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6014         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6015
6016         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6017         tw32_f(MAC_MODE, tp->mac_mode);
6018         udelay(40);
6019
6020         tp->tx_mode &= ~TX_MODE_ENABLE;
6021         tw32_f(MAC_TX_MODE, tp->tx_mode);
6022
6023         for (i = 0; i < MAX_WAIT_CNT; i++) {
6024                 udelay(100);
6025                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6026                         break;
6027         }
6028         if (i >= MAX_WAIT_CNT) {
6029                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6030                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6031                        tp->dev->name, tr32(MAC_TX_MODE));
6032                 err |= -ENODEV;
6033         }
6034
6035         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6036         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6037         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6038
6039         tw32(FTQ_RESET, 0xffffffff);
6040         tw32(FTQ_RESET, 0x00000000);
6041
6042         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6043         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6044
6045         for (i = 0; i < tp->irq_cnt; i++) {
6046                 struct tg3_napi *tnapi = &tp->napi[i];
6047                 if (tnapi->hw_status)
6048                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6049         }
6050         if (tp->hw_stats)
6051                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6052
6053         return err;
6054 }
6055
6056 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6057 {
6058         int i;
6059         u32 apedata;
6060
6061         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6062         if (apedata != APE_SEG_SIG_MAGIC)
6063                 return;
6064
6065         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6066         if (!(apedata & APE_FW_STATUS_READY))
6067                 return;
6068
6069         /* Wait for up to 1 millisecond for APE to service previous event. */
6070         for (i = 0; i < 10; i++) {
6071                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6072                         return;
6073
6074                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6075
6076                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6077                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6078                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6079
6080                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6081
6082                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6083                         break;
6084
6085                 udelay(100);
6086         }
6087
6088         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6089                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6090 }
6091
6092 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6093 {
6094         u32 event;
6095         u32 apedata;
6096
6097         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6098                 return;
6099
6100         switch (kind) {
6101                 case RESET_KIND_INIT:
6102                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6103                                         APE_HOST_SEG_SIG_MAGIC);
6104                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6105                                         APE_HOST_SEG_LEN_MAGIC);
6106                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6107                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6108                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6109                                         APE_HOST_DRIVER_ID_MAGIC);
6110                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6111                                         APE_HOST_BEHAV_NO_PHYLOCK);
6112
6113                         event = APE_EVENT_STATUS_STATE_START;
6114                         break;
6115                 case RESET_KIND_SHUTDOWN:
6116                         /* With the interface we are currently using,
6117                          * APE does not track driver state.  Wiping
6118                          * out the HOST SEGMENT SIGNATURE forces
6119                          * the APE to assume OS absent status.
6120                          */
6121                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6122
6123                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6124                         break;
6125                 case RESET_KIND_SUSPEND:
6126                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6127                         break;
6128                 default:
6129                         return;
6130         }
6131
6132         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6133
6134         tg3_ape_send_event(tp, event);
6135 }
6136
6137 /* tp->lock is held. */
6138 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6139 {
6140         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6141                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6142
6143         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6144                 switch (kind) {
6145                 case RESET_KIND_INIT:
6146                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6147                                       DRV_STATE_START);
6148                         break;
6149
6150                 case RESET_KIND_SHUTDOWN:
6151                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6152                                       DRV_STATE_UNLOAD);
6153                         break;
6154
6155                 case RESET_KIND_SUSPEND:
6156                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6157                                       DRV_STATE_SUSPEND);
6158                         break;
6159
6160                 default:
6161                         break;
6162                 }
6163         }
6164
6165         if (kind == RESET_KIND_INIT ||
6166             kind == RESET_KIND_SUSPEND)
6167                 tg3_ape_driver_state_change(tp, kind);
6168 }
6169
6170 /* tp->lock is held. */
6171 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6172 {
6173         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6174                 switch (kind) {
6175                 case RESET_KIND_INIT:
6176                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6177                                       DRV_STATE_START_DONE);
6178                         break;
6179
6180                 case RESET_KIND_SHUTDOWN:
6181                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6182                                       DRV_STATE_UNLOAD_DONE);
6183                         break;
6184
6185                 default:
6186                         break;
6187                 }
6188         }
6189
6190         if (kind == RESET_KIND_SHUTDOWN)
6191                 tg3_ape_driver_state_change(tp, kind);
6192 }
6193
6194 /* tp->lock is held. */
6195 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6196 {
6197         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6198                 switch (kind) {
6199                 case RESET_KIND_INIT:
6200                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6201                                       DRV_STATE_START);
6202                         break;
6203
6204                 case RESET_KIND_SHUTDOWN:
6205                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6206                                       DRV_STATE_UNLOAD);
6207                         break;
6208
6209                 case RESET_KIND_SUSPEND:
6210                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6211                                       DRV_STATE_SUSPEND);
6212                         break;
6213
6214                 default:
6215                         break;
6216                 }
6217         }
6218 }
6219
6220 static int tg3_poll_fw(struct tg3 *tp)
6221 {
6222         int i;
6223         u32 val;
6224
6225         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6226                 /* Wait up to 20ms for init done. */
6227                 for (i = 0; i < 200; i++) {
6228                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6229                                 return 0;
6230                         udelay(100);
6231                 }
6232                 return -ENODEV;
6233         }
6234
6235         /* Wait for firmware initialization to complete. */
6236         for (i = 0; i < 100000; i++) {
6237                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6238                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6239                         break;
6240                 udelay(10);
6241         }
6242
6243         /* Chip might not be fitted with firmware.  Some Sun onboard
6244          * parts are configured like that.  So don't signal the timeout
6245          * of the above loop as an error, but do report the lack of
6246          * running firmware once.
6247          */
6248         if (i >= 100000 &&
6249             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6250                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6251
6252                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6253                        tp->dev->name);
6254         }
6255
6256         return 0;
6257 }
6258
6259 /* Save PCI command register before chip reset */
6260 static void tg3_save_pci_state(struct tg3 *tp)
6261 {
6262         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6263 }
6264
6265 /* Restore PCI state after chip reset */
6266 static void tg3_restore_pci_state(struct tg3 *tp)
6267 {
6268         u32 val;
6269
6270         /* Re-enable indirect register accesses. */
6271         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6272                                tp->misc_host_ctrl);
6273
6274         /* Set MAX PCI retry to zero. */
6275         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6276         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6277             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6278                 val |= PCISTATE_RETRY_SAME_DMA;
6279         /* Allow reads and writes to the APE register and memory space. */
6280         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6281                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6282                        PCISTATE_ALLOW_APE_SHMEM_WR;
6283         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6284
6285         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6286
6287         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6288                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6289                         pcie_set_readrq(tp->pdev, 4096);
6290                 else {
6291                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6292                                               tp->pci_cacheline_sz);
6293                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6294                                               tp->pci_lat_timer);
6295                 }
6296         }
6297
6298         /* Make sure PCI-X relaxed ordering bit is clear. */
6299         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6300                 u16 pcix_cmd;
6301
6302                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6303                                      &pcix_cmd);
6304                 pcix_cmd &= ~PCI_X_CMD_ERO;
6305                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6306                                       pcix_cmd);
6307         }
6308
6309         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6310
6311                 /* Chip reset on 5780 will reset MSI enable bit,
6312                  * so need to restore it.
6313                  */
6314                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6315                         u16 ctrl;
6316
6317                         pci_read_config_word(tp->pdev,
6318                                              tp->msi_cap + PCI_MSI_FLAGS,
6319                                              &ctrl);
6320                         pci_write_config_word(tp->pdev,
6321                                               tp->msi_cap + PCI_MSI_FLAGS,
6322                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6323                         val = tr32(MSGINT_MODE);
6324                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6325                 }
6326         }
6327 }
6328
6329 static void tg3_stop_fw(struct tg3 *);
6330
6331 /* tp->lock is held. */
6332 static int tg3_chip_reset(struct tg3 *tp)
6333 {
6334         u32 val;
6335         void (*write_op)(struct tg3 *, u32, u32);
6336         int i, err;
6337
6338         tg3_nvram_lock(tp);
6339
6340         tg3_mdio_stop(tp);
6341
6342         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6343
6344         /* No matching tg3_nvram_unlock() after this because
6345          * chip reset below will undo the nvram lock.
6346          */
6347         tp->nvram_lock_cnt = 0;
6348
6349         /* GRC_MISC_CFG core clock reset will clear the memory
6350          * enable bit in PCI register 4 and the MSI enable bit
6351          * on some chips, so we save relevant registers here.
6352          */
6353         tg3_save_pci_state(tp);
6354
6355         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6356             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6357                 tw32(GRC_FASTBOOT_PC, 0);
6358
6359         /*
6360          * We must avoid the readl() that normally takes place.
6361          * It locks machines, causes machine checks, and other
6362          * fun things.  So, temporarily disable the 5701
6363          * hardware workaround, while we do the reset.
6364          */
6365         write_op = tp->write32;
6366         if (write_op == tg3_write_flush_reg32)
6367                 tp->write32 = tg3_write32;
6368
6369         /* Prevent the irq handler from reading or writing PCI registers
6370          * during chip reset when the memory enable bit in the PCI command
6371          * register may be cleared.  The chip does not generate interrupt
6372          * at this time, but the irq handler may still be called due to irq
6373          * sharing or irqpoll.
6374          */
6375         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6376         for (i = 0; i < tp->irq_cnt; i++) {
6377                 struct tg3_napi *tnapi = &tp->napi[i];
6378                 if (tnapi->hw_status) {
6379                         tnapi->hw_status->status = 0;
6380                         tnapi->hw_status->status_tag = 0;
6381                 }
6382                 tnapi->last_tag = 0;
6383                 tnapi->last_irq_tag = 0;
6384         }
6385         smp_mb();
6386
6387         for (i = 0; i < tp->irq_cnt; i++)
6388                 synchronize_irq(tp->napi[i].irq_vec);
6389
6390         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6391                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6392                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6393         }
6394
6395         /* do the reset */
6396         val = GRC_MISC_CFG_CORECLK_RESET;
6397
6398         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6399                 if (tr32(0x7e2c) == 0x60) {
6400                         tw32(0x7e2c, 0x20);
6401                 }
6402                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6403                         tw32(GRC_MISC_CFG, (1 << 29));
6404                         val |= (1 << 29);
6405                 }
6406         }
6407
6408         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6409                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6410                 tw32(GRC_VCPU_EXT_CTRL,
6411                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6412         }
6413
6414         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6415                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6416         tw32(GRC_MISC_CFG, val);
6417
6418         /* restore 5701 hardware bug workaround write method */
6419         tp->write32 = write_op;
6420
6421         /* Unfortunately, we have to delay before the PCI read back.
6422          * Some 575X chips even will not respond to a PCI cfg access
6423          * when the reset command is given to the chip.
6424          *
6425          * How do these hardware designers expect things to work
6426          * properly if the PCI write is posted for a long period
6427          * of time?  It is always necessary to have some method by
6428          * which a register read back can occur to push the write
6429          * out which does the reset.
6430          *
6431          * For most tg3 variants the trick below was working.
6432          * Ho hum...
6433          */
6434         udelay(120);
6435
6436         /* Flush PCI posted writes.  The normal MMIO registers
6437          * are inaccessible at this time so this is the only
6438          * way to make this reliably (actually, this is no longer
6439          * the case, see above).  I tried to use indirect
6440          * register read/write but this upset some 5701 variants.
6441          */
6442         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6443
6444         udelay(120);
6445
6446         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6447                 u16 val16;
6448
6449                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6450                         int i;
6451                         u32 cfg_val;
6452
6453                         /* Wait for link training to complete.  */
6454                         for (i = 0; i < 5000; i++)
6455                                 udelay(100);
6456
6457                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6458                         pci_write_config_dword(tp->pdev, 0xc4,
6459                                                cfg_val | (1 << 15));
6460                 }
6461
6462                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6463                 pci_read_config_word(tp->pdev,
6464                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6465                                      &val16);
6466                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6467                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6468                 /*
6469                  * Older PCIe devices only support the 128 byte
6470                  * MPS setting.  Enforce the restriction.
6471                  */
6472                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6473                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6474                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6475                 pci_write_config_word(tp->pdev,
6476                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6477                                       val16);
6478
6479                 pcie_set_readrq(tp->pdev, 4096);
6480
6481                 /* Clear error status */
6482                 pci_write_config_word(tp->pdev,
6483                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6484                                       PCI_EXP_DEVSTA_CED |
6485                                       PCI_EXP_DEVSTA_NFED |
6486                                       PCI_EXP_DEVSTA_FED |
6487                                       PCI_EXP_DEVSTA_URD);
6488         }
6489
6490         tg3_restore_pci_state(tp);
6491
6492         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6493
6494         val = 0;
6495         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6496                 val = tr32(MEMARB_MODE);
6497         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6498
6499         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6500                 tg3_stop_fw(tp);
6501                 tw32(0x5000, 0x400);
6502         }
6503
6504         tw32(GRC_MODE, tp->grc_mode);
6505
6506         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6507                 val = tr32(0xc4);
6508
6509                 tw32(0xc4, val | (1 << 15));
6510         }
6511
6512         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6513             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6514                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6515                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6516                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6517                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6518         }
6519
6520         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6521                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6522                 tw32_f(MAC_MODE, tp->mac_mode);
6523         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6524                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6525                 tw32_f(MAC_MODE, tp->mac_mode);
6526         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6527                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6528                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6529                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6530                 tw32_f(MAC_MODE, tp->mac_mode);
6531         } else
6532                 tw32_f(MAC_MODE, 0);
6533         udelay(40);
6534
6535         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6536
6537         err = tg3_poll_fw(tp);
6538         if (err)
6539                 return err;
6540
6541         tg3_mdio_start(tp);
6542
6543         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6544             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6545                 val = tr32(0x7c00);
6546
6547                 tw32(0x7c00, val | (1 << 25));
6548         }
6549
6550         /* Reprobe ASF enable state.  */
6551         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6552         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6553         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6554         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6555                 u32 nic_cfg;
6556
6557                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6558                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6559                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6560                         tp->last_event_jiffies = jiffies;
6561                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6562                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6563                 }
6564         }
6565
6566         return 0;
6567 }
6568
6569 /* tp->lock is held. */
6570 static void tg3_stop_fw(struct tg3 *tp)
6571 {
6572         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6573            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6574                 /* Wait for RX cpu to ACK the previous event. */
6575                 tg3_wait_for_event_ack(tp);
6576
6577                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6578
6579                 tg3_generate_fw_event(tp);
6580
6581                 /* Wait for RX cpu to ACK this event. */
6582                 tg3_wait_for_event_ack(tp);
6583         }
6584 }
6585
6586 /* tp->lock is held. */
6587 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6588 {
6589         int err;
6590
6591         tg3_stop_fw(tp);
6592
6593         tg3_write_sig_pre_reset(tp, kind);
6594
6595         tg3_abort_hw(tp, silent);
6596         err = tg3_chip_reset(tp);
6597
6598         __tg3_set_mac_addr(tp, 0);
6599
6600         tg3_write_sig_legacy(tp, kind);
6601         tg3_write_sig_post_reset(tp, kind);
6602
6603         if (err)
6604                 return err;
6605
6606         return 0;
6607 }
6608
6609 #define RX_CPU_SCRATCH_BASE     0x30000
6610 #define RX_CPU_SCRATCH_SIZE     0x04000
6611 #define TX_CPU_SCRATCH_BASE     0x34000
6612 #define TX_CPU_SCRATCH_SIZE     0x04000
6613
6614 /* tp->lock is held. */
6615 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6616 {
6617         int i;
6618
6619         BUG_ON(offset == TX_CPU_BASE &&
6620             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6621
6622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6623                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6624
6625                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6626                 return 0;
6627         }
6628         if (offset == RX_CPU_BASE) {
6629                 for (i = 0; i < 10000; i++) {
6630                         tw32(offset + CPU_STATE, 0xffffffff);
6631                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6632                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6633                                 break;
6634                 }
6635
6636                 tw32(offset + CPU_STATE, 0xffffffff);
6637                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6638                 udelay(10);
6639         } else {
6640                 for (i = 0; i < 10000; i++) {
6641                         tw32(offset + CPU_STATE, 0xffffffff);
6642                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6643                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6644                                 break;
6645                 }
6646         }
6647
6648         if (i >= 10000) {
6649                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6650                        "and %s CPU\n",
6651                        tp->dev->name,
6652                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6653                 return -ENODEV;
6654         }
6655
6656         /* Clear firmware's nvram arbitration. */
6657         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6658                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6659         return 0;
6660 }
6661
6662 struct fw_info {
6663         unsigned int fw_base;
6664         unsigned int fw_len;
6665         const __be32 *fw_data;
6666 };
6667
6668 /* tp->lock is held. */
6669 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6670                                  int cpu_scratch_size, struct fw_info *info)
6671 {
6672         int err, lock_err, i;
6673         void (*write_op)(struct tg3 *, u32, u32);
6674
6675         if (cpu_base == TX_CPU_BASE &&
6676             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6677                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6678                        "TX cpu firmware on %s which is 5705.\n",
6679                        tp->dev->name);
6680                 return -EINVAL;
6681         }
6682
6683         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6684                 write_op = tg3_write_mem;
6685         else
6686                 write_op = tg3_write_indirect_reg32;
6687
6688         /* It is possible that bootcode is still loading at this point.
6689          * Get the nvram lock first before halting the cpu.
6690          */
6691         lock_err = tg3_nvram_lock(tp);
6692         err = tg3_halt_cpu(tp, cpu_base);
6693         if (!lock_err)
6694                 tg3_nvram_unlock(tp);
6695         if (err)
6696                 goto out;
6697
6698         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6699                 write_op(tp, cpu_scratch_base + i, 0);
6700         tw32(cpu_base + CPU_STATE, 0xffffffff);
6701         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6702         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6703                 write_op(tp, (cpu_scratch_base +
6704                               (info->fw_base & 0xffff) +
6705                               (i * sizeof(u32))),
6706                               be32_to_cpu(info->fw_data[i]));
6707
6708         err = 0;
6709
6710 out:
6711         return err;
6712 }
6713
6714 /* tp->lock is held. */
6715 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6716 {
6717         struct fw_info info;
6718         const __be32 *fw_data;
6719         int err, i;
6720
6721         fw_data = (void *)tp->fw->data;
6722
6723         /* Firmware blob starts with version numbers, followed by
6724            start address and length. We are setting complete length.
6725            length = end_address_of_bss - start_address_of_text.
6726            Remainder is the blob to be loaded contiguously
6727            from start address. */
6728
6729         info.fw_base = be32_to_cpu(fw_data[1]);
6730         info.fw_len = tp->fw->size - 12;
6731         info.fw_data = &fw_data[3];
6732
6733         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6734                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6735                                     &info);
6736         if (err)
6737                 return err;
6738
6739         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6740                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6741                                     &info);
6742         if (err)
6743                 return err;
6744
6745         /* Now startup only the RX cpu. */
6746         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6747         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6748
6749         for (i = 0; i < 5; i++) {
6750                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6751                         break;
6752                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6753                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6754                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6755                 udelay(1000);
6756         }
6757         if (i >= 5) {
6758                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6759                        "to set RX CPU PC, is %08x should be %08x\n",
6760                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6761                        info.fw_base);
6762                 return -ENODEV;
6763         }
6764         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6765         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6766
6767         return 0;
6768 }
6769
6770 /* 5705 needs a special version of the TSO firmware.  */
6771
6772 /* tp->lock is held. */
6773 static int tg3_load_tso_firmware(struct tg3 *tp)
6774 {
6775         struct fw_info info;
6776         const __be32 *fw_data;
6777         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6778         int err, i;
6779
6780         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6781                 return 0;
6782
6783         fw_data = (void *)tp->fw->data;
6784
6785         /* Firmware blob starts with version numbers, followed by
6786            start address and length. We are setting complete length.
6787            length = end_address_of_bss - start_address_of_text.
6788            Remainder is the blob to be loaded contiguously
6789            from start address. */
6790
6791         info.fw_base = be32_to_cpu(fw_data[1]);
6792         cpu_scratch_size = tp->fw_len;
6793         info.fw_len = tp->fw->size - 12;
6794         info.fw_data = &fw_data[3];
6795
6796         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6797                 cpu_base = RX_CPU_BASE;
6798                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6799         } else {
6800                 cpu_base = TX_CPU_BASE;
6801                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6802                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6803         }
6804
6805         err = tg3_load_firmware_cpu(tp, cpu_base,
6806                                     cpu_scratch_base, cpu_scratch_size,
6807                                     &info);
6808         if (err)
6809                 return err;
6810
6811         /* Now startup the cpu. */
6812         tw32(cpu_base + CPU_STATE, 0xffffffff);
6813         tw32_f(cpu_base + CPU_PC, info.fw_base);
6814
6815         for (i = 0; i < 5; i++) {
6816                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6817                         break;
6818                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6819                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6820                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6821                 udelay(1000);
6822         }
6823         if (i >= 5) {
6824                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6825                        "to set CPU PC, is %08x should be %08x\n",
6826                        tp->dev->name, tr32(cpu_base + CPU_PC),
6827                        info.fw_base);
6828                 return -ENODEV;
6829         }
6830         tw32(cpu_base + CPU_STATE, 0xffffffff);
6831         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6832         return 0;
6833 }
6834
6835
6836 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6837 {
6838         struct tg3 *tp = netdev_priv(dev);
6839         struct sockaddr *addr = p;
6840         int err = 0, skip_mac_1 = 0;
6841
6842         if (!is_valid_ether_addr(addr->sa_data))
6843                 return -EINVAL;
6844
6845         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6846
6847         if (!netif_running(dev))
6848                 return 0;
6849
6850         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6851                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6852
6853                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6854                 addr0_low = tr32(MAC_ADDR_0_LOW);
6855                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6856                 addr1_low = tr32(MAC_ADDR_1_LOW);
6857
6858                 /* Skip MAC addr 1 if ASF is using it. */
6859                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6860                     !(addr1_high == 0 && addr1_low == 0))
6861                         skip_mac_1 = 1;
6862         }
6863         spin_lock_bh(&tp->lock);
6864         __tg3_set_mac_addr(tp, skip_mac_1);
6865         spin_unlock_bh(&tp->lock);
6866
6867         return err;
6868 }
6869
6870 /* tp->lock is held. */
6871 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6872                            dma_addr_t mapping, u32 maxlen_flags,
6873                            u32 nic_addr)
6874 {
6875         tg3_write_mem(tp,
6876                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6877                       ((u64) mapping >> 32));
6878         tg3_write_mem(tp,
6879                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6880                       ((u64) mapping & 0xffffffff));
6881         tg3_write_mem(tp,
6882                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6883                        maxlen_flags);
6884
6885         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6886                 tg3_write_mem(tp,
6887                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6888                               nic_addr);
6889 }
6890
6891 static void __tg3_set_rx_mode(struct net_device *);
6892 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6893 {
6894         int i;
6895
6896         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
6897                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6898                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6899                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6900
6901                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6902                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6903                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6904         } else {
6905                 tw32(HOSTCC_TXCOL_TICKS, 0);
6906                 tw32(HOSTCC_TXMAX_FRAMES, 0);
6907                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
6908
6909                 tw32(HOSTCC_RXCOL_TICKS, 0);
6910                 tw32(HOSTCC_RXMAX_FRAMES, 0);
6911                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
6912         }
6913
6914         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6915                 u32 val = ec->stats_block_coalesce_usecs;
6916
6917                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6918                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6919
6920                 if (!netif_carrier_ok(tp->dev))
6921                         val = 0;
6922
6923                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6924         }
6925
6926         for (i = 0; i < tp->irq_cnt - 1; i++) {
6927                 u32 reg;
6928
6929                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
6930                 tw32(reg, ec->rx_coalesce_usecs);
6931                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
6932                 tw32(reg, ec->tx_coalesce_usecs);
6933                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
6934                 tw32(reg, ec->rx_max_coalesced_frames);
6935                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
6936                 tw32(reg, ec->tx_max_coalesced_frames);
6937                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
6938                 tw32(reg, ec->rx_max_coalesced_frames_irq);
6939                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
6940                 tw32(reg, ec->tx_max_coalesced_frames_irq);
6941         }
6942
6943         for (; i < tp->irq_max - 1; i++) {
6944                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
6945                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
6946                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
6947                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
6948                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
6949                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
6950         }
6951 }
6952
6953 /* tp->lock is held. */
6954 static void tg3_rings_reset(struct tg3 *tp)
6955 {
6956         int i;
6957         u32 stblk, txrcb, rxrcb, limit;
6958         struct tg3_napi *tnapi = &tp->napi[0];
6959
6960         /* Disable all transmit rings but the first. */
6961         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6962                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
6963         else
6964                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6965
6966         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6967              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
6968                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
6969                               BDINFO_FLAGS_DISABLED);
6970
6971
6972         /* Disable all receive return rings but the first. */
6973         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6974                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
6975         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6976                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
6977         else
6978                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6979
6980         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6981              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
6982                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
6983                               BDINFO_FLAGS_DISABLED);
6984
6985         /* Disable interrupts */
6986         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
6987
6988         /* Zero mailbox registers. */
6989         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
6990                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
6991                         tp->napi[i].tx_prod = 0;
6992                         tp->napi[i].tx_cons = 0;
6993                         tw32_mailbox(tp->napi[i].prodmbox, 0);
6994                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
6995                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
6996                 }
6997         } else {
6998                 tp->napi[0].tx_prod = 0;
6999                 tp->napi[0].tx_cons = 0;
7000                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7001                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7002         }
7003
7004         /* Make sure the NIC-based send BD rings are disabled. */
7005         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7006                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7007                 for (i = 0; i < 16; i++)
7008                         tw32_tx_mbox(mbox + i * 8, 0);
7009         }
7010
7011         txrcb = NIC_SRAM_SEND_RCB;
7012         rxrcb = NIC_SRAM_RCV_RET_RCB;
7013
7014         /* Clear status block in ram. */
7015         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7016
7017         /* Set status block DMA address */
7018         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7019              ((u64) tnapi->status_mapping >> 32));
7020         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7021              ((u64) tnapi->status_mapping & 0xffffffff));
7022
7023         if (tnapi->tx_ring) {
7024                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7025                                (TG3_TX_RING_SIZE <<
7026                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7027                                NIC_SRAM_TX_BUFFER_DESC);
7028                 txrcb += TG3_BDINFO_SIZE;
7029         }
7030
7031         if (tnapi->rx_rcb) {
7032                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7033                                (TG3_RX_RCB_RING_SIZE(tp) <<
7034                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7035                 rxrcb += TG3_BDINFO_SIZE;
7036         }
7037
7038         stblk = HOSTCC_STATBLCK_RING1;
7039
7040         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7041                 u64 mapping = (u64)tnapi->status_mapping;
7042                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7043                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7044
7045                 /* Clear status block in ram. */
7046                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7047
7048                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7049                                (TG3_TX_RING_SIZE <<
7050                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7051                                NIC_SRAM_TX_BUFFER_DESC);
7052
7053                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7054                                (TG3_RX_RCB_RING_SIZE(tp) <<
7055                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7056
7057                 stblk += 8;
7058                 txrcb += TG3_BDINFO_SIZE;
7059                 rxrcb += TG3_BDINFO_SIZE;
7060         }
7061 }
7062
7063 /* tp->lock is held. */
7064 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7065 {
7066         u32 val, rdmac_mode;
7067         int i, err, limit;
7068         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7069
7070         tg3_disable_ints(tp);
7071
7072         tg3_stop_fw(tp);
7073
7074         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7075
7076         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7077                 tg3_abort_hw(tp, 1);
7078         }
7079
7080         if (reset_phy &&
7081             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7082                 tg3_phy_reset(tp);
7083
7084         err = tg3_chip_reset(tp);
7085         if (err)
7086                 return err;
7087
7088         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7089
7090         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7091                 val = tr32(TG3_CPMU_CTRL);
7092                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7093                 tw32(TG3_CPMU_CTRL, val);
7094
7095                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7096                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7097                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7098                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7099
7100                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7101                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7102                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7103                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7104
7105                 val = tr32(TG3_CPMU_HST_ACC);
7106                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7107                 val |= CPMU_HST_ACC_MACCLK_6_25;
7108                 tw32(TG3_CPMU_HST_ACC, val);
7109         }
7110
7111         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7112                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7113                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7114                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7115                 tw32(PCIE_PWR_MGMT_THRESH, val);
7116
7117                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7118                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7119
7120                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7121         }
7122
7123         if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
7124                 val = tr32(TG3_PCIE_LNKCTL);
7125                 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
7126                         val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7127                 else
7128                         val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7129                 tw32(TG3_PCIE_LNKCTL, val);
7130         }
7131
7132         /* This works around an issue with Athlon chipsets on
7133          * B3 tigon3 silicon.  This bit has no effect on any
7134          * other revision.  But do not set this on PCI Express
7135          * chips and don't even touch the clocks if the CPMU is present.
7136          */
7137         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7138                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7139                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7140                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7141         }
7142
7143         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7144             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7145                 val = tr32(TG3PCI_PCISTATE);
7146                 val |= PCISTATE_RETRY_SAME_DMA;
7147                 tw32(TG3PCI_PCISTATE, val);
7148         }
7149
7150         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7151                 /* Allow reads and writes to the
7152                  * APE register and memory space.
7153                  */
7154                 val = tr32(TG3PCI_PCISTATE);
7155                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7156                        PCISTATE_ALLOW_APE_SHMEM_WR;
7157                 tw32(TG3PCI_PCISTATE, val);
7158         }
7159
7160         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7161                 /* Enable some hw fixes.  */
7162                 val = tr32(TG3PCI_MSI_DATA);
7163                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7164                 tw32(TG3PCI_MSI_DATA, val);
7165         }
7166
7167         /* Descriptor ring init may make accesses to the
7168          * NIC SRAM area to setup the TX descriptors, so we
7169          * can only do this after the hardware has been
7170          * successfully reset.
7171          */
7172         err = tg3_init_rings(tp);
7173         if (err)
7174                 return err;
7175
7176         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7177             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7178                 /* This value is determined during the probe time DMA
7179                  * engine test, tg3_test_dma.
7180                  */
7181                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7182         }
7183
7184         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7185                           GRC_MODE_4X_NIC_SEND_RINGS |
7186                           GRC_MODE_NO_TX_PHDR_CSUM |
7187                           GRC_MODE_NO_RX_PHDR_CSUM);
7188         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7189
7190         /* Pseudo-header checksum is done by hardware logic and not
7191          * the offload processers, so make the chip do the pseudo-
7192          * header checksums on receive.  For transmit it is more
7193          * convenient to do the pseudo-header checksum in software
7194          * as Linux does that on transmit for us in all cases.
7195          */
7196         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7197
7198         tw32(GRC_MODE,
7199              tp->grc_mode |
7200              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7201
7202         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7203         val = tr32(GRC_MISC_CFG);
7204         val &= ~0xff;
7205         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7206         tw32(GRC_MISC_CFG, val);
7207
7208         /* Initialize MBUF/DESC pool. */
7209         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7210                 /* Do nothing.  */
7211         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7212                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7213                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7214                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7215                 else
7216                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7217                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7218                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7219         }
7220         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7221                 int fw_len;
7222
7223                 fw_len = tp->fw_len;
7224                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7225                 tw32(BUFMGR_MB_POOL_ADDR,
7226                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7227                 tw32(BUFMGR_MB_POOL_SIZE,
7228                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7229         }
7230
7231         if (tp->dev->mtu <= ETH_DATA_LEN) {
7232                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7233                      tp->bufmgr_config.mbuf_read_dma_low_water);
7234                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7235                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7236                 tw32(BUFMGR_MB_HIGH_WATER,
7237                      tp->bufmgr_config.mbuf_high_water);
7238         } else {
7239                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7240                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7241                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7242                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7243                 tw32(BUFMGR_MB_HIGH_WATER,
7244                      tp->bufmgr_config.mbuf_high_water_jumbo);
7245         }
7246         tw32(BUFMGR_DMA_LOW_WATER,
7247              tp->bufmgr_config.dma_low_water);
7248         tw32(BUFMGR_DMA_HIGH_WATER,
7249              tp->bufmgr_config.dma_high_water);
7250
7251         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7252         for (i = 0; i < 2000; i++) {
7253                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7254                         break;
7255                 udelay(10);
7256         }
7257         if (i >= 2000) {
7258                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7259                        tp->dev->name);
7260                 return -ENODEV;
7261         }
7262
7263         /* Setup replenish threshold. */
7264         val = tp->rx_pending / 8;
7265         if (val == 0)
7266                 val = 1;
7267         else if (val > tp->rx_std_max_post)
7268                 val = tp->rx_std_max_post;
7269         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7270                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7271                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7272
7273                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7274                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7275         }
7276
7277         tw32(RCVBDI_STD_THRESH, val);
7278
7279         /* Initialize TG3_BDINFO's at:
7280          *  RCVDBDI_STD_BD:     standard eth size rx ring
7281          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7282          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7283          *
7284          * like so:
7285          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7286          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7287          *                              ring attribute flags
7288          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7289          *
7290          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7291          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7292          *
7293          * The size of each ring is fixed in the firmware, but the location is
7294          * configurable.
7295          */
7296         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7297              ((u64) tpr->rx_std_mapping >> 32));
7298         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7299              ((u64) tpr->rx_std_mapping & 0xffffffff));
7300         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7301              NIC_SRAM_RX_BUFFER_DESC);
7302
7303         /* Disable the mini ring */
7304         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7305                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7306                      BDINFO_FLAGS_DISABLED);
7307
7308         /* Program the jumbo buffer descriptor ring control
7309          * blocks on those devices that have them.
7310          */
7311         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7312             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7313                 /* Setup replenish threshold. */
7314                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7315
7316                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7317                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7318                              ((u64) tpr->rx_jmb_mapping >> 32));
7319                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7320                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7321                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7322                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7323                              BDINFO_FLAGS_USE_EXT_RECV);
7324                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7325                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7326                 } else {
7327                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7328                              BDINFO_FLAGS_DISABLED);
7329                 }
7330
7331                 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7332         } else
7333                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7334
7335         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7336
7337         tpr->rx_std_ptr = tp->rx_pending;
7338         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7339                      tpr->rx_std_ptr);
7340
7341         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7342                           tp->rx_jumbo_pending : 0;
7343         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7344                      tpr->rx_jmb_ptr);
7345
7346         tg3_rings_reset(tp);
7347
7348         /* Initialize MAC address and backoff seed. */
7349         __tg3_set_mac_addr(tp, 0);
7350
7351         /* MTU + ethernet header + FCS + optional VLAN tag */
7352         tw32(MAC_RX_MTU_SIZE,
7353              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7354
7355         /* The slot time is changed by tg3_setup_phy if we
7356          * run at gigabit with half duplex.
7357          */
7358         tw32(MAC_TX_LENGTHS,
7359              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7360              (6 << TX_LENGTHS_IPG_SHIFT) |
7361              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7362
7363         /* Receive rules. */
7364         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7365         tw32(RCVLPC_CONFIG, 0x0181);
7366
7367         /* Calculate RDMAC_MODE setting early, we need it to determine
7368          * the RCVLPC_STATE_ENABLE mask.
7369          */
7370         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7371                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7372                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7373                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7374                       RDMAC_MODE_LNGREAD_ENAB);
7375
7376         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7377             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7378             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7379                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7380                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7381                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7382
7383         /* If statement applies to 5705 and 5750 PCI devices only */
7384         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7385              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7386             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7387                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7388                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7389                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7390                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7391                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7392                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7393                 }
7394         }
7395
7396         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7397                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7398
7399         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7400                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7401
7402         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7403             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7404                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7405
7406         /* Receive/send statistics. */
7407         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7408                 val = tr32(RCVLPC_STATS_ENABLE);
7409                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7410                 tw32(RCVLPC_STATS_ENABLE, val);
7411         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7412                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7413                 val = tr32(RCVLPC_STATS_ENABLE);
7414                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7415                 tw32(RCVLPC_STATS_ENABLE, val);
7416         } else {
7417                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7418         }
7419         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7420         tw32(SNDDATAI_STATSENAB, 0xffffff);
7421         tw32(SNDDATAI_STATSCTRL,
7422              (SNDDATAI_SCTRL_ENABLE |
7423               SNDDATAI_SCTRL_FASTUPD));
7424
7425         /* Setup host coalescing engine. */
7426         tw32(HOSTCC_MODE, 0);
7427         for (i = 0; i < 2000; i++) {
7428                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7429                         break;
7430                 udelay(10);
7431         }
7432
7433         __tg3_set_coalesce(tp, &tp->coal);
7434
7435         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7436                 /* Status/statistics block address.  See tg3_timer,
7437                  * the tg3_periodic_fetch_stats call there, and
7438                  * tg3_get_stats to see how this works for 5705/5750 chips.
7439                  */
7440                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7441                      ((u64) tp->stats_mapping >> 32));
7442                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7443                      ((u64) tp->stats_mapping & 0xffffffff));
7444                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7445
7446                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7447
7448                 /* Clear statistics and status block memory areas */
7449                 for (i = NIC_SRAM_STATS_BLK;
7450                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7451                      i += sizeof(u32)) {
7452                         tg3_write_mem(tp, i, 0);
7453                         udelay(40);
7454                 }
7455         }
7456
7457         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7458
7459         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7460         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7461         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7462                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7463
7464         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7465                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7466                 /* reset to prevent losing 1st rx packet intermittently */
7467                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7468                 udelay(10);
7469         }
7470
7471         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7472                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7473         else
7474                 tp->mac_mode = 0;
7475         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7476                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7477         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7478             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7479             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7480                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7481         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7482         udelay(40);
7483
7484         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7485          * If TG3_FLG2_IS_NIC is zero, we should read the
7486          * register to preserve the GPIO settings for LOMs. The GPIOs,
7487          * whether used as inputs or outputs, are set by boot code after
7488          * reset.
7489          */
7490         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7491                 u32 gpio_mask;
7492
7493                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7494                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7495                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7496
7497                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7498                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7499                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7500
7501                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7502                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7503
7504                 tp->grc_local_ctrl &= ~gpio_mask;
7505                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7506
7507                 /* GPIO1 must be driven high for eeprom write protect */
7508                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7509                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7510                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7511         }
7512         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7513         udelay(100);
7514
7515         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7516                 val = tr32(MSGINT_MODE);
7517                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7518                 tw32(MSGINT_MODE, val);
7519         }
7520
7521         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7522                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7523                 udelay(40);
7524         }
7525
7526         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7527                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7528                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7529                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7530                WDMAC_MODE_LNGREAD_ENAB);
7531
7532         /* If statement applies to 5705 and 5750 PCI devices only */
7533         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7534              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7535             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7536                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7537                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7538                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7539                         /* nothing */
7540                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7541                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7542                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7543                         val |= WDMAC_MODE_RX_ACCEL;
7544                 }
7545         }
7546
7547         /* Enable host coalescing bug fix */
7548         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7549                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7550
7551         tw32_f(WDMAC_MODE, val);
7552         udelay(40);
7553
7554         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7555                 u16 pcix_cmd;
7556
7557                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7558                                      &pcix_cmd);
7559                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7560                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7561                         pcix_cmd |= PCI_X_CMD_READ_2K;
7562                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7563                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7564                         pcix_cmd |= PCI_X_CMD_READ_2K;
7565                 }
7566                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7567                                       pcix_cmd);
7568         }
7569
7570         tw32_f(RDMAC_MODE, rdmac_mode);
7571         udelay(40);
7572
7573         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7574         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7575                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7576
7577         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7578                 tw32(SNDDATAC_MODE,
7579                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7580         else
7581                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7582
7583         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7584         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7585         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7586         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7587         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7588                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7589         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7590         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7591                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7592         tw32(SNDBDI_MODE, val);
7593         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7594
7595         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7596                 err = tg3_load_5701_a0_firmware_fix(tp);
7597                 if (err)
7598                         return err;
7599         }
7600
7601         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7602                 err = tg3_load_tso_firmware(tp);
7603                 if (err)
7604                         return err;
7605         }
7606
7607         tp->tx_mode = TX_MODE_ENABLE;
7608         tw32_f(MAC_TX_MODE, tp->tx_mode);
7609         udelay(100);
7610
7611         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7612                 u32 reg = MAC_RSS_INDIR_TBL_0;
7613                 u8 *ent = (u8 *)&val;
7614
7615                 /* Setup the indirection table */
7616                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7617                         int idx = i % sizeof(val);
7618
7619                         ent[idx] = i % (tp->irq_cnt - 1);
7620                         if (idx == sizeof(val) - 1) {
7621                                 tw32(reg, val);
7622                                 reg += 4;
7623                         }
7624                 }
7625
7626                 /* Setup the "secret" hash key. */
7627                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7628                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7629                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7630                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7631                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7632                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7633                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7634                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7635                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7636                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7637         }
7638
7639         tp->rx_mode = RX_MODE_ENABLE;
7640         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7641                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7642
7643         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7644                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7645                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7646                                RX_MODE_RSS_IPV6_HASH_EN |
7647                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7648                                RX_MODE_RSS_IPV4_HASH_EN |
7649                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7650
7651         tw32_f(MAC_RX_MODE, tp->rx_mode);
7652         udelay(10);
7653
7654         tw32(MAC_LED_CTRL, tp->led_ctrl);
7655
7656         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7657         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7658                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7659                 udelay(10);
7660         }
7661         tw32_f(MAC_RX_MODE, tp->rx_mode);
7662         udelay(10);
7663
7664         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7665                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7666                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7667                         /* Set drive transmission level to 1.2V  */
7668                         /* only if the signal pre-emphasis bit is not set  */
7669                         val = tr32(MAC_SERDES_CFG);
7670                         val &= 0xfffff000;
7671                         val |= 0x880;
7672                         tw32(MAC_SERDES_CFG, val);
7673                 }
7674                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7675                         tw32(MAC_SERDES_CFG, 0x616000);
7676         }
7677
7678         /* Prevent chip from dropping frames when flow control
7679          * is enabled.
7680          */
7681         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7682
7683         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7684             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7685                 /* Use hardware link auto-negotiation */
7686                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7687         }
7688
7689         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7690             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7691                 u32 tmp;
7692
7693                 tmp = tr32(SERDES_RX_CTRL);
7694                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7695                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7696                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7697                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7698         }
7699
7700         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7701                 if (tp->link_config.phy_is_low_power) {
7702                         tp->link_config.phy_is_low_power = 0;
7703                         tp->link_config.speed = tp->link_config.orig_speed;
7704                         tp->link_config.duplex = tp->link_config.orig_duplex;
7705                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7706                 }
7707
7708                 err = tg3_setup_phy(tp, 0);
7709                 if (err)
7710                         return err;
7711
7712                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7713                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7714                         u32 tmp;
7715
7716                         /* Clear CRC stats. */
7717                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7718                                 tg3_writephy(tp, MII_TG3_TEST1,
7719                                              tmp | MII_TG3_TEST1_CRC_EN);
7720                                 tg3_readphy(tp, 0x14, &tmp);
7721                         }
7722                 }
7723         }
7724
7725         __tg3_set_rx_mode(tp->dev);
7726
7727         /* Initialize receive rules. */
7728         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7729         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7730         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7731         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7732
7733         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7734             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7735                 limit = 8;
7736         else
7737                 limit = 16;
7738         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7739                 limit -= 4;
7740         switch (limit) {
7741         case 16:
7742                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7743         case 15:
7744                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7745         case 14:
7746                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7747         case 13:
7748                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7749         case 12:
7750                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7751         case 11:
7752                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7753         case 10:
7754                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7755         case 9:
7756                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7757         case 8:
7758                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7759         case 7:
7760                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7761         case 6:
7762                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7763         case 5:
7764                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7765         case 4:
7766                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7767         case 3:
7768                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7769         case 2:
7770         case 1:
7771
7772         default:
7773                 break;
7774         }
7775
7776         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7777                 /* Write our heartbeat update interval to APE. */
7778                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7779                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7780
7781         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7782
7783         return 0;
7784 }
7785
7786 /* Called at device open time to get the chip ready for
7787  * packet processing.  Invoked with tp->lock held.
7788  */
7789 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7790 {
7791         tg3_switch_clocks(tp);
7792
7793         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7794
7795         return tg3_reset_hw(tp, reset_phy);
7796 }
7797
7798 #define TG3_STAT_ADD32(PSTAT, REG) \
7799 do {    u32 __val = tr32(REG); \
7800         (PSTAT)->low += __val; \
7801         if ((PSTAT)->low < __val) \
7802                 (PSTAT)->high += 1; \
7803 } while (0)
7804
7805 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7806 {
7807         struct tg3_hw_stats *sp = tp->hw_stats;
7808
7809         if (!netif_carrier_ok(tp->dev))
7810                 return;
7811
7812         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7813         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7814         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7815         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7816         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7817         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7818         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7819         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7820         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7821         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7822         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7823         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7824         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7825
7826         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7827         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7828         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7829         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7830         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7831         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7832         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7833         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7834         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7835         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7836         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7837         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7838         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7839         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7840
7841         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7842         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7843         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7844 }
7845
7846 static void tg3_timer(unsigned long __opaque)
7847 {
7848         struct tg3 *tp = (struct tg3 *) __opaque;
7849
7850         if (tp->irq_sync)
7851                 goto restart_timer;
7852
7853         spin_lock(&tp->lock);
7854
7855         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7856                 /* All of this garbage is because when using non-tagged
7857                  * IRQ status the mailbox/status_block protocol the chip
7858                  * uses with the cpu is race prone.
7859                  */
7860                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7861                         tw32(GRC_LOCAL_CTRL,
7862                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7863                 } else {
7864                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7865                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7866                 }
7867
7868                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7869                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7870                         spin_unlock(&tp->lock);
7871                         schedule_work(&tp->reset_task);
7872                         return;
7873                 }
7874         }
7875
7876         /* This part only runs once per second. */
7877         if (!--tp->timer_counter) {
7878                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7879                         tg3_periodic_fetch_stats(tp);
7880
7881                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7882                         u32 mac_stat;
7883                         int phy_event;
7884
7885                         mac_stat = tr32(MAC_STATUS);
7886
7887                         phy_event = 0;
7888                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7889                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7890                                         phy_event = 1;
7891                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7892                                 phy_event = 1;
7893
7894                         if (phy_event)
7895                                 tg3_setup_phy(tp, 0);
7896                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7897                         u32 mac_stat = tr32(MAC_STATUS);
7898                         int need_setup = 0;
7899
7900                         if (netif_carrier_ok(tp->dev) &&
7901                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7902                                 need_setup = 1;
7903                         }
7904                         if (! netif_carrier_ok(tp->dev) &&
7905                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7906                                          MAC_STATUS_SIGNAL_DET))) {
7907                                 need_setup = 1;
7908                         }
7909                         if (need_setup) {
7910                                 if (!tp->serdes_counter) {
7911                                         tw32_f(MAC_MODE,
7912                                              (tp->mac_mode &
7913                                               ~MAC_MODE_PORT_MODE_MASK));
7914                                         udelay(40);
7915                                         tw32_f(MAC_MODE, tp->mac_mode);
7916                                         udelay(40);
7917                                 }
7918                                 tg3_setup_phy(tp, 0);
7919                         }
7920                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7921                         tg3_serdes_parallel_detect(tp);
7922
7923                 tp->timer_counter = tp->timer_multiplier;
7924         }
7925
7926         /* Heartbeat is only sent once every 2 seconds.
7927          *
7928          * The heartbeat is to tell the ASF firmware that the host
7929          * driver is still alive.  In the event that the OS crashes,
7930          * ASF needs to reset the hardware to free up the FIFO space
7931          * that may be filled with rx packets destined for the host.
7932          * If the FIFO is full, ASF will no longer function properly.
7933          *
7934          * Unintended resets have been reported on real time kernels
7935          * where the timer doesn't run on time.  Netpoll will also have
7936          * same problem.
7937          *
7938          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7939          * to check the ring condition when the heartbeat is expiring
7940          * before doing the reset.  This will prevent most unintended
7941          * resets.
7942          */
7943         if (!--tp->asf_counter) {
7944                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7945                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7946                         tg3_wait_for_event_ack(tp);
7947
7948                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7949                                       FWCMD_NICDRV_ALIVE3);
7950                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7951                         /* 5 seconds timeout */
7952                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7953
7954                         tg3_generate_fw_event(tp);
7955                 }
7956                 tp->asf_counter = tp->asf_multiplier;
7957         }
7958
7959         spin_unlock(&tp->lock);
7960
7961 restart_timer:
7962         tp->timer.expires = jiffies + tp->timer_offset;
7963         add_timer(&tp->timer);
7964 }
7965
7966 static int tg3_request_irq(struct tg3 *tp, int irq_num)
7967 {
7968         irq_handler_t fn;
7969         unsigned long flags;
7970         char *name;
7971         struct tg3_napi *tnapi = &tp->napi[irq_num];
7972
7973         if (tp->irq_cnt == 1)
7974                 name = tp->dev->name;
7975         else {
7976                 name = &tnapi->irq_lbl[0];
7977                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
7978                 name[IFNAMSIZ-1] = 0;
7979         }
7980
7981         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
7982                 fn = tg3_msi;
7983                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7984                         fn = tg3_msi_1shot;
7985                 flags = IRQF_SAMPLE_RANDOM;
7986         } else {
7987                 fn = tg3_interrupt;
7988                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7989                         fn = tg3_interrupt_tagged;
7990                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7991         }
7992
7993         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
7994 }
7995
7996 static int tg3_test_interrupt(struct tg3 *tp)
7997 {
7998         struct tg3_napi *tnapi = &tp->napi[0];
7999         struct net_device *dev = tp->dev;
8000         int err, i, intr_ok = 0;
8001
8002         if (!netif_running(dev))
8003                 return -ENODEV;
8004
8005         tg3_disable_ints(tp);
8006
8007         free_irq(tnapi->irq_vec, tnapi);
8008
8009         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8010                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8011         if (err)
8012                 return err;
8013
8014         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8015         tg3_enable_ints(tp);
8016
8017         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8018                tnapi->coal_now);
8019
8020         for (i = 0; i < 5; i++) {
8021                 u32 int_mbox, misc_host_ctrl;
8022
8023                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8024                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8025
8026                 if ((int_mbox != 0) ||
8027                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8028                         intr_ok = 1;
8029                         break;
8030                 }
8031
8032                 msleep(10);
8033         }
8034
8035         tg3_disable_ints(tp);
8036
8037         free_irq(tnapi->irq_vec, tnapi);
8038
8039         err = tg3_request_irq(tp, 0);
8040
8041         if (err)
8042                 return err;
8043
8044         if (intr_ok)
8045                 return 0;
8046
8047         return -EIO;
8048 }
8049
8050 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8051  * successfully restored
8052  */
8053 static int tg3_test_msi(struct tg3 *tp)
8054 {
8055         int err;
8056         u16 pci_cmd;
8057
8058         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8059                 return 0;
8060
8061         /* Turn off SERR reporting in case MSI terminates with Master
8062          * Abort.
8063          */
8064         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8065         pci_write_config_word(tp->pdev, PCI_COMMAND,
8066                               pci_cmd & ~PCI_COMMAND_SERR);
8067
8068         err = tg3_test_interrupt(tp);
8069
8070         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8071
8072         if (!err)
8073                 return 0;
8074
8075         /* other failures */
8076         if (err != -EIO)
8077                 return err;
8078
8079         /* MSI test failed, go back to INTx mode */
8080         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8081                "switching to INTx mode. Please report this failure to "
8082                "the PCI maintainer and include system chipset information.\n",
8083                        tp->dev->name);
8084
8085         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8086
8087         pci_disable_msi(tp->pdev);
8088
8089         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8090
8091         err = tg3_request_irq(tp, 0);
8092         if (err)
8093                 return err;
8094
8095         /* Need to reset the chip because the MSI cycle may have terminated
8096          * with Master Abort.
8097          */
8098         tg3_full_lock(tp, 1);
8099
8100         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8101         err = tg3_init_hw(tp, 1);
8102
8103         tg3_full_unlock(tp);
8104
8105         if (err)
8106                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8107
8108         return err;
8109 }
8110
8111 static int tg3_request_firmware(struct tg3 *tp)
8112 {
8113         const __be32 *fw_data;
8114
8115         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8116                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8117                        tp->dev->name, tp->fw_needed);
8118                 return -ENOENT;
8119         }
8120
8121         fw_data = (void *)tp->fw->data;
8122
8123         /* Firmware blob starts with version numbers, followed by
8124          * start address and _full_ length including BSS sections
8125          * (which must be longer than the actual data, of course
8126          */
8127
8128         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8129         if (tp->fw_len < (tp->fw->size - 12)) {
8130                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8131                        tp->dev->name, tp->fw_len, tp->fw_needed);
8132                 release_firmware(tp->fw);
8133                 tp->fw = NULL;
8134                 return -EINVAL;
8135         }
8136
8137         /* We no longer need firmware; we have it. */
8138         tp->fw_needed = NULL;
8139         return 0;
8140 }
8141
8142 static bool tg3_enable_msix(struct tg3 *tp)
8143 {
8144         int i, rc, cpus = num_online_cpus();
8145         struct msix_entry msix_ent[tp->irq_max];
8146
8147         if (cpus == 1)
8148                 /* Just fallback to the simpler MSI mode. */
8149                 return false;
8150
8151         /*
8152          * We want as many rx rings enabled as there are cpus.
8153          * The first MSIX vector only deals with link interrupts, etc,
8154          * so we add one to the number of vectors we are requesting.
8155          */
8156         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8157
8158         for (i = 0; i < tp->irq_max; i++) {
8159                 msix_ent[i].entry  = i;
8160                 msix_ent[i].vector = 0;
8161         }
8162
8163         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8164         if (rc != 0) {
8165                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8166                         return false;
8167                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8168                         return false;
8169                 printk(KERN_NOTICE
8170                        "%s: Requested %d MSI-X vectors, received %d\n",
8171                        tp->dev->name, tp->irq_cnt, rc);
8172                 tp->irq_cnt = rc;
8173         }
8174
8175         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8176
8177         for (i = 0; i < tp->irq_max; i++)
8178                 tp->napi[i].irq_vec = msix_ent[i].vector;
8179
8180         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8181
8182         return true;
8183 }
8184
8185 static void tg3_ints_init(struct tg3 *tp)
8186 {
8187         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8188             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8189                 /* All MSI supporting chips should support tagged
8190                  * status.  Assert that this is the case.
8191                  */
8192                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8193                        "Not using MSI.\n", tp->dev->name);
8194                 goto defcfg;
8195         }
8196
8197         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8198                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8199         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8200                  pci_enable_msi(tp->pdev) == 0)
8201                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8202
8203         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8204                 u32 msi_mode = tr32(MSGINT_MODE);
8205                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8206                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8207                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8208         }
8209 defcfg:
8210         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8211                 tp->irq_cnt = 1;
8212                 tp->napi[0].irq_vec = tp->pdev->irq;
8213                 tp->dev->real_num_tx_queues = 1;
8214         }
8215 }
8216
8217 static void tg3_ints_fini(struct tg3 *tp)
8218 {
8219         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8220                 pci_disable_msix(tp->pdev);
8221         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8222                 pci_disable_msi(tp->pdev);
8223         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8224         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8225 }
8226
8227 static int tg3_open(struct net_device *dev)
8228 {
8229         struct tg3 *tp = netdev_priv(dev);
8230         int i, err;
8231
8232         if (tp->fw_needed) {
8233                 err = tg3_request_firmware(tp);
8234                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8235                         if (err)
8236                                 return err;
8237                 } else if (err) {
8238                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8239                                tp->dev->name);
8240                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8241                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8242                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8243                                tp->dev->name);
8244                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8245                 }
8246         }
8247
8248         netif_carrier_off(tp->dev);
8249
8250         err = tg3_set_power_state(tp, PCI_D0);
8251         if (err)
8252                 return err;
8253
8254         tg3_full_lock(tp, 0);
8255
8256         tg3_disable_ints(tp);
8257         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8258
8259         tg3_full_unlock(tp);
8260
8261         /*
8262          * Setup interrupts first so we know how
8263          * many NAPI resources to allocate
8264          */
8265         tg3_ints_init(tp);
8266
8267         /* The placement of this call is tied
8268          * to the setup and use of Host TX descriptors.
8269          */
8270         err = tg3_alloc_consistent(tp);
8271         if (err)
8272                 goto err_out1;
8273
8274         tg3_napi_enable(tp);
8275
8276         for (i = 0; i < tp->irq_cnt; i++) {
8277                 struct tg3_napi *tnapi = &tp->napi[i];
8278                 err = tg3_request_irq(tp, i);
8279                 if (err) {
8280                         for (i--; i >= 0; i--)
8281                                 free_irq(tnapi->irq_vec, tnapi);
8282                         break;
8283                 }
8284         }
8285
8286         if (err)
8287                 goto err_out2;
8288
8289         tg3_full_lock(tp, 0);
8290
8291         err = tg3_init_hw(tp, 1);
8292         if (err) {
8293                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8294                 tg3_free_rings(tp);
8295         } else {
8296                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8297                         tp->timer_offset = HZ;
8298                 else
8299                         tp->timer_offset = HZ / 10;
8300
8301                 BUG_ON(tp->timer_offset > HZ);
8302                 tp->timer_counter = tp->timer_multiplier =
8303                         (HZ / tp->timer_offset);
8304                 tp->asf_counter = tp->asf_multiplier =
8305                         ((HZ / tp->timer_offset) * 2);
8306
8307                 init_timer(&tp->timer);
8308                 tp->timer.expires = jiffies + tp->timer_offset;
8309                 tp->timer.data = (unsigned long) tp;
8310                 tp->timer.function = tg3_timer;
8311         }
8312
8313         tg3_full_unlock(tp);
8314
8315         if (err)
8316                 goto err_out3;
8317
8318         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8319                 err = tg3_test_msi(tp);
8320
8321                 if (err) {
8322                         tg3_full_lock(tp, 0);
8323                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8324                         tg3_free_rings(tp);
8325                         tg3_full_unlock(tp);
8326
8327                         goto err_out2;
8328                 }
8329
8330                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8331                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8332                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
8333
8334                                 tw32(PCIE_TRANSACTION_CFG,
8335                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
8336                         }
8337                 }
8338         }
8339
8340         tg3_phy_start(tp);
8341
8342         tg3_full_lock(tp, 0);
8343
8344         add_timer(&tp->timer);
8345         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8346         tg3_enable_ints(tp);
8347
8348         tg3_full_unlock(tp);
8349
8350         netif_tx_start_all_queues(dev);
8351
8352         return 0;
8353
8354 err_out3:
8355         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8356                 struct tg3_napi *tnapi = &tp->napi[i];
8357                 free_irq(tnapi->irq_vec, tnapi);
8358         }
8359
8360 err_out2:
8361         tg3_napi_disable(tp);
8362         tg3_free_consistent(tp);
8363
8364 err_out1:
8365         tg3_ints_fini(tp);
8366         return err;
8367 }
8368
8369 #if 0
8370 /*static*/ void tg3_dump_state(struct tg3 *tp)
8371 {
8372         u32 val32, val32_2, val32_3, val32_4, val32_5;
8373         u16 val16;
8374         int i;
8375         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8376
8377         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8378         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8379         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8380                val16, val32);
8381
8382         /* MAC block */
8383         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8384                tr32(MAC_MODE), tr32(MAC_STATUS));
8385         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8386                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8387         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8388                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8389         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8390                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8391
8392         /* Send data initiator control block */
8393         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8394                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8395         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8396                tr32(SNDDATAI_STATSCTRL));
8397
8398         /* Send data completion control block */
8399         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8400
8401         /* Send BD ring selector block */
8402         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8403                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8404
8405         /* Send BD initiator control block */
8406         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8407                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8408
8409         /* Send BD completion control block */
8410         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8411
8412         /* Receive list placement control block */
8413         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8414                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8415         printk("       RCVLPC_STATSCTRL[%08x]\n",
8416                tr32(RCVLPC_STATSCTRL));
8417
8418         /* Receive data and receive BD initiator control block */
8419         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8420                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8421
8422         /* Receive data completion control block */
8423         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8424                tr32(RCVDCC_MODE));
8425
8426         /* Receive BD initiator control block */
8427         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8428                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8429
8430         /* Receive BD completion control block */
8431         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8432                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8433
8434         /* Receive list selector control block */
8435         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8436                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8437
8438         /* Mbuf cluster free block */
8439         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8440                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8441
8442         /* Host coalescing control block */
8443         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8444                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8445         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8446                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8447                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8448         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8449                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8450                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8451         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8452                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8453         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8454                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8455
8456         /* Memory arbiter control block */
8457         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8458                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8459
8460         /* Buffer manager control block */
8461         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8462                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8463         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8464                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8465         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8466                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8467                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8468                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8469
8470         /* Read DMA control block */
8471         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8472                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8473
8474         /* Write DMA control block */
8475         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8476                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8477
8478         /* DMA completion block */
8479         printk("DEBUG: DMAC_MODE[%08x]\n",
8480                tr32(DMAC_MODE));
8481
8482         /* GRC block */
8483         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8484                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8485         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8486                tr32(GRC_LOCAL_CTRL));
8487
8488         /* TG3_BDINFOs */
8489         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8490                tr32(RCVDBDI_JUMBO_BD + 0x0),
8491                tr32(RCVDBDI_JUMBO_BD + 0x4),
8492                tr32(RCVDBDI_JUMBO_BD + 0x8),
8493                tr32(RCVDBDI_JUMBO_BD + 0xc));
8494         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8495                tr32(RCVDBDI_STD_BD + 0x0),
8496                tr32(RCVDBDI_STD_BD + 0x4),
8497                tr32(RCVDBDI_STD_BD + 0x8),
8498                tr32(RCVDBDI_STD_BD + 0xc));
8499         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8500                tr32(RCVDBDI_MINI_BD + 0x0),
8501                tr32(RCVDBDI_MINI_BD + 0x4),
8502                tr32(RCVDBDI_MINI_BD + 0x8),
8503                tr32(RCVDBDI_MINI_BD + 0xc));
8504
8505         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8506         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8507         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8508         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8509         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8510                val32, val32_2, val32_3, val32_4);
8511
8512         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8513         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8514         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8515         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8516         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8517                val32, val32_2, val32_3, val32_4);
8518
8519         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8520         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8521         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8522         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8523         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8524         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8525                val32, val32_2, val32_3, val32_4, val32_5);
8526
8527         /* SW status block */
8528         printk(KERN_DEBUG
8529          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8530                sblk->status,
8531                sblk->status_tag,
8532                sblk->rx_jumbo_consumer,
8533                sblk->rx_consumer,
8534                sblk->rx_mini_consumer,
8535                sblk->idx[0].rx_producer,
8536                sblk->idx[0].tx_consumer);
8537
8538         /* SW statistics block */
8539         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8540                ((u32 *)tp->hw_stats)[0],
8541                ((u32 *)tp->hw_stats)[1],
8542                ((u32 *)tp->hw_stats)[2],
8543                ((u32 *)tp->hw_stats)[3]);
8544
8545         /* Mailboxes */
8546         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8547                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8548                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8549                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8550                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8551
8552         /* NIC side send descriptors. */
8553         for (i = 0; i < 6; i++) {
8554                 unsigned long txd;
8555
8556                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8557                         + (i * sizeof(struct tg3_tx_buffer_desc));
8558                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8559                        i,
8560                        readl(txd + 0x0), readl(txd + 0x4),
8561                        readl(txd + 0x8), readl(txd + 0xc));
8562         }
8563
8564         /* NIC side RX descriptors. */
8565         for (i = 0; i < 6; i++) {
8566                 unsigned long rxd;
8567
8568                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8569                         + (i * sizeof(struct tg3_rx_buffer_desc));
8570                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8571                        i,
8572                        readl(rxd + 0x0), readl(rxd + 0x4),
8573                        readl(rxd + 0x8), readl(rxd + 0xc));
8574                 rxd += (4 * sizeof(u32));
8575                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8576                        i,
8577                        readl(rxd + 0x0), readl(rxd + 0x4),
8578                        readl(rxd + 0x8), readl(rxd + 0xc));
8579         }
8580
8581         for (i = 0; i < 6; i++) {
8582                 unsigned long rxd;
8583
8584                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8585                         + (i * sizeof(struct tg3_rx_buffer_desc));
8586                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8587                        i,
8588                        readl(rxd + 0x0), readl(rxd + 0x4),
8589                        readl(rxd + 0x8), readl(rxd + 0xc));
8590                 rxd += (4 * sizeof(u32));
8591                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8592                        i,
8593                        readl(rxd + 0x0), readl(rxd + 0x4),
8594                        readl(rxd + 0x8), readl(rxd + 0xc));
8595         }
8596 }
8597 #endif
8598
8599 static struct net_device_stats *tg3_get_stats(struct net_device *);
8600 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8601
8602 static int tg3_close(struct net_device *dev)
8603 {
8604         int i;
8605         struct tg3 *tp = netdev_priv(dev);
8606
8607         tg3_napi_disable(tp);
8608         cancel_work_sync(&tp->reset_task);
8609
8610         netif_tx_stop_all_queues(dev);
8611
8612         del_timer_sync(&tp->timer);
8613
8614         tg3_full_lock(tp, 1);
8615 #if 0
8616         tg3_dump_state(tp);
8617 #endif
8618
8619         tg3_disable_ints(tp);
8620
8621         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8622         tg3_free_rings(tp);
8623         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8624
8625         tg3_full_unlock(tp);
8626
8627         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8628                 struct tg3_napi *tnapi = &tp->napi[i];
8629                 free_irq(tnapi->irq_vec, tnapi);
8630         }
8631
8632         tg3_ints_fini(tp);
8633
8634         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8635                sizeof(tp->net_stats_prev));
8636         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8637                sizeof(tp->estats_prev));
8638
8639         tg3_free_consistent(tp);
8640
8641         tg3_set_power_state(tp, PCI_D3hot);
8642
8643         netif_carrier_off(tp->dev);
8644
8645         return 0;
8646 }
8647
8648 static inline unsigned long get_stat64(tg3_stat64_t *val)
8649 {
8650         unsigned long ret;
8651
8652 #if (BITS_PER_LONG == 32)
8653         ret = val->low;
8654 #else
8655         ret = ((u64)val->high << 32) | ((u64)val->low);
8656 #endif
8657         return ret;
8658 }
8659
8660 static inline u64 get_estat64(tg3_stat64_t *val)
8661 {
8662        return ((u64)val->high << 32) | ((u64)val->low);
8663 }
8664
8665 static unsigned long calc_crc_errors(struct tg3 *tp)
8666 {
8667         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8668
8669         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8670             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8671              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8672                 u32 val;
8673
8674                 spin_lock_bh(&tp->lock);
8675                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8676                         tg3_writephy(tp, MII_TG3_TEST1,
8677                                      val | MII_TG3_TEST1_CRC_EN);
8678                         tg3_readphy(tp, 0x14, &val);
8679                 } else
8680                         val = 0;
8681                 spin_unlock_bh(&tp->lock);
8682
8683                 tp->phy_crc_errors += val;
8684
8685                 return tp->phy_crc_errors;
8686         }
8687
8688         return get_stat64(&hw_stats->rx_fcs_errors);
8689 }
8690
8691 #define ESTAT_ADD(member) \
8692         estats->member =        old_estats->member + \
8693                                 get_estat64(&hw_stats->member)
8694
8695 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8696 {
8697         struct tg3_ethtool_stats *estats = &tp->estats;
8698         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8699         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8700
8701         if (!hw_stats)
8702                 return old_estats;
8703
8704         ESTAT_ADD(rx_octets);
8705         ESTAT_ADD(rx_fragments);
8706         ESTAT_ADD(rx_ucast_packets);
8707         ESTAT_ADD(rx_mcast_packets);
8708         ESTAT_ADD(rx_bcast_packets);
8709         ESTAT_ADD(rx_fcs_errors);
8710         ESTAT_ADD(rx_align_errors);
8711         ESTAT_ADD(rx_xon_pause_rcvd);
8712         ESTAT_ADD(rx_xoff_pause_rcvd);
8713         ESTAT_ADD(rx_mac_ctrl_rcvd);
8714         ESTAT_ADD(rx_xoff_entered);
8715         ESTAT_ADD(rx_frame_too_long_errors);
8716         ESTAT_ADD(rx_jabbers);
8717         ESTAT_ADD(rx_undersize_packets);
8718         ESTAT_ADD(rx_in_length_errors);
8719         ESTAT_ADD(rx_out_length_errors);
8720         ESTAT_ADD(rx_64_or_less_octet_packets);
8721         ESTAT_ADD(rx_65_to_127_octet_packets);
8722         ESTAT_ADD(rx_128_to_255_octet_packets);
8723         ESTAT_ADD(rx_256_to_511_octet_packets);
8724         ESTAT_ADD(rx_512_to_1023_octet_packets);
8725         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8726         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8727         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8728         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8729         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8730
8731         ESTAT_ADD(tx_octets);
8732         ESTAT_ADD(tx_collisions);
8733         ESTAT_ADD(tx_xon_sent);
8734         ESTAT_ADD(tx_xoff_sent);
8735         ESTAT_ADD(tx_flow_control);
8736         ESTAT_ADD(tx_mac_errors);
8737         ESTAT_ADD(tx_single_collisions);
8738         ESTAT_ADD(tx_mult_collisions);
8739         ESTAT_ADD(tx_deferred);
8740         ESTAT_ADD(tx_excessive_collisions);
8741         ESTAT_ADD(tx_late_collisions);
8742         ESTAT_ADD(tx_collide_2times);
8743         ESTAT_ADD(tx_collide_3times);
8744         ESTAT_ADD(tx_collide_4times);
8745         ESTAT_ADD(tx_collide_5times);
8746         ESTAT_ADD(tx_collide_6times);
8747         ESTAT_ADD(tx_collide_7times);
8748         ESTAT_ADD(tx_collide_8times);
8749         ESTAT_ADD(tx_collide_9times);
8750         ESTAT_ADD(tx_collide_10times);
8751         ESTAT_ADD(tx_collide_11times);
8752         ESTAT_ADD(tx_collide_12times);
8753         ESTAT_ADD(tx_collide_13times);
8754         ESTAT_ADD(tx_collide_14times);
8755         ESTAT_ADD(tx_collide_15times);
8756         ESTAT_ADD(tx_ucast_packets);
8757         ESTAT_ADD(tx_mcast_packets);
8758         ESTAT_ADD(tx_bcast_packets);
8759         ESTAT_ADD(tx_carrier_sense_errors);
8760         ESTAT_ADD(tx_discards);
8761         ESTAT_ADD(tx_errors);
8762
8763         ESTAT_ADD(dma_writeq_full);
8764         ESTAT_ADD(dma_write_prioq_full);
8765         ESTAT_ADD(rxbds_empty);
8766         ESTAT_ADD(rx_discards);
8767         ESTAT_ADD(rx_errors);
8768         ESTAT_ADD(rx_threshold_hit);
8769
8770         ESTAT_ADD(dma_readq_full);
8771         ESTAT_ADD(dma_read_prioq_full);
8772         ESTAT_ADD(tx_comp_queue_full);
8773
8774         ESTAT_ADD(ring_set_send_prod_index);
8775         ESTAT_ADD(ring_status_update);
8776         ESTAT_ADD(nic_irqs);
8777         ESTAT_ADD(nic_avoided_irqs);
8778         ESTAT_ADD(nic_tx_threshold_hit);
8779
8780         return estats;
8781 }
8782
8783 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8784 {
8785         struct tg3 *tp = netdev_priv(dev);
8786         struct net_device_stats *stats = &tp->net_stats;
8787         struct net_device_stats *old_stats = &tp->net_stats_prev;
8788         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8789
8790         if (!hw_stats)
8791                 return old_stats;
8792
8793         stats->rx_packets = old_stats->rx_packets +
8794                 get_stat64(&hw_stats->rx_ucast_packets) +
8795                 get_stat64(&hw_stats->rx_mcast_packets) +
8796                 get_stat64(&hw_stats->rx_bcast_packets);
8797
8798         stats->tx_packets = old_stats->tx_packets +
8799                 get_stat64(&hw_stats->tx_ucast_packets) +
8800                 get_stat64(&hw_stats->tx_mcast_packets) +
8801                 get_stat64(&hw_stats->tx_bcast_packets);
8802
8803         stats->rx_bytes = old_stats->rx_bytes +
8804                 get_stat64(&hw_stats->rx_octets);
8805         stats->tx_bytes = old_stats->tx_bytes +
8806                 get_stat64(&hw_stats->tx_octets);
8807
8808         stats->rx_errors = old_stats->rx_errors +
8809                 get_stat64(&hw_stats->rx_errors);
8810         stats->tx_errors = old_stats->tx_errors +
8811                 get_stat64(&hw_stats->tx_errors) +
8812                 get_stat64(&hw_stats->tx_mac_errors) +
8813                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8814                 get_stat64(&hw_stats->tx_discards);
8815
8816         stats->multicast = old_stats->multicast +
8817                 get_stat64(&hw_stats->rx_mcast_packets);
8818         stats->collisions = old_stats->collisions +
8819                 get_stat64(&hw_stats->tx_collisions);
8820
8821         stats->rx_length_errors = old_stats->rx_length_errors +
8822                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8823                 get_stat64(&hw_stats->rx_undersize_packets);
8824
8825         stats->rx_over_errors = old_stats->rx_over_errors +
8826                 get_stat64(&hw_stats->rxbds_empty);
8827         stats->rx_frame_errors = old_stats->rx_frame_errors +
8828                 get_stat64(&hw_stats->rx_align_errors);
8829         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8830                 get_stat64(&hw_stats->tx_discards);
8831         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8832                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8833
8834         stats->rx_crc_errors = old_stats->rx_crc_errors +
8835                 calc_crc_errors(tp);
8836
8837         stats->rx_missed_errors = old_stats->rx_missed_errors +
8838                 get_stat64(&hw_stats->rx_discards);
8839
8840         return stats;
8841 }
8842
8843 static inline u32 calc_crc(unsigned char *buf, int len)
8844 {
8845         u32 reg;
8846         u32 tmp;
8847         int j, k;
8848
8849         reg = 0xffffffff;
8850
8851         for (j = 0; j < len; j++) {
8852                 reg ^= buf[j];
8853
8854                 for (k = 0; k < 8; k++) {
8855                         tmp = reg & 0x01;
8856
8857                         reg >>= 1;
8858
8859                         if (tmp) {
8860                                 reg ^= 0xedb88320;
8861                         }
8862                 }
8863         }
8864
8865         return ~reg;
8866 }
8867
8868 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8869 {
8870         /* accept or reject all multicast frames */
8871         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8872         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8873         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8874         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8875 }
8876
8877 static void __tg3_set_rx_mode(struct net_device *dev)
8878 {
8879         struct tg3 *tp = netdev_priv(dev);
8880         u32 rx_mode;
8881
8882         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8883                                   RX_MODE_KEEP_VLAN_TAG);
8884
8885         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8886          * flag clear.
8887          */
8888 #if TG3_VLAN_TAG_USED
8889         if (!tp->vlgrp &&
8890             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8891                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8892 #else
8893         /* By definition, VLAN is disabled always in this
8894          * case.
8895          */
8896         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8897                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8898 #endif
8899
8900         if (dev->flags & IFF_PROMISC) {
8901                 /* Promiscuous mode. */
8902                 rx_mode |= RX_MODE_PROMISC;
8903         } else if (dev->flags & IFF_ALLMULTI) {
8904                 /* Accept all multicast. */
8905                 tg3_set_multi (tp, 1);
8906         } else if (dev->mc_count < 1) {
8907                 /* Reject all multicast. */
8908                 tg3_set_multi (tp, 0);
8909         } else {
8910                 /* Accept one or more multicast(s). */
8911                 struct dev_mc_list *mclist;
8912                 unsigned int i;
8913                 u32 mc_filter[4] = { 0, };
8914                 u32 regidx;
8915                 u32 bit;
8916                 u32 crc;
8917
8918                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8919                      i++, mclist = mclist->next) {
8920
8921                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8922                         bit = ~crc & 0x7f;
8923                         regidx = (bit & 0x60) >> 5;
8924                         bit &= 0x1f;
8925                         mc_filter[regidx] |= (1 << bit);
8926                 }
8927
8928                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8929                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8930                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8931                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8932         }
8933
8934         if (rx_mode != tp->rx_mode) {
8935                 tp->rx_mode = rx_mode;
8936                 tw32_f(MAC_RX_MODE, rx_mode);
8937                 udelay(10);
8938         }
8939 }
8940
8941 static void tg3_set_rx_mode(struct net_device *dev)
8942 {
8943         struct tg3 *tp = netdev_priv(dev);
8944
8945         if (!netif_running(dev))
8946                 return;
8947
8948         tg3_full_lock(tp, 0);
8949         __tg3_set_rx_mode(dev);
8950         tg3_full_unlock(tp);
8951 }
8952
8953 #define TG3_REGDUMP_LEN         (32 * 1024)
8954
8955 static int tg3_get_regs_len(struct net_device *dev)
8956 {
8957         return TG3_REGDUMP_LEN;
8958 }
8959
8960 static void tg3_get_regs(struct net_device *dev,
8961                 struct ethtool_regs *regs, void *_p)
8962 {
8963         u32 *p = _p;
8964         struct tg3 *tp = netdev_priv(dev);
8965         u8 *orig_p = _p;
8966         int i;
8967
8968         regs->version = 0;
8969
8970         memset(p, 0, TG3_REGDUMP_LEN);
8971
8972         if (tp->link_config.phy_is_low_power)
8973                 return;
8974
8975         tg3_full_lock(tp, 0);
8976
8977 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8978 #define GET_REG32_LOOP(base,len)                \
8979 do {    p = (u32 *)(orig_p + (base));           \
8980         for (i = 0; i < len; i += 4)            \
8981                 __GET_REG32((base) + i);        \
8982 } while (0)
8983 #define GET_REG32_1(reg)                        \
8984 do {    p = (u32 *)(orig_p + (reg));            \
8985         __GET_REG32((reg));                     \
8986 } while (0)
8987
8988         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8989         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8990         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8991         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8992         GET_REG32_1(SNDDATAC_MODE);
8993         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8994         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8995         GET_REG32_1(SNDBDC_MODE);
8996         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8997         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8998         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8999         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9000         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9001         GET_REG32_1(RCVDCC_MODE);
9002         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9003         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9004         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9005         GET_REG32_1(MBFREE_MODE);
9006         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9007         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9008         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9009         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9010         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9011         GET_REG32_1(RX_CPU_MODE);
9012         GET_REG32_1(RX_CPU_STATE);
9013         GET_REG32_1(RX_CPU_PGMCTR);
9014         GET_REG32_1(RX_CPU_HWBKPT);
9015         GET_REG32_1(TX_CPU_MODE);
9016         GET_REG32_1(TX_CPU_STATE);
9017         GET_REG32_1(TX_CPU_PGMCTR);
9018         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9019         GET_REG32_LOOP(FTQ_RESET, 0x120);
9020         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9021         GET_REG32_1(DMAC_MODE);
9022         GET_REG32_LOOP(GRC_MODE, 0x4c);
9023         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9024                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9025
9026 #undef __GET_REG32
9027 #undef GET_REG32_LOOP
9028 #undef GET_REG32_1
9029
9030         tg3_full_unlock(tp);
9031 }
9032
9033 static int tg3_get_eeprom_len(struct net_device *dev)
9034 {
9035         struct tg3 *tp = netdev_priv(dev);
9036
9037         return tp->nvram_size;
9038 }
9039
9040 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9041 {
9042         struct tg3 *tp = netdev_priv(dev);
9043         int ret;
9044         u8  *pd;
9045         u32 i, offset, len, b_offset, b_count;
9046         __be32 val;
9047
9048         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9049                 return -EINVAL;
9050
9051         if (tp->link_config.phy_is_low_power)
9052                 return -EAGAIN;
9053
9054         offset = eeprom->offset;
9055         len = eeprom->len;
9056         eeprom->len = 0;
9057
9058         eeprom->magic = TG3_EEPROM_MAGIC;
9059
9060         if (offset & 3) {
9061                 /* adjustments to start on required 4 byte boundary */
9062                 b_offset = offset & 3;
9063                 b_count = 4 - b_offset;
9064                 if (b_count > len) {
9065                         /* i.e. offset=1 len=2 */
9066                         b_count = len;
9067                 }
9068                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9069                 if (ret)
9070                         return ret;
9071                 memcpy(data, ((char*)&val) + b_offset, b_count);
9072                 len -= b_count;
9073                 offset += b_count;
9074                 eeprom->len += b_count;
9075         }
9076
9077         /* read bytes upto the last 4 byte boundary */
9078         pd = &data[eeprom->len];
9079         for (i = 0; i < (len - (len & 3)); i += 4) {
9080                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9081                 if (ret) {
9082                         eeprom->len += i;
9083                         return ret;
9084                 }
9085                 memcpy(pd + i, &val, 4);
9086         }
9087         eeprom->len += i;
9088
9089         if (len & 3) {
9090                 /* read last bytes not ending on 4 byte boundary */
9091                 pd = &data[eeprom->len];
9092                 b_count = len & 3;
9093                 b_offset = offset + len - b_count;
9094                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9095                 if (ret)
9096                         return ret;
9097                 memcpy(pd, &val, b_count);
9098                 eeprom->len += b_count;
9099         }
9100         return 0;
9101 }
9102
9103 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9104
9105 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9106 {
9107         struct tg3 *tp = netdev_priv(dev);
9108         int ret;
9109         u32 offset, len, b_offset, odd_len;
9110         u8 *buf;
9111         __be32 start, end;
9112
9113         if (tp->link_config.phy_is_low_power)
9114                 return -EAGAIN;
9115
9116         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9117             eeprom->magic != TG3_EEPROM_MAGIC)
9118                 return -EINVAL;
9119
9120         offset = eeprom->offset;
9121         len = eeprom->len;
9122
9123         if ((b_offset = (offset & 3))) {
9124                 /* adjustments to start on required 4 byte boundary */
9125                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9126                 if (ret)
9127                         return ret;
9128                 len += b_offset;
9129                 offset &= ~3;
9130                 if (len < 4)
9131                         len = 4;
9132         }
9133
9134         odd_len = 0;
9135         if (len & 3) {
9136                 /* adjustments to end on required 4 byte boundary */
9137                 odd_len = 1;
9138                 len = (len + 3) & ~3;
9139                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9140                 if (ret)
9141                         return ret;
9142         }
9143
9144         buf = data;
9145         if (b_offset || odd_len) {
9146                 buf = kmalloc(len, GFP_KERNEL);
9147                 if (!buf)
9148                         return -ENOMEM;
9149                 if (b_offset)
9150                         memcpy(buf, &start, 4);
9151                 if (odd_len)
9152                         memcpy(buf+len-4, &end, 4);
9153                 memcpy(buf + b_offset, data, eeprom->len);
9154         }
9155
9156         ret = tg3_nvram_write_block(tp, offset, len, buf);
9157
9158         if (buf != data)
9159                 kfree(buf);
9160
9161         return ret;
9162 }
9163
9164 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9165 {
9166         struct tg3 *tp = netdev_priv(dev);
9167
9168         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9169                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9170                         return -EAGAIN;
9171                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9172         }
9173
9174         cmd->supported = (SUPPORTED_Autoneg);
9175
9176         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9177                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9178                                    SUPPORTED_1000baseT_Full);
9179
9180         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9181                 cmd->supported |= (SUPPORTED_100baseT_Half |
9182                                   SUPPORTED_100baseT_Full |
9183                                   SUPPORTED_10baseT_Half |
9184                                   SUPPORTED_10baseT_Full |
9185                                   SUPPORTED_TP);
9186                 cmd->port = PORT_TP;
9187         } else {
9188                 cmd->supported |= SUPPORTED_FIBRE;
9189                 cmd->port = PORT_FIBRE;
9190         }
9191
9192         cmd->advertising = tp->link_config.advertising;
9193         if (netif_running(dev)) {
9194                 cmd->speed = tp->link_config.active_speed;
9195                 cmd->duplex = tp->link_config.active_duplex;
9196         }
9197         cmd->phy_address = PHY_ADDR;
9198         cmd->transceiver = XCVR_INTERNAL;
9199         cmd->autoneg = tp->link_config.autoneg;
9200         cmd->maxtxpkt = 0;
9201         cmd->maxrxpkt = 0;
9202         return 0;
9203 }
9204
9205 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9206 {
9207         struct tg3 *tp = netdev_priv(dev);
9208
9209         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9210                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9211                         return -EAGAIN;
9212                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9213         }
9214
9215         if (cmd->autoneg != AUTONEG_ENABLE &&
9216             cmd->autoneg != AUTONEG_DISABLE)
9217                 return -EINVAL;
9218
9219         if (cmd->autoneg == AUTONEG_DISABLE &&
9220             cmd->duplex != DUPLEX_FULL &&
9221             cmd->duplex != DUPLEX_HALF)
9222                 return -EINVAL;
9223
9224         if (cmd->autoneg == AUTONEG_ENABLE) {
9225                 u32 mask = ADVERTISED_Autoneg |
9226                            ADVERTISED_Pause |
9227                            ADVERTISED_Asym_Pause;
9228
9229                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9230                         mask |= ADVERTISED_1000baseT_Half |
9231                                 ADVERTISED_1000baseT_Full;
9232
9233                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9234                         mask |= ADVERTISED_100baseT_Half |
9235                                 ADVERTISED_100baseT_Full |
9236                                 ADVERTISED_10baseT_Half |
9237                                 ADVERTISED_10baseT_Full |
9238                                 ADVERTISED_TP;
9239                 else
9240                         mask |= ADVERTISED_FIBRE;
9241
9242                 if (cmd->advertising & ~mask)
9243                         return -EINVAL;
9244
9245                 mask &= (ADVERTISED_1000baseT_Half |
9246                          ADVERTISED_1000baseT_Full |
9247                          ADVERTISED_100baseT_Half |
9248                          ADVERTISED_100baseT_Full |
9249                          ADVERTISED_10baseT_Half |
9250                          ADVERTISED_10baseT_Full);
9251
9252                 cmd->advertising &= mask;
9253         } else {
9254                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9255                         if (cmd->speed != SPEED_1000)
9256                                 return -EINVAL;
9257
9258                         if (cmd->duplex != DUPLEX_FULL)
9259                                 return -EINVAL;
9260                 } else {
9261                         if (cmd->speed != SPEED_100 &&
9262                             cmd->speed != SPEED_10)
9263                                 return -EINVAL;
9264                 }
9265         }
9266
9267         tg3_full_lock(tp, 0);
9268
9269         tp->link_config.autoneg = cmd->autoneg;
9270         if (cmd->autoneg == AUTONEG_ENABLE) {
9271                 tp->link_config.advertising = (cmd->advertising |
9272                                               ADVERTISED_Autoneg);
9273                 tp->link_config.speed = SPEED_INVALID;
9274                 tp->link_config.duplex = DUPLEX_INVALID;
9275         } else {
9276                 tp->link_config.advertising = 0;
9277                 tp->link_config.speed = cmd->speed;
9278                 tp->link_config.duplex = cmd->duplex;
9279         }
9280
9281         tp->link_config.orig_speed = tp->link_config.speed;
9282         tp->link_config.orig_duplex = tp->link_config.duplex;
9283         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9284
9285         if (netif_running(dev))
9286                 tg3_setup_phy(tp, 1);
9287
9288         tg3_full_unlock(tp);
9289
9290         return 0;
9291 }
9292
9293 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9294 {
9295         struct tg3 *tp = netdev_priv(dev);
9296
9297         strcpy(info->driver, DRV_MODULE_NAME);
9298         strcpy(info->version, DRV_MODULE_VERSION);
9299         strcpy(info->fw_version, tp->fw_ver);
9300         strcpy(info->bus_info, pci_name(tp->pdev));
9301 }
9302
9303 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9304 {
9305         struct tg3 *tp = netdev_priv(dev);
9306
9307         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9308             device_can_wakeup(&tp->pdev->dev))
9309                 wol->supported = WAKE_MAGIC;
9310         else
9311                 wol->supported = 0;
9312         wol->wolopts = 0;
9313         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9314             device_can_wakeup(&tp->pdev->dev))
9315                 wol->wolopts = WAKE_MAGIC;
9316         memset(&wol->sopass, 0, sizeof(wol->sopass));
9317 }
9318
9319 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9320 {
9321         struct tg3 *tp = netdev_priv(dev);
9322         struct device *dp = &tp->pdev->dev;
9323
9324         if (wol->wolopts & ~WAKE_MAGIC)
9325                 return -EINVAL;
9326         if ((wol->wolopts & WAKE_MAGIC) &&
9327             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9328                 return -EINVAL;
9329
9330         spin_lock_bh(&tp->lock);
9331         if (wol->wolopts & WAKE_MAGIC) {
9332                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9333                 device_set_wakeup_enable(dp, true);
9334         } else {
9335                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9336                 device_set_wakeup_enable(dp, false);
9337         }
9338         spin_unlock_bh(&tp->lock);
9339
9340         return 0;
9341 }
9342
9343 static u32 tg3_get_msglevel(struct net_device *dev)
9344 {
9345         struct tg3 *tp = netdev_priv(dev);
9346         return tp->msg_enable;
9347 }
9348
9349 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9350 {
9351         struct tg3 *tp = netdev_priv(dev);
9352         tp->msg_enable = value;
9353 }
9354
9355 static int tg3_set_tso(struct net_device *dev, u32 value)
9356 {
9357         struct tg3 *tp = netdev_priv(dev);
9358
9359         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9360                 if (value)
9361                         return -EINVAL;
9362                 return 0;
9363         }
9364         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9365             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9366                 if (value) {
9367                         dev->features |= NETIF_F_TSO6;
9368                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9369                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9370                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9371                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9372                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9373                                 dev->features |= NETIF_F_TSO_ECN;
9374                 } else
9375                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9376         }
9377         return ethtool_op_set_tso(dev, value);
9378 }
9379
9380 static int tg3_nway_reset(struct net_device *dev)
9381 {
9382         struct tg3 *tp = netdev_priv(dev);
9383         int r;
9384
9385         if (!netif_running(dev))
9386                 return -EAGAIN;
9387
9388         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9389                 return -EINVAL;
9390
9391         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9392                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9393                         return -EAGAIN;
9394                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
9395         } else {
9396                 u32 bmcr;
9397
9398                 spin_lock_bh(&tp->lock);
9399                 r = -EINVAL;
9400                 tg3_readphy(tp, MII_BMCR, &bmcr);
9401                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9402                     ((bmcr & BMCR_ANENABLE) ||
9403                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9404                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9405                                                    BMCR_ANENABLE);
9406                         r = 0;
9407                 }
9408                 spin_unlock_bh(&tp->lock);
9409         }
9410
9411         return r;
9412 }
9413
9414 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9415 {
9416         struct tg3 *tp = netdev_priv(dev);
9417
9418         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9419         ering->rx_mini_max_pending = 0;
9420         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9421                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9422         else
9423                 ering->rx_jumbo_max_pending = 0;
9424
9425         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9426
9427         ering->rx_pending = tp->rx_pending;
9428         ering->rx_mini_pending = 0;
9429         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9430                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9431         else
9432                 ering->rx_jumbo_pending = 0;
9433
9434         ering->tx_pending = tp->napi[0].tx_pending;
9435 }
9436
9437 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9438 {
9439         struct tg3 *tp = netdev_priv(dev);
9440         int i, irq_sync = 0, err = 0;
9441
9442         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9443             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9444             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9445             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9446             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9447              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9448                 return -EINVAL;
9449
9450         if (netif_running(dev)) {
9451                 tg3_phy_stop(tp);
9452                 tg3_netif_stop(tp);
9453                 irq_sync = 1;
9454         }
9455
9456         tg3_full_lock(tp, irq_sync);
9457
9458         tp->rx_pending = ering->rx_pending;
9459
9460         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9461             tp->rx_pending > 63)
9462                 tp->rx_pending = 63;
9463         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9464
9465         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9466                 tp->napi[i].tx_pending = ering->tx_pending;
9467
9468         if (netif_running(dev)) {
9469                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9470                 err = tg3_restart_hw(tp, 1);
9471                 if (!err)
9472                         tg3_netif_start(tp);
9473         }
9474
9475         tg3_full_unlock(tp);
9476
9477         if (irq_sync && !err)
9478                 tg3_phy_start(tp);
9479
9480         return err;
9481 }
9482
9483 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9484 {
9485         struct tg3 *tp = netdev_priv(dev);
9486
9487         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9488
9489         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9490                 epause->rx_pause = 1;
9491         else
9492                 epause->rx_pause = 0;
9493
9494         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9495                 epause->tx_pause = 1;
9496         else
9497                 epause->tx_pause = 0;
9498 }
9499
9500 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9501 {
9502         struct tg3 *tp = netdev_priv(dev);
9503         int err = 0;
9504
9505         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9506                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9507                         return -EAGAIN;
9508
9509                 if (epause->autoneg) {
9510                         u32 newadv;
9511                         struct phy_device *phydev;
9512
9513                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9514
9515                         if (epause->rx_pause) {
9516                                 if (epause->tx_pause)
9517                                         newadv = ADVERTISED_Pause;
9518                                 else
9519                                         newadv = ADVERTISED_Pause |
9520                                                  ADVERTISED_Asym_Pause;
9521                         } else if (epause->tx_pause) {
9522                                 newadv = ADVERTISED_Asym_Pause;
9523                         } else
9524                                 newadv = 0;
9525
9526                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9527                                 u32 oldadv = phydev->advertising &
9528                                              (ADVERTISED_Pause |
9529                                               ADVERTISED_Asym_Pause);
9530                                 if (oldadv != newadv) {
9531                                         phydev->advertising &=
9532                                                 ~(ADVERTISED_Pause |
9533                                                   ADVERTISED_Asym_Pause);
9534                                         phydev->advertising |= newadv;
9535                                         err = phy_start_aneg(phydev);
9536                                 }
9537                         } else {
9538                                 tp->link_config.advertising &=
9539                                                 ~(ADVERTISED_Pause |
9540                                                   ADVERTISED_Asym_Pause);
9541                                 tp->link_config.advertising |= newadv;
9542                         }
9543                 } else {
9544                         if (epause->rx_pause)
9545                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9546                         else
9547                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9548
9549                         if (epause->tx_pause)
9550                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9551                         else
9552                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9553
9554                         if (netif_running(dev))
9555                                 tg3_setup_flow_control(tp, 0, 0);
9556                 }
9557         } else {
9558                 int irq_sync = 0;
9559
9560                 if (netif_running(dev)) {
9561                         tg3_netif_stop(tp);
9562                         irq_sync = 1;
9563                 }
9564
9565                 tg3_full_lock(tp, irq_sync);
9566
9567                 if (epause->autoneg)
9568                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9569                 else
9570                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9571                 if (epause->rx_pause)
9572                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9573                 else
9574                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9575                 if (epause->tx_pause)
9576                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9577                 else
9578                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9579
9580                 if (netif_running(dev)) {
9581                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9582                         err = tg3_restart_hw(tp, 1);
9583                         if (!err)
9584                                 tg3_netif_start(tp);
9585                 }
9586
9587                 tg3_full_unlock(tp);
9588         }
9589
9590         return err;
9591 }
9592
9593 static u32 tg3_get_rx_csum(struct net_device *dev)
9594 {
9595         struct tg3 *tp = netdev_priv(dev);
9596         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9597 }
9598
9599 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9600 {
9601         struct tg3 *tp = netdev_priv(dev);
9602
9603         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9604                 if (data != 0)
9605                         return -EINVAL;
9606                 return 0;
9607         }
9608
9609         spin_lock_bh(&tp->lock);
9610         if (data)
9611                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9612         else
9613                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9614         spin_unlock_bh(&tp->lock);
9615
9616         return 0;
9617 }
9618
9619 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9620 {
9621         struct tg3 *tp = netdev_priv(dev);
9622
9623         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9624                 if (data != 0)
9625                         return -EINVAL;
9626                 return 0;
9627         }
9628
9629         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9630                 ethtool_op_set_tx_ipv6_csum(dev, data);
9631         else
9632                 ethtool_op_set_tx_csum(dev, data);
9633
9634         return 0;
9635 }
9636
9637 static int tg3_get_sset_count (struct net_device *dev, int sset)
9638 {
9639         switch (sset) {
9640         case ETH_SS_TEST:
9641                 return TG3_NUM_TEST;
9642         case ETH_SS_STATS:
9643                 return TG3_NUM_STATS;
9644         default:
9645                 return -EOPNOTSUPP;
9646         }
9647 }
9648
9649 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9650 {
9651         switch (stringset) {
9652         case ETH_SS_STATS:
9653                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9654                 break;
9655         case ETH_SS_TEST:
9656                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9657                 break;
9658         default:
9659                 WARN_ON(1);     /* we need a WARN() */
9660                 break;
9661         }
9662 }
9663
9664 static int tg3_phys_id(struct net_device *dev, u32 data)
9665 {
9666         struct tg3 *tp = netdev_priv(dev);
9667         int i;
9668
9669         if (!netif_running(tp->dev))
9670                 return -EAGAIN;
9671
9672         if (data == 0)
9673                 data = UINT_MAX / 2;
9674
9675         for (i = 0; i < (data * 2); i++) {
9676                 if ((i % 2) == 0)
9677                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9678                                            LED_CTRL_1000MBPS_ON |
9679                                            LED_CTRL_100MBPS_ON |
9680                                            LED_CTRL_10MBPS_ON |
9681                                            LED_CTRL_TRAFFIC_OVERRIDE |
9682                                            LED_CTRL_TRAFFIC_BLINK |
9683                                            LED_CTRL_TRAFFIC_LED);
9684
9685                 else
9686                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9687                                            LED_CTRL_TRAFFIC_OVERRIDE);
9688
9689                 if (msleep_interruptible(500))
9690                         break;
9691         }
9692         tw32(MAC_LED_CTRL, tp->led_ctrl);
9693         return 0;
9694 }
9695
9696 static void tg3_get_ethtool_stats (struct net_device *dev,
9697                                    struct ethtool_stats *estats, u64 *tmp_stats)
9698 {
9699         struct tg3 *tp = netdev_priv(dev);
9700         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9701 }
9702
9703 #define NVRAM_TEST_SIZE 0x100
9704 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9705 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9706 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9707 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9708 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9709
9710 static int tg3_test_nvram(struct tg3 *tp)
9711 {
9712         u32 csum, magic;
9713         __be32 *buf;
9714         int i, j, k, err = 0, size;
9715
9716         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9717                 return 0;
9718
9719         if (tg3_nvram_read(tp, 0, &magic) != 0)
9720                 return -EIO;
9721
9722         if (magic == TG3_EEPROM_MAGIC)
9723                 size = NVRAM_TEST_SIZE;
9724         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9725                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9726                     TG3_EEPROM_SB_FORMAT_1) {
9727                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9728                         case TG3_EEPROM_SB_REVISION_0:
9729                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9730                                 break;
9731                         case TG3_EEPROM_SB_REVISION_2:
9732                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9733                                 break;
9734                         case TG3_EEPROM_SB_REVISION_3:
9735                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9736                                 break;
9737                         default:
9738                                 return 0;
9739                         }
9740                 } else
9741                         return 0;
9742         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9743                 size = NVRAM_SELFBOOT_HW_SIZE;
9744         else
9745                 return -EIO;
9746
9747         buf = kmalloc(size, GFP_KERNEL);
9748         if (buf == NULL)
9749                 return -ENOMEM;
9750
9751         err = -EIO;
9752         for (i = 0, j = 0; i < size; i += 4, j++) {
9753                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9754                 if (err)
9755                         break;
9756         }
9757         if (i < size)
9758                 goto out;
9759
9760         /* Selfboot format */
9761         magic = be32_to_cpu(buf[0]);
9762         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9763             TG3_EEPROM_MAGIC_FW) {
9764                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9765
9766                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9767                     TG3_EEPROM_SB_REVISION_2) {
9768                         /* For rev 2, the csum doesn't include the MBA. */
9769                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9770                                 csum8 += buf8[i];
9771                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9772                                 csum8 += buf8[i];
9773                 } else {
9774                         for (i = 0; i < size; i++)
9775                                 csum8 += buf8[i];
9776                 }
9777
9778                 if (csum8 == 0) {
9779                         err = 0;
9780                         goto out;
9781                 }
9782
9783                 err = -EIO;
9784                 goto out;
9785         }
9786
9787         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9788             TG3_EEPROM_MAGIC_HW) {
9789                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9790                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9791                 u8 *buf8 = (u8 *) buf;
9792
9793                 /* Separate the parity bits and the data bytes.  */
9794                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9795                         if ((i == 0) || (i == 8)) {
9796                                 int l;
9797                                 u8 msk;
9798
9799                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9800                                         parity[k++] = buf8[i] & msk;
9801                                 i++;
9802                         }
9803                         else if (i == 16) {
9804                                 int l;
9805                                 u8 msk;
9806
9807                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9808                                         parity[k++] = buf8[i] & msk;
9809                                 i++;
9810
9811                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9812                                         parity[k++] = buf8[i] & msk;
9813                                 i++;
9814                         }
9815                         data[j++] = buf8[i];
9816                 }
9817
9818                 err = -EIO;
9819                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9820                         u8 hw8 = hweight8(data[i]);
9821
9822                         if ((hw8 & 0x1) && parity[i])
9823                                 goto out;
9824                         else if (!(hw8 & 0x1) && !parity[i])
9825                                 goto out;
9826                 }
9827                 err = 0;
9828                 goto out;
9829         }
9830
9831         /* Bootstrap checksum at offset 0x10 */
9832         csum = calc_crc((unsigned char *) buf, 0x10);
9833         if (csum != be32_to_cpu(buf[0x10/4]))
9834                 goto out;
9835
9836         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9837         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9838         if (csum != be32_to_cpu(buf[0xfc/4]))
9839                 goto out;
9840
9841         err = 0;
9842
9843 out:
9844         kfree(buf);
9845         return err;
9846 }
9847
9848 #define TG3_SERDES_TIMEOUT_SEC  2
9849 #define TG3_COPPER_TIMEOUT_SEC  6
9850
9851 static int tg3_test_link(struct tg3 *tp)
9852 {
9853         int i, max;
9854
9855         if (!netif_running(tp->dev))
9856                 return -ENODEV;
9857
9858         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9859                 max = TG3_SERDES_TIMEOUT_SEC;
9860         else
9861                 max = TG3_COPPER_TIMEOUT_SEC;
9862
9863         for (i = 0; i < max; i++) {
9864                 if (netif_carrier_ok(tp->dev))
9865                         return 0;
9866
9867                 if (msleep_interruptible(1000))
9868                         break;
9869         }
9870
9871         return -EIO;
9872 }
9873
9874 /* Only test the commonly used registers */
9875 static int tg3_test_registers(struct tg3 *tp)
9876 {
9877         int i, is_5705, is_5750;
9878         u32 offset, read_mask, write_mask, val, save_val, read_val;
9879         static struct {
9880                 u16 offset;
9881                 u16 flags;
9882 #define TG3_FL_5705     0x1
9883 #define TG3_FL_NOT_5705 0x2
9884 #define TG3_FL_NOT_5788 0x4
9885 #define TG3_FL_NOT_5750 0x8
9886                 u32 read_mask;
9887                 u32 write_mask;
9888         } reg_tbl[] = {
9889                 /* MAC Control Registers */
9890                 { MAC_MODE, TG3_FL_NOT_5705,
9891                         0x00000000, 0x00ef6f8c },
9892                 { MAC_MODE, TG3_FL_5705,
9893                         0x00000000, 0x01ef6b8c },
9894                 { MAC_STATUS, TG3_FL_NOT_5705,
9895                         0x03800107, 0x00000000 },
9896                 { MAC_STATUS, TG3_FL_5705,
9897                         0x03800100, 0x00000000 },
9898                 { MAC_ADDR_0_HIGH, 0x0000,
9899                         0x00000000, 0x0000ffff },
9900                 { MAC_ADDR_0_LOW, 0x0000,
9901                         0x00000000, 0xffffffff },
9902                 { MAC_RX_MTU_SIZE, 0x0000,
9903                         0x00000000, 0x0000ffff },
9904                 { MAC_TX_MODE, 0x0000,
9905                         0x00000000, 0x00000070 },
9906                 { MAC_TX_LENGTHS, 0x0000,
9907                         0x00000000, 0x00003fff },
9908                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9909                         0x00000000, 0x000007fc },
9910                 { MAC_RX_MODE, TG3_FL_5705,
9911                         0x00000000, 0x000007dc },
9912                 { MAC_HASH_REG_0, 0x0000,
9913                         0x00000000, 0xffffffff },
9914                 { MAC_HASH_REG_1, 0x0000,
9915                         0x00000000, 0xffffffff },
9916                 { MAC_HASH_REG_2, 0x0000,
9917                         0x00000000, 0xffffffff },
9918                 { MAC_HASH_REG_3, 0x0000,
9919                         0x00000000, 0xffffffff },
9920
9921                 /* Receive Data and Receive BD Initiator Control Registers. */
9922                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9923                         0x00000000, 0xffffffff },
9924                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9925                         0x00000000, 0xffffffff },
9926                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9927                         0x00000000, 0x00000003 },
9928                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9929                         0x00000000, 0xffffffff },
9930                 { RCVDBDI_STD_BD+0, 0x0000,
9931                         0x00000000, 0xffffffff },
9932                 { RCVDBDI_STD_BD+4, 0x0000,
9933                         0x00000000, 0xffffffff },
9934                 { RCVDBDI_STD_BD+8, 0x0000,
9935                         0x00000000, 0xffff0002 },
9936                 { RCVDBDI_STD_BD+0xc, 0x0000,
9937                         0x00000000, 0xffffffff },
9938
9939                 /* Receive BD Initiator Control Registers. */
9940                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9941                         0x00000000, 0xffffffff },
9942                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9943                         0x00000000, 0x000003ff },
9944                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9945                         0x00000000, 0xffffffff },
9946
9947                 /* Host Coalescing Control Registers. */
9948                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9949                         0x00000000, 0x00000004 },
9950                 { HOSTCC_MODE, TG3_FL_5705,
9951                         0x00000000, 0x000000f6 },
9952                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9953                         0x00000000, 0xffffffff },
9954                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9955                         0x00000000, 0x000003ff },
9956                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9957                         0x00000000, 0xffffffff },
9958                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9959                         0x00000000, 0x000003ff },
9960                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9961                         0x00000000, 0xffffffff },
9962                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9963                         0x00000000, 0x000000ff },
9964                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9965                         0x00000000, 0xffffffff },
9966                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9967                         0x00000000, 0x000000ff },
9968                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9969                         0x00000000, 0xffffffff },
9970                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9971                         0x00000000, 0xffffffff },
9972                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9973                         0x00000000, 0xffffffff },
9974                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9975                         0x00000000, 0x000000ff },
9976                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9977                         0x00000000, 0xffffffff },
9978                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9979                         0x00000000, 0x000000ff },
9980                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9981                         0x00000000, 0xffffffff },
9982                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9983                         0x00000000, 0xffffffff },
9984                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9985                         0x00000000, 0xffffffff },
9986                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9987                         0x00000000, 0xffffffff },
9988                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9989                         0x00000000, 0xffffffff },
9990                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9991                         0xffffffff, 0x00000000 },
9992                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9993                         0xffffffff, 0x00000000 },
9994
9995                 /* Buffer Manager Control Registers. */
9996                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9997                         0x00000000, 0x007fff80 },
9998                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9999                         0x00000000, 0x007fffff },
10000                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10001                         0x00000000, 0x0000003f },
10002                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10003                         0x00000000, 0x000001ff },
10004                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10005                         0x00000000, 0x000001ff },
10006                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10007                         0xffffffff, 0x00000000 },
10008                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10009                         0xffffffff, 0x00000000 },
10010
10011                 /* Mailbox Registers */
10012                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10013                         0x00000000, 0x000001ff },
10014                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10015                         0x00000000, 0x000001ff },
10016                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10017                         0x00000000, 0x000007ff },
10018                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10019                         0x00000000, 0x000001ff },
10020
10021                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10022         };
10023
10024         is_5705 = is_5750 = 0;
10025         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10026                 is_5705 = 1;
10027                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10028                         is_5750 = 1;
10029         }
10030
10031         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10032                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10033                         continue;
10034
10035                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10036                         continue;
10037
10038                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10039                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10040                         continue;
10041
10042                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10043                         continue;
10044
10045                 offset = (u32) reg_tbl[i].offset;
10046                 read_mask = reg_tbl[i].read_mask;
10047                 write_mask = reg_tbl[i].write_mask;
10048
10049                 /* Save the original register content */
10050                 save_val = tr32(offset);
10051
10052                 /* Determine the read-only value. */
10053                 read_val = save_val & read_mask;
10054
10055                 /* Write zero to the register, then make sure the read-only bits
10056                  * are not changed and the read/write bits are all zeros.
10057                  */
10058                 tw32(offset, 0);
10059
10060                 val = tr32(offset);
10061
10062                 /* Test the read-only and read/write bits. */
10063                 if (((val & read_mask) != read_val) || (val & write_mask))
10064                         goto out;
10065
10066                 /* Write ones to all the bits defined by RdMask and WrMask, then
10067                  * make sure the read-only bits are not changed and the
10068                  * read/write bits are all ones.
10069                  */
10070                 tw32(offset, read_mask | write_mask);
10071
10072                 val = tr32(offset);
10073
10074                 /* Test the read-only bits. */
10075                 if ((val & read_mask) != read_val)
10076                         goto out;
10077
10078                 /* Test the read/write bits. */
10079                 if ((val & write_mask) != write_mask)
10080                         goto out;
10081
10082                 tw32(offset, save_val);
10083         }
10084
10085         return 0;
10086
10087 out:
10088         if (netif_msg_hw(tp))
10089                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10090                        offset);
10091         tw32(offset, save_val);
10092         return -EIO;
10093 }
10094
10095 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10096 {
10097         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10098         int i;
10099         u32 j;
10100
10101         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10102                 for (j = 0; j < len; j += 4) {
10103                         u32 val;
10104
10105                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10106                         tg3_read_mem(tp, offset + j, &val);
10107                         if (val != test_pattern[i])
10108                                 return -EIO;
10109                 }
10110         }
10111         return 0;
10112 }
10113
10114 static int tg3_test_memory(struct tg3 *tp)
10115 {
10116         static struct mem_entry {
10117                 u32 offset;
10118                 u32 len;
10119         } mem_tbl_570x[] = {
10120                 { 0x00000000, 0x00b50},
10121                 { 0x00002000, 0x1c000},
10122                 { 0xffffffff, 0x00000}
10123         }, mem_tbl_5705[] = {
10124                 { 0x00000100, 0x0000c},
10125                 { 0x00000200, 0x00008},
10126                 { 0x00004000, 0x00800},
10127                 { 0x00006000, 0x01000},
10128                 { 0x00008000, 0x02000},
10129                 { 0x00010000, 0x0e000},
10130                 { 0xffffffff, 0x00000}
10131         }, mem_tbl_5755[] = {
10132                 { 0x00000200, 0x00008},
10133                 { 0x00004000, 0x00800},
10134                 { 0x00006000, 0x00800},
10135                 { 0x00008000, 0x02000},
10136                 { 0x00010000, 0x0c000},
10137                 { 0xffffffff, 0x00000}
10138         }, mem_tbl_5906[] = {
10139                 { 0x00000200, 0x00008},
10140                 { 0x00004000, 0x00400},
10141                 { 0x00006000, 0x00400},
10142                 { 0x00008000, 0x01000},
10143                 { 0x00010000, 0x01000},
10144                 { 0xffffffff, 0x00000}
10145         };
10146         struct mem_entry *mem_tbl;
10147         int err = 0;
10148         int i;
10149
10150         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10151                 mem_tbl = mem_tbl_5755;
10152         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10153                 mem_tbl = mem_tbl_5906;
10154         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10155                 mem_tbl = mem_tbl_5705;
10156         else
10157                 mem_tbl = mem_tbl_570x;
10158
10159         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10160                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10161                     mem_tbl[i].len)) != 0)
10162                         break;
10163         }
10164
10165         return err;
10166 }
10167
10168 #define TG3_MAC_LOOPBACK        0
10169 #define TG3_PHY_LOOPBACK        1
10170
10171 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10172 {
10173         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10174         u32 desc_idx, coal_now;
10175         struct sk_buff *skb, *rx_skb;
10176         u8 *tx_data;
10177         dma_addr_t map;
10178         int num_pkts, tx_len, rx_len, i, err;
10179         struct tg3_rx_buffer_desc *desc;
10180         struct tg3_napi *tnapi, *rnapi;
10181         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10182
10183         if (tp->irq_cnt > 1) {
10184                 tnapi = &tp->napi[1];
10185                 rnapi = &tp->napi[1];
10186         } else {
10187                 tnapi = &tp->napi[0];
10188                 rnapi = &tp->napi[0];
10189         }
10190         coal_now = tnapi->coal_now | rnapi->coal_now;
10191
10192         if (loopback_mode == TG3_MAC_LOOPBACK) {
10193                 /* HW errata - mac loopback fails in some cases on 5780.
10194                  * Normal traffic and PHY loopback are not affected by
10195                  * errata.
10196                  */
10197                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10198                         return 0;
10199
10200                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10201                            MAC_MODE_PORT_INT_LPBACK;
10202                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10203                         mac_mode |= MAC_MODE_LINK_POLARITY;
10204                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10205                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10206                 else
10207                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10208                 tw32(MAC_MODE, mac_mode);
10209         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10210                 u32 val;
10211
10212                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10213                         tg3_phy_fet_toggle_apd(tp, false);
10214                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10215                 } else
10216                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10217
10218                 tg3_phy_toggle_automdix(tp, 0);
10219
10220                 tg3_writephy(tp, MII_BMCR, val);
10221                 udelay(40);
10222
10223                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10224                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10225                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10226                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10227                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10228                 } else
10229                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10230
10231                 /* reset to prevent losing 1st rx packet intermittently */
10232                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10233                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10234                         udelay(10);
10235                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10236                 }
10237                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10238                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10239                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10240                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10241                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10242                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10243                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10244                 }
10245                 tw32(MAC_MODE, mac_mode);
10246         }
10247         else
10248                 return -EINVAL;
10249
10250         err = -EIO;
10251
10252         tx_len = 1514;
10253         skb = netdev_alloc_skb(tp->dev, tx_len);
10254         if (!skb)
10255                 return -ENOMEM;
10256
10257         tx_data = skb_put(skb, tx_len);
10258         memcpy(tx_data, tp->dev->dev_addr, 6);
10259         memset(tx_data + 6, 0x0, 8);
10260
10261         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10262
10263         for (i = 14; i < tx_len; i++)
10264                 tx_data[i] = (u8) (i & 0xff);
10265
10266         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10267
10268         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10269                rnapi->coal_now);
10270
10271         udelay(10);
10272
10273         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10274
10275         num_pkts = 0;
10276
10277         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10278
10279         tnapi->tx_prod++;
10280         num_pkts++;
10281
10282         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10283         tr32_mailbox(tnapi->prodmbox);
10284
10285         udelay(10);
10286
10287         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
10288         for (i = 0; i < 25; i++) {
10289                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10290                        coal_now);
10291
10292                 udelay(10);
10293
10294                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10295                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10296                 if ((tx_idx == tnapi->tx_prod) &&
10297                     (rx_idx == (rx_start_idx + num_pkts)))
10298                         break;
10299         }
10300
10301         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10302         dev_kfree_skb(skb);
10303
10304         if (tx_idx != tnapi->tx_prod)
10305                 goto out;
10306
10307         if (rx_idx != rx_start_idx + num_pkts)
10308                 goto out;
10309
10310         desc = &rnapi->rx_rcb[rx_start_idx];
10311         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10312         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10313         if (opaque_key != RXD_OPAQUE_RING_STD)
10314                 goto out;
10315
10316         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10317             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10318                 goto out;
10319
10320         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10321         if (rx_len != tx_len)
10322                 goto out;
10323
10324         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10325
10326         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10327         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10328
10329         for (i = 14; i < tx_len; i++) {
10330                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10331                         goto out;
10332         }
10333         err = 0;
10334
10335         /* tg3_free_rings will unmap and free the rx_skb */
10336 out:
10337         return err;
10338 }
10339
10340 #define TG3_MAC_LOOPBACK_FAILED         1
10341 #define TG3_PHY_LOOPBACK_FAILED         2
10342 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10343                                          TG3_PHY_LOOPBACK_FAILED)
10344
10345 static int tg3_test_loopback(struct tg3 *tp)
10346 {
10347         int err = 0;
10348         u32 cpmuctrl = 0;
10349
10350         if (!netif_running(tp->dev))
10351                 return TG3_LOOPBACK_FAILED;
10352
10353         err = tg3_reset_hw(tp, 1);
10354         if (err)
10355                 return TG3_LOOPBACK_FAILED;
10356
10357         /* Turn off gphy autopowerdown. */
10358         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10359                 tg3_phy_toggle_apd(tp, false);
10360
10361         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10362                 int i;
10363                 u32 status;
10364
10365                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10366
10367                 /* Wait for up to 40 microseconds to acquire lock. */
10368                 for (i = 0; i < 4; i++) {
10369                         status = tr32(TG3_CPMU_MUTEX_GNT);
10370                         if (status == CPMU_MUTEX_GNT_DRIVER)
10371                                 break;
10372                         udelay(10);
10373                 }
10374
10375                 if (status != CPMU_MUTEX_GNT_DRIVER)
10376                         return TG3_LOOPBACK_FAILED;
10377
10378                 /* Turn off link-based power management. */
10379                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10380                 tw32(TG3_CPMU_CTRL,
10381                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10382                                   CPMU_CTRL_LINK_AWARE_MODE));
10383         }
10384
10385         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10386                 err |= TG3_MAC_LOOPBACK_FAILED;
10387
10388         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10389                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10390
10391                 /* Release the mutex */
10392                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10393         }
10394
10395         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10396             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10397                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10398                         err |= TG3_PHY_LOOPBACK_FAILED;
10399         }
10400
10401         /* Re-enable gphy autopowerdown. */
10402         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10403                 tg3_phy_toggle_apd(tp, true);
10404
10405         return err;
10406 }
10407
10408 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10409                           u64 *data)
10410 {
10411         struct tg3 *tp = netdev_priv(dev);
10412
10413         if (tp->link_config.phy_is_low_power)
10414                 tg3_set_power_state(tp, PCI_D0);
10415
10416         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10417
10418         if (tg3_test_nvram(tp) != 0) {
10419                 etest->flags |= ETH_TEST_FL_FAILED;
10420                 data[0] = 1;
10421         }
10422         if (tg3_test_link(tp) != 0) {
10423                 etest->flags |= ETH_TEST_FL_FAILED;
10424                 data[1] = 1;
10425         }
10426         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10427                 int err, err2 = 0, irq_sync = 0;
10428
10429                 if (netif_running(dev)) {
10430                         tg3_phy_stop(tp);
10431                         tg3_netif_stop(tp);
10432                         irq_sync = 1;
10433                 }
10434
10435                 tg3_full_lock(tp, irq_sync);
10436
10437                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10438                 err = tg3_nvram_lock(tp);
10439                 tg3_halt_cpu(tp, RX_CPU_BASE);
10440                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10441                         tg3_halt_cpu(tp, TX_CPU_BASE);
10442                 if (!err)
10443                         tg3_nvram_unlock(tp);
10444
10445                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10446                         tg3_phy_reset(tp);
10447
10448                 if (tg3_test_registers(tp) != 0) {
10449                         etest->flags |= ETH_TEST_FL_FAILED;
10450                         data[2] = 1;
10451                 }
10452                 if (tg3_test_memory(tp) != 0) {
10453                         etest->flags |= ETH_TEST_FL_FAILED;
10454                         data[3] = 1;
10455                 }
10456                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10457                         etest->flags |= ETH_TEST_FL_FAILED;
10458
10459                 tg3_full_unlock(tp);
10460
10461                 if (tg3_test_interrupt(tp) != 0) {
10462                         etest->flags |= ETH_TEST_FL_FAILED;
10463                         data[5] = 1;
10464                 }
10465
10466                 tg3_full_lock(tp, 0);
10467
10468                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10469                 if (netif_running(dev)) {
10470                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10471                         err2 = tg3_restart_hw(tp, 1);
10472                         if (!err2)
10473                                 tg3_netif_start(tp);
10474                 }
10475
10476                 tg3_full_unlock(tp);
10477
10478                 if (irq_sync && !err2)
10479                         tg3_phy_start(tp);
10480         }
10481         if (tp->link_config.phy_is_low_power)
10482                 tg3_set_power_state(tp, PCI_D3hot);
10483
10484 }
10485
10486 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10487 {
10488         struct mii_ioctl_data *data = if_mii(ifr);
10489         struct tg3 *tp = netdev_priv(dev);
10490         int err;
10491
10492         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10493                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10494                         return -EAGAIN;
10495                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10496         }
10497
10498         switch(cmd) {
10499         case SIOCGMIIPHY:
10500                 data->phy_id = PHY_ADDR;
10501
10502                 /* fallthru */
10503         case SIOCGMIIREG: {
10504                 u32 mii_regval;
10505
10506                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10507                         break;                  /* We have no PHY */
10508
10509                 if (tp->link_config.phy_is_low_power)
10510                         return -EAGAIN;
10511
10512                 spin_lock_bh(&tp->lock);
10513                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10514                 spin_unlock_bh(&tp->lock);
10515
10516                 data->val_out = mii_regval;
10517
10518                 return err;
10519         }
10520
10521         case SIOCSMIIREG:
10522                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10523                         break;                  /* We have no PHY */
10524
10525                 if (!capable(CAP_NET_ADMIN))
10526                         return -EPERM;
10527
10528                 if (tp->link_config.phy_is_low_power)
10529                         return -EAGAIN;
10530
10531                 spin_lock_bh(&tp->lock);
10532                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10533                 spin_unlock_bh(&tp->lock);
10534
10535                 return err;
10536
10537         default:
10538                 /* do nothing */
10539                 break;
10540         }
10541         return -EOPNOTSUPP;
10542 }
10543
10544 #if TG3_VLAN_TAG_USED
10545 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10546 {
10547         struct tg3 *tp = netdev_priv(dev);
10548
10549         if (!netif_running(dev)) {
10550                 tp->vlgrp = grp;
10551                 return;
10552         }
10553
10554         tg3_netif_stop(tp);
10555
10556         tg3_full_lock(tp, 0);
10557
10558         tp->vlgrp = grp;
10559
10560         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10561         __tg3_set_rx_mode(dev);
10562
10563         tg3_netif_start(tp);
10564
10565         tg3_full_unlock(tp);
10566 }
10567 #endif
10568
10569 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10570 {
10571         struct tg3 *tp = netdev_priv(dev);
10572
10573         memcpy(ec, &tp->coal, sizeof(*ec));
10574         return 0;
10575 }
10576
10577 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10578 {
10579         struct tg3 *tp = netdev_priv(dev);
10580         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10581         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10582
10583         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10584                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10585                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10586                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10587                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10588         }
10589
10590         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10591             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10592             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10593             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10594             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10595             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10596             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10597             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10598             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10599             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10600                 return -EINVAL;
10601
10602         /* No rx interrupts will be generated if both are zero */
10603         if ((ec->rx_coalesce_usecs == 0) &&
10604             (ec->rx_max_coalesced_frames == 0))
10605                 return -EINVAL;
10606
10607         /* No tx interrupts will be generated if both are zero */
10608         if ((ec->tx_coalesce_usecs == 0) &&
10609             (ec->tx_max_coalesced_frames == 0))
10610                 return -EINVAL;
10611
10612         /* Only copy relevant parameters, ignore all others. */
10613         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10614         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10615         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10616         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10617         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10618         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10619         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10620         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10621         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10622
10623         if (netif_running(dev)) {
10624                 tg3_full_lock(tp, 0);
10625                 __tg3_set_coalesce(tp, &tp->coal);
10626                 tg3_full_unlock(tp);
10627         }
10628         return 0;
10629 }
10630
10631 static const struct ethtool_ops tg3_ethtool_ops = {
10632         .get_settings           = tg3_get_settings,
10633         .set_settings           = tg3_set_settings,
10634         .get_drvinfo            = tg3_get_drvinfo,
10635         .get_regs_len           = tg3_get_regs_len,
10636         .get_regs               = tg3_get_regs,
10637         .get_wol                = tg3_get_wol,
10638         .set_wol                = tg3_set_wol,
10639         .get_msglevel           = tg3_get_msglevel,
10640         .set_msglevel           = tg3_set_msglevel,
10641         .nway_reset             = tg3_nway_reset,
10642         .get_link               = ethtool_op_get_link,
10643         .get_eeprom_len         = tg3_get_eeprom_len,
10644         .get_eeprom             = tg3_get_eeprom,
10645         .set_eeprom             = tg3_set_eeprom,
10646         .get_ringparam          = tg3_get_ringparam,
10647         .set_ringparam          = tg3_set_ringparam,
10648         .get_pauseparam         = tg3_get_pauseparam,
10649         .set_pauseparam         = tg3_set_pauseparam,
10650         .get_rx_csum            = tg3_get_rx_csum,
10651         .set_rx_csum            = tg3_set_rx_csum,
10652         .set_tx_csum            = tg3_set_tx_csum,
10653         .set_sg                 = ethtool_op_set_sg,
10654         .set_tso                = tg3_set_tso,
10655         .self_test              = tg3_self_test,
10656         .get_strings            = tg3_get_strings,
10657         .phys_id                = tg3_phys_id,
10658         .get_ethtool_stats      = tg3_get_ethtool_stats,
10659         .get_coalesce           = tg3_get_coalesce,
10660         .set_coalesce           = tg3_set_coalesce,
10661         .get_sset_count         = tg3_get_sset_count,
10662 };
10663
10664 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10665 {
10666         u32 cursize, val, magic;
10667
10668         tp->nvram_size = EEPROM_CHIP_SIZE;
10669
10670         if (tg3_nvram_read(tp, 0, &magic) != 0)
10671                 return;
10672
10673         if ((magic != TG3_EEPROM_MAGIC) &&
10674             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10675             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10676                 return;
10677
10678         /*
10679          * Size the chip by reading offsets at increasing powers of two.
10680          * When we encounter our validation signature, we know the addressing
10681          * has wrapped around, and thus have our chip size.
10682          */
10683         cursize = 0x10;
10684
10685         while (cursize < tp->nvram_size) {
10686                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10687                         return;
10688
10689                 if (val == magic)
10690                         break;
10691
10692                 cursize <<= 1;
10693         }
10694
10695         tp->nvram_size = cursize;
10696 }
10697
10698 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10699 {
10700         u32 val;
10701
10702         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10703             tg3_nvram_read(tp, 0, &val) != 0)
10704                 return;
10705
10706         /* Selfboot format */
10707         if (val != TG3_EEPROM_MAGIC) {
10708                 tg3_get_eeprom_size(tp);
10709                 return;
10710         }
10711
10712         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10713                 if (val != 0) {
10714                         /* This is confusing.  We want to operate on the
10715                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10716                          * call will read from NVRAM and byteswap the data
10717                          * according to the byteswapping settings for all
10718                          * other register accesses.  This ensures the data we
10719                          * want will always reside in the lower 16-bits.
10720                          * However, the data in NVRAM is in LE format, which
10721                          * means the data from the NVRAM read will always be
10722                          * opposite the endianness of the CPU.  The 16-bit
10723                          * byteswap then brings the data to CPU endianness.
10724                          */
10725                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10726                         return;
10727                 }
10728         }
10729         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10730 }
10731
10732 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10733 {
10734         u32 nvcfg1;
10735
10736         nvcfg1 = tr32(NVRAM_CFG1);
10737         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10738                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10739         } else {
10740                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10741                 tw32(NVRAM_CFG1, nvcfg1);
10742         }
10743
10744         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10745             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10746                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10747                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10748                         tp->nvram_jedecnum = JEDEC_ATMEL;
10749                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10750                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10751                         break;
10752                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10753                         tp->nvram_jedecnum = JEDEC_ATMEL;
10754                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10755                         break;
10756                 case FLASH_VENDOR_ATMEL_EEPROM:
10757                         tp->nvram_jedecnum = JEDEC_ATMEL;
10758                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10759                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10760                         break;
10761                 case FLASH_VENDOR_ST:
10762                         tp->nvram_jedecnum = JEDEC_ST;
10763                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10764                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10765                         break;
10766                 case FLASH_VENDOR_SAIFUN:
10767                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10768                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10769                         break;
10770                 case FLASH_VENDOR_SST_SMALL:
10771                 case FLASH_VENDOR_SST_LARGE:
10772                         tp->nvram_jedecnum = JEDEC_SST;
10773                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10774                         break;
10775                 }
10776         } else {
10777                 tp->nvram_jedecnum = JEDEC_ATMEL;
10778                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10779                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10780         }
10781 }
10782
10783 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10784 {
10785         u32 nvcfg1;
10786
10787         nvcfg1 = tr32(NVRAM_CFG1);
10788
10789         /* NVRAM protection for TPM */
10790         if (nvcfg1 & (1 << 27))
10791                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10792
10793         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10794         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10795         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10796                 tp->nvram_jedecnum = JEDEC_ATMEL;
10797                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10798                 break;
10799         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10800                 tp->nvram_jedecnum = JEDEC_ATMEL;
10801                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10802                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10803                 break;
10804         case FLASH_5752VENDOR_ST_M45PE10:
10805         case FLASH_5752VENDOR_ST_M45PE20:
10806         case FLASH_5752VENDOR_ST_M45PE40:
10807                 tp->nvram_jedecnum = JEDEC_ST;
10808                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10809                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10810                 break;
10811         }
10812
10813         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10814                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10815                 case FLASH_5752PAGE_SIZE_256:
10816                         tp->nvram_pagesize = 256;
10817                         break;
10818                 case FLASH_5752PAGE_SIZE_512:
10819                         tp->nvram_pagesize = 512;
10820                         break;
10821                 case FLASH_5752PAGE_SIZE_1K:
10822                         tp->nvram_pagesize = 1024;
10823                         break;
10824                 case FLASH_5752PAGE_SIZE_2K:
10825                         tp->nvram_pagesize = 2048;
10826                         break;
10827                 case FLASH_5752PAGE_SIZE_4K:
10828                         tp->nvram_pagesize = 4096;
10829                         break;
10830                 case FLASH_5752PAGE_SIZE_264:
10831                         tp->nvram_pagesize = 264;
10832                         break;
10833                 }
10834         } else {
10835                 /* For eeprom, set pagesize to maximum eeprom size */
10836                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10837
10838                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10839                 tw32(NVRAM_CFG1, nvcfg1);
10840         }
10841 }
10842
10843 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10844 {
10845         u32 nvcfg1, protect = 0;
10846
10847         nvcfg1 = tr32(NVRAM_CFG1);
10848
10849         /* NVRAM protection for TPM */
10850         if (nvcfg1 & (1 << 27)) {
10851                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10852                 protect = 1;
10853         }
10854
10855         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10856         switch (nvcfg1) {
10857         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10858         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10859         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10860         case FLASH_5755VENDOR_ATMEL_FLASH_5:
10861                 tp->nvram_jedecnum = JEDEC_ATMEL;
10862                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10863                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10864                 tp->nvram_pagesize = 264;
10865                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10866                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10867                         tp->nvram_size = (protect ? 0x3e200 :
10868                                           TG3_NVRAM_SIZE_512KB);
10869                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10870                         tp->nvram_size = (protect ? 0x1f200 :
10871                                           TG3_NVRAM_SIZE_256KB);
10872                 else
10873                         tp->nvram_size = (protect ? 0x1f200 :
10874                                           TG3_NVRAM_SIZE_128KB);
10875                 break;
10876         case FLASH_5752VENDOR_ST_M45PE10:
10877         case FLASH_5752VENDOR_ST_M45PE20:
10878         case FLASH_5752VENDOR_ST_M45PE40:
10879                 tp->nvram_jedecnum = JEDEC_ST;
10880                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10881                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10882                 tp->nvram_pagesize = 256;
10883                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10884                         tp->nvram_size = (protect ?
10885                                           TG3_NVRAM_SIZE_64KB :
10886                                           TG3_NVRAM_SIZE_128KB);
10887                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10888                         tp->nvram_size = (protect ?
10889                                           TG3_NVRAM_SIZE_64KB :
10890                                           TG3_NVRAM_SIZE_256KB);
10891                 else
10892                         tp->nvram_size = (protect ?
10893                                           TG3_NVRAM_SIZE_128KB :
10894                                           TG3_NVRAM_SIZE_512KB);
10895                 break;
10896         }
10897 }
10898
10899 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10900 {
10901         u32 nvcfg1;
10902
10903         nvcfg1 = tr32(NVRAM_CFG1);
10904
10905         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10906         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10907         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10908         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10909         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10910                 tp->nvram_jedecnum = JEDEC_ATMEL;
10911                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10912                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10913
10914                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10915                 tw32(NVRAM_CFG1, nvcfg1);
10916                 break;
10917         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10918         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10919         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10920         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10921                 tp->nvram_jedecnum = JEDEC_ATMEL;
10922                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10923                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10924                 tp->nvram_pagesize = 264;
10925                 break;
10926         case FLASH_5752VENDOR_ST_M45PE10:
10927         case FLASH_5752VENDOR_ST_M45PE20:
10928         case FLASH_5752VENDOR_ST_M45PE40:
10929                 tp->nvram_jedecnum = JEDEC_ST;
10930                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10931                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10932                 tp->nvram_pagesize = 256;
10933                 break;
10934         }
10935 }
10936
10937 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10938 {
10939         u32 nvcfg1, protect = 0;
10940
10941         nvcfg1 = tr32(NVRAM_CFG1);
10942
10943         /* NVRAM protection for TPM */
10944         if (nvcfg1 & (1 << 27)) {
10945                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10946                 protect = 1;
10947         }
10948
10949         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10950         switch (nvcfg1) {
10951         case FLASH_5761VENDOR_ATMEL_ADB021D:
10952         case FLASH_5761VENDOR_ATMEL_ADB041D:
10953         case FLASH_5761VENDOR_ATMEL_ADB081D:
10954         case FLASH_5761VENDOR_ATMEL_ADB161D:
10955         case FLASH_5761VENDOR_ATMEL_MDB021D:
10956         case FLASH_5761VENDOR_ATMEL_MDB041D:
10957         case FLASH_5761VENDOR_ATMEL_MDB081D:
10958         case FLASH_5761VENDOR_ATMEL_MDB161D:
10959                 tp->nvram_jedecnum = JEDEC_ATMEL;
10960                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10961                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10962                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10963                 tp->nvram_pagesize = 256;
10964                 break;
10965         case FLASH_5761VENDOR_ST_A_M45PE20:
10966         case FLASH_5761VENDOR_ST_A_M45PE40:
10967         case FLASH_5761VENDOR_ST_A_M45PE80:
10968         case FLASH_5761VENDOR_ST_A_M45PE16:
10969         case FLASH_5761VENDOR_ST_M_M45PE20:
10970         case FLASH_5761VENDOR_ST_M_M45PE40:
10971         case FLASH_5761VENDOR_ST_M_M45PE80:
10972         case FLASH_5761VENDOR_ST_M_M45PE16:
10973                 tp->nvram_jedecnum = JEDEC_ST;
10974                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10975                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10976                 tp->nvram_pagesize = 256;
10977                 break;
10978         }
10979
10980         if (protect) {
10981                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10982         } else {
10983                 switch (nvcfg1) {
10984                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10985                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10986                 case FLASH_5761VENDOR_ST_A_M45PE16:
10987                 case FLASH_5761VENDOR_ST_M_M45PE16:
10988                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10989                         break;
10990                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10991                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10992                 case FLASH_5761VENDOR_ST_A_M45PE80:
10993                 case FLASH_5761VENDOR_ST_M_M45PE80:
10994                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10995                         break;
10996                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10997                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10998                 case FLASH_5761VENDOR_ST_A_M45PE40:
10999                 case FLASH_5761VENDOR_ST_M_M45PE40:
11000                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11001                         break;
11002                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11003                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11004                 case FLASH_5761VENDOR_ST_A_M45PE20:
11005                 case FLASH_5761VENDOR_ST_M_M45PE20:
11006                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11007                         break;
11008                 }
11009         }
11010 }
11011
11012 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11013 {
11014         tp->nvram_jedecnum = JEDEC_ATMEL;
11015         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11016         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11017 }
11018
11019 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11020 {
11021         u32 nvcfg1;
11022
11023         nvcfg1 = tr32(NVRAM_CFG1);
11024
11025         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11026         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11027         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11028                 tp->nvram_jedecnum = JEDEC_ATMEL;
11029                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11030                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11031
11032                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11033                 tw32(NVRAM_CFG1, nvcfg1);
11034                 return;
11035         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11036         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11037         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11038         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11039         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11040         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11041         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11042                 tp->nvram_jedecnum = JEDEC_ATMEL;
11043                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11044                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11045
11046                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11047                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11048                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11049                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11050                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11051                         break;
11052                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11053                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11054                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11055                         break;
11056                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11057                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11058                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11059                         break;
11060                 }
11061                 break;
11062         case FLASH_5752VENDOR_ST_M45PE10:
11063         case FLASH_5752VENDOR_ST_M45PE20:
11064         case FLASH_5752VENDOR_ST_M45PE40:
11065                 tp->nvram_jedecnum = JEDEC_ST;
11066                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11067                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11068
11069                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11070                 case FLASH_5752VENDOR_ST_M45PE10:
11071                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11072                         break;
11073                 case FLASH_5752VENDOR_ST_M45PE20:
11074                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11075                         break;
11076                 case FLASH_5752VENDOR_ST_M45PE40:
11077                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11078                         break;
11079                 }
11080                 break;
11081         default:
11082                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11083                 return;
11084         }
11085
11086         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11087         case FLASH_5752PAGE_SIZE_256:
11088                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11089                 tp->nvram_pagesize = 256;
11090                 break;
11091         case FLASH_5752PAGE_SIZE_512:
11092                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11093                 tp->nvram_pagesize = 512;
11094                 break;
11095         case FLASH_5752PAGE_SIZE_1K:
11096                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11097                 tp->nvram_pagesize = 1024;
11098                 break;
11099         case FLASH_5752PAGE_SIZE_2K:
11100                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11101                 tp->nvram_pagesize = 2048;
11102                 break;
11103         case FLASH_5752PAGE_SIZE_4K:
11104                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11105                 tp->nvram_pagesize = 4096;
11106                 break;
11107         case FLASH_5752PAGE_SIZE_264:
11108                 tp->nvram_pagesize = 264;
11109                 break;
11110         case FLASH_5752PAGE_SIZE_528:
11111                 tp->nvram_pagesize = 528;
11112                 break;
11113         }
11114 }
11115
11116 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11117 static void __devinit tg3_nvram_init(struct tg3 *tp)
11118 {
11119         tw32_f(GRC_EEPROM_ADDR,
11120              (EEPROM_ADDR_FSM_RESET |
11121               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11122                EEPROM_ADDR_CLKPERD_SHIFT)));
11123
11124         msleep(1);
11125
11126         /* Enable seeprom accesses. */
11127         tw32_f(GRC_LOCAL_CTRL,
11128              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11129         udelay(100);
11130
11131         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11132             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11133                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11134
11135                 if (tg3_nvram_lock(tp)) {
11136                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11137                                "tg3_nvram_init failed.\n", tp->dev->name);
11138                         return;
11139                 }
11140                 tg3_enable_nvram_access(tp);
11141
11142                 tp->nvram_size = 0;
11143
11144                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11145                         tg3_get_5752_nvram_info(tp);
11146                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11147                         tg3_get_5755_nvram_info(tp);
11148                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11149                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11150                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11151                         tg3_get_5787_nvram_info(tp);
11152                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11153                         tg3_get_5761_nvram_info(tp);
11154                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11155                         tg3_get_5906_nvram_info(tp);
11156                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11157                         tg3_get_57780_nvram_info(tp);
11158                 else
11159                         tg3_get_nvram_info(tp);
11160
11161                 if (tp->nvram_size == 0)
11162                         tg3_get_nvram_size(tp);
11163
11164                 tg3_disable_nvram_access(tp);
11165                 tg3_nvram_unlock(tp);
11166
11167         } else {
11168                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11169
11170                 tg3_get_eeprom_size(tp);
11171         }
11172 }
11173
11174 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11175                                     u32 offset, u32 len, u8 *buf)
11176 {
11177         int i, j, rc = 0;
11178         u32 val;
11179
11180         for (i = 0; i < len; i += 4) {
11181                 u32 addr;
11182                 __be32 data;
11183
11184                 addr = offset + i;
11185
11186                 memcpy(&data, buf + i, 4);
11187
11188                 /*
11189                  * The SEEPROM interface expects the data to always be opposite
11190                  * the native endian format.  We accomplish this by reversing
11191                  * all the operations that would have been performed on the
11192                  * data from a call to tg3_nvram_read_be32().
11193                  */
11194                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11195
11196                 val = tr32(GRC_EEPROM_ADDR);
11197                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11198
11199                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11200                         EEPROM_ADDR_READ);
11201                 tw32(GRC_EEPROM_ADDR, val |
11202                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11203                         (addr & EEPROM_ADDR_ADDR_MASK) |
11204                         EEPROM_ADDR_START |
11205                         EEPROM_ADDR_WRITE);
11206
11207                 for (j = 0; j < 1000; j++) {
11208                         val = tr32(GRC_EEPROM_ADDR);
11209
11210                         if (val & EEPROM_ADDR_COMPLETE)
11211                                 break;
11212                         msleep(1);
11213                 }
11214                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11215                         rc = -EBUSY;
11216                         break;
11217                 }
11218         }
11219
11220         return rc;
11221 }
11222
11223 /* offset and length are dword aligned */
11224 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11225                 u8 *buf)
11226 {
11227         int ret = 0;
11228         u32 pagesize = tp->nvram_pagesize;
11229         u32 pagemask = pagesize - 1;
11230         u32 nvram_cmd;
11231         u8 *tmp;
11232
11233         tmp = kmalloc(pagesize, GFP_KERNEL);
11234         if (tmp == NULL)
11235                 return -ENOMEM;
11236
11237         while (len) {
11238                 int j;
11239                 u32 phy_addr, page_off, size;
11240
11241                 phy_addr = offset & ~pagemask;
11242
11243                 for (j = 0; j < pagesize; j += 4) {
11244                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11245                                                   (__be32 *) (tmp + j));
11246                         if (ret)
11247                                 break;
11248                 }
11249                 if (ret)
11250                         break;
11251
11252                 page_off = offset & pagemask;
11253                 size = pagesize;
11254                 if (len < size)
11255                         size = len;
11256
11257                 len -= size;
11258
11259                 memcpy(tmp + page_off, buf, size);
11260
11261                 offset = offset + (pagesize - page_off);
11262
11263                 tg3_enable_nvram_access(tp);
11264
11265                 /*
11266                  * Before we can erase the flash page, we need
11267                  * to issue a special "write enable" command.
11268                  */
11269                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11270
11271                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11272                         break;
11273
11274                 /* Erase the target page */
11275                 tw32(NVRAM_ADDR, phy_addr);
11276
11277                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11278                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11279
11280                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11281                         break;
11282
11283                 /* Issue another write enable to start the write. */
11284                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11285
11286                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11287                         break;
11288
11289                 for (j = 0; j < pagesize; j += 4) {
11290                         __be32 data;
11291
11292                         data = *((__be32 *) (tmp + j));
11293
11294                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11295
11296                         tw32(NVRAM_ADDR, phy_addr + j);
11297
11298                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11299                                 NVRAM_CMD_WR;
11300
11301                         if (j == 0)
11302                                 nvram_cmd |= NVRAM_CMD_FIRST;
11303                         else if (j == (pagesize - 4))
11304                                 nvram_cmd |= NVRAM_CMD_LAST;
11305
11306                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11307                                 break;
11308                 }
11309                 if (ret)
11310                         break;
11311         }
11312
11313         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11314         tg3_nvram_exec_cmd(tp, nvram_cmd);
11315
11316         kfree(tmp);
11317
11318         return ret;
11319 }
11320
11321 /* offset and length are dword aligned */
11322 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11323                 u8 *buf)
11324 {
11325         int i, ret = 0;
11326
11327         for (i = 0; i < len; i += 4, offset += 4) {
11328                 u32 page_off, phy_addr, nvram_cmd;
11329                 __be32 data;
11330
11331                 memcpy(&data, buf + i, 4);
11332                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11333
11334                 page_off = offset % tp->nvram_pagesize;
11335
11336                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11337
11338                 tw32(NVRAM_ADDR, phy_addr);
11339
11340                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11341
11342                 if ((page_off == 0) || (i == 0))
11343                         nvram_cmd |= NVRAM_CMD_FIRST;
11344                 if (page_off == (tp->nvram_pagesize - 4))
11345                         nvram_cmd |= NVRAM_CMD_LAST;
11346
11347                 if (i == (len - 4))
11348                         nvram_cmd |= NVRAM_CMD_LAST;
11349
11350                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11351                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11352                     (tp->nvram_jedecnum == JEDEC_ST) &&
11353                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11354
11355                         if ((ret = tg3_nvram_exec_cmd(tp,
11356                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11357                                 NVRAM_CMD_DONE)))
11358
11359                                 break;
11360                 }
11361                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11362                         /* We always do complete word writes to eeprom. */
11363                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11364                 }
11365
11366                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11367                         break;
11368         }
11369         return ret;
11370 }
11371
11372 /* offset and length are dword aligned */
11373 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11374 {
11375         int ret;
11376
11377         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11378                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11379                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11380                 udelay(40);
11381         }
11382
11383         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11384                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11385         }
11386         else {
11387                 u32 grc_mode;
11388
11389                 ret = tg3_nvram_lock(tp);
11390                 if (ret)
11391                         return ret;
11392
11393                 tg3_enable_nvram_access(tp);
11394                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11395                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11396                         tw32(NVRAM_WRITE1, 0x406);
11397
11398                 grc_mode = tr32(GRC_MODE);
11399                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11400
11401                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11402                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11403
11404                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11405                                 buf);
11406                 }
11407                 else {
11408                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11409                                 buf);
11410                 }
11411
11412                 grc_mode = tr32(GRC_MODE);
11413                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11414
11415                 tg3_disable_nvram_access(tp);
11416                 tg3_nvram_unlock(tp);
11417         }
11418
11419         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11420                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11421                 udelay(40);
11422         }
11423
11424         return ret;
11425 }
11426
11427 struct subsys_tbl_ent {
11428         u16 subsys_vendor, subsys_devid;
11429         u32 phy_id;
11430 };
11431
11432 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11433         /* Broadcom boards. */
11434         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11435         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11436         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11437         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11438         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11439         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11440         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11441         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11442         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11443         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11444         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11445
11446         /* 3com boards. */
11447         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11448         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11449         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11450         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11451         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11452
11453         /* DELL boards. */
11454         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11455         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11456         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11457         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11458
11459         /* Compaq boards. */
11460         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11461         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11462         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11463         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11464         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11465
11466         /* IBM boards. */
11467         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11468 };
11469
11470 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11471 {
11472         int i;
11473
11474         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11475                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11476                      tp->pdev->subsystem_vendor) &&
11477                     (subsys_id_to_phy_id[i].subsys_devid ==
11478                      tp->pdev->subsystem_device))
11479                         return &subsys_id_to_phy_id[i];
11480         }
11481         return NULL;
11482 }
11483
11484 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11485 {
11486         u32 val;
11487         u16 pmcsr;
11488
11489         /* On some early chips the SRAM cannot be accessed in D3hot state,
11490          * so need make sure we're in D0.
11491          */
11492         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11493         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11494         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11495         msleep(1);
11496
11497         /* Make sure register accesses (indirect or otherwise)
11498          * will function correctly.
11499          */
11500         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11501                                tp->misc_host_ctrl);
11502
11503         /* The memory arbiter has to be enabled in order for SRAM accesses
11504          * to succeed.  Normally on powerup the tg3 chip firmware will make
11505          * sure it is enabled, but other entities such as system netboot
11506          * code might disable it.
11507          */
11508         val = tr32(MEMARB_MODE);
11509         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11510
11511         tp->phy_id = PHY_ID_INVALID;
11512         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11513
11514         /* Assume an onboard device and WOL capable by default.  */
11515         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11516
11517         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11518                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11519                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11520                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11521                 }
11522                 val = tr32(VCPU_CFGSHDW);
11523                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11524                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11525                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11526                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11527                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11528                 goto done;
11529         }
11530
11531         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11532         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11533                 u32 nic_cfg, led_cfg;
11534                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11535                 int eeprom_phy_serdes = 0;
11536
11537                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11538                 tp->nic_sram_data_cfg = nic_cfg;
11539
11540                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11541                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11542                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11543                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11544                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11545                     (ver > 0) && (ver < 0x100))
11546                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11547
11548                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11549                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11550
11551                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11552                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11553                         eeprom_phy_serdes = 1;
11554
11555                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11556                 if (nic_phy_id != 0) {
11557                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11558                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11559
11560                         eeprom_phy_id  = (id1 >> 16) << 10;
11561                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11562                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11563                 } else
11564                         eeprom_phy_id = 0;
11565
11566                 tp->phy_id = eeprom_phy_id;
11567                 if (eeprom_phy_serdes) {
11568                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11569                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11570                         else
11571                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11572                 }
11573
11574                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11575                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11576                                     SHASTA_EXT_LED_MODE_MASK);
11577                 else
11578                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11579
11580                 switch (led_cfg) {
11581                 default:
11582                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11583                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11584                         break;
11585
11586                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11587                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11588                         break;
11589
11590                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11591                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11592
11593                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11594                          * read on some older 5700/5701 bootcode.
11595                          */
11596                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11597                             ASIC_REV_5700 ||
11598                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11599                             ASIC_REV_5701)
11600                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11601
11602                         break;
11603
11604                 case SHASTA_EXT_LED_SHARED:
11605                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11606                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11607                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11608                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11609                                                  LED_CTRL_MODE_PHY_2);
11610                         break;
11611
11612                 case SHASTA_EXT_LED_MAC:
11613                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11614                         break;
11615
11616                 case SHASTA_EXT_LED_COMBO:
11617                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11618                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11619                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11620                                                  LED_CTRL_MODE_PHY_2);
11621                         break;
11622
11623                 }
11624
11625                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11626                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11627                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11628                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11629
11630                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11631                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11632
11633                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11634                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11635                         if ((tp->pdev->subsystem_vendor ==
11636                              PCI_VENDOR_ID_ARIMA) &&
11637                             (tp->pdev->subsystem_device == 0x205a ||
11638                              tp->pdev->subsystem_device == 0x2063))
11639                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11640                 } else {
11641                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11642                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11643                 }
11644
11645                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11646                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11647                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11648                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11649                 }
11650
11651                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11652                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11653                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11654
11655                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11656                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11657                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11658
11659                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11660                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11661                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11662
11663                 if (cfg2 & (1 << 17))
11664                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11665
11666                 /* serdes signal pre-emphasis in register 0x590 set by */
11667                 /* bootcode if bit 18 is set */
11668                 if (cfg2 & (1 << 18))
11669                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11670
11671                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11672                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11673                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11674                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11675
11676                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11677                         u32 cfg3;
11678
11679                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11680                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11681                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11682                 }
11683
11684                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11685                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11686                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11687                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11688                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11689                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11690         }
11691 done:
11692         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11693         device_set_wakeup_enable(&tp->pdev->dev,
11694                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11695 }
11696
11697 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11698 {
11699         int i;
11700         u32 val;
11701
11702         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11703         tw32(OTP_CTRL, cmd);
11704
11705         /* Wait for up to 1 ms for command to execute. */
11706         for (i = 0; i < 100; i++) {
11707                 val = tr32(OTP_STATUS);
11708                 if (val & OTP_STATUS_CMD_DONE)
11709                         break;
11710                 udelay(10);
11711         }
11712
11713         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11714 }
11715
11716 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11717  * configuration is a 32-bit value that straddles the alignment boundary.
11718  * We do two 32-bit reads and then shift and merge the results.
11719  */
11720 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11721 {
11722         u32 bhalf_otp, thalf_otp;
11723
11724         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11725
11726         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11727                 return 0;
11728
11729         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11730
11731         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11732                 return 0;
11733
11734         thalf_otp = tr32(OTP_READ_DATA);
11735
11736         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11737
11738         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11739                 return 0;
11740
11741         bhalf_otp = tr32(OTP_READ_DATA);
11742
11743         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11744 }
11745
11746 static int __devinit tg3_phy_probe(struct tg3 *tp)
11747 {
11748         u32 hw_phy_id_1, hw_phy_id_2;
11749         u32 hw_phy_id, hw_phy_id_masked;
11750         int err;
11751
11752         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11753                 return tg3_phy_init(tp);
11754
11755         /* Reading the PHY ID register can conflict with ASF
11756          * firmware access to the PHY hardware.
11757          */
11758         err = 0;
11759         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11760             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11761                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11762         } else {
11763                 /* Now read the physical PHY_ID from the chip and verify
11764                  * that it is sane.  If it doesn't look good, we fall back
11765                  * to either the hard-coded table based PHY_ID and failing
11766                  * that the value found in the eeprom area.
11767                  */
11768                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11769                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11770
11771                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11772                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11773                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11774
11775                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11776         }
11777
11778         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11779                 tp->phy_id = hw_phy_id;
11780                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11781                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11782                 else
11783                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11784         } else {
11785                 if (tp->phy_id != PHY_ID_INVALID) {
11786                         /* Do nothing, phy ID already set up in
11787                          * tg3_get_eeprom_hw_cfg().
11788                          */
11789                 } else {
11790                         struct subsys_tbl_ent *p;
11791
11792                         /* No eeprom signature?  Try the hardcoded
11793                          * subsys device table.
11794                          */
11795                         p = lookup_by_subsys(tp);
11796                         if (!p)
11797                                 return -ENODEV;
11798
11799                         tp->phy_id = p->phy_id;
11800                         if (!tp->phy_id ||
11801                             tp->phy_id == PHY_ID_BCM8002)
11802                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11803                 }
11804         }
11805
11806         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11807             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11808             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11809                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11810
11811                 tg3_readphy(tp, MII_BMSR, &bmsr);
11812                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11813                     (bmsr & BMSR_LSTATUS))
11814                         goto skip_phy_reset;
11815
11816                 err = tg3_phy_reset(tp);
11817                 if (err)
11818                         return err;
11819
11820                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11821                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11822                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11823                 tg3_ctrl = 0;
11824                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11825                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11826                                     MII_TG3_CTRL_ADV_1000_FULL);
11827                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11828                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11829                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11830                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11831                 }
11832
11833                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11834                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11835                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11836                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11837                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11838
11839                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11840                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11841
11842                         tg3_writephy(tp, MII_BMCR,
11843                                      BMCR_ANENABLE | BMCR_ANRESTART);
11844                 }
11845                 tg3_phy_set_wirespeed(tp);
11846
11847                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11848                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11849                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11850         }
11851
11852 skip_phy_reset:
11853         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11854                 err = tg3_init_5401phy_dsp(tp);
11855                 if (err)
11856                         return err;
11857         }
11858
11859         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11860                 err = tg3_init_5401phy_dsp(tp);
11861         }
11862
11863         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11864                 tp->link_config.advertising =
11865                         (ADVERTISED_1000baseT_Half |
11866                          ADVERTISED_1000baseT_Full |
11867                          ADVERTISED_Autoneg |
11868                          ADVERTISED_FIBRE);
11869         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11870                 tp->link_config.advertising &=
11871                         ~(ADVERTISED_1000baseT_Half |
11872                           ADVERTISED_1000baseT_Full);
11873
11874         return err;
11875 }
11876
11877 static void __devinit tg3_read_partno(struct tg3 *tp)
11878 {
11879         unsigned char vpd_data[256];   /* in little-endian format */
11880         unsigned int i;
11881         u32 magic;
11882
11883         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11884             tg3_nvram_read(tp, 0x0, &magic))
11885                 goto out_not_found;
11886
11887         if (magic == TG3_EEPROM_MAGIC) {
11888                 for (i = 0; i < 256; i += 4) {
11889                         u32 tmp;
11890
11891                         /* The data is in little-endian format in NVRAM.
11892                          * Use the big-endian read routines to preserve
11893                          * the byte order as it exists in NVRAM.
11894                          */
11895                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11896                                 goto out_not_found;
11897
11898                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11899                 }
11900         } else {
11901                 int vpd_cap;
11902
11903                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11904                 for (i = 0; i < 256; i += 4) {
11905                         u32 tmp, j = 0;
11906                         __le32 v;
11907                         u16 tmp16;
11908
11909                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11910                                               i);
11911                         while (j++ < 100) {
11912                                 pci_read_config_word(tp->pdev, vpd_cap +
11913                                                      PCI_VPD_ADDR, &tmp16);
11914                                 if (tmp16 & 0x8000)
11915                                         break;
11916                                 msleep(1);
11917                         }
11918                         if (!(tmp16 & 0x8000))
11919                                 goto out_not_found;
11920
11921                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11922                                               &tmp);
11923                         v = cpu_to_le32(tmp);
11924                         memcpy(&vpd_data[i], &v, sizeof(v));
11925                 }
11926         }
11927
11928         /* Now parse and find the part number. */
11929         for (i = 0; i < 254; ) {
11930                 unsigned char val = vpd_data[i];
11931                 unsigned int block_end;
11932
11933                 if (val == 0x82 || val == 0x91) {
11934                         i = (i + 3 +
11935                              (vpd_data[i + 1] +
11936                               (vpd_data[i + 2] << 8)));
11937                         continue;
11938                 }
11939
11940                 if (val != 0x90)
11941                         goto out_not_found;
11942
11943                 block_end = (i + 3 +
11944                              (vpd_data[i + 1] +
11945                               (vpd_data[i + 2] << 8)));
11946                 i += 3;
11947
11948                 if (block_end > 256)
11949                         goto out_not_found;
11950
11951                 while (i < (block_end - 2)) {
11952                         if (vpd_data[i + 0] == 'P' &&
11953                             vpd_data[i + 1] == 'N') {
11954                                 int partno_len = vpd_data[i + 2];
11955
11956                                 i += 3;
11957                                 if (partno_len > 24 || (partno_len + i) > 256)
11958                                         goto out_not_found;
11959
11960                                 memcpy(tp->board_part_number,
11961                                        &vpd_data[i], partno_len);
11962
11963                                 /* Success. */
11964                                 return;
11965                         }
11966                         i += 3 + vpd_data[i + 2];
11967                 }
11968
11969                 /* Part number not found. */
11970                 goto out_not_found;
11971         }
11972
11973 out_not_found:
11974         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11975                 strcpy(tp->board_part_number, "BCM95906");
11976         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11977                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11978                 strcpy(tp->board_part_number, "BCM57780");
11979         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11980                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11981                 strcpy(tp->board_part_number, "BCM57760");
11982         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11983                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11984                 strcpy(tp->board_part_number, "BCM57790");
11985         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11986                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11987                 strcpy(tp->board_part_number, "BCM57788");
11988         else
11989                 strcpy(tp->board_part_number, "none");
11990 }
11991
11992 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11993 {
11994         u32 val;
11995
11996         if (tg3_nvram_read(tp, offset, &val) ||
11997             (val & 0xfc000000) != 0x0c000000 ||
11998             tg3_nvram_read(tp, offset + 4, &val) ||
11999             val != 0)
12000                 return 0;
12001
12002         return 1;
12003 }
12004
12005 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12006 {
12007         u32 val, offset, start, ver_offset;
12008         int i;
12009         bool newver = false;
12010
12011         if (tg3_nvram_read(tp, 0xc, &offset) ||
12012             tg3_nvram_read(tp, 0x4, &start))
12013                 return;
12014
12015         offset = tg3_nvram_logical_addr(tp, offset);
12016
12017         if (tg3_nvram_read(tp, offset, &val))
12018                 return;
12019
12020         if ((val & 0xfc000000) == 0x0c000000) {
12021                 if (tg3_nvram_read(tp, offset + 4, &val))
12022                         return;
12023
12024                 if (val == 0)
12025                         newver = true;
12026         }
12027
12028         if (newver) {
12029                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12030                         return;
12031
12032                 offset = offset + ver_offset - start;
12033                 for (i = 0; i < 16; i += 4) {
12034                         __be32 v;
12035                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12036                                 return;
12037
12038                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12039                 }
12040         } else {
12041                 u32 major, minor;
12042
12043                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12044                         return;
12045
12046                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12047                         TG3_NVM_BCVER_MAJSFT;
12048                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12049                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12050         }
12051 }
12052
12053 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12054 {
12055         u32 val, major, minor;
12056
12057         /* Use native endian representation */
12058         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12059                 return;
12060
12061         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12062                 TG3_NVM_HWSB_CFG1_MAJSFT;
12063         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12064                 TG3_NVM_HWSB_CFG1_MINSFT;
12065
12066         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12067 }
12068
12069 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12070 {
12071         u32 offset, major, minor, build;
12072
12073         tp->fw_ver[0] = 's';
12074         tp->fw_ver[1] = 'b';
12075         tp->fw_ver[2] = '\0';
12076
12077         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12078                 return;
12079
12080         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12081         case TG3_EEPROM_SB_REVISION_0:
12082                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12083                 break;
12084         case TG3_EEPROM_SB_REVISION_2:
12085                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12086                 break;
12087         case TG3_EEPROM_SB_REVISION_3:
12088                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12089                 break;
12090         default:
12091                 return;
12092         }
12093
12094         if (tg3_nvram_read(tp, offset, &val))
12095                 return;
12096
12097         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12098                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12099         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12100                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12101         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12102
12103         if (minor > 99 || build > 26)
12104                 return;
12105
12106         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12107
12108         if (build > 0) {
12109                 tp->fw_ver[8] = 'a' + build - 1;
12110                 tp->fw_ver[9] = '\0';
12111         }
12112 }
12113
12114 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12115 {
12116         u32 val, offset, start;
12117         int i, vlen;
12118
12119         for (offset = TG3_NVM_DIR_START;
12120              offset < TG3_NVM_DIR_END;
12121              offset += TG3_NVM_DIRENT_SIZE) {
12122                 if (tg3_nvram_read(tp, offset, &val))
12123                         return;
12124
12125                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12126                         break;
12127         }
12128
12129         if (offset == TG3_NVM_DIR_END)
12130                 return;
12131
12132         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12133                 start = 0x08000000;
12134         else if (tg3_nvram_read(tp, offset - 4, &start))
12135                 return;
12136
12137         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12138             !tg3_fw_img_is_valid(tp, offset) ||
12139             tg3_nvram_read(tp, offset + 8, &val))
12140                 return;
12141
12142         offset += val - start;
12143
12144         vlen = strlen(tp->fw_ver);
12145
12146         tp->fw_ver[vlen++] = ',';
12147         tp->fw_ver[vlen++] = ' ';
12148
12149         for (i = 0; i < 4; i++) {
12150                 __be32 v;
12151                 if (tg3_nvram_read_be32(tp, offset, &v))
12152                         return;
12153
12154                 offset += sizeof(v);
12155
12156                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12157                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12158                         break;
12159                 }
12160
12161                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12162                 vlen += sizeof(v);
12163         }
12164 }
12165
12166 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12167 {
12168         int vlen;
12169         u32 apedata;
12170
12171         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12172             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12173                 return;
12174
12175         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12176         if (apedata != APE_SEG_SIG_MAGIC)
12177                 return;
12178
12179         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12180         if (!(apedata & APE_FW_STATUS_READY))
12181                 return;
12182
12183         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12184
12185         vlen = strlen(tp->fw_ver);
12186
12187         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12188                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12189                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12190                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12191                  (apedata & APE_FW_VERSION_BLDMSK));
12192 }
12193
12194 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12195 {
12196         u32 val;
12197
12198         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12199                 tp->fw_ver[0] = 's';
12200                 tp->fw_ver[1] = 'b';
12201                 tp->fw_ver[2] = '\0';
12202
12203                 return;
12204         }
12205
12206         if (tg3_nvram_read(tp, 0, &val))
12207                 return;
12208
12209         if (val == TG3_EEPROM_MAGIC)
12210                 tg3_read_bc_ver(tp);
12211         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12212                 tg3_read_sb_ver(tp, val);
12213         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12214                 tg3_read_hwsb_ver(tp);
12215         else
12216                 return;
12217
12218         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12219              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12220                 return;
12221
12222         tg3_read_mgmtfw_ver(tp);
12223
12224         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12225 }
12226
12227 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12228
12229 static int __devinit tg3_get_invariants(struct tg3 *tp)
12230 {
12231         static struct pci_device_id write_reorder_chipsets[] = {
12232                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12233                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12234                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12235                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12236                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12237                              PCI_DEVICE_ID_VIA_8385_0) },
12238                 { },
12239         };
12240         u32 misc_ctrl_reg;
12241         u32 pci_state_reg, grc_misc_cfg;
12242         u32 val;
12243         u16 pci_cmd;
12244         int err;
12245
12246         /* Force memory write invalidate off.  If we leave it on,
12247          * then on 5700_BX chips we have to enable a workaround.
12248          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12249          * to match the cacheline size.  The Broadcom driver have this
12250          * workaround but turns MWI off all the times so never uses
12251          * it.  This seems to suggest that the workaround is insufficient.
12252          */
12253         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12254         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12255         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12256
12257         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12258          * has the register indirect write enable bit set before
12259          * we try to access any of the MMIO registers.  It is also
12260          * critical that the PCI-X hw workaround situation is decided
12261          * before that as well.
12262          */
12263         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12264                               &misc_ctrl_reg);
12265
12266         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12267                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12268         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12269                 u32 prod_id_asic_rev;
12270
12271                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12272                                       &prod_id_asic_rev);
12273                 tp->pci_chip_rev_id = prod_id_asic_rev;
12274         }
12275
12276         /* Wrong chip ID in 5752 A0. This code can be removed later
12277          * as A0 is not in production.
12278          */
12279         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12280                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12281
12282         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12283          * we need to disable memory and use config. cycles
12284          * only to access all registers. The 5702/03 chips
12285          * can mistakenly decode the special cycles from the
12286          * ICH chipsets as memory write cycles, causing corruption
12287          * of register and memory space. Only certain ICH bridges
12288          * will drive special cycles with non-zero data during the
12289          * address phase which can fall within the 5703's address
12290          * range. This is not an ICH bug as the PCI spec allows
12291          * non-zero address during special cycles. However, only
12292          * these ICH bridges are known to drive non-zero addresses
12293          * during special cycles.
12294          *
12295          * Since special cycles do not cross PCI bridges, we only
12296          * enable this workaround if the 5703 is on the secondary
12297          * bus of these ICH bridges.
12298          */
12299         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12300             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12301                 static struct tg3_dev_id {
12302                         u32     vendor;
12303                         u32     device;
12304                         u32     rev;
12305                 } ich_chipsets[] = {
12306                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12307                           PCI_ANY_ID },
12308                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12309                           PCI_ANY_ID },
12310                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12311                           0xa },
12312                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12313                           PCI_ANY_ID },
12314                         { },
12315                 };
12316                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12317                 struct pci_dev *bridge = NULL;
12318
12319                 while (pci_id->vendor != 0) {
12320                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12321                                                 bridge);
12322                         if (!bridge) {
12323                                 pci_id++;
12324                                 continue;
12325                         }
12326                         if (pci_id->rev != PCI_ANY_ID) {
12327                                 if (bridge->revision > pci_id->rev)
12328                                         continue;
12329                         }
12330                         if (bridge->subordinate &&
12331                             (bridge->subordinate->number ==
12332                              tp->pdev->bus->number)) {
12333
12334                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12335                                 pci_dev_put(bridge);
12336                                 break;
12337                         }
12338                 }
12339         }
12340
12341         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12342                 static struct tg3_dev_id {
12343                         u32     vendor;
12344                         u32     device;
12345                 } bridge_chipsets[] = {
12346                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12347                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12348                         { },
12349                 };
12350                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12351                 struct pci_dev *bridge = NULL;
12352
12353                 while (pci_id->vendor != 0) {
12354                         bridge = pci_get_device(pci_id->vendor,
12355                                                 pci_id->device,
12356                                                 bridge);
12357                         if (!bridge) {
12358                                 pci_id++;
12359                                 continue;
12360                         }
12361                         if (bridge->subordinate &&
12362                             (bridge->subordinate->number <=
12363                              tp->pdev->bus->number) &&
12364                             (bridge->subordinate->subordinate >=
12365                              tp->pdev->bus->number)) {
12366                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12367                                 pci_dev_put(bridge);
12368                                 break;
12369                         }
12370                 }
12371         }
12372
12373         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12374          * DMA addresses > 40-bit. This bridge may have other additional
12375          * 57xx devices behind it in some 4-port NIC designs for example.
12376          * Any tg3 device found behind the bridge will also need the 40-bit
12377          * DMA workaround.
12378          */
12379         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12380             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12381                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12382                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12383                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12384         }
12385         else {
12386                 struct pci_dev *bridge = NULL;
12387
12388                 do {
12389                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12390                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12391                                                 bridge);
12392                         if (bridge && bridge->subordinate &&
12393                             (bridge->subordinate->number <=
12394                              tp->pdev->bus->number) &&
12395                             (bridge->subordinate->subordinate >=
12396                              tp->pdev->bus->number)) {
12397                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12398                                 pci_dev_put(bridge);
12399                                 break;
12400                         }
12401                 } while (bridge);
12402         }
12403
12404         /* Initialize misc host control in PCI block. */
12405         tp->misc_host_ctrl |= (misc_ctrl_reg &
12406                                MISC_HOST_CTRL_CHIPREV);
12407         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12408                                tp->misc_host_ctrl);
12409
12410         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12411             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12412                 tp->pdev_peer = tg3_find_peer(tp);
12413
12414         /* Intentionally exclude ASIC_REV_5906 */
12415         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12416             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12417             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12418             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12419             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12420             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12421                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12422
12423         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12424             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12425             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12426             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12427             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12428                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12429
12430         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12431             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12432                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12433
12434         /* 5700 B0 chips do not support checksumming correctly due
12435          * to hardware bugs.
12436          */
12437         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12438                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12439         else {
12440                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12441                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12442                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12443                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12444         }
12445
12446         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12447                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12448                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12449                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12450                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12451                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12452                      tp->pdev_peer == tp->pdev))
12453                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12454
12455                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12456                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12457                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12458                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12459                 } else {
12460                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12461                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12462                                 ASIC_REV_5750 &&
12463                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12464                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12465                 }
12466         }
12467
12468         tp->irq_max = 1;
12469
12470         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12471              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12472                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12473
12474         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12475                               &pci_state_reg);
12476
12477         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12478         if (tp->pcie_cap != 0) {
12479                 u16 lnkctl;
12480
12481                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12482
12483                 pcie_set_readrq(tp->pdev, 4096);
12484
12485                 pci_read_config_word(tp->pdev,
12486                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12487                                      &lnkctl);
12488                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12489                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12490                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12491                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12492                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12493                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12494                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12495                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12496                 }
12497         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12498                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12499         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12500                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12501                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12502                 if (!tp->pcix_cap) {
12503                         printk(KERN_ERR PFX "Cannot find PCI-X "
12504                                             "capability, aborting.\n");
12505                         return -EIO;
12506                 }
12507
12508                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12509                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12510         }
12511
12512         /* If we have an AMD 762 or VIA K8T800 chipset, write
12513          * reordering to the mailbox registers done by the host
12514          * controller can cause major troubles.  We read back from
12515          * every mailbox register write to force the writes to be
12516          * posted to the chip in order.
12517          */
12518         if (pci_dev_present(write_reorder_chipsets) &&
12519             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12520                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12521
12522         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12523                              &tp->pci_cacheline_sz);
12524         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12525                              &tp->pci_lat_timer);
12526         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12527             tp->pci_lat_timer < 64) {
12528                 tp->pci_lat_timer = 64;
12529                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12530                                       tp->pci_lat_timer);
12531         }
12532
12533         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12534                 /* 5700 BX chips need to have their TX producer index
12535                  * mailboxes written twice to workaround a bug.
12536                  */
12537                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12538
12539                 /* If we are in PCI-X mode, enable register write workaround.
12540                  *
12541                  * The workaround is to use indirect register accesses
12542                  * for all chip writes not to mailbox registers.
12543                  */
12544                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12545                         u32 pm_reg;
12546
12547                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12548
12549                         /* The chip can have it's power management PCI config
12550                          * space registers clobbered due to this bug.
12551                          * So explicitly force the chip into D0 here.
12552                          */
12553                         pci_read_config_dword(tp->pdev,
12554                                               tp->pm_cap + PCI_PM_CTRL,
12555                                               &pm_reg);
12556                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12557                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12558                         pci_write_config_dword(tp->pdev,
12559                                                tp->pm_cap + PCI_PM_CTRL,
12560                                                pm_reg);
12561
12562                         /* Also, force SERR#/PERR# in PCI command. */
12563                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12564                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12565                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12566                 }
12567         }
12568
12569         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12570                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12571         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12572                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12573
12574         /* Chip-specific fixup from Broadcom driver */
12575         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12576             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12577                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12578                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12579         }
12580
12581         /* Default fast path register access methods */
12582         tp->read32 = tg3_read32;
12583         tp->write32 = tg3_write32;
12584         tp->read32_mbox = tg3_read32;
12585         tp->write32_mbox = tg3_write32;
12586         tp->write32_tx_mbox = tg3_write32;
12587         tp->write32_rx_mbox = tg3_write32;
12588
12589         /* Various workaround register access methods */
12590         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12591                 tp->write32 = tg3_write_indirect_reg32;
12592         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12593                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12594                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12595                 /*
12596                  * Back to back register writes can cause problems on these
12597                  * chips, the workaround is to read back all reg writes
12598                  * except those to mailbox regs.
12599                  *
12600                  * See tg3_write_indirect_reg32().
12601                  */
12602                 tp->write32 = tg3_write_flush_reg32;
12603         }
12604
12605
12606         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12607             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12608                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12609                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12610                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12611         }
12612
12613         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12614                 tp->read32 = tg3_read_indirect_reg32;
12615                 tp->write32 = tg3_write_indirect_reg32;
12616                 tp->read32_mbox = tg3_read_indirect_mbox;
12617                 tp->write32_mbox = tg3_write_indirect_mbox;
12618                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12619                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12620
12621                 iounmap(tp->regs);
12622                 tp->regs = NULL;
12623
12624                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12625                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12626                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12627         }
12628         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12629                 tp->read32_mbox = tg3_read32_mbox_5906;
12630                 tp->write32_mbox = tg3_write32_mbox_5906;
12631                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12632                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12633         }
12634
12635         if (tp->write32 == tg3_write_indirect_reg32 ||
12636             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12637              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12638               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12639                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12640
12641         /* Get eeprom hw config before calling tg3_set_power_state().
12642          * In particular, the TG3_FLG2_IS_NIC flag must be
12643          * determined before calling tg3_set_power_state() so that
12644          * we know whether or not to switch out of Vaux power.
12645          * When the flag is set, it means that GPIO1 is used for eeprom
12646          * write protect and also implies that it is a LOM where GPIOs
12647          * are not used to switch power.
12648          */
12649         tg3_get_eeprom_hw_cfg(tp);
12650
12651         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12652                 /* Allow reads and writes to the
12653                  * APE register and memory space.
12654                  */
12655                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12656                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12657                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12658                                        pci_state_reg);
12659         }
12660
12661         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12662             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12663             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12664             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12665                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12666
12667         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12668          * GPIO1 driven high will bring 5700's external PHY out of reset.
12669          * It is also used as eeprom write protect on LOMs.
12670          */
12671         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12672         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12673             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12674                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12675                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12676         /* Unused GPIO3 must be driven as output on 5752 because there
12677          * are no pull-up resistors on unused GPIO pins.
12678          */
12679         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12680                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12681
12682         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12683             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12684                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12685
12686         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12687             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12688                 /* Turn off the debug UART. */
12689                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12690                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12691                         /* Keep VMain power. */
12692                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12693                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12694         }
12695
12696         /* Force the chip into D0. */
12697         err = tg3_set_power_state(tp, PCI_D0);
12698         if (err) {
12699                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12700                        pci_name(tp->pdev));
12701                 return err;
12702         }
12703
12704         /* Derive initial jumbo mode from MTU assigned in
12705          * ether_setup() via the alloc_etherdev() call
12706          */
12707         if (tp->dev->mtu > ETH_DATA_LEN &&
12708             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12709                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12710
12711         /* Determine WakeOnLan speed to use. */
12712         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12713             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12714             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12715             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12716                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12717         } else {
12718                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12719         }
12720
12721         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12722                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12723
12724         /* A few boards don't want Ethernet@WireSpeed phy feature */
12725         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12726             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12727              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12728              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12729             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12730             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12731                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12732
12733         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12734             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12735                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12736         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12737                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12738
12739         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12740             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12741             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12742             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12743                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12744                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12745                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12746                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12747                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12748                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12749                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12750                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12751                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12752                 } else
12753                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12754         }
12755
12756         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12757             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12758                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12759                 if (tp->phy_otp == 0)
12760                         tp->phy_otp = TG3_OTP_DEFAULT;
12761         }
12762
12763         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12764                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12765         else
12766                 tp->mi_mode = MAC_MI_MODE_BASE;
12767
12768         tp->coalesce_mode = 0;
12769         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12770             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12771                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12772
12773         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12774             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12775                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12776
12777         if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12778              tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12779             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12780                 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12781
12782         err = tg3_mdio_init(tp);
12783         if (err)
12784                 return err;
12785
12786         /* Initialize data/descriptor byte/word swapping. */
12787         val = tr32(GRC_MODE);
12788         val &= GRC_MODE_HOST_STACKUP;
12789         tw32(GRC_MODE, val | tp->grc_mode);
12790
12791         tg3_switch_clocks(tp);
12792
12793         /* Clear this out for sanity. */
12794         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12795
12796         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12797                               &pci_state_reg);
12798         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12799             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12800                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12801
12802                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12803                     chiprevid == CHIPREV_ID_5701_B0 ||
12804                     chiprevid == CHIPREV_ID_5701_B2 ||
12805                     chiprevid == CHIPREV_ID_5701_B5) {
12806                         void __iomem *sram_base;
12807
12808                         /* Write some dummy words into the SRAM status block
12809                          * area, see if it reads back correctly.  If the return
12810                          * value is bad, force enable the PCIX workaround.
12811                          */
12812                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12813
12814                         writel(0x00000000, sram_base);
12815                         writel(0x00000000, sram_base + 4);
12816                         writel(0xffffffff, sram_base + 4);
12817                         if (readl(sram_base) != 0x00000000)
12818                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12819                 }
12820         }
12821
12822         udelay(50);
12823         tg3_nvram_init(tp);
12824
12825         grc_misc_cfg = tr32(GRC_MISC_CFG);
12826         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12827
12828         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12829             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12830              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12831                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12832
12833         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12834             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12835                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12836         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12837                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12838                                       HOSTCC_MODE_CLRTICK_TXBD);
12839
12840                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12841                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12842                                        tp->misc_host_ctrl);
12843         }
12844
12845         /* Preserve the APE MAC_MODE bits */
12846         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12847                 tp->mac_mode = tr32(MAC_MODE) |
12848                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12849         else
12850                 tp->mac_mode = TG3_DEF_MAC_MODE;
12851
12852         /* these are limited to 10/100 only */
12853         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12854              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12855             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12856              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12857              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12858               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12859               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12860             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12861              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12862               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12863               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12864             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12865             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
12866                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12867
12868         err = tg3_phy_probe(tp);
12869         if (err) {
12870                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12871                        pci_name(tp->pdev), err);
12872                 /* ... but do not return immediately ... */
12873                 tg3_mdio_fini(tp);
12874         }
12875
12876         tg3_read_partno(tp);
12877         tg3_read_fw_ver(tp);
12878
12879         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12880                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12881         } else {
12882                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12883                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12884                 else
12885                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12886         }
12887
12888         /* 5700 {AX,BX} chips have a broken status block link
12889          * change bit implementation, so we must use the
12890          * status register in those cases.
12891          */
12892         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12893                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12894         else
12895                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12896
12897         /* The led_ctrl is set during tg3_phy_probe, here we might
12898          * have to force the link status polling mechanism based
12899          * upon subsystem IDs.
12900          */
12901         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12902             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12903             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12904                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12905                                   TG3_FLAG_USE_LINKCHG_REG);
12906         }
12907
12908         /* For all SERDES we poll the MAC status register. */
12909         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12910                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12911         else
12912                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12913
12914         tp->rx_offset = NET_IP_ALIGN;
12915         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12916             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12917                 tp->rx_offset = 0;
12918
12919         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12920
12921         /* Increment the rx prod index on the rx std ring by at most
12922          * 8 for these chips to workaround hw errata.
12923          */
12924         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12925             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12926             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12927                 tp->rx_std_max_post = 8;
12928
12929         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12930                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12931                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12932
12933         return err;
12934 }
12935
12936 #ifdef CONFIG_SPARC
12937 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12938 {
12939         struct net_device *dev = tp->dev;
12940         struct pci_dev *pdev = tp->pdev;
12941         struct device_node *dp = pci_device_to_OF_node(pdev);
12942         const unsigned char *addr;
12943         int len;
12944
12945         addr = of_get_property(dp, "local-mac-address", &len);
12946         if (addr && len == 6) {
12947                 memcpy(dev->dev_addr, addr, 6);
12948                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12949                 return 0;
12950         }
12951         return -ENODEV;
12952 }
12953
12954 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12955 {
12956         struct net_device *dev = tp->dev;
12957
12958         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12959         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12960         return 0;
12961 }
12962 #endif
12963
12964 static int __devinit tg3_get_device_address(struct tg3 *tp)
12965 {
12966         struct net_device *dev = tp->dev;
12967         u32 hi, lo, mac_offset;
12968         int addr_ok = 0;
12969
12970 #ifdef CONFIG_SPARC
12971         if (!tg3_get_macaddr_sparc(tp))
12972                 return 0;
12973 #endif
12974
12975         mac_offset = 0x7c;
12976         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12977             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12978                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12979                         mac_offset = 0xcc;
12980                 if (tg3_nvram_lock(tp))
12981                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12982                 else
12983                         tg3_nvram_unlock(tp);
12984         }
12985         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12986                 mac_offset = 0x10;
12987
12988         /* First try to get it from MAC address mailbox. */
12989         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12990         if ((hi >> 16) == 0x484b) {
12991                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12992                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12993
12994                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12995                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12996                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12997                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12998                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12999
13000                 /* Some old bootcode may report a 0 MAC address in SRAM */
13001                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13002         }
13003         if (!addr_ok) {
13004                 /* Next, try NVRAM. */
13005                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13006                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13007                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13008                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13009                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13010                 }
13011                 /* Finally just fetch it out of the MAC control regs. */
13012                 else {
13013                         hi = tr32(MAC_ADDR_0_HIGH);
13014                         lo = tr32(MAC_ADDR_0_LOW);
13015
13016                         dev->dev_addr[5] = lo & 0xff;
13017                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13018                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13019                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13020                         dev->dev_addr[1] = hi & 0xff;
13021                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13022                 }
13023         }
13024
13025         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13026 #ifdef CONFIG_SPARC
13027                 if (!tg3_get_default_macaddr_sparc(tp))
13028                         return 0;
13029 #endif
13030                 return -EINVAL;
13031         }
13032         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13033         return 0;
13034 }
13035
13036 #define BOUNDARY_SINGLE_CACHELINE       1
13037 #define BOUNDARY_MULTI_CACHELINE        2
13038
13039 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13040 {
13041         int cacheline_size;
13042         u8 byte;
13043         int goal;
13044
13045         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13046         if (byte == 0)
13047                 cacheline_size = 1024;
13048         else
13049                 cacheline_size = (int) byte * 4;
13050
13051         /* On 5703 and later chips, the boundary bits have no
13052          * effect.
13053          */
13054         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13055             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13056             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13057                 goto out;
13058
13059 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13060         goal = BOUNDARY_MULTI_CACHELINE;
13061 #else
13062 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13063         goal = BOUNDARY_SINGLE_CACHELINE;
13064 #else
13065         goal = 0;
13066 #endif
13067 #endif
13068
13069         if (!goal)
13070                 goto out;
13071
13072         /* PCI controllers on most RISC systems tend to disconnect
13073          * when a device tries to burst across a cache-line boundary.
13074          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13075          *
13076          * Unfortunately, for PCI-E there are only limited
13077          * write-side controls for this, and thus for reads
13078          * we will still get the disconnects.  We'll also waste
13079          * these PCI cycles for both read and write for chips
13080          * other than 5700 and 5701 which do not implement the
13081          * boundary bits.
13082          */
13083         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13084             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13085                 switch (cacheline_size) {
13086                 case 16:
13087                 case 32:
13088                 case 64:
13089                 case 128:
13090                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13091                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13092                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13093                         } else {
13094                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13095                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13096                         }
13097                         break;
13098
13099                 case 256:
13100                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13101                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13102                         break;
13103
13104                 default:
13105                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13106                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13107                         break;
13108                 }
13109         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13110                 switch (cacheline_size) {
13111                 case 16:
13112                 case 32:
13113                 case 64:
13114                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13115                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13116                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13117                                 break;
13118                         }
13119                         /* fallthrough */
13120                 case 128:
13121                 default:
13122                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13123                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13124                         break;
13125                 }
13126         } else {
13127                 switch (cacheline_size) {
13128                 case 16:
13129                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13130                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13131                                         DMA_RWCTRL_WRITE_BNDRY_16);
13132                                 break;
13133                         }
13134                         /* fallthrough */
13135                 case 32:
13136                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13137                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13138                                         DMA_RWCTRL_WRITE_BNDRY_32);
13139                                 break;
13140                         }
13141                         /* fallthrough */
13142                 case 64:
13143                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13144                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13145                                         DMA_RWCTRL_WRITE_BNDRY_64);
13146                                 break;
13147                         }
13148                         /* fallthrough */
13149                 case 128:
13150                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13151                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13152                                         DMA_RWCTRL_WRITE_BNDRY_128);
13153                                 break;
13154                         }
13155                         /* fallthrough */
13156                 case 256:
13157                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13158                                 DMA_RWCTRL_WRITE_BNDRY_256);
13159                         break;
13160                 case 512:
13161                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13162                                 DMA_RWCTRL_WRITE_BNDRY_512);
13163                         break;
13164                 case 1024:
13165                 default:
13166                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13167                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13168                         break;
13169                 }
13170         }
13171
13172 out:
13173         return val;
13174 }
13175
13176 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13177 {
13178         struct tg3_internal_buffer_desc test_desc;
13179         u32 sram_dma_descs;
13180         int i, ret;
13181
13182         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13183
13184         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13185         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13186         tw32(RDMAC_STATUS, 0);
13187         tw32(WDMAC_STATUS, 0);
13188
13189         tw32(BUFMGR_MODE, 0);
13190         tw32(FTQ_RESET, 0);
13191
13192         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13193         test_desc.addr_lo = buf_dma & 0xffffffff;
13194         test_desc.nic_mbuf = 0x00002100;
13195         test_desc.len = size;
13196
13197         /*
13198          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13199          * the *second* time the tg3 driver was getting loaded after an
13200          * initial scan.
13201          *
13202          * Broadcom tells me:
13203          *   ...the DMA engine is connected to the GRC block and a DMA
13204          *   reset may affect the GRC block in some unpredictable way...
13205          *   The behavior of resets to individual blocks has not been tested.
13206          *
13207          * Broadcom noted the GRC reset will also reset all sub-components.
13208          */
13209         if (to_device) {
13210                 test_desc.cqid_sqid = (13 << 8) | 2;
13211
13212                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13213                 udelay(40);
13214         } else {
13215                 test_desc.cqid_sqid = (16 << 8) | 7;
13216
13217                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13218                 udelay(40);
13219         }
13220         test_desc.flags = 0x00000005;
13221
13222         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13223                 u32 val;
13224
13225                 val = *(((u32 *)&test_desc) + i);
13226                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13227                                        sram_dma_descs + (i * sizeof(u32)));
13228                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13229         }
13230         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13231
13232         if (to_device) {
13233                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13234         } else {
13235                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13236         }
13237
13238         ret = -ENODEV;
13239         for (i = 0; i < 40; i++) {
13240                 u32 val;
13241
13242                 if (to_device)
13243                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13244                 else
13245                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13246                 if ((val & 0xffff) == sram_dma_descs) {
13247                         ret = 0;
13248                         break;
13249                 }
13250
13251                 udelay(100);
13252         }
13253
13254         return ret;
13255 }
13256
13257 #define TEST_BUFFER_SIZE        0x2000
13258
13259 static int __devinit tg3_test_dma(struct tg3 *tp)
13260 {
13261         dma_addr_t buf_dma;
13262         u32 *buf, saved_dma_rwctrl;
13263         int ret;
13264
13265         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13266         if (!buf) {
13267                 ret = -ENOMEM;
13268                 goto out_nofree;
13269         }
13270
13271         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13272                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13273
13274         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13275
13276         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13277                 /* DMA read watermark not used on PCIE */
13278                 tp->dma_rwctrl |= 0x00180000;
13279         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13280                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13281                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13282                         tp->dma_rwctrl |= 0x003f0000;
13283                 else
13284                         tp->dma_rwctrl |= 0x003f000f;
13285         } else {
13286                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13287                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13288                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13289                         u32 read_water = 0x7;
13290
13291                         /* If the 5704 is behind the EPB bridge, we can
13292                          * do the less restrictive ONE_DMA workaround for
13293                          * better performance.
13294                          */
13295                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13296                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13297                                 tp->dma_rwctrl |= 0x8000;
13298                         else if (ccval == 0x6 || ccval == 0x7)
13299                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13300
13301                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13302                                 read_water = 4;
13303                         /* Set bit 23 to enable PCIX hw bug fix */
13304                         tp->dma_rwctrl |=
13305                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13306                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13307                                 (1 << 23);
13308                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13309                         /* 5780 always in PCIX mode */
13310                         tp->dma_rwctrl |= 0x00144000;
13311                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13312                         /* 5714 always in PCIX mode */
13313                         tp->dma_rwctrl |= 0x00148000;
13314                 } else {
13315                         tp->dma_rwctrl |= 0x001b000f;
13316                 }
13317         }
13318
13319         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13320             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13321                 tp->dma_rwctrl &= 0xfffffff0;
13322
13323         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13324             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13325                 /* Remove this if it causes problems for some boards. */
13326                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13327
13328                 /* On 5700/5701 chips, we need to set this bit.
13329                  * Otherwise the chip will issue cacheline transactions
13330                  * to streamable DMA memory with not all the byte
13331                  * enables turned on.  This is an error on several
13332                  * RISC PCI controllers, in particular sparc64.
13333                  *
13334                  * On 5703/5704 chips, this bit has been reassigned
13335                  * a different meaning.  In particular, it is used
13336                  * on those chips to enable a PCI-X workaround.
13337                  */
13338                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13339         }
13340
13341         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13342
13343 #if 0
13344         /* Unneeded, already done by tg3_get_invariants.  */
13345         tg3_switch_clocks(tp);
13346 #endif
13347
13348         ret = 0;
13349         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13350             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13351                 goto out;
13352
13353         /* It is best to perform DMA test with maximum write burst size
13354          * to expose the 5700/5701 write DMA bug.
13355          */
13356         saved_dma_rwctrl = tp->dma_rwctrl;
13357         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13358         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13359
13360         while (1) {
13361                 u32 *p = buf, i;
13362
13363                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13364                         p[i] = i;
13365
13366                 /* Send the buffer to the chip. */
13367                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13368                 if (ret) {
13369                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13370                         break;
13371                 }
13372
13373 #if 0
13374                 /* validate data reached card RAM correctly. */
13375                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13376                         u32 val;
13377                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13378                         if (le32_to_cpu(val) != p[i]) {
13379                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13380                                 /* ret = -ENODEV here? */
13381                         }
13382                         p[i] = 0;
13383                 }
13384 #endif
13385                 /* Now read it back. */
13386                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13387                 if (ret) {
13388                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13389
13390                         break;
13391                 }
13392
13393                 /* Verify it. */
13394                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13395                         if (p[i] == i)
13396                                 continue;
13397
13398                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13399                             DMA_RWCTRL_WRITE_BNDRY_16) {
13400                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13401                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13402                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13403                                 break;
13404                         } else {
13405                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13406                                 ret = -ENODEV;
13407                                 goto out;
13408                         }
13409                 }
13410
13411                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13412                         /* Success. */
13413                         ret = 0;
13414                         break;
13415                 }
13416         }
13417         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13418             DMA_RWCTRL_WRITE_BNDRY_16) {
13419                 static struct pci_device_id dma_wait_state_chipsets[] = {
13420                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13421                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13422                         { },
13423                 };
13424
13425                 /* DMA test passed without adjusting DMA boundary,
13426                  * now look for chipsets that are known to expose the
13427                  * DMA bug without failing the test.
13428                  */
13429                 if (pci_dev_present(dma_wait_state_chipsets)) {
13430                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13431                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13432                 }
13433                 else
13434                         /* Safe to use the calculated DMA boundary. */
13435                         tp->dma_rwctrl = saved_dma_rwctrl;
13436
13437                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13438         }
13439
13440 out:
13441         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13442 out_nofree:
13443         return ret;
13444 }
13445
13446 static void __devinit tg3_init_link_config(struct tg3 *tp)
13447 {
13448         tp->link_config.advertising =
13449                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13450                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13451                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13452                  ADVERTISED_Autoneg | ADVERTISED_MII);
13453         tp->link_config.speed = SPEED_INVALID;
13454         tp->link_config.duplex = DUPLEX_INVALID;
13455         tp->link_config.autoneg = AUTONEG_ENABLE;
13456         tp->link_config.active_speed = SPEED_INVALID;
13457         tp->link_config.active_duplex = DUPLEX_INVALID;
13458         tp->link_config.phy_is_low_power = 0;
13459         tp->link_config.orig_speed = SPEED_INVALID;
13460         tp->link_config.orig_duplex = DUPLEX_INVALID;
13461         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13462 }
13463
13464 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13465 {
13466         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13467                 tp->bufmgr_config.mbuf_read_dma_low_water =
13468                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13469                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13470                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13471                 tp->bufmgr_config.mbuf_high_water =
13472                         DEFAULT_MB_HIGH_WATER_5705;
13473                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13474                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13475                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13476                         tp->bufmgr_config.mbuf_high_water =
13477                                 DEFAULT_MB_HIGH_WATER_5906;
13478                 }
13479
13480                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13481                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13482                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13483                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13484                 tp->bufmgr_config.mbuf_high_water_jumbo =
13485                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13486         } else {
13487                 tp->bufmgr_config.mbuf_read_dma_low_water =
13488                         DEFAULT_MB_RDMA_LOW_WATER;
13489                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13490                         DEFAULT_MB_MACRX_LOW_WATER;
13491                 tp->bufmgr_config.mbuf_high_water =
13492                         DEFAULT_MB_HIGH_WATER;
13493
13494                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13495                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13496                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13497                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13498                 tp->bufmgr_config.mbuf_high_water_jumbo =
13499                         DEFAULT_MB_HIGH_WATER_JUMBO;
13500         }
13501
13502         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13503         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13504 }
13505
13506 static char * __devinit tg3_phy_string(struct tg3 *tp)
13507 {
13508         switch (tp->phy_id & PHY_ID_MASK) {
13509         case PHY_ID_BCM5400:    return "5400";
13510         case PHY_ID_BCM5401:    return "5401";
13511         case PHY_ID_BCM5411:    return "5411";
13512         case PHY_ID_BCM5701:    return "5701";
13513         case PHY_ID_BCM5703:    return "5703";
13514         case PHY_ID_BCM5704:    return "5704";
13515         case PHY_ID_BCM5705:    return "5705";
13516         case PHY_ID_BCM5750:    return "5750";
13517         case PHY_ID_BCM5752:    return "5752";
13518         case PHY_ID_BCM5714:    return "5714";
13519         case PHY_ID_BCM5780:    return "5780";
13520         case PHY_ID_BCM5755:    return "5755";
13521         case PHY_ID_BCM5787:    return "5787";
13522         case PHY_ID_BCM5784:    return "5784";
13523         case PHY_ID_BCM5756:    return "5722/5756";
13524         case PHY_ID_BCM5906:    return "5906";
13525         case PHY_ID_BCM5761:    return "5761";
13526         case PHY_ID_BCM8002:    return "8002/serdes";
13527         case 0:                 return "serdes";
13528         default:                return "unknown";
13529         }
13530 }
13531
13532 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13533 {
13534         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13535                 strcpy(str, "PCI Express");
13536                 return str;
13537         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13538                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13539
13540                 strcpy(str, "PCIX:");
13541
13542                 if ((clock_ctrl == 7) ||
13543                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13544                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13545                         strcat(str, "133MHz");
13546                 else if (clock_ctrl == 0)
13547                         strcat(str, "33MHz");
13548                 else if (clock_ctrl == 2)
13549                         strcat(str, "50MHz");
13550                 else if (clock_ctrl == 4)
13551                         strcat(str, "66MHz");
13552                 else if (clock_ctrl == 6)
13553                         strcat(str, "100MHz");
13554         } else {
13555                 strcpy(str, "PCI:");
13556                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13557                         strcat(str, "66MHz");
13558                 else
13559                         strcat(str, "33MHz");
13560         }
13561         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13562                 strcat(str, ":32-bit");
13563         else
13564                 strcat(str, ":64-bit");
13565         return str;
13566 }
13567
13568 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13569 {
13570         struct pci_dev *peer;
13571         unsigned int func, devnr = tp->pdev->devfn & ~7;
13572
13573         for (func = 0; func < 8; func++) {
13574                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13575                 if (peer && peer != tp->pdev)
13576                         break;
13577                 pci_dev_put(peer);
13578         }
13579         /* 5704 can be configured in single-port mode, set peer to
13580          * tp->pdev in that case.
13581          */
13582         if (!peer) {
13583                 peer = tp->pdev;
13584                 return peer;
13585         }
13586
13587         /*
13588          * We don't need to keep the refcount elevated; there's no way
13589          * to remove one half of this device without removing the other
13590          */
13591         pci_dev_put(peer);
13592
13593         return peer;
13594 }
13595
13596 static void __devinit tg3_init_coal(struct tg3 *tp)
13597 {
13598         struct ethtool_coalesce *ec = &tp->coal;
13599
13600         memset(ec, 0, sizeof(*ec));
13601         ec->cmd = ETHTOOL_GCOALESCE;
13602         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13603         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13604         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13605         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13606         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13607         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13608         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13609         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13610         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13611
13612         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13613                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13614                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13615                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13616                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13617                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13618         }
13619
13620         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13621                 ec->rx_coalesce_usecs_irq = 0;
13622                 ec->tx_coalesce_usecs_irq = 0;
13623                 ec->stats_block_coalesce_usecs = 0;
13624         }
13625 }
13626
13627 static const struct net_device_ops tg3_netdev_ops = {
13628         .ndo_open               = tg3_open,
13629         .ndo_stop               = tg3_close,
13630         .ndo_start_xmit         = tg3_start_xmit,
13631         .ndo_get_stats          = tg3_get_stats,
13632         .ndo_validate_addr      = eth_validate_addr,
13633         .ndo_set_multicast_list = tg3_set_rx_mode,
13634         .ndo_set_mac_address    = tg3_set_mac_addr,
13635         .ndo_do_ioctl           = tg3_ioctl,
13636         .ndo_tx_timeout         = tg3_tx_timeout,
13637         .ndo_change_mtu         = tg3_change_mtu,
13638 #if TG3_VLAN_TAG_USED
13639         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13640 #endif
13641 #ifdef CONFIG_NET_POLL_CONTROLLER
13642         .ndo_poll_controller    = tg3_poll_controller,
13643 #endif
13644 };
13645
13646 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13647         .ndo_open               = tg3_open,
13648         .ndo_stop               = tg3_close,
13649         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13650         .ndo_get_stats          = tg3_get_stats,
13651         .ndo_validate_addr      = eth_validate_addr,
13652         .ndo_set_multicast_list = tg3_set_rx_mode,
13653         .ndo_set_mac_address    = tg3_set_mac_addr,
13654         .ndo_do_ioctl           = tg3_ioctl,
13655         .ndo_tx_timeout         = tg3_tx_timeout,
13656         .ndo_change_mtu         = tg3_change_mtu,
13657 #if TG3_VLAN_TAG_USED
13658         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13659 #endif
13660 #ifdef CONFIG_NET_POLL_CONTROLLER
13661         .ndo_poll_controller    = tg3_poll_controller,
13662 #endif
13663 };
13664
13665 static int __devinit tg3_init_one(struct pci_dev *pdev,
13666                                   const struct pci_device_id *ent)
13667 {
13668         static int tg3_version_printed = 0;
13669         struct net_device *dev;
13670         struct tg3 *tp;
13671         int i, err, pm_cap;
13672         u32 sndmbx, rcvmbx, intmbx;
13673         char str[40];
13674         u64 dma_mask, persist_dma_mask;
13675
13676         if (tg3_version_printed++ == 0)
13677                 printk(KERN_INFO "%s", version);
13678
13679         err = pci_enable_device(pdev);
13680         if (err) {
13681                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13682                        "aborting.\n");
13683                 return err;
13684         }
13685
13686         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13687         if (err) {
13688                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13689                        "aborting.\n");
13690                 goto err_out_disable_pdev;
13691         }
13692
13693         pci_set_master(pdev);
13694
13695         /* Find power-management capability. */
13696         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13697         if (pm_cap == 0) {
13698                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13699                        "aborting.\n");
13700                 err = -EIO;
13701                 goto err_out_free_res;
13702         }
13703
13704         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13705         if (!dev) {
13706                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13707                 err = -ENOMEM;
13708                 goto err_out_free_res;
13709         }
13710
13711         SET_NETDEV_DEV(dev, &pdev->dev);
13712
13713 #if TG3_VLAN_TAG_USED
13714         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13715 #endif
13716
13717         tp = netdev_priv(dev);
13718         tp->pdev = pdev;
13719         tp->dev = dev;
13720         tp->pm_cap = pm_cap;
13721         tp->rx_mode = TG3_DEF_RX_MODE;
13722         tp->tx_mode = TG3_DEF_TX_MODE;
13723
13724         if (tg3_debug > 0)
13725                 tp->msg_enable = tg3_debug;
13726         else
13727                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13728
13729         /* The word/byte swap controls here control register access byte
13730          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13731          * setting below.
13732          */
13733         tp->misc_host_ctrl =
13734                 MISC_HOST_CTRL_MASK_PCI_INT |
13735                 MISC_HOST_CTRL_WORD_SWAP |
13736                 MISC_HOST_CTRL_INDIR_ACCESS |
13737                 MISC_HOST_CTRL_PCISTATE_RW;
13738
13739         /* The NONFRM (non-frame) byte/word swap controls take effect
13740          * on descriptor entries, anything which isn't packet data.
13741          *
13742          * The StrongARM chips on the board (one for tx, one for rx)
13743          * are running in big-endian mode.
13744          */
13745         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13746                         GRC_MODE_WSWAP_NONFRM_DATA);
13747 #ifdef __BIG_ENDIAN
13748         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13749 #endif
13750         spin_lock_init(&tp->lock);
13751         spin_lock_init(&tp->indirect_lock);
13752         INIT_WORK(&tp->reset_task, tg3_reset_task);
13753
13754         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13755         if (!tp->regs) {
13756                 printk(KERN_ERR PFX "Cannot map device registers, "
13757                        "aborting.\n");
13758                 err = -ENOMEM;
13759                 goto err_out_free_dev;
13760         }
13761
13762         tg3_init_link_config(tp);
13763
13764         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13765         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13766
13767         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13768         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13769         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13770         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13771                 struct tg3_napi *tnapi = &tp->napi[i];
13772
13773                 tnapi->tp = tp;
13774                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
13775
13776                 tnapi->int_mbox = intmbx;
13777                 if (i < 4)
13778                         intmbx += 0x8;
13779                 else
13780                         intmbx += 0x4;
13781
13782                 tnapi->consmbox = rcvmbx;
13783                 tnapi->prodmbox = sndmbx;
13784
13785                 if (i)
13786                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
13787                 else
13788                         tnapi->coal_now = HOSTCC_MODE_NOW;
13789
13790                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
13791                         break;
13792
13793                 /*
13794                  * If we support MSIX, we'll be using RSS.  If we're using
13795                  * RSS, the first vector only handles link interrupts and the
13796                  * remaining vectors handle rx and tx interrupts.  Reuse the
13797                  * mailbox values for the next iteration.  The values we setup
13798                  * above are still useful for the single vectored mode.
13799                  */
13800                 if (!i)
13801                         continue;
13802
13803                 rcvmbx += 0x8;
13804
13805                 if (sndmbx & 0x4)
13806                         sndmbx -= 0x4;
13807                 else
13808                         sndmbx += 0xc;
13809         }
13810
13811         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
13812         dev->ethtool_ops = &tg3_ethtool_ops;
13813         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13814         dev->irq = pdev->irq;
13815
13816         err = tg3_get_invariants(tp);
13817         if (err) {
13818                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13819                        "aborting.\n");
13820                 goto err_out_iounmap;
13821         }
13822
13823         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13824             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13825                 dev->netdev_ops = &tg3_netdev_ops;
13826         else
13827                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13828
13829
13830         /* The EPB bridge inside 5714, 5715, and 5780 and any
13831          * device behind the EPB cannot support DMA addresses > 40-bit.
13832          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13833          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13834          * do DMA address check in tg3_start_xmit().
13835          */
13836         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13837                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13838         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13839                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13840 #ifdef CONFIG_HIGHMEM
13841                 dma_mask = DMA_BIT_MASK(64);
13842 #endif
13843         } else
13844                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13845
13846         /* Configure DMA attributes. */
13847         if (dma_mask > DMA_BIT_MASK(32)) {
13848                 err = pci_set_dma_mask(pdev, dma_mask);
13849                 if (!err) {
13850                         dev->features |= NETIF_F_HIGHDMA;
13851                         err = pci_set_consistent_dma_mask(pdev,
13852                                                           persist_dma_mask);
13853                         if (err < 0) {
13854                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13855                                        "DMA for consistent allocations\n");
13856                                 goto err_out_iounmap;
13857                         }
13858                 }
13859         }
13860         if (err || dma_mask == DMA_BIT_MASK(32)) {
13861                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13862                 if (err) {
13863                         printk(KERN_ERR PFX "No usable DMA configuration, "
13864                                "aborting.\n");
13865                         goto err_out_iounmap;
13866                 }
13867         }
13868
13869         tg3_init_bufmgr_config(tp);
13870
13871         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13872                 tp->fw_needed = FIRMWARE_TG3;
13873
13874         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13875                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13876         }
13877         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13878             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13879             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13880             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13881             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13882                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13883         } else {
13884                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13885                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13886                         tp->fw_needed = FIRMWARE_TG3TSO5;
13887                 else
13888                         tp->fw_needed = FIRMWARE_TG3TSO;
13889         }
13890
13891         /* TSO is on by default on chips that support hardware TSO.
13892          * Firmware TSO on older chips gives lower performance, so it
13893          * is off by default, but can be enabled using ethtool.
13894          */
13895         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13896                 if (dev->features & NETIF_F_IP_CSUM)
13897                         dev->features |= NETIF_F_TSO;
13898                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13899                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13900                         dev->features |= NETIF_F_TSO6;
13901                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13902                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13903                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13904                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13905                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13906                         dev->features |= NETIF_F_TSO_ECN;
13907         }
13908
13909
13910         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13911             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13912             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13913                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13914                 tp->rx_pending = 63;
13915         }
13916
13917         err = tg3_get_device_address(tp);
13918         if (err) {
13919                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13920                        "aborting.\n");
13921                 goto err_out_fw;
13922         }
13923
13924         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13925                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13926                 if (!tp->aperegs) {
13927                         printk(KERN_ERR PFX "Cannot map APE registers, "
13928                                "aborting.\n");
13929                         err = -ENOMEM;
13930                         goto err_out_fw;
13931                 }
13932
13933                 tg3_ape_lock_init(tp);
13934
13935                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13936                         tg3_read_dash_ver(tp);
13937         }
13938
13939         /*
13940          * Reset chip in case UNDI or EFI driver did not shutdown
13941          * DMA self test will enable WDMAC and we'll see (spurious)
13942          * pending DMA on the PCI bus at that point.
13943          */
13944         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13945             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13946                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13947                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13948         }
13949
13950         err = tg3_test_dma(tp);
13951         if (err) {
13952                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13953                 goto err_out_apeunmap;
13954         }
13955
13956         /* flow control autonegotiation is default behavior */
13957         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13958         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13959
13960         tg3_init_coal(tp);
13961
13962         pci_set_drvdata(pdev, dev);
13963
13964         err = register_netdev(dev);
13965         if (err) {
13966                 printk(KERN_ERR PFX "Cannot register net device, "
13967                        "aborting.\n");
13968                 goto err_out_apeunmap;
13969         }
13970
13971         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13972                dev->name,
13973                tp->board_part_number,
13974                tp->pci_chip_rev_id,
13975                tg3_bus_string(tp, str),
13976                dev->dev_addr);
13977
13978         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13979                 printk(KERN_INFO
13980                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13981                        tp->dev->name,
13982                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13983                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13984         else
13985                 printk(KERN_INFO
13986                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13987                        tp->dev->name, tg3_phy_string(tp),
13988                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13989                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13990                          "10/100/1000Base-T")),
13991                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13992
13993         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13994                dev->name,
13995                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13996                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13997                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13998                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13999                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14000         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14001                dev->name, tp->dma_rwctrl,
14002                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14003                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14004
14005         return 0;
14006
14007 err_out_apeunmap:
14008         if (tp->aperegs) {
14009                 iounmap(tp->aperegs);
14010                 tp->aperegs = NULL;
14011         }
14012
14013 err_out_fw:
14014         if (tp->fw)
14015                 release_firmware(tp->fw);
14016
14017 err_out_iounmap:
14018         if (tp->regs) {
14019                 iounmap(tp->regs);
14020                 tp->regs = NULL;
14021         }
14022
14023 err_out_free_dev:
14024         free_netdev(dev);
14025
14026 err_out_free_res:
14027         pci_release_regions(pdev);
14028
14029 err_out_disable_pdev:
14030         pci_disable_device(pdev);
14031         pci_set_drvdata(pdev, NULL);
14032         return err;
14033 }
14034
14035 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14036 {
14037         struct net_device *dev = pci_get_drvdata(pdev);
14038
14039         if (dev) {
14040                 struct tg3 *tp = netdev_priv(dev);
14041
14042                 if (tp->fw)
14043                         release_firmware(tp->fw);
14044
14045                 flush_scheduled_work();
14046
14047                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14048                         tg3_phy_fini(tp);
14049                         tg3_mdio_fini(tp);
14050                 }
14051
14052                 unregister_netdev(dev);
14053                 if (tp->aperegs) {
14054                         iounmap(tp->aperegs);
14055                         tp->aperegs = NULL;
14056                 }
14057                 if (tp->regs) {
14058                         iounmap(tp->regs);
14059                         tp->regs = NULL;
14060                 }
14061                 free_netdev(dev);
14062                 pci_release_regions(pdev);
14063                 pci_disable_device(pdev);
14064                 pci_set_drvdata(pdev, NULL);
14065         }
14066 }
14067
14068 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14069 {
14070         struct net_device *dev = pci_get_drvdata(pdev);
14071         struct tg3 *tp = netdev_priv(dev);
14072         pci_power_t target_state;
14073         int err;
14074
14075         /* PCI register 4 needs to be saved whether netif_running() or not.
14076          * MSI address and data need to be saved if using MSI and
14077          * netif_running().
14078          */
14079         pci_save_state(pdev);
14080
14081         if (!netif_running(dev))
14082                 return 0;
14083
14084         flush_scheduled_work();
14085         tg3_phy_stop(tp);
14086         tg3_netif_stop(tp);
14087
14088         del_timer_sync(&tp->timer);
14089
14090         tg3_full_lock(tp, 1);
14091         tg3_disable_ints(tp);
14092         tg3_full_unlock(tp);
14093
14094         netif_device_detach(dev);
14095
14096         tg3_full_lock(tp, 0);
14097         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14098         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14099         tg3_full_unlock(tp);
14100
14101         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14102
14103         err = tg3_set_power_state(tp, target_state);
14104         if (err) {
14105                 int err2;
14106
14107                 tg3_full_lock(tp, 0);
14108
14109                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14110                 err2 = tg3_restart_hw(tp, 1);
14111                 if (err2)
14112                         goto out;
14113
14114                 tp->timer.expires = jiffies + tp->timer_offset;
14115                 add_timer(&tp->timer);
14116
14117                 netif_device_attach(dev);
14118                 tg3_netif_start(tp);
14119
14120 out:
14121                 tg3_full_unlock(tp);
14122
14123                 if (!err2)
14124                         tg3_phy_start(tp);
14125         }
14126
14127         return err;
14128 }
14129
14130 static int tg3_resume(struct pci_dev *pdev)
14131 {
14132         struct net_device *dev = pci_get_drvdata(pdev);
14133         struct tg3 *tp = netdev_priv(dev);
14134         int err;
14135
14136         pci_restore_state(tp->pdev);
14137
14138         if (!netif_running(dev))
14139                 return 0;
14140
14141         err = tg3_set_power_state(tp, PCI_D0);
14142         if (err)
14143                 return err;
14144
14145         netif_device_attach(dev);
14146
14147         tg3_full_lock(tp, 0);
14148
14149         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14150         err = tg3_restart_hw(tp, 1);
14151         if (err)
14152                 goto out;
14153
14154         tp->timer.expires = jiffies + tp->timer_offset;
14155         add_timer(&tp->timer);
14156
14157         tg3_netif_start(tp);
14158
14159 out:
14160         tg3_full_unlock(tp);
14161
14162         if (!err)
14163                 tg3_phy_start(tp);
14164
14165         return err;
14166 }
14167
14168 static struct pci_driver tg3_driver = {
14169         .name           = DRV_MODULE_NAME,
14170         .id_table       = tg3_pci_tbl,
14171         .probe          = tg3_init_one,
14172         .remove         = __devexit_p(tg3_remove_one),
14173         .suspend        = tg3_suspend,
14174         .resume         = tg3_resume
14175 };
14176
14177 static int __init tg3_init(void)
14178 {
14179         return pci_register_driver(&tg3_driver);
14180 }
14181
14182 static void __exit tg3_cleanup(void)
14183 {
14184         pci_unregister_driver(&tg3_driver);
14185 }
14186
14187 module_init(tg3_init);
14188 module_exit(tg3_cleanup);