drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.102"
  72 #define DRV_MODULE_RELDATE      "September 1, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 /* minimum number of free TX descriptors required to wake up TX process */
 141 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 142
 143 #define TG3_RAW_IP_ALIGN 2
 144
 145 /* number of ETHTOOL_GSTATS u64's */
 146 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 147
 148 #define TG3_NUM_TEST            6
 149
 150 #define FIRMWARE_TG3            "tigon/tg3.bin"
 151 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 152 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 153
 154 static char version[] __devinitdata =
 155         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 156
 157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_MODULE_VERSION);
 161 MODULE_FIRMWARE(FIRMWARE_TG3);
 162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 164
 165 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 166
 167 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 168 module_param(tg3_debug, int, 0);
 169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 170
 171 static struct pci_device_id tg3_pci_tbl[] = {
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 245         {}
 246 };
 247
 248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 249
 250 static const struct {
 251         const char string[ETH_GSTRING_LEN];
 252 } ethtool_stats_keys[TG3_NUM_STATS] = {
 253         { "rx_octets" },
 254         { "rx_fragments" },
 255         { "rx_ucast_packets" },
 256         { "rx_mcast_packets" },
 257         { "rx_bcast_packets" },
 258         { "rx_fcs_errors" },
 259         { "rx_align_errors" },
 260         { "rx_xon_pause_rcvd" },
 261         { "rx_xoff_pause_rcvd" },
 262         { "rx_mac_ctrl_rcvd" },
 263         { "rx_xoff_entered" },
 264         { "rx_frame_too_long_errors" },
 265         { "rx_jabbers" },
 266         { "rx_undersize_packets" },
 267         { "rx_in_length_errors" },
 268         { "rx_out_length_errors" },
 269         { "rx_64_or_less_octet_packets" },
 270         { "rx_65_to_127_octet_packets" },
 271         { "rx_128_to_255_octet_packets" },
 272         { "rx_256_to_511_octet_packets" },
 273         { "rx_512_to_1023_octet_packets" },
 274         { "rx_1024_to_1522_octet_packets" },
 275         { "rx_1523_to_2047_octet_packets" },
 276         { "rx_2048_to_4095_octet_packets" },
 277         { "rx_4096_to_8191_octet_packets" },
 278         { "rx_8192_to_9022_octet_packets" },
 279
 280         { "tx_octets" },
 281         { "tx_collisions" },
 282
 283         { "tx_xon_sent" },
 284         { "tx_xoff_sent" },
 285         { "tx_flow_control" },
 286         { "tx_mac_errors" },
 287         { "tx_single_collisions" },
 288         { "tx_mult_collisions" },
 289         { "tx_deferred" },
 290         { "tx_excessive_collisions" },
 291         { "tx_late_collisions" },
 292         { "tx_collide_2times" },
 293         { "tx_collide_3times" },
 294         { "tx_collide_4times" },
 295         { "tx_collide_5times" },
 296         { "tx_collide_6times" },
 297         { "tx_collide_7times" },
 298         { "tx_collide_8times" },
 299         { "tx_collide_9times" },
 300         { "tx_collide_10times" },
 301         { "tx_collide_11times" },
 302         { "tx_collide_12times" },
 303         { "tx_collide_13times" },
 304         { "tx_collide_14times" },
 305         { "tx_collide_15times" },
 306         { "tx_ucast_packets" },
 307         { "tx_mcast_packets" },
 308         { "tx_bcast_packets" },
 309         { "tx_carrier_sense_errors" },
 310         { "tx_discards" },
 311         { "tx_errors" },
 312
 313         { "dma_writeq_full" },
 314         { "dma_write_prioq_full" },
 315         { "rxbds_empty" },
 316         { "rx_discards" },
 317         { "rx_errors" },
 318         { "rx_threshold_hit" },
 319
 320         { "dma_readq_full" },
 321         { "dma_read_prioq_full" },
 322         { "tx_comp_queue_full" },
 323
 324         { "ring_set_send_prod_index" },
 325         { "ring_status_update" },
 326         { "nic_irqs" },
 327         { "nic_avoided_irqs" },
 328         { "nic_tx_threshold_hit" }
 329 };
 330
 331 static const struct {
 332         const char string[ETH_GSTRING_LEN];
 333 } ethtool_test_keys[TG3_NUM_TEST] = {
 334         { "nvram test     (online) " },
 335         { "link test      (online) " },
 336         { "register test  (offline)" },
 337         { "memory test    (offline)" },
 338         { "loopback test  (offline)" },
 339         { "interrupt test (offline)" },
 340 };
 341
 342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 343 {
 344         writel(val, tp->regs + off);
 345 }
 346
 347 static u32 tg3_read32(struct tg3 *tp, u32 off)
 348 {
 349         return (readl(tp->regs + off));
 350 }
 351
 352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 353 {
 354         writel(val, tp->aperegs + off);
 355 }
 356
 357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 358 {
 359         return (readl(tp->aperegs + off));
 360 }
 361
 362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 363 {
 364         unsigned long flags;
 365
 366         spin_lock_irqsave(&tp->indirect_lock, flags);
 367         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 368         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 369         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 370 }
 371
 372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         writel(val, tp->regs + off);
 375         readl(tp->regs + off);
 376 }
 377
 378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 379 {
 380         unsigned long flags;
 381         u32 val;
 382
 383         spin_lock_irqsave(&tp->indirect_lock, flags);
 384         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 385         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 386         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 387         return val;
 388 }
 389
 390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 391 {
 392         unsigned long flags;
 393
 394         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 395                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 396                                        TG3_64BIT_REG_LOW, val);
 397                 return;
 398         }
 399         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 400                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 401                                        TG3_64BIT_REG_LOW, val);
 402                 return;
 403         }
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409
 410         /* In indirect mode when disabling interrupts, we also need
 411          * to clear the interrupt bit in the GRC local ctrl register.
 412          */
 413         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 414             (val == 0x1)) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 416                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 417         }
 418 }
 419
 420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 421 {
 422         unsigned long flags;
 423         u32 val;
 424
 425         spin_lock_irqsave(&tp->indirect_lock, flags);
 426         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 427         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 428         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 429         return val;
 430 }
 431
 432 /* usec_wait specifies the wait time in usec when writing to certain registers
 433  * where it is unsafe to read back the register without some delay.
 434  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 435  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 436  */
 437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 438 {
 439         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 440             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 441                 /* Non-posted methods */
 442                 tp->write32(tp, off, val);
 443         else {
 444                 /* Posted method */
 445                 tg3_write32(tp, off, val);
 446                 if (usec_wait)
 447                         udelay(usec_wait);
 448                 tp->read32(tp, off);
 449         }
 450         /* Wait again after the read for the posted method to guarantee that
 451          * the wait time is met.
 452          */
 453         if (usec_wait)
 454                 udelay(usec_wait);
 455 }
 456
 457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 458 {
 459         tp->write32_mbox(tp, off, val);
 460         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 461             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 462                 tp->read32_mbox(tp, off);
 463 }
 464
 465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 466 {
 467         void __iomem *mbox = tp->regs + off;
 468         writel(val, mbox);
 469         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 470                 writel(val, mbox);
 471         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 472                 readl(mbox);
 473 }
 474
 475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 476 {
 477         return (readl(tp->regs + off + GRCMBOX_BASE));
 478 }
 479
 480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         writel(val, tp->regs + off + GRCMBOX_BASE);
 483 }
 484
 485 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 486 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 487 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 488 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 489 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 490
 491 #define tw32(reg,val)           tp->write32(tp, reg, val)
 492 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 494 #define tr32(reg)               tp->read32(tp, reg)
 495
 496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         unsigned long flags;
 499
 500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 501             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 502                 return;
 503
 504         spin_lock_irqsave(&tp->indirect_lock, flags);
 505         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 508
 509                 /* Always leave this as zero. */
 510                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 511         } else {
 512                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 513                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 514
 515                 /* Always leave this as zero. */
 516                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 517         }
 518         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 519 }
 520
 521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 522 {
 523         unsigned long flags;
 524
 525         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 526             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 527                 *val = 0;
 528                 return;
 529         }
 530
 531         spin_lock_irqsave(&tp->indirect_lock, flags);
 532         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 533                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 534                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 535
 536                 /* Always leave this as zero. */
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 538         } else {
 539                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 540                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 541
 542                 /* Always leave this as zero. */
 543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 544         }
 545         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 546 }
 547
 548 static void tg3_ape_lock_init(struct tg3 *tp)
 549 {
 550         int i;
 551
 552         /* Make sure the driver hasn't any stale locks. */
 553         for (i = 0; i < 8; i++)
 554                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 555                                 APE_LOCK_GRANT_DRIVER);
 556 }
 557
 558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 559 {
 560         int i, off;
 561         int ret = 0;
 562         u32 status;
 563
 564         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 565                 return 0;
 566
 567         switch (locknum) {
 568                 case TG3_APE_LOCK_GRC:
 569                 case TG3_APE_LOCK_MEM:
 570                         break;
 571                 default:
 572                         return -EINVAL;
 573         }
 574
 575         off = 4 * locknum;
 576
 577         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 578
 579         /* Wait for up to 1 millisecond to acquire lock. */
 580         for (i = 0; i < 100; i++) {
 581                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 582                 if (status == APE_LOCK_GRANT_DRIVER)
 583                         break;
 584                 udelay(10);
 585         }
 586
 587         if (status != APE_LOCK_GRANT_DRIVER) {
 588                 /* Revoke the lock request. */
 589                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 590                                 APE_LOCK_GRANT_DRIVER);
 591
 592                 ret = -EBUSY;
 593         }
 594
 595         return ret;
 596 }
 597
 598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 599 {
 600         int off;
 601
 602         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 603                 return;
 604
 605         switch (locknum) {
 606                 case TG3_APE_LOCK_GRC:
 607                 case TG3_APE_LOCK_MEM:
 608                         break;
 609                 default:
 610                         return;
 611         }
 612
 613         off = 4 * locknum;
 614         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 615 }
 616
 617 static void tg3_disable_ints(struct tg3 *tp)
 618 {
 619         int i;
 620
 621         tw32(TG3PCI_MISC_HOST_CTRL,
 622              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 623         for (i = 0; i < tp->irq_max; i++)
 624                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 625 }
 626
 627 static void tg3_enable_ints(struct tg3 *tp)
 628 {
 629         int i;
 630         u32 coal_now = 0;
 631
 632         tp->irq_sync = 0;
 633         wmb();
 634
 635         tw32(TG3PCI_MISC_HOST_CTRL,
 636              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 637
 638         for (i = 0; i < tp->irq_cnt; i++) {
 639                 struct tg3_napi *tnapi = &tp->napi[i];
 640                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 641                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 642                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 643
 644                 coal_now |= tnapi->coal_now;
 645         }
 646
 647         /* Force an initial interrupt */
 648         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 649             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 650                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 651         else
 652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 653                      HOSTCC_MODE_ENABLE | coal_now);
 654 }
 655
 656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 657 {
 658         struct tg3 *tp = tnapi->tp;
 659         struct tg3_hw_status *sblk = tnapi->hw_status;
 660         unsigned int work_exists = 0;
 661
 662         /* check for phy events */
 663         if (!(tp->tg3_flags &
 664               (TG3_FLAG_USE_LINKCHG_REG |
 665                TG3_FLAG_POLL_SERDES))) {
 666                 if (sblk->status & SD_STATUS_LINK_CHG)
 667                         work_exists = 1;
 668         }
 669         /* check for RX/TX work to do */
 670         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 671             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 672                 work_exists = 1;
 673
 674         return work_exists;
 675 }
 676
 677 /* tg3_int_reenable
 678  *  similar to tg3_enable_ints, but it accurately determines whether there
 679  *  is new work pending and can return without flushing the PIO write
 680  *  which reenables interrupts
 681  */
 682 static void tg3_int_reenable(struct tg3_napi *tnapi)
 683 {
 684         struct tg3 *tp = tnapi->tp;
 685
 686         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 687         mmiowb();
 688
 689         /* When doing tagged status, this work check is unnecessary.
 690          * The last_tag we write above tells the chip which piece of
 691          * work we've completed.
 692          */
 693         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 694             tg3_has_work(tnapi))
 695                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 696                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 697 }
 698
 699 static void tg3_napi_disable(struct tg3 *tp)
 700 {
 701         int i;
 702
 703         for (i = tp->irq_cnt - 1; i >= 0; i--)
 704                 napi_disable(&tp->napi[i].napi);
 705 }
 706
 707 static void tg3_napi_enable(struct tg3 *tp)
 708 {
 709         int i;
 710
 711         for (i = 0; i < tp->irq_cnt; i++)
 712                 napi_enable(&tp->napi[i].napi);
 713 }
 714
 715 static inline void tg3_netif_stop(struct tg3 *tp)
 716 {
 717         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 718         tg3_napi_disable(tp);
 719         netif_tx_disable(tp->dev);
 720 }
 721
 722 static inline void tg3_netif_start(struct tg3 *tp)
 723 {
 724         /* NOTE: unconditional netif_tx_wake_all_queues is only
 725          * appropriate so long as all callers are assured to
 726          * have free tx slots (such as after tg3_init_hw)
 727          */
 728         netif_tx_wake_all_queues(tp->dev);
 729
 730         tg3_napi_enable(tp);
 731         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 732         tg3_enable_ints(tp);
 733 }
 734
 735 static void tg3_switch_clocks(struct tg3 *tp)
 736 {
 737         u32 clock_ctrl;
 738         u32 orig_clock_ctrl;
 739
 740         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 741             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 742                 return;
 743
 744         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 745
 746         orig_clock_ctrl = clock_ctrl;
 747         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 748                        CLOCK_CTRL_CLKRUN_OENABLE |
 749                        0x1f);
 750         tp->pci_clock_ctrl = clock_ctrl;
 751
 752         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 753                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 754                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 755                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 756                 }
 757         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 758                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 759                             clock_ctrl |
 760                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 761                             40);
 762                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 763                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 764                             40);
 765         }
 766         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 767 }
 768
 769 #define PHY_BUSY_LOOPS  5000
 770
 771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 772 {
 773         u32 frame_val;
 774         unsigned int loops;
 775         int ret;
 776
 777         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 778                 tw32_f(MAC_MI_MODE,
 779                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 780                 udelay(80);
 781         }
 782
 783         *val = 0x0;
 784
 785         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 786                       MI_COM_PHY_ADDR_MASK);
 787         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 788                       MI_COM_REG_ADDR_MASK);
 789         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 790
 791         tw32_f(MAC_MI_COM, frame_val);
 792
 793         loops = PHY_BUSY_LOOPS;
 794         while (loops != 0) {
 795                 udelay(10);
 796                 frame_val = tr32(MAC_MI_COM);
 797
 798                 if ((frame_val & MI_COM_BUSY) == 0) {
 799                         udelay(5);
 800                         frame_val = tr32(MAC_MI_COM);
 801                         break;
 802                 }
 803                 loops -= 1;
 804         }
 805
 806         ret = -EBUSY;
 807         if (loops != 0) {
 808                 *val = frame_val & MI_COM_DATA_MASK;
 809                 ret = 0;
 810         }
 811
 812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 813                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 814                 udelay(80);
 815         }
 816
 817         return ret;
 818 }
 819
 820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 821 {
 822         u32 frame_val;
 823         unsigned int loops;
 824         int ret;
 825
 826         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 827             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 828                 return 0;
 829
 830         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 831                 tw32_f(MAC_MI_MODE,
 832                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 833                 udelay(80);
 834         }
 835
 836         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 837                       MI_COM_PHY_ADDR_MASK);
 838         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 839                       MI_COM_REG_ADDR_MASK);
 840         frame_val |= (val & MI_COM_DATA_MASK);
 841         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 842
 843         tw32_f(MAC_MI_COM, frame_val);
 844
 845         loops = PHY_BUSY_LOOPS;
 846         while (loops != 0) {
 847                 udelay(10);
 848                 frame_val = tr32(MAC_MI_COM);
 849                 if ((frame_val & MI_COM_BUSY) == 0) {
 850                         udelay(5);
 851                         frame_val = tr32(MAC_MI_COM);
 852                         break;
 853                 }
 854                 loops -= 1;
 855         }
 856
 857         ret = -EBUSY;
 858         if (loops != 0)
 859                 ret = 0;
 860
 861         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 862                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 863                 udelay(80);
 864         }
 865
 866         return ret;
 867 }
 868
 869 static int tg3_bmcr_reset(struct tg3 *tp)
 870 {
 871         u32 phy_control;
 872         int limit, err;
 873
 874         /* OK, reset it, and poll the BMCR_RESET bit until it
 875          * clears or we time out.
 876          */
 877         phy_control = BMCR_RESET;
 878         err = tg3_writephy(tp, MII_BMCR, phy_control);
 879         if (err != 0)
 880                 return -EBUSY;
 881
 882         limit = 5000;
 883         while (limit--) {
 884                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 885                 if (err != 0)
 886                         return -EBUSY;
 887
 888                 if ((phy_control & BMCR_RESET) == 0) {
 889                         udelay(40);
 890                         break;
 891                 }
 892                 udelay(10);
 893         }
 894         if (limit < 0)
 895                 return -EBUSY;
 896
 897         return 0;
 898 }
 899
 900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 901 {
 902         struct tg3 *tp = bp->priv;
 903         u32 val;
 904
 905         spin_lock_bh(&tp->lock);
 906
 907         if (tg3_readphy(tp, reg, &val))
 908                 val = -EIO;
 909
 910         spin_unlock_bh(&tp->lock);
 911
 912         return val;
 913 }
 914
 915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 ret = 0;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_writephy(tp, reg, val))
 923                 ret = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return ret;
 928 }
 929
 930 static int tg3_mdio_reset(struct mii_bus *bp)
 931 {
 932         return 0;
 933 }
 934
 935 static void tg3_mdio_config_5785(struct tg3 *tp)
 936 {
 937         u32 val;
 938         struct phy_device *phydev;
 939
 940         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 941         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 942         case TG3_PHY_ID_BCM50610:
 943         case TG3_PHY_ID_BCM50610M:
 944                 val = MAC_PHYCFG2_50610_LED_MODES;
 945                 break;
 946         case TG3_PHY_ID_BCMAC131:
 947                 val = MAC_PHYCFG2_AC131_LED_MODES;
 948                 break;
 949         case TG3_PHY_ID_RTL8211C:
 950                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 951                 break;
 952         case TG3_PHY_ID_RTL8201E:
 953                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 954                 break;
 955         default:
 956                 return;
 957         }
 958
 959         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 960                 tw32(MAC_PHYCFG2, val);
 961
 962                 val = tr32(MAC_PHYCFG1);
 963                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 964                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 965                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 966                 tw32(MAC_PHYCFG1, val);
 967
 968                 return;
 969         }
 970
 971         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 972                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 973                        MAC_PHYCFG2_FMODE_MASK_MASK |
 974                        MAC_PHYCFG2_GMODE_MASK_MASK |
 975                        MAC_PHYCFG2_ACT_MASK_MASK   |
 976                        MAC_PHYCFG2_QUAL_MASK_MASK |
 977                        MAC_PHYCFG2_INBAND_ENABLE;
 978
 979         tw32(MAC_PHYCFG2, val);
 980
 981         val = tr32(MAC_PHYCFG1);
 982         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 983                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 984         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 985                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 986                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 987                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 988                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 989         }
 990         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 991                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 992         tw32(MAC_PHYCFG1, val);
 993
 994         val = tr32(MAC_EXT_RGMII_MODE);
 995         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 996                  MAC_RGMII_MODE_RX_QUALITY |
 997                  MAC_RGMII_MODE_RX_ACTIVITY |
 998                  MAC_RGMII_MODE_RX_ENG_DET |
 999                  MAC_RGMII_MODE_TX_ENABLE |
1000                  MAC_RGMII_MODE_TX_LOWPWR |
1001                  MAC_RGMII_MODE_TX_RESET);
1002         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1003                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004                         val |= MAC_RGMII_MODE_RX_INT_B |
1005                                MAC_RGMII_MODE_RX_QUALITY |
1006                                MAC_RGMII_MODE_RX_ACTIVITY |
1007                                MAC_RGMII_MODE_RX_ENG_DET;
1008                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009                         val |= MAC_RGMII_MODE_TX_ENABLE |
1010                                MAC_RGMII_MODE_TX_LOWPWR |
1011                                MAC_RGMII_MODE_TX_RESET;
1012         }
1013         tw32(MAC_EXT_RGMII_MODE, val);
1014 }
1015
1016 static void tg3_mdio_start(struct tg3 *tp)
1017 {
1018         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019         tw32_f(MAC_MI_MODE, tp->mi_mode);
1020         udelay(80);
1021
1022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023                 u32 funcnum, is_serdes;
1024
1025                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026                 if (funcnum)
1027                         tp->phy_addr = 2;
1028                 else
1029                         tp->phy_addr = 1;
1030
1031                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032                 if (is_serdes)
1033                         tp->phy_addr += 7;
1034         } else
1035                 tp->phy_addr = TG3_PHY_MII_ADDR;
1036
1037         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039                 tg3_mdio_config_5785(tp);
1040 }
1041
1042 static int tg3_mdio_init(struct tg3 *tp)
1043 {
1044         int i;
1045         u32 reg;
1046         struct phy_device *phydev;
1047
1048         tg3_mdio_start(tp);
1049
1050         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052                 return 0;
1053
1054         tp->mdio_bus = mdiobus_alloc();
1055         if (tp->mdio_bus == NULL)
1056                 return -ENOMEM;
1057
1058         tp->mdio_bus->name     = "tg3 mdio bus";
1059         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1060                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1061         tp->mdio_bus->priv     = tp;
1062         tp->mdio_bus->parent   = &tp->pdev->dev;
1063         tp->mdio_bus->read     = &tg3_mdio_read;
1064         tp->mdio_bus->write    = &tg3_mdio_write;
1065         tp->mdio_bus->reset    = &tg3_mdio_reset;
1066         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1067         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1068
1069         for (i = 0; i < PHY_MAX_ADDR; i++)
1070                 tp->mdio_bus->irq[i] = PHY_POLL;
1071
1072         /* The bus registration will look for all the PHYs on the mdio bus.
1073          * Unfortunately, it does not ensure the PHY is powered up before
1074          * accessing the PHY ID registers.  A chip reset is the
1075          * quickest way to bring the device back to an operational state..
1076          */
1077         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078                 tg3_bmcr_reset(tp);
1079
1080         i = mdiobus_register(tp->mdio_bus);
1081         if (i) {
1082                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083                         tp->dev->name, i);
1084                 mdiobus_free(tp->mdio_bus);
1085                 return i;
1086         }
1087
1088         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1089
1090         if (!phydev || !phydev->drv) {
1091                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092                 mdiobus_unregister(tp->mdio_bus);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return -ENODEV;
1095         }
1096
1097         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1098         case TG3_PHY_ID_BCM57780:
1099                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1100                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1101                 break;
1102         case TG3_PHY_ID_BCM50610:
1103         case TG3_PHY_ID_BCM50610M:
1104                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1105                                      PHY_BRCM_RX_REFCLK_UNUSED |
1106                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1107                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1108                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1109                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1110                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1111                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1112                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1113                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1114                 /* fallthru */
1115         case TG3_PHY_ID_RTL8211C:
1116                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1117                 break;
1118         case TG3_PHY_ID_RTL8201E:
1119         case TG3_PHY_ID_BCMAC131:
1120                 phydev->interface = PHY_INTERFACE_MODE_MII;
1121                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1122                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1123                 break;
1124         }
1125
1126         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1127
1128         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1129                 tg3_mdio_config_5785(tp);
1130
1131         return 0;
1132 }
1133
1134 static void tg3_mdio_fini(struct tg3 *tp)
1135 {
1136         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1137                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1138                 mdiobus_unregister(tp->mdio_bus);
1139                 mdiobus_free(tp->mdio_bus);
1140         }
1141 }
1142
1143 /* tp->lock is held. */
1144 static inline void tg3_generate_fw_event(struct tg3 *tp)
1145 {
1146         u32 val;
1147
1148         val = tr32(GRC_RX_CPU_EVENT);
1149         val |= GRC_RX_CPU_DRIVER_EVENT;
1150         tw32_f(GRC_RX_CPU_EVENT, val);
1151
1152         tp->last_event_jiffies = jiffies;
1153 }
1154
1155 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1156
1157 /* tp->lock is held. */
1158 static void tg3_wait_for_event_ack(struct tg3 *tp)
1159 {
1160         int i;
1161         unsigned int delay_cnt;
1162         long time_remain;
1163
1164         /* If enough time has passed, no wait is necessary. */
1165         time_remain = (long)(tp->last_event_jiffies + 1 +
1166                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1167                       (long)jiffies;
1168         if (time_remain < 0)
1169                 return;
1170
1171         /* Check if we can shorten the wait time. */
1172         delay_cnt = jiffies_to_usecs(time_remain);
1173         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1174                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1175         delay_cnt = (delay_cnt >> 3) + 1;
1176
1177         for (i = 0; i < delay_cnt; i++) {
1178                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1179                         break;
1180                 udelay(8);
1181         }
1182 }
1183
1184 /* tp->lock is held. */
1185 static void tg3_ump_link_report(struct tg3 *tp)
1186 {
1187         u32 reg;
1188         u32 val;
1189
1190         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1191             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1192                 return;
1193
1194         tg3_wait_for_event_ack(tp);
1195
1196         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1197
1198         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1199
1200         val = 0;
1201         if (!tg3_readphy(tp, MII_BMCR, &reg))
1202                 val = reg << 16;
1203         if (!tg3_readphy(tp, MII_BMSR, &reg))
1204                 val |= (reg & 0xffff);
1205         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1206
1207         val = 0;
1208         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1209                 val = reg << 16;
1210         if (!tg3_readphy(tp, MII_LPA, &reg))
1211                 val |= (reg & 0xffff);
1212         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1213
1214         val = 0;
1215         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1216                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1217                         val = reg << 16;
1218                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1219                         val |= (reg & 0xffff);
1220         }
1221         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1222
1223         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1224                 val = reg << 16;
1225         else
1226                 val = 0;
1227         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1228
1229         tg3_generate_fw_event(tp);
1230 }
1231
1232 static void tg3_link_report(struct tg3 *tp)
1233 {
1234         if (!netif_carrier_ok(tp->dev)) {
1235                 if (netif_msg_link(tp))
1236                         printk(KERN_INFO PFX "%s: Link is down.\n",
1237                                tp->dev->name);
1238                 tg3_ump_link_report(tp);
1239         } else if (netif_msg_link(tp)) {
1240                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1241                        tp->dev->name,
1242                        (tp->link_config.active_speed == SPEED_1000 ?
1243                         1000 :
1244                         (tp->link_config.active_speed == SPEED_100 ?
1245                          100 : 10)),
1246                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1247                         "full" : "half"));
1248
1249                 printk(KERN_INFO PFX
1250                        "%s: Flow control is %s for TX and %s for RX.\n",
1251                        tp->dev->name,
1252                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1253                        "on" : "off",
1254                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1255                        "on" : "off");
1256                 tg3_ump_link_report(tp);
1257         }
1258 }
1259
1260 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1261 {
1262         u16 miireg;
1263
1264         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1265                 miireg = ADVERTISE_PAUSE_CAP;
1266         else if (flow_ctrl & FLOW_CTRL_TX)
1267                 miireg = ADVERTISE_PAUSE_ASYM;
1268         else if (flow_ctrl & FLOW_CTRL_RX)
1269                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1270         else
1271                 miireg = 0;
1272
1273         return miireg;
1274 }
1275
1276 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1277 {
1278         u16 miireg;
1279
1280         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1281                 miireg = ADVERTISE_1000XPAUSE;
1282         else if (flow_ctrl & FLOW_CTRL_TX)
1283                 miireg = ADVERTISE_1000XPSE_ASYM;
1284         else if (flow_ctrl & FLOW_CTRL_RX)
1285                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1286         else
1287                 miireg = 0;
1288
1289         return miireg;
1290 }
1291
1292 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1293 {
1294         u8 cap = 0;
1295
1296         if (lcladv & ADVERTISE_1000XPAUSE) {
1297                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1298                         if (rmtadv & LPA_1000XPAUSE)
1299                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1300                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1301                                 cap = FLOW_CTRL_RX;
1302                 } else {
1303                         if (rmtadv & LPA_1000XPAUSE)
1304                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1305                 }
1306         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1308                         cap = FLOW_CTRL_TX;
1309         }
1310
1311         return cap;
1312 }
1313
1314 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1315 {
1316         u8 autoneg;
1317         u8 flowctrl = 0;
1318         u32 old_rx_mode = tp->rx_mode;
1319         u32 old_tx_mode = tp->tx_mode;
1320
1321         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1322                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1323         else
1324                 autoneg = tp->link_config.autoneg;
1325
1326         if (autoneg == AUTONEG_ENABLE &&
1327             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1328                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1329                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1330                 else
1331                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1332         } else
1333                 flowctrl = tp->link_config.flowctrl;
1334
1335         tp->link_config.active_flowctrl = flowctrl;
1336
1337         if (flowctrl & FLOW_CTRL_RX)
1338                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1339         else
1340                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1341
1342         if (old_rx_mode != tp->rx_mode)
1343                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1344
1345         if (flowctrl & FLOW_CTRL_TX)
1346                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1347         else
1348                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1349
1350         if (old_tx_mode != tp->tx_mode)
1351                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1352 }
1353
1354 static void tg3_adjust_link(struct net_device *dev)
1355 {
1356         u8 oldflowctrl, linkmesg = 0;
1357         u32 mac_mode, lcl_adv, rmt_adv;
1358         struct tg3 *tp = netdev_priv(dev);
1359         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1360
1361         spin_lock_bh(&tp->lock);
1362
1363         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1364                                     MAC_MODE_HALF_DUPLEX);
1365
1366         oldflowctrl = tp->link_config.active_flowctrl;
1367
1368         if (phydev->link) {
1369                 lcl_adv = 0;
1370                 rmt_adv = 0;
1371
1372                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1373                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1374                 else if (phydev->speed == SPEED_1000 ||
1375                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1376                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1377                 else
1378                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1379
1380                 if (phydev->duplex == DUPLEX_HALF)
1381                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1382                 else {
1383                         lcl_adv = tg3_advert_flowctrl_1000T(
1384                                   tp->link_config.flowctrl);
1385
1386                         if (phydev->pause)
1387                                 rmt_adv = LPA_PAUSE_CAP;
1388                         if (phydev->asym_pause)
1389                                 rmt_adv |= LPA_PAUSE_ASYM;
1390                 }
1391
1392                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1393         } else
1394                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1395
1396         if (mac_mode != tp->mac_mode) {
1397                 tp->mac_mode = mac_mode;
1398                 tw32_f(MAC_MODE, tp->mac_mode);
1399                 udelay(40);
1400         }
1401
1402         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1403                 if (phydev->speed == SPEED_10)
1404                         tw32(MAC_MI_STAT,
1405                              MAC_MI_STAT_10MBPS_MODE |
1406                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1407                 else
1408                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1409         }
1410
1411         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1412                 tw32(MAC_TX_LENGTHS,
1413                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1414                       (6 << TX_LENGTHS_IPG_SHIFT) |
1415                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1416         else
1417                 tw32(MAC_TX_LENGTHS,
1418                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1419                       (6 << TX_LENGTHS_IPG_SHIFT) |
1420                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1421
1422         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1423             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1424             phydev->speed != tp->link_config.active_speed ||
1425             phydev->duplex != tp->link_config.active_duplex ||
1426             oldflowctrl != tp->link_config.active_flowctrl)
1427             linkmesg = 1;
1428
1429         tp->link_config.active_speed = phydev->speed;
1430         tp->link_config.active_duplex = phydev->duplex;
1431
1432         spin_unlock_bh(&tp->lock);
1433
1434         if (linkmesg)
1435                 tg3_link_report(tp);
1436 }
1437
1438 static int tg3_phy_init(struct tg3 *tp)
1439 {
1440         struct phy_device *phydev;
1441
1442         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1443                 return 0;
1444
1445         /* Bring the PHY back to a known state. */
1446         tg3_bmcr_reset(tp);
1447
1448         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1449
1450         /* Attach the MAC to the PHY. */
1451         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1452                              phydev->dev_flags, phydev->interface);
1453         if (IS_ERR(phydev)) {
1454                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1455                 return PTR_ERR(phydev);
1456         }
1457
1458         /* Mask with MAC supported features. */
1459         switch (phydev->interface) {
1460         case PHY_INTERFACE_MODE_GMII:
1461         case PHY_INTERFACE_MODE_RGMII:
1462                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1463                         phydev->supported &= (PHY_GBIT_FEATURES |
1464                                               SUPPORTED_Pause |
1465                                               SUPPORTED_Asym_Pause);
1466                         break;
1467                 }
1468                 /* fallthru */
1469         case PHY_INTERFACE_MODE_MII:
1470                 phydev->supported &= (PHY_BASIC_FEATURES |
1471                                       SUPPORTED_Pause |
1472                                       SUPPORTED_Asym_Pause);
1473                 break;
1474         default:
1475                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1476                 return -EINVAL;
1477         }
1478
1479         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1480
1481         phydev->advertising = phydev->supported;
1482
1483         return 0;
1484 }
1485
1486 static void tg3_phy_start(struct tg3 *tp)
1487 {
1488         struct phy_device *phydev;
1489
1490         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1491                 return;
1492
1493         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1494
1495         if (tp->link_config.phy_is_low_power) {
1496                 tp->link_config.phy_is_low_power = 0;
1497                 phydev->speed = tp->link_config.orig_speed;
1498                 phydev->duplex = tp->link_config.orig_duplex;
1499                 phydev->autoneg = tp->link_config.orig_autoneg;
1500                 phydev->advertising = tp->link_config.orig_advertising;
1501         }
1502
1503         phy_start(phydev);
1504
1505         phy_start_aneg(phydev);
1506 }
1507
1508 static void tg3_phy_stop(struct tg3 *tp)
1509 {
1510         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511                 return;
1512
1513         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1514 }
1515
1516 static void tg3_phy_fini(struct tg3 *tp)
1517 {
1518         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1519                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1520                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1521         }
1522 }
1523
1524 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1525 {
1526         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1527         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1528 }
1529
1530 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1531 {
1532         u32 phytest;
1533
1534         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1535                 u32 phy;
1536
1537                 tg3_writephy(tp, MII_TG3_FET_TEST,
1538                              phytest | MII_TG3_FET_SHADOW_EN);
1539                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1540                         if (enable)
1541                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1542                         else
1543                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1544                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1545                 }
1546                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1547         }
1548 }
1549
1550 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1551 {
1552         u32 reg;
1553
1554         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1555                 return;
1556
1557         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1558                 tg3_phy_fet_toggle_apd(tp, enable);
1559                 return;
1560         }
1561
1562         reg = MII_TG3_MISC_SHDW_WREN |
1563               MII_TG3_MISC_SHDW_SCR5_SEL |
1564               MII_TG3_MISC_SHDW_SCR5_LPED |
1565               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1566               MII_TG3_MISC_SHDW_SCR5_SDTL |
1567               MII_TG3_MISC_SHDW_SCR5_C125OE;
1568         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1569                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1570
1571         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1572
1573
1574         reg = MII_TG3_MISC_SHDW_WREN |
1575               MII_TG3_MISC_SHDW_APD_SEL |
1576               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1577         if (enable)
1578                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1579
1580         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581 }
1582
1583 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1584 {
1585         u32 phy;
1586
1587         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1588             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1589                 return;
1590
1591         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1592                 u32 ephy;
1593
1594                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1595                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1596
1597                         tg3_writephy(tp, MII_TG3_FET_TEST,
1598                                      ephy | MII_TG3_FET_SHADOW_EN);
1599                         if (!tg3_readphy(tp, reg, &phy)) {
1600                                 if (enable)
1601                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1602                                 else
1603                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1604                                 tg3_writephy(tp, reg, phy);
1605                         }
1606                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1607                 }
1608         } else {
1609                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1610                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1611                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1612                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1613                         if (enable)
1614                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1615                         else
1616                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1617                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1618                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1619                 }
1620         }
1621 }
1622
1623 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1624 {
1625         u32 val;
1626
1627         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1628                 return;
1629
1630         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1631             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1632                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1633                              (val | (1 << 15) | (1 << 4)));
1634 }
1635
1636 static void tg3_phy_apply_otp(struct tg3 *tp)
1637 {
1638         u32 otp, phy;
1639
1640         if (!tp->phy_otp)
1641                 return;
1642
1643         otp = tp->phy_otp;
1644
1645         /* Enable SM_DSP clock and tx 6dB coding. */
1646         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1647               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1648               MII_TG3_AUXCTL_ACTL_TX_6DB;
1649         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1650
1651         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1652         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1653         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1654
1655         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1656               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1657         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1658
1659         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1660         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1661         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1662
1663         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1664         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1665
1666         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1667         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1668
1669         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1670               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1671         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1672
1673         /* Turn off SM_DSP clock. */
1674         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1675               MII_TG3_AUXCTL_ACTL_TX_6DB;
1676         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1677 }
1678
1679 static int tg3_wait_macro_done(struct tg3 *tp)
1680 {
1681         int limit = 100;
1682
1683         while (limit--) {
1684                 u32 tmp32;
1685
1686                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1687                         if ((tmp32 & 0x1000) == 0)
1688                                 break;
1689                 }
1690         }
1691         if (limit < 0)
1692                 return -EBUSY;
1693
1694         return 0;
1695 }
1696
1697 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1698 {
1699         static const u32 test_pat[4][6] = {
1700         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1701         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1702         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1703         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1704         };
1705         int chan;
1706
1707         for (chan = 0; chan < 4; chan++) {
1708                 int i;
1709
1710                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1711                              (chan * 0x2000) | 0x0200);
1712                 tg3_writephy(tp, 0x16, 0x0002);
1713
1714                 for (i = 0; i < 6; i++)
1715                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1716                                      test_pat[chan][i]);
1717
1718                 tg3_writephy(tp, 0x16, 0x0202);
1719                 if (tg3_wait_macro_done(tp)) {
1720                         *resetp = 1;
1721                         return -EBUSY;
1722                 }
1723
1724                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1725                              (chan * 0x2000) | 0x0200);
1726                 tg3_writephy(tp, 0x16, 0x0082);
1727                 if (tg3_wait_macro_done(tp)) {
1728                         *resetp = 1;
1729                         return -EBUSY;
1730                 }
1731
1732                 tg3_writephy(tp, 0x16, 0x0802);
1733                 if (tg3_wait_macro_done(tp)) {
1734                         *resetp = 1;
1735                         return -EBUSY;
1736                 }
1737
1738                 for (i = 0; i < 6; i += 2) {
1739                         u32 low, high;
1740
1741                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1742                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1743                             tg3_wait_macro_done(tp)) {
1744                                 *resetp = 1;
1745                                 return -EBUSY;
1746                         }
1747                         low &= 0x7fff;
1748                         high &= 0x000f;
1749                         if (low != test_pat[chan][i] ||
1750                             high != test_pat[chan][i+1]) {
1751                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1752                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1753                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1754
1755                                 return -EBUSY;
1756                         }
1757                 }
1758         }
1759
1760         return 0;
1761 }
1762
1763 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1764 {
1765         int chan;
1766
1767         for (chan = 0; chan < 4; chan++) {
1768                 int i;
1769
1770                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1771                              (chan * 0x2000) | 0x0200);
1772                 tg3_writephy(tp, 0x16, 0x0002);
1773                 for (i = 0; i < 6; i++)
1774                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1775                 tg3_writephy(tp, 0x16, 0x0202);
1776                 if (tg3_wait_macro_done(tp))
1777                         return -EBUSY;
1778         }
1779
1780         return 0;
1781 }
1782
1783 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1784 {
1785         u32 reg32, phy9_orig;
1786         int retries, do_phy_reset, err;
1787
1788         retries = 10;
1789         do_phy_reset = 1;
1790         do {
1791                 if (do_phy_reset) {
1792                         err = tg3_bmcr_reset(tp);
1793                         if (err)
1794                                 return err;
1795                         do_phy_reset = 0;
1796                 }
1797
1798                 /* Disable transmitter and interrupt.  */
1799                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1800                         continue;
1801
1802                 reg32 |= 0x3000;
1803                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1804
1805                 /* Set full-duplex, 1000 mbps.  */
1806                 tg3_writephy(tp, MII_BMCR,
1807                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1808
1809                 /* Set to master mode.  */
1810                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1811                         continue;
1812
1813                 tg3_writephy(tp, MII_TG3_CTRL,
1814                              (MII_TG3_CTRL_AS_MASTER |
1815                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1816
1817                 /* Enable SM_DSP_CLOCK and 6dB.  */
1818                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1819
1820                 /* Block the PHY control access.  */
1821                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1822                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1823
1824                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1825                 if (!err)
1826                         break;
1827         } while (--retries);
1828
1829         err = tg3_phy_reset_chanpat(tp);
1830         if (err)
1831                 return err;
1832
1833         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1834         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1835
1836         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1837         tg3_writephy(tp, 0x16, 0x0000);
1838
1839         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1840             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1841                 /* Set Extended packet length bit for jumbo frames */
1842                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1843         }
1844         else {
1845                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1846         }
1847
1848         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1849
1850         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1851                 reg32 &= ~0x3000;
1852                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1853         } else if (!err)
1854                 err = -EBUSY;
1855
1856         return err;
1857 }
1858
1859 /* This will reset the tigon3 PHY if there is no valid
1860  * link unless the FORCE argument is non-zero.
1861  */
1862 static int tg3_phy_reset(struct tg3 *tp)
1863 {
1864         u32 cpmuctrl;
1865         u32 phy_status;
1866         int err;
1867
1868         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1869                 u32 val;
1870
1871                 val = tr32(GRC_MISC_CFG);
1872                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1873                 udelay(40);
1874         }
1875         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1876         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1877         if (err != 0)
1878                 return -EBUSY;
1879
1880         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1881                 netif_carrier_off(tp->dev);
1882                 tg3_link_report(tp);
1883         }
1884
1885         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1886             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1887             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1888                 err = tg3_phy_reset_5703_4_5(tp);
1889                 if (err)
1890                         return err;
1891                 goto out;
1892         }
1893
1894         cpmuctrl = 0;
1895         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1896             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1897                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1898                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1899                         tw32(TG3_CPMU_CTRL,
1900                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1901         }
1902
1903         err = tg3_bmcr_reset(tp);
1904         if (err)
1905                 return err;
1906
1907         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1908                 u32 phy;
1909
1910                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1911                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1912
1913                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1914         }
1915
1916         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1917             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1918                 u32 val;
1919
1920                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1921                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1922                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1923                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1924                         udelay(40);
1925                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1926                 }
1927         }
1928
1929         tg3_phy_apply_otp(tp);
1930
1931         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1932                 tg3_phy_toggle_apd(tp, true);
1933         else
1934                 tg3_phy_toggle_apd(tp, false);
1935
1936 out:
1937         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1939                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1940                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1941                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1942                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1943                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1944         }
1945         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1946                 tg3_writephy(tp, 0x1c, 0x8d68);
1947                 tg3_writephy(tp, 0x1c, 0x8d68);
1948         }
1949         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1950                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1951                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1952                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1953                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1954                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1955                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1956                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1957                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958         }
1959         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1961                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1962                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1963                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1964                         tg3_writephy(tp, MII_TG3_TEST1,
1965                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1966                 } else
1967                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1969         }
1970         /* Set Extended packet length bit (bit 14) on all chips that */
1971         /* support jumbo frames */
1972         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1973                 /* Cannot do read-modify-write on 5401 */
1974                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1975         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1976                 u32 phy_reg;
1977
1978                 /* Set bit 14 with read-modify-write to preserve other bits */
1979                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1980                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1981                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1982         }
1983
1984         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1985          * jumbo frames transmission.
1986          */
1987         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1988                 u32 phy_reg;
1989
1990                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1991                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1992                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1993         }
1994
1995         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1996                 /* adjust output voltage */
1997                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1998         }
1999
2000         tg3_phy_toggle_automdix(tp, 1);
2001         tg3_phy_set_wirespeed(tp);
2002         return 0;
2003 }
2004
2005 static void tg3_frob_aux_power(struct tg3 *tp)
2006 {
2007         struct tg3 *tp_peer = tp;
2008
2009         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2010                 return;
2011
2012         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2013             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2015                 struct net_device *dev_peer;
2016
2017                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2018                 /* remove_one() may have been run on the peer. */
2019                 if (!dev_peer)
2020                         tp_peer = tp;
2021                 else
2022                         tp_peer = netdev_priv(dev_peer);
2023         }
2024
2025         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2026             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2027             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2028             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2029                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2030                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2031                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2032                                     (GRC_LCLCTRL_GPIO_OE0 |
2033                                      GRC_LCLCTRL_GPIO_OE1 |
2034                                      GRC_LCLCTRL_GPIO_OE2 |
2035                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2036                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2037                                     100);
2038                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2039                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2040                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2041                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2042                                              GRC_LCLCTRL_GPIO_OE1 |
2043                                              GRC_LCLCTRL_GPIO_OE2 |
2044                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2045                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2046                                              tp->grc_local_ctrl;
2047                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2048
2049                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2050                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2051
2052                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2053                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2054                 } else {
2055                         u32 no_gpio2;
2056                         u32 grc_local_ctrl = 0;
2057
2058                         if (tp_peer != tp &&
2059                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2060                                 return;
2061
2062                         /* Workaround to prevent overdrawing Amps. */
2063                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2064                             ASIC_REV_5714) {
2065                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2066                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067                                             grc_local_ctrl, 100);
2068                         }
2069
2070                         /* On 5753 and variants, GPIO2 cannot be used. */
2071                         no_gpio2 = tp->nic_sram_data_cfg &
2072                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2073
2074                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2075                                          GRC_LCLCTRL_GPIO_OE1 |
2076                                          GRC_LCLCTRL_GPIO_OE2 |
2077                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2078                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2079                         if (no_gpio2) {
2080                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2081                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2082                         }
2083                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2084                                                     grc_local_ctrl, 100);
2085
2086                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2087
2088                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089                                                     grc_local_ctrl, 100);
2090
2091                         if (!no_gpio2) {
2092                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2093                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094                                             grc_local_ctrl, 100);
2095                         }
2096                 }
2097         } else {
2098                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2099                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2100                         if (tp_peer != tp &&
2101                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2102                                 return;
2103
2104                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105                                     (GRC_LCLCTRL_GPIO_OE1 |
2106                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2107
2108                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109                                     GRC_LCLCTRL_GPIO_OE1, 100);
2110
2111                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112                                     (GRC_LCLCTRL_GPIO_OE1 |
2113                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2114                 }
2115         }
2116 }
2117
2118 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2119 {
2120         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2121                 return 1;
2122         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2123                 if (speed != SPEED_10)
2124                         return 1;
2125         } else if (speed == SPEED_10)
2126                 return 1;
2127
2128         return 0;
2129 }
2130
2131 static int tg3_setup_phy(struct tg3 *, int);
2132
2133 #define RESET_KIND_SHUTDOWN     0
2134 #define RESET_KIND_INIT         1
2135 #define RESET_KIND_SUSPEND      2
2136
2137 static void tg3_write_sig_post_reset(struct tg3 *, int);
2138 static int tg3_halt_cpu(struct tg3 *, u32);
2139
2140 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2141 {
2142         u32 val;
2143
2144         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2146                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2147                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2148
2149                         sg_dig_ctrl |=
2150                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2151                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2152                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2153                 }
2154                 return;
2155         }
2156
2157         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2158                 tg3_bmcr_reset(tp);
2159                 val = tr32(GRC_MISC_CFG);
2160                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2161                 udelay(40);
2162                 return;
2163         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2164                 u32 phytest;
2165                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2166                         u32 phy;
2167
2168                         tg3_writephy(tp, MII_ADVERTISE, 0);
2169                         tg3_writephy(tp, MII_BMCR,
2170                                      BMCR_ANENABLE | BMCR_ANRESTART);
2171
2172                         tg3_writephy(tp, MII_TG3_FET_TEST,
2173                                      phytest | MII_TG3_FET_SHADOW_EN);
2174                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2175                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2176                                 tg3_writephy(tp,
2177                                              MII_TG3_FET_SHDW_AUXMODE4,
2178                                              phy);
2179                         }
2180                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2181                 }
2182                 return;
2183         } else if (do_low_power) {
2184                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2185                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2186
2187                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2188                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2189                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2190                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2191                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2192         }
2193
2194         /* The PHY should not be powered down on some chips because
2195          * of bugs.
2196          */
2197         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2198             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2199             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2200              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2201                 return;
2202
2203         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2204             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2205                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2206                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2207                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2208                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2209         }
2210
2211         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2212 }
2213
2214 /* tp->lock is held. */
2215 static int tg3_nvram_lock(struct tg3 *tp)
2216 {
2217         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2218                 int i;
2219
2220                 if (tp->nvram_lock_cnt == 0) {
2221                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2222                         for (i = 0; i < 8000; i++) {
2223                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2224                                         break;
2225                                 udelay(20);
2226                         }
2227                         if (i == 8000) {
2228                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2229                                 return -ENODEV;
2230                         }
2231                 }
2232                 tp->nvram_lock_cnt++;
2233         }
2234         return 0;
2235 }
2236
2237 /* tp->lock is held. */
2238 static void tg3_nvram_unlock(struct tg3 *tp)
2239 {
2240         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2241                 if (tp->nvram_lock_cnt > 0)
2242                         tp->nvram_lock_cnt--;
2243                 if (tp->nvram_lock_cnt == 0)
2244                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2245         }
2246 }
2247
2248 /* tp->lock is held. */
2249 static void tg3_enable_nvram_access(struct tg3 *tp)
2250 {
2251         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2252             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2253                 u32 nvaccess = tr32(NVRAM_ACCESS);
2254
2255                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2256         }
2257 }
2258
2259 /* tp->lock is held. */
2260 static void tg3_disable_nvram_access(struct tg3 *tp)
2261 {
2262         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2263             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2264                 u32 nvaccess = tr32(NVRAM_ACCESS);
2265
2266                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2267         }
2268 }
2269
2270 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2271                                         u32 offset, u32 *val)
2272 {
2273         u32 tmp;
2274         int i;
2275
2276         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2277                 return -EINVAL;
2278
2279         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2280                                         EEPROM_ADDR_DEVID_MASK |
2281                                         EEPROM_ADDR_READ);
2282         tw32(GRC_EEPROM_ADDR,
2283              tmp |
2284              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2285              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2286               EEPROM_ADDR_ADDR_MASK) |
2287              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2288
2289         for (i = 0; i < 1000; i++) {
2290                 tmp = tr32(GRC_EEPROM_ADDR);
2291
2292                 if (tmp & EEPROM_ADDR_COMPLETE)
2293                         break;
2294                 msleep(1);
2295         }
2296         if (!(tmp & EEPROM_ADDR_COMPLETE))
2297                 return -EBUSY;
2298
2299         tmp = tr32(GRC_EEPROM_DATA);
2300
2301         /*
2302          * The data will always be opposite the native endian
2303          * format.  Perform a blind byteswap to compensate.
2304          */
2305         *val = swab32(tmp);
2306
2307         return 0;
2308 }
2309
2310 #define NVRAM_CMD_TIMEOUT 10000
2311
2312 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2313 {
2314         int i;
2315
2316         tw32(NVRAM_CMD, nvram_cmd);
2317         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2318                 udelay(10);
2319                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2320                         udelay(10);
2321                         break;
2322                 }
2323         }
2324
2325         if (i == NVRAM_CMD_TIMEOUT)
2326                 return -EBUSY;
2327
2328         return 0;
2329 }
2330
2331 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2332 {
2333         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2334             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2335             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2336            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2337             (tp->nvram_jedecnum == JEDEC_ATMEL))
2338
2339                 addr = ((addr / tp->nvram_pagesize) <<
2340                         ATMEL_AT45DB0X1B_PAGE_POS) +
2341                        (addr % tp->nvram_pagesize);
2342
2343         return addr;
2344 }
2345
2346 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2347 {
2348         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352             (tp->nvram_jedecnum == JEDEC_ATMEL))
2353
2354                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2355                         tp->nvram_pagesize) +
2356                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2357
2358         return addr;
2359 }
2360
2361 /* NOTE: Data read in from NVRAM is byteswapped according to
2362  * the byteswapping settings for all other register accesses.
2363  * tg3 devices are BE devices, so on a BE machine, the data
2364  * returned will be exactly as it is seen in NVRAM.  On a LE
2365  * machine, the 32-bit value will be byteswapped.
2366  */
2367 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2368 {
2369         int ret;
2370
2371         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2372                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2373
2374         offset = tg3_nvram_phys_addr(tp, offset);
2375
2376         if (offset > NVRAM_ADDR_MSK)
2377                 return -EINVAL;
2378
2379         ret = tg3_nvram_lock(tp);
2380         if (ret)
2381                 return ret;
2382
2383         tg3_enable_nvram_access(tp);
2384
2385         tw32(NVRAM_ADDR, offset);
2386         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2387                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2388
2389         if (ret == 0)
2390                 *val = tr32(NVRAM_RDDATA);
2391
2392         tg3_disable_nvram_access(tp);
2393
2394         tg3_nvram_unlock(tp);
2395
2396         return ret;
2397 }
2398
2399 /* Ensures NVRAM data is in bytestream format. */
2400 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2401 {
2402         u32 v;
2403         int res = tg3_nvram_read(tp, offset, &v);
2404         if (!res)
2405                 *val = cpu_to_be32(v);
2406         return res;
2407 }
2408
2409 /* tp->lock is held. */
2410 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2411 {
2412         u32 addr_high, addr_low;
2413         int i;
2414
2415         addr_high = ((tp->dev->dev_addr[0] << 8) |
2416                      tp->dev->dev_addr[1]);
2417         addr_low = ((tp->dev->dev_addr[2] << 24) |
2418                     (tp->dev->dev_addr[3] << 16) |
2419                     (tp->dev->dev_addr[4] <<  8) |
2420                     (tp->dev->dev_addr[5] <<  0));
2421         for (i = 0; i < 4; i++) {
2422                 if (i == 1 && skip_mac_1)
2423                         continue;
2424                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2425                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2426         }
2427
2428         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2429             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2430                 for (i = 0; i < 12; i++) {
2431                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2432                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2433                 }
2434         }
2435
2436         addr_high = (tp->dev->dev_addr[0] +
2437                      tp->dev->dev_addr[1] +
2438                      tp->dev->dev_addr[2] +
2439                      tp->dev->dev_addr[3] +
2440                      tp->dev->dev_addr[4] +
2441                      tp->dev->dev_addr[5]) &
2442                 TX_BACKOFF_SEED_MASK;
2443         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2444 }
2445
2446 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2447 {
2448         u32 misc_host_ctrl;
2449         bool device_should_wake, do_low_power;
2450
2451         /* Make sure register accesses (indirect or otherwise)
2452          * will function correctly.
2453          */
2454         pci_write_config_dword(tp->pdev,
2455                                TG3PCI_MISC_HOST_CTRL,
2456                                tp->misc_host_ctrl);
2457
2458         switch (state) {
2459         case PCI_D0:
2460                 pci_enable_wake(tp->pdev, state, false);
2461                 pci_set_power_state(tp->pdev, PCI_D0);
2462
2463                 /* Switch out of Vaux if it is a NIC */
2464                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2465                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2466
2467                 return 0;
2468
2469         case PCI_D1:
2470         case PCI_D2:
2471         case PCI_D3hot:
2472                 break;
2473
2474         default:
2475                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2476                         tp->dev->name, state);
2477                 return -EINVAL;
2478         }
2479
2480         /* Restore the CLKREQ setting. */
2481         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2482                 u16 lnkctl;
2483
2484                 pci_read_config_word(tp->pdev,
2485                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2486                                      &lnkctl);
2487                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2488                 pci_write_config_word(tp->pdev,
2489                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2490                                       lnkctl);
2491         }
2492
2493         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2494         tw32(TG3PCI_MISC_HOST_CTRL,
2495              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2496
2497         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2498                              device_may_wakeup(&tp->pdev->dev) &&
2499                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2500
2501         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2502                 do_low_power = false;
2503                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2504                     !tp->link_config.phy_is_low_power) {
2505                         struct phy_device *phydev;
2506                         u32 phyid, advertising;
2507
2508                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2509
2510                         tp->link_config.phy_is_low_power = 1;
2511
2512                         tp->link_config.orig_speed = phydev->speed;
2513                         tp->link_config.orig_duplex = phydev->duplex;
2514                         tp->link_config.orig_autoneg = phydev->autoneg;
2515                         tp->link_config.orig_advertising = phydev->advertising;
2516
2517                         advertising = ADVERTISED_TP |
2518                                       ADVERTISED_Pause |
2519                                       ADVERTISED_Autoneg |
2520                                       ADVERTISED_10baseT_Half;
2521
2522                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2523                             device_should_wake) {
2524                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2525                                         advertising |=
2526                                                 ADVERTISED_100baseT_Half |
2527                                                 ADVERTISED_100baseT_Full |
2528                                                 ADVERTISED_10baseT_Full;
2529                                 else
2530                                         advertising |= ADVERTISED_10baseT_Full;
2531                         }
2532
2533                         phydev->advertising = advertising;
2534
2535                         phy_start_aneg(phydev);
2536
2537                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2538                         if (phyid != TG3_PHY_ID_BCMAC131) {
2539                                 phyid &= TG3_PHY_OUI_MASK;
2540                                 if (phyid == TG3_PHY_OUI_1 ||
2541                                     phyid == TG3_PHY_OUI_2 ||
2542                                     phyid == TG3_PHY_OUI_3)
2543                                         do_low_power = true;
2544                         }
2545                 }
2546         } else {
2547                 do_low_power = true;
2548
2549                 if (tp->link_config.phy_is_low_power == 0) {
2550                         tp->link_config.phy_is_low_power = 1;
2551                         tp->link_config.orig_speed = tp->link_config.speed;
2552                         tp->link_config.orig_duplex = tp->link_config.duplex;
2553                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2554                 }
2555
2556                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2557                         tp->link_config.speed = SPEED_10;
2558                         tp->link_config.duplex = DUPLEX_HALF;
2559                         tp->link_config.autoneg = AUTONEG_ENABLE;
2560                         tg3_setup_phy(tp, 0);
2561                 }
2562         }
2563
2564         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2565                 u32 val;
2566
2567                 val = tr32(GRC_VCPU_EXT_CTRL);
2568                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2569         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2570                 int i;
2571                 u32 val;
2572
2573                 for (i = 0; i < 200; i++) {
2574                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2575                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2576                                 break;
2577                         msleep(1);
2578                 }
2579         }
2580         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2581                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2582                                                      WOL_DRV_STATE_SHUTDOWN |
2583                                                      WOL_DRV_WOL |
2584                                                      WOL_SET_MAGIC_PKT);
2585
2586         if (device_should_wake) {
2587                 u32 mac_mode;
2588
2589                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2590                         if (do_low_power) {
2591                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2592                                 udelay(40);
2593                         }
2594
2595                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2596                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2597                         else
2598                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2599
2600                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2601                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2602                             ASIC_REV_5700) {
2603                                 u32 speed = (tp->tg3_flags &
2604                                              TG3_FLAG_WOL_SPEED_100MB) ?
2605                                              SPEED_100 : SPEED_10;
2606                                 if (tg3_5700_link_polarity(tp, speed))
2607                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2608                                 else
2609                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2610                         }
2611                 } else {
2612                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2613                 }
2614
2615                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2616                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2617
2618                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2619                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2620                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2621                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2622                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2623                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2624
2625                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2626                         mac_mode |= tp->mac_mode &
2627                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2628                         if (mac_mode & MAC_MODE_APE_TX_EN)
2629                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2630                 }
2631
2632                 tw32_f(MAC_MODE, mac_mode);
2633                 udelay(100);
2634
2635                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2636                 udelay(10);
2637         }
2638
2639         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2640             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2641              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2642                 u32 base_val;
2643
2644                 base_val = tp->pci_clock_ctrl;
2645                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2646                              CLOCK_CTRL_TXCLK_DISABLE);
2647
2648                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2649                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2650         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2651                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2652                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2653                 /* do nothing */
2654         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2655                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2656                 u32 newbits1, newbits2;
2657
2658                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2659                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2660                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2661                                     CLOCK_CTRL_TXCLK_DISABLE |
2662                                     CLOCK_CTRL_ALTCLK);
2663                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2664                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2665                         newbits1 = CLOCK_CTRL_625_CORE;
2666                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2667                 } else {
2668                         newbits1 = CLOCK_CTRL_ALTCLK;
2669                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2670                 }
2671
2672                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2673                             40);
2674
2675                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2676                             40);
2677
2678                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2679                         u32 newbits3;
2680
2681                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2682                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2683                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2684                                             CLOCK_CTRL_TXCLK_DISABLE |
2685                                             CLOCK_CTRL_44MHZ_CORE);
2686                         } else {
2687                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2688                         }
2689
2690                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2691                                     tp->pci_clock_ctrl | newbits3, 40);
2692                 }
2693         }
2694
2695         if (!(device_should_wake) &&
2696             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2697                 tg3_power_down_phy(tp, do_low_power);
2698
2699         tg3_frob_aux_power(tp);
2700
2701         /* Workaround for unstable PLL clock */
2702         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2703             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2704                 u32 val = tr32(0x7d00);
2705
2706                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2707                 tw32(0x7d00, val);
2708                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2709                         int err;
2710
2711                         err = tg3_nvram_lock(tp);
2712                         tg3_halt_cpu(tp, RX_CPU_BASE);
2713                         if (!err)
2714                                 tg3_nvram_unlock(tp);
2715                 }
2716         }
2717
2718         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2719
2720         if (device_should_wake)
2721                 pci_enable_wake(tp->pdev, state, true);
2722
2723         /* Finally, set the new power state. */
2724         pci_set_power_state(tp->pdev, state);
2725
2726         return 0;
2727 }
2728
2729 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2730 {
2731         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2732         case MII_TG3_AUX_STAT_10HALF:
2733                 *speed = SPEED_10;
2734                 *duplex = DUPLEX_HALF;
2735                 break;
2736
2737         case MII_TG3_AUX_STAT_10FULL:
2738                 *speed = SPEED_10;
2739                 *duplex = DUPLEX_FULL;
2740                 break;
2741
2742         case MII_TG3_AUX_STAT_100HALF:
2743                 *speed = SPEED_100;
2744                 *duplex = DUPLEX_HALF;
2745                 break;
2746
2747         case MII_TG3_AUX_STAT_100FULL:
2748                 *speed = SPEED_100;
2749                 *duplex = DUPLEX_FULL;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_1000HALF:
2753                 *speed = SPEED_1000;
2754                 *duplex = DUPLEX_HALF;
2755                 break;
2756
2757         case MII_TG3_AUX_STAT_1000FULL:
2758                 *speed = SPEED_1000;
2759                 *duplex = DUPLEX_FULL;
2760                 break;
2761
2762         default:
2763                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2764                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2765                                  SPEED_10;
2766                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2767                                   DUPLEX_HALF;
2768                         break;
2769                 }
2770                 *speed = SPEED_INVALID;
2771                 *duplex = DUPLEX_INVALID;
2772                 break;
2773         }
2774 }
2775
2776 static void tg3_phy_copper_begin(struct tg3 *tp)
2777 {
2778         u32 new_adv;
2779         int i;
2780
2781         if (tp->link_config.phy_is_low_power) {
2782                 /* Entering low power mode.  Disable gigabit and
2783                  * 100baseT advertisements.
2784                  */
2785                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2786
2787                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2788                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2789                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2790                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2791
2792                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2793         } else if (tp->link_config.speed == SPEED_INVALID) {
2794                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2795                         tp->link_config.advertising &=
2796                                 ~(ADVERTISED_1000baseT_Half |
2797                                   ADVERTISED_1000baseT_Full);
2798
2799                 new_adv = ADVERTISE_CSMA;
2800                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2801                         new_adv |= ADVERTISE_10HALF;
2802                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2803                         new_adv |= ADVERTISE_10FULL;
2804                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2805                         new_adv |= ADVERTISE_100HALF;
2806                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2807                         new_adv |= ADVERTISE_100FULL;
2808
2809                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2810
2811                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2812
2813                 if (tp->link_config.advertising &
2814                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2815                         new_adv = 0;
2816                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2817                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2818                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2819                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2820                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2821                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2822                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2823                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2824                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2825                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2826                 } else {
2827                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2828                 }
2829         } else {
2830                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2831                 new_adv |= ADVERTISE_CSMA;
2832
2833                 /* Asking for a specific link mode. */
2834                 if (tp->link_config.speed == SPEED_1000) {
2835                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2836
2837                         if (tp->link_config.duplex == DUPLEX_FULL)
2838                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2839                         else
2840                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2841                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2842                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2843                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2844                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2845                 } else {
2846                         if (tp->link_config.speed == SPEED_100) {
2847                                 if (tp->link_config.duplex == DUPLEX_FULL)
2848                                         new_adv |= ADVERTISE_100FULL;
2849                                 else
2850                                         new_adv |= ADVERTISE_100HALF;
2851                         } else {
2852                                 if (tp->link_config.duplex == DUPLEX_FULL)
2853                                         new_adv |= ADVERTISE_10FULL;
2854                                 else
2855                                         new_adv |= ADVERTISE_10HALF;
2856                         }
2857                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2858
2859                         new_adv = 0;
2860                 }
2861
2862                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2863         }
2864
2865         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2866             tp->link_config.speed != SPEED_INVALID) {
2867                 u32 bmcr, orig_bmcr;
2868
2869                 tp->link_config.active_speed = tp->link_config.speed;
2870                 tp->link_config.active_duplex = tp->link_config.duplex;
2871
2872                 bmcr = 0;
2873                 switch (tp->link_config.speed) {
2874                 default:
2875                 case SPEED_10:
2876                         break;
2877
2878                 case SPEED_100:
2879                         bmcr |= BMCR_SPEED100;
2880                         break;
2881
2882                 case SPEED_1000:
2883                         bmcr |= TG3_BMCR_SPEED1000;
2884                         break;
2885                 }
2886
2887                 if (tp->link_config.duplex == DUPLEX_FULL)
2888                         bmcr |= BMCR_FULLDPLX;
2889
2890                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2891                     (bmcr != orig_bmcr)) {
2892                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2893                         for (i = 0; i < 1500; i++) {
2894                                 u32 tmp;
2895
2896                                 udelay(10);
2897                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2898                                     tg3_readphy(tp, MII_BMSR, &tmp))
2899                                         continue;
2900                                 if (!(tmp & BMSR_LSTATUS)) {
2901                                         udelay(40);
2902                                         break;
2903                                 }
2904                         }
2905                         tg3_writephy(tp, MII_BMCR, bmcr);
2906                         udelay(40);
2907                 }
2908         } else {
2909                 tg3_writephy(tp, MII_BMCR,
2910                              BMCR_ANENABLE | BMCR_ANRESTART);
2911         }
2912 }
2913
2914 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2915 {
2916         int err;
2917
2918         /* Turn off tap power management. */
2919         /* Set Extended packet length bit */
2920         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2921
2922         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2923         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2924
2925         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2926         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2927
2928         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2929         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2930
2931         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2932         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2933
2934         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2935         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2936
2937         udelay(40);
2938
2939         return err;
2940 }
2941
2942 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2943 {
2944         u32 adv_reg, all_mask = 0;
2945
2946         if (mask & ADVERTISED_10baseT_Half)
2947                 all_mask |= ADVERTISE_10HALF;
2948         if (mask & ADVERTISED_10baseT_Full)
2949                 all_mask |= ADVERTISE_10FULL;
2950         if (mask & ADVERTISED_100baseT_Half)
2951                 all_mask |= ADVERTISE_100HALF;
2952         if (mask & ADVERTISED_100baseT_Full)
2953                 all_mask |= ADVERTISE_100FULL;
2954
2955         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2956                 return 0;
2957
2958         if ((adv_reg & all_mask) != all_mask)
2959                 return 0;
2960         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2961                 u32 tg3_ctrl;
2962
2963                 all_mask = 0;
2964                 if (mask & ADVERTISED_1000baseT_Half)
2965                         all_mask |= ADVERTISE_1000HALF;
2966                 if (mask & ADVERTISED_1000baseT_Full)
2967                         all_mask |= ADVERTISE_1000FULL;
2968
2969                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2970                         return 0;
2971
2972                 if ((tg3_ctrl & all_mask) != all_mask)
2973                         return 0;
2974         }
2975         return 1;
2976 }
2977
2978 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2979 {
2980         u32 curadv, reqadv;
2981
2982         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2983                 return 1;
2984
2985         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2986         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2987
2988         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2989                 if (curadv != reqadv)
2990                         return 0;
2991
2992                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2993                         tg3_readphy(tp, MII_LPA, rmtadv);
2994         } else {
2995                 /* Reprogram the advertisement register, even if it
2996                  * does not affect the current link.  If the link
2997                  * gets renegotiated in the future, we can save an
2998                  * additional renegotiation cycle by advertising
2999                  * it correctly in the first place.
3000                  */
3001                 if (curadv != reqadv) {
3002                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3003                                      ADVERTISE_PAUSE_ASYM);
3004                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3005                 }
3006         }
3007
3008         return 1;
3009 }
3010
3011 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3012 {
3013         int current_link_up;
3014         u32 bmsr, dummy;
3015         u32 lcl_adv, rmt_adv;
3016         u16 current_speed;
3017         u8 current_duplex;
3018         int i, err;
3019
3020         tw32(MAC_EVENT, 0);
3021
3022         tw32_f(MAC_STATUS,
3023              (MAC_STATUS_SYNC_CHANGED |
3024               MAC_STATUS_CFG_CHANGED |
3025               MAC_STATUS_MI_COMPLETION |
3026               MAC_STATUS_LNKSTATE_CHANGED));
3027         udelay(40);
3028
3029         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3030                 tw32_f(MAC_MI_MODE,
3031                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3032                 udelay(80);
3033         }
3034
3035         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3036
3037         /* Some third-party PHYs need to be reset on link going
3038          * down.
3039          */
3040         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3041              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3042              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3043             netif_carrier_ok(tp->dev)) {
3044                 tg3_readphy(tp, MII_BMSR, &bmsr);
3045                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3046                     !(bmsr & BMSR_LSTATUS))
3047                         force_reset = 1;
3048         }
3049         if (force_reset)
3050                 tg3_phy_reset(tp);
3051
3052         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3053                 tg3_readphy(tp, MII_BMSR, &bmsr);
3054                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3055                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3056                         bmsr = 0;
3057
3058                 if (!(bmsr & BMSR_LSTATUS)) {
3059                         err = tg3_init_5401phy_dsp(tp);
3060                         if (err)
3061                                 return err;
3062
3063                         tg3_readphy(tp, MII_BMSR, &bmsr);
3064                         for (i = 0; i < 1000; i++) {
3065                                 udelay(10);
3066                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067                                     (bmsr & BMSR_LSTATUS)) {
3068                                         udelay(40);
3069                                         break;
3070                                 }
3071                         }
3072
3073                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3074                             !(bmsr & BMSR_LSTATUS) &&
3075                             tp->link_config.active_speed == SPEED_1000) {
3076                                 err = tg3_phy_reset(tp);
3077                                 if (!err)
3078                                         err = tg3_init_5401phy_dsp(tp);
3079                                 if (err)
3080                                         return err;
3081                         }
3082                 }
3083         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3084                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3085                 /* 5701 {A0,B0} CRC bug workaround */
3086                 tg3_writephy(tp, 0x15, 0x0a75);
3087                 tg3_writephy(tp, 0x1c, 0x8c68);
3088                 tg3_writephy(tp, 0x1c, 0x8d68);
3089                 tg3_writephy(tp, 0x1c, 0x8c68);
3090         }
3091
3092         /* Clear pending interrupts... */
3093         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3094         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3095
3096         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3097                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3098         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3099                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3100
3101         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3102             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3103                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3104                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3105                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3106                 else
3107                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3108         }
3109
3110         current_link_up = 0;
3111         current_speed = SPEED_INVALID;
3112         current_duplex = DUPLEX_INVALID;
3113
3114         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3115                 u32 val;
3116
3117                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119                 if (!(val & (1 << 10))) {
3120                         val |= (1 << 10);
3121                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3122                         goto relink;
3123                 }
3124         }
3125
3126         bmsr = 0;
3127         for (i = 0; i < 100; i++) {
3128                 tg3_readphy(tp, MII_BMSR, &bmsr);
3129                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130                     (bmsr & BMSR_LSTATUS))
3131                         break;
3132                 udelay(40);
3133         }
3134
3135         if (bmsr & BMSR_LSTATUS) {
3136                 u32 aux_stat, bmcr;
3137
3138                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139                 for (i = 0; i < 2000; i++) {
3140                         udelay(10);
3141                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3142                             aux_stat)
3143                                 break;
3144                 }
3145
3146                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3147                                              &current_speed,
3148                                              &current_duplex);
3149
3150                 bmcr = 0;
3151                 for (i = 0; i < 200; i++) {
3152                         tg3_readphy(tp, MII_BMCR, &bmcr);
3153                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3154                                 continue;
3155                         if (bmcr && bmcr != 0x7fff)
3156                                 break;
3157                         udelay(10);
3158                 }
3159
3160                 lcl_adv = 0;
3161                 rmt_adv = 0;
3162
3163                 tp->link_config.active_speed = current_speed;
3164                 tp->link_config.active_duplex = current_duplex;
3165
3166                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167                         if ((bmcr & BMCR_ANENABLE) &&
3168                             tg3_copper_is_advertising_all(tp,
3169                                                 tp->link_config.advertising)) {
3170                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3171                                                                   &rmt_adv))
3172                                         current_link_up = 1;
3173                         }
3174                 } else {
3175                         if (!(bmcr & BMCR_ANENABLE) &&
3176                             tp->link_config.speed == current_speed &&
3177                             tp->link_config.duplex == current_duplex &&
3178                             tp->link_config.flowctrl ==
3179                             tp->link_config.active_flowctrl) {
3180                                 current_link_up = 1;
3181                         }
3182                 }
3183
3184                 if (current_link_up == 1 &&
3185                     tp->link_config.active_duplex == DUPLEX_FULL)
3186                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3187         }
3188
3189 relink:
3190         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3191                 u32 tmp;
3192
3193                 tg3_phy_copper_begin(tp);
3194
3195                 tg3_readphy(tp, MII_BMSR, &tmp);
3196                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3197                     (tmp & BMSR_LSTATUS))
3198                         current_link_up = 1;
3199         }
3200
3201         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3202         if (current_link_up == 1) {
3203                 if (tp->link_config.active_speed == SPEED_100 ||
3204                     tp->link_config.active_speed == SPEED_10)
3205                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3206                 else
3207                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3208         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3209                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3210         else
3211                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3212
3213         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3214         if (tp->link_config.active_duplex == DUPLEX_HALF)
3215                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3216
3217         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3218                 if (current_link_up == 1 &&
3219                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3220                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3221                 else
3222                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3223         }
3224
3225         /* ??? Without this setting Netgear GA302T PHY does not
3226          * ??? send/receive packets...
3227          */
3228         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3229             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3230                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3231                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3232                 udelay(80);
3233         }
3234
3235         tw32_f(MAC_MODE, tp->mac_mode);
3236         udelay(40);
3237
3238         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3239                 /* Polled via timer. */
3240                 tw32_f(MAC_EVENT, 0);
3241         } else {
3242                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3243         }
3244         udelay(40);
3245
3246         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3247             current_link_up == 1 &&
3248             tp->link_config.active_speed == SPEED_1000 &&
3249             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3250              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3251                 udelay(120);
3252                 tw32_f(MAC_STATUS,
3253                      (MAC_STATUS_SYNC_CHANGED |
3254                       MAC_STATUS_CFG_CHANGED));
3255                 udelay(40);
3256                 tg3_write_mem(tp,
3257                               NIC_SRAM_FIRMWARE_MBOX,
3258                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3259         }
3260
3261         /* Prevent send BD corruption. */
3262         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3263                 u16 oldlnkctl, newlnkctl;
3264
3265                 pci_read_config_word(tp->pdev,
3266                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3267                                      &oldlnkctl);
3268                 if (tp->link_config.active_speed == SPEED_100 ||
3269                     tp->link_config.active_speed == SPEED_10)
3270                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3271                 else
3272                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3273                 if (newlnkctl != oldlnkctl)
3274                         pci_write_config_word(tp->pdev,
3275                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3276                                               newlnkctl);
3277         }
3278
3279         if (current_link_up != netif_carrier_ok(tp->dev)) {
3280                 if (current_link_up)
3281                         netif_carrier_on(tp->dev);
3282                 else
3283                         netif_carrier_off(tp->dev);
3284                 tg3_link_report(tp);
3285         }
3286
3287         return 0;
3288 }
3289
3290 struct tg3_fiber_aneginfo {
3291         int state;
3292 #define ANEG_STATE_UNKNOWN              0
3293 #define ANEG_STATE_AN_ENABLE            1
3294 #define ANEG_STATE_RESTART_INIT         2
3295 #define ANEG_STATE_RESTART              3
3296 #define ANEG_STATE_DISABLE_LINK_OK      4
3297 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3298 #define ANEG_STATE_ABILITY_DETECT       6
3299 #define ANEG_STATE_ACK_DETECT_INIT      7
3300 #define ANEG_STATE_ACK_DETECT           8
3301 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3302 #define ANEG_STATE_COMPLETE_ACK         10
3303 #define ANEG_STATE_IDLE_DETECT_INIT     11
3304 #define ANEG_STATE_IDLE_DETECT          12
3305 #define ANEG_STATE_LINK_OK              13
3306 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3307 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3308
3309         u32 flags;
3310 #define MR_AN_ENABLE            0x00000001
3311 #define MR_RESTART_AN           0x00000002
3312 #define MR_AN_COMPLETE          0x00000004
3313 #define MR_PAGE_RX              0x00000008
3314 #define MR_NP_LOADED            0x00000010
3315 #define MR_TOGGLE_TX            0x00000020
3316 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3317 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3318 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3319 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3320 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3321 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3322 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3323 #define MR_TOGGLE_RX            0x00002000
3324 #define MR_NP_RX                0x00004000
3325
3326 #define MR_LINK_OK              0x80000000
3327
3328         unsigned long link_time, cur_time;
3329
3330         u32 ability_match_cfg;
3331         int ability_match_count;
3332
3333         char ability_match, idle_match, ack_match;
3334
3335         u32 txconfig, rxconfig;
3336 #define ANEG_CFG_NP             0x00000080
3337 #define ANEG_CFG_ACK            0x00000040
3338 #define ANEG_CFG_RF2            0x00000020
3339 #define ANEG_CFG_RF1            0x00000010
3340 #define ANEG_CFG_PS2            0x00000001
3341 #define ANEG_CFG_PS1            0x00008000
3342 #define ANEG_CFG_HD             0x00004000
3343 #define ANEG_CFG_FD             0x00002000
3344 #define ANEG_CFG_INVAL          0x00001f06
3345
3346 };
3347 #define ANEG_OK         0
3348 #define ANEG_DONE       1
3349 #define ANEG_TIMER_ENAB 2
3350 #define ANEG_FAILED     -1
3351
3352 #define ANEG_STATE_SETTLE_TIME  10000
3353
3354 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3355                                    struct tg3_fiber_aneginfo *ap)
3356 {
3357         u16 flowctrl;
3358         unsigned long delta;
3359         u32 rx_cfg_reg;
3360         int ret;
3361
3362         if (ap->state == ANEG_STATE_UNKNOWN) {
3363                 ap->rxconfig = 0;
3364                 ap->link_time = 0;
3365                 ap->cur_time = 0;
3366                 ap->ability_match_cfg = 0;
3367                 ap->ability_match_count = 0;
3368                 ap->ability_match = 0;
3369                 ap->idle_match = 0;
3370                 ap->ack_match = 0;
3371         }
3372         ap->cur_time++;
3373
3374         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3375                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3376
3377                 if (rx_cfg_reg != ap->ability_match_cfg) {
3378                         ap->ability_match_cfg = rx_cfg_reg;
3379                         ap->ability_match = 0;
3380                         ap->ability_match_count = 0;
3381                 } else {
3382                         if (++ap->ability_match_count > 1) {
3383                                 ap->ability_match = 1;
3384                                 ap->ability_match_cfg = rx_cfg_reg;
3385                         }
3386                 }
3387                 if (rx_cfg_reg & ANEG_CFG_ACK)
3388                         ap->ack_match = 1;
3389                 else
3390                         ap->ack_match = 0;
3391
3392                 ap->idle_match = 0;
3393         } else {
3394                 ap->idle_match = 1;
3395                 ap->ability_match_cfg = 0;
3396                 ap->ability_match_count = 0;
3397                 ap->ability_match = 0;
3398                 ap->ack_match = 0;
3399
3400                 rx_cfg_reg = 0;
3401         }
3402
3403         ap->rxconfig = rx_cfg_reg;
3404         ret = ANEG_OK;
3405
3406         switch(ap->state) {
3407         case ANEG_STATE_UNKNOWN:
3408                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3409                         ap->state = ANEG_STATE_AN_ENABLE;
3410
3411                 /* fallthru */
3412         case ANEG_STATE_AN_ENABLE:
3413                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3414                 if (ap->flags & MR_AN_ENABLE) {
3415                         ap->link_time = 0;
3416                         ap->cur_time = 0;
3417                         ap->ability_match_cfg = 0;
3418                         ap->ability_match_count = 0;
3419                         ap->ability_match = 0;
3420                         ap->idle_match = 0;
3421                         ap->ack_match = 0;
3422
3423                         ap->state = ANEG_STATE_RESTART_INIT;
3424                 } else {
3425                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3426                 }
3427                 break;
3428
3429         case ANEG_STATE_RESTART_INIT:
3430                 ap->link_time = ap->cur_time;
3431                 ap->flags &= ~(MR_NP_LOADED);
3432                 ap->txconfig = 0;
3433                 tw32(MAC_TX_AUTO_NEG, 0);
3434                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3435                 tw32_f(MAC_MODE, tp->mac_mode);
3436                 udelay(40);
3437
3438                 ret = ANEG_TIMER_ENAB;
3439                 ap->state = ANEG_STATE_RESTART;
3440
3441                 /* fallthru */
3442         case ANEG_STATE_RESTART:
3443                 delta = ap->cur_time - ap->link_time;
3444                 if (delta > ANEG_STATE_SETTLE_TIME) {
3445                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3446                 } else {
3447                         ret = ANEG_TIMER_ENAB;
3448                 }
3449                 break;
3450
3451         case ANEG_STATE_DISABLE_LINK_OK:
3452                 ret = ANEG_DONE;
3453                 break;
3454
3455         case ANEG_STATE_ABILITY_DETECT_INIT:
3456                 ap->flags &= ~(MR_TOGGLE_TX);
3457                 ap->txconfig = ANEG_CFG_FD;
3458                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3459                 if (flowctrl & ADVERTISE_1000XPAUSE)
3460                         ap->txconfig |= ANEG_CFG_PS1;
3461                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3462                         ap->txconfig |= ANEG_CFG_PS2;
3463                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3464                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3465                 tw32_f(MAC_MODE, tp->mac_mode);
3466                 udelay(40);
3467
3468                 ap->state = ANEG_STATE_ABILITY_DETECT;
3469                 break;
3470
3471         case ANEG_STATE_ABILITY_DETECT:
3472                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3473                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3474                 }
3475                 break;
3476
3477         case ANEG_STATE_ACK_DETECT_INIT:
3478                 ap->txconfig |= ANEG_CFG_ACK;
3479                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3480                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3481                 tw32_f(MAC_MODE, tp->mac_mode);
3482                 udelay(40);
3483
3484                 ap->state = ANEG_STATE_ACK_DETECT;
3485
3486                 /* fallthru */
3487         case ANEG_STATE_ACK_DETECT:
3488                 if (ap->ack_match != 0) {
3489                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3490                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3491                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3492                         } else {
3493                                 ap->state = ANEG_STATE_AN_ENABLE;
3494                         }
3495                 } else if (ap->ability_match != 0 &&
3496                            ap->rxconfig == 0) {
3497                         ap->state = ANEG_STATE_AN_ENABLE;
3498                 }
3499                 break;
3500
3501         case ANEG_STATE_COMPLETE_ACK_INIT:
3502                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3503                         ret = ANEG_FAILED;
3504                         break;
3505                 }
3506                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3507                                MR_LP_ADV_HALF_DUPLEX |
3508                                MR_LP_ADV_SYM_PAUSE |
3509                                MR_LP_ADV_ASYM_PAUSE |
3510                                MR_LP_ADV_REMOTE_FAULT1 |
3511                                MR_LP_ADV_REMOTE_FAULT2 |
3512                                MR_LP_ADV_NEXT_PAGE |
3513                                MR_TOGGLE_RX |
3514                                MR_NP_RX);
3515                 if (ap->rxconfig & ANEG_CFG_FD)
3516                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3517                 if (ap->rxconfig & ANEG_CFG_HD)
3518                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3519                 if (ap->rxconfig & ANEG_CFG_PS1)
3520                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3521                 if (ap->rxconfig & ANEG_CFG_PS2)
3522                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3523                 if (ap->rxconfig & ANEG_CFG_RF1)
3524                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3525                 if (ap->rxconfig & ANEG_CFG_RF2)
3526                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3527                 if (ap->rxconfig & ANEG_CFG_NP)
3528                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3529
3530                 ap->link_time = ap->cur_time;
3531
3532                 ap->flags ^= (MR_TOGGLE_TX);
3533                 if (ap->rxconfig & 0x0008)
3534                         ap->flags |= MR_TOGGLE_RX;
3535                 if (ap->rxconfig & ANEG_CFG_NP)
3536                         ap->flags |= MR_NP_RX;
3537                 ap->flags |= MR_PAGE_RX;
3538
3539                 ap->state = ANEG_STATE_COMPLETE_ACK;
3540                 ret = ANEG_TIMER_ENAB;
3541                 break;
3542
3543         case ANEG_STATE_COMPLETE_ACK:
3544                 if (ap->ability_match != 0 &&
3545                     ap->rxconfig == 0) {
3546                         ap->state = ANEG_STATE_AN_ENABLE;
3547                         break;
3548                 }
3549                 delta = ap->cur_time - ap->link_time;
3550                 if (delta > ANEG_STATE_SETTLE_TIME) {
3551                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3552                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553                         } else {
3554                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3555                                     !(ap->flags & MR_NP_RX)) {
3556                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3557                                 } else {
3558                                         ret = ANEG_FAILED;
3559                                 }
3560                         }
3561                 }
3562                 break;
3563
3564         case ANEG_STATE_IDLE_DETECT_INIT:
3565                 ap->link_time = ap->cur_time;
3566                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3567                 tw32_f(MAC_MODE, tp->mac_mode);
3568                 udelay(40);
3569
3570                 ap->state = ANEG_STATE_IDLE_DETECT;
3571                 ret = ANEG_TIMER_ENAB;
3572                 break;
3573
3574         case ANEG_STATE_IDLE_DETECT:
3575                 if (ap->ability_match != 0 &&
3576                     ap->rxconfig == 0) {
3577                         ap->state = ANEG_STATE_AN_ENABLE;
3578                         break;
3579                 }
3580                 delta = ap->cur_time - ap->link_time;
3581                 if (delta > ANEG_STATE_SETTLE_TIME) {
3582                         /* XXX another gem from the Broadcom driver :( */
3583                         ap->state = ANEG_STATE_LINK_OK;
3584                 }
3585                 break;
3586
3587         case ANEG_STATE_LINK_OK:
3588                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3589                 ret = ANEG_DONE;
3590                 break;
3591
3592         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3593                 /* ??? unimplemented */
3594                 break;
3595
3596         case ANEG_STATE_NEXT_PAGE_WAIT:
3597                 /* ??? unimplemented */
3598                 break;
3599
3600         default:
3601                 ret = ANEG_FAILED;
3602                 break;
3603         }
3604
3605         return ret;
3606 }
3607
3608 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3609 {
3610         int res = 0;
3611         struct tg3_fiber_aneginfo aninfo;
3612         int status = ANEG_FAILED;
3613         unsigned int tick;
3614         u32 tmp;
3615
3616         tw32_f(MAC_TX_AUTO_NEG, 0);
3617
3618         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3619         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3620         udelay(40);
3621
3622         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3623         udelay(40);
3624
3625         memset(&aninfo, 0, sizeof(aninfo));
3626         aninfo.flags |= MR_AN_ENABLE;
3627         aninfo.state = ANEG_STATE_UNKNOWN;
3628         aninfo.cur_time = 0;
3629         tick = 0;
3630         while (++tick < 195000) {
3631                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3632                 if (status == ANEG_DONE || status == ANEG_FAILED)
3633                         break;
3634
3635                 udelay(1);
3636         }
3637
3638         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3639         tw32_f(MAC_MODE, tp->mac_mode);
3640         udelay(40);
3641
3642         *txflags = aninfo.txconfig;
3643         *rxflags = aninfo.flags;
3644
3645         if (status == ANEG_DONE &&
3646             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3647                              MR_LP_ADV_FULL_DUPLEX)))
3648                 res = 1;
3649
3650         return res;
3651 }
3652
3653 static void tg3_init_bcm8002(struct tg3 *tp)
3654 {
3655         u32 mac_status = tr32(MAC_STATUS);
3656         int i;
3657
3658         /* Reset when initting first time or we have a link. */
3659         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3660             !(mac_status & MAC_STATUS_PCS_SYNCED))
3661                 return;
3662
3663         /* Set PLL lock range. */
3664         tg3_writephy(tp, 0x16, 0x8007);
3665
3666         /* SW reset */
3667         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3668
3669         /* Wait for reset to complete. */
3670         /* XXX schedule_timeout() ... */
3671         for (i = 0; i < 500; i++)
3672                 udelay(10);
3673
3674         /* Config mode; select PMA/Ch 1 regs. */
3675         tg3_writephy(tp, 0x10, 0x8411);
3676
3677         /* Enable auto-lock and comdet, select txclk for tx. */
3678         tg3_writephy(tp, 0x11, 0x0a10);
3679
3680         tg3_writephy(tp, 0x18, 0x00a0);
3681         tg3_writephy(tp, 0x16, 0x41ff);
3682
3683         /* Assert and deassert POR. */
3684         tg3_writephy(tp, 0x13, 0x0400);
3685         udelay(40);
3686         tg3_writephy(tp, 0x13, 0x0000);
3687
3688         tg3_writephy(tp, 0x11, 0x0a50);
3689         udelay(40);
3690         tg3_writephy(tp, 0x11, 0x0a10);
3691
3692         /* Wait for signal to stabilize */
3693         /* XXX schedule_timeout() ... */
3694         for (i = 0; i < 15000; i++)
3695                 udelay(10);
3696
3697         /* Deselect the channel register so we can read the PHYID
3698          * later.
3699          */
3700         tg3_writephy(tp, 0x10, 0x8011);
3701 }
3702
3703 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3704 {
3705         u16 flowctrl;
3706         u32 sg_dig_ctrl, sg_dig_status;
3707         u32 serdes_cfg, expected_sg_dig_ctrl;
3708         int workaround, port_a;
3709         int current_link_up;
3710
3711         serdes_cfg = 0;
3712         expected_sg_dig_ctrl = 0;
3713         workaround = 0;
3714         port_a = 1;
3715         current_link_up = 0;
3716
3717         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3718             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3719                 workaround = 1;
3720                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3721                         port_a = 0;
3722
3723                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3724                 /* preserve bits 20-23 for voltage regulator */
3725                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3726         }
3727
3728         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3729
3730         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3731                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3732                         if (workaround) {
3733                                 u32 val = serdes_cfg;
3734
3735                                 if (port_a)
3736                                         val |= 0xc010000;
3737                                 else
3738                                         val |= 0x4010000;
3739                                 tw32_f(MAC_SERDES_CFG, val);
3740                         }
3741
3742                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3743                 }
3744                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3745                         tg3_setup_flow_control(tp, 0, 0);
3746                         current_link_up = 1;
3747                 }
3748                 goto out;
3749         }
3750
3751         /* Want auto-negotiation.  */
3752         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3753
3754         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3755         if (flowctrl & ADVERTISE_1000XPAUSE)
3756                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3757         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3758                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3759
3760         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3761                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3762                     tp->serdes_counter &&
3763                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3764                                     MAC_STATUS_RCVD_CFG)) ==
3765                      MAC_STATUS_PCS_SYNCED)) {
3766                         tp->serdes_counter--;
3767                         current_link_up = 1;
3768                         goto out;
3769                 }
3770 restart_autoneg:
3771                 if (workaround)
3772                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3773                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3774                 udelay(5);
3775                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3776
3777                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3778                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3779         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3780                                  MAC_STATUS_SIGNAL_DET)) {
3781                 sg_dig_status = tr32(SG_DIG_STATUS);
3782                 mac_status = tr32(MAC_STATUS);
3783
3784                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3785                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3786                         u32 local_adv = 0, remote_adv = 0;
3787
3788                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3789                                 local_adv |= ADVERTISE_1000XPAUSE;
3790                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3791                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3792
3793                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3794                                 remote_adv |= LPA_1000XPAUSE;
3795                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3796                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3797
3798                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3799                         current_link_up = 1;
3800                         tp->serdes_counter = 0;
3801                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3802                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3803                         if (tp->serdes_counter)
3804                                 tp->serdes_counter--;
3805                         else {
3806                                 if (workaround) {
3807                                         u32 val = serdes_cfg;
3808
3809                                         if (port_a)
3810                                                 val |= 0xc010000;
3811                                         else
3812                                                 val |= 0x4010000;
3813
3814                                         tw32_f(MAC_SERDES_CFG, val);
3815                                 }
3816
3817                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3818                                 udelay(40);
3819
3820                                 /* Link parallel detection - link is up */
3821                                 /* only if we have PCS_SYNC and not */
3822                                 /* receiving config code words */
3823                                 mac_status = tr32(MAC_STATUS);
3824                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3825                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3826                                         tg3_setup_flow_control(tp, 0, 0);
3827                                         current_link_up = 1;
3828                                         tp->tg3_flags2 |=
3829                                                 TG3_FLG2_PARALLEL_DETECT;
3830                                         tp->serdes_counter =
3831                                                 SERDES_PARALLEL_DET_TIMEOUT;
3832                                 } else
3833                                         goto restart_autoneg;
3834                         }
3835                 }
3836         } else {
3837                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3838                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3839         }
3840
3841 out:
3842         return current_link_up;
3843 }
3844
3845 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3846 {
3847         int current_link_up = 0;
3848
3849         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3850                 goto out;
3851
3852         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3853                 u32 txflags, rxflags;
3854                 int i;
3855
3856                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3857                         u32 local_adv = 0, remote_adv = 0;
3858
3859                         if (txflags & ANEG_CFG_PS1)
3860                                 local_adv |= ADVERTISE_1000XPAUSE;
3861                         if (txflags & ANEG_CFG_PS2)
3862                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3863
3864                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3865                                 remote_adv |= LPA_1000XPAUSE;
3866                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3867                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3868
3869                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3870
3871                         current_link_up = 1;
3872                 }
3873                 for (i = 0; i < 30; i++) {
3874                         udelay(20);
3875                         tw32_f(MAC_STATUS,
3876                                (MAC_STATUS_SYNC_CHANGED |
3877                                 MAC_STATUS_CFG_CHANGED));
3878                         udelay(40);
3879                         if ((tr32(MAC_STATUS) &
3880                              (MAC_STATUS_SYNC_CHANGED |
3881                               MAC_STATUS_CFG_CHANGED)) == 0)
3882                                 break;
3883                 }
3884
3885                 mac_status = tr32(MAC_STATUS);
3886                 if (current_link_up == 0 &&
3887                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3888                     !(mac_status & MAC_STATUS_RCVD_CFG))
3889                         current_link_up = 1;
3890         } else {
3891                 tg3_setup_flow_control(tp, 0, 0);
3892
3893                 /* Forcing 1000FD link up. */
3894                 current_link_up = 1;
3895
3896                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3897                 udelay(40);
3898
3899                 tw32_f(MAC_MODE, tp->mac_mode);
3900                 udelay(40);
3901         }
3902
3903 out:
3904         return current_link_up;
3905 }
3906
3907 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3908 {
3909         u32 orig_pause_cfg;
3910         u16 orig_active_speed;
3911         u8 orig_active_duplex;
3912         u32 mac_status;
3913         int current_link_up;
3914         int i;
3915
3916         orig_pause_cfg = tp->link_config.active_flowctrl;
3917         orig_active_speed = tp->link_config.active_speed;
3918         orig_active_duplex = tp->link_config.active_duplex;
3919
3920         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3921             netif_carrier_ok(tp->dev) &&
3922             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3923                 mac_status = tr32(MAC_STATUS);
3924                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3925                                MAC_STATUS_SIGNAL_DET |
3926                                MAC_STATUS_CFG_CHANGED |
3927                                MAC_STATUS_RCVD_CFG);
3928                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3929                                    MAC_STATUS_SIGNAL_DET)) {
3930                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3931                                             MAC_STATUS_CFG_CHANGED));
3932                         return 0;
3933                 }
3934         }
3935
3936         tw32_f(MAC_TX_AUTO_NEG, 0);
3937
3938         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3939         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3940         tw32_f(MAC_MODE, tp->mac_mode);
3941         udelay(40);
3942
3943         if (tp->phy_id == PHY_ID_BCM8002)
3944                 tg3_init_bcm8002(tp);
3945
3946         /* Enable link change event even when serdes polling.  */
3947         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3948         udelay(40);
3949
3950         current_link_up = 0;
3951         mac_status = tr32(MAC_STATUS);
3952
3953         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3954                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3955         else
3956                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3957
3958         tp->napi[0].hw_status->status =
3959                 (SD_STATUS_UPDATED |
3960                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3961
3962         for (i = 0; i < 100; i++) {
3963                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3964                                     MAC_STATUS_CFG_CHANGED));
3965                 udelay(5);
3966                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3967                                          MAC_STATUS_CFG_CHANGED |
3968                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3969                         break;
3970         }
3971
3972         mac_status = tr32(MAC_STATUS);
3973         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3974                 current_link_up = 0;
3975                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3976                     tp->serdes_counter == 0) {
3977                         tw32_f(MAC_MODE, (tp->mac_mode |
3978                                           MAC_MODE_SEND_CONFIGS));
3979                         udelay(1);
3980                         tw32_f(MAC_MODE, tp->mac_mode);
3981                 }
3982         }
3983
3984         if (current_link_up == 1) {
3985                 tp->link_config.active_speed = SPEED_1000;
3986                 tp->link_config.active_duplex = DUPLEX_FULL;
3987                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3988                                     LED_CTRL_LNKLED_OVERRIDE |
3989                                     LED_CTRL_1000MBPS_ON));
3990         } else {
3991                 tp->link_config.active_speed = SPEED_INVALID;
3992                 tp->link_config.active_duplex = DUPLEX_INVALID;
3993                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3994                                     LED_CTRL_LNKLED_OVERRIDE |
3995                                     LED_CTRL_TRAFFIC_OVERRIDE));
3996         }
3997
3998         if (current_link_up != netif_carrier_ok(tp->dev)) {
3999                 if (current_link_up)
4000                         netif_carrier_on(tp->dev);
4001                 else
4002                         netif_carrier_off(tp->dev);
4003                 tg3_link_report(tp);
4004         } else {
4005                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4006                 if (orig_pause_cfg != now_pause_cfg ||
4007                     orig_active_speed != tp->link_config.active_speed ||
4008                     orig_active_duplex != tp->link_config.active_duplex)
4009                         tg3_link_report(tp);
4010         }
4011
4012         return 0;
4013 }
4014
4015 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4016 {
4017         int current_link_up, err = 0;
4018         u32 bmsr, bmcr;
4019         u16 current_speed;
4020         u8 current_duplex;
4021         u32 local_adv, remote_adv;
4022
4023         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4024         tw32_f(MAC_MODE, tp->mac_mode);
4025         udelay(40);
4026
4027         tw32(MAC_EVENT, 0);
4028
4029         tw32_f(MAC_STATUS,
4030              (MAC_STATUS_SYNC_CHANGED |
4031               MAC_STATUS_CFG_CHANGED |
4032               MAC_STATUS_MI_COMPLETION |
4033               MAC_STATUS_LNKSTATE_CHANGED));
4034         udelay(40);
4035
4036         if (force_reset)
4037                 tg3_phy_reset(tp);
4038
4039         current_link_up = 0;
4040         current_speed = SPEED_INVALID;
4041         current_duplex = DUPLEX_INVALID;
4042
4043         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4044         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4045         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4046                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4047                         bmsr |= BMSR_LSTATUS;
4048                 else
4049                         bmsr &= ~BMSR_LSTATUS;
4050         }
4051
4052         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4053
4054         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4055             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4056                 /* do nothing, just check for link up at the end */
4057         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4058                 u32 adv, new_adv;
4059
4060                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4061                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4062                                   ADVERTISE_1000XPAUSE |
4063                                   ADVERTISE_1000XPSE_ASYM |
4064                                   ADVERTISE_SLCT);
4065
4066                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4067
4068                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4069                         new_adv |= ADVERTISE_1000XHALF;
4070                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4071                         new_adv |= ADVERTISE_1000XFULL;
4072
4073                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4074                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4075                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4076                         tg3_writephy(tp, MII_BMCR, bmcr);
4077
4078                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4079                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4080                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4081
4082                         return err;
4083                 }
4084         } else {
4085                 u32 new_bmcr;
4086
4087                 bmcr &= ~BMCR_SPEED1000;
4088                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4089
4090                 if (tp->link_config.duplex == DUPLEX_FULL)
4091                         new_bmcr |= BMCR_FULLDPLX;
4092
4093                 if (new_bmcr != bmcr) {
4094                         /* BMCR_SPEED1000 is a reserved bit that needs
4095                          * to be set on write.
4096                          */
4097                         new_bmcr |= BMCR_SPEED1000;
4098
4099                         /* Force a linkdown */
4100                         if (netif_carrier_ok(tp->dev)) {
4101                                 u32 adv;
4102
4103                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4104                                 adv &= ~(ADVERTISE_1000XFULL |
4105                                          ADVERTISE_1000XHALF |
4106                                          ADVERTISE_SLCT);
4107                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4108                                 tg3_writephy(tp, MII_BMCR, bmcr |
4109                                                            BMCR_ANRESTART |
4110                                                            BMCR_ANENABLE);
4111                                 udelay(10);
4112                                 netif_carrier_off(tp->dev);
4113                         }
4114                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4115                         bmcr = new_bmcr;
4116                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4117                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4118                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4119                             ASIC_REV_5714) {
4120                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4121                                         bmsr |= BMSR_LSTATUS;
4122                                 else
4123                                         bmsr &= ~BMSR_LSTATUS;
4124                         }
4125                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126                 }
4127         }
4128
4129         if (bmsr & BMSR_LSTATUS) {
4130                 current_speed = SPEED_1000;
4131                 current_link_up = 1;
4132                 if (bmcr & BMCR_FULLDPLX)
4133                         current_duplex = DUPLEX_FULL;
4134                 else
4135                         current_duplex = DUPLEX_HALF;
4136
4137                 local_adv = 0;
4138                 remote_adv = 0;
4139
4140                 if (bmcr & BMCR_ANENABLE) {
4141                         u32 common;
4142
4143                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4144                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4145                         common = local_adv & remote_adv;
4146                         if (common & (ADVERTISE_1000XHALF |
4147                                       ADVERTISE_1000XFULL)) {
4148                                 if (common & ADVERTISE_1000XFULL)
4149                                         current_duplex = DUPLEX_FULL;
4150                                 else
4151                                         current_duplex = DUPLEX_HALF;
4152                         }
4153                         else
4154                                 current_link_up = 0;
4155                 }
4156         }
4157
4158         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4159                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4160
4161         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4162         if (tp->link_config.active_duplex == DUPLEX_HALF)
4163                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4164
4165         tw32_f(MAC_MODE, tp->mac_mode);
4166         udelay(40);
4167
4168         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4169
4170         tp->link_config.active_speed = current_speed;
4171         tp->link_config.active_duplex = current_duplex;
4172
4173         if (current_link_up != netif_carrier_ok(tp->dev)) {
4174                 if (current_link_up)
4175                         netif_carrier_on(tp->dev);
4176                 else {
4177                         netif_carrier_off(tp->dev);
4178                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4179                 }
4180                 tg3_link_report(tp);
4181         }
4182         return err;
4183 }
4184
4185 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4186 {
4187         if (tp->serdes_counter) {
4188                 /* Give autoneg time to complete. */
4189                 tp->serdes_counter--;
4190                 return;
4191         }
4192         if (!netif_carrier_ok(tp->dev) &&
4193             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4194                 u32 bmcr;
4195
4196                 tg3_readphy(tp, MII_BMCR, &bmcr);
4197                 if (bmcr & BMCR_ANENABLE) {
4198                         u32 phy1, phy2;
4199
4200                         /* Select shadow register 0x1f */
4201                         tg3_writephy(tp, 0x1c, 0x7c00);
4202                         tg3_readphy(tp, 0x1c, &phy1);
4203
4204                         /* Select expansion interrupt status register */
4205                         tg3_writephy(tp, 0x17, 0x0f01);
4206                         tg3_readphy(tp, 0x15, &phy2);
4207                         tg3_readphy(tp, 0x15, &phy2);
4208
4209                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210                                 /* We have signal detect and not receiving
4211                                  * config code words, link is up by parallel
4212                                  * detection.
4213                                  */
4214
4215                                 bmcr &= ~BMCR_ANENABLE;
4216                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217                                 tg3_writephy(tp, MII_BMCR, bmcr);
4218                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4219                         }
4220                 }
4221         }
4222         else if (netif_carrier_ok(tp->dev) &&
4223                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4224                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4225                 u32 phy2;
4226
4227                 /* Select expansion interrupt status register */
4228                 tg3_writephy(tp, 0x17, 0x0f01);
4229                 tg3_readphy(tp, 0x15, &phy2);
4230                 if (phy2 & 0x20) {
4231                         u32 bmcr;
4232
4233                         /* Config code words received, turn on autoneg. */
4234                         tg3_readphy(tp, MII_BMCR, &bmcr);
4235                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4236
4237                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4238
4239                 }
4240         }
4241 }
4242
4243 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4244 {
4245         int err;
4246
4247         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4248                 err = tg3_setup_fiber_phy(tp, force_reset);
4249         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4250                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4251         } else {
4252                 err = tg3_setup_copper_phy(tp, force_reset);
4253         }
4254
4255         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4256                 u32 val, scale;
4257
4258                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4259                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4260                         scale = 65;
4261                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4262                         scale = 6;
4263                 else
4264                         scale = 12;
4265
4266                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4267                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4268                 tw32(GRC_MISC_CFG, val);
4269         }
4270
4271         if (tp->link_config.active_speed == SPEED_1000 &&
4272             tp->link_config.active_duplex == DUPLEX_HALF)
4273                 tw32(MAC_TX_LENGTHS,
4274                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275                       (6 << TX_LENGTHS_IPG_SHIFT) |
4276                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277         else
4278                 tw32(MAC_TX_LENGTHS,
4279                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4280                       (6 << TX_LENGTHS_IPG_SHIFT) |
4281                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4282
4283         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4284                 if (netif_carrier_ok(tp->dev)) {
4285                         tw32(HOSTCC_STAT_COAL_TICKS,
4286                              tp->coal.stats_block_coalesce_usecs);
4287                 } else {
4288                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4289                 }
4290         }
4291
4292         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4293                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4294                 if (!netif_carrier_ok(tp->dev))
4295                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4296                               tp->pwrmgmt_thresh;
4297                 else
4298                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4299                 tw32(PCIE_PWR_MGMT_THRESH, val);
4300         }
4301
4302         return err;
4303 }
4304
4305 /* This is called whenever we suspect that the system chipset is re-
4306  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4307  * is bogus tx completions. We try to recover by setting the
4308  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4309  * in the workqueue.
4310  */
4311 static void tg3_tx_recover(struct tg3 *tp)
4312 {
4313         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4314                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4315
4316         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4317                "mapped I/O cycles to the network device, attempting to "
4318                "recover. Please report the problem to the driver maintainer "
4319                "and include system chipset information.\n", tp->dev->name);
4320
4321         spin_lock(&tp->lock);
4322         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4323         spin_unlock(&tp->lock);
4324 }
4325
4326 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4327 {
4328         smp_mb();
4329         return tnapi->tx_pending -
4330                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4331 }
4332
4333 /* Tigon3 never reports partial packet sends.  So we do not
4334  * need special logic to handle SKBs that have not had all
4335  * of their frags sent yet, like SunGEM does.
4336  */
4337 static void tg3_tx(struct tg3_napi *tnapi)
4338 {
4339         struct tg3 *tp = tnapi->tp;
4340         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4341         u32 sw_idx = tnapi->tx_cons;
4342         struct netdev_queue *txq;
4343         int index = tnapi - tp->napi;
4344
4345         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4346                 index--;
4347
4348         txq = netdev_get_tx_queue(tp->dev, index);
4349
4350         while (sw_idx != hw_idx) {
4351                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4352                 struct sk_buff *skb = ri->skb;
4353                 int i, tx_bug = 0;
4354
4355                 if (unlikely(skb == NULL)) {
4356                         tg3_tx_recover(tp);
4357                         return;
4358                 }
4359
4360                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4361
4362                 ri->skb = NULL;
4363
4364                 sw_idx = NEXT_TX(sw_idx);
4365
4366                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4367                         ri = &tnapi->tx_buffers[sw_idx];
4368                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4369                                 tx_bug = 1;
4370                         sw_idx = NEXT_TX(sw_idx);
4371                 }
4372
4373                 dev_kfree_skb(skb);
4374
4375                 if (unlikely(tx_bug)) {
4376                         tg3_tx_recover(tp);
4377                         return;
4378                 }
4379         }
4380
4381         tnapi->tx_cons = sw_idx;
4382
4383         /* Need to make the tx_cons update visible to tg3_start_xmit()
4384          * before checking for netif_queue_stopped().  Without the
4385          * memory barrier, there is a small possibility that tg3_start_xmit()
4386          * will miss it and cause the queue to be stopped forever.
4387          */
4388         smp_mb();
4389
4390         if (unlikely(netif_tx_queue_stopped(txq) &&
4391                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4392                 __netif_tx_lock(txq, smp_processor_id());
4393                 if (netif_tx_queue_stopped(txq) &&
4394                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4395                         netif_tx_wake_queue(txq);
4396                 __netif_tx_unlock(txq);
4397         }
4398 }
4399
4400 /* Returns size of skb allocated or < 0 on error.
4401  *
4402  * We only need to fill in the address because the other members
4403  * of the RX descriptor are invariant, see tg3_init_rings.
4404  *
4405  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4406  * posting buffers we only dirty the first cache line of the RX
4407  * descriptor (containing the address).  Whereas for the RX status
4408  * buffers the cpu only reads the last cacheline of the RX descriptor
4409  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4410  */
4411 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4412                             int src_idx, u32 dest_idx_unmasked)
4413 {
4414         struct tg3 *tp = tnapi->tp;
4415         struct tg3_rx_buffer_desc *desc;
4416         struct ring_info *map, *src_map;
4417         struct sk_buff *skb;
4418         dma_addr_t mapping;
4419         int skb_size, dest_idx;
4420         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4421
4422         src_map = NULL;
4423         switch (opaque_key) {
4424         case RXD_OPAQUE_RING_STD:
4425                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4426                 desc = &tpr->rx_std[dest_idx];
4427                 map = &tpr->rx_std_buffers[dest_idx];
4428                 if (src_idx >= 0)
4429                         src_map = &tpr->rx_std_buffers[src_idx];
4430                 skb_size = tp->rx_pkt_map_sz;
4431                 break;
4432
4433         case RXD_OPAQUE_RING_JUMBO:
4434                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4435                 desc = &tpr->rx_jmb[dest_idx].std;
4436                 map = &tpr->rx_jmb_buffers[dest_idx];
4437                 if (src_idx >= 0)
4438                         src_map = &tpr->rx_jmb_buffers[src_idx];
4439                 skb_size = TG3_RX_JMB_MAP_SZ;
4440                 break;
4441
4442         default:
4443                 return -EINVAL;
4444         }
4445
4446         /* Do not overwrite any of the map or rp information
4447          * until we are sure we can commit to a new buffer.
4448          *
4449          * Callers depend upon this behavior and assume that
4450          * we leave everything unchanged if we fail.
4451          */
4452         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4453         if (skb == NULL)
4454                 return -ENOMEM;
4455
4456         skb_reserve(skb, tp->rx_offset);
4457
4458         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4459                                  PCI_DMA_FROMDEVICE);
4460         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4461                 dev_kfree_skb(skb);
4462                 return -EIO;
4463         }
4464
4465         map->skb = skb;
4466         pci_unmap_addr_set(map, mapping, mapping);
4467
4468         if (src_map != NULL)
4469                 src_map->skb = NULL;
4470
4471         desc->addr_hi = ((u64)mapping >> 32);
4472         desc->addr_lo = ((u64)mapping & 0xffffffff);
4473
4474         return skb_size;
4475 }
4476
4477 /* We only need to move over in the address because the other
4478  * members of the RX descriptor are invariant.  See notes above
4479  * tg3_alloc_rx_skb for full details.
4480  */
4481 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4482                            int src_idx, u32 dest_idx_unmasked)
4483 {
4484         struct tg3 *tp = tnapi->tp;
4485         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4486         struct ring_info *src_map, *dest_map;
4487         int dest_idx;
4488         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4489
4490         switch (opaque_key) {
4491         case RXD_OPAQUE_RING_STD:
4492                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4493                 dest_desc = &tpr->rx_std[dest_idx];
4494                 dest_map = &tpr->rx_std_buffers[dest_idx];
4495                 src_desc = &tpr->rx_std[src_idx];
4496                 src_map = &tpr->rx_std_buffers[src_idx];
4497                 break;
4498
4499         case RXD_OPAQUE_RING_JUMBO:
4500                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4501                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4502                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4503                 src_desc = &tpr->rx_jmb[src_idx].std;
4504                 src_map = &tpr->rx_jmb_buffers[src_idx];
4505                 break;
4506
4507         default:
4508                 return;
4509         }
4510
4511         dest_map->skb = src_map->skb;
4512         pci_unmap_addr_set(dest_map, mapping,
4513                            pci_unmap_addr(src_map, mapping));
4514         dest_desc->addr_hi = src_desc->addr_hi;
4515         dest_desc->addr_lo = src_desc->addr_lo;
4516
4517         src_map->skb = NULL;
4518 }
4519
4520 /* The RX ring scheme is composed of multiple rings which post fresh
4521  * buffers to the chip, and one special ring the chip uses to report
4522  * status back to the host.
4523  *
4524  * The special ring reports the status of received packets to the
4525  * host.  The chip does not write into the original descriptor the
4526  * RX buffer was obtained from.  The chip simply takes the original
4527  * descriptor as provided by the host, updates the status and length
4528  * field, then writes this into the next status ring entry.
4529  *
4530  * Each ring the host uses to post buffers to the chip is described
4531  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4532  * it is first placed into the on-chip ram.  When the packet's length
4533  * is known, it walks down the TG3_BDINFO entries to select the ring.
4534  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4535  * which is within the range of the new packet's length is chosen.
4536  *
4537  * The "separate ring for rx status" scheme may sound queer, but it makes
4538  * sense from a cache coherency perspective.  If only the host writes
4539  * to the buffer post rings, and only the chip writes to the rx status
4540  * rings, then cache lines never move beyond shared-modified state.
4541  * If both the host and chip were to write into the same ring, cache line
4542  * eviction could occur since both entities want it in an exclusive state.
4543  */
4544 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4545 {
4546         struct tg3 *tp = tnapi->tp;
4547         u32 work_mask, rx_std_posted = 0;
4548         u32 sw_idx = tnapi->rx_rcb_ptr;
4549         u16 hw_idx;
4550         int received;
4551         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4552
4553         hw_idx = *(tnapi->rx_rcb_prod_idx);
4554         /*
4555          * We need to order the read of hw_idx and the read of
4556          * the opaque cookie.
4557          */
4558         rmb();
4559         work_mask = 0;
4560         received = 0;
4561         while (sw_idx != hw_idx && budget > 0) {
4562                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4563                 unsigned int len;
4564                 struct sk_buff *skb;
4565                 dma_addr_t dma_addr;
4566                 u32 opaque_key, desc_idx, *post_ptr;
4567
4568                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4569                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4570                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4571                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4572                         dma_addr = pci_unmap_addr(ri, mapping);
4573                         skb = ri->skb;
4574                         post_ptr = &tpr->rx_std_ptr;
4575                         rx_std_posted++;
4576                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4577                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4578                         dma_addr = pci_unmap_addr(ri, mapping);
4579                         skb = ri->skb;
4580                         post_ptr = &tpr->rx_jmb_ptr;
4581                 } else
4582                         goto next_pkt_nopost;
4583
4584                 work_mask |= opaque_key;
4585
4586                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4587                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4588                 drop_it:
4589                         tg3_recycle_rx(tnapi, opaque_key,
4590                                        desc_idx, *post_ptr);
4591                 drop_it_no_recycle:
4592                         /* Other statistics kept track of by card. */
4593                         tp->net_stats.rx_dropped++;
4594                         goto next_pkt;
4595                 }
4596
4597                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4598                       ETH_FCS_LEN;
4599
4600                 if (len > RX_COPY_THRESHOLD
4601                         && tp->rx_offset == NET_IP_ALIGN
4602                         /* rx_offset will likely not equal NET_IP_ALIGN
4603                          * if this is a 5701 card running in PCI-X mode
4604                          * [see tg3_get_invariants()]
4605                          */
4606                 ) {
4607                         int skb_size;
4608
4609                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4610                                                     desc_idx, *post_ptr);
4611                         if (skb_size < 0)
4612                                 goto drop_it;
4613
4614                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4615                                          PCI_DMA_FROMDEVICE);
4616
4617                         skb_put(skb, len);
4618                 } else {
4619                         struct sk_buff *copy_skb;
4620
4621                         tg3_recycle_rx(tnapi, opaque_key,
4622                                        desc_idx, *post_ptr);
4623
4624                         copy_skb = netdev_alloc_skb(tp->dev,
4625                                                     len + TG3_RAW_IP_ALIGN);
4626                         if (copy_skb == NULL)
4627                                 goto drop_it_no_recycle;
4628
4629                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4630                         skb_put(copy_skb, len);
4631                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4632                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4633                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4634
4635                         /* We'll reuse the original ring buffer. */
4636                         skb = copy_skb;
4637                 }
4638
4639                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4640                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4641                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4642                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4643                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4644                 else
4645                         skb->ip_summed = CHECKSUM_NONE;
4646
4647                 skb->protocol = eth_type_trans(skb, tp->dev);
4648
4649                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4650                     skb->protocol != htons(ETH_P_8021Q)) {
4651                         dev_kfree_skb(skb);
4652                         goto next_pkt;
4653                 }
4654
4655 #if TG3_VLAN_TAG_USED
4656                 if (tp->vlgrp != NULL &&
4657                     desc->type_flags & RXD_FLAG_VLAN) {
4658                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4659                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4660                 } else
4661 #endif
4662                         napi_gro_receive(&tnapi->napi, skb);
4663
4664                 received++;
4665                 budget--;
4666
4667 next_pkt:
4668                 (*post_ptr)++;
4669
4670                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4671                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4672
4673                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4674                                      TG3_64BIT_REG_LOW, idx);
4675                         work_mask &= ~RXD_OPAQUE_RING_STD;
4676                         rx_std_posted = 0;
4677                 }
4678 next_pkt_nopost:
4679                 sw_idx++;
4680                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4681
4682                 /* Refresh hw_idx to see if there is new work */
4683                 if (sw_idx == hw_idx) {
4684                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4685                         rmb();
4686                 }
4687         }
4688
4689         /* ACK the status ring. */
4690         tnapi->rx_rcb_ptr = sw_idx;
4691         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4692
4693         /* Refill RX ring(s). */
4694         if (work_mask & RXD_OPAQUE_RING_STD) {
4695                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4696                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4697                              sw_idx);
4698         }
4699         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4700                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4701                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4702                              sw_idx);
4703         }
4704         mmiowb();
4705
4706         return received;
4707 }
4708
4709 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4710 {
4711         struct tg3 *tp = tnapi->tp;
4712         struct tg3_hw_status *sblk = tnapi->hw_status;
4713
4714         /* handle link change and other phy events */
4715         if (!(tp->tg3_flags &
4716               (TG3_FLAG_USE_LINKCHG_REG |
4717                TG3_FLAG_POLL_SERDES))) {
4718                 if (sblk->status & SD_STATUS_LINK_CHG) {
4719                         sblk->status = SD_STATUS_UPDATED |
4720                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4721                         spin_lock(&tp->lock);
4722                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4723                                 tw32_f(MAC_STATUS,
4724                                      (MAC_STATUS_SYNC_CHANGED |
4725                                       MAC_STATUS_CFG_CHANGED |
4726                                       MAC_STATUS_MI_COMPLETION |
4727                                       MAC_STATUS_LNKSTATE_CHANGED));
4728                                 udelay(40);
4729                         } else
4730                                 tg3_setup_phy(tp, 0);
4731                         spin_unlock(&tp->lock);
4732                 }
4733         }
4734
4735         /* run TX completion thread */
4736         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4737                 tg3_tx(tnapi);
4738                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4739                         return work_done;
4740         }
4741
4742         /* run RX thread, within the bounds set by NAPI.
4743          * All RX "locking" is done by ensuring outside
4744          * code synchronizes with tg3->napi.poll()
4745          */
4746         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4747                 work_done += tg3_rx(tnapi, budget - work_done);
4748
4749         return work_done;
4750 }
4751
4752 static int tg3_poll(struct napi_struct *napi, int budget)
4753 {
4754         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4755         struct tg3 *tp = tnapi->tp;
4756         int work_done = 0;
4757         struct tg3_hw_status *sblk = tnapi->hw_status;
4758
4759         while (1) {
4760                 work_done = tg3_poll_work(tnapi, work_done, budget);
4761
4762                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4763                         goto tx_recovery;
4764
4765                 if (unlikely(work_done >= budget))
4766                         break;
4767
4768                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4769                         /* tp->last_tag is used in tg3_int_reenable() below
4770                          * to tell the hw how much work has been processed,
4771                          * so we must read it before checking for more work.
4772                          */
4773                         tnapi->last_tag = sblk->status_tag;
4774                         tnapi->last_irq_tag = tnapi->last_tag;
4775                         rmb();
4776                 } else
4777                         sblk->status &= ~SD_STATUS_UPDATED;
4778
4779                 if (likely(!tg3_has_work(tnapi))) {
4780                         napi_complete(napi);
4781                         tg3_int_reenable(tnapi);
4782                         break;
4783                 }
4784         }
4785
4786         return work_done;
4787
4788 tx_recovery:
4789         /* work_done is guaranteed to be less than budget. */
4790         napi_complete(napi);
4791         schedule_work(&tp->reset_task);
4792         return work_done;
4793 }
4794
4795 static void tg3_irq_quiesce(struct tg3 *tp)
4796 {
4797         int i;
4798
4799         BUG_ON(tp->irq_sync);
4800
4801         tp->irq_sync = 1;
4802         smp_mb();
4803
4804         for (i = 0; i < tp->irq_cnt; i++)
4805                 synchronize_irq(tp->napi[i].irq_vec);
4806 }
4807
4808 static inline int tg3_irq_sync(struct tg3 *tp)
4809 {
4810         return tp->irq_sync;
4811 }
4812
4813 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4814  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4815  * with as well.  Most of the time, this is not necessary except when
4816  * shutting down the device.
4817  */
4818 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4819 {
4820         spin_lock_bh(&tp->lock);
4821         if (irq_sync)
4822                 tg3_irq_quiesce(tp);
4823 }
4824
4825 static inline void tg3_full_unlock(struct tg3 *tp)
4826 {
4827         spin_unlock_bh(&tp->lock);
4828 }
4829
4830 /* One-shot MSI handler - Chip automatically disables interrupt
4831  * after sending MSI so driver doesn't have to do it.
4832  */
4833 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4834 {
4835         struct tg3_napi *tnapi = dev_id;
4836         struct tg3 *tp = tnapi->tp;
4837
4838         prefetch(tnapi->hw_status);
4839         if (tnapi->rx_rcb)
4840                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4841
4842         if (likely(!tg3_irq_sync(tp)))
4843                 napi_schedule(&tnapi->napi);
4844
4845         return IRQ_HANDLED;
4846 }
4847
4848 /* MSI ISR - No need to check for interrupt sharing and no need to
4849  * flush status block and interrupt mailbox. PCI ordering rules
4850  * guarantee that MSI will arrive after the status block.
4851  */
4852 static irqreturn_t tg3_msi(int irq, void *dev_id)
4853 {
4854         struct tg3_napi *tnapi = dev_id;
4855         struct tg3 *tp = tnapi->tp;
4856
4857         prefetch(tnapi->hw_status);
4858         if (tnapi->rx_rcb)
4859                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4860         /*
4861          * Writing any value to intr-mbox-0 clears PCI INTA# and
4862          * chip-internal interrupt pending events.
4863          * Writing non-zero to intr-mbox-0 additional tells the
4864          * NIC to stop sending us irqs, engaging "in-intr-handler"
4865          * event coalescing.
4866          */
4867         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4868         if (likely(!tg3_irq_sync(tp)))
4869                 napi_schedule(&tnapi->napi);
4870
4871         return IRQ_RETVAL(1);
4872 }
4873
4874 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4875 {
4876         struct tg3_napi *tnapi = dev_id;
4877         struct tg3 *tp = tnapi->tp;
4878         struct tg3_hw_status *sblk = tnapi->hw_status;
4879         unsigned int handled = 1;
4880
4881         /* In INTx mode, it is possible for the interrupt to arrive at
4882          * the CPU before the status block posted prior to the interrupt.
4883          * Reading the PCI State register will confirm whether the
4884          * interrupt is ours and will flush the status block.
4885          */
4886         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4887                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4888                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4889                         handled = 0;
4890                         goto out;
4891                 }
4892         }
4893
4894         /*
4895          * Writing any value to intr-mbox-0 clears PCI INTA# and
4896          * chip-internal interrupt pending events.
4897          * Writing non-zero to intr-mbox-0 additional tells the
4898          * NIC to stop sending us irqs, engaging "in-intr-handler"
4899          * event coalescing.
4900          *
4901          * Flush the mailbox to de-assert the IRQ immediately to prevent
4902          * spurious interrupts.  The flush impacts performance but
4903          * excessive spurious interrupts can be worse in some cases.
4904          */
4905         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4906         if (tg3_irq_sync(tp))
4907                 goto out;
4908         sblk->status &= ~SD_STATUS_UPDATED;
4909         if (likely(tg3_has_work(tnapi))) {
4910                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4911                 napi_schedule(&tnapi->napi);
4912         } else {
4913                 /* No work, shared interrupt perhaps?  re-enable
4914                  * interrupts, and flush that PCI write
4915                  */
4916                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4917                                0x00000000);
4918         }
4919 out:
4920         return IRQ_RETVAL(handled);
4921 }
4922
4923 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4924 {
4925         struct tg3_napi *tnapi = dev_id;
4926         struct tg3 *tp = tnapi->tp;
4927         struct tg3_hw_status *sblk = tnapi->hw_status;
4928         unsigned int handled = 1;
4929
4930         /* In INTx mode, it is possible for the interrupt to arrive at
4931          * the CPU before the status block posted prior to the interrupt.
4932          * Reading the PCI State register will confirm whether the
4933          * interrupt is ours and will flush the status block.
4934          */
4935         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4936                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4937                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4938                         handled = 0;
4939                         goto out;
4940                 }
4941         }
4942
4943         /*
4944          * writing any value to intr-mbox-0 clears PCI INTA# and
4945          * chip-internal interrupt pending events.
4946          * writing non-zero to intr-mbox-0 additional tells the
4947          * NIC to stop sending us irqs, engaging "in-intr-handler"
4948          * event coalescing.
4949          *
4950          * Flush the mailbox to de-assert the IRQ immediately to prevent
4951          * spurious interrupts.  The flush impacts performance but
4952          * excessive spurious interrupts can be worse in some cases.
4953          */
4954         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4955
4956         /*
4957          * In a shared interrupt configuration, sometimes other devices'
4958          * interrupts will scream.  We record the current status tag here
4959          * so that the above check can report that the screaming interrupts
4960          * are unhandled.  Eventually they will be silenced.
4961          */
4962         tnapi->last_irq_tag = sblk->status_tag;
4963
4964         if (tg3_irq_sync(tp))
4965                 goto out;
4966
4967         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4968
4969         napi_schedule(&tnapi->napi);
4970
4971 out:
4972         return IRQ_RETVAL(handled);
4973 }
4974
4975 /* ISR for interrupt test */
4976 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4977 {
4978         struct tg3_napi *tnapi = dev_id;
4979         struct tg3 *tp = tnapi->tp;
4980         struct tg3_hw_status *sblk = tnapi->hw_status;
4981
4982         if ((sblk->status & SD_STATUS_UPDATED) ||
4983             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4984                 tg3_disable_ints(tp);
4985                 return IRQ_RETVAL(1);
4986         }
4987         return IRQ_RETVAL(0);
4988 }
4989
4990 static int tg3_init_hw(struct tg3 *, int);
4991 static int tg3_halt(struct tg3 *, int, int);
4992
4993 /* Restart hardware after configuration changes, self-test, etc.
4994  * Invoked with tp->lock held.
4995  */
4996 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4997         __releases(tp->lock)
4998         __acquires(tp->lock)
4999 {
5000         int err;
5001
5002         err = tg3_init_hw(tp, reset_phy);
5003         if (err) {
5004                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5005                        "aborting.\n", tp->dev->name);
5006                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5007                 tg3_full_unlock(tp);
5008                 del_timer_sync(&tp->timer);
5009                 tp->irq_sync = 0;
5010                 tg3_napi_enable(tp);
5011                 dev_close(tp->dev);
5012                 tg3_full_lock(tp, 0);
5013         }
5014         return err;
5015 }
5016
5017 #ifdef CONFIG_NET_POLL_CONTROLLER
5018 static void tg3_poll_controller(struct net_device *dev)
5019 {
5020         int i;
5021         struct tg3 *tp = netdev_priv(dev);
5022
5023         for (i = 0; i < tp->irq_cnt; i++)
5024                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5025 }
5026 #endif
5027
5028 static void tg3_reset_task(struct work_struct *work)
5029 {
5030         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5031         int err;
5032         unsigned int restart_timer;
5033
5034         tg3_full_lock(tp, 0);
5035
5036         if (!netif_running(tp->dev)) {
5037                 tg3_full_unlock(tp);
5038                 return;
5039         }
5040
5041         tg3_full_unlock(tp);
5042
5043         tg3_phy_stop(tp);
5044
5045         tg3_netif_stop(tp);
5046
5047         tg3_full_lock(tp, 1);
5048
5049         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5050         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5051
5052         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5053                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5054                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5055                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5056                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5057         }
5058
5059         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5060         err = tg3_init_hw(tp, 1);
5061         if (err)
5062                 goto out;
5063
5064         tg3_netif_start(tp);
5065
5066         if (restart_timer)
5067                 mod_timer(&tp->timer, jiffies + 1);
5068
5069 out:
5070         tg3_full_unlock(tp);
5071
5072         if (!err)
5073                 tg3_phy_start(tp);
5074 }
5075
5076 static void tg3_dump_short_state(struct tg3 *tp)
5077 {
5078         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5079                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5080         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5081                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5082 }
5083
5084 static void tg3_tx_timeout(struct net_device *dev)
5085 {
5086         struct tg3 *tp = netdev_priv(dev);
5087
5088         if (netif_msg_tx_err(tp)) {
5089                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5090                        dev->name);
5091                 tg3_dump_short_state(tp);
5092         }
5093
5094         schedule_work(&tp->reset_task);
5095 }
5096
5097 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5098 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5099 {
5100         u32 base = (u32) mapping & 0xffffffff;
5101
5102         return ((base > 0xffffdcc0) &&
5103                 (base + len + 8 < base));
5104 }
5105
5106 /* Test for DMA addresses > 40-bit */
5107 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5108                                           int len)
5109 {
5110 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5111         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5112                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5113         return 0;
5114 #else
5115         return 0;
5116 #endif
5117 }
5118
5119 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5120
5121 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5122 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5123                                        u32 last_plus_one, u32 *start,
5124                                        u32 base_flags, u32 mss)
5125 {
5126         struct tg3_napi *tnapi = &tp->napi[0];
5127         struct sk_buff *new_skb;
5128         dma_addr_t new_addr = 0;
5129         u32 entry = *start;
5130         int i, ret = 0;
5131
5132         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5133                 new_skb = skb_copy(skb, GFP_ATOMIC);
5134         else {
5135                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5136
5137                 new_skb = skb_copy_expand(skb,
5138                                           skb_headroom(skb) + more_headroom,
5139                                           skb_tailroom(skb), GFP_ATOMIC);
5140         }
5141
5142         if (!new_skb) {
5143                 ret = -1;
5144         } else {
5145                 /* New SKB is guaranteed to be linear. */
5146                 entry = *start;
5147                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5148                 new_addr = skb_shinfo(new_skb)->dma_head;
5149
5150                 /* Make sure new skb does not cross any 4G boundaries.
5151                  * Drop the packet if it does.
5152                  */
5153                 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5154                             tg3_4g_overflow_test(new_addr, new_skb->len))) {
5155                         if (!ret)
5156                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5157                                               DMA_TO_DEVICE);
5158                         ret = -1;
5159                         dev_kfree_skb(new_skb);
5160                         new_skb = NULL;
5161                 } else {
5162                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5163                                     base_flags, 1 | (mss << 1));
5164                         *start = NEXT_TX(entry);
5165                 }
5166         }
5167
5168         /* Now clean up the sw ring entries. */
5169         i = 0;
5170         while (entry != last_plus_one) {
5171                 if (i == 0)
5172                         tnapi->tx_buffers[entry].skb = new_skb;
5173                 else
5174                         tnapi->tx_buffers[entry].skb = NULL;
5175                 entry = NEXT_TX(entry);
5176                 i++;
5177         }
5178
5179         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5180         dev_kfree_skb(skb);
5181
5182         return ret;
5183 }
5184
5185 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5186                         dma_addr_t mapping, int len, u32 flags,
5187                         u32 mss_and_is_end)
5188 {
5189         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5190         int is_end = (mss_and_is_end & 0x1);
5191         u32 mss = (mss_and_is_end >> 1);
5192         u32 vlan_tag = 0;
5193
5194         if (is_end)
5195                 flags |= TXD_FLAG_END;
5196         if (flags & TXD_FLAG_VLAN) {
5197                 vlan_tag = flags >> 16;
5198                 flags &= 0xffff;
5199         }
5200         vlan_tag |= (mss << TXD_MSS_SHIFT);
5201
5202         txd->addr_hi = ((u64) mapping >> 32);
5203         txd->addr_lo = ((u64) mapping & 0xffffffff);
5204         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5205         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5206 }
5207
5208 /* hard_start_xmit for devices that don't have any bugs and
5209  * support TG3_FLG2_HW_TSO_2 only.
5210  */
5211 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5212                                   struct net_device *dev)
5213 {
5214         struct tg3 *tp = netdev_priv(dev);
5215         u32 len, entry, base_flags, mss;
5216         struct skb_shared_info *sp;
5217         dma_addr_t mapping;
5218         struct tg3_napi *tnapi;
5219         struct netdev_queue *txq;
5220
5221         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5222         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5223         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5224                 tnapi++;
5225
5226         /* We are running in BH disabled context with netif_tx_lock
5227          * and TX reclaim runs via tp->napi.poll inside of a software
5228          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5229          * no IRQ context deadlocks to worry about either.  Rejoice!
5230          */
5231         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5232                 if (!netif_tx_queue_stopped(txq)) {
5233                         netif_tx_stop_queue(txq);
5234
5235                         /* This is a hard error, log it. */
5236                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5237                                "queue awake!\n", dev->name);
5238                 }
5239                 return NETDEV_TX_BUSY;
5240         }
5241
5242         entry = tnapi->tx_prod;
5243         base_flags = 0;
5244         mss = 0;
5245         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5246                 int tcp_opt_len, ip_tcp_len;
5247                 u32 hdrlen;
5248
5249                 if (skb_header_cloned(skb) &&
5250                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5251                         dev_kfree_skb(skb);
5252                         goto out_unlock;
5253                 }
5254
5255                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5256                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5257                 else {
5258                         struct iphdr *iph = ip_hdr(skb);
5259
5260                         tcp_opt_len = tcp_optlen(skb);
5261                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5262
5263                         iph->check = 0;
5264                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5265                         hdrlen = ip_tcp_len + tcp_opt_len;
5266                 }
5267
5268                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5269                         mss |= (hdrlen & 0xc) << 12;
5270                         if (hdrlen & 0x10)
5271                                 base_flags |= 0x00000010;
5272                         base_flags |= (hdrlen & 0x3e0) << 5;
5273                 } else
5274                         mss |= hdrlen << 9;
5275
5276                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5277                                TXD_FLAG_CPU_POST_DMA);
5278
5279                 tcp_hdr(skb)->check = 0;
5280
5281         }
5282         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5283                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5284 #if TG3_VLAN_TAG_USED
5285         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5286                 base_flags |= (TXD_FLAG_VLAN |
5287                                (vlan_tx_tag_get(skb) << 16));
5288 #endif
5289
5290         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5291                 dev_kfree_skb(skb);
5292                 goto out_unlock;
5293         }
5294
5295         sp = skb_shinfo(skb);
5296
5297         mapping = sp->dma_head;
5298
5299         tnapi->tx_buffers[entry].skb = skb;
5300
5301         len = skb_headlen(skb);
5302
5303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5304             !mss && skb->len > ETH_DATA_LEN)
5305                 base_flags |= TXD_FLAG_JMB_PKT;
5306
5307         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5308                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5309
5310         entry = NEXT_TX(entry);
5311
5312         /* Now loop through additional data fragments, and queue them. */
5313         if (skb_shinfo(skb)->nr_frags > 0) {
5314                 unsigned int i, last;
5315
5316                 last = skb_shinfo(skb)->nr_frags - 1;
5317                 for (i = 0; i <= last; i++) {
5318                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5319
5320                         len = frag->size;
5321                         mapping = sp->dma_maps[i];
5322                         tnapi->tx_buffers[entry].skb = NULL;
5323
5324                         tg3_set_txd(tnapi, entry, mapping, len,
5325                                     base_flags, (i == last) | (mss << 1));
5326
5327                         entry = NEXT_TX(entry);
5328                 }
5329         }
5330
5331         /* Packets are ready, update Tx producer idx local and on card. */
5332         tw32_tx_mbox(tnapi->prodmbox, entry);
5333
5334         tnapi->tx_prod = entry;
5335         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5336                 netif_tx_stop_queue(txq);
5337                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5338                         netif_tx_wake_queue(txq);
5339         }
5340
5341 out_unlock:
5342         mmiowb();
5343
5344         return NETDEV_TX_OK;
5345 }
5346
5347 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5348                                           struct net_device *);
5349
5350 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5351  * TSO header is greater than 80 bytes.
5352  */
5353 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5354 {
5355         struct sk_buff *segs, *nskb;
5356         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5357
5358         /* Estimate the number of fragments in the worst case */
5359         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5360                 netif_stop_queue(tp->dev);
5361                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5362                         return NETDEV_TX_BUSY;
5363
5364                 netif_wake_queue(tp->dev);
5365         }
5366
5367         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5368         if (IS_ERR(segs))
5369                 goto tg3_tso_bug_end;
5370
5371         do {
5372                 nskb = segs;
5373                 segs = segs->next;
5374                 nskb->next = NULL;
5375                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5376         } while (segs);
5377
5378 tg3_tso_bug_end:
5379         dev_kfree_skb(skb);
5380
5381         return NETDEV_TX_OK;
5382 }
5383
5384 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5385  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5386  */
5387 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5388                                           struct net_device *dev)
5389 {
5390         struct tg3 *tp = netdev_priv(dev);
5391         u32 len, entry, base_flags, mss;
5392         struct skb_shared_info *sp;
5393         int would_hit_hwbug;
5394         dma_addr_t mapping;
5395         struct tg3_napi *tnapi = &tp->napi[0];
5396
5397         len = skb_headlen(skb);
5398
5399         /* We are running in BH disabled context with netif_tx_lock
5400          * and TX reclaim runs via tp->napi.poll inside of a software
5401          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5402          * no IRQ context deadlocks to worry about either.  Rejoice!
5403          */
5404         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5405                 if (!netif_queue_stopped(dev)) {
5406                         netif_stop_queue(dev);
5407
5408                         /* This is a hard error, log it. */
5409                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5410                                "queue awake!\n", dev->name);
5411                 }
5412                 return NETDEV_TX_BUSY;
5413         }
5414
5415         entry = tnapi->tx_prod;
5416         base_flags = 0;
5417         if (skb->ip_summed == CHECKSUM_PARTIAL)
5418                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5419         mss = 0;
5420         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5421                 struct iphdr *iph;
5422                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5423
5424                 if (skb_header_cloned(skb) &&
5425                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5426                         dev_kfree_skb(skb);
5427                         goto out_unlock;
5428                 }
5429
5430                 tcp_opt_len = tcp_optlen(skb);
5431                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5432
5433                 hdr_len = ip_tcp_len + tcp_opt_len;
5434                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5435                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5436                         return (tg3_tso_bug(tp, skb));
5437
5438                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5439                                TXD_FLAG_CPU_POST_DMA);
5440
5441                 iph = ip_hdr(skb);
5442                 iph->check = 0;
5443                 iph->tot_len = htons(mss + hdr_len);
5444                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5445                         tcp_hdr(skb)->check = 0;
5446                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5447                 } else
5448                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5449                                                                  iph->daddr, 0,
5450                                                                  IPPROTO_TCP,
5451                                                                  0);
5452
5453                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5454                         mss |= hdr_len << 9;
5455                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5456                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5457                         if (tcp_opt_len || iph->ihl > 5) {
5458                                 int tsflags;
5459
5460                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5461                                 mss |= (tsflags << 11);
5462                         }
5463                 } else {
5464                         if (tcp_opt_len || iph->ihl > 5) {
5465                                 int tsflags;
5466
5467                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5468                                 base_flags |= tsflags << 12;
5469                         }
5470                 }
5471         }
5472 #if TG3_VLAN_TAG_USED
5473         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5474                 base_flags |= (TXD_FLAG_VLAN |
5475                                (vlan_tx_tag_get(skb) << 16));
5476 #endif
5477
5478         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5479                 dev_kfree_skb(skb);
5480                 goto out_unlock;
5481         }
5482
5483         sp = skb_shinfo(skb);
5484
5485         mapping = sp->dma_head;
5486
5487         tnapi->tx_buffers[entry].skb = skb;
5488
5489         would_hit_hwbug = 0;
5490
5491         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5492                 would_hit_hwbug = 1;
5493
5494         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5495             tg3_4g_overflow_test(mapping, len))
5496                 would_hit_hwbug = 1;
5497
5498         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5499             tg3_40bit_overflow_test(tp, mapping, len))
5500                 would_hit_hwbug = 1;
5501
5502         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5503                 would_hit_hwbug = 1;
5504
5505         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5506                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5507
5508         entry = NEXT_TX(entry);
5509
5510         /* Now loop through additional data fragments, and queue them. */
5511         if (skb_shinfo(skb)->nr_frags > 0) {
5512                 unsigned int i, last;
5513
5514                 last = skb_shinfo(skb)->nr_frags - 1;
5515                 for (i = 0; i <= last; i++) {
5516                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5517
5518                         len = frag->size;
5519                         mapping = sp->dma_maps[i];
5520
5521                         tnapi->tx_buffers[entry].skb = NULL;
5522
5523                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5524                             len <= 8)
5525                                 would_hit_hwbug = 1;
5526
5527                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5528                             tg3_4g_overflow_test(mapping, len))
5529                                 would_hit_hwbug = 1;
5530
5531                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5532                             tg3_40bit_overflow_test(tp, mapping, len))
5533                                 would_hit_hwbug = 1;
5534
5535                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5536                                 tg3_set_txd(tnapi, entry, mapping, len,
5537                                             base_flags, (i == last)|(mss << 1));
5538                         else
5539                                 tg3_set_txd(tnapi, entry, mapping, len,
5540                                             base_flags, (i == last));
5541
5542                         entry = NEXT_TX(entry);
5543                 }
5544         }
5545
5546         if (would_hit_hwbug) {
5547                 u32 last_plus_one = entry;
5548                 u32 start;
5549
5550                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5551                 start &= (TG3_TX_RING_SIZE - 1);
5552
5553                 /* If the workaround fails due to memory/mapping
5554                  * failure, silently drop this packet.
5555                  */
5556                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5557                                                 &start, base_flags, mss))
5558                         goto out_unlock;
5559
5560                 entry = start;
5561         }
5562
5563         /* Packets are ready, update Tx producer idx local and on card. */
5564         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5565
5566         tnapi->tx_prod = entry;
5567         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5568                 netif_stop_queue(dev);
5569                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5570                         netif_wake_queue(tp->dev);
5571         }
5572
5573 out_unlock:
5574         mmiowb();
5575
5576         return NETDEV_TX_OK;
5577 }
5578
5579 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5580                                int new_mtu)
5581 {
5582         dev->mtu = new_mtu;
5583
5584         if (new_mtu > ETH_DATA_LEN) {
5585                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5586                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5587                         ethtool_op_set_tso(dev, 0);
5588                 }
5589                 else
5590                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5591         } else {
5592                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5593                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5594                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5595         }
5596 }
5597
5598 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5599 {
5600         struct tg3 *tp = netdev_priv(dev);
5601         int err;
5602
5603         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5604                 return -EINVAL;
5605
5606         if (!netif_running(dev)) {
5607                 /* We'll just catch it later when the
5608                  * device is up'd.
5609                  */
5610                 tg3_set_mtu(dev, tp, new_mtu);
5611                 return 0;
5612         }
5613
5614         tg3_phy_stop(tp);
5615
5616         tg3_netif_stop(tp);
5617
5618         tg3_full_lock(tp, 1);
5619
5620         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5621
5622         tg3_set_mtu(dev, tp, new_mtu);
5623
5624         err = tg3_restart_hw(tp, 0);
5625
5626         if (!err)
5627                 tg3_netif_start(tp);
5628
5629         tg3_full_unlock(tp);
5630
5631         if (!err)
5632                 tg3_phy_start(tp);
5633
5634         return err;
5635 }
5636
5637 static void tg3_rx_prodring_free(struct tg3 *tp,
5638                                  struct tg3_rx_prodring_set *tpr)
5639 {
5640         int i;
5641         struct ring_info *rxp;
5642
5643         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5644                 rxp = &tpr->rx_std_buffers[i];
5645
5646                 if (rxp->skb == NULL)
5647                         continue;
5648
5649                 pci_unmap_single(tp->pdev,
5650                                  pci_unmap_addr(rxp, mapping),
5651                                  tp->rx_pkt_map_sz,
5652                                  PCI_DMA_FROMDEVICE);
5653                 dev_kfree_skb_any(rxp->skb);
5654                 rxp->skb = NULL;
5655         }
5656
5657         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5658                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5659                         rxp = &tpr->rx_jmb_buffers[i];
5660
5661                         if (rxp->skb == NULL)
5662                                 continue;
5663
5664                         pci_unmap_single(tp->pdev,
5665                                          pci_unmap_addr(rxp, mapping),
5666                                          TG3_RX_JMB_MAP_SZ,
5667                                          PCI_DMA_FROMDEVICE);
5668                         dev_kfree_skb_any(rxp->skb);
5669                         rxp->skb = NULL;
5670                 }
5671         }
5672 }
5673
5674 /* Initialize tx/rx rings for packet processing.
5675  *
5676  * The chip has been shut down and the driver detached from
5677  * the networking, so no interrupts or new tx packets will
5678  * end up in the driver.  tp->{tx,}lock are held and thus
5679  * we may not sleep.
5680  */
5681 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5682                                  struct tg3_rx_prodring_set *tpr)
5683 {
5684         u32 i, rx_pkt_dma_sz;
5685         struct tg3_napi *tnapi = &tp->napi[0];
5686
5687         /* Zero out all descriptors. */
5688         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5689
5690         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5691         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5692             tp->dev->mtu > ETH_DATA_LEN)
5693                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5694         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5695
5696         /* Initialize invariants of the rings, we only set this
5697          * stuff once.  This works because the card does not
5698          * write into the rx buffer posting rings.
5699          */
5700         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5701                 struct tg3_rx_buffer_desc *rxd;
5702
5703                 rxd = &tpr->rx_std[i];
5704                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5705                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5706                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5707                                (i << RXD_OPAQUE_INDEX_SHIFT));
5708         }
5709
5710         /* Now allocate fresh SKBs for each rx ring. */
5711         for (i = 0; i < tp->rx_pending; i++) {
5712                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5713                         printk(KERN_WARNING PFX
5714                                "%s: Using a smaller RX standard ring, "
5715                                "only %d out of %d buffers were allocated "
5716                                "successfully.\n",
5717                                tp->dev->name, i, tp->rx_pending);
5718                         if (i == 0)
5719                                 goto initfail;
5720                         tp->rx_pending = i;
5721                         break;
5722                 }
5723         }
5724
5725         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5726                 goto done;
5727
5728         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5729
5730         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5731                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5732                         struct tg3_rx_buffer_desc *rxd;
5733
5734                         rxd = &tpr->rx_jmb[i].std;
5735                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5736                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5737                                 RXD_FLAG_JUMBO;
5738                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5739                                (i << RXD_OPAQUE_INDEX_SHIFT));
5740                 }
5741
5742                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5743                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5744                                              -1, i) < 0) {
5745                                 printk(KERN_WARNING PFX
5746                                        "%s: Using a smaller RX jumbo ring, "
5747                                        "only %d out of %d buffers were "
5748                                        "allocated successfully.\n",
5749                                        tp->dev->name, i, tp->rx_jumbo_pending);
5750                                 if (i == 0)
5751                                         goto initfail;
5752                                 tp->rx_jumbo_pending = i;
5753                                 break;
5754                         }
5755                 }
5756         }
5757
5758 done:
5759         return 0;
5760
5761 initfail:
5762         tg3_rx_prodring_free(tp, tpr);
5763         return -ENOMEM;
5764 }
5765
5766 static void tg3_rx_prodring_fini(struct tg3 *tp,
5767                                  struct tg3_rx_prodring_set *tpr)
5768 {
5769         kfree(tpr->rx_std_buffers);
5770         tpr->rx_std_buffers = NULL;
5771         kfree(tpr->rx_jmb_buffers);
5772         tpr->rx_jmb_buffers = NULL;
5773         if (tpr->rx_std) {
5774                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5775                                     tpr->rx_std, tpr->rx_std_mapping);
5776                 tpr->rx_std = NULL;
5777         }
5778         if (tpr->rx_jmb) {
5779                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5780                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5781                 tpr->rx_jmb = NULL;
5782         }
5783 }
5784
5785 static int tg3_rx_prodring_init(struct tg3 *tp,
5786                                 struct tg3_rx_prodring_set *tpr)
5787 {
5788         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5789                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5790         if (!tpr->rx_std_buffers)
5791                 return -ENOMEM;
5792
5793         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5794                                            &tpr->rx_std_mapping);
5795         if (!tpr->rx_std)
5796                 goto err_out;
5797
5798         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5799                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5800                                               TG3_RX_JUMBO_RING_SIZE,
5801                                               GFP_KERNEL);
5802                 if (!tpr->rx_jmb_buffers)
5803                         goto err_out;
5804
5805                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5806                                                    TG3_RX_JUMBO_RING_BYTES,
5807                                                    &tpr->rx_jmb_mapping);
5808                 if (!tpr->rx_jmb)
5809                         goto err_out;
5810         }
5811
5812         return 0;
5813
5814 err_out:
5815         tg3_rx_prodring_fini(tp, tpr);
5816         return -ENOMEM;
5817 }
5818
5819 /* Free up pending packets in all rx/tx rings.
5820  *
5821  * The chip has been shut down and the driver detached from
5822  * the networking, so no interrupts or new tx packets will
5823  * end up in the driver.  tp->{tx,}lock is not held and we are not
5824  * in an interrupt context and thus may sleep.
5825  */
5826 static void tg3_free_rings(struct tg3 *tp)
5827 {
5828         int i, j;
5829
5830         for (j = 0; j < tp->irq_cnt; j++) {
5831                 struct tg3_napi *tnapi = &tp->napi[j];
5832
5833                 if (!tnapi->tx_buffers)
5834                         continue;
5835
5836                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5837                         struct tx_ring_info *txp;
5838                         struct sk_buff *skb;
5839
5840                         txp = &tnapi->tx_buffers[i];
5841                         skb = txp->skb;
5842
5843                         if (skb == NULL) {
5844                                 i++;
5845                                 continue;
5846                         }
5847
5848                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5849
5850                         txp->skb = NULL;
5851
5852                         i += skb_shinfo(skb)->nr_frags + 1;
5853
5854                         dev_kfree_skb_any(skb);
5855                 }
5856         }
5857
5858         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5859 }
5860
5861 /* Initialize tx/rx rings for packet processing.
5862  *
5863  * The chip has been shut down and the driver detached from
5864  * the networking, so no interrupts or new tx packets will
5865  * end up in the driver.  tp->{tx,}lock are held and thus
5866  * we may not sleep.
5867  */
5868 static int tg3_init_rings(struct tg3 *tp)
5869 {
5870         int i;
5871
5872         /* Free up all the SKBs. */
5873         tg3_free_rings(tp);
5874
5875         for (i = 0; i < tp->irq_cnt; i++) {
5876                 struct tg3_napi *tnapi = &tp->napi[i];
5877
5878                 tnapi->last_tag = 0;
5879                 tnapi->last_irq_tag = 0;
5880                 tnapi->hw_status->status = 0;
5881                 tnapi->hw_status->status_tag = 0;
5882                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5883
5884                 tnapi->tx_prod = 0;
5885                 tnapi->tx_cons = 0;
5886                 if (tnapi->tx_ring)
5887                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5888
5889                 tnapi->rx_rcb_ptr = 0;
5890                 if (tnapi->rx_rcb)
5891                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5892         }
5893
5894         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5895 }
5896
5897 /*
5898  * Must not be invoked with interrupt sources disabled and
5899  * the hardware shutdown down.
5900  */
5901 static void tg3_free_consistent(struct tg3 *tp)
5902 {
5903         int i;
5904
5905         for (i = 0; i < tp->irq_cnt; i++) {
5906                 struct tg3_napi *tnapi = &tp->napi[i];
5907
5908                 if (tnapi->tx_ring) {
5909                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5910                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5911                         tnapi->tx_ring = NULL;
5912                 }
5913
5914                 kfree(tnapi->tx_buffers);
5915                 tnapi->tx_buffers = NULL;
5916
5917                 if (tnapi->rx_rcb) {
5918                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5919                                             tnapi->rx_rcb,
5920                                             tnapi->rx_rcb_mapping);
5921                         tnapi->rx_rcb = NULL;
5922                 }
5923
5924                 if (tnapi->hw_status) {
5925                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5926                                             tnapi->hw_status,
5927                                             tnapi->status_mapping);
5928                         tnapi->hw_status = NULL;
5929                 }
5930         }
5931
5932         if (tp->hw_stats) {
5933                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5934                                     tp->hw_stats, tp->stats_mapping);
5935                 tp->hw_stats = NULL;
5936         }
5937
5938         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5939 }
5940
5941 /*
5942  * Must not be invoked with interrupt sources disabled and
5943  * the hardware shutdown down.  Can sleep.
5944  */
5945 static int tg3_alloc_consistent(struct tg3 *tp)
5946 {
5947         int i;
5948
5949         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5950                 return -ENOMEM;
5951
5952         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5953                                             sizeof(struct tg3_hw_stats),
5954                                             &tp->stats_mapping);
5955         if (!tp->hw_stats)
5956                 goto err_out;
5957
5958         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5959
5960         for (i = 0; i < tp->irq_cnt; i++) {
5961                 struct tg3_napi *tnapi = &tp->napi[i];
5962                 struct tg3_hw_status *sblk;
5963
5964                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5965                                                         TG3_HW_STATUS_SIZE,
5966                                                         &tnapi->status_mapping);
5967                 if (!tnapi->hw_status)
5968                         goto err_out;
5969
5970                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5971                 sblk = tnapi->hw_status;
5972
5973                 /*
5974                  * When RSS is enabled, the status block format changes
5975                  * slightly.  The "rx_jumbo_consumer", "reserved",
5976                  * and "rx_mini_consumer" members get mapped to the
5977                  * other three rx return ring producer indexes.
5978                  */
5979                 switch (i) {
5980                 default:
5981                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5982                         break;
5983                 case 2:
5984                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5985                         break;
5986                 case 3:
5987                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
5988                         break;
5989                 case 4:
5990                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5991                         break;
5992                 }
5993
5994                 /*
5995                  * If multivector RSS is enabled, vector 0 does not handle
5996                  * rx or tx interrupts.  Don't allocate any resources for it.
5997                  */
5998                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5999                         continue;
6000
6001                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6002                                                      TG3_RX_RCB_RING_BYTES(tp),
6003                                                      &tnapi->rx_rcb_mapping);
6004                 if (!tnapi->rx_rcb)
6005                         goto err_out;
6006
6007                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6008
6009                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6010                                             TG3_TX_RING_SIZE, GFP_KERNEL);
6011                 if (!tnapi->tx_buffers)
6012                         goto err_out;
6013
6014                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6015                                                       TG3_TX_RING_BYTES,
6016                                                       &tnapi->tx_desc_mapping);
6017                 if (!tnapi->tx_ring)
6018                         goto err_out;
6019         }
6020
6021         return 0;
6022
6023 err_out:
6024         tg3_free_consistent(tp);
6025         return -ENOMEM;
6026 }
6027
6028 #define MAX_WAIT_CNT 1000
6029
6030 /* To stop a block, clear the enable bit and poll till it
6031  * clears.  tp->lock is held.
6032  */
6033 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6034 {
6035         unsigned int i;
6036         u32 val;
6037
6038         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6039                 switch (ofs) {
6040                 case RCVLSC_MODE:
6041                 case DMAC_MODE:
6042                 case MBFREE_MODE:
6043                 case BUFMGR_MODE:
6044                 case MEMARB_MODE:
6045                         /* We can't enable/disable these bits of the
6046                          * 5705/5750, just say success.
6047                          */
6048                         return 0;
6049
6050                 default:
6051                         break;
6052                 }
6053         }
6054
6055         val = tr32(ofs);
6056         val &= ~enable_bit;
6057         tw32_f(ofs, val);
6058
6059         for (i = 0; i < MAX_WAIT_CNT; i++) {
6060                 udelay(100);
6061                 val = tr32(ofs);
6062                 if ((val & enable_bit) == 0)
6063                         break;
6064         }
6065
6066         if (i == MAX_WAIT_CNT && !silent) {
6067                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6068                        "ofs=%lx enable_bit=%x\n",
6069                        ofs, enable_bit);
6070                 return -ENODEV;
6071         }
6072
6073         return 0;
6074 }
6075
6076 /* tp->lock is held. */
6077 static int tg3_abort_hw(struct tg3 *tp, int silent)
6078 {
6079         int i, err;
6080
6081         tg3_disable_ints(tp);
6082
6083         tp->rx_mode &= ~RX_MODE_ENABLE;
6084         tw32_f(MAC_RX_MODE, tp->rx_mode);
6085         udelay(10);
6086
6087         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6088         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6089         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6090         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6091         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6092         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6093
6094         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6095         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6096         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6097         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6098         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6099         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6100         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6101
6102         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6103         tw32_f(MAC_MODE, tp->mac_mode);
6104         udelay(40);
6105
6106         tp->tx_mode &= ~TX_MODE_ENABLE;
6107         tw32_f(MAC_TX_MODE, tp->tx_mode);
6108
6109         for (i = 0; i < MAX_WAIT_CNT; i++) {
6110                 udelay(100);
6111                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6112                         break;
6113         }
6114         if (i >= MAX_WAIT_CNT) {
6115                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6116                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6117                        tp->dev->name, tr32(MAC_TX_MODE));
6118                 err |= -ENODEV;
6119         }
6120
6121         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6122         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6123         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6124
6125         tw32(FTQ_RESET, 0xffffffff);
6126         tw32(FTQ_RESET, 0x00000000);
6127
6128         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6129         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6130
6131         for (i = 0; i < tp->irq_cnt; i++) {
6132                 struct tg3_napi *tnapi = &tp->napi[i];
6133                 if (tnapi->hw_status)
6134                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6135         }
6136         if (tp->hw_stats)
6137                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6138
6139         return err;
6140 }
6141
6142 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6143 {
6144         int i;
6145         u32 apedata;
6146
6147         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6148         if (apedata != APE_SEG_SIG_MAGIC)
6149                 return;
6150
6151         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6152         if (!(apedata & APE_FW_STATUS_READY))
6153                 return;
6154
6155         /* Wait for up to 1 millisecond for APE to service previous event. */
6156         for (i = 0; i < 10; i++) {
6157                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6158                         return;
6159
6160                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6161
6162                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6163                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6164                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6165
6166                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6167
6168                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6169                         break;
6170
6171                 udelay(100);
6172         }
6173
6174         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6175                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6176 }
6177
6178 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6179 {
6180         u32 event;
6181         u32 apedata;
6182
6183         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6184                 return;
6185
6186         switch (kind) {
6187                 case RESET_KIND_INIT:
6188                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6189                                         APE_HOST_SEG_SIG_MAGIC);
6190                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6191                                         APE_HOST_SEG_LEN_MAGIC);
6192                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6193                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6194                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6195                                         APE_HOST_DRIVER_ID_MAGIC);
6196                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6197                                         APE_HOST_BEHAV_NO_PHYLOCK);
6198
6199                         event = APE_EVENT_STATUS_STATE_START;
6200                         break;
6201                 case RESET_KIND_SHUTDOWN:
6202                         /* With the interface we are currently using,
6203                          * APE does not track driver state.  Wiping
6204                          * out the HOST SEGMENT SIGNATURE forces
6205                          * the APE to assume OS absent status.
6206                          */
6207                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6208
6209                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6210                         break;
6211                 case RESET_KIND_SUSPEND:
6212                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6213                         break;
6214                 default:
6215                         return;
6216         }
6217
6218         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6219
6220         tg3_ape_send_event(tp, event);
6221 }
6222
6223 /* tp->lock is held. */
6224 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6225 {
6226         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6227                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6228
6229         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6230                 switch (kind) {
6231                 case RESET_KIND_INIT:
6232                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6233                                       DRV_STATE_START);
6234                         break;
6235
6236                 case RESET_KIND_SHUTDOWN:
6237                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6238                                       DRV_STATE_UNLOAD);
6239                         break;
6240
6241                 case RESET_KIND_SUSPEND:
6242                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6243                                       DRV_STATE_SUSPEND);
6244                         break;
6245
6246                 default:
6247                         break;
6248                 }
6249         }
6250
6251         if (kind == RESET_KIND_INIT ||
6252             kind == RESET_KIND_SUSPEND)
6253                 tg3_ape_driver_state_change(tp, kind);
6254 }
6255
6256 /* tp->lock is held. */
6257 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6258 {
6259         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6260                 switch (kind) {
6261                 case RESET_KIND_INIT:
6262                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6263                                       DRV_STATE_START_DONE);
6264                         break;
6265
6266                 case RESET_KIND_SHUTDOWN:
6267                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6268                                       DRV_STATE_UNLOAD_DONE);
6269                         break;
6270
6271                 default:
6272                         break;
6273                 }
6274         }
6275
6276         if (kind == RESET_KIND_SHUTDOWN)
6277                 tg3_ape_driver_state_change(tp, kind);
6278 }
6279
6280 /* tp->lock is held. */
6281 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6282 {
6283         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6284                 switch (kind) {
6285                 case RESET_KIND_INIT:
6286                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6287                                       DRV_STATE_START);
6288                         break;
6289
6290                 case RESET_KIND_SHUTDOWN:
6291                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6292                                       DRV_STATE_UNLOAD);
6293                         break;
6294
6295                 case RESET_KIND_SUSPEND:
6296                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6297                                       DRV_STATE_SUSPEND);
6298                         break;
6299
6300                 default:
6301                         break;
6302                 }
6303         }
6304 }
6305
6306 static int tg3_poll_fw(struct tg3 *tp)
6307 {
6308         int i;
6309         u32 val;
6310
6311         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6312                 /* Wait up to 20ms for init done. */
6313                 for (i = 0; i < 200; i++) {
6314                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6315                                 return 0;
6316                         udelay(100);
6317                 }
6318                 return -ENODEV;
6319         }
6320
6321         /* Wait for firmware initialization to complete. */
6322         for (i = 0; i < 100000; i++) {
6323                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6324                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6325                         break;
6326                 udelay(10);
6327         }
6328
6329         /* Chip might not be fitted with firmware.  Some Sun onboard
6330          * parts are configured like that.  So don't signal the timeout
6331          * of the above loop as an error, but do report the lack of
6332          * running firmware once.
6333          */
6334         if (i >= 100000 &&
6335             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6336                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6337
6338                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6339                        tp->dev->name);
6340         }
6341
6342         return 0;
6343 }
6344
6345 /* Save PCI command register before chip reset */
6346 static void tg3_save_pci_state(struct tg3 *tp)
6347 {
6348         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6349 }
6350
6351 /* Restore PCI state after chip reset */
6352 static void tg3_restore_pci_state(struct tg3 *tp)
6353 {
6354         u32 val;
6355
6356         /* Re-enable indirect register accesses. */
6357         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6358                                tp->misc_host_ctrl);
6359
6360         /* Set MAX PCI retry to zero. */
6361         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6362         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6363             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6364                 val |= PCISTATE_RETRY_SAME_DMA;
6365         /* Allow reads and writes to the APE register and memory space. */
6366         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6367                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6368                        PCISTATE_ALLOW_APE_SHMEM_WR;
6369         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6370
6371         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6372
6373         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6374                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6375                         pcie_set_readrq(tp->pdev, 4096);
6376                 else {
6377                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6378                                               tp->pci_cacheline_sz);
6379                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6380                                               tp->pci_lat_timer);
6381                 }
6382         }
6383
6384         /* Make sure PCI-X relaxed ordering bit is clear. */
6385         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6386                 u16 pcix_cmd;
6387
6388                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6389                                      &pcix_cmd);
6390                 pcix_cmd &= ~PCI_X_CMD_ERO;
6391                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6392                                       pcix_cmd);
6393         }
6394
6395         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6396
6397                 /* Chip reset on 5780 will reset MSI enable bit,
6398                  * so need to restore it.
6399                  */
6400                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6401                         u16 ctrl;
6402
6403                         pci_read_config_word(tp->pdev,
6404                                              tp->msi_cap + PCI_MSI_FLAGS,
6405                                              &ctrl);
6406                         pci_write_config_word(tp->pdev,
6407                                               tp->msi_cap + PCI_MSI_FLAGS,
6408                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6409                         val = tr32(MSGINT_MODE);
6410                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6411                 }
6412         }
6413 }
6414
6415 static void tg3_stop_fw(struct tg3 *);
6416
6417 /* tp->lock is held. */
6418 static int tg3_chip_reset(struct tg3 *tp)
6419 {
6420         u32 val;
6421         void (*write_op)(struct tg3 *, u32, u32);
6422         int i, err;
6423
6424         tg3_nvram_lock(tp);
6425
6426         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6427
6428         /* No matching tg3_nvram_unlock() after this because
6429          * chip reset below will undo the nvram lock.
6430          */
6431         tp->nvram_lock_cnt = 0;
6432
6433         /* GRC_MISC_CFG core clock reset will clear the memory
6434          * enable bit in PCI register 4 and the MSI enable bit
6435          * on some chips, so we save relevant registers here.
6436          */
6437         tg3_save_pci_state(tp);
6438
6439         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6440             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6441                 tw32(GRC_FASTBOOT_PC, 0);
6442
6443         /*
6444          * We must avoid the readl() that normally takes place.
6445          * It locks machines, causes machine checks, and other
6446          * fun things.  So, temporarily disable the 5701
6447          * hardware workaround, while we do the reset.
6448          */
6449         write_op = tp->write32;
6450         if (write_op == tg3_write_flush_reg32)
6451                 tp->write32 = tg3_write32;
6452
6453         /* Prevent the irq handler from reading or writing PCI registers
6454          * during chip reset when the memory enable bit in the PCI command
6455          * register may be cleared.  The chip does not generate interrupt
6456          * at this time, but the irq handler may still be called due to irq
6457          * sharing or irqpoll.
6458          */
6459         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6460         for (i = 0; i < tp->irq_cnt; i++) {
6461                 struct tg3_napi *tnapi = &tp->napi[i];
6462                 if (tnapi->hw_status) {
6463                         tnapi->hw_status->status = 0;
6464                         tnapi->hw_status->status_tag = 0;
6465                 }
6466                 tnapi->last_tag = 0;
6467                 tnapi->last_irq_tag = 0;
6468         }
6469         smp_mb();
6470
6471         for (i = 0; i < tp->irq_cnt; i++)
6472                 synchronize_irq(tp->napi[i].irq_vec);
6473
6474         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6475                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6476                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6477         }
6478
6479         /* do the reset */
6480         val = GRC_MISC_CFG_CORECLK_RESET;
6481
6482         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6483                 if (tr32(0x7e2c) == 0x60) {
6484                         tw32(0x7e2c, 0x20);
6485                 }
6486                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6487                         tw32(GRC_MISC_CFG, (1 << 29));
6488                         val |= (1 << 29);
6489                 }
6490         }
6491
6492         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6493                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6494                 tw32(GRC_VCPU_EXT_CTRL,
6495                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6496         }
6497
6498         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6499                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6500         tw32(GRC_MISC_CFG, val);
6501
6502         /* restore 5701 hardware bug workaround write method */
6503         tp->write32 = write_op;
6504
6505         /* Unfortunately, we have to delay before the PCI read back.
6506          * Some 575X chips even will not respond to a PCI cfg access
6507          * when the reset command is given to the chip.
6508          *
6509          * How do these hardware designers expect things to work
6510          * properly if the PCI write is posted for a long period
6511          * of time?  It is always necessary to have some method by
6512          * which a register read back can occur to push the write
6513          * out which does the reset.
6514          *
6515          * For most tg3 variants the trick below was working.
6516          * Ho hum...
6517          */
6518         udelay(120);
6519
6520         /* Flush PCI posted writes.  The normal MMIO registers
6521          * are inaccessible at this time so this is the only
6522          * way to make this reliably (actually, this is no longer
6523          * the case, see above).  I tried to use indirect
6524          * register read/write but this upset some 5701 variants.
6525          */
6526         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6527
6528         udelay(120);
6529
6530         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6531                 u16 val16;
6532
6533                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6534                         int i;
6535                         u32 cfg_val;
6536
6537                         /* Wait for link training to complete.  */
6538                         for (i = 0; i < 5000; i++)
6539                                 udelay(100);
6540
6541                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6542                         pci_write_config_dword(tp->pdev, 0xc4,
6543                                                cfg_val | (1 << 15));
6544                 }
6545
6546                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6547                 pci_read_config_word(tp->pdev,
6548                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6549                                      &val16);
6550                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6551                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6552                 /*
6553                  * Older PCIe devices only support the 128 byte
6554                  * MPS setting.  Enforce the restriction.
6555                  */
6556                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6557                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6558                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6559                 pci_write_config_word(tp->pdev,
6560                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6561                                       val16);
6562
6563                 pcie_set_readrq(tp->pdev, 4096);
6564
6565                 /* Clear error status */
6566                 pci_write_config_word(tp->pdev,
6567                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6568                                       PCI_EXP_DEVSTA_CED |
6569                                       PCI_EXP_DEVSTA_NFED |
6570                                       PCI_EXP_DEVSTA_FED |
6571                                       PCI_EXP_DEVSTA_URD);
6572         }
6573
6574         tg3_restore_pci_state(tp);
6575
6576         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6577
6578         val = 0;
6579         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6580                 val = tr32(MEMARB_MODE);
6581         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6582
6583         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6584                 tg3_stop_fw(tp);
6585                 tw32(0x5000, 0x400);
6586         }
6587
6588         tw32(GRC_MODE, tp->grc_mode);
6589
6590         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6591                 val = tr32(0xc4);
6592
6593                 tw32(0xc4, val | (1 << 15));
6594         }
6595
6596         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6597             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6598                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6599                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6600                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6601                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6602         }
6603
6604         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6605                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6606                 tw32_f(MAC_MODE, tp->mac_mode);
6607         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6608                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6609                 tw32_f(MAC_MODE, tp->mac_mode);
6610         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6611                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6612                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6613                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6614                 tw32_f(MAC_MODE, tp->mac_mode);
6615         } else
6616                 tw32_f(MAC_MODE, 0);
6617         udelay(40);
6618
6619         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6620
6621         err = tg3_poll_fw(tp);
6622         if (err)
6623                 return err;
6624
6625         tg3_mdio_start(tp);
6626
6627         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6628                 u8 phy_addr;
6629
6630                 phy_addr = tp->phy_addr;
6631                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6632
6633                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6634                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6635                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6636                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6637                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6638                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6639                 udelay(10);
6640
6641                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6642                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6643                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6644                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6645                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6646                 udelay(10);
6647
6648                 tp->phy_addr = phy_addr;
6649         }
6650
6651         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6652             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6653             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6654             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6655                 val = tr32(0x7c00);
6656
6657                 tw32(0x7c00, val | (1 << 25));
6658         }
6659
6660         /* Reprobe ASF enable state.  */
6661         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6662         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6663         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6664         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6665                 u32 nic_cfg;
6666
6667                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6668                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6669                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6670                         tp->last_event_jiffies = jiffies;
6671                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6672                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6673                 }
6674         }
6675
6676         return 0;
6677 }
6678
6679 /* tp->lock is held. */
6680 static void tg3_stop_fw(struct tg3 *tp)
6681 {
6682         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6683            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6684                 /* Wait for RX cpu to ACK the previous event. */
6685                 tg3_wait_for_event_ack(tp);
6686
6687                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6688
6689                 tg3_generate_fw_event(tp);
6690
6691                 /* Wait for RX cpu to ACK this event. */
6692                 tg3_wait_for_event_ack(tp);
6693         }
6694 }
6695
6696 /* tp->lock is held. */
6697 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6698 {
6699         int err;
6700
6701         tg3_stop_fw(tp);
6702
6703         tg3_write_sig_pre_reset(tp, kind);
6704
6705         tg3_abort_hw(tp, silent);
6706         err = tg3_chip_reset(tp);
6707
6708         __tg3_set_mac_addr(tp, 0);
6709
6710         tg3_write_sig_legacy(tp, kind);
6711         tg3_write_sig_post_reset(tp, kind);
6712
6713         if (err)
6714                 return err;
6715
6716         return 0;
6717 }
6718
6719 #define RX_CPU_SCRATCH_BASE     0x30000
6720 #define RX_CPU_SCRATCH_SIZE     0x04000
6721 #define TX_CPU_SCRATCH_BASE     0x34000
6722 #define TX_CPU_SCRATCH_SIZE     0x04000
6723
6724 /* tp->lock is held. */
6725 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6726 {
6727         int i;
6728
6729         BUG_ON(offset == TX_CPU_BASE &&
6730             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6731
6732         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6733                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6734
6735                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6736                 return 0;
6737         }
6738         if (offset == RX_CPU_BASE) {
6739                 for (i = 0; i < 10000; i++) {
6740                         tw32(offset + CPU_STATE, 0xffffffff);
6741                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6742                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6743                                 break;
6744                 }
6745
6746                 tw32(offset + CPU_STATE, 0xffffffff);
6747                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6748                 udelay(10);
6749         } else {
6750                 for (i = 0; i < 10000; i++) {
6751                         tw32(offset + CPU_STATE, 0xffffffff);
6752                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6753                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6754                                 break;
6755                 }
6756         }
6757
6758         if (i >= 10000) {
6759                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6760                        "and %s CPU\n",
6761                        tp->dev->name,
6762                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6763                 return -ENODEV;
6764         }
6765
6766         /* Clear firmware's nvram arbitration. */
6767         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6768                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6769         return 0;
6770 }
6771
6772 struct fw_info {
6773         unsigned int fw_base;
6774         unsigned int fw_len;
6775         const __be32 *fw_data;
6776 };
6777
6778 /* tp->lock is held. */
6779 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6780                                  int cpu_scratch_size, struct fw_info *info)
6781 {
6782         int err, lock_err, i;
6783         void (*write_op)(struct tg3 *, u32, u32);
6784
6785         if (cpu_base == TX_CPU_BASE &&
6786             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6787                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6788                        "TX cpu firmware on %s which is 5705.\n",
6789                        tp->dev->name);
6790                 return -EINVAL;
6791         }
6792
6793         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6794                 write_op = tg3_write_mem;
6795         else
6796                 write_op = tg3_write_indirect_reg32;
6797
6798         /* It is possible that bootcode is still loading at this point.
6799          * Get the nvram lock first before halting the cpu.
6800          */
6801         lock_err = tg3_nvram_lock(tp);
6802         err = tg3_halt_cpu(tp, cpu_base);
6803         if (!lock_err)
6804                 tg3_nvram_unlock(tp);
6805         if (err)
6806                 goto out;
6807
6808         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6809                 write_op(tp, cpu_scratch_base + i, 0);
6810         tw32(cpu_base + CPU_STATE, 0xffffffff);
6811         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6812         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6813                 write_op(tp, (cpu_scratch_base +
6814                               (info->fw_base & 0xffff) +
6815                               (i * sizeof(u32))),
6816                               be32_to_cpu(info->fw_data[i]));
6817
6818         err = 0;
6819
6820 out:
6821         return err;
6822 }
6823
6824 /* tp->lock is held. */
6825 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6826 {
6827         struct fw_info info;
6828         const __be32 *fw_data;
6829         int err, i;
6830
6831         fw_data = (void *)tp->fw->data;
6832
6833         /* Firmware blob starts with version numbers, followed by
6834            start address and length. We are setting complete length.
6835            length = end_address_of_bss - start_address_of_text.
6836            Remainder is the blob to be loaded contiguously
6837            from start address. */
6838
6839         info.fw_base = be32_to_cpu(fw_data[1]);
6840         info.fw_len = tp->fw->size - 12;
6841         info.fw_data = &fw_data[3];
6842
6843         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6844                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6845                                     &info);
6846         if (err)
6847                 return err;
6848
6849         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6850                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6851                                     &info);
6852         if (err)
6853                 return err;
6854
6855         /* Now startup only the RX cpu. */
6856         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6857         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6858
6859         for (i = 0; i < 5; i++) {
6860                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6861                         break;
6862                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6863                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6864                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6865                 udelay(1000);
6866         }
6867         if (i >= 5) {
6868                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6869                        "to set RX CPU PC, is %08x should be %08x\n",
6870                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6871                        info.fw_base);
6872                 return -ENODEV;
6873         }
6874         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6875         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6876
6877         return 0;
6878 }
6879
6880 /* 5705 needs a special version of the TSO firmware.  */
6881
6882 /* tp->lock is held. */
6883 static int tg3_load_tso_firmware(struct tg3 *tp)
6884 {
6885         struct fw_info info;
6886         const __be32 *fw_data;
6887         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6888         int err, i;
6889
6890         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6891                 return 0;
6892
6893         fw_data = (void *)tp->fw->data;
6894
6895         /* Firmware blob starts with version numbers, followed by
6896            start address and length. We are setting complete length.
6897            length = end_address_of_bss - start_address_of_text.
6898            Remainder is the blob to be loaded contiguously
6899            from start address. */
6900
6901         info.fw_base = be32_to_cpu(fw_data[1]);
6902         cpu_scratch_size = tp->fw_len;
6903         info.fw_len = tp->fw->size - 12;
6904         info.fw_data = &fw_data[3];
6905
6906         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6907                 cpu_base = RX_CPU_BASE;
6908                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6909         } else {
6910                 cpu_base = TX_CPU_BASE;
6911                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6912                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6913         }
6914
6915         err = tg3_load_firmware_cpu(tp, cpu_base,
6916                                     cpu_scratch_base, cpu_scratch_size,
6917                                     &info);
6918         if (err)
6919                 return err;
6920
6921         /* Now startup the cpu. */
6922         tw32(cpu_base + CPU_STATE, 0xffffffff);
6923         tw32_f(cpu_base + CPU_PC, info.fw_base);
6924
6925         for (i = 0; i < 5; i++) {
6926                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6927                         break;
6928                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6929                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6930                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6931                 udelay(1000);
6932         }
6933         if (i >= 5) {
6934                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6935                        "to set CPU PC, is %08x should be %08x\n",
6936                        tp->dev->name, tr32(cpu_base + CPU_PC),
6937                        info.fw_base);
6938                 return -ENODEV;
6939         }
6940         tw32(cpu_base + CPU_STATE, 0xffffffff);
6941         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6942         return 0;
6943 }
6944
6945
6946 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6947 {
6948         struct tg3 *tp = netdev_priv(dev);
6949         struct sockaddr *addr = p;
6950         int err = 0, skip_mac_1 = 0;
6951
6952         if (!is_valid_ether_addr(addr->sa_data))
6953                 return -EINVAL;
6954
6955         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6956
6957         if (!netif_running(dev))
6958                 return 0;
6959
6960         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6961                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6962
6963                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6964                 addr0_low = tr32(MAC_ADDR_0_LOW);
6965                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6966                 addr1_low = tr32(MAC_ADDR_1_LOW);
6967
6968                 /* Skip MAC addr 1 if ASF is using it. */
6969                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6970                     !(addr1_high == 0 && addr1_low == 0))
6971                         skip_mac_1 = 1;
6972         }
6973         spin_lock_bh(&tp->lock);
6974         __tg3_set_mac_addr(tp, skip_mac_1);
6975         spin_unlock_bh(&tp->lock);
6976
6977         return err;
6978 }
6979
6980 /* tp->lock is held. */
6981 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6982                            dma_addr_t mapping, u32 maxlen_flags,
6983                            u32 nic_addr)
6984 {
6985         tg3_write_mem(tp,
6986                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6987                       ((u64) mapping >> 32));
6988         tg3_write_mem(tp,
6989                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6990                       ((u64) mapping & 0xffffffff));
6991         tg3_write_mem(tp,
6992                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6993                        maxlen_flags);
6994
6995         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6996                 tg3_write_mem(tp,
6997                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6998                               nic_addr);
6999 }
7000
7001 static void __tg3_set_rx_mode(struct net_device *);
7002 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7003 {
7004         int i;
7005
7006         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7007                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7008                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7009                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7010
7011                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7012                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7013                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7014         } else {
7015                 tw32(HOSTCC_TXCOL_TICKS, 0);
7016                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7017                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7018
7019                 tw32(HOSTCC_RXCOL_TICKS, 0);
7020                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7021                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7022         }
7023
7024         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7025                 u32 val = ec->stats_block_coalesce_usecs;
7026
7027                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7028                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7029
7030                 if (!netif_carrier_ok(tp->dev))
7031                         val = 0;
7032
7033                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7034         }
7035
7036         for (i = 0; i < tp->irq_cnt - 1; i++) {
7037                 u32 reg;
7038
7039                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7040                 tw32(reg, ec->rx_coalesce_usecs);
7041                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7042                 tw32(reg, ec->tx_coalesce_usecs);
7043                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7044                 tw32(reg, ec->rx_max_coalesced_frames);
7045                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7046                 tw32(reg, ec->tx_max_coalesced_frames);
7047                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7048                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7049                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7050                 tw32(reg, ec->tx_max_coalesced_frames_irq);
7051         }
7052
7053         for (; i < tp->irq_max - 1; i++) {
7054                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7055                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7056                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7057                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7058                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7059                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7060         }
7061 }
7062
7063 /* tp->lock is held. */
7064 static void tg3_rings_reset(struct tg3 *tp)
7065 {
7066         int i;
7067         u32 stblk, txrcb, rxrcb, limit;
7068         struct tg3_napi *tnapi = &tp->napi[0];
7069
7070         /* Disable all transmit rings but the first. */
7071         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7072                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7073         else
7074                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7075
7076         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7077              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7078                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7079                               BDINFO_FLAGS_DISABLED);
7080
7081
7082         /* Disable all receive return rings but the first. */
7083         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7084                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7085         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7086                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7087         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7088                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7089         else
7090                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7091
7092         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7093              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7094                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7095                               BDINFO_FLAGS_DISABLED);
7096
7097         /* Disable interrupts */
7098         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7099
7100         /* Zero mailbox registers. */
7101         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7102                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7103                         tp->napi[i].tx_prod = 0;
7104                         tp->napi[i].tx_cons = 0;
7105                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7106                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7107                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7108                 }
7109         } else {
7110                 tp->napi[0].tx_prod = 0;
7111                 tp->napi[0].tx_cons = 0;
7112                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7113                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7114         }
7115
7116         /* Make sure the NIC-based send BD rings are disabled. */
7117         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7118                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7119                 for (i = 0; i < 16; i++)
7120                         tw32_tx_mbox(mbox + i * 8, 0);
7121         }
7122
7123         txrcb = NIC_SRAM_SEND_RCB;
7124         rxrcb = NIC_SRAM_RCV_RET_RCB;
7125
7126         /* Clear status block in ram. */
7127         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7128
7129         /* Set status block DMA address */
7130         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7131              ((u64) tnapi->status_mapping >> 32));
7132         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7133              ((u64) tnapi->status_mapping & 0xffffffff));
7134
7135         if (tnapi->tx_ring) {
7136                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7137                                (TG3_TX_RING_SIZE <<
7138                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7139                                NIC_SRAM_TX_BUFFER_DESC);
7140                 txrcb += TG3_BDINFO_SIZE;
7141         }
7142
7143         if (tnapi->rx_rcb) {
7144                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7145                                (TG3_RX_RCB_RING_SIZE(tp) <<
7146                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7147                 rxrcb += TG3_BDINFO_SIZE;
7148         }
7149
7150         stblk = HOSTCC_STATBLCK_RING1;
7151
7152         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7153                 u64 mapping = (u64)tnapi->status_mapping;
7154                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7155                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7156
7157                 /* Clear status block in ram. */
7158                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7159
7160                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7161                                (TG3_TX_RING_SIZE <<
7162                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7163                                NIC_SRAM_TX_BUFFER_DESC);
7164
7165                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7166                                (TG3_RX_RCB_RING_SIZE(tp) <<
7167                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7168
7169                 stblk += 8;
7170                 txrcb += TG3_BDINFO_SIZE;
7171                 rxrcb += TG3_BDINFO_SIZE;
7172         }
7173 }
7174
7175 /* tp->lock is held. */
7176 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7177 {
7178         u32 val, rdmac_mode;
7179         int i, err, limit;
7180         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7181
7182         tg3_disable_ints(tp);
7183
7184         tg3_stop_fw(tp);
7185
7186         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7187
7188         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7189                 tg3_abort_hw(tp, 1);
7190         }
7191
7192         if (reset_phy &&
7193             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7194                 tg3_phy_reset(tp);
7195
7196         err = tg3_chip_reset(tp);
7197         if (err)
7198                 return err;
7199
7200         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7201
7202         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7203                 val = tr32(TG3_CPMU_CTRL);
7204                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7205                 tw32(TG3_CPMU_CTRL, val);
7206
7207                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7208                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7209                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7210                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7211
7212                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7213                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7214                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7215                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7216
7217                 val = tr32(TG3_CPMU_HST_ACC);
7218                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7219                 val |= CPMU_HST_ACC_MACCLK_6_25;
7220                 tw32(TG3_CPMU_HST_ACC, val);
7221         }
7222
7223         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7224                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7225                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7226                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7227                 tw32(PCIE_PWR_MGMT_THRESH, val);
7228
7229                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7230                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7231
7232                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7233
7234                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7235                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7236         }
7237
7238         /* This works around an issue with Athlon chipsets on
7239          * B3 tigon3 silicon.  This bit has no effect on any
7240          * other revision.  But do not set this on PCI Express
7241          * chips and don't even touch the clocks if the CPMU is present.
7242          */
7243         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7244                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7245                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7246                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7247         }
7248
7249         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7250             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7251                 val = tr32(TG3PCI_PCISTATE);
7252                 val |= PCISTATE_RETRY_SAME_DMA;
7253                 tw32(TG3PCI_PCISTATE, val);
7254         }
7255
7256         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7257                 /* Allow reads and writes to the
7258                  * APE register and memory space.
7259                  */
7260                 val = tr32(TG3PCI_PCISTATE);
7261                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7262                        PCISTATE_ALLOW_APE_SHMEM_WR;
7263                 tw32(TG3PCI_PCISTATE, val);
7264         }
7265
7266         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7267                 /* Enable some hw fixes.  */
7268                 val = tr32(TG3PCI_MSI_DATA);
7269                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7270                 tw32(TG3PCI_MSI_DATA, val);
7271         }
7272
7273         /* Descriptor ring init may make accesses to the
7274          * NIC SRAM area to setup the TX descriptors, so we
7275          * can only do this after the hardware has been
7276          * successfully reset.
7277          */
7278         err = tg3_init_rings(tp);
7279         if (err)
7280                 return err;
7281
7282         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7283             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7284             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
7285                 /* This value is determined during the probe time DMA
7286                  * engine test, tg3_test_dma.
7287                  */
7288                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7289         }
7290
7291         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7292                           GRC_MODE_4X_NIC_SEND_RINGS |
7293                           GRC_MODE_NO_TX_PHDR_CSUM |
7294                           GRC_MODE_NO_RX_PHDR_CSUM);
7295         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7296
7297         /* Pseudo-header checksum is done by hardware logic and not
7298          * the offload processers, so make the chip do the pseudo-
7299          * header checksums on receive.  For transmit it is more
7300          * convenient to do the pseudo-header checksum in software
7301          * as Linux does that on transmit for us in all cases.
7302          */
7303         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7304
7305         tw32(GRC_MODE,
7306              tp->grc_mode |
7307              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7308
7309         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7310         val = tr32(GRC_MISC_CFG);
7311         val &= ~0xff;
7312         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7313         tw32(GRC_MISC_CFG, val);
7314
7315         /* Initialize MBUF/DESC pool. */
7316         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7317                 /* Do nothing.  */
7318         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7319                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7320                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7321                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7322                 else
7323                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7324                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7325                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7326         }
7327         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7328                 int fw_len;
7329
7330                 fw_len = tp->fw_len;
7331                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7332                 tw32(BUFMGR_MB_POOL_ADDR,
7333                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7334                 tw32(BUFMGR_MB_POOL_SIZE,
7335                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7336         }
7337
7338         if (tp->dev->mtu <= ETH_DATA_LEN) {
7339                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7340                      tp->bufmgr_config.mbuf_read_dma_low_water);
7341                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7342                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7343                 tw32(BUFMGR_MB_HIGH_WATER,
7344                      tp->bufmgr_config.mbuf_high_water);
7345         } else {
7346                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7347                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7348                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7349                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7350                 tw32(BUFMGR_MB_HIGH_WATER,
7351                      tp->bufmgr_config.mbuf_high_water_jumbo);
7352         }
7353         tw32(BUFMGR_DMA_LOW_WATER,
7354              tp->bufmgr_config.dma_low_water);
7355         tw32(BUFMGR_DMA_HIGH_WATER,
7356              tp->bufmgr_config.dma_high_water);
7357
7358         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7359         for (i = 0; i < 2000; i++) {
7360                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7361                         break;
7362                 udelay(10);
7363         }
7364         if (i >= 2000) {
7365                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7366                        tp->dev->name);
7367                 return -ENODEV;
7368         }
7369
7370         /* Setup replenish threshold. */
7371         val = tp->rx_pending / 8;
7372         if (val == 0)
7373                 val = 1;
7374         else if (val > tp->rx_std_max_post)
7375                 val = tp->rx_std_max_post;
7376         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7377                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7378                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7379
7380                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7381                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7382         }
7383
7384         tw32(RCVBDI_STD_THRESH, val);
7385
7386         /* Initialize TG3_BDINFO's at:
7387          *  RCVDBDI_STD_BD:     standard eth size rx ring
7388          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7389          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7390          *
7391          * like so:
7392          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7393          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7394          *                              ring attribute flags
7395          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7396          *
7397          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7398          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7399          *
7400          * The size of each ring is fixed in the firmware, but the location is
7401          * configurable.
7402          */
7403         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7404              ((u64) tpr->rx_std_mapping >> 32));
7405         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7406              ((u64) tpr->rx_std_mapping & 0xffffffff));
7407         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7408              NIC_SRAM_RX_BUFFER_DESC);
7409
7410         /* Disable the mini ring */
7411         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7412                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7413                      BDINFO_FLAGS_DISABLED);
7414
7415         /* Program the jumbo buffer descriptor ring control
7416          * blocks on those devices that have them.
7417          */
7418         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7419             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7420                 /* Setup replenish threshold. */
7421                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7422
7423                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7424                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7425                              ((u64) tpr->rx_jmb_mapping >> 32));
7426                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7427                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7428                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7429                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7430                              BDINFO_FLAGS_USE_EXT_RECV);
7431                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7432                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7433                 } else {
7434                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7435                              BDINFO_FLAGS_DISABLED);
7436                 }
7437
7438                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7439                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7440                               (RX_STD_MAX_SIZE << 2);
7441                 else
7442                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7443         } else
7444                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7445
7446         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7447
7448         tpr->rx_std_ptr = tp->rx_pending;
7449         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7450                      tpr->rx_std_ptr);
7451
7452         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7453                           tp->rx_jumbo_pending : 0;
7454         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7455                      tpr->rx_jmb_ptr);
7456
7457         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7458                 tw32(STD_REPLENISH_LWM, 32);
7459                 tw32(JMB_REPLENISH_LWM, 16);
7460         }
7461
7462         tg3_rings_reset(tp);
7463
7464         /* Initialize MAC address and backoff seed. */
7465         __tg3_set_mac_addr(tp, 0);
7466
7467         /* MTU + ethernet header + FCS + optional VLAN tag */
7468         tw32(MAC_RX_MTU_SIZE,
7469              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7470
7471         /* The slot time is changed by tg3_setup_phy if we
7472          * run at gigabit with half duplex.
7473          */
7474         tw32(MAC_TX_LENGTHS,
7475              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7476              (6 << TX_LENGTHS_IPG_SHIFT) |
7477              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7478
7479         /* Receive rules. */
7480         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7481         tw32(RCVLPC_CONFIG, 0x0181);
7482
7483         /* Calculate RDMAC_MODE setting early, we need it to determine
7484          * the RCVLPC_STATE_ENABLE mask.
7485          */
7486         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7487                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7488                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7489                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7490                       RDMAC_MODE_LNGREAD_ENAB);
7491
7492         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7493             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7494             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7495                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7496                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7497                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7498
7499         /* If statement applies to 5705 and 5750 PCI devices only */
7500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7501              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7502             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7503                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7504                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7505                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7506                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7507                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7508                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7509                 }
7510         }
7511
7512         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7513                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7514
7515         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7516                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7517
7518         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7519             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7520                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7521
7522         /* Receive/send statistics. */
7523         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7524                 val = tr32(RCVLPC_STATS_ENABLE);
7525                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7526                 tw32(RCVLPC_STATS_ENABLE, val);
7527         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7528                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7529                 val = tr32(RCVLPC_STATS_ENABLE);
7530                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7531                 tw32(RCVLPC_STATS_ENABLE, val);
7532         } else {
7533                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7534         }
7535         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7536         tw32(SNDDATAI_STATSENAB, 0xffffff);
7537         tw32(SNDDATAI_STATSCTRL,
7538              (SNDDATAI_SCTRL_ENABLE |
7539               SNDDATAI_SCTRL_FASTUPD));
7540
7541         /* Setup host coalescing engine. */
7542         tw32(HOSTCC_MODE, 0);
7543         for (i = 0; i < 2000; i++) {
7544                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7545                         break;
7546                 udelay(10);
7547         }
7548
7549         __tg3_set_coalesce(tp, &tp->coal);
7550
7551         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7552                 /* Status/statistics block address.  See tg3_timer,
7553                  * the tg3_periodic_fetch_stats call there, and
7554                  * tg3_get_stats to see how this works for 5705/5750 chips.
7555                  */
7556                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7557                      ((u64) tp->stats_mapping >> 32));
7558                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7559                      ((u64) tp->stats_mapping & 0xffffffff));
7560                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7561
7562                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7563
7564                 /* Clear statistics and status block memory areas */
7565                 for (i = NIC_SRAM_STATS_BLK;
7566                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7567                      i += sizeof(u32)) {
7568                         tg3_write_mem(tp, i, 0);
7569                         udelay(40);
7570                 }
7571         }
7572
7573         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7574
7575         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7576         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7577         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7578                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7579
7580         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7581                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7582                 /* reset to prevent losing 1st rx packet intermittently */
7583                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7584                 udelay(10);
7585         }
7586
7587         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7588                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7589         else
7590                 tp->mac_mode = 0;
7591         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7592                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7593         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7594             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7595             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7596                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7597         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7598         udelay(40);
7599
7600         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7601          * If TG3_FLG2_IS_NIC is zero, we should read the
7602          * register to preserve the GPIO settings for LOMs. The GPIOs,
7603          * whether used as inputs or outputs, are set by boot code after
7604          * reset.
7605          */
7606         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7607                 u32 gpio_mask;
7608
7609                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7610                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7611                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7612
7613                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7614                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7615                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7616
7617                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7618                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7619
7620                 tp->grc_local_ctrl &= ~gpio_mask;
7621                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7622
7623                 /* GPIO1 must be driven high for eeprom write protect */
7624                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7625                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7626                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7627         }
7628         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7629         udelay(100);
7630
7631         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7632                 val = tr32(MSGINT_MODE);
7633                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7634                 tw32(MSGINT_MODE, val);
7635         }
7636
7637         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7638                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7639                 udelay(40);
7640         }
7641
7642         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7643                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7644                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7645                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7646                WDMAC_MODE_LNGREAD_ENAB);
7647
7648         /* If statement applies to 5705 and 5750 PCI devices only */
7649         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7650              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7651             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7652                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7653                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7654                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7655                         /* nothing */
7656                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7657                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7658                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7659                         val |= WDMAC_MODE_RX_ACCEL;
7660                 }
7661         }
7662
7663         /* Enable host coalescing bug fix */
7664         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7665                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7666
7667         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7668                 val |= WDMAC_MODE_BURST_ALL_DATA;
7669
7670         tw32_f(WDMAC_MODE, val);
7671         udelay(40);
7672
7673         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7674                 u16 pcix_cmd;
7675
7676                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7677                                      &pcix_cmd);
7678                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7679                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7680                         pcix_cmd |= PCI_X_CMD_READ_2K;
7681                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7682                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7683                         pcix_cmd |= PCI_X_CMD_READ_2K;
7684                 }
7685                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7686                                       pcix_cmd);
7687         }
7688
7689         tw32_f(RDMAC_MODE, rdmac_mode);
7690         udelay(40);
7691
7692         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7693         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7694                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7695
7696         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7697                 tw32(SNDDATAC_MODE,
7698                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7699         else
7700                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7701
7702         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7703         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7704         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7705         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7706         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7707                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7708         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7709         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7710                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7711         tw32(SNDBDI_MODE, val);
7712         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7713
7714         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7715                 err = tg3_load_5701_a0_firmware_fix(tp);
7716                 if (err)
7717                         return err;
7718         }
7719
7720         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7721                 err = tg3_load_tso_firmware(tp);
7722                 if (err)
7723                         return err;
7724         }
7725
7726         tp->tx_mode = TX_MODE_ENABLE;
7727         tw32_f(MAC_TX_MODE, tp->tx_mode);
7728         udelay(100);
7729
7730         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7731                 u32 reg = MAC_RSS_INDIR_TBL_0;
7732                 u8 *ent = (u8 *)&val;
7733
7734                 /* Setup the indirection table */
7735                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7736                         int idx = i % sizeof(val);
7737
7738                         ent[idx] = i % (tp->irq_cnt - 1);
7739                         if (idx == sizeof(val) - 1) {
7740                                 tw32(reg, val);
7741                                 reg += 4;
7742                         }
7743                 }
7744
7745                 /* Setup the "secret" hash key. */
7746                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7747                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7748                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7749                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7750                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7751                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7752                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7753                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7754                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7755                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7756         }
7757
7758         tp->rx_mode = RX_MODE_ENABLE;
7759         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7760                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7761
7762         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7763                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7764                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7765                                RX_MODE_RSS_IPV6_HASH_EN |
7766                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7767                                RX_MODE_RSS_IPV4_HASH_EN |
7768                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7769
7770         tw32_f(MAC_RX_MODE, tp->rx_mode);
7771         udelay(10);
7772
7773         tw32(MAC_LED_CTRL, tp->led_ctrl);
7774
7775         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7776         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7777                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7778                 udelay(10);
7779         }
7780         tw32_f(MAC_RX_MODE, tp->rx_mode);
7781         udelay(10);
7782
7783         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7784                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7785                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7786                         /* Set drive transmission level to 1.2V  */
7787                         /* only if the signal pre-emphasis bit is not set  */
7788                         val = tr32(MAC_SERDES_CFG);
7789                         val &= 0xfffff000;
7790                         val |= 0x880;
7791                         tw32(MAC_SERDES_CFG, val);
7792                 }
7793                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7794                         tw32(MAC_SERDES_CFG, 0x616000);
7795         }
7796
7797         /* Prevent chip from dropping frames when flow control
7798          * is enabled.
7799          */
7800         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7801
7802         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7803             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7804                 /* Use hardware link auto-negotiation */
7805                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7806         }
7807
7808         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7809             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7810                 u32 tmp;
7811
7812                 tmp = tr32(SERDES_RX_CTRL);
7813                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7814                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7815                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7816                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7817         }
7818
7819         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7820                 if (tp->link_config.phy_is_low_power) {
7821                         tp->link_config.phy_is_low_power = 0;
7822                         tp->link_config.speed = tp->link_config.orig_speed;
7823                         tp->link_config.duplex = tp->link_config.orig_duplex;
7824                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7825                 }
7826
7827                 err = tg3_setup_phy(tp, 0);
7828                 if (err)
7829                         return err;
7830
7831                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7832                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7833                         u32 tmp;
7834
7835                         /* Clear CRC stats. */
7836                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7837                                 tg3_writephy(tp, MII_TG3_TEST1,
7838                                              tmp | MII_TG3_TEST1_CRC_EN);
7839                                 tg3_readphy(tp, 0x14, &tmp);
7840                         }
7841                 }
7842         }
7843
7844         __tg3_set_rx_mode(tp->dev);
7845
7846         /* Initialize receive rules. */
7847         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7848         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7849         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7850         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7851
7852         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7853             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7854                 limit = 8;
7855         else
7856                 limit = 16;
7857         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7858                 limit -= 4;
7859         switch (limit) {
7860         case 16:
7861                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7862         case 15:
7863                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7864         case 14:
7865                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7866         case 13:
7867                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7868         case 12:
7869                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7870         case 11:
7871                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7872         case 10:
7873                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7874         case 9:
7875                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7876         case 8:
7877                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7878         case 7:
7879                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7880         case 6:
7881                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7882         case 5:
7883                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7884         case 4:
7885                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7886         case 3:
7887                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7888         case 2:
7889         case 1:
7890
7891         default:
7892                 break;
7893         }
7894
7895         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7896                 /* Write our heartbeat update interval to APE. */
7897                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7898                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7899
7900         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7901
7902         return 0;
7903 }
7904
7905 /* Called at device open time to get the chip ready for
7906  * packet processing.  Invoked with tp->lock held.
7907  */
7908 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7909 {
7910         tg3_switch_clocks(tp);
7911
7912         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7913
7914         return tg3_reset_hw(tp, reset_phy);
7915 }
7916
7917 #define TG3_STAT_ADD32(PSTAT, REG) \
7918 do {    u32 __val = tr32(REG); \
7919         (PSTAT)->low += __val; \
7920         if ((PSTAT)->low < __val) \
7921                 (PSTAT)->high += 1; \
7922 } while (0)
7923
7924 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7925 {
7926         struct tg3_hw_stats *sp = tp->hw_stats;
7927
7928         if (!netif_carrier_ok(tp->dev))
7929                 return;
7930
7931         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7932         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7933         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7934         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7935         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7936         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7937         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7938         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7939         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7940         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7941         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7942         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7943         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7944
7945         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7946         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7947         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7948         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7949         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7950         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7951         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7952         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7953         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7954         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7955         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7956         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7957         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7958         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7959
7960         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7961         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7962         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7963 }
7964
7965 static void tg3_timer(unsigned long __opaque)
7966 {
7967         struct tg3 *tp = (struct tg3 *) __opaque;
7968
7969         if (tp->irq_sync)
7970                 goto restart_timer;
7971
7972         spin_lock(&tp->lock);
7973
7974         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7975                 /* All of this garbage is because when using non-tagged
7976                  * IRQ status the mailbox/status_block protocol the chip
7977                  * uses with the cpu is race prone.
7978                  */
7979                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7980                         tw32(GRC_LOCAL_CTRL,
7981                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7982                 } else {
7983                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7984                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7985                 }
7986
7987                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7988                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7989                         spin_unlock(&tp->lock);
7990                         schedule_work(&tp->reset_task);
7991                         return;
7992                 }
7993         }
7994
7995         /* This part only runs once per second. */
7996         if (!--tp->timer_counter) {
7997                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7998                         tg3_periodic_fetch_stats(tp);
7999
8000                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8001                         u32 mac_stat;
8002                         int phy_event;
8003
8004                         mac_stat = tr32(MAC_STATUS);
8005
8006                         phy_event = 0;
8007                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8008                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8009                                         phy_event = 1;
8010                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8011                                 phy_event = 1;
8012
8013                         if (phy_event)
8014                                 tg3_setup_phy(tp, 0);
8015                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8016                         u32 mac_stat = tr32(MAC_STATUS);
8017                         int need_setup = 0;
8018
8019                         if (netif_carrier_ok(tp->dev) &&
8020                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8021                                 need_setup = 1;
8022                         }
8023                         if (! netif_carrier_ok(tp->dev) &&
8024                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8025                                          MAC_STATUS_SIGNAL_DET))) {
8026                                 need_setup = 1;
8027                         }
8028                         if (need_setup) {
8029                                 if (!tp->serdes_counter) {
8030                                         tw32_f(MAC_MODE,
8031                                              (tp->mac_mode &
8032                                               ~MAC_MODE_PORT_MODE_MASK));
8033                                         udelay(40);
8034                                         tw32_f(MAC_MODE, tp->mac_mode);
8035                                         udelay(40);
8036                                 }
8037                                 tg3_setup_phy(tp, 0);
8038                         }
8039                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8040                         tg3_serdes_parallel_detect(tp);
8041
8042                 tp->timer_counter = tp->timer_multiplier;
8043         }
8044
8045         /* Heartbeat is only sent once every 2 seconds.
8046          *
8047          * The heartbeat is to tell the ASF firmware that the host
8048          * driver is still alive.  In the event that the OS crashes,
8049          * ASF needs to reset the hardware to free up the FIFO space
8050          * that may be filled with rx packets destined for the host.
8051          * If the FIFO is full, ASF will no longer function properly.
8052          *
8053          * Unintended resets have been reported on real time kernels
8054          * where the timer doesn't run on time.  Netpoll will also have
8055          * same problem.
8056          *
8057          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8058          * to check the ring condition when the heartbeat is expiring
8059          * before doing the reset.  This will prevent most unintended
8060          * resets.
8061          */
8062         if (!--tp->asf_counter) {
8063                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8064                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8065                         tg3_wait_for_event_ack(tp);
8066
8067                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8068                                       FWCMD_NICDRV_ALIVE3);
8069                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8070                         /* 5 seconds timeout */
8071                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8072
8073                         tg3_generate_fw_event(tp);
8074                 }
8075                 tp->asf_counter = tp->asf_multiplier;
8076         }
8077
8078         spin_unlock(&tp->lock);
8079
8080 restart_timer:
8081         tp->timer.expires = jiffies + tp->timer_offset;
8082         add_timer(&tp->timer);
8083 }
8084
8085 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8086 {
8087         irq_handler_t fn;
8088         unsigned long flags;
8089         char *name;
8090         struct tg3_napi *tnapi = &tp->napi[irq_num];
8091
8092         if (tp->irq_cnt == 1)
8093                 name = tp->dev->name;
8094         else {
8095                 name = &tnapi->irq_lbl[0];
8096                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8097                 name[IFNAMSIZ-1] = 0;
8098         }
8099
8100         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8101                 fn = tg3_msi;
8102                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8103                         fn = tg3_msi_1shot;
8104                 flags = IRQF_SAMPLE_RANDOM;
8105         } else {
8106                 fn = tg3_interrupt;
8107                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8108                         fn = tg3_interrupt_tagged;
8109                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8110         }
8111
8112         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8113 }
8114
8115 static int tg3_test_interrupt(struct tg3 *tp)
8116 {
8117         struct tg3_napi *tnapi = &tp->napi[0];
8118         struct net_device *dev = tp->dev;
8119         int err, i, intr_ok = 0;
8120         u32 val;
8121
8122         if (!netif_running(dev))
8123                 return -ENODEV;
8124
8125         tg3_disable_ints(tp);
8126
8127         free_irq(tnapi->irq_vec, tnapi);
8128
8129         /*
8130          * Turn off MSI one shot mode.  Otherwise this test has no
8131          * observable way to know whether the interrupt was delivered.
8132          */
8133         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8134             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8135                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8136                 tw32(MSGINT_MODE, val);
8137         }
8138
8139         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8140                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8141         if (err)
8142                 return err;
8143
8144         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8145         tg3_enable_ints(tp);
8146
8147         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8148                tnapi->coal_now);
8149
8150         for (i = 0; i < 5; i++) {
8151                 u32 int_mbox, misc_host_ctrl;
8152
8153                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8154                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8155
8156                 if ((int_mbox != 0) ||
8157                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8158                         intr_ok = 1;
8159                         break;
8160                 }
8161
8162                 msleep(10);
8163         }
8164
8165         tg3_disable_ints(tp);
8166
8167         free_irq(tnapi->irq_vec, tnapi);
8168
8169         err = tg3_request_irq(tp, 0);
8170
8171         if (err)
8172                 return err;
8173
8174         if (intr_ok) {
8175                 /* Reenable MSI one shot mode. */
8176                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8177                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8178                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8179                         tw32(MSGINT_MODE, val);
8180                 }
8181                 return 0;
8182         }
8183
8184         return -EIO;
8185 }
8186
8187 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8188  * successfully restored
8189  */
8190 static int tg3_test_msi(struct tg3 *tp)
8191 {
8192         int err;
8193         u16 pci_cmd;
8194
8195         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8196                 return 0;
8197
8198         /* Turn off SERR reporting in case MSI terminates with Master
8199          * Abort.
8200          */
8201         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8202         pci_write_config_word(tp->pdev, PCI_COMMAND,
8203                               pci_cmd & ~PCI_COMMAND_SERR);
8204
8205         err = tg3_test_interrupt(tp);
8206
8207         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8208
8209         if (!err)
8210                 return 0;
8211
8212         /* other failures */
8213         if (err != -EIO)
8214                 return err;
8215
8216         /* MSI test failed, go back to INTx mode */
8217         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8218                "switching to INTx mode. Please report this failure to "
8219                "the PCI maintainer and include system chipset information.\n",
8220                        tp->dev->name);
8221
8222         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8223
8224         pci_disable_msi(tp->pdev);
8225
8226         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8227
8228         err = tg3_request_irq(tp, 0);
8229         if (err)
8230                 return err;
8231
8232         /* Need to reset the chip because the MSI cycle may have terminated
8233          * with Master Abort.
8234          */
8235         tg3_full_lock(tp, 1);
8236
8237         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8238         err = tg3_init_hw(tp, 1);
8239
8240         tg3_full_unlock(tp);
8241
8242         if (err)
8243                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8244
8245         return err;
8246 }
8247
8248 static int tg3_request_firmware(struct tg3 *tp)
8249 {
8250         const __be32 *fw_data;
8251
8252         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8253                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8254                        tp->dev->name, tp->fw_needed);
8255                 return -ENOENT;
8256         }
8257
8258         fw_data = (void *)tp->fw->data;
8259
8260         /* Firmware blob starts with version numbers, followed by
8261          * start address and _full_ length including BSS sections
8262          * (which must be longer than the actual data, of course
8263          */
8264
8265         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8266         if (tp->fw_len < (tp->fw->size - 12)) {
8267                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8268                        tp->dev->name, tp->fw_len, tp->fw_needed);
8269                 release_firmware(tp->fw);
8270                 tp->fw = NULL;
8271                 return -EINVAL;
8272         }
8273
8274         /* We no longer need firmware; we have it. */
8275         tp->fw_needed = NULL;
8276         return 0;
8277 }
8278
8279 static bool tg3_enable_msix(struct tg3 *tp)
8280 {
8281         int i, rc, cpus = num_online_cpus();
8282         struct msix_entry msix_ent[tp->irq_max];
8283
8284         if (cpus == 1)
8285                 /* Just fallback to the simpler MSI mode. */
8286                 return false;
8287
8288         /*
8289          * We want as many rx rings enabled as there are cpus.
8290          * The first MSIX vector only deals with link interrupts, etc,
8291          * so we add one to the number of vectors we are requesting.
8292          */
8293         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8294
8295         for (i = 0; i < tp->irq_max; i++) {
8296                 msix_ent[i].entry  = i;
8297                 msix_ent[i].vector = 0;
8298         }
8299
8300         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8301         if (rc != 0) {
8302                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8303                         return false;
8304                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8305                         return false;
8306                 printk(KERN_NOTICE
8307                        "%s: Requested %d MSI-X vectors, received %d\n",
8308                        tp->dev->name, tp->irq_cnt, rc);
8309                 tp->irq_cnt = rc;
8310         }
8311
8312         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8313
8314         for (i = 0; i < tp->irq_max; i++)
8315                 tp->napi[i].irq_vec = msix_ent[i].vector;
8316
8317         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8318
8319         return true;
8320 }
8321
8322 static void tg3_ints_init(struct tg3 *tp)
8323 {
8324         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8325             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8326                 /* All MSI supporting chips should support tagged
8327                  * status.  Assert that this is the case.
8328                  */
8329                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8330                        "Not using MSI.\n", tp->dev->name);
8331                 goto defcfg;
8332         }
8333
8334         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8335                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8336         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8337                  pci_enable_msi(tp->pdev) == 0)
8338                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8339
8340         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8341                 u32 msi_mode = tr32(MSGINT_MODE);
8342                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8343                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8344                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8345         }
8346 defcfg:
8347         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8348                 tp->irq_cnt = 1;
8349                 tp->napi[0].irq_vec = tp->pdev->irq;
8350                 tp->dev->real_num_tx_queues = 1;
8351         }
8352 }
8353
8354 static void tg3_ints_fini(struct tg3 *tp)
8355 {
8356         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8357                 pci_disable_msix(tp->pdev);
8358         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8359                 pci_disable_msi(tp->pdev);
8360         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8361         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8362 }
8363
8364 static int tg3_open(struct net_device *dev)
8365 {
8366         struct tg3 *tp = netdev_priv(dev);
8367         int i, err;
8368
8369         if (tp->fw_needed) {
8370                 err = tg3_request_firmware(tp);
8371                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8372                         if (err)
8373                                 return err;
8374                 } else if (err) {
8375                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8376                                tp->dev->name);
8377                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8378                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8379                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8380                                tp->dev->name);
8381                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8382                 }
8383         }
8384
8385         netif_carrier_off(tp->dev);
8386
8387         err = tg3_set_power_state(tp, PCI_D0);
8388         if (err)
8389                 return err;
8390
8391         tg3_full_lock(tp, 0);
8392
8393         tg3_disable_ints(tp);
8394         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8395
8396         tg3_full_unlock(tp);
8397
8398         /*
8399          * Setup interrupts first so we know how
8400          * many NAPI resources to allocate
8401          */
8402         tg3_ints_init(tp);
8403
8404         /* The placement of this call is tied
8405          * to the setup and use of Host TX descriptors.
8406          */
8407         err = tg3_alloc_consistent(tp);
8408         if (err)
8409                 goto err_out1;
8410
8411         tg3_napi_enable(tp);
8412
8413         for (i = 0; i < tp->irq_cnt; i++) {
8414                 struct tg3_napi *tnapi = &tp->napi[i];
8415                 err = tg3_request_irq(tp, i);
8416                 if (err) {
8417                         for (i--; i >= 0; i--)
8418                                 free_irq(tnapi->irq_vec, tnapi);
8419                         break;
8420                 }
8421         }
8422
8423         if (err)
8424                 goto err_out2;
8425
8426         tg3_full_lock(tp, 0);
8427
8428         err = tg3_init_hw(tp, 1);
8429         if (err) {
8430                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8431                 tg3_free_rings(tp);
8432         } else {
8433                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8434                         tp->timer_offset = HZ;
8435                 else
8436                         tp->timer_offset = HZ / 10;
8437
8438                 BUG_ON(tp->timer_offset > HZ);
8439                 tp->timer_counter = tp->timer_multiplier =
8440                         (HZ / tp->timer_offset);
8441                 tp->asf_counter = tp->asf_multiplier =
8442                         ((HZ / tp->timer_offset) * 2);
8443
8444                 init_timer(&tp->timer);
8445                 tp->timer.expires = jiffies + tp->timer_offset;
8446                 tp->timer.data = (unsigned long) tp;
8447                 tp->timer.function = tg3_timer;
8448         }
8449
8450         tg3_full_unlock(tp);
8451
8452         if (err)
8453                 goto err_out3;
8454
8455         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8456                 err = tg3_test_msi(tp);
8457
8458                 if (err) {
8459                         tg3_full_lock(tp, 0);
8460                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8461                         tg3_free_rings(tp);
8462                         tg3_full_unlock(tp);
8463
8464                         goto err_out2;
8465                 }
8466
8467                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8468                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8469                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8470                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8471
8472                         tw32(PCIE_TRANSACTION_CFG,
8473                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8474                 }
8475         }
8476
8477         tg3_phy_start(tp);
8478
8479         tg3_full_lock(tp, 0);
8480
8481         add_timer(&tp->timer);
8482         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8483         tg3_enable_ints(tp);
8484
8485         tg3_full_unlock(tp);
8486
8487         netif_tx_start_all_queues(dev);
8488
8489         return 0;
8490
8491 err_out3:
8492         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8493                 struct tg3_napi *tnapi = &tp->napi[i];
8494                 free_irq(tnapi->irq_vec, tnapi);
8495         }
8496
8497 err_out2:
8498         tg3_napi_disable(tp);
8499         tg3_free_consistent(tp);
8500
8501 err_out1:
8502         tg3_ints_fini(tp);
8503         return err;
8504 }
8505
8506 #if 0
8507 /*static*/ void tg3_dump_state(struct tg3 *tp)
8508 {
8509         u32 val32, val32_2, val32_3, val32_4, val32_5;
8510         u16 val16;
8511         int i;
8512         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8513
8514         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8515         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8516         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8517                val16, val32);
8518
8519         /* MAC block */
8520         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8521                tr32(MAC_MODE), tr32(MAC_STATUS));
8522         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8523                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8524         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8525                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8526         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8527                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8528
8529         /* Send data initiator control block */
8530         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8531                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8532         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8533                tr32(SNDDATAI_STATSCTRL));
8534
8535         /* Send data completion control block */
8536         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8537
8538         /* Send BD ring selector block */
8539         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8540                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8541
8542         /* Send BD initiator control block */
8543         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8544                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8545
8546         /* Send BD completion control block */
8547         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8548
8549         /* Receive list placement control block */
8550         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8551                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8552         printk("       RCVLPC_STATSCTRL[%08x]\n",
8553                tr32(RCVLPC_STATSCTRL));
8554
8555         /* Receive data and receive BD initiator control block */
8556         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8557                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8558
8559         /* Receive data completion control block */
8560         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8561                tr32(RCVDCC_MODE));
8562
8563         /* Receive BD initiator control block */
8564         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8565                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8566
8567         /* Receive BD completion control block */
8568         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8569                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8570
8571         /* Receive list selector control block */
8572         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8573                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8574
8575         /* Mbuf cluster free block */
8576         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8577                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8578
8579         /* Host coalescing control block */
8580         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8581                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8582         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8583                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8584                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8585         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8586                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8587                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8588         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8589                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8590         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8591                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8592
8593         /* Memory arbiter control block */
8594         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8595                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8596
8597         /* Buffer manager control block */
8598         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8599                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8600         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8601                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8602         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8603                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8604                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8605                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8606
8607         /* Read DMA control block */
8608         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8609                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8610
8611         /* Write DMA control block */
8612         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8613                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8614
8615         /* DMA completion block */
8616         printk("DEBUG: DMAC_MODE[%08x]\n",
8617                tr32(DMAC_MODE));
8618
8619         /* GRC block */
8620         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8621                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8622         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8623                tr32(GRC_LOCAL_CTRL));
8624
8625         /* TG3_BDINFOs */
8626         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8627                tr32(RCVDBDI_JUMBO_BD + 0x0),
8628                tr32(RCVDBDI_JUMBO_BD + 0x4),
8629                tr32(RCVDBDI_JUMBO_BD + 0x8),
8630                tr32(RCVDBDI_JUMBO_BD + 0xc));
8631         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8632                tr32(RCVDBDI_STD_BD + 0x0),
8633                tr32(RCVDBDI_STD_BD + 0x4),
8634                tr32(RCVDBDI_STD_BD + 0x8),
8635                tr32(RCVDBDI_STD_BD + 0xc));
8636         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8637                tr32(RCVDBDI_MINI_BD + 0x0),
8638                tr32(RCVDBDI_MINI_BD + 0x4),
8639                tr32(RCVDBDI_MINI_BD + 0x8),
8640                tr32(RCVDBDI_MINI_BD + 0xc));
8641
8642         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8643         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8644         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8645         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8646         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8647                val32, val32_2, val32_3, val32_4);
8648
8649         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8650         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8651         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8652         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8653         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8654                val32, val32_2, val32_3, val32_4);
8655
8656         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8657         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8658         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8659         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8660         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8661         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8662                val32, val32_2, val32_3, val32_4, val32_5);
8663
8664         /* SW status block */
8665         printk(KERN_DEBUG
8666          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8667                sblk->status,
8668                sblk->status_tag,
8669                sblk->rx_jumbo_consumer,
8670                sblk->rx_consumer,
8671                sblk->rx_mini_consumer,
8672                sblk->idx[0].rx_producer,
8673                sblk->idx[0].tx_consumer);
8674
8675         /* SW statistics block */
8676         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8677                ((u32 *)tp->hw_stats)[0],
8678                ((u32 *)tp->hw_stats)[1],
8679                ((u32 *)tp->hw_stats)[2],
8680                ((u32 *)tp->hw_stats)[3]);
8681
8682         /* Mailboxes */
8683         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8684                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8685                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8686                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8687                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8688
8689         /* NIC side send descriptors. */
8690         for (i = 0; i < 6; i++) {
8691                 unsigned long txd;
8692
8693                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8694                         + (i * sizeof(struct tg3_tx_buffer_desc));
8695                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8696                        i,
8697                        readl(txd + 0x0), readl(txd + 0x4),
8698                        readl(txd + 0x8), readl(txd + 0xc));
8699         }
8700
8701         /* NIC side RX descriptors. */
8702         for (i = 0; i < 6; i++) {
8703                 unsigned long rxd;
8704
8705                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8706                         + (i * sizeof(struct tg3_rx_buffer_desc));
8707                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8708                        i,
8709                        readl(rxd + 0x0), readl(rxd + 0x4),
8710                        readl(rxd + 0x8), readl(rxd + 0xc));
8711                 rxd += (4 * sizeof(u32));
8712                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8713                        i,
8714                        readl(rxd + 0x0), readl(rxd + 0x4),
8715                        readl(rxd + 0x8), readl(rxd + 0xc));
8716         }
8717
8718         for (i = 0; i < 6; i++) {
8719                 unsigned long rxd;
8720
8721                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8722                         + (i * sizeof(struct tg3_rx_buffer_desc));
8723                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8724                        i,
8725                        readl(rxd + 0x0), readl(rxd + 0x4),
8726                        readl(rxd + 0x8), readl(rxd + 0xc));
8727                 rxd += (4 * sizeof(u32));
8728                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8729                        i,
8730                        readl(rxd + 0x0), readl(rxd + 0x4),
8731                        readl(rxd + 0x8), readl(rxd + 0xc));
8732         }
8733 }
8734 #endif
8735
8736 static struct net_device_stats *tg3_get_stats(struct net_device *);
8737 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8738
8739 static int tg3_close(struct net_device *dev)
8740 {
8741         int i;
8742         struct tg3 *tp = netdev_priv(dev);
8743
8744         tg3_napi_disable(tp);
8745         cancel_work_sync(&tp->reset_task);
8746
8747         netif_tx_stop_all_queues(dev);
8748
8749         del_timer_sync(&tp->timer);
8750
8751         tg3_phy_stop(tp);
8752
8753         tg3_full_lock(tp, 1);
8754 #if 0
8755         tg3_dump_state(tp);
8756 #endif
8757
8758         tg3_disable_ints(tp);
8759
8760         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8761         tg3_free_rings(tp);
8762         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8763
8764         tg3_full_unlock(tp);
8765
8766         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8767                 struct tg3_napi *tnapi = &tp->napi[i];
8768                 free_irq(tnapi->irq_vec, tnapi);
8769         }
8770
8771         tg3_ints_fini(tp);
8772
8773         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8774                sizeof(tp->net_stats_prev));
8775         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8776                sizeof(tp->estats_prev));
8777
8778         tg3_free_consistent(tp);
8779
8780         tg3_set_power_state(tp, PCI_D3hot);
8781
8782         netif_carrier_off(tp->dev);
8783
8784         return 0;
8785 }
8786
8787 static inline unsigned long get_stat64(tg3_stat64_t *val)
8788 {
8789         unsigned long ret;
8790
8791 #if (BITS_PER_LONG == 32)
8792         ret = val->low;
8793 #else
8794         ret = ((u64)val->high << 32) | ((u64)val->low);
8795 #endif
8796         return ret;
8797 }
8798
8799 static inline u64 get_estat64(tg3_stat64_t *val)
8800 {
8801        return ((u64)val->high << 32) | ((u64)val->low);
8802 }
8803
8804 static unsigned long calc_crc_errors(struct tg3 *tp)
8805 {
8806         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8807
8808         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8809             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8810              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8811                 u32 val;
8812
8813                 spin_lock_bh(&tp->lock);
8814                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8815                         tg3_writephy(tp, MII_TG3_TEST1,
8816                                      val | MII_TG3_TEST1_CRC_EN);
8817                         tg3_readphy(tp, 0x14, &val);
8818                 } else
8819                         val = 0;
8820                 spin_unlock_bh(&tp->lock);
8821
8822                 tp->phy_crc_errors += val;
8823
8824                 return tp->phy_crc_errors;
8825         }
8826
8827         return get_stat64(&hw_stats->rx_fcs_errors);
8828 }
8829
8830 #define ESTAT_ADD(member) \
8831         estats->member =        old_estats->member + \
8832                                 get_estat64(&hw_stats->member)
8833
8834 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8835 {
8836         struct tg3_ethtool_stats *estats = &tp->estats;
8837         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8838         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8839
8840         if (!hw_stats)
8841                 return old_estats;
8842
8843         ESTAT_ADD(rx_octets);
8844         ESTAT_ADD(rx_fragments);
8845         ESTAT_ADD(rx_ucast_packets);
8846         ESTAT_ADD(rx_mcast_packets);
8847         ESTAT_ADD(rx_bcast_packets);
8848         ESTAT_ADD(rx_fcs_errors);
8849         ESTAT_ADD(rx_align_errors);
8850         ESTAT_ADD(rx_xon_pause_rcvd);
8851         ESTAT_ADD(rx_xoff_pause_rcvd);
8852         ESTAT_ADD(rx_mac_ctrl_rcvd);
8853         ESTAT_ADD(rx_xoff_entered);
8854         ESTAT_ADD(rx_frame_too_long_errors);
8855         ESTAT_ADD(rx_jabbers);
8856         ESTAT_ADD(rx_undersize_packets);
8857         ESTAT_ADD(rx_in_length_errors);
8858         ESTAT_ADD(rx_out_length_errors);
8859         ESTAT_ADD(rx_64_or_less_octet_packets);
8860         ESTAT_ADD(rx_65_to_127_octet_packets);
8861         ESTAT_ADD(rx_128_to_255_octet_packets);
8862         ESTAT_ADD(rx_256_to_511_octet_packets);
8863         ESTAT_ADD(rx_512_to_1023_octet_packets);
8864         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8865         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8866         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8867         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8868         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8869
8870         ESTAT_ADD(tx_octets);
8871         ESTAT_ADD(tx_collisions);
8872         ESTAT_ADD(tx_xon_sent);
8873         ESTAT_ADD(tx_xoff_sent);
8874         ESTAT_ADD(tx_flow_control);
8875         ESTAT_ADD(tx_mac_errors);
8876         ESTAT_ADD(tx_single_collisions);
8877         ESTAT_ADD(tx_mult_collisions);
8878         ESTAT_ADD(tx_deferred);
8879         ESTAT_ADD(tx_excessive_collisions);
8880         ESTAT_ADD(tx_late_collisions);
8881         ESTAT_ADD(tx_collide_2times);
8882         ESTAT_ADD(tx_collide_3times);
8883         ESTAT_ADD(tx_collide_4times);
8884         ESTAT_ADD(tx_collide_5times);
8885         ESTAT_ADD(tx_collide_6times);
8886         ESTAT_ADD(tx_collide_7times);
8887         ESTAT_ADD(tx_collide_8times);
8888         ESTAT_ADD(tx_collide_9times);
8889         ESTAT_ADD(tx_collide_10times);
8890         ESTAT_ADD(tx_collide_11times);
8891         ESTAT_ADD(tx_collide_12times);
8892         ESTAT_ADD(tx_collide_13times);
8893         ESTAT_ADD(tx_collide_14times);
8894         ESTAT_ADD(tx_collide_15times);
8895         ESTAT_ADD(tx_ucast_packets);
8896         ESTAT_ADD(tx_mcast_packets);
8897         ESTAT_ADD(tx_bcast_packets);
8898         ESTAT_ADD(tx_carrier_sense_errors);
8899         ESTAT_ADD(tx_discards);
8900         ESTAT_ADD(tx_errors);
8901
8902         ESTAT_ADD(dma_writeq_full);
8903         ESTAT_ADD(dma_write_prioq_full);
8904         ESTAT_ADD(rxbds_empty);
8905         ESTAT_ADD(rx_discards);
8906         ESTAT_ADD(rx_errors);
8907         ESTAT_ADD(rx_threshold_hit);
8908
8909         ESTAT_ADD(dma_readq_full);
8910         ESTAT_ADD(dma_read_prioq_full);
8911         ESTAT_ADD(tx_comp_queue_full);
8912
8913         ESTAT_ADD(ring_set_send_prod_index);
8914         ESTAT_ADD(ring_status_update);
8915         ESTAT_ADD(nic_irqs);
8916         ESTAT_ADD(nic_avoided_irqs);
8917         ESTAT_ADD(nic_tx_threshold_hit);
8918
8919         return estats;
8920 }
8921
8922 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8923 {
8924         struct tg3 *tp = netdev_priv(dev);
8925         struct net_device_stats *stats = &tp->net_stats;
8926         struct net_device_stats *old_stats = &tp->net_stats_prev;
8927         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8928
8929         if (!hw_stats)
8930                 return old_stats;
8931
8932         stats->rx_packets = old_stats->rx_packets +
8933                 get_stat64(&hw_stats->rx_ucast_packets) +
8934                 get_stat64(&hw_stats->rx_mcast_packets) +
8935                 get_stat64(&hw_stats->rx_bcast_packets);
8936
8937         stats->tx_packets = old_stats->tx_packets +
8938                 get_stat64(&hw_stats->tx_ucast_packets) +
8939                 get_stat64(&hw_stats->tx_mcast_packets) +
8940                 get_stat64(&hw_stats->tx_bcast_packets);
8941
8942         stats->rx_bytes = old_stats->rx_bytes +
8943                 get_stat64(&hw_stats->rx_octets);
8944         stats->tx_bytes = old_stats->tx_bytes +
8945                 get_stat64(&hw_stats->tx_octets);
8946
8947         stats->rx_errors = old_stats->rx_errors +
8948                 get_stat64(&hw_stats->rx_errors);
8949         stats->tx_errors = old_stats->tx_errors +
8950                 get_stat64(&hw_stats->tx_errors) +
8951                 get_stat64(&hw_stats->tx_mac_errors) +
8952                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8953                 get_stat64(&hw_stats->tx_discards);
8954
8955         stats->multicast = old_stats->multicast +
8956                 get_stat64(&hw_stats->rx_mcast_packets);
8957         stats->collisions = old_stats->collisions +
8958                 get_stat64(&hw_stats->tx_collisions);
8959
8960         stats->rx_length_errors = old_stats->rx_length_errors +
8961                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8962                 get_stat64(&hw_stats->rx_undersize_packets);
8963
8964         stats->rx_over_errors = old_stats->rx_over_errors +
8965                 get_stat64(&hw_stats->rxbds_empty);
8966         stats->rx_frame_errors = old_stats->rx_frame_errors +
8967                 get_stat64(&hw_stats->rx_align_errors);
8968         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8969                 get_stat64(&hw_stats->tx_discards);
8970         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8971                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8972
8973         stats->rx_crc_errors = old_stats->rx_crc_errors +
8974                 calc_crc_errors(tp);
8975
8976         stats->rx_missed_errors = old_stats->rx_missed_errors +
8977                 get_stat64(&hw_stats->rx_discards);
8978
8979         return stats;
8980 }
8981
8982 static inline u32 calc_crc(unsigned char *buf, int len)
8983 {
8984         u32 reg;
8985         u32 tmp;
8986         int j, k;
8987
8988         reg = 0xffffffff;
8989
8990         for (j = 0; j < len; j++) {
8991                 reg ^= buf[j];
8992
8993                 for (k = 0; k < 8; k++) {
8994                         tmp = reg & 0x01;
8995
8996                         reg >>= 1;
8997
8998                         if (tmp) {
8999                                 reg ^= 0xedb88320;
9000                         }
9001                 }
9002         }
9003
9004         return ~reg;
9005 }
9006
9007 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9008 {
9009         /* accept or reject all multicast frames */
9010         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9011         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9012         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9013         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9014 }
9015
9016 static void __tg3_set_rx_mode(struct net_device *dev)
9017 {
9018         struct tg3 *tp = netdev_priv(dev);
9019         u32 rx_mode;
9020
9021         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9022                                   RX_MODE_KEEP_VLAN_TAG);
9023
9024         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9025          * flag clear.
9026          */
9027 #if TG3_VLAN_TAG_USED
9028         if (!tp->vlgrp &&
9029             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9030                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9031 #else
9032         /* By definition, VLAN is disabled always in this
9033          * case.
9034          */
9035         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9036                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9037 #endif
9038
9039         if (dev->flags & IFF_PROMISC) {
9040                 /* Promiscuous mode. */
9041                 rx_mode |= RX_MODE_PROMISC;
9042         } else if (dev->flags & IFF_ALLMULTI) {
9043                 /* Accept all multicast. */
9044                 tg3_set_multi (tp, 1);
9045         } else if (dev->mc_count < 1) {
9046                 /* Reject all multicast. */
9047                 tg3_set_multi (tp, 0);
9048         } else {
9049                 /* Accept one or more multicast(s). */
9050                 struct dev_mc_list *mclist;
9051                 unsigned int i;
9052                 u32 mc_filter[4] = { 0, };
9053                 u32 regidx;
9054                 u32 bit;
9055                 u32 crc;
9056
9057                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9058                      i++, mclist = mclist->next) {
9059
9060                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9061                         bit = ~crc & 0x7f;
9062                         regidx = (bit & 0x60) >> 5;
9063                         bit &= 0x1f;
9064                         mc_filter[regidx] |= (1 << bit);
9065                 }
9066
9067                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9068                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9069                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9070                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9071         }
9072
9073         if (rx_mode != tp->rx_mode) {
9074                 tp->rx_mode = rx_mode;
9075                 tw32_f(MAC_RX_MODE, rx_mode);
9076                 udelay(10);
9077         }
9078 }
9079
9080 static void tg3_set_rx_mode(struct net_device *dev)
9081 {
9082         struct tg3 *tp = netdev_priv(dev);
9083
9084         if (!netif_running(dev))
9085                 return;
9086
9087         tg3_full_lock(tp, 0);
9088         __tg3_set_rx_mode(dev);
9089         tg3_full_unlock(tp);
9090 }
9091
9092 #define TG3_REGDUMP_LEN         (32 * 1024)
9093
9094 static int tg3_get_regs_len(struct net_device *dev)
9095 {
9096         return TG3_REGDUMP_LEN;
9097 }
9098
9099 static void tg3_get_regs(struct net_device *dev,
9100                 struct ethtool_regs *regs, void *_p)
9101 {
9102         u32 *p = _p;
9103         struct tg3 *tp = netdev_priv(dev);
9104         u8 *orig_p = _p;
9105         int i;
9106
9107         regs->version = 0;
9108
9109         memset(p, 0, TG3_REGDUMP_LEN);
9110
9111         if (tp->link_config.phy_is_low_power)
9112                 return;
9113
9114         tg3_full_lock(tp, 0);
9115
9116 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9117 #define GET_REG32_LOOP(base,len)                \
9118 do {    p = (u32 *)(orig_p + (base));           \
9119         for (i = 0; i < len; i += 4)            \
9120                 __GET_REG32((base) + i);        \
9121 } while (0)
9122 #define GET_REG32_1(reg)                        \
9123 do {    p = (u32 *)(orig_p + (reg));            \
9124         __GET_REG32((reg));                     \
9125 } while (0)
9126
9127         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9128         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9129         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9130         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9131         GET_REG32_1(SNDDATAC_MODE);
9132         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9133         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9134         GET_REG32_1(SNDBDC_MODE);
9135         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9136         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9137         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9138         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9139         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9140         GET_REG32_1(RCVDCC_MODE);
9141         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9142         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9143         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9144         GET_REG32_1(MBFREE_MODE);
9145         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9146         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9147         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9148         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9149         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9150         GET_REG32_1(RX_CPU_MODE);
9151         GET_REG32_1(RX_CPU_STATE);
9152         GET_REG32_1(RX_CPU_PGMCTR);
9153         GET_REG32_1(RX_CPU_HWBKPT);
9154         GET_REG32_1(TX_CPU_MODE);
9155         GET_REG32_1(TX_CPU_STATE);
9156         GET_REG32_1(TX_CPU_PGMCTR);
9157         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9158         GET_REG32_LOOP(FTQ_RESET, 0x120);
9159         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9160         GET_REG32_1(DMAC_MODE);
9161         GET_REG32_LOOP(GRC_MODE, 0x4c);
9162         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9163                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9164
9165 #undef __GET_REG32
9166 #undef GET_REG32_LOOP
9167 #undef GET_REG32_1
9168
9169         tg3_full_unlock(tp);
9170 }
9171
9172 static int tg3_get_eeprom_len(struct net_device *dev)
9173 {
9174         struct tg3 *tp = netdev_priv(dev);
9175
9176         return tp->nvram_size;
9177 }
9178
9179 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9180 {
9181         struct tg3 *tp = netdev_priv(dev);
9182         int ret;
9183         u8  *pd;
9184         u32 i, offset, len, b_offset, b_count;
9185         __be32 val;
9186
9187         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9188                 return -EINVAL;
9189
9190         if (tp->link_config.phy_is_low_power)
9191                 return -EAGAIN;
9192
9193         offset = eeprom->offset;
9194         len = eeprom->len;
9195         eeprom->len = 0;
9196
9197         eeprom->magic = TG3_EEPROM_MAGIC;
9198
9199         if (offset & 3) {
9200                 /* adjustments to start on required 4 byte boundary */
9201                 b_offset = offset & 3;
9202                 b_count = 4 - b_offset;
9203                 if (b_count > len) {
9204                         /* i.e. offset=1 len=2 */
9205                         b_count = len;
9206                 }
9207                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9208                 if (ret)
9209                         return ret;
9210                 memcpy(data, ((char*)&val) + b_offset, b_count);
9211                 len -= b_count;
9212                 offset += b_count;
9213                 eeprom->len += b_count;
9214         }
9215
9216         /* read bytes upto the last 4 byte boundary */
9217         pd = &data[eeprom->len];
9218         for (i = 0; i < (len - (len & 3)); i += 4) {
9219                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9220                 if (ret) {
9221                         eeprom->len += i;
9222                         return ret;
9223                 }
9224                 memcpy(pd + i, &val, 4);
9225         }
9226         eeprom->len += i;
9227
9228         if (len & 3) {
9229                 /* read last bytes not ending on 4 byte boundary */
9230                 pd = &data[eeprom->len];
9231                 b_count = len & 3;
9232                 b_offset = offset + len - b_count;
9233                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9234                 if (ret)
9235                         return ret;
9236                 memcpy(pd, &val, b_count);
9237                 eeprom->len += b_count;
9238         }
9239         return 0;
9240 }
9241
9242 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9243
9244 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9245 {
9246         struct tg3 *tp = netdev_priv(dev);
9247         int ret;
9248         u32 offset, len, b_offset, odd_len;
9249         u8 *buf;
9250         __be32 start, end;
9251
9252         if (tp->link_config.phy_is_low_power)
9253                 return -EAGAIN;
9254
9255         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9256             eeprom->magic != TG3_EEPROM_MAGIC)
9257                 return -EINVAL;
9258
9259         offset = eeprom->offset;
9260         len = eeprom->len;
9261
9262         if ((b_offset = (offset & 3))) {
9263                 /* adjustments to start on required 4 byte boundary */
9264                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9265                 if (ret)
9266                         return ret;
9267                 len += b_offset;
9268                 offset &= ~3;
9269                 if (len < 4)
9270                         len = 4;
9271         }
9272
9273         odd_len = 0;
9274         if (len & 3) {
9275                 /* adjustments to end on required 4 byte boundary */
9276                 odd_len = 1;
9277                 len = (len + 3) & ~3;
9278                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9279                 if (ret)
9280                         return ret;
9281         }
9282
9283         buf = data;
9284         if (b_offset || odd_len) {
9285                 buf = kmalloc(len, GFP_KERNEL);
9286                 if (!buf)
9287                         return -ENOMEM;
9288                 if (b_offset)
9289                         memcpy(buf, &start, 4);
9290                 if (odd_len)
9291                         memcpy(buf+len-4, &end, 4);
9292                 memcpy(buf + b_offset, data, eeprom->len);
9293         }
9294
9295         ret = tg3_nvram_write_block(tp, offset, len, buf);
9296
9297         if (buf != data)
9298                 kfree(buf);
9299
9300         return ret;
9301 }
9302
9303 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9304 {
9305         struct tg3 *tp = netdev_priv(dev);
9306
9307         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9308                 struct phy_device *phydev;
9309                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9310                         return -EAGAIN;
9311                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9312                 return phy_ethtool_gset(phydev, cmd);
9313         }
9314
9315         cmd->supported = (SUPPORTED_Autoneg);
9316
9317         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9318                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9319                                    SUPPORTED_1000baseT_Full);
9320
9321         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9322                 cmd->supported |= (SUPPORTED_100baseT_Half |
9323                                   SUPPORTED_100baseT_Full |
9324                                   SUPPORTED_10baseT_Half |
9325                                   SUPPORTED_10baseT_Full |
9326                                   SUPPORTED_TP);
9327                 cmd->port = PORT_TP;
9328         } else {
9329                 cmd->supported |= SUPPORTED_FIBRE;
9330                 cmd->port = PORT_FIBRE;
9331         }
9332
9333         cmd->advertising = tp->link_config.advertising;
9334         if (netif_running(dev)) {
9335                 cmd->speed = tp->link_config.active_speed;
9336                 cmd->duplex = tp->link_config.active_duplex;
9337         }
9338         cmd->phy_address = tp->phy_addr;
9339         cmd->transceiver = XCVR_INTERNAL;
9340         cmd->autoneg = tp->link_config.autoneg;
9341         cmd->maxtxpkt = 0;
9342         cmd->maxrxpkt = 0;
9343         return 0;
9344 }
9345
9346 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9347 {
9348         struct tg3 *tp = netdev_priv(dev);
9349
9350         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9351                 struct phy_device *phydev;
9352                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9353                         return -EAGAIN;
9354                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9355                 return phy_ethtool_sset(phydev, cmd);
9356         }
9357
9358         if (cmd->autoneg != AUTONEG_ENABLE &&
9359             cmd->autoneg != AUTONEG_DISABLE)
9360                 return -EINVAL;
9361
9362         if (cmd->autoneg == AUTONEG_DISABLE &&
9363             cmd->duplex != DUPLEX_FULL &&
9364             cmd->duplex != DUPLEX_HALF)
9365                 return -EINVAL;
9366
9367         if (cmd->autoneg == AUTONEG_ENABLE) {
9368                 u32 mask = ADVERTISED_Autoneg |
9369                            ADVERTISED_Pause |
9370                            ADVERTISED_Asym_Pause;
9371
9372                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9373                         mask |= ADVERTISED_1000baseT_Half |
9374                                 ADVERTISED_1000baseT_Full;
9375
9376                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9377                         mask |= ADVERTISED_100baseT_Half |
9378                                 ADVERTISED_100baseT_Full |
9379                                 ADVERTISED_10baseT_Half |
9380                                 ADVERTISED_10baseT_Full |
9381                                 ADVERTISED_TP;
9382                 else
9383                         mask |= ADVERTISED_FIBRE;
9384
9385                 if (cmd->advertising & ~mask)
9386                         return -EINVAL;
9387
9388                 mask &= (ADVERTISED_1000baseT_Half |
9389                          ADVERTISED_1000baseT_Full |
9390                          ADVERTISED_100baseT_Half |
9391                          ADVERTISED_100baseT_Full |
9392                          ADVERTISED_10baseT_Half |
9393                          ADVERTISED_10baseT_Full);
9394
9395                 cmd->advertising &= mask;
9396         } else {
9397                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9398                         if (cmd->speed != SPEED_1000)
9399                                 return -EINVAL;
9400
9401                         if (cmd->duplex != DUPLEX_FULL)
9402                                 return -EINVAL;
9403                 } else {
9404                         if (cmd->speed != SPEED_100 &&
9405                             cmd->speed != SPEED_10)
9406                                 return -EINVAL;
9407                 }
9408         }
9409
9410         tg3_full_lock(tp, 0);
9411
9412         tp->link_config.autoneg = cmd->autoneg;
9413         if (cmd->autoneg == AUTONEG_ENABLE) {
9414                 tp->link_config.advertising = (cmd->advertising |
9415                                               ADVERTISED_Autoneg);
9416                 tp->link_config.speed = SPEED_INVALID;
9417                 tp->link_config.duplex = DUPLEX_INVALID;
9418         } else {
9419                 tp->link_config.advertising = 0;
9420                 tp->link_config.speed = cmd->speed;
9421                 tp->link_config.duplex = cmd->duplex;
9422         }
9423
9424         tp->link_config.orig_speed = tp->link_config.speed;
9425         tp->link_config.orig_duplex = tp->link_config.duplex;
9426         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9427
9428         if (netif_running(dev))
9429                 tg3_setup_phy(tp, 1);
9430
9431         tg3_full_unlock(tp);
9432
9433         return 0;
9434 }
9435
9436 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9437 {
9438         struct tg3 *tp = netdev_priv(dev);
9439
9440         strcpy(info->driver, DRV_MODULE_NAME);
9441         strcpy(info->version, DRV_MODULE_VERSION);
9442         strcpy(info->fw_version, tp->fw_ver);
9443         strcpy(info->bus_info, pci_name(tp->pdev));
9444 }
9445
9446 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9447 {
9448         struct tg3 *tp = netdev_priv(dev);
9449
9450         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9451             device_can_wakeup(&tp->pdev->dev))
9452                 wol->supported = WAKE_MAGIC;
9453         else
9454                 wol->supported = 0;
9455         wol->wolopts = 0;
9456         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9457             device_can_wakeup(&tp->pdev->dev))
9458                 wol->wolopts = WAKE_MAGIC;
9459         memset(&wol->sopass, 0, sizeof(wol->sopass));
9460 }
9461
9462 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9463 {
9464         struct tg3 *tp = netdev_priv(dev);
9465         struct device *dp = &tp->pdev->dev;
9466
9467         if (wol->wolopts & ~WAKE_MAGIC)
9468                 return -EINVAL;
9469         if ((wol->wolopts & WAKE_MAGIC) &&
9470             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9471                 return -EINVAL;
9472
9473         spin_lock_bh(&tp->lock);
9474         if (wol->wolopts & WAKE_MAGIC) {
9475                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9476                 device_set_wakeup_enable(dp, true);
9477         } else {
9478                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9479                 device_set_wakeup_enable(dp, false);
9480         }
9481         spin_unlock_bh(&tp->lock);
9482
9483         return 0;
9484 }
9485
9486 static u32 tg3_get_msglevel(struct net_device *dev)
9487 {
9488         struct tg3 *tp = netdev_priv(dev);
9489         return tp->msg_enable;
9490 }
9491
9492 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9493 {
9494         struct tg3 *tp = netdev_priv(dev);
9495         tp->msg_enable = value;
9496 }
9497
9498 static int tg3_set_tso(struct net_device *dev, u32 value)
9499 {
9500         struct tg3 *tp = netdev_priv(dev);
9501
9502         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9503                 if (value)
9504                         return -EINVAL;
9505                 return 0;
9506         }
9507         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9508             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9509                 if (value) {
9510                         dev->features |= NETIF_F_TSO6;
9511                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9512                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9513                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9514                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9515                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9516                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9517                                 dev->features |= NETIF_F_TSO_ECN;
9518                 } else
9519                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9520         }
9521         return ethtool_op_set_tso(dev, value);
9522 }
9523
9524 static int tg3_nway_reset(struct net_device *dev)
9525 {
9526         struct tg3 *tp = netdev_priv(dev);
9527         int r;
9528
9529         if (!netif_running(dev))
9530                 return -EAGAIN;
9531
9532         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9533                 return -EINVAL;
9534
9535         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9536                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9537                         return -EAGAIN;
9538                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9539         } else {
9540                 u32 bmcr;
9541
9542                 spin_lock_bh(&tp->lock);
9543                 r = -EINVAL;
9544                 tg3_readphy(tp, MII_BMCR, &bmcr);
9545                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9546                     ((bmcr & BMCR_ANENABLE) ||
9547                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9548                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9549                                                    BMCR_ANENABLE);
9550                         r = 0;
9551                 }
9552                 spin_unlock_bh(&tp->lock);
9553         }
9554
9555         return r;
9556 }
9557
9558 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9559 {
9560         struct tg3 *tp = netdev_priv(dev);
9561
9562         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9563         ering->rx_mini_max_pending = 0;
9564         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9565                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9566         else
9567                 ering->rx_jumbo_max_pending = 0;
9568
9569         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9570
9571         ering->rx_pending = tp->rx_pending;
9572         ering->rx_mini_pending = 0;
9573         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9574                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9575         else
9576                 ering->rx_jumbo_pending = 0;
9577
9578         ering->tx_pending = tp->napi[0].tx_pending;
9579 }
9580
9581 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9582 {
9583         struct tg3 *tp = netdev_priv(dev);
9584         int i, irq_sync = 0, err = 0;
9585
9586         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9587             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9588             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9589             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9590             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9591              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9592                 return -EINVAL;
9593
9594         if (netif_running(dev)) {
9595                 tg3_phy_stop(tp);
9596                 tg3_netif_stop(tp);
9597                 irq_sync = 1;
9598         }
9599
9600         tg3_full_lock(tp, irq_sync);
9601
9602         tp->rx_pending = ering->rx_pending;
9603
9604         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9605             tp->rx_pending > 63)
9606                 tp->rx_pending = 63;
9607         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9608
9609         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9610                 tp->napi[i].tx_pending = ering->tx_pending;
9611
9612         if (netif_running(dev)) {
9613                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9614                 err = tg3_restart_hw(tp, 1);
9615                 if (!err)
9616                         tg3_netif_start(tp);
9617         }
9618
9619         tg3_full_unlock(tp);
9620
9621         if (irq_sync && !err)
9622                 tg3_phy_start(tp);
9623
9624         return err;
9625 }
9626
9627 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9628 {
9629         struct tg3 *tp = netdev_priv(dev);
9630
9631         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9632
9633         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9634                 epause->rx_pause = 1;
9635         else
9636                 epause->rx_pause = 0;
9637
9638         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9639                 epause->tx_pause = 1;
9640         else
9641                 epause->tx_pause = 0;
9642 }
9643
9644 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9645 {
9646         struct tg3 *tp = netdev_priv(dev);
9647         int err = 0;
9648
9649         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9650                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9651                         return -EAGAIN;
9652
9653                 if (epause->autoneg) {
9654                         u32 newadv;
9655                         struct phy_device *phydev;
9656
9657                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9658
9659                         if (epause->rx_pause) {
9660                                 if (epause->tx_pause)
9661                                         newadv = ADVERTISED_Pause;
9662                                 else
9663                                         newadv = ADVERTISED_Pause |
9664                                                  ADVERTISED_Asym_Pause;
9665                         } else if (epause->tx_pause) {
9666                                 newadv = ADVERTISED_Asym_Pause;
9667                         } else
9668                                 newadv = 0;
9669
9670                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9671                                 u32 oldadv = phydev->advertising &
9672                                              (ADVERTISED_Pause |
9673                                               ADVERTISED_Asym_Pause);
9674                                 if (oldadv != newadv) {
9675                                         phydev->advertising &=
9676                                                 ~(ADVERTISED_Pause |
9677                                                   ADVERTISED_Asym_Pause);
9678                                         phydev->advertising |= newadv;
9679                                         err = phy_start_aneg(phydev);
9680                                 }
9681                         } else {
9682                                 tp->link_config.advertising &=
9683                                                 ~(ADVERTISED_Pause |
9684                                                   ADVERTISED_Asym_Pause);
9685                                 tp->link_config.advertising |= newadv;
9686                         }
9687                 } else {
9688                         if (epause->rx_pause)
9689                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9690                         else
9691                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9692
9693                         if (epause->tx_pause)
9694                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9695                         else
9696                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9697
9698                         if (netif_running(dev))
9699                                 tg3_setup_flow_control(tp, 0, 0);
9700                 }
9701         } else {
9702                 int irq_sync = 0;
9703
9704                 if (netif_running(dev)) {
9705                         tg3_netif_stop(tp);
9706                         irq_sync = 1;
9707                 }
9708
9709                 tg3_full_lock(tp, irq_sync);
9710
9711                 if (epause->autoneg)
9712                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9713                 else
9714                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9715                 if (epause->rx_pause)
9716                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9717                 else
9718                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9719                 if (epause->tx_pause)
9720                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9721                 else
9722                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9723
9724                 if (netif_running(dev)) {
9725                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9726                         err = tg3_restart_hw(tp, 1);
9727                         if (!err)
9728                                 tg3_netif_start(tp);
9729                 }
9730
9731                 tg3_full_unlock(tp);
9732         }
9733
9734         return err;
9735 }
9736
9737 static u32 tg3_get_rx_csum(struct net_device *dev)
9738 {
9739         struct tg3 *tp = netdev_priv(dev);
9740         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9741 }
9742
9743 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9744 {
9745         struct tg3 *tp = netdev_priv(dev);
9746
9747         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9748                 if (data != 0)
9749                         return -EINVAL;
9750                 return 0;
9751         }
9752
9753         spin_lock_bh(&tp->lock);
9754         if (data)
9755                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9756         else
9757                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9758         spin_unlock_bh(&tp->lock);
9759
9760         return 0;
9761 }
9762
9763 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9764 {
9765         struct tg3 *tp = netdev_priv(dev);
9766
9767         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9768                 if (data != 0)
9769                         return -EINVAL;
9770                 return 0;
9771         }
9772
9773         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9774                 ethtool_op_set_tx_ipv6_csum(dev, data);
9775         else
9776                 ethtool_op_set_tx_csum(dev, data);
9777
9778         return 0;
9779 }
9780
9781 static int tg3_get_sset_count (struct net_device *dev, int sset)
9782 {
9783         switch (sset) {
9784         case ETH_SS_TEST:
9785                 return TG3_NUM_TEST;
9786         case ETH_SS_STATS:
9787                 return TG3_NUM_STATS;
9788         default:
9789                 return -EOPNOTSUPP;
9790         }
9791 }
9792
9793 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9794 {
9795         switch (stringset) {
9796         case ETH_SS_STATS:
9797                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9798                 break;
9799         case ETH_SS_TEST:
9800                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9801                 break;
9802         default:
9803                 WARN_ON(1);     /* we need a WARN() */
9804                 break;
9805         }
9806 }
9807
9808 static int tg3_phys_id(struct net_device *dev, u32 data)
9809 {
9810         struct tg3 *tp = netdev_priv(dev);
9811         int i;
9812
9813         if (!netif_running(tp->dev))
9814                 return -EAGAIN;
9815
9816         if (data == 0)
9817                 data = UINT_MAX / 2;
9818
9819         for (i = 0; i < (data * 2); i++) {
9820                 if ((i % 2) == 0)
9821                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9822                                            LED_CTRL_1000MBPS_ON |
9823                                            LED_CTRL_100MBPS_ON |
9824                                            LED_CTRL_10MBPS_ON |
9825                                            LED_CTRL_TRAFFIC_OVERRIDE |
9826                                            LED_CTRL_TRAFFIC_BLINK |
9827                                            LED_CTRL_TRAFFIC_LED);
9828
9829                 else
9830                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9831                                            LED_CTRL_TRAFFIC_OVERRIDE);
9832
9833                 if (msleep_interruptible(500))
9834                         break;
9835         }
9836         tw32(MAC_LED_CTRL, tp->led_ctrl);
9837         return 0;
9838 }
9839
9840 static void tg3_get_ethtool_stats (struct net_device *dev,
9841                                    struct ethtool_stats *estats, u64 *tmp_stats)
9842 {
9843         struct tg3 *tp = netdev_priv(dev);
9844         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9845 }
9846
9847 #define NVRAM_TEST_SIZE 0x100
9848 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9849 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9850 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9851 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9852 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9853
9854 static int tg3_test_nvram(struct tg3 *tp)
9855 {
9856         u32 csum, magic;
9857         __be32 *buf;
9858         int i, j, k, err = 0, size;
9859
9860         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9861                 return 0;
9862
9863         if (tg3_nvram_read(tp, 0, &magic) != 0)
9864                 return -EIO;
9865
9866         if (magic == TG3_EEPROM_MAGIC)
9867                 size = NVRAM_TEST_SIZE;
9868         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9869                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9870                     TG3_EEPROM_SB_FORMAT_1) {
9871                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9872                         case TG3_EEPROM_SB_REVISION_0:
9873                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9874                                 break;
9875                         case TG3_EEPROM_SB_REVISION_2:
9876                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9877                                 break;
9878                         case TG3_EEPROM_SB_REVISION_3:
9879                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9880                                 break;
9881                         default:
9882                                 return 0;
9883                         }
9884                 } else
9885                         return 0;
9886         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9887                 size = NVRAM_SELFBOOT_HW_SIZE;
9888         else
9889                 return -EIO;
9890
9891         buf = kmalloc(size, GFP_KERNEL);
9892         if (buf == NULL)
9893                 return -ENOMEM;
9894
9895         err = -EIO;
9896         for (i = 0, j = 0; i < size; i += 4, j++) {
9897                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9898                 if (err)
9899                         break;
9900         }
9901         if (i < size)
9902                 goto out;
9903
9904         /* Selfboot format */
9905         magic = be32_to_cpu(buf[0]);
9906         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9907             TG3_EEPROM_MAGIC_FW) {
9908                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9909
9910                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9911                     TG3_EEPROM_SB_REVISION_2) {
9912                         /* For rev 2, the csum doesn't include the MBA. */
9913                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9914                                 csum8 += buf8[i];
9915                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9916                                 csum8 += buf8[i];
9917                 } else {
9918                         for (i = 0; i < size; i++)
9919                                 csum8 += buf8[i];
9920                 }
9921
9922                 if (csum8 == 0) {
9923                         err = 0;
9924                         goto out;
9925                 }
9926
9927                 err = -EIO;
9928                 goto out;
9929         }
9930
9931         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9932             TG3_EEPROM_MAGIC_HW) {
9933                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9934                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9935                 u8 *buf8 = (u8 *) buf;
9936
9937                 /* Separate the parity bits and the data bytes.  */
9938                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9939                         if ((i == 0) || (i == 8)) {
9940                                 int l;
9941                                 u8 msk;
9942
9943                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9944                                         parity[k++] = buf8[i] & msk;
9945                                 i++;
9946                         }
9947                         else if (i == 16) {
9948                                 int l;
9949                                 u8 msk;
9950
9951                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9952                                         parity[k++] = buf8[i] & msk;
9953                                 i++;
9954
9955                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9956                                         parity[k++] = buf8[i] & msk;
9957                                 i++;
9958                         }
9959                         data[j++] = buf8[i];
9960                 }
9961
9962                 err = -EIO;
9963                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9964                         u8 hw8 = hweight8(data[i]);
9965
9966                         if ((hw8 & 0x1) && parity[i])
9967                                 goto out;
9968                         else if (!(hw8 & 0x1) && !parity[i])
9969                                 goto out;
9970                 }
9971                 err = 0;
9972                 goto out;
9973         }
9974
9975         /* Bootstrap checksum at offset 0x10 */
9976         csum = calc_crc((unsigned char *) buf, 0x10);
9977         if (csum != be32_to_cpu(buf[0x10/4]))
9978                 goto out;
9979
9980         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9981         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9982         if (csum != be32_to_cpu(buf[0xfc/4]))
9983                 goto out;
9984
9985         err = 0;
9986
9987 out:
9988         kfree(buf);
9989         return err;
9990 }
9991
9992 #define TG3_SERDES_TIMEOUT_SEC  2
9993 #define TG3_COPPER_TIMEOUT_SEC  6
9994
9995 static int tg3_test_link(struct tg3 *tp)
9996 {
9997         int i, max;
9998
9999         if (!netif_running(tp->dev))
10000                 return -ENODEV;
10001
10002         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10003                 max = TG3_SERDES_TIMEOUT_SEC;
10004         else
10005                 max = TG3_COPPER_TIMEOUT_SEC;
10006
10007         for (i = 0; i < max; i++) {
10008                 if (netif_carrier_ok(tp->dev))
10009                         return 0;
10010
10011                 if (msleep_interruptible(1000))
10012                         break;
10013         }
10014
10015         return -EIO;
10016 }
10017
10018 /* Only test the commonly used registers */
10019 static int tg3_test_registers(struct tg3 *tp)
10020 {
10021         int i, is_5705, is_5750;
10022         u32 offset, read_mask, write_mask, val, save_val, read_val;
10023         static struct {
10024                 u16 offset;
10025                 u16 flags;
10026 #define TG3_FL_5705     0x1
10027 #define TG3_FL_NOT_5705 0x2
10028 #define TG3_FL_NOT_5788 0x4
10029 #define TG3_FL_NOT_5750 0x8
10030                 u32 read_mask;
10031                 u32 write_mask;
10032         } reg_tbl[] = {
10033                 /* MAC Control Registers */
10034                 { MAC_MODE, TG3_FL_NOT_5705,
10035                         0x00000000, 0x00ef6f8c },
10036                 { MAC_MODE, TG3_FL_5705,
10037                         0x00000000, 0x01ef6b8c },
10038                 { MAC_STATUS, TG3_FL_NOT_5705,
10039                         0x03800107, 0x00000000 },
10040                 { MAC_STATUS, TG3_FL_5705,
10041                         0x03800100, 0x00000000 },
10042                 { MAC_ADDR_0_HIGH, 0x0000,
10043                         0x00000000, 0x0000ffff },
10044                 { MAC_ADDR_0_LOW, 0x0000,
10045                         0x00000000, 0xffffffff },
10046                 { MAC_RX_MTU_SIZE, 0x0000,
10047                         0x00000000, 0x0000ffff },
10048                 { MAC_TX_MODE, 0x0000,
10049                         0x00000000, 0x00000070 },
10050                 { MAC_TX_LENGTHS, 0x0000,
10051                         0x00000000, 0x00003fff },
10052                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10053                         0x00000000, 0x000007fc },
10054                 { MAC_RX_MODE, TG3_FL_5705,
10055                         0x00000000, 0x000007dc },
10056                 { MAC_HASH_REG_0, 0x0000,
10057                         0x00000000, 0xffffffff },
10058                 { MAC_HASH_REG_1, 0x0000,
10059                         0x00000000, 0xffffffff },
10060                 { MAC_HASH_REG_2, 0x0000,
10061                         0x00000000, 0xffffffff },
10062                 { MAC_HASH_REG_3, 0x0000,
10063                         0x00000000, 0xffffffff },
10064
10065                 /* Receive Data and Receive BD Initiator Control Registers. */
10066                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10067                         0x00000000, 0xffffffff },
10068                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10069                         0x00000000, 0xffffffff },
10070                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10071                         0x00000000, 0x00000003 },
10072                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10073                         0x00000000, 0xffffffff },
10074                 { RCVDBDI_STD_BD+0, 0x0000,
10075                         0x00000000, 0xffffffff },
10076                 { RCVDBDI_STD_BD+4, 0x0000,
10077                         0x00000000, 0xffffffff },
10078                 { RCVDBDI_STD_BD+8, 0x0000,
10079                         0x00000000, 0xffff0002 },
10080                 { RCVDBDI_STD_BD+0xc, 0x0000,
10081                         0x00000000, 0xffffffff },
10082
10083                 /* Receive BD Initiator Control Registers. */
10084                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10085                         0x00000000, 0xffffffff },
10086                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10087                         0x00000000, 0x000003ff },
10088                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10089                         0x00000000, 0xffffffff },
10090
10091                 /* Host Coalescing Control Registers. */
10092                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10093                         0x00000000, 0x00000004 },
10094                 { HOSTCC_MODE, TG3_FL_5705,
10095                         0x00000000, 0x000000f6 },
10096                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10097                         0x00000000, 0xffffffff },
10098                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10099                         0x00000000, 0x000003ff },
10100                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10101                         0x00000000, 0xffffffff },
10102                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10103                         0x00000000, 0x000003ff },
10104                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10105                         0x00000000, 0xffffffff },
10106                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10107                         0x00000000, 0x000000ff },
10108                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10109                         0x00000000, 0xffffffff },
10110                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10111                         0x00000000, 0x000000ff },
10112                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10113                         0x00000000, 0xffffffff },
10114                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10115                         0x00000000, 0xffffffff },
10116                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10117                         0x00000000, 0xffffffff },
10118                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10119                         0x00000000, 0x000000ff },
10120                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10121                         0x00000000, 0xffffffff },
10122                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10123                         0x00000000, 0x000000ff },
10124                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10125                         0x00000000, 0xffffffff },
10126                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10127                         0x00000000, 0xffffffff },
10128                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10129                         0x00000000, 0xffffffff },
10130                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10131                         0x00000000, 0xffffffff },
10132                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10133                         0x00000000, 0xffffffff },
10134                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10135                         0xffffffff, 0x00000000 },
10136                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10137                         0xffffffff, 0x00000000 },
10138
10139                 /* Buffer Manager Control Registers. */
10140                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10141                         0x00000000, 0x007fff80 },
10142                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10143                         0x00000000, 0x007fffff },
10144                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10145                         0x00000000, 0x0000003f },
10146                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10147                         0x00000000, 0x000001ff },
10148                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10149                         0x00000000, 0x000001ff },
10150                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10151                         0xffffffff, 0x00000000 },
10152                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10153                         0xffffffff, 0x00000000 },
10154
10155                 /* Mailbox Registers */
10156                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10157                         0x00000000, 0x000001ff },
10158                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10159                         0x00000000, 0x000001ff },
10160                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10161                         0x00000000, 0x000007ff },
10162                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10163                         0x00000000, 0x000001ff },
10164
10165                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10166         };
10167
10168         is_5705 = is_5750 = 0;
10169         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10170                 is_5705 = 1;
10171                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10172                         is_5750 = 1;
10173         }
10174
10175         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10176                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10177                         continue;
10178
10179                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10180                         continue;
10181
10182                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10183                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10184                         continue;
10185
10186                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10187                         continue;
10188
10189                 offset = (u32) reg_tbl[i].offset;
10190                 read_mask = reg_tbl[i].read_mask;
10191                 write_mask = reg_tbl[i].write_mask;
10192
10193                 /* Save the original register content */
10194                 save_val = tr32(offset);
10195
10196                 /* Determine the read-only value. */
10197                 read_val = save_val & read_mask;
10198
10199                 /* Write zero to the register, then make sure the read-only bits
10200                  * are not changed and the read/write bits are all zeros.
10201                  */
10202                 tw32(offset, 0);
10203
10204                 val = tr32(offset);
10205
10206                 /* Test the read-only and read/write bits. */
10207                 if (((val & read_mask) != read_val) || (val & write_mask))
10208                         goto out;
10209
10210                 /* Write ones to all the bits defined by RdMask and WrMask, then
10211                  * make sure the read-only bits are not changed and the
10212                  * read/write bits are all ones.
10213                  */
10214                 tw32(offset, read_mask | write_mask);
10215
10216                 val = tr32(offset);
10217
10218                 /* Test the read-only bits. */
10219                 if ((val & read_mask) != read_val)
10220                         goto out;
10221
10222                 /* Test the read/write bits. */
10223                 if ((val & write_mask) != write_mask)
10224                         goto out;
10225
10226                 tw32(offset, save_val);
10227         }
10228
10229         return 0;
10230
10231 out:
10232         if (netif_msg_hw(tp))
10233                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10234                        offset);
10235         tw32(offset, save_val);
10236         return -EIO;
10237 }
10238
10239 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10240 {
10241         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10242         int i;
10243         u32 j;
10244
10245         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10246                 for (j = 0; j < len; j += 4) {
10247                         u32 val;
10248
10249                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10250                         tg3_read_mem(tp, offset + j, &val);
10251                         if (val != test_pattern[i])
10252                                 return -EIO;
10253                 }
10254         }
10255         return 0;
10256 }
10257
10258 static int tg3_test_memory(struct tg3 *tp)
10259 {
10260         static struct mem_entry {
10261                 u32 offset;
10262                 u32 len;
10263         } mem_tbl_570x[] = {
10264                 { 0x00000000, 0x00b50},
10265                 { 0x00002000, 0x1c000},
10266                 { 0xffffffff, 0x00000}
10267         }, mem_tbl_5705[] = {
10268                 { 0x00000100, 0x0000c},
10269                 { 0x00000200, 0x00008},
10270                 { 0x00004000, 0x00800},
10271                 { 0x00006000, 0x01000},
10272                 { 0x00008000, 0x02000},
10273                 { 0x00010000, 0x0e000},
10274                 { 0xffffffff, 0x00000}
10275         }, mem_tbl_5755[] = {
10276                 { 0x00000200, 0x00008},
10277                 { 0x00004000, 0x00800},
10278                 { 0x00006000, 0x00800},
10279                 { 0x00008000, 0x02000},
10280                 { 0x00010000, 0x0c000},
10281                 { 0xffffffff, 0x00000}
10282         }, mem_tbl_5906[] = {
10283                 { 0x00000200, 0x00008},
10284                 { 0x00004000, 0x00400},
10285                 { 0x00006000, 0x00400},
10286                 { 0x00008000, 0x01000},
10287                 { 0x00010000, 0x01000},
10288                 { 0xffffffff, 0x00000}
10289         };
10290         struct mem_entry *mem_tbl;
10291         int err = 0;
10292         int i;
10293
10294         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10295                 mem_tbl = mem_tbl_5755;
10296         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10297                 mem_tbl = mem_tbl_5906;
10298         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10299                 mem_tbl = mem_tbl_5705;
10300         else
10301                 mem_tbl = mem_tbl_570x;
10302
10303         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10304                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10305                     mem_tbl[i].len)) != 0)
10306                         break;
10307         }
10308
10309         return err;
10310 }
10311
10312 #define TG3_MAC_LOOPBACK        0
10313 #define TG3_PHY_LOOPBACK        1
10314
10315 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10316 {
10317         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10318         u32 desc_idx, coal_now;
10319         struct sk_buff *skb, *rx_skb;
10320         u8 *tx_data;
10321         dma_addr_t map;
10322         int num_pkts, tx_len, rx_len, i, err;
10323         struct tg3_rx_buffer_desc *desc;
10324         struct tg3_napi *tnapi, *rnapi;
10325         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10326
10327         if (tp->irq_cnt > 1) {
10328                 tnapi = &tp->napi[1];
10329                 rnapi = &tp->napi[1];
10330         } else {
10331                 tnapi = &tp->napi[0];
10332                 rnapi = &tp->napi[0];
10333         }
10334         coal_now = tnapi->coal_now | rnapi->coal_now;
10335
10336         if (loopback_mode == TG3_MAC_LOOPBACK) {
10337                 /* HW errata - mac loopback fails in some cases on 5780.
10338                  * Normal traffic and PHY loopback are not affected by
10339                  * errata.
10340                  */
10341                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10342                         return 0;
10343
10344                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10345                            MAC_MODE_PORT_INT_LPBACK;
10346                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10347                         mac_mode |= MAC_MODE_LINK_POLARITY;
10348                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10349                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10350                 else
10351                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10352                 tw32(MAC_MODE, mac_mode);
10353         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10354                 u32 val;
10355
10356                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10357                         tg3_phy_fet_toggle_apd(tp, false);
10358                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10359                 } else
10360                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10361
10362                 tg3_phy_toggle_automdix(tp, 0);
10363
10364                 tg3_writephy(tp, MII_BMCR, val);
10365                 udelay(40);
10366
10367                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10368                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10369                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10370                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10371                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10372                 } else
10373                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10374
10375                 /* reset to prevent losing 1st rx packet intermittently */
10376                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10377                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10378                         udelay(10);
10379                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10380                 }
10381                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10382                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10383                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10384                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10385                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10386                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10387                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10388                 }
10389                 tw32(MAC_MODE, mac_mode);
10390         }
10391         else
10392                 return -EINVAL;
10393
10394         err = -EIO;
10395
10396         tx_len = 1514;
10397         skb = netdev_alloc_skb(tp->dev, tx_len);
10398         if (!skb)
10399                 return -ENOMEM;
10400
10401         tx_data = skb_put(skb, tx_len);
10402         memcpy(tx_data, tp->dev->dev_addr, 6);
10403         memset(tx_data + 6, 0x0, 8);
10404
10405         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10406
10407         for (i = 14; i < tx_len; i++)
10408                 tx_data[i] = (u8) (i & 0xff);
10409
10410         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10411                 dev_kfree_skb(skb);
10412                 return -EIO;
10413         }
10414
10415         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10416                rnapi->coal_now);
10417
10418         udelay(10);
10419
10420         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10421
10422         num_pkts = 0;
10423
10424         tg3_set_txd(tnapi, tnapi->tx_prod,
10425                     skb_shinfo(skb)->dma_head, tx_len, 0, 1);
10426
10427         tnapi->tx_prod++;
10428         num_pkts++;
10429
10430         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10431         tr32_mailbox(tnapi->prodmbox);
10432
10433         udelay(10);
10434
10435         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10436         for (i = 0; i < 35; i++) {
10437                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10438                        coal_now);
10439
10440                 udelay(10);
10441
10442                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10443                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10444                 if ((tx_idx == tnapi->tx_prod) &&
10445                     (rx_idx == (rx_start_idx + num_pkts)))
10446                         break;
10447         }
10448
10449         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
10450         dev_kfree_skb(skb);
10451
10452         if (tx_idx != tnapi->tx_prod)
10453                 goto out;
10454
10455         if (rx_idx != rx_start_idx + num_pkts)
10456                 goto out;
10457
10458         desc = &rnapi->rx_rcb[rx_start_idx];
10459         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10460         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10461         if (opaque_key != RXD_OPAQUE_RING_STD)
10462                 goto out;
10463
10464         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10465             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10466                 goto out;
10467
10468         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10469         if (rx_len != tx_len)
10470                 goto out;
10471
10472         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10473
10474         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10475         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10476
10477         for (i = 14; i < tx_len; i++) {
10478                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10479                         goto out;
10480         }
10481         err = 0;
10482
10483         /* tg3_free_rings will unmap and free the rx_skb */
10484 out:
10485         return err;
10486 }
10487
10488 #define TG3_MAC_LOOPBACK_FAILED         1
10489 #define TG3_PHY_LOOPBACK_FAILED         2
10490 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10491                                          TG3_PHY_LOOPBACK_FAILED)
10492
10493 static int tg3_test_loopback(struct tg3 *tp)
10494 {
10495         int err = 0;
10496         u32 cpmuctrl = 0;
10497
10498         if (!netif_running(tp->dev))
10499                 return TG3_LOOPBACK_FAILED;
10500
10501         err = tg3_reset_hw(tp, 1);
10502         if (err)
10503                 return TG3_LOOPBACK_FAILED;
10504
10505         /* Turn off gphy autopowerdown. */
10506         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10507                 tg3_phy_toggle_apd(tp, false);
10508
10509         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10510                 int i;
10511                 u32 status;
10512
10513                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10514
10515                 /* Wait for up to 40 microseconds to acquire lock. */
10516                 for (i = 0; i < 4; i++) {
10517                         status = tr32(TG3_CPMU_MUTEX_GNT);
10518                         if (status == CPMU_MUTEX_GNT_DRIVER)
10519                                 break;
10520                         udelay(10);
10521                 }
10522
10523                 if (status != CPMU_MUTEX_GNT_DRIVER)
10524                         return TG3_LOOPBACK_FAILED;
10525
10526                 /* Turn off link-based power management. */
10527                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10528                 tw32(TG3_CPMU_CTRL,
10529                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10530                                   CPMU_CTRL_LINK_AWARE_MODE));
10531         }
10532
10533         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10534                 err |= TG3_MAC_LOOPBACK_FAILED;
10535
10536         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10537                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10538
10539                 /* Release the mutex */
10540                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10541         }
10542
10543         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10544             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10545                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10546                         err |= TG3_PHY_LOOPBACK_FAILED;
10547         }
10548
10549         /* Re-enable gphy autopowerdown. */
10550         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10551                 tg3_phy_toggle_apd(tp, true);
10552
10553         return err;
10554 }
10555
10556 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10557                           u64 *data)
10558 {
10559         struct tg3 *tp = netdev_priv(dev);
10560
10561         if (tp->link_config.phy_is_low_power)
10562                 tg3_set_power_state(tp, PCI_D0);
10563
10564         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10565
10566         if (tg3_test_nvram(tp) != 0) {
10567                 etest->flags |= ETH_TEST_FL_FAILED;
10568                 data[0] = 1;
10569         }
10570         if (tg3_test_link(tp) != 0) {
10571                 etest->flags |= ETH_TEST_FL_FAILED;
10572                 data[1] = 1;
10573         }
10574         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10575                 int err, err2 = 0, irq_sync = 0;
10576
10577                 if (netif_running(dev)) {
10578                         tg3_phy_stop(tp);
10579                         tg3_netif_stop(tp);
10580                         irq_sync = 1;
10581                 }
10582
10583                 tg3_full_lock(tp, irq_sync);
10584
10585                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10586                 err = tg3_nvram_lock(tp);
10587                 tg3_halt_cpu(tp, RX_CPU_BASE);
10588                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10589                         tg3_halt_cpu(tp, TX_CPU_BASE);
10590                 if (!err)
10591                         tg3_nvram_unlock(tp);
10592
10593                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10594                         tg3_phy_reset(tp);
10595
10596                 if (tg3_test_registers(tp) != 0) {
10597                         etest->flags |= ETH_TEST_FL_FAILED;
10598                         data[2] = 1;
10599                 }
10600                 if (tg3_test_memory(tp) != 0) {
10601                         etest->flags |= ETH_TEST_FL_FAILED;
10602                         data[3] = 1;
10603                 }
10604                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10605                         etest->flags |= ETH_TEST_FL_FAILED;
10606
10607                 tg3_full_unlock(tp);
10608
10609                 if (tg3_test_interrupt(tp) != 0) {
10610                         etest->flags |= ETH_TEST_FL_FAILED;
10611                         data[5] = 1;
10612                 }
10613
10614                 tg3_full_lock(tp, 0);
10615
10616                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10617                 if (netif_running(dev)) {
10618                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10619                         err2 = tg3_restart_hw(tp, 1);
10620                         if (!err2)
10621                                 tg3_netif_start(tp);
10622                 }
10623
10624                 tg3_full_unlock(tp);
10625
10626                 if (irq_sync && !err2)
10627                         tg3_phy_start(tp);
10628         }
10629         if (tp->link_config.phy_is_low_power)
10630                 tg3_set_power_state(tp, PCI_D3hot);
10631
10632 }
10633
10634 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10635 {
10636         struct mii_ioctl_data *data = if_mii(ifr);
10637         struct tg3 *tp = netdev_priv(dev);
10638         int err;
10639
10640         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10641                 struct phy_device *phydev;
10642                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10643                         return -EAGAIN;
10644                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10645                 return phy_mii_ioctl(phydev, data, cmd);
10646         }
10647
10648         switch(cmd) {
10649         case SIOCGMIIPHY:
10650                 data->phy_id = tp->phy_addr;
10651
10652                 /* fallthru */
10653         case SIOCGMIIREG: {
10654                 u32 mii_regval;
10655
10656                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10657                         break;                  /* We have no PHY */
10658
10659                 if (tp->link_config.phy_is_low_power)
10660                         return -EAGAIN;
10661
10662                 spin_lock_bh(&tp->lock);
10663                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10664                 spin_unlock_bh(&tp->lock);
10665
10666                 data->val_out = mii_regval;
10667
10668                 return err;
10669         }
10670
10671         case SIOCSMIIREG:
10672                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10673                         break;                  /* We have no PHY */
10674
10675                 if (tp->link_config.phy_is_low_power)
10676                         return -EAGAIN;
10677
10678                 spin_lock_bh(&tp->lock);
10679                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10680                 spin_unlock_bh(&tp->lock);
10681
10682                 return err;
10683
10684         default:
10685                 /* do nothing */
10686                 break;
10687         }
10688         return -EOPNOTSUPP;
10689 }
10690
10691 #if TG3_VLAN_TAG_USED
10692 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10693 {
10694         struct tg3 *tp = netdev_priv(dev);
10695
10696         if (!netif_running(dev)) {
10697                 tp->vlgrp = grp;
10698                 return;
10699         }
10700
10701         tg3_netif_stop(tp);
10702
10703         tg3_full_lock(tp, 0);
10704
10705         tp->vlgrp = grp;
10706
10707         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10708         __tg3_set_rx_mode(dev);
10709
10710         tg3_netif_start(tp);
10711
10712         tg3_full_unlock(tp);
10713 }
10714 #endif
10715
10716 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10717 {
10718         struct tg3 *tp = netdev_priv(dev);
10719
10720         memcpy(ec, &tp->coal, sizeof(*ec));
10721         return 0;
10722 }
10723
10724 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10725 {
10726         struct tg3 *tp = netdev_priv(dev);
10727         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10728         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10729
10730         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10731                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10732                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10733                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10734                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10735         }
10736
10737         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10738             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10739             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10740             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10741             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10742             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10743             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10744             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10745             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10746             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10747                 return -EINVAL;
10748
10749         /* No rx interrupts will be generated if both are zero */
10750         if ((ec->rx_coalesce_usecs == 0) &&
10751             (ec->rx_max_coalesced_frames == 0))
10752                 return -EINVAL;
10753
10754         /* No tx interrupts will be generated if both are zero */
10755         if ((ec->tx_coalesce_usecs == 0) &&
10756             (ec->tx_max_coalesced_frames == 0))
10757                 return -EINVAL;
10758
10759         /* Only copy relevant parameters, ignore all others. */
10760         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10761         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10762         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10763         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10764         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10765         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10766         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10767         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10768         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10769
10770         if (netif_running(dev)) {
10771                 tg3_full_lock(tp, 0);
10772                 __tg3_set_coalesce(tp, &tp->coal);
10773                 tg3_full_unlock(tp);
10774         }
10775         return 0;
10776 }
10777
10778 static const struct ethtool_ops tg3_ethtool_ops = {
10779         .get_settings           = tg3_get_settings,
10780         .set_settings           = tg3_set_settings,
10781         .get_drvinfo            = tg3_get_drvinfo,
10782         .get_regs_len           = tg3_get_regs_len,
10783         .get_regs               = tg3_get_regs,
10784         .get_wol                = tg3_get_wol,
10785         .set_wol                = tg3_set_wol,
10786         .get_msglevel           = tg3_get_msglevel,
10787         .set_msglevel           = tg3_set_msglevel,
10788         .nway_reset             = tg3_nway_reset,
10789         .get_link               = ethtool_op_get_link,
10790         .get_eeprom_len         = tg3_get_eeprom_len,
10791         .get_eeprom             = tg3_get_eeprom,
10792         .set_eeprom             = tg3_set_eeprom,
10793         .get_ringparam          = tg3_get_ringparam,
10794         .set_ringparam          = tg3_set_ringparam,
10795         .get_pauseparam         = tg3_get_pauseparam,
10796         .set_pauseparam         = tg3_set_pauseparam,
10797         .get_rx_csum            = tg3_get_rx_csum,
10798         .set_rx_csum            = tg3_set_rx_csum,
10799         .set_tx_csum            = tg3_set_tx_csum,
10800         .set_sg                 = ethtool_op_set_sg,
10801         .set_tso                = tg3_set_tso,
10802         .self_test              = tg3_self_test,
10803         .get_strings            = tg3_get_strings,
10804         .phys_id                = tg3_phys_id,
10805         .get_ethtool_stats      = tg3_get_ethtool_stats,
10806         .get_coalesce           = tg3_get_coalesce,
10807         .set_coalesce           = tg3_set_coalesce,
10808         .get_sset_count         = tg3_get_sset_count,
10809 };
10810
10811 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10812 {
10813         u32 cursize, val, magic;
10814
10815         tp->nvram_size = EEPROM_CHIP_SIZE;
10816
10817         if (tg3_nvram_read(tp, 0, &magic) != 0)
10818                 return;
10819
10820         if ((magic != TG3_EEPROM_MAGIC) &&
10821             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10822             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10823                 return;
10824
10825         /*
10826          * Size the chip by reading offsets at increasing powers of two.
10827          * When we encounter our validation signature, we know the addressing
10828          * has wrapped around, and thus have our chip size.
10829          */
10830         cursize = 0x10;
10831
10832         while (cursize < tp->nvram_size) {
10833                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10834                         return;
10835
10836                 if (val == magic)
10837                         break;
10838
10839                 cursize <<= 1;
10840         }
10841
10842         tp->nvram_size = cursize;
10843 }
10844
10845 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10846 {
10847         u32 val;
10848
10849         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10850             tg3_nvram_read(tp, 0, &val) != 0)
10851                 return;
10852
10853         /* Selfboot format */
10854         if (val != TG3_EEPROM_MAGIC) {
10855                 tg3_get_eeprom_size(tp);
10856                 return;
10857         }
10858
10859         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10860                 if (val != 0) {
10861                         /* This is confusing.  We want to operate on the
10862                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10863                          * call will read from NVRAM and byteswap the data
10864                          * according to the byteswapping settings for all
10865                          * other register accesses.  This ensures the data we
10866                          * want will always reside in the lower 16-bits.
10867                          * However, the data in NVRAM is in LE format, which
10868                          * means the data from the NVRAM read will always be
10869                          * opposite the endianness of the CPU.  The 16-bit
10870                          * byteswap then brings the data to CPU endianness.
10871                          */
10872                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10873                         return;
10874                 }
10875         }
10876         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10877 }
10878
10879 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10880 {
10881         u32 nvcfg1;
10882
10883         nvcfg1 = tr32(NVRAM_CFG1);
10884         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10885                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10886         } else {
10887                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10888                 tw32(NVRAM_CFG1, nvcfg1);
10889         }
10890
10891         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10892             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10893                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10894                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10895                         tp->nvram_jedecnum = JEDEC_ATMEL;
10896                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10897                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10898                         break;
10899                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10900                         tp->nvram_jedecnum = JEDEC_ATMEL;
10901                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10902                         break;
10903                 case FLASH_VENDOR_ATMEL_EEPROM:
10904                         tp->nvram_jedecnum = JEDEC_ATMEL;
10905                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10906                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10907                         break;
10908                 case FLASH_VENDOR_ST:
10909                         tp->nvram_jedecnum = JEDEC_ST;
10910                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10911                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10912                         break;
10913                 case FLASH_VENDOR_SAIFUN:
10914                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10915                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10916                         break;
10917                 case FLASH_VENDOR_SST_SMALL:
10918                 case FLASH_VENDOR_SST_LARGE:
10919                         tp->nvram_jedecnum = JEDEC_SST;
10920                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10921                         break;
10922                 }
10923         } else {
10924                 tp->nvram_jedecnum = JEDEC_ATMEL;
10925                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10926                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10927         }
10928 }
10929
10930 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10931 {
10932         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10933         case FLASH_5752PAGE_SIZE_256:
10934                 tp->nvram_pagesize = 256;
10935                 break;
10936         case FLASH_5752PAGE_SIZE_512:
10937                 tp->nvram_pagesize = 512;
10938                 break;
10939         case FLASH_5752PAGE_SIZE_1K:
10940                 tp->nvram_pagesize = 1024;
10941                 break;
10942         case FLASH_5752PAGE_SIZE_2K:
10943                 tp->nvram_pagesize = 2048;
10944                 break;
10945         case FLASH_5752PAGE_SIZE_4K:
10946                 tp->nvram_pagesize = 4096;
10947                 break;
10948         case FLASH_5752PAGE_SIZE_264:
10949                 tp->nvram_pagesize = 264;
10950                 break;
10951         case FLASH_5752PAGE_SIZE_528:
10952                 tp->nvram_pagesize = 528;
10953                 break;
10954         }
10955 }
10956
10957 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10958 {
10959         u32 nvcfg1;
10960
10961         nvcfg1 = tr32(NVRAM_CFG1);
10962
10963         /* NVRAM protection for TPM */
10964         if (nvcfg1 & (1 << 27))
10965                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10966
10967         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10968         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10969         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10970                 tp->nvram_jedecnum = JEDEC_ATMEL;
10971                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10972                 break;
10973         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10974                 tp->nvram_jedecnum = JEDEC_ATMEL;
10975                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10976                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10977                 break;
10978         case FLASH_5752VENDOR_ST_M45PE10:
10979         case FLASH_5752VENDOR_ST_M45PE20:
10980         case FLASH_5752VENDOR_ST_M45PE40:
10981                 tp->nvram_jedecnum = JEDEC_ST;
10982                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10983                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10984                 break;
10985         }
10986
10987         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10988                 tg3_nvram_get_pagesize(tp, nvcfg1);
10989         } else {
10990                 /* For eeprom, set pagesize to maximum eeprom size */
10991                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10992
10993                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10994                 tw32(NVRAM_CFG1, nvcfg1);
10995         }
10996 }
10997
10998 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10999 {
11000         u32 nvcfg1, protect = 0;
11001
11002         nvcfg1 = tr32(NVRAM_CFG1);
11003
11004         /* NVRAM protection for TPM */
11005         if (nvcfg1 & (1 << 27)) {
11006                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11007                 protect = 1;
11008         }
11009
11010         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11011         switch (nvcfg1) {
11012         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11013         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11014         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11015         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11016                 tp->nvram_jedecnum = JEDEC_ATMEL;
11017                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11018                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11019                 tp->nvram_pagesize = 264;
11020                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11021                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11022                         tp->nvram_size = (protect ? 0x3e200 :
11023                                           TG3_NVRAM_SIZE_512KB);
11024                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11025                         tp->nvram_size = (protect ? 0x1f200 :
11026                                           TG3_NVRAM_SIZE_256KB);
11027                 else
11028                         tp->nvram_size = (protect ? 0x1f200 :
11029                                           TG3_NVRAM_SIZE_128KB);
11030                 break;
11031         case FLASH_5752VENDOR_ST_M45PE10:
11032         case FLASH_5752VENDOR_ST_M45PE20:
11033         case FLASH_5752VENDOR_ST_M45PE40:
11034                 tp->nvram_jedecnum = JEDEC_ST;
11035                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11036                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11037                 tp->nvram_pagesize = 256;
11038                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11039                         tp->nvram_size = (protect ?
11040                                           TG3_NVRAM_SIZE_64KB :
11041                                           TG3_NVRAM_SIZE_128KB);
11042                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11043                         tp->nvram_size = (protect ?
11044                                           TG3_NVRAM_SIZE_64KB :
11045                                           TG3_NVRAM_SIZE_256KB);
11046                 else
11047                         tp->nvram_size = (protect ?
11048                                           TG3_NVRAM_SIZE_128KB :
11049                                           TG3_NVRAM_SIZE_512KB);
11050                 break;
11051         }
11052 }
11053
11054 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11055 {
11056         u32 nvcfg1;
11057
11058         nvcfg1 = tr32(NVRAM_CFG1);
11059
11060         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11061         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11062         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11063         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11064         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11065                 tp->nvram_jedecnum = JEDEC_ATMEL;
11066                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11067                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11068
11069                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11070                 tw32(NVRAM_CFG1, nvcfg1);
11071                 break;
11072         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11073         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11074         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11075         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11076                 tp->nvram_jedecnum = JEDEC_ATMEL;
11077                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11078                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11079                 tp->nvram_pagesize = 264;
11080                 break;
11081         case FLASH_5752VENDOR_ST_M45PE10:
11082         case FLASH_5752VENDOR_ST_M45PE20:
11083         case FLASH_5752VENDOR_ST_M45PE40:
11084                 tp->nvram_jedecnum = JEDEC_ST;
11085                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11086                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11087                 tp->nvram_pagesize = 256;
11088                 break;
11089         }
11090 }
11091
11092 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11093 {
11094         u32 nvcfg1, protect = 0;
11095
11096         nvcfg1 = tr32(NVRAM_CFG1);
11097
11098         /* NVRAM protection for TPM */
11099         if (nvcfg1 & (1 << 27)) {
11100                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11101                 protect = 1;
11102         }
11103
11104         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11105         switch (nvcfg1) {
11106         case FLASH_5761VENDOR_ATMEL_ADB021D:
11107         case FLASH_5761VENDOR_ATMEL_ADB041D:
11108         case FLASH_5761VENDOR_ATMEL_ADB081D:
11109         case FLASH_5761VENDOR_ATMEL_ADB161D:
11110         case FLASH_5761VENDOR_ATMEL_MDB021D:
11111         case FLASH_5761VENDOR_ATMEL_MDB041D:
11112         case FLASH_5761VENDOR_ATMEL_MDB081D:
11113         case FLASH_5761VENDOR_ATMEL_MDB161D:
11114                 tp->nvram_jedecnum = JEDEC_ATMEL;
11115                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11116                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11117                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11118                 tp->nvram_pagesize = 256;
11119                 break;
11120         case FLASH_5761VENDOR_ST_A_M45PE20:
11121         case FLASH_5761VENDOR_ST_A_M45PE40:
11122         case FLASH_5761VENDOR_ST_A_M45PE80:
11123         case FLASH_5761VENDOR_ST_A_M45PE16:
11124         case FLASH_5761VENDOR_ST_M_M45PE20:
11125         case FLASH_5761VENDOR_ST_M_M45PE40:
11126         case FLASH_5761VENDOR_ST_M_M45PE80:
11127         case FLASH_5761VENDOR_ST_M_M45PE16:
11128                 tp->nvram_jedecnum = JEDEC_ST;
11129                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11130                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11131                 tp->nvram_pagesize = 256;
11132                 break;
11133         }
11134
11135         if (protect) {
11136                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11137         } else {
11138                 switch (nvcfg1) {
11139                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11140                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11141                 case FLASH_5761VENDOR_ST_A_M45PE16:
11142                 case FLASH_5761VENDOR_ST_M_M45PE16:
11143                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11144                         break;
11145                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11146                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11147                 case FLASH_5761VENDOR_ST_A_M45PE80:
11148                 case FLASH_5761VENDOR_ST_M_M45PE80:
11149                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11150                         break;
11151                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11152                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11153                 case FLASH_5761VENDOR_ST_A_M45PE40:
11154                 case FLASH_5761VENDOR_ST_M_M45PE40:
11155                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11156                         break;
11157                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11158                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11159                 case FLASH_5761VENDOR_ST_A_M45PE20:
11160                 case FLASH_5761VENDOR_ST_M_M45PE20:
11161                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11162                         break;
11163                 }
11164         }
11165 }
11166
11167 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11168 {
11169         tp->nvram_jedecnum = JEDEC_ATMEL;
11170         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11171         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11172 }
11173
11174 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11175 {
11176         u32 nvcfg1;
11177
11178         nvcfg1 = tr32(NVRAM_CFG1);
11179
11180         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11181         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11182         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11183                 tp->nvram_jedecnum = JEDEC_ATMEL;
11184                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11185                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11186
11187                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11188                 tw32(NVRAM_CFG1, nvcfg1);
11189                 return;
11190         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11191         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11192         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11193         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11194         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11195         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11196         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11197                 tp->nvram_jedecnum = JEDEC_ATMEL;
11198                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11199                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11200
11201                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11202                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11203                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11204                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11205                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11206                         break;
11207                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11208                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11209                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11210                         break;
11211                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11212                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11213                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11214                         break;
11215                 }
11216                 break;
11217         case FLASH_5752VENDOR_ST_M45PE10:
11218         case FLASH_5752VENDOR_ST_M45PE20:
11219         case FLASH_5752VENDOR_ST_M45PE40:
11220                 tp->nvram_jedecnum = JEDEC_ST;
11221                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11222                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11223
11224                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11225                 case FLASH_5752VENDOR_ST_M45PE10:
11226                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11227                         break;
11228                 case FLASH_5752VENDOR_ST_M45PE20:
11229                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11230                         break;
11231                 case FLASH_5752VENDOR_ST_M45PE40:
11232                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11233                         break;
11234                 }
11235                 break;
11236         default:
11237                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11238                 return;
11239         }
11240
11241         tg3_nvram_get_pagesize(tp, nvcfg1);
11242         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11243                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11244 }
11245
11246
11247 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11248 {
11249         u32 nvcfg1;
11250
11251         nvcfg1 = tr32(NVRAM_CFG1);
11252
11253         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11254         case FLASH_5717VENDOR_ATMEL_EEPROM:
11255         case FLASH_5717VENDOR_MICRO_EEPROM:
11256                 tp->nvram_jedecnum = JEDEC_ATMEL;
11257                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11258                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11259
11260                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11261                 tw32(NVRAM_CFG1, nvcfg1);
11262                 return;
11263         case FLASH_5717VENDOR_ATMEL_MDB011D:
11264         case FLASH_5717VENDOR_ATMEL_ADB011B:
11265         case FLASH_5717VENDOR_ATMEL_ADB011D:
11266         case FLASH_5717VENDOR_ATMEL_MDB021D:
11267         case FLASH_5717VENDOR_ATMEL_ADB021B:
11268         case FLASH_5717VENDOR_ATMEL_ADB021D:
11269         case FLASH_5717VENDOR_ATMEL_45USPT:
11270                 tp->nvram_jedecnum = JEDEC_ATMEL;
11271                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11272                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11273
11274                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11275                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11276                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11277                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11278                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11279                         break;
11280                 default:
11281                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11282                         break;
11283                 }
11284                 break;
11285         case FLASH_5717VENDOR_ST_M_M25PE10:
11286         case FLASH_5717VENDOR_ST_A_M25PE10:
11287         case FLASH_5717VENDOR_ST_M_M45PE10:
11288         case FLASH_5717VENDOR_ST_A_M45PE10:
11289         case FLASH_5717VENDOR_ST_M_M25PE20:
11290         case FLASH_5717VENDOR_ST_A_M25PE20:
11291         case FLASH_5717VENDOR_ST_M_M45PE20:
11292         case FLASH_5717VENDOR_ST_A_M45PE20:
11293         case FLASH_5717VENDOR_ST_25USPT:
11294         case FLASH_5717VENDOR_ST_45USPT:
11295                 tp->nvram_jedecnum = JEDEC_ST;
11296                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11297                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11298
11299                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11300                 case FLASH_5717VENDOR_ST_M_M25PE20:
11301                 case FLASH_5717VENDOR_ST_A_M25PE20:
11302                 case FLASH_5717VENDOR_ST_M_M45PE20:
11303                 case FLASH_5717VENDOR_ST_A_M45PE20:
11304                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11305                         break;
11306                 default:
11307                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11308                         break;
11309                 }
11310                 break;
11311         default:
11312                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11313                 return;
11314         }
11315
11316         tg3_nvram_get_pagesize(tp, nvcfg1);
11317         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11318                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11319 }
11320
11321 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11322 static void __devinit tg3_nvram_init(struct tg3 *tp)
11323 {
11324         tw32_f(GRC_EEPROM_ADDR,
11325              (EEPROM_ADDR_FSM_RESET |
11326               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11327                EEPROM_ADDR_CLKPERD_SHIFT)));
11328
11329         msleep(1);
11330
11331         /* Enable seeprom accesses. */
11332         tw32_f(GRC_LOCAL_CTRL,
11333              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11334         udelay(100);
11335
11336         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11337             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11338                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11339
11340                 if (tg3_nvram_lock(tp)) {
11341                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11342                                "tg3_nvram_init failed.\n", tp->dev->name);
11343                         return;
11344                 }
11345                 tg3_enable_nvram_access(tp);
11346
11347                 tp->nvram_size = 0;
11348
11349                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11350                         tg3_get_5752_nvram_info(tp);
11351                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11352                         tg3_get_5755_nvram_info(tp);
11353                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11354                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11355                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11356                         tg3_get_5787_nvram_info(tp);
11357                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11358                         tg3_get_5761_nvram_info(tp);
11359                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11360                         tg3_get_5906_nvram_info(tp);
11361                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11362                         tg3_get_57780_nvram_info(tp);
11363                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11364                         tg3_get_5717_nvram_info(tp);
11365                 else
11366                         tg3_get_nvram_info(tp);
11367
11368                 if (tp->nvram_size == 0)
11369                         tg3_get_nvram_size(tp);
11370
11371                 tg3_disable_nvram_access(tp);
11372                 tg3_nvram_unlock(tp);
11373
11374         } else {
11375                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11376
11377                 tg3_get_eeprom_size(tp);
11378         }
11379 }
11380
11381 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11382                                     u32 offset, u32 len, u8 *buf)
11383 {
11384         int i, j, rc = 0;
11385         u32 val;
11386
11387         for (i = 0; i < len; i += 4) {
11388                 u32 addr;
11389                 __be32 data;
11390
11391                 addr = offset + i;
11392
11393                 memcpy(&data, buf + i, 4);
11394
11395                 /*
11396                  * The SEEPROM interface expects the data to always be opposite
11397                  * the native endian format.  We accomplish this by reversing
11398                  * all the operations that would have been performed on the
11399                  * data from a call to tg3_nvram_read_be32().
11400                  */
11401                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11402
11403                 val = tr32(GRC_EEPROM_ADDR);
11404                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11405
11406                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11407                         EEPROM_ADDR_READ);
11408                 tw32(GRC_EEPROM_ADDR, val |
11409                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11410                         (addr & EEPROM_ADDR_ADDR_MASK) |
11411                         EEPROM_ADDR_START |
11412                         EEPROM_ADDR_WRITE);
11413
11414                 for (j = 0; j < 1000; j++) {
11415                         val = tr32(GRC_EEPROM_ADDR);
11416
11417                         if (val & EEPROM_ADDR_COMPLETE)
11418                                 break;
11419                         msleep(1);
11420                 }
11421                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11422                         rc = -EBUSY;
11423                         break;
11424                 }
11425         }
11426
11427         return rc;
11428 }
11429
11430 /* offset and length are dword aligned */
11431 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11432                 u8 *buf)
11433 {
11434         int ret = 0;
11435         u32 pagesize = tp->nvram_pagesize;
11436         u32 pagemask = pagesize - 1;
11437         u32 nvram_cmd;
11438         u8 *tmp;
11439
11440         tmp = kmalloc(pagesize, GFP_KERNEL);
11441         if (tmp == NULL)
11442                 return -ENOMEM;
11443
11444         while (len) {
11445                 int j;
11446                 u32 phy_addr, page_off, size;
11447
11448                 phy_addr = offset & ~pagemask;
11449
11450                 for (j = 0; j < pagesize; j += 4) {
11451                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11452                                                   (__be32 *) (tmp + j));
11453                         if (ret)
11454                                 break;
11455                 }
11456                 if (ret)
11457                         break;
11458
11459                 page_off = offset & pagemask;
11460                 size = pagesize;
11461                 if (len < size)
11462                         size = len;
11463
11464                 len -= size;
11465
11466                 memcpy(tmp + page_off, buf, size);
11467
11468                 offset = offset + (pagesize - page_off);
11469
11470                 tg3_enable_nvram_access(tp);
11471
11472                 /*
11473                  * Before we can erase the flash page, we need
11474                  * to issue a special "write enable" command.
11475                  */
11476                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11477
11478                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11479                         break;
11480
11481                 /* Erase the target page */
11482                 tw32(NVRAM_ADDR, phy_addr);
11483
11484                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11485                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11486
11487                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11488                         break;
11489
11490                 /* Issue another write enable to start the write. */
11491                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11492
11493                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11494                         break;
11495
11496                 for (j = 0; j < pagesize; j += 4) {
11497                         __be32 data;
11498
11499                         data = *((__be32 *) (tmp + j));
11500
11501                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11502
11503                         tw32(NVRAM_ADDR, phy_addr + j);
11504
11505                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11506                                 NVRAM_CMD_WR;
11507
11508                         if (j == 0)
11509                                 nvram_cmd |= NVRAM_CMD_FIRST;
11510                         else if (j == (pagesize - 4))
11511                                 nvram_cmd |= NVRAM_CMD_LAST;
11512
11513                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11514                                 break;
11515                 }
11516                 if (ret)
11517                         break;
11518         }
11519
11520         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11521         tg3_nvram_exec_cmd(tp, nvram_cmd);
11522
11523         kfree(tmp);
11524
11525         return ret;
11526 }
11527
11528 /* offset and length are dword aligned */
11529 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11530                 u8 *buf)
11531 {
11532         int i, ret = 0;
11533
11534         for (i = 0; i < len; i += 4, offset += 4) {
11535                 u32 page_off, phy_addr, nvram_cmd;
11536                 __be32 data;
11537
11538                 memcpy(&data, buf + i, 4);
11539                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11540
11541                 page_off = offset % tp->nvram_pagesize;
11542
11543                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11544
11545                 tw32(NVRAM_ADDR, phy_addr);
11546
11547                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11548
11549                 if ((page_off == 0) || (i == 0))
11550                         nvram_cmd |= NVRAM_CMD_FIRST;
11551                 if (page_off == (tp->nvram_pagesize - 4))
11552                         nvram_cmd |= NVRAM_CMD_LAST;
11553
11554                 if (i == (len - 4))
11555                         nvram_cmd |= NVRAM_CMD_LAST;
11556
11557                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11558                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11559                     (tp->nvram_jedecnum == JEDEC_ST) &&
11560                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11561
11562                         if ((ret = tg3_nvram_exec_cmd(tp,
11563                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11564                                 NVRAM_CMD_DONE)))
11565
11566                                 break;
11567                 }
11568                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11569                         /* We always do complete word writes to eeprom. */
11570                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11571                 }
11572
11573                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11574                         break;
11575         }
11576         return ret;
11577 }
11578
11579 /* offset and length are dword aligned */
11580 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11581 {
11582         int ret;
11583
11584         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11585                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11586                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11587                 udelay(40);
11588         }
11589
11590         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11591                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11592         }
11593         else {
11594                 u32 grc_mode;
11595
11596                 ret = tg3_nvram_lock(tp);
11597                 if (ret)
11598                         return ret;
11599
11600                 tg3_enable_nvram_access(tp);
11601                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11602                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11603                         tw32(NVRAM_WRITE1, 0x406);
11604
11605                 grc_mode = tr32(GRC_MODE);
11606                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11607
11608                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11609                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11610
11611                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11612                                 buf);
11613                 }
11614                 else {
11615                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11616                                 buf);
11617                 }
11618
11619                 grc_mode = tr32(GRC_MODE);
11620                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11621
11622                 tg3_disable_nvram_access(tp);
11623                 tg3_nvram_unlock(tp);
11624         }
11625
11626         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11627                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11628                 udelay(40);
11629         }
11630
11631         return ret;
11632 }
11633
11634 struct subsys_tbl_ent {
11635         u16 subsys_vendor, subsys_devid;
11636         u32 phy_id;
11637 };
11638
11639 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11640         /* Broadcom boards. */
11641         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11642         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11643         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11644         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11645         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11646         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11647         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11648         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11649         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11650         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11651         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11652
11653         /* 3com boards. */
11654         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11655         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11656         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11657         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11658         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11659
11660         /* DELL boards. */
11661         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11662         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11663         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11664         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11665
11666         /* Compaq boards. */
11667         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11668         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11669         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11670         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11671         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11672
11673         /* IBM boards. */
11674         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11675 };
11676
11677 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11678 {
11679         int i;
11680
11681         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11682                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11683                      tp->pdev->subsystem_vendor) &&
11684                     (subsys_id_to_phy_id[i].subsys_devid ==
11685                      tp->pdev->subsystem_device))
11686                         return &subsys_id_to_phy_id[i];
11687         }
11688         return NULL;
11689 }
11690
11691 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11692 {
11693         u32 val;
11694         u16 pmcsr;
11695
11696         /* On some early chips the SRAM cannot be accessed in D3hot state,
11697          * so need make sure we're in D0.
11698          */
11699         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11700         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11701         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11702         msleep(1);
11703
11704         /* Make sure register accesses (indirect or otherwise)
11705          * will function correctly.
11706          */
11707         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11708                                tp->misc_host_ctrl);
11709
11710         /* The memory arbiter has to be enabled in order for SRAM accesses
11711          * to succeed.  Normally on powerup the tg3 chip firmware will make
11712          * sure it is enabled, but other entities such as system netboot
11713          * code might disable it.
11714          */
11715         val = tr32(MEMARB_MODE);
11716         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11717
11718         tp->phy_id = PHY_ID_INVALID;
11719         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11720
11721         /* Assume an onboard device and WOL capable by default.  */
11722         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11723
11724         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11725                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11726                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11727                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11728                 }
11729                 val = tr32(VCPU_CFGSHDW);
11730                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11731                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11732                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11733                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11734                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11735                 goto done;
11736         }
11737
11738         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11739         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11740                 u32 nic_cfg, led_cfg;
11741                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11742                 int eeprom_phy_serdes = 0;
11743
11744                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11745                 tp->nic_sram_data_cfg = nic_cfg;
11746
11747                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11748                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11749                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11750                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11751                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11752                     (ver > 0) && (ver < 0x100))
11753                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11754
11755                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11756                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11757
11758                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11759                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11760                         eeprom_phy_serdes = 1;
11761
11762                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11763                 if (nic_phy_id != 0) {
11764                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11765                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11766
11767                         eeprom_phy_id  = (id1 >> 16) << 10;
11768                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11769                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11770                 } else
11771                         eeprom_phy_id = 0;
11772
11773                 tp->phy_id = eeprom_phy_id;
11774                 if (eeprom_phy_serdes) {
11775                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11776                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11777                         else
11778                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11779                 }
11780
11781                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11782                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11783                                     SHASTA_EXT_LED_MODE_MASK);
11784                 else
11785                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11786
11787                 switch (led_cfg) {
11788                 default:
11789                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11790                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11791                         break;
11792
11793                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11794                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11795                         break;
11796
11797                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11798                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11799
11800                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11801                          * read on some older 5700/5701 bootcode.
11802                          */
11803                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11804                             ASIC_REV_5700 ||
11805                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11806                             ASIC_REV_5701)
11807                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11808
11809                         break;
11810
11811                 case SHASTA_EXT_LED_SHARED:
11812                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11813                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11814                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11815                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11816                                                  LED_CTRL_MODE_PHY_2);
11817                         break;
11818
11819                 case SHASTA_EXT_LED_MAC:
11820                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11821                         break;
11822
11823                 case SHASTA_EXT_LED_COMBO:
11824                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11825                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11826                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11827                                                  LED_CTRL_MODE_PHY_2);
11828                         break;
11829
11830                 }
11831
11832                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11833                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11834                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11835                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11836
11837                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11838                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11839
11840                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11841                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11842                         if ((tp->pdev->subsystem_vendor ==
11843                              PCI_VENDOR_ID_ARIMA) &&
11844                             (tp->pdev->subsystem_device == 0x205a ||
11845                              tp->pdev->subsystem_device == 0x2063))
11846                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11847                 } else {
11848                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11849                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11850                 }
11851
11852                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11853                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11854                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11855                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11856                 }
11857
11858                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11859                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11860                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11861
11862                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11863                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11864                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11865
11866                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11867                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11868                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11869
11870                 if (cfg2 & (1 << 17))
11871                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11872
11873                 /* serdes signal pre-emphasis in register 0x590 set by */
11874                 /* bootcode if bit 18 is set */
11875                 if (cfg2 & (1 << 18))
11876                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11877
11878                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11879                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11880                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11881                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11882
11883                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11884                         u32 cfg3;
11885
11886                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11887                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11888                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11889                 }
11890
11891                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11892                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11893                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11894                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11895                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11896                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11897         }
11898 done:
11899         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11900         device_set_wakeup_enable(&tp->pdev->dev,
11901                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11902 }
11903
11904 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11905 {
11906         int i;
11907         u32 val;
11908
11909         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11910         tw32(OTP_CTRL, cmd);
11911
11912         /* Wait for up to 1 ms for command to execute. */
11913         for (i = 0; i < 100; i++) {
11914                 val = tr32(OTP_STATUS);
11915                 if (val & OTP_STATUS_CMD_DONE)
11916                         break;
11917                 udelay(10);
11918         }
11919
11920         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11921 }
11922
11923 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11924  * configuration is a 32-bit value that straddles the alignment boundary.
11925  * We do two 32-bit reads and then shift and merge the results.
11926  */
11927 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11928 {
11929         u32 bhalf_otp, thalf_otp;
11930
11931         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11932
11933         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11934                 return 0;
11935
11936         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11937
11938         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11939                 return 0;
11940
11941         thalf_otp = tr32(OTP_READ_DATA);
11942
11943         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11944
11945         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11946                 return 0;
11947
11948         bhalf_otp = tr32(OTP_READ_DATA);
11949
11950         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11951 }
11952
11953 static int __devinit tg3_phy_probe(struct tg3 *tp)
11954 {
11955         u32 hw_phy_id_1, hw_phy_id_2;
11956         u32 hw_phy_id, hw_phy_id_masked;
11957         int err;
11958
11959         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11960                 return tg3_phy_init(tp);
11961
11962         /* Reading the PHY ID register can conflict with ASF
11963          * firmware access to the PHY hardware.
11964          */
11965         err = 0;
11966         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11967             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11968                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11969         } else {
11970                 /* Now read the physical PHY_ID from the chip and verify
11971                  * that it is sane.  If it doesn't look good, we fall back
11972                  * to either the hard-coded table based PHY_ID and failing
11973                  * that the value found in the eeprom area.
11974                  */
11975                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11976                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11977
11978                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11979                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11980                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11981
11982                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11983         }
11984
11985         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11986                 tp->phy_id = hw_phy_id;
11987                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11988                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11989                 else
11990                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11991         } else {
11992                 if (tp->phy_id != PHY_ID_INVALID) {
11993                         /* Do nothing, phy ID already set up in
11994                          * tg3_get_eeprom_hw_cfg().
11995                          */
11996                 } else {
11997                         struct subsys_tbl_ent *p;
11998
11999                         /* No eeprom signature?  Try the hardcoded
12000                          * subsys device table.
12001                          */
12002                         p = lookup_by_subsys(tp);
12003                         if (!p)
12004                                 return -ENODEV;
12005
12006                         tp->phy_id = p->phy_id;
12007                         if (!tp->phy_id ||
12008                             tp->phy_id == PHY_ID_BCM8002)
12009                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12010                 }
12011         }
12012
12013         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12014             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12015             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12016                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12017
12018                 tg3_readphy(tp, MII_BMSR, &bmsr);
12019                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12020                     (bmsr & BMSR_LSTATUS))
12021                         goto skip_phy_reset;
12022
12023                 err = tg3_phy_reset(tp);
12024                 if (err)
12025                         return err;
12026
12027                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12028                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12029                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12030                 tg3_ctrl = 0;
12031                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12032                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12033                                     MII_TG3_CTRL_ADV_1000_FULL);
12034                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12035                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12036                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12037                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12038                 }
12039
12040                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12041                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12042                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12043                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12044                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12045
12046                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12047                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12048
12049                         tg3_writephy(tp, MII_BMCR,
12050                                      BMCR_ANENABLE | BMCR_ANRESTART);
12051                 }
12052                 tg3_phy_set_wirespeed(tp);
12053
12054                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12055                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12056                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12057         }
12058
12059 skip_phy_reset:
12060         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12061                 err = tg3_init_5401phy_dsp(tp);
12062                 if (err)
12063                         return err;
12064         }
12065
12066         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12067                 err = tg3_init_5401phy_dsp(tp);
12068         }
12069
12070         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12071                 tp->link_config.advertising =
12072                         (ADVERTISED_1000baseT_Half |
12073                          ADVERTISED_1000baseT_Full |
12074                          ADVERTISED_Autoneg |
12075                          ADVERTISED_FIBRE);
12076         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12077                 tp->link_config.advertising &=
12078                         ~(ADVERTISED_1000baseT_Half |
12079                           ADVERTISED_1000baseT_Full);
12080
12081         return err;
12082 }
12083
12084 static void __devinit tg3_read_partno(struct tg3 *tp)
12085 {
12086         unsigned char vpd_data[256];   /* in little-endian format */
12087         unsigned int i;
12088         u32 magic;
12089
12090         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12091             tg3_nvram_read(tp, 0x0, &magic))
12092                 goto out_not_found;
12093
12094         if (magic == TG3_EEPROM_MAGIC) {
12095                 for (i = 0; i < 256; i += 4) {
12096                         u32 tmp;
12097
12098                         /* The data is in little-endian format in NVRAM.
12099                          * Use the big-endian read routines to preserve
12100                          * the byte order as it exists in NVRAM.
12101                          */
12102                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12103                                 goto out_not_found;
12104
12105                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12106                 }
12107         } else {
12108                 int vpd_cap;
12109
12110                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12111                 for (i = 0; i < 256; i += 4) {
12112                         u32 tmp, j = 0;
12113                         __le32 v;
12114                         u16 tmp16;
12115
12116                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12117                                               i);
12118                         while (j++ < 100) {
12119                                 pci_read_config_word(tp->pdev, vpd_cap +
12120                                                      PCI_VPD_ADDR, &tmp16);
12121                                 if (tmp16 & 0x8000)
12122                                         break;
12123                                 msleep(1);
12124                         }
12125                         if (!(tmp16 & 0x8000))
12126                                 goto out_not_found;
12127
12128                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12129                                               &tmp);
12130                         v = cpu_to_le32(tmp);
12131                         memcpy(&vpd_data[i], &v, sizeof(v));
12132                 }
12133         }
12134
12135         /* Now parse and find the part number. */
12136         for (i = 0; i < 254; ) {
12137                 unsigned char val = vpd_data[i];
12138                 unsigned int block_end;
12139
12140                 if (val == 0x82 || val == 0x91) {
12141                         i = (i + 3 +
12142                              (vpd_data[i + 1] +
12143                               (vpd_data[i + 2] << 8)));
12144                         continue;
12145                 }
12146
12147                 if (val != 0x90)
12148                         goto out_not_found;
12149
12150                 block_end = (i + 3 +
12151                              (vpd_data[i + 1] +
12152                               (vpd_data[i + 2] << 8)));
12153                 i += 3;
12154
12155                 if (block_end > 256)
12156                         goto out_not_found;
12157
12158                 while (i < (block_end - 2)) {
12159                         if (vpd_data[i + 0] == 'P' &&
12160                             vpd_data[i + 1] == 'N') {
12161                                 int partno_len = vpd_data[i + 2];
12162
12163                                 i += 3;
12164                                 if (partno_len > 24 || (partno_len + i) > 256)
12165                                         goto out_not_found;
12166
12167                                 memcpy(tp->board_part_number,
12168                                        &vpd_data[i], partno_len);
12169
12170                                 /* Success. */
12171                                 return;
12172                         }
12173                         i += 3 + vpd_data[i + 2];
12174                 }
12175
12176                 /* Part number not found. */
12177                 goto out_not_found;
12178         }
12179
12180 out_not_found:
12181         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12182                 strcpy(tp->board_part_number, "BCM95906");
12183         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12184                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12185                 strcpy(tp->board_part_number, "BCM57780");
12186         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12187                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12188                 strcpy(tp->board_part_number, "BCM57760");
12189         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12190                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12191                 strcpy(tp->board_part_number, "BCM57790");
12192         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12193                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12194                 strcpy(tp->board_part_number, "BCM57788");
12195         else
12196                 strcpy(tp->board_part_number, "none");
12197 }
12198
12199 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12200 {
12201         u32 val;
12202
12203         if (tg3_nvram_read(tp, offset, &val) ||
12204             (val & 0xfc000000) != 0x0c000000 ||
12205             tg3_nvram_read(tp, offset + 4, &val) ||
12206             val != 0)
12207                 return 0;
12208
12209         return 1;
12210 }
12211
12212 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12213 {
12214         u32 val, offset, start, ver_offset;
12215         int i;
12216         bool newver = false;
12217
12218         if (tg3_nvram_read(tp, 0xc, &offset) ||
12219             tg3_nvram_read(tp, 0x4, &start))
12220                 return;
12221
12222         offset = tg3_nvram_logical_addr(tp, offset);
12223
12224         if (tg3_nvram_read(tp, offset, &val))
12225                 return;
12226
12227         if ((val & 0xfc000000) == 0x0c000000) {
12228                 if (tg3_nvram_read(tp, offset + 4, &val))
12229                         return;
12230
12231                 if (val == 0)
12232                         newver = true;
12233         }
12234
12235         if (newver) {
12236                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12237                         return;
12238
12239                 offset = offset + ver_offset - start;
12240                 for (i = 0; i < 16; i += 4) {
12241                         __be32 v;
12242                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12243                                 return;
12244
12245                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12246                 }
12247         } else {
12248                 u32 major, minor;
12249
12250                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12251                         return;
12252
12253                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12254                         TG3_NVM_BCVER_MAJSFT;
12255                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12256                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12257         }
12258 }
12259
12260 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12261 {
12262         u32 val, major, minor;
12263
12264         /* Use native endian representation */
12265         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12266                 return;
12267
12268         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12269                 TG3_NVM_HWSB_CFG1_MAJSFT;
12270         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12271                 TG3_NVM_HWSB_CFG1_MINSFT;
12272
12273         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12274 }
12275
12276 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12277 {
12278         u32 offset, major, minor, build;
12279
12280         tp->fw_ver[0] = 's';
12281         tp->fw_ver[1] = 'b';
12282         tp->fw_ver[2] = '\0';
12283
12284         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12285                 return;
12286
12287         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12288         case TG3_EEPROM_SB_REVISION_0:
12289                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12290                 break;
12291         case TG3_EEPROM_SB_REVISION_2:
12292                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12293                 break;
12294         case TG3_EEPROM_SB_REVISION_3:
12295                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12296                 break;
12297         default:
12298                 return;
12299         }
12300
12301         if (tg3_nvram_read(tp, offset, &val))
12302                 return;
12303
12304         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12305                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12306         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12307                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12308         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12309
12310         if (minor > 99 || build > 26)
12311                 return;
12312
12313         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12314
12315         if (build > 0) {
12316                 tp->fw_ver[8] = 'a' + build - 1;
12317                 tp->fw_ver[9] = '\0';
12318         }
12319 }
12320
12321 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12322 {
12323         u32 val, offset, start;
12324         int i, vlen;
12325
12326         for (offset = TG3_NVM_DIR_START;
12327              offset < TG3_NVM_DIR_END;
12328              offset += TG3_NVM_DIRENT_SIZE) {
12329                 if (tg3_nvram_read(tp, offset, &val))
12330                         return;
12331
12332                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12333                         break;
12334         }
12335
12336         if (offset == TG3_NVM_DIR_END)
12337                 return;
12338
12339         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12340                 start = 0x08000000;
12341         else if (tg3_nvram_read(tp, offset - 4, &start))
12342                 return;
12343
12344         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12345             !tg3_fw_img_is_valid(tp, offset) ||
12346             tg3_nvram_read(tp, offset + 8, &val))
12347                 return;
12348
12349         offset += val - start;
12350
12351         vlen = strlen(tp->fw_ver);
12352
12353         tp->fw_ver[vlen++] = ',';
12354         tp->fw_ver[vlen++] = ' ';
12355
12356         for (i = 0; i < 4; i++) {
12357                 __be32 v;
12358                 if (tg3_nvram_read_be32(tp, offset, &v))
12359                         return;
12360
12361                 offset += sizeof(v);
12362
12363                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12364                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12365                         break;
12366                 }
12367
12368                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12369                 vlen += sizeof(v);
12370         }
12371 }
12372
12373 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12374 {
12375         int vlen;
12376         u32 apedata;
12377
12378         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12379             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12380                 return;
12381
12382         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12383         if (apedata != APE_SEG_SIG_MAGIC)
12384                 return;
12385
12386         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12387         if (!(apedata & APE_FW_STATUS_READY))
12388                 return;
12389
12390         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12391
12392         vlen = strlen(tp->fw_ver);
12393
12394         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12395                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12396                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12397                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12398                  (apedata & APE_FW_VERSION_BLDMSK));
12399 }
12400
12401 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12402 {
12403         u32 val;
12404
12405         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12406                 tp->fw_ver[0] = 's';
12407                 tp->fw_ver[1] = 'b';
12408                 tp->fw_ver[2] = '\0';
12409
12410                 return;
12411         }
12412
12413         if (tg3_nvram_read(tp, 0, &val))
12414                 return;
12415
12416         if (val == TG3_EEPROM_MAGIC)
12417                 tg3_read_bc_ver(tp);
12418         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12419                 tg3_read_sb_ver(tp, val);
12420         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12421                 tg3_read_hwsb_ver(tp);
12422         else
12423                 return;
12424
12425         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12426              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12427                 return;
12428
12429         tg3_read_mgmtfw_ver(tp);
12430
12431         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12432 }
12433
12434 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12435
12436 static int __devinit tg3_get_invariants(struct tg3 *tp)
12437 {
12438         static struct pci_device_id write_reorder_chipsets[] = {
12439                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12440                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12441                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12442                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12443                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12444                              PCI_DEVICE_ID_VIA_8385_0) },
12445                 { },
12446         };
12447         u32 misc_ctrl_reg;
12448         u32 pci_state_reg, grc_misc_cfg;
12449         u32 val;
12450         u16 pci_cmd;
12451         int err;
12452
12453         /* Force memory write invalidate off.  If we leave it on,
12454          * then on 5700_BX chips we have to enable a workaround.
12455          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12456          * to match the cacheline size.  The Broadcom driver have this
12457          * workaround but turns MWI off all the times so never uses
12458          * it.  This seems to suggest that the workaround is insufficient.
12459          */
12460         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12461         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12462         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12463
12464         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12465          * has the register indirect write enable bit set before
12466          * we try to access any of the MMIO registers.  It is also
12467          * critical that the PCI-X hw workaround situation is decided
12468          * before that as well.
12469          */
12470         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12471                               &misc_ctrl_reg);
12472
12473         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12474                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12475         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12476                 u32 prod_id_asic_rev;
12477
12478                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12479                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12480                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12481                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12482                         pci_read_config_dword(tp->pdev,
12483                                               TG3PCI_GEN2_PRODID_ASICREV,
12484                                               &prod_id_asic_rev);
12485                 else
12486                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12487                                               &prod_id_asic_rev);
12488
12489                 tp->pci_chip_rev_id = prod_id_asic_rev;
12490         }
12491
12492         /* Wrong chip ID in 5752 A0. This code can be removed later
12493          * as A0 is not in production.
12494          */
12495         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12496                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12497
12498         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12499          * we need to disable memory and use config. cycles
12500          * only to access all registers. The 5702/03 chips
12501          * can mistakenly decode the special cycles from the
12502          * ICH chipsets as memory write cycles, causing corruption
12503          * of register and memory space. Only certain ICH bridges
12504          * will drive special cycles with non-zero data during the
12505          * address phase which can fall within the 5703's address
12506          * range. This is not an ICH bug as the PCI spec allows
12507          * non-zero address during special cycles. However, only
12508          * these ICH bridges are known to drive non-zero addresses
12509          * during special cycles.
12510          *
12511          * Since special cycles do not cross PCI bridges, we only
12512          * enable this workaround if the 5703 is on the secondary
12513          * bus of these ICH bridges.
12514          */
12515         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12516             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12517                 static struct tg3_dev_id {
12518                         u32     vendor;
12519                         u32     device;
12520                         u32     rev;
12521                 } ich_chipsets[] = {
12522                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12523                           PCI_ANY_ID },
12524                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12525                           PCI_ANY_ID },
12526                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12527                           0xa },
12528                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12529                           PCI_ANY_ID },
12530                         { },
12531                 };
12532                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12533                 struct pci_dev *bridge = NULL;
12534
12535                 while (pci_id->vendor != 0) {
12536                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12537                                                 bridge);
12538                         if (!bridge) {
12539                                 pci_id++;
12540                                 continue;
12541                         }
12542                         if (pci_id->rev != PCI_ANY_ID) {
12543                                 if (bridge->revision > pci_id->rev)
12544                                         continue;
12545                         }
12546                         if (bridge->subordinate &&
12547                             (bridge->subordinate->number ==
12548                              tp->pdev->bus->number)) {
12549
12550                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12551                                 pci_dev_put(bridge);
12552                                 break;
12553                         }
12554                 }
12555         }
12556
12557         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12558                 static struct tg3_dev_id {
12559                         u32     vendor;
12560                         u32     device;
12561                 } bridge_chipsets[] = {
12562                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12563                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12564                         { },
12565                 };
12566                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12567                 struct pci_dev *bridge = NULL;
12568
12569                 while (pci_id->vendor != 0) {
12570                         bridge = pci_get_device(pci_id->vendor,
12571                                                 pci_id->device,
12572                                                 bridge);
12573                         if (!bridge) {
12574                                 pci_id++;
12575                                 continue;
12576                         }
12577                         if (bridge->subordinate &&
12578                             (bridge->subordinate->number <=
12579                              tp->pdev->bus->number) &&
12580                             (bridge->subordinate->subordinate >=
12581                              tp->pdev->bus->number)) {
12582                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12583                                 pci_dev_put(bridge);
12584                                 break;
12585                         }
12586                 }
12587         }
12588
12589         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12590          * DMA addresses > 40-bit. This bridge may have other additional
12591          * 57xx devices behind it in some 4-port NIC designs for example.
12592          * Any tg3 device found behind the bridge will also need the 40-bit
12593          * DMA workaround.
12594          */
12595         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12596             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12597                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12598                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12599                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12600         }
12601         else {
12602                 struct pci_dev *bridge = NULL;
12603
12604                 do {
12605                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12606                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12607                                                 bridge);
12608                         if (bridge && bridge->subordinate &&
12609                             (bridge->subordinate->number <=
12610                              tp->pdev->bus->number) &&
12611                             (bridge->subordinate->subordinate >=
12612                              tp->pdev->bus->number)) {
12613                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12614                                 pci_dev_put(bridge);
12615                                 break;
12616                         }
12617                 } while (bridge);
12618         }
12619
12620         /* Initialize misc host control in PCI block. */
12621         tp->misc_host_ctrl |= (misc_ctrl_reg &
12622                                MISC_HOST_CTRL_CHIPREV);
12623         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12624                                tp->misc_host_ctrl);
12625
12626         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12627             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12628             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12629                 tp->pdev_peer = tg3_find_peer(tp);
12630
12631         /* Intentionally exclude ASIC_REV_5906 */
12632         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12633             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12634             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12635             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12636             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12637             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12638             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12639                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12640
12641         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12642             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12643             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12644             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12645             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12646                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12647
12648         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12649             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12650                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12651
12652         /* 5700 B0 chips do not support checksumming correctly due
12653          * to hardware bugs.
12654          */
12655         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12656                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12657         else {
12658                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12659                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12660                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12661                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12662         }
12663
12664         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12665                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12666                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12667                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12668                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12669                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12670                      tp->pdev_peer == tp->pdev))
12671                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12672
12673                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12674                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12675                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12676                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12677                 } else {
12678                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12679                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12680                                 ASIC_REV_5750 &&
12681                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12682                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12683                 }
12684         }
12685
12686         tp->irq_max = 1;
12687
12688         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12689                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12690                 tp->irq_max = TG3_IRQ_MAX_VECS;
12691         }
12692
12693         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12694                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12695                         tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12696                 else {
12697                         tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12698                         tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12699                 }
12700         }
12701
12702         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12703              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12704             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12705                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12706
12707         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12708                               &pci_state_reg);
12709
12710         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12711         if (tp->pcie_cap != 0) {
12712                 u16 lnkctl;
12713
12714                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12715
12716                 pcie_set_readrq(tp->pdev, 4096);
12717
12718                 pci_read_config_word(tp->pdev,
12719                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12720                                      &lnkctl);
12721                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12722                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12723                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12724                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12725                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12726                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12727                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12728                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12729                 }
12730         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12731                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12732         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12733                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12734                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12735                 if (!tp->pcix_cap) {
12736                         printk(KERN_ERR PFX "Cannot find PCI-X "
12737                                             "capability, aborting.\n");
12738                         return -EIO;
12739                 }
12740
12741                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12742                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12743         }
12744
12745         /* If we have an AMD 762 or VIA K8T800 chipset, write
12746          * reordering to the mailbox registers done by the host
12747          * controller can cause major troubles.  We read back from
12748          * every mailbox register write to force the writes to be
12749          * posted to the chip in order.
12750          */
12751         if (pci_dev_present(write_reorder_chipsets) &&
12752             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12753                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12754
12755         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12756                              &tp->pci_cacheline_sz);
12757         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12758                              &tp->pci_lat_timer);
12759         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12760             tp->pci_lat_timer < 64) {
12761                 tp->pci_lat_timer = 64;
12762                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12763                                       tp->pci_lat_timer);
12764         }
12765
12766         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12767                 /* 5700 BX chips need to have their TX producer index
12768                  * mailboxes written twice to workaround a bug.
12769                  */
12770                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12771
12772                 /* If we are in PCI-X mode, enable register write workaround.
12773                  *
12774                  * The workaround is to use indirect register accesses
12775                  * for all chip writes not to mailbox registers.
12776                  */
12777                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12778                         u32 pm_reg;
12779
12780                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12781
12782                         /* The chip can have it's power management PCI config
12783                          * space registers clobbered due to this bug.
12784                          * So explicitly force the chip into D0 here.
12785                          */
12786                         pci_read_config_dword(tp->pdev,
12787                                               tp->pm_cap + PCI_PM_CTRL,
12788                                               &pm_reg);
12789                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12790                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12791                         pci_write_config_dword(tp->pdev,
12792                                                tp->pm_cap + PCI_PM_CTRL,
12793                                                pm_reg);
12794
12795                         /* Also, force SERR#/PERR# in PCI command. */
12796                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12797                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12798                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12799                 }
12800         }
12801
12802         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12803                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12804         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12805                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12806
12807         /* Chip-specific fixup from Broadcom driver */
12808         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12809             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12810                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12811                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12812         }
12813
12814         /* Default fast path register access methods */
12815         tp->read32 = tg3_read32;
12816         tp->write32 = tg3_write32;
12817         tp->read32_mbox = tg3_read32;
12818         tp->write32_mbox = tg3_write32;
12819         tp->write32_tx_mbox = tg3_write32;
12820         tp->write32_rx_mbox = tg3_write32;
12821
12822         /* Various workaround register access methods */
12823         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12824                 tp->write32 = tg3_write_indirect_reg32;
12825         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12826                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12827                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12828                 /*
12829                  * Back to back register writes can cause problems on these
12830                  * chips, the workaround is to read back all reg writes
12831                  * except those to mailbox regs.
12832                  *
12833                  * See tg3_write_indirect_reg32().
12834                  */
12835                 tp->write32 = tg3_write_flush_reg32;
12836         }
12837
12838         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12839             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12840                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12841                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12842                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12843         }
12844
12845         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12846                 tp->read32 = tg3_read_indirect_reg32;
12847                 tp->write32 = tg3_write_indirect_reg32;
12848                 tp->read32_mbox = tg3_read_indirect_mbox;
12849                 tp->write32_mbox = tg3_write_indirect_mbox;
12850                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12851                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12852
12853                 iounmap(tp->regs);
12854                 tp->regs = NULL;
12855
12856                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12857                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12858                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12859         }
12860         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12861                 tp->read32_mbox = tg3_read32_mbox_5906;
12862                 tp->write32_mbox = tg3_write32_mbox_5906;
12863                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12864                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12865         }
12866
12867         if (tp->write32 == tg3_write_indirect_reg32 ||
12868             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12869              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12870               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12871                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12872
12873         /* Get eeprom hw config before calling tg3_set_power_state().
12874          * In particular, the TG3_FLG2_IS_NIC flag must be
12875          * determined before calling tg3_set_power_state() so that
12876          * we know whether or not to switch out of Vaux power.
12877          * When the flag is set, it means that GPIO1 is used for eeprom
12878          * write protect and also implies that it is a LOM where GPIOs
12879          * are not used to switch power.
12880          */
12881         tg3_get_eeprom_hw_cfg(tp);
12882
12883         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12884                 /* Allow reads and writes to the
12885                  * APE register and memory space.
12886                  */
12887                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12888                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12889                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12890                                        pci_state_reg);
12891         }
12892
12893         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12894             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12895             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12896             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12897             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12898                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12899
12900         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12901          * GPIO1 driven high will bring 5700's external PHY out of reset.
12902          * It is also used as eeprom write protect on LOMs.
12903          */
12904         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12905         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12906             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12907                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12908                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12909         /* Unused GPIO3 must be driven as output on 5752 because there
12910          * are no pull-up resistors on unused GPIO pins.
12911          */
12912         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12913                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12914
12915         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12916             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12917                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12918
12919         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12920             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12921                 /* Turn off the debug UART. */
12922                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12923                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12924                         /* Keep VMain power. */
12925                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12926                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12927         }
12928
12929         /* Force the chip into D0. */
12930         err = tg3_set_power_state(tp, PCI_D0);
12931         if (err) {
12932                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12933                        pci_name(tp->pdev));
12934                 return err;
12935         }
12936
12937         /* Derive initial jumbo mode from MTU assigned in
12938          * ether_setup() via the alloc_etherdev() call
12939          */
12940         if (tp->dev->mtu > ETH_DATA_LEN &&
12941             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12942                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12943
12944         /* Determine WakeOnLan speed to use. */
12945         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12946             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12947             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12948             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12949                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12950         } else {
12951                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12952         }
12953
12954         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12955                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12956
12957         /* A few boards don't want Ethernet@WireSpeed phy feature */
12958         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12959             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12960              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12961              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12962             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12963             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12964                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12965
12966         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12967             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12968                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12969         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12970                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12971
12972         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12973             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12974             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12975             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12976             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
12977                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12978                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12979                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12980                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12981                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12982                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12983                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12984                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12985                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12986                 } else
12987                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12988         }
12989
12990         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12991             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12992                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12993                 if (tp->phy_otp == 0)
12994                         tp->phy_otp = TG3_OTP_DEFAULT;
12995         }
12996
12997         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12998                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12999         else
13000                 tp->mi_mode = MAC_MI_MODE_BASE;
13001
13002         tp->coalesce_mode = 0;
13003         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13004             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13005                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13006
13007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13008             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13009                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13010
13011         err = tg3_mdio_init(tp);
13012         if (err)
13013                 return err;
13014
13015         /* Initialize data/descriptor byte/word swapping. */
13016         val = tr32(GRC_MODE);
13017         val &= GRC_MODE_HOST_STACKUP;
13018         tw32(GRC_MODE, val | tp->grc_mode);
13019
13020         tg3_switch_clocks(tp);
13021
13022         /* Clear this out for sanity. */
13023         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13024
13025         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13026                               &pci_state_reg);
13027         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13028             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13029                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13030
13031                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13032                     chiprevid == CHIPREV_ID_5701_B0 ||
13033                     chiprevid == CHIPREV_ID_5701_B2 ||
13034                     chiprevid == CHIPREV_ID_5701_B5) {
13035                         void __iomem *sram_base;
13036
13037                         /* Write some dummy words into the SRAM status block
13038                          * area, see if it reads back correctly.  If the return
13039                          * value is bad, force enable the PCIX workaround.
13040                          */
13041                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13042
13043                         writel(0x00000000, sram_base);
13044                         writel(0x00000000, sram_base + 4);
13045                         writel(0xffffffff, sram_base + 4);
13046                         if (readl(sram_base) != 0x00000000)
13047                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13048                 }
13049         }
13050
13051         udelay(50);
13052         tg3_nvram_init(tp);
13053
13054         grc_misc_cfg = tr32(GRC_MISC_CFG);
13055         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13056
13057         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13058             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13059              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13060                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13061
13062         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13063             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13064                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13065         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13066                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13067                                       HOSTCC_MODE_CLRTICK_TXBD);
13068
13069                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13070                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13071                                        tp->misc_host_ctrl);
13072         }
13073
13074         /* Preserve the APE MAC_MODE bits */
13075         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13076                 tp->mac_mode = tr32(MAC_MODE) |
13077                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13078         else
13079                 tp->mac_mode = TG3_DEF_MAC_MODE;
13080
13081         /* these are limited to 10/100 only */
13082         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13083              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13084             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13085              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13086              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13087               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13088               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13089             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13090              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13091               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13092               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13093             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13094             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13095                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13096
13097         err = tg3_phy_probe(tp);
13098         if (err) {
13099                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13100                        pci_name(tp->pdev), err);
13101                 /* ... but do not return immediately ... */
13102                 tg3_mdio_fini(tp);
13103         }
13104
13105         tg3_read_partno(tp);
13106         tg3_read_fw_ver(tp);
13107
13108         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13109                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13110         } else {
13111                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13112                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13113                 else
13114                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13115         }
13116
13117         /* 5700 {AX,BX} chips have a broken status block link
13118          * change bit implementation, so we must use the
13119          * status register in those cases.
13120          */
13121         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13122                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13123         else
13124                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13125
13126         /* The led_ctrl is set during tg3_phy_probe, here we might
13127          * have to force the link status polling mechanism based
13128          * upon subsystem IDs.
13129          */
13130         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13131             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13132             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13133                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13134                                   TG3_FLAG_USE_LINKCHG_REG);
13135         }
13136
13137         /* For all SERDES we poll the MAC status register. */
13138         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13139                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13140         else
13141                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13142
13143         tp->rx_offset = NET_IP_ALIGN;
13144         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13145             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13146                 tp->rx_offset = 0;
13147
13148         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13149
13150         /* Increment the rx prod index on the rx std ring by at most
13151          * 8 for these chips to workaround hw errata.
13152          */
13153         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13154             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13155             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13156                 tp->rx_std_max_post = 8;
13157
13158         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13159                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13160                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13161
13162         return err;
13163 }
13164
13165 #ifdef CONFIG_SPARC
13166 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13167 {
13168         struct net_device *dev = tp->dev;
13169         struct pci_dev *pdev = tp->pdev;
13170         struct device_node *dp = pci_device_to_OF_node(pdev);
13171         const unsigned char *addr;
13172         int len;
13173
13174         addr = of_get_property(dp, "local-mac-address", &len);
13175         if (addr && len == 6) {
13176                 memcpy(dev->dev_addr, addr, 6);
13177                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13178                 return 0;
13179         }
13180         return -ENODEV;
13181 }
13182
13183 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13184 {
13185         struct net_device *dev = tp->dev;
13186
13187         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13188         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13189         return 0;
13190 }
13191 #endif
13192
13193 static int __devinit tg3_get_device_address(struct tg3 *tp)
13194 {
13195         struct net_device *dev = tp->dev;
13196         u32 hi, lo, mac_offset;
13197         int addr_ok = 0;
13198
13199 #ifdef CONFIG_SPARC
13200         if (!tg3_get_macaddr_sparc(tp))
13201                 return 0;
13202 #endif
13203
13204         mac_offset = 0x7c;
13205         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13206             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13207                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13208                         mac_offset = 0xcc;
13209                 if (tg3_nvram_lock(tp))
13210                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13211                 else
13212                         tg3_nvram_unlock(tp);
13213         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13214                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13215                         mac_offset = 0xcc;
13216         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13217                 mac_offset = 0x10;
13218
13219         /* First try to get it from MAC address mailbox. */
13220         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13221         if ((hi >> 16) == 0x484b) {
13222                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13223                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13224
13225                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13226                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13227                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13228                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13229                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13230
13231                 /* Some old bootcode may report a 0 MAC address in SRAM */
13232                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13233         }
13234         if (!addr_ok) {
13235                 /* Next, try NVRAM. */
13236                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13237                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13238                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13239                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13240                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13241                 }
13242                 /* Finally just fetch it out of the MAC control regs. */
13243                 else {
13244                         hi = tr32(MAC_ADDR_0_HIGH);
13245                         lo = tr32(MAC_ADDR_0_LOW);
13246
13247                         dev->dev_addr[5] = lo & 0xff;
13248                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13249                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13250                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13251                         dev->dev_addr[1] = hi & 0xff;
13252                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13253                 }
13254         }
13255
13256         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13257 #ifdef CONFIG_SPARC
13258                 if (!tg3_get_default_macaddr_sparc(tp))
13259                         return 0;
13260 #endif
13261                 return -EINVAL;
13262         }
13263         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13264         return 0;
13265 }
13266
13267 #define BOUNDARY_SINGLE_CACHELINE       1
13268 #define BOUNDARY_MULTI_CACHELINE        2
13269
13270 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13271 {
13272         int cacheline_size;
13273         u8 byte;
13274         int goal;
13275
13276         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13277         if (byte == 0)
13278                 cacheline_size = 1024;
13279         else
13280                 cacheline_size = (int) byte * 4;
13281
13282         /* On 5703 and later chips, the boundary bits have no
13283          * effect.
13284          */
13285         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13286             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13287             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13288                 goto out;
13289
13290 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13291         goal = BOUNDARY_MULTI_CACHELINE;
13292 #else
13293 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13294         goal = BOUNDARY_SINGLE_CACHELINE;
13295 #else
13296         goal = 0;
13297 #endif
13298 #endif
13299
13300         if (!goal)
13301                 goto out;
13302
13303         /* PCI controllers on most RISC systems tend to disconnect
13304          * when a device tries to burst across a cache-line boundary.
13305          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13306          *
13307          * Unfortunately, for PCI-E there are only limited
13308          * write-side controls for this, and thus for reads
13309          * we will still get the disconnects.  We'll also waste
13310          * these PCI cycles for both read and write for chips
13311          * other than 5700 and 5701 which do not implement the
13312          * boundary bits.
13313          */
13314         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13315             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13316                 switch (cacheline_size) {
13317                 case 16:
13318                 case 32:
13319                 case 64:
13320                 case 128:
13321                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13322                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13323                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13324                         } else {
13325                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13326                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13327                         }
13328                         break;
13329
13330                 case 256:
13331                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13332                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13333                         break;
13334
13335                 default:
13336                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13337                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13338                         break;
13339                 }
13340         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13341                 switch (cacheline_size) {
13342                 case 16:
13343                 case 32:
13344                 case 64:
13345                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13346                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13347                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13348                                 break;
13349                         }
13350                         /* fallthrough */
13351                 case 128:
13352                 default:
13353                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13354                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13355                         break;
13356                 }
13357         } else {
13358                 switch (cacheline_size) {
13359                 case 16:
13360                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13361                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13362                                         DMA_RWCTRL_WRITE_BNDRY_16);
13363                                 break;
13364                         }
13365                         /* fallthrough */
13366                 case 32:
13367                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13368                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13369                                         DMA_RWCTRL_WRITE_BNDRY_32);
13370                                 break;
13371                         }
13372                         /* fallthrough */
13373                 case 64:
13374                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13375                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13376                                         DMA_RWCTRL_WRITE_BNDRY_64);
13377                                 break;
13378                         }
13379                         /* fallthrough */
13380                 case 128:
13381                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13382                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13383                                         DMA_RWCTRL_WRITE_BNDRY_128);
13384                                 break;
13385                         }
13386                         /* fallthrough */
13387                 case 256:
13388                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13389                                 DMA_RWCTRL_WRITE_BNDRY_256);
13390                         break;
13391                 case 512:
13392                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13393                                 DMA_RWCTRL_WRITE_BNDRY_512);
13394                         break;
13395                 case 1024:
13396                 default:
13397                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13398                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13399                         break;
13400                 }
13401         }
13402
13403 out:
13404         return val;
13405 }
13406
13407 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13408 {
13409         struct tg3_internal_buffer_desc test_desc;
13410         u32 sram_dma_descs;
13411         int i, ret;
13412
13413         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13414
13415         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13416         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13417         tw32(RDMAC_STATUS, 0);
13418         tw32(WDMAC_STATUS, 0);
13419
13420         tw32(BUFMGR_MODE, 0);
13421         tw32(FTQ_RESET, 0);
13422
13423         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13424         test_desc.addr_lo = buf_dma & 0xffffffff;
13425         test_desc.nic_mbuf = 0x00002100;
13426         test_desc.len = size;
13427
13428         /*
13429          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13430          * the *second* time the tg3 driver was getting loaded after an
13431          * initial scan.
13432          *
13433          * Broadcom tells me:
13434          *   ...the DMA engine is connected to the GRC block and a DMA
13435          *   reset may affect the GRC block in some unpredictable way...
13436          *   The behavior of resets to individual blocks has not been tested.
13437          *
13438          * Broadcom noted the GRC reset will also reset all sub-components.
13439          */
13440         if (to_device) {
13441                 test_desc.cqid_sqid = (13 << 8) | 2;
13442
13443                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13444                 udelay(40);
13445         } else {
13446                 test_desc.cqid_sqid = (16 << 8) | 7;
13447
13448                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13449                 udelay(40);
13450         }
13451         test_desc.flags = 0x00000005;
13452
13453         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13454                 u32 val;
13455
13456                 val = *(((u32 *)&test_desc) + i);
13457                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13458                                        sram_dma_descs + (i * sizeof(u32)));
13459                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13460         }
13461         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13462
13463         if (to_device) {
13464                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13465         } else {
13466                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13467         }
13468
13469         ret = -ENODEV;
13470         for (i = 0; i < 40; i++) {
13471                 u32 val;
13472
13473                 if (to_device)
13474                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13475                 else
13476                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13477                 if ((val & 0xffff) == sram_dma_descs) {
13478                         ret = 0;
13479                         break;
13480                 }
13481
13482                 udelay(100);
13483         }
13484
13485         return ret;
13486 }
13487
13488 #define TEST_BUFFER_SIZE        0x2000
13489
13490 static int __devinit tg3_test_dma(struct tg3 *tp)
13491 {
13492         dma_addr_t buf_dma;
13493         u32 *buf, saved_dma_rwctrl;
13494         int ret;
13495
13496         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13497         if (!buf) {
13498                 ret = -ENOMEM;
13499                 goto out_nofree;
13500         }
13501
13502         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13503                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13504
13505         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13506
13507         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13508                 /* DMA read watermark not used on PCIE */
13509                 tp->dma_rwctrl |= 0x00180000;
13510         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13511                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13512                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13513                         tp->dma_rwctrl |= 0x003f0000;
13514                 else
13515                         tp->dma_rwctrl |= 0x003f000f;
13516         } else {
13517                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13518                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13519                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13520                         u32 read_water = 0x7;
13521
13522                         /* If the 5704 is behind the EPB bridge, we can
13523                          * do the less restrictive ONE_DMA workaround for
13524                          * better performance.
13525                          */
13526                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13527                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13528                                 tp->dma_rwctrl |= 0x8000;
13529                         else if (ccval == 0x6 || ccval == 0x7)
13530                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13531
13532                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13533                                 read_water = 4;
13534                         /* Set bit 23 to enable PCIX hw bug fix */
13535                         tp->dma_rwctrl |=
13536                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13537                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13538                                 (1 << 23);
13539                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13540                         /* 5780 always in PCIX mode */
13541                         tp->dma_rwctrl |= 0x00144000;
13542                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13543                         /* 5714 always in PCIX mode */
13544                         tp->dma_rwctrl |= 0x00148000;
13545                 } else {
13546                         tp->dma_rwctrl |= 0x001b000f;
13547                 }
13548         }
13549
13550         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13551             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13552                 tp->dma_rwctrl &= 0xfffffff0;
13553
13554         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13555             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13556                 /* Remove this if it causes problems for some boards. */
13557                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13558
13559                 /* On 5700/5701 chips, we need to set this bit.
13560                  * Otherwise the chip will issue cacheline transactions
13561                  * to streamable DMA memory with not all the byte
13562                  * enables turned on.  This is an error on several
13563                  * RISC PCI controllers, in particular sparc64.
13564                  *
13565                  * On 5703/5704 chips, this bit has been reassigned
13566                  * a different meaning.  In particular, it is used
13567                  * on those chips to enable a PCI-X workaround.
13568                  */
13569                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13570         }
13571
13572         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13573
13574 #if 0
13575         /* Unneeded, already done by tg3_get_invariants.  */
13576         tg3_switch_clocks(tp);
13577 #endif
13578
13579         ret = 0;
13580         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13581             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13582                 goto out;
13583
13584         /* It is best to perform DMA test with maximum write burst size
13585          * to expose the 5700/5701 write DMA bug.
13586          */
13587         saved_dma_rwctrl = tp->dma_rwctrl;
13588         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13589         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13590
13591         while (1) {
13592                 u32 *p = buf, i;
13593
13594                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13595                         p[i] = i;
13596
13597                 /* Send the buffer to the chip. */
13598                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13599                 if (ret) {
13600                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13601                         break;
13602                 }
13603
13604 #if 0
13605                 /* validate data reached card RAM correctly. */
13606                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13607                         u32 val;
13608                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13609                         if (le32_to_cpu(val) != p[i]) {
13610                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13611                                 /* ret = -ENODEV here? */
13612                         }
13613                         p[i] = 0;
13614                 }
13615 #endif
13616                 /* Now read it back. */
13617                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13618                 if (ret) {
13619                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13620
13621                         break;
13622                 }
13623
13624                 /* Verify it. */
13625                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13626                         if (p[i] == i)
13627                                 continue;
13628
13629                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13630                             DMA_RWCTRL_WRITE_BNDRY_16) {
13631                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13632                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13633                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13634                                 break;
13635                         } else {
13636                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13637                                 ret = -ENODEV;
13638                                 goto out;
13639                         }
13640                 }
13641
13642                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13643                         /* Success. */
13644                         ret = 0;
13645                         break;
13646                 }
13647         }
13648         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13649             DMA_RWCTRL_WRITE_BNDRY_16) {
13650                 static struct pci_device_id dma_wait_state_chipsets[] = {
13651                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13652                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13653                         { },
13654                 };
13655
13656                 /* DMA test passed without adjusting DMA boundary,
13657                  * now look for chipsets that are known to expose the
13658                  * DMA bug without failing the test.
13659                  */
13660                 if (pci_dev_present(dma_wait_state_chipsets)) {
13661                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13662                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13663                 }
13664                 else
13665                         /* Safe to use the calculated DMA boundary. */
13666                         tp->dma_rwctrl = saved_dma_rwctrl;
13667
13668                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13669         }
13670
13671 out:
13672         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13673 out_nofree:
13674         return ret;
13675 }
13676
13677 static void __devinit tg3_init_link_config(struct tg3 *tp)
13678 {
13679         tp->link_config.advertising =
13680                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13681                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13682                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13683                  ADVERTISED_Autoneg | ADVERTISED_MII);
13684         tp->link_config.speed = SPEED_INVALID;
13685         tp->link_config.duplex = DUPLEX_INVALID;
13686         tp->link_config.autoneg = AUTONEG_ENABLE;
13687         tp->link_config.active_speed = SPEED_INVALID;
13688         tp->link_config.active_duplex = DUPLEX_INVALID;
13689         tp->link_config.phy_is_low_power = 0;
13690         tp->link_config.orig_speed = SPEED_INVALID;
13691         tp->link_config.orig_duplex = DUPLEX_INVALID;
13692         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13693 }
13694
13695 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13696 {
13697         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13698             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13699                 tp->bufmgr_config.mbuf_read_dma_low_water =
13700                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13701                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13702                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13703                 tp->bufmgr_config.mbuf_high_water =
13704                         DEFAULT_MB_HIGH_WATER_5705;
13705                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13706                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13707                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13708                         tp->bufmgr_config.mbuf_high_water =
13709                                 DEFAULT_MB_HIGH_WATER_5906;
13710                 }
13711
13712                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13713                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13714                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13715                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13716                 tp->bufmgr_config.mbuf_high_water_jumbo =
13717                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13718         } else {
13719                 tp->bufmgr_config.mbuf_read_dma_low_water =
13720                         DEFAULT_MB_RDMA_LOW_WATER;
13721                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13722                         DEFAULT_MB_MACRX_LOW_WATER;
13723                 tp->bufmgr_config.mbuf_high_water =
13724                         DEFAULT_MB_HIGH_WATER;
13725
13726                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13727                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13728                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13729                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13730                 tp->bufmgr_config.mbuf_high_water_jumbo =
13731                         DEFAULT_MB_HIGH_WATER_JUMBO;
13732         }
13733
13734         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13735         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13736 }
13737
13738 static char * __devinit tg3_phy_string(struct tg3 *tp)
13739 {
13740         switch (tp->phy_id & PHY_ID_MASK) {
13741         case PHY_ID_BCM5400:    return "5400";
13742         case PHY_ID_BCM5401:    return "5401";
13743         case PHY_ID_BCM5411:    return "5411";
13744         case PHY_ID_BCM5701:    return "5701";
13745         case PHY_ID_BCM5703:    return "5703";
13746         case PHY_ID_BCM5704:    return "5704";
13747         case PHY_ID_BCM5705:    return "5705";
13748         case PHY_ID_BCM5750:    return "5750";
13749         case PHY_ID_BCM5752:    return "5752";
13750         case PHY_ID_BCM5714:    return "5714";
13751         case PHY_ID_BCM5780:    return "5780";
13752         case PHY_ID_BCM5755:    return "5755";
13753         case PHY_ID_BCM5787:    return "5787";
13754         case PHY_ID_BCM5784:    return "5784";
13755         case PHY_ID_BCM5756:    return "5722/5756";
13756         case PHY_ID_BCM5906:    return "5906";
13757         case PHY_ID_BCM5761:    return "5761";
13758         case PHY_ID_BCM8002:    return "8002/serdes";
13759         case 0:                 return "serdes";
13760         default:                return "unknown";
13761         }
13762 }
13763
13764 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13765 {
13766         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13767                 strcpy(str, "PCI Express");
13768                 return str;
13769         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13770                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13771
13772                 strcpy(str, "PCIX:");
13773
13774                 if ((clock_ctrl == 7) ||
13775                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13776                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13777                         strcat(str, "133MHz");
13778                 else if (clock_ctrl == 0)
13779                         strcat(str, "33MHz");
13780                 else if (clock_ctrl == 2)
13781                         strcat(str, "50MHz");
13782                 else if (clock_ctrl == 4)
13783                         strcat(str, "66MHz");
13784                 else if (clock_ctrl == 6)
13785                         strcat(str, "100MHz");
13786         } else {
13787                 strcpy(str, "PCI:");
13788                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13789                         strcat(str, "66MHz");
13790                 else
13791                         strcat(str, "33MHz");
13792         }
13793         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13794                 strcat(str, ":32-bit");
13795         else
13796                 strcat(str, ":64-bit");
13797         return str;
13798 }
13799
13800 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13801 {
13802         struct pci_dev *peer;
13803         unsigned int func, devnr = tp->pdev->devfn & ~7;
13804
13805         for (func = 0; func < 8; func++) {
13806                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13807                 if (peer && peer != tp->pdev)
13808                         break;
13809                 pci_dev_put(peer);
13810         }
13811         /* 5704 can be configured in single-port mode, set peer to
13812          * tp->pdev in that case.
13813          */
13814         if (!peer) {
13815                 peer = tp->pdev;
13816                 return peer;
13817         }
13818
13819         /*
13820          * We don't need to keep the refcount elevated; there's no way
13821          * to remove one half of this device without removing the other
13822          */
13823         pci_dev_put(peer);
13824
13825         return peer;
13826 }
13827
13828 static void __devinit tg3_init_coal(struct tg3 *tp)
13829 {
13830         struct ethtool_coalesce *ec = &tp->coal;
13831
13832         memset(ec, 0, sizeof(*ec));
13833         ec->cmd = ETHTOOL_GCOALESCE;
13834         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13835         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13836         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13837         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13838         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13839         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13840         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13841         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13842         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13843
13844         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13845                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13846                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13847                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13848                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13849                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13850         }
13851
13852         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13853                 ec->rx_coalesce_usecs_irq = 0;
13854                 ec->tx_coalesce_usecs_irq = 0;
13855                 ec->stats_block_coalesce_usecs = 0;
13856         }
13857 }
13858
13859 static const struct net_device_ops tg3_netdev_ops = {
13860         .ndo_open               = tg3_open,
13861         .ndo_stop               = tg3_close,
13862         .ndo_start_xmit         = tg3_start_xmit,
13863         .ndo_get_stats          = tg3_get_stats,
13864         .ndo_validate_addr      = eth_validate_addr,
13865         .ndo_set_multicast_list = tg3_set_rx_mode,
13866         .ndo_set_mac_address    = tg3_set_mac_addr,
13867         .ndo_do_ioctl           = tg3_ioctl,
13868         .ndo_tx_timeout         = tg3_tx_timeout,
13869         .ndo_change_mtu         = tg3_change_mtu,
13870 #if TG3_VLAN_TAG_USED
13871         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13872 #endif
13873 #ifdef CONFIG_NET_POLL_CONTROLLER
13874         .ndo_poll_controller    = tg3_poll_controller,
13875 #endif
13876 };
13877
13878 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13879         .ndo_open               = tg3_open,
13880         .ndo_stop               = tg3_close,
13881         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13882         .ndo_get_stats          = tg3_get_stats,
13883         .ndo_validate_addr      = eth_validate_addr,
13884         .ndo_set_multicast_list = tg3_set_rx_mode,
13885         .ndo_set_mac_address    = tg3_set_mac_addr,
13886         .ndo_do_ioctl           = tg3_ioctl,
13887         .ndo_tx_timeout         = tg3_tx_timeout,
13888         .ndo_change_mtu         = tg3_change_mtu,
13889 #if TG3_VLAN_TAG_USED
13890         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13891 #endif
13892 #ifdef CONFIG_NET_POLL_CONTROLLER
13893         .ndo_poll_controller    = tg3_poll_controller,
13894 #endif
13895 };
13896
13897 static int __devinit tg3_init_one(struct pci_dev *pdev,
13898                                   const struct pci_device_id *ent)
13899 {
13900         static int tg3_version_printed = 0;
13901         struct net_device *dev;
13902         struct tg3 *tp;
13903         int i, err, pm_cap;
13904         u32 sndmbx, rcvmbx, intmbx;
13905         char str[40];
13906         u64 dma_mask, persist_dma_mask;
13907
13908         if (tg3_version_printed++ == 0)
13909                 printk(KERN_INFO "%s", version);
13910
13911         err = pci_enable_device(pdev);
13912         if (err) {
13913                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13914                        "aborting.\n");
13915                 return err;
13916         }
13917
13918         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13919         if (err) {
13920                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13921                        "aborting.\n");
13922                 goto err_out_disable_pdev;
13923         }
13924
13925         pci_set_master(pdev);
13926
13927         /* Find power-management capability. */
13928         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13929         if (pm_cap == 0) {
13930                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13931                        "aborting.\n");
13932                 err = -EIO;
13933                 goto err_out_free_res;
13934         }
13935
13936         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13937         if (!dev) {
13938                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13939                 err = -ENOMEM;
13940                 goto err_out_free_res;
13941         }
13942
13943         SET_NETDEV_DEV(dev, &pdev->dev);
13944
13945 #if TG3_VLAN_TAG_USED
13946         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13947 #endif
13948
13949         tp = netdev_priv(dev);
13950         tp->pdev = pdev;
13951         tp->dev = dev;
13952         tp->pm_cap = pm_cap;
13953         tp->rx_mode = TG3_DEF_RX_MODE;
13954         tp->tx_mode = TG3_DEF_TX_MODE;
13955
13956         if (tg3_debug > 0)
13957                 tp->msg_enable = tg3_debug;
13958         else
13959                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13960
13961         /* The word/byte swap controls here control register access byte
13962          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13963          * setting below.
13964          */
13965         tp->misc_host_ctrl =
13966                 MISC_HOST_CTRL_MASK_PCI_INT |
13967                 MISC_HOST_CTRL_WORD_SWAP |
13968                 MISC_HOST_CTRL_INDIR_ACCESS |
13969                 MISC_HOST_CTRL_PCISTATE_RW;
13970
13971         /* The NONFRM (non-frame) byte/word swap controls take effect
13972          * on descriptor entries, anything which isn't packet data.
13973          *
13974          * The StrongARM chips on the board (one for tx, one for rx)
13975          * are running in big-endian mode.
13976          */
13977         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13978                         GRC_MODE_WSWAP_NONFRM_DATA);
13979 #ifdef __BIG_ENDIAN
13980         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13981 #endif
13982         spin_lock_init(&tp->lock);
13983         spin_lock_init(&tp->indirect_lock);
13984         INIT_WORK(&tp->reset_task, tg3_reset_task);
13985
13986         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13987         if (!tp->regs) {
13988                 printk(KERN_ERR PFX "Cannot map device registers, "
13989                        "aborting.\n");
13990                 err = -ENOMEM;
13991                 goto err_out_free_dev;
13992         }
13993
13994         tg3_init_link_config(tp);
13995
13996         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13997         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13998
13999         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14000         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14001         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14002         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14003                 struct tg3_napi *tnapi = &tp->napi[i];
14004
14005                 tnapi->tp = tp;
14006                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14007
14008                 tnapi->int_mbox = intmbx;
14009                 if (i < 4)
14010                         intmbx += 0x8;
14011                 else
14012                         intmbx += 0x4;
14013
14014                 tnapi->consmbox = rcvmbx;
14015                 tnapi->prodmbox = sndmbx;
14016
14017                 if (i)
14018                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14019                 else
14020                         tnapi->coal_now = HOSTCC_MODE_NOW;
14021
14022                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14023                         break;
14024
14025                 /*
14026                  * If we support MSIX, we'll be using RSS.  If we're using
14027                  * RSS, the first vector only handles link interrupts and the
14028                  * remaining vectors handle rx and tx interrupts.  Reuse the
14029                  * mailbox values for the next iteration.  The values we setup
14030                  * above are still useful for the single vectored mode.
14031                  */
14032                 if (!i)
14033                         continue;
14034
14035                 rcvmbx += 0x8;
14036
14037                 if (sndmbx & 0x4)
14038                         sndmbx -= 0x4;
14039                 else
14040                         sndmbx += 0xc;
14041         }
14042
14043         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
14044         dev->ethtool_ops = &tg3_ethtool_ops;
14045         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14046         dev->irq = pdev->irq;
14047
14048         err = tg3_get_invariants(tp);
14049         if (err) {
14050                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14051                        "aborting.\n");
14052                 goto err_out_iounmap;
14053         }
14054
14055         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
14056                 dev->netdev_ops = &tg3_netdev_ops;
14057         else
14058                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14059
14060
14061         /* The EPB bridge inside 5714, 5715, and 5780 and any
14062          * device behind the EPB cannot support DMA addresses > 40-bit.
14063          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14064          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14065          * do DMA address check in tg3_start_xmit().
14066          */
14067         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14068                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14069         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14070                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14071 #ifdef CONFIG_HIGHMEM
14072                 dma_mask = DMA_BIT_MASK(64);
14073 #endif
14074         } else
14075                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14076
14077         /* Configure DMA attributes. */
14078         if (dma_mask > DMA_BIT_MASK(32)) {
14079                 err = pci_set_dma_mask(pdev, dma_mask);
14080                 if (!err) {
14081                         dev->features |= NETIF_F_HIGHDMA;
14082                         err = pci_set_consistent_dma_mask(pdev,
14083                                                           persist_dma_mask);
14084                         if (err < 0) {
14085                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14086                                        "DMA for consistent allocations\n");
14087                                 goto err_out_iounmap;
14088                         }
14089                 }
14090         }
14091         if (err || dma_mask == DMA_BIT_MASK(32)) {
14092                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14093                 if (err) {
14094                         printk(KERN_ERR PFX "No usable DMA configuration, "
14095                                "aborting.\n");
14096                         goto err_out_iounmap;
14097                 }
14098         }
14099
14100         tg3_init_bufmgr_config(tp);
14101
14102         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14103                 tp->fw_needed = FIRMWARE_TG3;
14104
14105         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14106                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14107         }
14108         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14109             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14110             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
14111             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14112             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14113                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14114         } else {
14115                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
14116                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14117                         tp->fw_needed = FIRMWARE_TG3TSO5;
14118                 else
14119                         tp->fw_needed = FIRMWARE_TG3TSO;
14120         }
14121
14122         /* TSO is on by default on chips that support hardware TSO.
14123          * Firmware TSO on older chips gives lower performance, so it
14124          * is off by default, but can be enabled using ethtool.
14125          */
14126         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14127                 if (dev->features & NETIF_F_IP_CSUM)
14128                         dev->features |= NETIF_F_TSO;
14129                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14130                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
14131                         dev->features |= NETIF_F_TSO6;
14132                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14133                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14134                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14135                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14136                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14137                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
14138                         dev->features |= NETIF_F_TSO_ECN;
14139         }
14140
14141
14142         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14143             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14144             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14145                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14146                 tp->rx_pending = 63;
14147         }
14148
14149         err = tg3_get_device_address(tp);
14150         if (err) {
14151                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14152                        "aborting.\n");
14153                 goto err_out_fw;
14154         }
14155
14156         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14157                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14158                 if (!tp->aperegs) {
14159                         printk(KERN_ERR PFX "Cannot map APE registers, "
14160                                "aborting.\n");
14161                         err = -ENOMEM;
14162                         goto err_out_fw;
14163                 }
14164
14165                 tg3_ape_lock_init(tp);
14166
14167                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14168                         tg3_read_dash_ver(tp);
14169         }
14170
14171         /*
14172          * Reset chip in case UNDI or EFI driver did not shutdown
14173          * DMA self test will enable WDMAC and we'll see (spurious)
14174          * pending DMA on the PCI bus at that point.
14175          */
14176         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14177             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14178                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14179                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14180         }
14181
14182         err = tg3_test_dma(tp);
14183         if (err) {
14184                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14185                 goto err_out_apeunmap;
14186         }
14187
14188         /* flow control autonegotiation is default behavior */
14189         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14190         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14191
14192         tg3_init_coal(tp);
14193
14194         pci_set_drvdata(pdev, dev);
14195
14196         err = register_netdev(dev);
14197         if (err) {
14198                 printk(KERN_ERR PFX "Cannot register net device, "
14199                        "aborting.\n");
14200                 goto err_out_apeunmap;
14201         }
14202
14203         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14204                dev->name,
14205                tp->board_part_number,
14206                tp->pci_chip_rev_id,
14207                tg3_bus_string(tp, str),
14208                dev->dev_addr);
14209
14210         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14211                 struct phy_device *phydev;
14212                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14213                 printk(KERN_INFO
14214                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14215                        tp->dev->name, phydev->drv->name,
14216                        dev_name(&phydev->dev));
14217         } else
14218                 printk(KERN_INFO
14219                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14220                        tp->dev->name, tg3_phy_string(tp),
14221                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14222                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14223                          "10/100/1000Base-T")),
14224                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14225
14226         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14227                dev->name,
14228                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14229                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14230                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14231                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14232                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14233         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14234                dev->name, tp->dma_rwctrl,
14235                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14236                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14237
14238         return 0;
14239
14240 err_out_apeunmap:
14241         if (tp->aperegs) {
14242                 iounmap(tp->aperegs);
14243                 tp->aperegs = NULL;
14244         }
14245
14246 err_out_fw:
14247         if (tp->fw)
14248                 release_firmware(tp->fw);
14249
14250 err_out_iounmap:
14251         if (tp->regs) {
14252                 iounmap(tp->regs);
14253                 tp->regs = NULL;
14254         }
14255
14256 err_out_free_dev:
14257         free_netdev(dev);
14258
14259 err_out_free_res:
14260         pci_release_regions(pdev);
14261
14262 err_out_disable_pdev:
14263         pci_disable_device(pdev);
14264         pci_set_drvdata(pdev, NULL);
14265         return err;
14266 }
14267
14268 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14269 {
14270         struct net_device *dev = pci_get_drvdata(pdev);
14271
14272         if (dev) {
14273                 struct tg3 *tp = netdev_priv(dev);
14274
14275                 if (tp->fw)
14276                         release_firmware(tp->fw);
14277
14278                 flush_scheduled_work();
14279
14280                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14281                         tg3_phy_fini(tp);
14282                         tg3_mdio_fini(tp);
14283                 }
14284
14285                 unregister_netdev(dev);
14286                 if (tp->aperegs) {
14287                         iounmap(tp->aperegs);
14288                         tp->aperegs = NULL;
14289                 }
14290                 if (tp->regs) {
14291                         iounmap(tp->regs);
14292                         tp->regs = NULL;
14293                 }
14294                 free_netdev(dev);
14295                 pci_release_regions(pdev);
14296                 pci_disable_device(pdev);
14297                 pci_set_drvdata(pdev, NULL);
14298         }
14299 }
14300
14301 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14302 {
14303         struct net_device *dev = pci_get_drvdata(pdev);
14304         struct tg3 *tp = netdev_priv(dev);
14305         pci_power_t target_state;
14306         int err;
14307
14308         /* PCI register 4 needs to be saved whether netif_running() or not.
14309          * MSI address and data need to be saved if using MSI and
14310          * netif_running().
14311          */
14312         pci_save_state(pdev);
14313
14314         if (!netif_running(dev))
14315                 return 0;
14316
14317         flush_scheduled_work();
14318         tg3_phy_stop(tp);
14319         tg3_netif_stop(tp);
14320
14321         del_timer_sync(&tp->timer);
14322
14323         tg3_full_lock(tp, 1);
14324         tg3_disable_ints(tp);
14325         tg3_full_unlock(tp);
14326
14327         netif_device_detach(dev);
14328
14329         tg3_full_lock(tp, 0);
14330         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14331         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14332         tg3_full_unlock(tp);
14333
14334         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14335
14336         err = tg3_set_power_state(tp, target_state);
14337         if (err) {
14338                 int err2;
14339
14340                 tg3_full_lock(tp, 0);
14341
14342                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14343                 err2 = tg3_restart_hw(tp, 1);
14344                 if (err2)
14345                         goto out;
14346
14347                 tp->timer.expires = jiffies + tp->timer_offset;
14348                 add_timer(&tp->timer);
14349
14350                 netif_device_attach(dev);
14351                 tg3_netif_start(tp);
14352
14353 out:
14354                 tg3_full_unlock(tp);
14355
14356                 if (!err2)
14357                         tg3_phy_start(tp);
14358         }
14359
14360         return err;
14361 }
14362
14363 static int tg3_resume(struct pci_dev *pdev)
14364 {
14365         struct net_device *dev = pci_get_drvdata(pdev);
14366         struct tg3 *tp = netdev_priv(dev);
14367         int err;
14368
14369         pci_restore_state(tp->pdev);
14370
14371         if (!netif_running(dev))
14372                 return 0;
14373
14374         err = tg3_set_power_state(tp, PCI_D0);
14375         if (err)
14376                 return err;
14377
14378         netif_device_attach(dev);
14379
14380         tg3_full_lock(tp, 0);
14381
14382         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14383         err = tg3_restart_hw(tp, 1);
14384         if (err)
14385                 goto out;
14386
14387         tp->timer.expires = jiffies + tp->timer_offset;
14388         add_timer(&tp->timer);
14389
14390         tg3_netif_start(tp);
14391
14392 out:
14393         tg3_full_unlock(tp);
14394
14395         if (!err)
14396                 tg3_phy_start(tp);
14397
14398         return err;
14399 }
14400
14401 static struct pci_driver tg3_driver = {
14402         .name           = DRV_MODULE_NAME,
14403         .id_table       = tg3_pci_tbl,
14404         .probe          = tg3_init_one,
14405         .remove         = __devexit_p(tg3_remove_one),
14406         .suspend        = tg3_suspend,
14407         .resume         = tg3_resume
14408 };
14409
14410 static int __init tg3_init(void)
14411 {
14412         return pci_register_driver(&tg3_driver);
14413 }
14414
14415 static void __exit tg3_cleanup(void)
14416 {
14417         pci_unregister_driver(&tg3_driver);
14418 }
14419
14420 module_init(tg3_init);
14421 module_exit(tg3_cleanup);