drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.99"
  72 #define DRV_MODULE_RELDATE      "April 20, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 130
 131 /* minimum number of free TX descriptors required to wake up TX process */
 132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 133
 134 #define TG3_RAW_IP_ALIGN 2
 135
 136 /* number of ETHTOOL_GSTATS u64's */
 137 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 138
 139 #define TG3_NUM_TEST            6
 140
 141 #define FIRMWARE_TG3            "tigon/tg3.bin"
 142 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 143 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 144
 145 static char version[] __devinitdata =
 146         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 147
 148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 150 MODULE_LICENSE("GPL");
 151 MODULE_VERSION(DRV_MODULE_VERSION);
 152 MODULE_FIRMWARE(FIRMWARE_TG3);
 153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 155
 156
 157 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 158 module_param(tg3_debug, int, 0);
 159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 160
 161 static struct pci_device_id tg3_pci_tbl[] = {
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 234         {}
 235 };
 236
 237 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 238
 239 static const struct {
 240         const char string[ETH_GSTRING_LEN];
 241 } ethtool_stats_keys[TG3_NUM_STATS] = {
 242         { "rx_octets" },
 243         { "rx_fragments" },
 244         { "rx_ucast_packets" },
 245         { "rx_mcast_packets" },
 246         { "rx_bcast_packets" },
 247         { "rx_fcs_errors" },
 248         { "rx_align_errors" },
 249         { "rx_xon_pause_rcvd" },
 250         { "rx_xoff_pause_rcvd" },
 251         { "rx_mac_ctrl_rcvd" },
 252         { "rx_xoff_entered" },
 253         { "rx_frame_too_long_errors" },
 254         { "rx_jabbers" },
 255         { "rx_undersize_packets" },
 256         { "rx_in_length_errors" },
 257         { "rx_out_length_errors" },
 258         { "rx_64_or_less_octet_packets" },
 259         { "rx_65_to_127_octet_packets" },
 260         { "rx_128_to_255_octet_packets" },
 261         { "rx_256_to_511_octet_packets" },
 262         { "rx_512_to_1023_octet_packets" },
 263         { "rx_1024_to_1522_octet_packets" },
 264         { "rx_1523_to_2047_octet_packets" },
 265         { "rx_2048_to_4095_octet_packets" },
 266         { "rx_4096_to_8191_octet_packets" },
 267         { "rx_8192_to_9022_octet_packets" },
 268
 269         { "tx_octets" },
 270         { "tx_collisions" },
 271
 272         { "tx_xon_sent" },
 273         { "tx_xoff_sent" },
 274         { "tx_flow_control" },
 275         { "tx_mac_errors" },
 276         { "tx_single_collisions" },
 277         { "tx_mult_collisions" },
 278         { "tx_deferred" },
 279         { "tx_excessive_collisions" },
 280         { "tx_late_collisions" },
 281         { "tx_collide_2times" },
 282         { "tx_collide_3times" },
 283         { "tx_collide_4times" },
 284         { "tx_collide_5times" },
 285         { "tx_collide_6times" },
 286         { "tx_collide_7times" },
 287         { "tx_collide_8times" },
 288         { "tx_collide_9times" },
 289         { "tx_collide_10times" },
 290         { "tx_collide_11times" },
 291         { "tx_collide_12times" },
 292         { "tx_collide_13times" },
 293         { "tx_collide_14times" },
 294         { "tx_collide_15times" },
 295         { "tx_ucast_packets" },
 296         { "tx_mcast_packets" },
 297         { "tx_bcast_packets" },
 298         { "tx_carrier_sense_errors" },
 299         { "tx_discards" },
 300         { "tx_errors" },
 301
 302         { "dma_writeq_full" },
 303         { "dma_write_prioq_full" },
 304         { "rxbds_empty" },
 305         { "rx_discards" },
 306         { "rx_errors" },
 307         { "rx_threshold_hit" },
 308
 309         { "dma_readq_full" },
 310         { "dma_read_prioq_full" },
 311         { "tx_comp_queue_full" },
 312
 313         { "ring_set_send_prod_index" },
 314         { "ring_status_update" },
 315         { "nic_irqs" },
 316         { "nic_avoided_irqs" },
 317         { "nic_tx_threshold_hit" }
 318 };
 319
 320 static const struct {
 321         const char string[ETH_GSTRING_LEN];
 322 } ethtool_test_keys[TG3_NUM_TEST] = {
 323         { "nvram test     (online) " },
 324         { "link test      (online) " },
 325         { "register test  (offline)" },
 326         { "memory test    (offline)" },
 327         { "loopback test  (offline)" },
 328         { "interrupt test (offline)" },
 329 };
 330
 331 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 332 {
 333         writel(val, tp->regs + off);
 334 }
 335
 336 static u32 tg3_read32(struct tg3 *tp, u32 off)
 337 {
 338         return (readl(tp->regs + off));
 339 }
 340
 341 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 342 {
 343         writel(val, tp->aperegs + off);
 344 }
 345
 346 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 347 {
 348         return (readl(tp->aperegs + off));
 349 }
 350
 351 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         unsigned long flags;
 354
 355         spin_lock_irqsave(&tp->indirect_lock, flags);
 356         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 357         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 358         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 359 }
 360
 361 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         writel(val, tp->regs + off);
 364         readl(tp->regs + off);
 365 }
 366
 367 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 368 {
 369         unsigned long flags;
 370         u32 val;
 371
 372         spin_lock_irqsave(&tp->indirect_lock, flags);
 373         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 374         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 375         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 376         return val;
 377 }
 378
 379 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         unsigned long flags;
 382
 383         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 384                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 385                                        TG3_64BIT_REG_LOW, val);
 386                 return;
 387         }
 388         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 389                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 390                                        TG3_64BIT_REG_LOW, val);
 391                 return;
 392         }
 393
 394         spin_lock_irqsave(&tp->indirect_lock, flags);
 395         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 396         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 397         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 398
 399         /* In indirect mode when disabling interrupts, we also need
 400          * to clear the interrupt bit in the GRC local ctrl register.
 401          */
 402         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 403             (val == 0x1)) {
 404                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 405                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 406         }
 407 }
 408
 409 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 410 {
 411         unsigned long flags;
 412         u32 val;
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418         return val;
 419 }
 420
 421 /* usec_wait specifies the wait time in usec when writing to certain registers
 422  * where it is unsafe to read back the register without some delay.
 423  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 424  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 425  */
 426 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 427 {
 428         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 429             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 430                 /* Non-posted methods */
 431                 tp->write32(tp, off, val);
 432         else {
 433                 /* Posted method */
 434                 tg3_write32(tp, off, val);
 435                 if (usec_wait)
 436                         udelay(usec_wait);
 437                 tp->read32(tp, off);
 438         }
 439         /* Wait again after the read for the posted method to guarantee that
 440          * the wait time is met.
 441          */
 442         if (usec_wait)
 443                 udelay(usec_wait);
 444 }
 445
 446 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 447 {
 448         tp->write32_mbox(tp, off, val);
 449         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 450             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 451                 tp->read32_mbox(tp, off);
 452 }
 453
 454 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 455 {
 456         void __iomem *mbox = tp->regs + off;
 457         writel(val, mbox);
 458         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 459                 writel(val, mbox);
 460         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 461                 readl(mbox);
 462 }
 463
 464 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 465 {
 466         return (readl(tp->regs + off + GRCMBOX_BASE));
 467 }
 468
 469 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 470 {
 471         writel(val, tp->regs + off + GRCMBOX_BASE);
 472 }
 473
 474 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 475 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 476 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 477 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 478 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 479
 480 #define tw32(reg,val)           tp->write32(tp, reg, val)
 481 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 483 #define tr32(reg)               tp->read32(tp, reg)
 484
 485 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 486 {
 487         unsigned long flags;
 488
 489         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 490             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 491                 return;
 492
 493         spin_lock_irqsave(&tp->indirect_lock, flags);
 494         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 495                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 496                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 497
 498                 /* Always leave this as zero. */
 499                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 500         } else {
 501                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 502                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 503
 504                 /* Always leave this as zero. */
 505                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 506         }
 507         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 508 }
 509
 510 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 511 {
 512         unsigned long flags;
 513
 514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 515             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 516                 *val = 0;
 517                 return;
 518         }
 519
 520         spin_lock_irqsave(&tp->indirect_lock, flags);
 521         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 523                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 524
 525                 /* Always leave this as zero. */
 526                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 527         } else {
 528                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 529                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 530
 531                 /* Always leave this as zero. */
 532                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 533         }
 534         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 535 }
 536
 537 static void tg3_ape_lock_init(struct tg3 *tp)
 538 {
 539         int i;
 540
 541         /* Make sure the driver hasn't any stale locks. */
 542         for (i = 0; i < 8; i++)
 543                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 544                                 APE_LOCK_GRANT_DRIVER);
 545 }
 546
 547 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 548 {
 549         int i, off;
 550         int ret = 0;
 551         u32 status;
 552
 553         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 554                 return 0;
 555
 556         switch (locknum) {
 557                 case TG3_APE_LOCK_GRC:
 558                 case TG3_APE_LOCK_MEM:
 559                         break;
 560                 default:
 561                         return -EINVAL;
 562         }
 563
 564         off = 4 * locknum;
 565
 566         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 567
 568         /* Wait for up to 1 millisecond to acquire lock. */
 569         for (i = 0; i < 100; i++) {
 570                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 571                 if (status == APE_LOCK_GRANT_DRIVER)
 572                         break;
 573                 udelay(10);
 574         }
 575
 576         if (status != APE_LOCK_GRANT_DRIVER) {
 577                 /* Revoke the lock request. */
 578                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 579                                 APE_LOCK_GRANT_DRIVER);
 580
 581                 ret = -EBUSY;
 582         }
 583
 584         return ret;
 585 }
 586
 587 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 588 {
 589         int off;
 590
 591         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 592                 return;
 593
 594         switch (locknum) {
 595                 case TG3_APE_LOCK_GRC:
 596                 case TG3_APE_LOCK_MEM:
 597                         break;
 598                 default:
 599                         return;
 600         }
 601
 602         off = 4 * locknum;
 603         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 604 }
 605
 606 static void tg3_disable_ints(struct tg3 *tp)
 607 {
 608         tw32(TG3PCI_MISC_HOST_CTRL,
 609              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 610         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 611 }
 612
 613 static inline void tg3_cond_int(struct tg3 *tp)
 614 {
 615         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 616             (tp->hw_status->status & SD_STATUS_UPDATED))
 617                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 618         else
 619                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 620                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 621 }
 622
 623 static void tg3_enable_ints(struct tg3 *tp)
 624 {
 625         tp->irq_sync = 0;
 626         wmb();
 627
 628         tw32(TG3PCI_MISC_HOST_CTRL,
 629              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 630         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 631                        (tp->last_tag << 24));
 632         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 633                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 634                                (tp->last_tag << 24));
 635         tg3_cond_int(tp);
 636 }
 637
 638 static inline unsigned int tg3_has_work(struct tg3 *tp)
 639 {
 640         struct tg3_hw_status *sblk = tp->hw_status;
 641         unsigned int work_exists = 0;
 642
 643         /* check for phy events */
 644         if (!(tp->tg3_flags &
 645               (TG3_FLAG_USE_LINKCHG_REG |
 646                TG3_FLAG_POLL_SERDES))) {
 647                 if (sblk->status & SD_STATUS_LINK_CHG)
 648                         work_exists = 1;
 649         }
 650         /* check for RX/TX work to do */
 651         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 652             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 653                 work_exists = 1;
 654
 655         return work_exists;
 656 }
 657
 658 /* tg3_restart_ints
 659  *  similar to tg3_enable_ints, but it accurately determines whether there
 660  *  is new work pending and can return without flushing the PIO write
 661  *  which reenables interrupts
 662  */
 663 static void tg3_restart_ints(struct tg3 *tp)
 664 {
 665         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 666                      tp->last_tag << 24);
 667         mmiowb();
 668
 669         /* When doing tagged status, this work check is unnecessary.
 670          * The last_tag we write above tells the chip which piece of
 671          * work we've completed.
 672          */
 673         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 674             tg3_has_work(tp))
 675                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 676                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 677 }
 678
 679 static inline void tg3_netif_stop(struct tg3 *tp)
 680 {
 681         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 682         napi_disable(&tp->napi);
 683         netif_tx_disable(tp->dev);
 684 }
 685
 686 static inline void tg3_netif_start(struct tg3 *tp)
 687 {
 688         netif_wake_queue(tp->dev);
 689         /* NOTE: unconditional netif_wake_queue is only appropriate
 690          * so long as all callers are assured to have free tx slots
 691          * (such as after tg3_init_hw)
 692          */
 693         napi_enable(&tp->napi);
 694         tp->hw_status->status |= SD_STATUS_UPDATED;
 695         tg3_enable_ints(tp);
 696 }
 697
 698 static void tg3_switch_clocks(struct tg3 *tp)
 699 {
 700         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 701         u32 orig_clock_ctrl;
 702
 703         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 704             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 705                 return;
 706
 707         orig_clock_ctrl = clock_ctrl;
 708         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 709                        CLOCK_CTRL_CLKRUN_OENABLE |
 710                        0x1f);
 711         tp->pci_clock_ctrl = clock_ctrl;
 712
 713         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 714                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 715                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 716                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 717                 }
 718         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 719                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 720                             clock_ctrl |
 721                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 722                             40);
 723                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 724                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 725                             40);
 726         }
 727         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 728 }
 729
 730 #define PHY_BUSY_LOOPS  5000
 731
 732 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 733 {
 734         u32 frame_val;
 735         unsigned int loops;
 736         int ret;
 737
 738         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 739                 tw32_f(MAC_MI_MODE,
 740                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 741                 udelay(80);
 742         }
 743
 744         *val = 0x0;
 745
 746         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 747                       MI_COM_PHY_ADDR_MASK);
 748         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 749                       MI_COM_REG_ADDR_MASK);
 750         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 751
 752         tw32_f(MAC_MI_COM, frame_val);
 753
 754         loops = PHY_BUSY_LOOPS;
 755         while (loops != 0) {
 756                 udelay(10);
 757                 frame_val = tr32(MAC_MI_COM);
 758
 759                 if ((frame_val & MI_COM_BUSY) == 0) {
 760                         udelay(5);
 761                         frame_val = tr32(MAC_MI_COM);
 762                         break;
 763                 }
 764                 loops -= 1;
 765         }
 766
 767         ret = -EBUSY;
 768         if (loops != 0) {
 769                 *val = frame_val & MI_COM_DATA_MASK;
 770                 ret = 0;
 771         }
 772
 773         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 774                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 775                 udelay(80);
 776         }
 777
 778         return ret;
 779 }
 780
 781 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 782 {
 783         u32 frame_val;
 784         unsigned int loops;
 785         int ret;
 786
 787         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 788             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 789                 return 0;
 790
 791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 792                 tw32_f(MAC_MI_MODE,
 793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 794                 udelay(80);
 795         }
 796
 797         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 798                       MI_COM_PHY_ADDR_MASK);
 799         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 800                       MI_COM_REG_ADDR_MASK);
 801         frame_val |= (val & MI_COM_DATA_MASK);
 802         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 803
 804         tw32_f(MAC_MI_COM, frame_val);
 805
 806         loops = PHY_BUSY_LOOPS;
 807         while (loops != 0) {
 808                 udelay(10);
 809                 frame_val = tr32(MAC_MI_COM);
 810                 if ((frame_val & MI_COM_BUSY) == 0) {
 811                         udelay(5);
 812                         frame_val = tr32(MAC_MI_COM);
 813                         break;
 814                 }
 815                 loops -= 1;
 816         }
 817
 818         ret = -EBUSY;
 819         if (loops != 0)
 820                 ret = 0;
 821
 822         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 823                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 824                 udelay(80);
 825         }
 826
 827         return ret;
 828 }
 829
 830 static int tg3_bmcr_reset(struct tg3 *tp)
 831 {
 832         u32 phy_control;
 833         int limit, err;
 834
 835         /* OK, reset it, and poll the BMCR_RESET bit until it
 836          * clears or we time out.
 837          */
 838         phy_control = BMCR_RESET;
 839         err = tg3_writephy(tp, MII_BMCR, phy_control);
 840         if (err != 0)
 841                 return -EBUSY;
 842
 843         limit = 5000;
 844         while (limit--) {
 845                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 846                 if (err != 0)
 847                         return -EBUSY;
 848
 849                 if ((phy_control & BMCR_RESET) == 0) {
 850                         udelay(40);
 851                         break;
 852                 }
 853                 udelay(10);
 854         }
 855         if (limit < 0)
 856                 return -EBUSY;
 857
 858         return 0;
 859 }
 860
 861 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 862 {
 863         struct tg3 *tp = bp->priv;
 864         u32 val;
 865
 866         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 867                 return -EAGAIN;
 868
 869         if (tg3_readphy(tp, reg, &val))
 870                 return -EIO;
 871
 872         return val;
 873 }
 874
 875 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 876 {
 877         struct tg3 *tp = bp->priv;
 878
 879         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 880                 return -EAGAIN;
 881
 882         if (tg3_writephy(tp, reg, val))
 883                 return -EIO;
 884
 885         return 0;
 886 }
 887
 888 static int tg3_mdio_reset(struct mii_bus *bp)
 889 {
 890         return 0;
 891 }
 892
 893 static void tg3_mdio_config_5785(struct tg3 *tp)
 894 {
 895         u32 val;
 896         struct phy_device *phydev;
 897
 898         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 899         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 900         case TG3_PHY_ID_BCM50610:
 901                 val = MAC_PHYCFG2_50610_LED_MODES;
 902                 break;
 903         case TG3_PHY_ID_BCMAC131:
 904                 val = MAC_PHYCFG2_AC131_LED_MODES;
 905                 break;
 906         case TG3_PHY_ID_RTL8211C:
 907                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 908                 break;
 909         case TG3_PHY_ID_RTL8201E:
 910                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 911                 break;
 912         default:
 913                 return;
 914         }
 915
 916         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 917                 tw32(MAC_PHYCFG2, val);
 918
 919                 val = tr32(MAC_PHYCFG1);
 920                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 921                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 922                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 923                 tw32(MAC_PHYCFG1, val);
 924
 925                 return;
 926         }
 927
 928         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 929                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 930                        MAC_PHYCFG2_FMODE_MASK_MASK |
 931                        MAC_PHYCFG2_GMODE_MASK_MASK |
 932                        MAC_PHYCFG2_ACT_MASK_MASK   |
 933                        MAC_PHYCFG2_QUAL_MASK_MASK |
 934                        MAC_PHYCFG2_INBAND_ENABLE;
 935
 936         tw32(MAC_PHYCFG2, val);
 937
 938         val = tr32(MAC_PHYCFG1);
 939         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 940                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 941         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 942                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 943                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 944                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 945                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 946         }
 947         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 948                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 949         tw32(MAC_PHYCFG1, val);
 950
 951         val = tr32(MAC_EXT_RGMII_MODE);
 952         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 953                  MAC_RGMII_MODE_RX_QUALITY |
 954                  MAC_RGMII_MODE_RX_ACTIVITY |
 955                  MAC_RGMII_MODE_RX_ENG_DET |
 956                  MAC_RGMII_MODE_TX_ENABLE |
 957                  MAC_RGMII_MODE_TX_LOWPWR |
 958                  MAC_RGMII_MODE_TX_RESET);
 959         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 960                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 961                         val |= MAC_RGMII_MODE_RX_INT_B |
 962                                MAC_RGMII_MODE_RX_QUALITY |
 963                                MAC_RGMII_MODE_RX_ACTIVITY |
 964                                MAC_RGMII_MODE_RX_ENG_DET;
 965                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 966                         val |= MAC_RGMII_MODE_TX_ENABLE |
 967                                MAC_RGMII_MODE_TX_LOWPWR |
 968                                MAC_RGMII_MODE_TX_RESET;
 969         }
 970         tw32(MAC_EXT_RGMII_MODE, val);
 971 }
 972
 973 static void tg3_mdio_start(struct tg3 *tp)
 974 {
 975         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 976                 mutex_lock(&tp->mdio_bus->mdio_lock);
 977                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 978                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 979         }
 980
 981         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 982         tw32_f(MAC_MI_MODE, tp->mi_mode);
 983         udelay(80);
 984
 985         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
 986             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
 987                 tg3_mdio_config_5785(tp);
 988 }
 989
 990 static void tg3_mdio_stop(struct tg3 *tp)
 991 {
 992         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 993                 mutex_lock(&tp->mdio_bus->mdio_lock);
 994                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
 995                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 996         }
 997 }
 998
 999 static int tg3_mdio_init(struct tg3 *tp)
1000 {
1001         int i;
1002         u32 reg;
1003         struct phy_device *phydev;
1004
1005         tg3_mdio_start(tp);
1006
1007         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1008             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1009                 return 0;
1010
1011         tp->mdio_bus = mdiobus_alloc();
1012         if (tp->mdio_bus == NULL)
1013                 return -ENOMEM;
1014
1015         tp->mdio_bus->name     = "tg3 mdio bus";
1016         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1017                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1018         tp->mdio_bus->priv     = tp;
1019         tp->mdio_bus->parent   = &tp->pdev->dev;
1020         tp->mdio_bus->read     = &tg3_mdio_read;
1021         tp->mdio_bus->write    = &tg3_mdio_write;
1022         tp->mdio_bus->reset    = &tg3_mdio_reset;
1023         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1024         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1025
1026         for (i = 0; i < PHY_MAX_ADDR; i++)
1027                 tp->mdio_bus->irq[i] = PHY_POLL;
1028
1029         /* The bus registration will look for all the PHYs on the mdio bus.
1030          * Unfortunately, it does not ensure the PHY is powered up before
1031          * accessing the PHY ID registers.  A chip reset is the
1032          * quickest way to bring the device back to an operational state..
1033          */
1034         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1035                 tg3_bmcr_reset(tp);
1036
1037         i = mdiobus_register(tp->mdio_bus);
1038         if (i) {
1039                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1040                         tp->dev->name, i);
1041                 mdiobus_free(tp->mdio_bus);
1042                 return i;
1043         }
1044
1045         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1046
1047         if (!phydev || !phydev->drv) {
1048                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1049                 mdiobus_unregister(tp->mdio_bus);
1050                 mdiobus_free(tp->mdio_bus);
1051                 return -ENODEV;
1052         }
1053
1054         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1055         case TG3_PHY_ID_BCM57780:
1056                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1057                 break;
1058         case TG3_PHY_ID_BCM50610:
1059                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1060                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1061                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1062                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1063                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1064                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1065                 /* fallthru */
1066         case TG3_PHY_ID_RTL8211C:
1067                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1068                 break;
1069         case TG3_PHY_ID_RTL8201E:
1070         case TG3_PHY_ID_BCMAC131:
1071                 phydev->interface = PHY_INTERFACE_MODE_MII;
1072                 break;
1073         }
1074
1075         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1076
1077         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1078                 tg3_mdio_config_5785(tp);
1079
1080         return 0;
1081 }
1082
1083 static void tg3_mdio_fini(struct tg3 *tp)
1084 {
1085         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1086                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1087                 mdiobus_unregister(tp->mdio_bus);
1088                 mdiobus_free(tp->mdio_bus);
1089                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1090         }
1091 }
1092
1093 /* tp->lock is held. */
1094 static inline void tg3_generate_fw_event(struct tg3 *tp)
1095 {
1096         u32 val;
1097
1098         val = tr32(GRC_RX_CPU_EVENT);
1099         val |= GRC_RX_CPU_DRIVER_EVENT;
1100         tw32_f(GRC_RX_CPU_EVENT, val);
1101
1102         tp->last_event_jiffies = jiffies;
1103 }
1104
1105 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1106
1107 /* tp->lock is held. */
1108 static void tg3_wait_for_event_ack(struct tg3 *tp)
1109 {
1110         int i;
1111         unsigned int delay_cnt;
1112         long time_remain;
1113
1114         /* If enough time has passed, no wait is necessary. */
1115         time_remain = (long)(tp->last_event_jiffies + 1 +
1116                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1117                       (long)jiffies;
1118         if (time_remain < 0)
1119                 return;
1120
1121         /* Check if we can shorten the wait time. */
1122         delay_cnt = jiffies_to_usecs(time_remain);
1123         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1124                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1125         delay_cnt = (delay_cnt >> 3) + 1;
1126
1127         for (i = 0; i < delay_cnt; i++) {
1128                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1129                         break;
1130                 udelay(8);
1131         }
1132 }
1133
1134 /* tp->lock is held. */
1135 static void tg3_ump_link_report(struct tg3 *tp)
1136 {
1137         u32 reg;
1138         u32 val;
1139
1140         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1141             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1142                 return;
1143
1144         tg3_wait_for_event_ack(tp);
1145
1146         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1147
1148         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1149
1150         val = 0;
1151         if (!tg3_readphy(tp, MII_BMCR, &reg))
1152                 val = reg << 16;
1153         if (!tg3_readphy(tp, MII_BMSR, &reg))
1154                 val |= (reg & 0xffff);
1155         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1156
1157         val = 0;
1158         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1159                 val = reg << 16;
1160         if (!tg3_readphy(tp, MII_LPA, &reg))
1161                 val |= (reg & 0xffff);
1162         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1163
1164         val = 0;
1165         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1166                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1167                         val = reg << 16;
1168                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1169                         val |= (reg & 0xffff);
1170         }
1171         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1172
1173         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1174                 val = reg << 16;
1175         else
1176                 val = 0;
1177         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1178
1179         tg3_generate_fw_event(tp);
1180 }
1181
1182 static void tg3_link_report(struct tg3 *tp)
1183 {
1184         if (!netif_carrier_ok(tp->dev)) {
1185                 if (netif_msg_link(tp))
1186                         printk(KERN_INFO PFX "%s: Link is down.\n",
1187                                tp->dev->name);
1188                 tg3_ump_link_report(tp);
1189         } else if (netif_msg_link(tp)) {
1190                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1191                        tp->dev->name,
1192                        (tp->link_config.active_speed == SPEED_1000 ?
1193                         1000 :
1194                         (tp->link_config.active_speed == SPEED_100 ?
1195                          100 : 10)),
1196                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1197                         "full" : "half"));
1198
1199                 printk(KERN_INFO PFX
1200                        "%s: Flow control is %s for TX and %s for RX.\n",
1201                        tp->dev->name,
1202                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1203                        "on" : "off",
1204                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1205                        "on" : "off");
1206                 tg3_ump_link_report(tp);
1207         }
1208 }
1209
1210 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1211 {
1212         u16 miireg;
1213
1214         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1215                 miireg = ADVERTISE_PAUSE_CAP;
1216         else if (flow_ctrl & FLOW_CTRL_TX)
1217                 miireg = ADVERTISE_PAUSE_ASYM;
1218         else if (flow_ctrl & FLOW_CTRL_RX)
1219                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1220         else
1221                 miireg = 0;
1222
1223         return miireg;
1224 }
1225
1226 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1227 {
1228         u16 miireg;
1229
1230         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1231                 miireg = ADVERTISE_1000XPAUSE;
1232         else if (flow_ctrl & FLOW_CTRL_TX)
1233                 miireg = ADVERTISE_1000XPSE_ASYM;
1234         else if (flow_ctrl & FLOW_CTRL_RX)
1235                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1236         else
1237                 miireg = 0;
1238
1239         return miireg;
1240 }
1241
1242 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1243 {
1244         u8 cap = 0;
1245
1246         if (lcladv & ADVERTISE_1000XPAUSE) {
1247                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1248                         if (rmtadv & LPA_1000XPAUSE)
1249                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1250                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1251                                 cap = FLOW_CTRL_RX;
1252                 } else {
1253                         if (rmtadv & LPA_1000XPAUSE)
1254                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1255                 }
1256         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1257                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1258                         cap = FLOW_CTRL_TX;
1259         }
1260
1261         return cap;
1262 }
1263
1264 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1265 {
1266         u8 autoneg;
1267         u8 flowctrl = 0;
1268         u32 old_rx_mode = tp->rx_mode;
1269         u32 old_tx_mode = tp->tx_mode;
1270
1271         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1272                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1273         else
1274                 autoneg = tp->link_config.autoneg;
1275
1276         if (autoneg == AUTONEG_ENABLE &&
1277             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1278                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1279                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1280                 else
1281                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1282         } else
1283                 flowctrl = tp->link_config.flowctrl;
1284
1285         tp->link_config.active_flowctrl = flowctrl;
1286
1287         if (flowctrl & FLOW_CTRL_RX)
1288                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1289         else
1290                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1291
1292         if (old_rx_mode != tp->rx_mode)
1293                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1294
1295         if (flowctrl & FLOW_CTRL_TX)
1296                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1297         else
1298                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1299
1300         if (old_tx_mode != tp->tx_mode)
1301                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1302 }
1303
1304 static void tg3_adjust_link(struct net_device *dev)
1305 {
1306         u8 oldflowctrl, linkmesg = 0;
1307         u32 mac_mode, lcl_adv, rmt_adv;
1308         struct tg3 *tp = netdev_priv(dev);
1309         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1310
1311         spin_lock(&tp->lock);
1312
1313         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1314                                     MAC_MODE_HALF_DUPLEX);
1315
1316         oldflowctrl = tp->link_config.active_flowctrl;
1317
1318         if (phydev->link) {
1319                 lcl_adv = 0;
1320                 rmt_adv = 0;
1321
1322                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1323                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1324                 else
1325                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1326
1327                 if (phydev->duplex == DUPLEX_HALF)
1328                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1329                 else {
1330                         lcl_adv = tg3_advert_flowctrl_1000T(
1331                                   tp->link_config.flowctrl);
1332
1333                         if (phydev->pause)
1334                                 rmt_adv = LPA_PAUSE_CAP;
1335                         if (phydev->asym_pause)
1336                                 rmt_adv |= LPA_PAUSE_ASYM;
1337                 }
1338
1339                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1340         } else
1341                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1342
1343         if (mac_mode != tp->mac_mode) {
1344                 tp->mac_mode = mac_mode;
1345                 tw32_f(MAC_MODE, tp->mac_mode);
1346                 udelay(40);
1347         }
1348
1349         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1350                 if (phydev->speed == SPEED_10)
1351                         tw32(MAC_MI_STAT,
1352                              MAC_MI_STAT_10MBPS_MODE |
1353                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1354                 else
1355                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1356         }
1357
1358         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1359                 tw32(MAC_TX_LENGTHS,
1360                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361                       (6 << TX_LENGTHS_IPG_SHIFT) |
1362                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363         else
1364                 tw32(MAC_TX_LENGTHS,
1365                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1366                       (6 << TX_LENGTHS_IPG_SHIFT) |
1367                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1368
1369         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1370             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1371             phydev->speed != tp->link_config.active_speed ||
1372             phydev->duplex != tp->link_config.active_duplex ||
1373             oldflowctrl != tp->link_config.active_flowctrl)
1374             linkmesg = 1;
1375
1376         tp->link_config.active_speed = phydev->speed;
1377         tp->link_config.active_duplex = phydev->duplex;
1378
1379         spin_unlock(&tp->lock);
1380
1381         if (linkmesg)
1382                 tg3_link_report(tp);
1383 }
1384
1385 static int tg3_phy_init(struct tg3 *tp)
1386 {
1387         struct phy_device *phydev;
1388
1389         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1390                 return 0;
1391
1392         /* Bring the PHY back to a known state. */
1393         tg3_bmcr_reset(tp);
1394
1395         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1396
1397         /* Attach the MAC to the PHY. */
1398         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1399                              phydev->dev_flags, phydev->interface);
1400         if (IS_ERR(phydev)) {
1401                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1402                 return PTR_ERR(phydev);
1403         }
1404
1405         /* Mask with MAC supported features. */
1406         switch (phydev->interface) {
1407         case PHY_INTERFACE_MODE_GMII:
1408         case PHY_INTERFACE_MODE_RGMII:
1409                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1410                         phydev->supported &= (PHY_GBIT_FEATURES |
1411                                               SUPPORTED_Pause |
1412                                               SUPPORTED_Asym_Pause);
1413                         break;
1414                 }
1415                 /* fallthru */
1416         case PHY_INTERFACE_MODE_MII:
1417                 phydev->supported &= (PHY_BASIC_FEATURES |
1418                                       SUPPORTED_Pause |
1419                                       SUPPORTED_Asym_Pause);
1420                 break;
1421         default:
1422                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1423                 return -EINVAL;
1424         }
1425
1426         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1427
1428         phydev->advertising = phydev->supported;
1429
1430         return 0;
1431 }
1432
1433 static void tg3_phy_start(struct tg3 *tp)
1434 {
1435         struct phy_device *phydev;
1436
1437         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1438                 return;
1439
1440         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1441
1442         if (tp->link_config.phy_is_low_power) {
1443                 tp->link_config.phy_is_low_power = 0;
1444                 phydev->speed = tp->link_config.orig_speed;
1445                 phydev->duplex = tp->link_config.orig_duplex;
1446                 phydev->autoneg = tp->link_config.orig_autoneg;
1447                 phydev->advertising = tp->link_config.orig_advertising;
1448         }
1449
1450         phy_start(phydev);
1451
1452         phy_start_aneg(phydev);
1453 }
1454
1455 static void tg3_phy_stop(struct tg3 *tp)
1456 {
1457         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1458                 return;
1459
1460         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1461 }
1462
1463 static void tg3_phy_fini(struct tg3 *tp)
1464 {
1465         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1466                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1467                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1468         }
1469 }
1470
1471 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1472 {
1473         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1474         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1475 }
1476
1477 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1478 {
1479         u32 reg;
1480
1481         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1482             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1483                 return;
1484
1485         reg = MII_TG3_MISC_SHDW_WREN |
1486               MII_TG3_MISC_SHDW_SCR5_SEL |
1487               MII_TG3_MISC_SHDW_SCR5_LPED |
1488               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1489               MII_TG3_MISC_SHDW_SCR5_SDTL |
1490               MII_TG3_MISC_SHDW_SCR5_C125OE;
1491         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1492                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1493
1494         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1495
1496
1497         reg = MII_TG3_MISC_SHDW_WREN |
1498               MII_TG3_MISC_SHDW_APD_SEL |
1499               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1500         if (enable)
1501                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1502
1503         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1504 }
1505
1506 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1507 {
1508         u32 phy;
1509
1510         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1511             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1512                 return;
1513
1514         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1515                 u32 ephy;
1516
1517                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1518                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1519                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1520                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1521                                 if (enable)
1522                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1523                                 else
1524                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1525                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1526                         }
1527                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1528                 }
1529         } else {
1530                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1531                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1532                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1533                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1534                         if (enable)
1535                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1536                         else
1537                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1538                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1539                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1540                 }
1541         }
1542 }
1543
1544 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1545 {
1546         u32 val;
1547
1548         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1549                 return;
1550
1551         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1552             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1553                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1554                              (val | (1 << 15) | (1 << 4)));
1555 }
1556
1557 static void tg3_phy_apply_otp(struct tg3 *tp)
1558 {
1559         u32 otp, phy;
1560
1561         if (!tp->phy_otp)
1562                 return;
1563
1564         otp = tp->phy_otp;
1565
1566         /* Enable SM_DSP clock and tx 6dB coding. */
1567         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1568               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1569               MII_TG3_AUXCTL_ACTL_TX_6DB;
1570         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1571
1572         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1573         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1574         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1575
1576         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1577               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1578         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1579
1580         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1581         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1582         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1583
1584         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1585         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1586
1587         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1588         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1589
1590         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1591               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1592         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1593
1594         /* Turn off SM_DSP clock. */
1595         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1596               MII_TG3_AUXCTL_ACTL_TX_6DB;
1597         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1598 }
1599
1600 static int tg3_wait_macro_done(struct tg3 *tp)
1601 {
1602         int limit = 100;
1603
1604         while (limit--) {
1605                 u32 tmp32;
1606
1607                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1608                         if ((tmp32 & 0x1000) == 0)
1609                                 break;
1610                 }
1611         }
1612         if (limit < 0)
1613                 return -EBUSY;
1614
1615         return 0;
1616 }
1617
1618 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1619 {
1620         static const u32 test_pat[4][6] = {
1621         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1622         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1623         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1624         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1625         };
1626         int chan;
1627
1628         for (chan = 0; chan < 4; chan++) {
1629                 int i;
1630
1631                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1632                              (chan * 0x2000) | 0x0200);
1633                 tg3_writephy(tp, 0x16, 0x0002);
1634
1635                 for (i = 0; i < 6; i++)
1636                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1637                                      test_pat[chan][i]);
1638
1639                 tg3_writephy(tp, 0x16, 0x0202);
1640                 if (tg3_wait_macro_done(tp)) {
1641                         *resetp = 1;
1642                         return -EBUSY;
1643                 }
1644
1645                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1646                              (chan * 0x2000) | 0x0200);
1647                 tg3_writephy(tp, 0x16, 0x0082);
1648                 if (tg3_wait_macro_done(tp)) {
1649                         *resetp = 1;
1650                         return -EBUSY;
1651                 }
1652
1653                 tg3_writephy(tp, 0x16, 0x0802);
1654                 if (tg3_wait_macro_done(tp)) {
1655                         *resetp = 1;
1656                         return -EBUSY;
1657                 }
1658
1659                 for (i = 0; i < 6; i += 2) {
1660                         u32 low, high;
1661
1662                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1663                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1664                             tg3_wait_macro_done(tp)) {
1665                                 *resetp = 1;
1666                                 return -EBUSY;
1667                         }
1668                         low &= 0x7fff;
1669                         high &= 0x000f;
1670                         if (low != test_pat[chan][i] ||
1671                             high != test_pat[chan][i+1]) {
1672                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1673                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1674                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1675
1676                                 return -EBUSY;
1677                         }
1678                 }
1679         }
1680
1681         return 0;
1682 }
1683
1684 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1685 {
1686         int chan;
1687
1688         for (chan = 0; chan < 4; chan++) {
1689                 int i;
1690
1691                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1692                              (chan * 0x2000) | 0x0200);
1693                 tg3_writephy(tp, 0x16, 0x0002);
1694                 for (i = 0; i < 6; i++)
1695                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1696                 tg3_writephy(tp, 0x16, 0x0202);
1697                 if (tg3_wait_macro_done(tp))
1698                         return -EBUSY;
1699         }
1700
1701         return 0;
1702 }
1703
1704 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1705 {
1706         u32 reg32, phy9_orig;
1707         int retries, do_phy_reset, err;
1708
1709         retries = 10;
1710         do_phy_reset = 1;
1711         do {
1712                 if (do_phy_reset) {
1713                         err = tg3_bmcr_reset(tp);
1714                         if (err)
1715                                 return err;
1716                         do_phy_reset = 0;
1717                 }
1718
1719                 /* Disable transmitter and interrupt.  */
1720                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1721                         continue;
1722
1723                 reg32 |= 0x3000;
1724                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1725
1726                 /* Set full-duplex, 1000 mbps.  */
1727                 tg3_writephy(tp, MII_BMCR,
1728                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1729
1730                 /* Set to master mode.  */
1731                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1732                         continue;
1733
1734                 tg3_writephy(tp, MII_TG3_CTRL,
1735                              (MII_TG3_CTRL_AS_MASTER |
1736                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1737
1738                 /* Enable SM_DSP_CLOCK and 6dB.  */
1739                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1740
1741                 /* Block the PHY control access.  */
1742                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1743                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1744
1745                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1746                 if (!err)
1747                         break;
1748         } while (--retries);
1749
1750         err = tg3_phy_reset_chanpat(tp);
1751         if (err)
1752                 return err;
1753
1754         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1755         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1756
1757         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1758         tg3_writephy(tp, 0x16, 0x0000);
1759
1760         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1761             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1762                 /* Set Extended packet length bit for jumbo frames */
1763                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1764         }
1765         else {
1766                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1767         }
1768
1769         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1770
1771         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1772                 reg32 &= ~0x3000;
1773                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1774         } else if (!err)
1775                 err = -EBUSY;
1776
1777         return err;
1778 }
1779
1780 /* This will reset the tigon3 PHY if there is no valid
1781  * link unless the FORCE argument is non-zero.
1782  */
1783 static int tg3_phy_reset(struct tg3 *tp)
1784 {
1785         u32 cpmuctrl;
1786         u32 phy_status;
1787         int err;
1788
1789         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1790                 u32 val;
1791
1792                 val = tr32(GRC_MISC_CFG);
1793                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1794                 udelay(40);
1795         }
1796         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1797         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1798         if (err != 0)
1799                 return -EBUSY;
1800
1801         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1802                 netif_carrier_off(tp->dev);
1803                 tg3_link_report(tp);
1804         }
1805
1806         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1807             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1808             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1809                 err = tg3_phy_reset_5703_4_5(tp);
1810                 if (err)
1811                         return err;
1812                 goto out;
1813         }
1814
1815         cpmuctrl = 0;
1816         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1817             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1818                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1819                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1820                         tw32(TG3_CPMU_CTRL,
1821                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1822         }
1823
1824         err = tg3_bmcr_reset(tp);
1825         if (err)
1826                 return err;
1827
1828         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1829                 u32 phy;
1830
1831                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1832                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1833
1834                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1835         }
1836
1837         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1838             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1839                 u32 val;
1840
1841                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1842                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1843                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1844                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1845                         udelay(40);
1846                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1847                 }
1848         }
1849
1850         tg3_phy_apply_otp(tp);
1851
1852         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1853                 tg3_phy_toggle_apd(tp, true);
1854         else
1855                 tg3_phy_toggle_apd(tp, false);
1856
1857 out:
1858         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1859                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1860                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1861                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1862                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1863                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1864                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1865         }
1866         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1867                 tg3_writephy(tp, 0x1c, 0x8d68);
1868                 tg3_writephy(tp, 0x1c, 0x8d68);
1869         }
1870         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1871                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1872                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1873                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1874                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1875                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1876                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1877                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1878                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1879         }
1880         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1881                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1882                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1883                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1884                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1885                         tg3_writephy(tp, MII_TG3_TEST1,
1886                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1887                 } else
1888                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1889                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1890         }
1891         /* Set Extended packet length bit (bit 14) on all chips that */
1892         /* support jumbo frames */
1893         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1894                 /* Cannot do read-modify-write on 5401 */
1895                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1896         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1897                 u32 phy_reg;
1898
1899                 /* Set bit 14 with read-modify-write to preserve other bits */
1900                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1901                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1902                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1903         }
1904
1905         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1906          * jumbo frames transmission.
1907          */
1908         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1909                 u32 phy_reg;
1910
1911                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1912                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1913                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1914         }
1915
1916         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1917                 /* adjust output voltage */
1918                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1919         }
1920
1921         tg3_phy_toggle_automdix(tp, 1);
1922         tg3_phy_set_wirespeed(tp);
1923         return 0;
1924 }
1925
1926 static void tg3_frob_aux_power(struct tg3 *tp)
1927 {
1928         struct tg3 *tp_peer = tp;
1929
1930         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1931                 return;
1932
1933         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1934             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1935                 struct net_device *dev_peer;
1936
1937                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1938                 /* remove_one() may have been run on the peer. */
1939                 if (!dev_peer)
1940                         tp_peer = tp;
1941                 else
1942                         tp_peer = netdev_priv(dev_peer);
1943         }
1944
1945         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1946             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1947             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1948             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1949                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1950                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1951                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1952                                     (GRC_LCLCTRL_GPIO_OE0 |
1953                                      GRC_LCLCTRL_GPIO_OE1 |
1954                                      GRC_LCLCTRL_GPIO_OE2 |
1955                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1956                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1957                                     100);
1958                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1959                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1960                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1961                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1962                                              GRC_LCLCTRL_GPIO_OE1 |
1963                                              GRC_LCLCTRL_GPIO_OE2 |
1964                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1965                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1966                                              tp->grc_local_ctrl;
1967                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1968
1969                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1970                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1971
1972                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1973                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1974                 } else {
1975                         u32 no_gpio2;
1976                         u32 grc_local_ctrl = 0;
1977
1978                         if (tp_peer != tp &&
1979                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1980                                 return;
1981
1982                         /* Workaround to prevent overdrawing Amps. */
1983                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1984                             ASIC_REV_5714) {
1985                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1986                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1987                                             grc_local_ctrl, 100);
1988                         }
1989
1990                         /* On 5753 and variants, GPIO2 cannot be used. */
1991                         no_gpio2 = tp->nic_sram_data_cfg &
1992                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1993
1994                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1995                                          GRC_LCLCTRL_GPIO_OE1 |
1996                                          GRC_LCLCTRL_GPIO_OE2 |
1997                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1998                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1999                         if (no_gpio2) {
2000                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2001                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2002                         }
2003                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2004                                                     grc_local_ctrl, 100);
2005
2006                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2007
2008                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2009                                                     grc_local_ctrl, 100);
2010
2011                         if (!no_gpio2) {
2012                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2013                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2014                                             grc_local_ctrl, 100);
2015                         }
2016                 }
2017         } else {
2018                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2019                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2020                         if (tp_peer != tp &&
2021                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2022                                 return;
2023
2024                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2025                                     (GRC_LCLCTRL_GPIO_OE1 |
2026                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2027
2028                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2029                                     GRC_LCLCTRL_GPIO_OE1, 100);
2030
2031                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2032                                     (GRC_LCLCTRL_GPIO_OE1 |
2033                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2034                 }
2035         }
2036 }
2037
2038 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2039 {
2040         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2041                 return 1;
2042         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2043                 if (speed != SPEED_10)
2044                         return 1;
2045         } else if (speed == SPEED_10)
2046                 return 1;
2047
2048         return 0;
2049 }
2050
2051 static int tg3_setup_phy(struct tg3 *, int);
2052
2053 #define RESET_KIND_SHUTDOWN     0
2054 #define RESET_KIND_INIT         1
2055 #define RESET_KIND_SUSPEND      2
2056
2057 static void tg3_write_sig_post_reset(struct tg3 *, int);
2058 static int tg3_halt_cpu(struct tg3 *, u32);
2059
2060 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2061 {
2062         u32 val;
2063
2064         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2065                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2066                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2067                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2068
2069                         sg_dig_ctrl |=
2070                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2071                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2072                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2073                 }
2074                 return;
2075         }
2076
2077         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2078                 tg3_bmcr_reset(tp);
2079                 val = tr32(GRC_MISC_CFG);
2080                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2081                 udelay(40);
2082                 return;
2083         } else if (do_low_power) {
2084                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2085                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2086
2087                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2088                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2089                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2090                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2091                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2092         }
2093
2094         /* The PHY should not be powered down on some chips because
2095          * of bugs.
2096          */
2097         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2098             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2099             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2100              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2101                 return;
2102
2103         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2104             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2105                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2106                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2107                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2108                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2109         }
2110
2111         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2112 }
2113
2114 /* tp->lock is held. */
2115 static int tg3_nvram_lock(struct tg3 *tp)
2116 {
2117         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2118                 int i;
2119
2120                 if (tp->nvram_lock_cnt == 0) {
2121                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2122                         for (i = 0; i < 8000; i++) {
2123                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2124                                         break;
2125                                 udelay(20);
2126                         }
2127                         if (i == 8000) {
2128                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2129                                 return -ENODEV;
2130                         }
2131                 }
2132                 tp->nvram_lock_cnt++;
2133         }
2134         return 0;
2135 }
2136
2137 /* tp->lock is held. */
2138 static void tg3_nvram_unlock(struct tg3 *tp)
2139 {
2140         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2141                 if (tp->nvram_lock_cnt > 0)
2142                         tp->nvram_lock_cnt--;
2143                 if (tp->nvram_lock_cnt == 0)
2144                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2145         }
2146 }
2147
2148 /* tp->lock is held. */
2149 static void tg3_enable_nvram_access(struct tg3 *tp)
2150 {
2151         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2152             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2153                 u32 nvaccess = tr32(NVRAM_ACCESS);
2154
2155                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2156         }
2157 }
2158
2159 /* tp->lock is held. */
2160 static void tg3_disable_nvram_access(struct tg3 *tp)
2161 {
2162         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2163             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2164                 u32 nvaccess = tr32(NVRAM_ACCESS);
2165
2166                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2167         }
2168 }
2169
2170 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2171                                         u32 offset, u32 *val)
2172 {
2173         u32 tmp;
2174         int i;
2175
2176         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2177                 return -EINVAL;
2178
2179         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2180                                         EEPROM_ADDR_DEVID_MASK |
2181                                         EEPROM_ADDR_READ);
2182         tw32(GRC_EEPROM_ADDR,
2183              tmp |
2184              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2185              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2186               EEPROM_ADDR_ADDR_MASK) |
2187              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2188
2189         for (i = 0; i < 1000; i++) {
2190                 tmp = tr32(GRC_EEPROM_ADDR);
2191
2192                 if (tmp & EEPROM_ADDR_COMPLETE)
2193                         break;
2194                 msleep(1);
2195         }
2196         if (!(tmp & EEPROM_ADDR_COMPLETE))
2197                 return -EBUSY;
2198
2199         tmp = tr32(GRC_EEPROM_DATA);
2200
2201         /*
2202          * The data will always be opposite the native endian
2203          * format.  Perform a blind byteswap to compensate.
2204          */
2205         *val = swab32(tmp);
2206
2207         return 0;
2208 }
2209
2210 #define NVRAM_CMD_TIMEOUT 10000
2211
2212 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2213 {
2214         int i;
2215
2216         tw32(NVRAM_CMD, nvram_cmd);
2217         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2218                 udelay(10);
2219                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2220                         udelay(10);
2221                         break;
2222                 }
2223         }
2224
2225         if (i == NVRAM_CMD_TIMEOUT)
2226                 return -EBUSY;
2227
2228         return 0;
2229 }
2230
2231 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2232 {
2233         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2234             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2235             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2236            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2237             (tp->nvram_jedecnum == JEDEC_ATMEL))
2238
2239                 addr = ((addr / tp->nvram_pagesize) <<
2240                         ATMEL_AT45DB0X1B_PAGE_POS) +
2241                        (addr % tp->nvram_pagesize);
2242
2243         return addr;
2244 }
2245
2246 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2247 {
2248         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2249             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2250             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2251            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2252             (tp->nvram_jedecnum == JEDEC_ATMEL))
2253
2254                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2255                         tp->nvram_pagesize) +
2256                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2257
2258         return addr;
2259 }
2260
2261 /* NOTE: Data read in from NVRAM is byteswapped according to
2262  * the byteswapping settings for all other register accesses.
2263  * tg3 devices are BE devices, so on a BE machine, the data
2264  * returned will be exactly as it is seen in NVRAM.  On a LE
2265  * machine, the 32-bit value will be byteswapped.
2266  */
2267 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2268 {
2269         int ret;
2270
2271         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2272                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2273
2274         offset = tg3_nvram_phys_addr(tp, offset);
2275
2276         if (offset > NVRAM_ADDR_MSK)
2277                 return -EINVAL;
2278
2279         ret = tg3_nvram_lock(tp);
2280         if (ret)
2281                 return ret;
2282
2283         tg3_enable_nvram_access(tp);
2284
2285         tw32(NVRAM_ADDR, offset);
2286         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2287                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2288
2289         if (ret == 0)
2290                 *val = tr32(NVRAM_RDDATA);
2291
2292         tg3_disable_nvram_access(tp);
2293
2294         tg3_nvram_unlock(tp);
2295
2296         return ret;
2297 }
2298
2299 /* Ensures NVRAM data is in bytestream format. */
2300 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2301 {
2302         u32 v;
2303         int res = tg3_nvram_read(tp, offset, &v);
2304         if (!res)
2305                 *val = cpu_to_be32(v);
2306         return res;
2307 }
2308
2309 /* tp->lock is held. */
2310 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2311 {
2312         u32 addr_high, addr_low;
2313         int i;
2314
2315         addr_high = ((tp->dev->dev_addr[0] << 8) |
2316                      tp->dev->dev_addr[1]);
2317         addr_low = ((tp->dev->dev_addr[2] << 24) |
2318                     (tp->dev->dev_addr[3] << 16) |
2319                     (tp->dev->dev_addr[4] <<  8) |
2320                     (tp->dev->dev_addr[5] <<  0));
2321         for (i = 0; i < 4; i++) {
2322                 if (i == 1 && skip_mac_1)
2323                         continue;
2324                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2325                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2326         }
2327
2328         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2329             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2330                 for (i = 0; i < 12; i++) {
2331                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2332                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2333                 }
2334         }
2335
2336         addr_high = (tp->dev->dev_addr[0] +
2337                      tp->dev->dev_addr[1] +
2338                      tp->dev->dev_addr[2] +
2339                      tp->dev->dev_addr[3] +
2340                      tp->dev->dev_addr[4] +
2341                      tp->dev->dev_addr[5]) &
2342                 TX_BACKOFF_SEED_MASK;
2343         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2344 }
2345
2346 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2347 {
2348         u32 misc_host_ctrl;
2349         bool device_should_wake, do_low_power;
2350
2351         /* Make sure register accesses (indirect or otherwise)
2352          * will function correctly.
2353          */
2354         pci_write_config_dword(tp->pdev,
2355                                TG3PCI_MISC_HOST_CTRL,
2356                                tp->misc_host_ctrl);
2357
2358         switch (state) {
2359         case PCI_D0:
2360                 pci_enable_wake(tp->pdev, state, false);
2361                 pci_set_power_state(tp->pdev, PCI_D0);
2362
2363                 /* Switch out of Vaux if it is a NIC */
2364                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2365                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2366
2367                 return 0;
2368
2369         case PCI_D1:
2370         case PCI_D2:
2371         case PCI_D3hot:
2372                 break;
2373
2374         default:
2375                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2376                         tp->dev->name, state);
2377                 return -EINVAL;
2378         }
2379
2380         /* Restore the CLKREQ setting. */
2381         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2382                 u16 lnkctl;
2383
2384                 pci_read_config_word(tp->pdev,
2385                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2386                                      &lnkctl);
2387                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2388                 pci_write_config_word(tp->pdev,
2389                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2390                                       lnkctl);
2391         }
2392
2393         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2394         tw32(TG3PCI_MISC_HOST_CTRL,
2395              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2396
2397         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2398                              device_may_wakeup(&tp->pdev->dev) &&
2399                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2400
2401         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2402                 do_low_power = false;
2403                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2404                     !tp->link_config.phy_is_low_power) {
2405                         struct phy_device *phydev;
2406                         u32 phyid, advertising;
2407
2408                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2409
2410                         tp->link_config.phy_is_low_power = 1;
2411
2412                         tp->link_config.orig_speed = phydev->speed;
2413                         tp->link_config.orig_duplex = phydev->duplex;
2414                         tp->link_config.orig_autoneg = phydev->autoneg;
2415                         tp->link_config.orig_advertising = phydev->advertising;
2416
2417                         advertising = ADVERTISED_TP |
2418                                       ADVERTISED_Pause |
2419                                       ADVERTISED_Autoneg |
2420                                       ADVERTISED_10baseT_Half;
2421
2422                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2423                             device_should_wake) {
2424                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2425                                         advertising |=
2426                                                 ADVERTISED_100baseT_Half |
2427                                                 ADVERTISED_100baseT_Full |
2428                                                 ADVERTISED_10baseT_Full;
2429                                 else
2430                                         advertising |= ADVERTISED_10baseT_Full;
2431                         }
2432
2433                         phydev->advertising = advertising;
2434
2435                         phy_start_aneg(phydev);
2436
2437                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2438                         if (phyid != TG3_PHY_ID_BCMAC131) {
2439                                 phyid &= TG3_PHY_OUI_MASK;
2440                                 if (phyid == TG3_PHY_OUI_1 ||
2441                                     phyid == TG3_PHY_OUI_2 ||
2442                                     phyid == TG3_PHY_OUI_3)
2443                                         do_low_power = true;
2444                         }
2445                 }
2446         } else {
2447                 do_low_power = true;
2448
2449                 if (tp->link_config.phy_is_low_power == 0) {
2450                         tp->link_config.phy_is_low_power = 1;
2451                         tp->link_config.orig_speed = tp->link_config.speed;
2452                         tp->link_config.orig_duplex = tp->link_config.duplex;
2453                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2454                 }
2455
2456                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2457                         tp->link_config.speed = SPEED_10;
2458                         tp->link_config.duplex = DUPLEX_HALF;
2459                         tp->link_config.autoneg = AUTONEG_ENABLE;
2460                         tg3_setup_phy(tp, 0);
2461                 }
2462         }
2463
2464         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2465                 u32 val;
2466
2467                 val = tr32(GRC_VCPU_EXT_CTRL);
2468                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2469         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2470                 int i;
2471                 u32 val;
2472
2473                 for (i = 0; i < 200; i++) {
2474                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2475                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2476                                 break;
2477                         msleep(1);
2478                 }
2479         }
2480         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2481                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2482                                                      WOL_DRV_STATE_SHUTDOWN |
2483                                                      WOL_DRV_WOL |
2484                                                      WOL_SET_MAGIC_PKT);
2485
2486         if (device_should_wake) {
2487                 u32 mac_mode;
2488
2489                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2490                         if (do_low_power) {
2491                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2492                                 udelay(40);
2493                         }
2494
2495                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2496                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2497                         else
2498                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2499
2500                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2501                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2502                             ASIC_REV_5700) {
2503                                 u32 speed = (tp->tg3_flags &
2504                                              TG3_FLAG_WOL_SPEED_100MB) ?
2505                                              SPEED_100 : SPEED_10;
2506                                 if (tg3_5700_link_polarity(tp, speed))
2507                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2508                                 else
2509                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2510                         }
2511                 } else {
2512                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2513                 }
2514
2515                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2516                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2517
2518                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2519                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2520                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2521                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2522                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2523                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2524
2525                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2526                         mac_mode |= tp->mac_mode &
2527                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2528                         if (mac_mode & MAC_MODE_APE_TX_EN)
2529                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2530                 }
2531
2532                 tw32_f(MAC_MODE, mac_mode);
2533                 udelay(100);
2534
2535                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2536                 udelay(10);
2537         }
2538
2539         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2540             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2541              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2542                 u32 base_val;
2543
2544                 base_val = tp->pci_clock_ctrl;
2545                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2546                              CLOCK_CTRL_TXCLK_DISABLE);
2547
2548                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2549                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2550         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2551                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2552                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2553                 /* do nothing */
2554         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2555                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2556                 u32 newbits1, newbits2;
2557
2558                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2559                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2560                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2561                                     CLOCK_CTRL_TXCLK_DISABLE |
2562                                     CLOCK_CTRL_ALTCLK);
2563                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2564                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2565                         newbits1 = CLOCK_CTRL_625_CORE;
2566                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2567                 } else {
2568                         newbits1 = CLOCK_CTRL_ALTCLK;
2569                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2570                 }
2571
2572                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2573                             40);
2574
2575                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2576                             40);
2577
2578                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2579                         u32 newbits3;
2580
2581                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2582                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2583                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2584                                             CLOCK_CTRL_TXCLK_DISABLE |
2585                                             CLOCK_CTRL_44MHZ_CORE);
2586                         } else {
2587                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2588                         }
2589
2590                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2591                                     tp->pci_clock_ctrl | newbits3, 40);
2592                 }
2593         }
2594
2595         if (!(device_should_wake) &&
2596             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2597                 tg3_power_down_phy(tp, do_low_power);
2598
2599         tg3_frob_aux_power(tp);
2600
2601         /* Workaround for unstable PLL clock */
2602         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2603             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2604                 u32 val = tr32(0x7d00);
2605
2606                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2607                 tw32(0x7d00, val);
2608                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2609                         int err;
2610
2611                         err = tg3_nvram_lock(tp);
2612                         tg3_halt_cpu(tp, RX_CPU_BASE);
2613                         if (!err)
2614                                 tg3_nvram_unlock(tp);
2615                 }
2616         }
2617
2618         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2619
2620         if (device_should_wake)
2621                 pci_enable_wake(tp->pdev, state, true);
2622
2623         /* Finally, set the new power state. */
2624         pci_set_power_state(tp->pdev, state);
2625
2626         return 0;
2627 }
2628
2629 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2630 {
2631         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2632         case MII_TG3_AUX_STAT_10HALF:
2633                 *speed = SPEED_10;
2634                 *duplex = DUPLEX_HALF;
2635                 break;
2636
2637         case MII_TG3_AUX_STAT_10FULL:
2638                 *speed = SPEED_10;
2639                 *duplex = DUPLEX_FULL;
2640                 break;
2641
2642         case MII_TG3_AUX_STAT_100HALF:
2643                 *speed = SPEED_100;
2644                 *duplex = DUPLEX_HALF;
2645                 break;
2646
2647         case MII_TG3_AUX_STAT_100FULL:
2648                 *speed = SPEED_100;
2649                 *duplex = DUPLEX_FULL;
2650                 break;
2651
2652         case MII_TG3_AUX_STAT_1000HALF:
2653                 *speed = SPEED_1000;
2654                 *duplex = DUPLEX_HALF;
2655                 break;
2656
2657         case MII_TG3_AUX_STAT_1000FULL:
2658                 *speed = SPEED_1000;
2659                 *duplex = DUPLEX_FULL;
2660                 break;
2661
2662         default:
2663                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2664                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2665                                  SPEED_10;
2666                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2667                                   DUPLEX_HALF;
2668                         break;
2669                 }
2670                 *speed = SPEED_INVALID;
2671                 *duplex = DUPLEX_INVALID;
2672                 break;
2673         }
2674 }
2675
2676 static void tg3_phy_copper_begin(struct tg3 *tp)
2677 {
2678         u32 new_adv;
2679         int i;
2680
2681         if (tp->link_config.phy_is_low_power) {
2682                 /* Entering low power mode.  Disable gigabit and
2683                  * 100baseT advertisements.
2684                  */
2685                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2686
2687                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2688                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2689                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2690                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2691
2692                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2693         } else if (tp->link_config.speed == SPEED_INVALID) {
2694                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2695                         tp->link_config.advertising &=
2696                                 ~(ADVERTISED_1000baseT_Half |
2697                                   ADVERTISED_1000baseT_Full);
2698
2699                 new_adv = ADVERTISE_CSMA;
2700                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2701                         new_adv |= ADVERTISE_10HALF;
2702                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2703                         new_adv |= ADVERTISE_10FULL;
2704                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2705                         new_adv |= ADVERTISE_100HALF;
2706                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2707                         new_adv |= ADVERTISE_100FULL;
2708
2709                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2710
2711                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2712
2713                 if (tp->link_config.advertising &
2714                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2715                         new_adv = 0;
2716                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2717                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2718                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2719                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2720                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2721                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2722                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2723                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2724                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2725                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2726                 } else {
2727                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2728                 }
2729         } else {
2730                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2731                 new_adv |= ADVERTISE_CSMA;
2732
2733                 /* Asking for a specific link mode. */
2734                 if (tp->link_config.speed == SPEED_1000) {
2735                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2736
2737                         if (tp->link_config.duplex == DUPLEX_FULL)
2738                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2739                         else
2740                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2741                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2742                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2743                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2744                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2745                 } else {
2746                         if (tp->link_config.speed == SPEED_100) {
2747                                 if (tp->link_config.duplex == DUPLEX_FULL)
2748                                         new_adv |= ADVERTISE_100FULL;
2749                                 else
2750                                         new_adv |= ADVERTISE_100HALF;
2751                         } else {
2752                                 if (tp->link_config.duplex == DUPLEX_FULL)
2753                                         new_adv |= ADVERTISE_10FULL;
2754                                 else
2755                                         new_adv |= ADVERTISE_10HALF;
2756                         }
2757                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2758
2759                         new_adv = 0;
2760                 }
2761
2762                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2763         }
2764
2765         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2766             tp->link_config.speed != SPEED_INVALID) {
2767                 u32 bmcr, orig_bmcr;
2768
2769                 tp->link_config.active_speed = tp->link_config.speed;
2770                 tp->link_config.active_duplex = tp->link_config.duplex;
2771
2772                 bmcr = 0;
2773                 switch (tp->link_config.speed) {
2774                 default:
2775                 case SPEED_10:
2776                         break;
2777
2778                 case SPEED_100:
2779                         bmcr |= BMCR_SPEED100;
2780                         break;
2781
2782                 case SPEED_1000:
2783                         bmcr |= TG3_BMCR_SPEED1000;
2784                         break;
2785                 }
2786
2787                 if (tp->link_config.duplex == DUPLEX_FULL)
2788                         bmcr |= BMCR_FULLDPLX;
2789
2790                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2791                     (bmcr != orig_bmcr)) {
2792                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2793                         for (i = 0; i < 1500; i++) {
2794                                 u32 tmp;
2795
2796                                 udelay(10);
2797                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2798                                     tg3_readphy(tp, MII_BMSR, &tmp))
2799                                         continue;
2800                                 if (!(tmp & BMSR_LSTATUS)) {
2801                                         udelay(40);
2802                                         break;
2803                                 }
2804                         }
2805                         tg3_writephy(tp, MII_BMCR, bmcr);
2806                         udelay(40);
2807                 }
2808         } else {
2809                 tg3_writephy(tp, MII_BMCR,
2810                              BMCR_ANENABLE | BMCR_ANRESTART);
2811         }
2812 }
2813
2814 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2815 {
2816         int err;
2817
2818         /* Turn off tap power management. */
2819         /* Set Extended packet length bit */
2820         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2821
2822         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2823         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2824
2825         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2826         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2827
2828         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2829         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2830
2831         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2832         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2833
2834         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2835         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2836
2837         udelay(40);
2838
2839         return err;
2840 }
2841
2842 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2843 {
2844         u32 adv_reg, all_mask = 0;
2845
2846         if (mask & ADVERTISED_10baseT_Half)
2847                 all_mask |= ADVERTISE_10HALF;
2848         if (mask & ADVERTISED_10baseT_Full)
2849                 all_mask |= ADVERTISE_10FULL;
2850         if (mask & ADVERTISED_100baseT_Half)
2851                 all_mask |= ADVERTISE_100HALF;
2852         if (mask & ADVERTISED_100baseT_Full)
2853                 all_mask |= ADVERTISE_100FULL;
2854
2855         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2856                 return 0;
2857
2858         if ((adv_reg & all_mask) != all_mask)
2859                 return 0;
2860         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2861                 u32 tg3_ctrl;
2862
2863                 all_mask = 0;
2864                 if (mask & ADVERTISED_1000baseT_Half)
2865                         all_mask |= ADVERTISE_1000HALF;
2866                 if (mask & ADVERTISED_1000baseT_Full)
2867                         all_mask |= ADVERTISE_1000FULL;
2868
2869                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2870                         return 0;
2871
2872                 if ((tg3_ctrl & all_mask) != all_mask)
2873                         return 0;
2874         }
2875         return 1;
2876 }
2877
2878 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2879 {
2880         u32 curadv, reqadv;
2881
2882         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2883                 return 1;
2884
2885         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2886         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2887
2888         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2889                 if (curadv != reqadv)
2890                         return 0;
2891
2892                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2893                         tg3_readphy(tp, MII_LPA, rmtadv);
2894         } else {
2895                 /* Reprogram the advertisement register, even if it
2896                  * does not affect the current link.  If the link
2897                  * gets renegotiated in the future, we can save an
2898                  * additional renegotiation cycle by advertising
2899                  * it correctly in the first place.
2900                  */
2901                 if (curadv != reqadv) {
2902                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2903                                      ADVERTISE_PAUSE_ASYM);
2904                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2905                 }
2906         }
2907
2908         return 1;
2909 }
2910
2911 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2912 {
2913         int current_link_up;
2914         u32 bmsr, dummy;
2915         u32 lcl_adv, rmt_adv;
2916         u16 current_speed;
2917         u8 current_duplex;
2918         int i, err;
2919
2920         tw32(MAC_EVENT, 0);
2921
2922         tw32_f(MAC_STATUS,
2923              (MAC_STATUS_SYNC_CHANGED |
2924               MAC_STATUS_CFG_CHANGED |
2925               MAC_STATUS_MI_COMPLETION |
2926               MAC_STATUS_LNKSTATE_CHANGED));
2927         udelay(40);
2928
2929         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2930                 tw32_f(MAC_MI_MODE,
2931                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2932                 udelay(80);
2933         }
2934
2935         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2936
2937         /* Some third-party PHYs need to be reset on link going
2938          * down.
2939          */
2940         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2941              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2942              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2943             netif_carrier_ok(tp->dev)) {
2944                 tg3_readphy(tp, MII_BMSR, &bmsr);
2945                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2946                     !(bmsr & BMSR_LSTATUS))
2947                         force_reset = 1;
2948         }
2949         if (force_reset)
2950                 tg3_phy_reset(tp);
2951
2952         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2953                 tg3_readphy(tp, MII_BMSR, &bmsr);
2954                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2955                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2956                         bmsr = 0;
2957
2958                 if (!(bmsr & BMSR_LSTATUS)) {
2959                         err = tg3_init_5401phy_dsp(tp);
2960                         if (err)
2961                                 return err;
2962
2963                         tg3_readphy(tp, MII_BMSR, &bmsr);
2964                         for (i = 0; i < 1000; i++) {
2965                                 udelay(10);
2966                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2967                                     (bmsr & BMSR_LSTATUS)) {
2968                                         udelay(40);
2969                                         break;
2970                                 }
2971                         }
2972
2973                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2974                             !(bmsr & BMSR_LSTATUS) &&
2975                             tp->link_config.active_speed == SPEED_1000) {
2976                                 err = tg3_phy_reset(tp);
2977                                 if (!err)
2978                                         err = tg3_init_5401phy_dsp(tp);
2979                                 if (err)
2980                                         return err;
2981                         }
2982                 }
2983         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2984                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2985                 /* 5701 {A0,B0} CRC bug workaround */
2986                 tg3_writephy(tp, 0x15, 0x0a75);
2987                 tg3_writephy(tp, 0x1c, 0x8c68);
2988                 tg3_writephy(tp, 0x1c, 0x8d68);
2989                 tg3_writephy(tp, 0x1c, 0x8c68);
2990         }
2991
2992         /* Clear pending interrupts... */
2993         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2994         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2995
2996         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2997                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2998         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2999                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3000
3001         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3002             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3003                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3004                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3005                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3006                 else
3007                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3008         }
3009
3010         current_link_up = 0;
3011         current_speed = SPEED_INVALID;
3012         current_duplex = DUPLEX_INVALID;
3013
3014         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3015                 u32 val;
3016
3017                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3018                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3019                 if (!(val & (1 << 10))) {
3020                         val |= (1 << 10);
3021                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3022                         goto relink;
3023                 }
3024         }
3025
3026         bmsr = 0;
3027         for (i = 0; i < 100; i++) {
3028                 tg3_readphy(tp, MII_BMSR, &bmsr);
3029                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3030                     (bmsr & BMSR_LSTATUS))
3031                         break;
3032                 udelay(40);
3033         }
3034
3035         if (bmsr & BMSR_LSTATUS) {
3036                 u32 aux_stat, bmcr;
3037
3038                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3039                 for (i = 0; i < 2000; i++) {
3040                         udelay(10);
3041                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3042                             aux_stat)
3043                                 break;
3044                 }
3045
3046                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3047                                              &current_speed,
3048                                              &current_duplex);
3049
3050                 bmcr = 0;
3051                 for (i = 0; i < 200; i++) {
3052                         tg3_readphy(tp, MII_BMCR, &bmcr);
3053                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3054                                 continue;
3055                         if (bmcr && bmcr != 0x7fff)
3056                                 break;
3057                         udelay(10);
3058                 }
3059
3060                 lcl_adv = 0;
3061                 rmt_adv = 0;
3062
3063                 tp->link_config.active_speed = current_speed;
3064                 tp->link_config.active_duplex = current_duplex;
3065
3066                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3067                         if ((bmcr & BMCR_ANENABLE) &&
3068                             tg3_copper_is_advertising_all(tp,
3069                                                 tp->link_config.advertising)) {
3070                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3071                                                                   &rmt_adv))
3072                                         current_link_up = 1;
3073                         }
3074                 } else {
3075                         if (!(bmcr & BMCR_ANENABLE) &&
3076                             tp->link_config.speed == current_speed &&
3077                             tp->link_config.duplex == current_duplex &&
3078                             tp->link_config.flowctrl ==
3079                             tp->link_config.active_flowctrl) {
3080                                 current_link_up = 1;
3081                         }
3082                 }
3083
3084                 if (current_link_up == 1 &&
3085                     tp->link_config.active_duplex == DUPLEX_FULL)
3086                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3087         }
3088
3089 relink:
3090         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3091                 u32 tmp;
3092
3093                 tg3_phy_copper_begin(tp);
3094
3095                 tg3_readphy(tp, MII_BMSR, &tmp);
3096                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3097                     (tmp & BMSR_LSTATUS))
3098                         current_link_up = 1;
3099         }
3100
3101         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3102         if (current_link_up == 1) {
3103                 if (tp->link_config.active_speed == SPEED_100 ||
3104                     tp->link_config.active_speed == SPEED_10)
3105                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3106                 else
3107                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3108         } else
3109                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3110
3111         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3112         if (tp->link_config.active_duplex == DUPLEX_HALF)
3113                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3114
3115         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3116                 if (current_link_up == 1 &&
3117                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3118                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3119                 else
3120                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3121         }
3122
3123         /* ??? Without this setting Netgear GA302T PHY does not
3124          * ??? send/receive packets...
3125          */
3126         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3127             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3128                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3129                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3130                 udelay(80);
3131         }
3132
3133         tw32_f(MAC_MODE, tp->mac_mode);
3134         udelay(40);
3135
3136         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3137                 /* Polled via timer. */
3138                 tw32_f(MAC_EVENT, 0);
3139         } else {
3140                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3141         }
3142         udelay(40);
3143
3144         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3145             current_link_up == 1 &&
3146             tp->link_config.active_speed == SPEED_1000 &&
3147             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3148              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3149                 udelay(120);
3150                 tw32_f(MAC_STATUS,
3151                      (MAC_STATUS_SYNC_CHANGED |
3152                       MAC_STATUS_CFG_CHANGED));
3153                 udelay(40);
3154                 tg3_write_mem(tp,
3155                               NIC_SRAM_FIRMWARE_MBOX,
3156                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3157         }
3158
3159         /* Prevent send BD corruption. */
3160         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3161                 u16 oldlnkctl, newlnkctl;
3162
3163                 pci_read_config_word(tp->pdev,
3164                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3165                                      &oldlnkctl);
3166                 if (tp->link_config.active_speed == SPEED_100 ||
3167                     tp->link_config.active_speed == SPEED_10)
3168                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3169                 else
3170                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3171                 if (newlnkctl != oldlnkctl)
3172                         pci_write_config_word(tp->pdev,
3173                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3174                                               newlnkctl);
3175         } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3176                 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3177                 if (tp->link_config.active_speed == SPEED_100 ||
3178                     tp->link_config.active_speed == SPEED_10)
3179                         newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3180                 else
3181                         newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3182                 if (newreg != oldreg)
3183                         tw32(TG3_PCIE_LNKCTL, newreg);
3184         }
3185
3186         if (current_link_up != netif_carrier_ok(tp->dev)) {
3187                 if (current_link_up)
3188                         netif_carrier_on(tp->dev);
3189                 else
3190                         netif_carrier_off(tp->dev);
3191                 tg3_link_report(tp);
3192         }
3193
3194         return 0;
3195 }
3196
3197 struct tg3_fiber_aneginfo {
3198         int state;
3199 #define ANEG_STATE_UNKNOWN              0
3200 #define ANEG_STATE_AN_ENABLE            1
3201 #define ANEG_STATE_RESTART_INIT         2
3202 #define ANEG_STATE_RESTART              3
3203 #define ANEG_STATE_DISABLE_LINK_OK      4
3204 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3205 #define ANEG_STATE_ABILITY_DETECT       6
3206 #define ANEG_STATE_ACK_DETECT_INIT      7
3207 #define ANEG_STATE_ACK_DETECT           8
3208 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3209 #define ANEG_STATE_COMPLETE_ACK         10
3210 #define ANEG_STATE_IDLE_DETECT_INIT     11
3211 #define ANEG_STATE_IDLE_DETECT          12
3212 #define ANEG_STATE_LINK_OK              13
3213 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3214 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3215
3216         u32 flags;
3217 #define MR_AN_ENABLE            0x00000001
3218 #define MR_RESTART_AN           0x00000002
3219 #define MR_AN_COMPLETE          0x00000004
3220 #define MR_PAGE_RX              0x00000008
3221 #define MR_NP_LOADED            0x00000010
3222 #define MR_TOGGLE_TX            0x00000020
3223 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3224 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3225 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3226 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3227 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3228 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3229 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3230 #define MR_TOGGLE_RX            0x00002000
3231 #define MR_NP_RX                0x00004000
3232
3233 #define MR_LINK_OK              0x80000000
3234
3235         unsigned long link_time, cur_time;
3236
3237         u32 ability_match_cfg;
3238         int ability_match_count;
3239
3240         char ability_match, idle_match, ack_match;
3241
3242         u32 txconfig, rxconfig;
3243 #define ANEG_CFG_NP             0x00000080
3244 #define ANEG_CFG_ACK            0x00000040
3245 #define ANEG_CFG_RF2            0x00000020
3246 #define ANEG_CFG_RF1            0x00000010
3247 #define ANEG_CFG_PS2            0x00000001
3248 #define ANEG_CFG_PS1            0x00008000
3249 #define ANEG_CFG_HD             0x00004000
3250 #define ANEG_CFG_FD             0x00002000
3251 #define ANEG_CFG_INVAL          0x00001f06
3252
3253 };
3254 #define ANEG_OK         0
3255 #define ANEG_DONE       1
3256 #define ANEG_TIMER_ENAB 2
3257 #define ANEG_FAILED     -1
3258
3259 #define ANEG_STATE_SETTLE_TIME  10000
3260
3261 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3262                                    struct tg3_fiber_aneginfo *ap)
3263 {
3264         u16 flowctrl;
3265         unsigned long delta;
3266         u32 rx_cfg_reg;
3267         int ret;
3268
3269         if (ap->state == ANEG_STATE_UNKNOWN) {
3270                 ap->rxconfig = 0;
3271                 ap->link_time = 0;
3272                 ap->cur_time = 0;
3273                 ap->ability_match_cfg = 0;
3274                 ap->ability_match_count = 0;
3275                 ap->ability_match = 0;
3276                 ap->idle_match = 0;
3277                 ap->ack_match = 0;
3278         }
3279         ap->cur_time++;
3280
3281         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3282                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3283
3284                 if (rx_cfg_reg != ap->ability_match_cfg) {
3285                         ap->ability_match_cfg = rx_cfg_reg;
3286                         ap->ability_match = 0;
3287                         ap->ability_match_count = 0;
3288                 } else {
3289                         if (++ap->ability_match_count > 1) {
3290                                 ap->ability_match = 1;
3291                                 ap->ability_match_cfg = rx_cfg_reg;
3292                         }
3293                 }
3294                 if (rx_cfg_reg & ANEG_CFG_ACK)
3295                         ap->ack_match = 1;
3296                 else
3297                         ap->ack_match = 0;
3298
3299                 ap->idle_match = 0;
3300         } else {
3301                 ap->idle_match = 1;
3302                 ap->ability_match_cfg = 0;
3303                 ap->ability_match_count = 0;
3304                 ap->ability_match = 0;
3305                 ap->ack_match = 0;
3306
3307                 rx_cfg_reg = 0;
3308         }
3309
3310         ap->rxconfig = rx_cfg_reg;
3311         ret = ANEG_OK;
3312
3313         switch(ap->state) {
3314         case ANEG_STATE_UNKNOWN:
3315                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3316                         ap->state = ANEG_STATE_AN_ENABLE;
3317
3318                 /* fallthru */
3319         case ANEG_STATE_AN_ENABLE:
3320                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3321                 if (ap->flags & MR_AN_ENABLE) {
3322                         ap->link_time = 0;
3323                         ap->cur_time = 0;
3324                         ap->ability_match_cfg = 0;
3325                         ap->ability_match_count = 0;
3326                         ap->ability_match = 0;
3327                         ap->idle_match = 0;
3328                         ap->ack_match = 0;
3329
3330                         ap->state = ANEG_STATE_RESTART_INIT;
3331                 } else {
3332                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3333                 }
3334                 break;
3335
3336         case ANEG_STATE_RESTART_INIT:
3337                 ap->link_time = ap->cur_time;
3338                 ap->flags &= ~(MR_NP_LOADED);
3339                 ap->txconfig = 0;
3340                 tw32(MAC_TX_AUTO_NEG, 0);
3341                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3342                 tw32_f(MAC_MODE, tp->mac_mode);
3343                 udelay(40);
3344
3345                 ret = ANEG_TIMER_ENAB;
3346                 ap->state = ANEG_STATE_RESTART;
3347
3348                 /* fallthru */
3349         case ANEG_STATE_RESTART:
3350                 delta = ap->cur_time - ap->link_time;
3351                 if (delta > ANEG_STATE_SETTLE_TIME) {
3352                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3353                 } else {
3354                         ret = ANEG_TIMER_ENAB;
3355                 }
3356                 break;
3357
3358         case ANEG_STATE_DISABLE_LINK_OK:
3359                 ret = ANEG_DONE;
3360                 break;
3361
3362         case ANEG_STATE_ABILITY_DETECT_INIT:
3363                 ap->flags &= ~(MR_TOGGLE_TX);
3364                 ap->txconfig = ANEG_CFG_FD;
3365                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3366                 if (flowctrl & ADVERTISE_1000XPAUSE)
3367                         ap->txconfig |= ANEG_CFG_PS1;
3368                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3369                         ap->txconfig |= ANEG_CFG_PS2;
3370                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3371                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3372                 tw32_f(MAC_MODE, tp->mac_mode);
3373                 udelay(40);
3374
3375                 ap->state = ANEG_STATE_ABILITY_DETECT;
3376                 break;
3377
3378         case ANEG_STATE_ABILITY_DETECT:
3379                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3380                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3381                 }
3382                 break;
3383
3384         case ANEG_STATE_ACK_DETECT_INIT:
3385                 ap->txconfig |= ANEG_CFG_ACK;
3386                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3387                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3388                 tw32_f(MAC_MODE, tp->mac_mode);
3389                 udelay(40);
3390
3391                 ap->state = ANEG_STATE_ACK_DETECT;
3392
3393                 /* fallthru */
3394         case ANEG_STATE_ACK_DETECT:
3395                 if (ap->ack_match != 0) {
3396                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3397                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3398                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3399                         } else {
3400                                 ap->state = ANEG_STATE_AN_ENABLE;
3401                         }
3402                 } else if (ap->ability_match != 0 &&
3403                            ap->rxconfig == 0) {
3404                         ap->state = ANEG_STATE_AN_ENABLE;
3405                 }
3406                 break;
3407
3408         case ANEG_STATE_COMPLETE_ACK_INIT:
3409                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3410                         ret = ANEG_FAILED;
3411                         break;
3412                 }
3413                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3414                                MR_LP_ADV_HALF_DUPLEX |
3415                                MR_LP_ADV_SYM_PAUSE |
3416                                MR_LP_ADV_ASYM_PAUSE |
3417                                MR_LP_ADV_REMOTE_FAULT1 |
3418                                MR_LP_ADV_REMOTE_FAULT2 |
3419                                MR_LP_ADV_NEXT_PAGE |
3420                                MR_TOGGLE_RX |
3421                                MR_NP_RX);
3422                 if (ap->rxconfig & ANEG_CFG_FD)
3423                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3424                 if (ap->rxconfig & ANEG_CFG_HD)
3425                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3426                 if (ap->rxconfig & ANEG_CFG_PS1)
3427                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3428                 if (ap->rxconfig & ANEG_CFG_PS2)
3429                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3430                 if (ap->rxconfig & ANEG_CFG_RF1)
3431                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3432                 if (ap->rxconfig & ANEG_CFG_RF2)
3433                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3434                 if (ap->rxconfig & ANEG_CFG_NP)
3435                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3436
3437                 ap->link_time = ap->cur_time;
3438
3439                 ap->flags ^= (MR_TOGGLE_TX);
3440                 if (ap->rxconfig & 0x0008)
3441                         ap->flags |= MR_TOGGLE_RX;
3442                 if (ap->rxconfig & ANEG_CFG_NP)
3443                         ap->flags |= MR_NP_RX;
3444                 ap->flags |= MR_PAGE_RX;
3445
3446                 ap->state = ANEG_STATE_COMPLETE_ACK;
3447                 ret = ANEG_TIMER_ENAB;
3448                 break;
3449
3450         case ANEG_STATE_COMPLETE_ACK:
3451                 if (ap->ability_match != 0 &&
3452                     ap->rxconfig == 0) {
3453                         ap->state = ANEG_STATE_AN_ENABLE;
3454                         break;
3455                 }
3456                 delta = ap->cur_time - ap->link_time;
3457                 if (delta > ANEG_STATE_SETTLE_TIME) {
3458                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3459                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3460                         } else {
3461                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3462                                     !(ap->flags & MR_NP_RX)) {
3463                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3464                                 } else {
3465                                         ret = ANEG_FAILED;
3466                                 }
3467                         }
3468                 }
3469                 break;
3470
3471         case ANEG_STATE_IDLE_DETECT_INIT:
3472                 ap->link_time = ap->cur_time;
3473                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3474                 tw32_f(MAC_MODE, tp->mac_mode);
3475                 udelay(40);
3476
3477                 ap->state = ANEG_STATE_IDLE_DETECT;
3478                 ret = ANEG_TIMER_ENAB;
3479                 break;
3480
3481         case ANEG_STATE_IDLE_DETECT:
3482                 if (ap->ability_match != 0 &&
3483                     ap->rxconfig == 0) {
3484                         ap->state = ANEG_STATE_AN_ENABLE;
3485                         break;
3486                 }
3487                 delta = ap->cur_time - ap->link_time;
3488                 if (delta > ANEG_STATE_SETTLE_TIME) {
3489                         /* XXX another gem from the Broadcom driver :( */
3490                         ap->state = ANEG_STATE_LINK_OK;
3491                 }
3492                 break;
3493
3494         case ANEG_STATE_LINK_OK:
3495                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3496                 ret = ANEG_DONE;
3497                 break;
3498
3499         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3500                 /* ??? unimplemented */
3501                 break;
3502
3503         case ANEG_STATE_NEXT_PAGE_WAIT:
3504                 /* ??? unimplemented */
3505                 break;
3506
3507         default:
3508                 ret = ANEG_FAILED;
3509                 break;
3510         }
3511
3512         return ret;
3513 }
3514
3515 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3516 {
3517         int res = 0;
3518         struct tg3_fiber_aneginfo aninfo;
3519         int status = ANEG_FAILED;
3520         unsigned int tick;
3521         u32 tmp;
3522
3523         tw32_f(MAC_TX_AUTO_NEG, 0);
3524
3525         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3526         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3527         udelay(40);
3528
3529         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3530         udelay(40);
3531
3532         memset(&aninfo, 0, sizeof(aninfo));
3533         aninfo.flags |= MR_AN_ENABLE;
3534         aninfo.state = ANEG_STATE_UNKNOWN;
3535         aninfo.cur_time = 0;
3536         tick = 0;
3537         while (++tick < 195000) {
3538                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3539                 if (status == ANEG_DONE || status == ANEG_FAILED)
3540                         break;
3541
3542                 udelay(1);
3543         }
3544
3545         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3546         tw32_f(MAC_MODE, tp->mac_mode);
3547         udelay(40);
3548
3549         *txflags = aninfo.txconfig;
3550         *rxflags = aninfo.flags;
3551
3552         if (status == ANEG_DONE &&
3553             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3554                              MR_LP_ADV_FULL_DUPLEX)))
3555                 res = 1;
3556
3557         return res;
3558 }
3559
3560 static void tg3_init_bcm8002(struct tg3 *tp)
3561 {
3562         u32 mac_status = tr32(MAC_STATUS);
3563         int i;
3564
3565         /* Reset when initting first time or we have a link. */
3566         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3567             !(mac_status & MAC_STATUS_PCS_SYNCED))
3568                 return;
3569
3570         /* Set PLL lock range. */
3571         tg3_writephy(tp, 0x16, 0x8007);
3572
3573         /* SW reset */
3574         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3575
3576         /* Wait for reset to complete. */
3577         /* XXX schedule_timeout() ... */
3578         for (i = 0; i < 500; i++)
3579                 udelay(10);
3580
3581         /* Config mode; select PMA/Ch 1 regs. */
3582         tg3_writephy(tp, 0x10, 0x8411);
3583
3584         /* Enable auto-lock and comdet, select txclk for tx. */
3585         tg3_writephy(tp, 0x11, 0x0a10);
3586
3587         tg3_writephy(tp, 0x18, 0x00a0);
3588         tg3_writephy(tp, 0x16, 0x41ff);
3589
3590         /* Assert and deassert POR. */
3591         tg3_writephy(tp, 0x13, 0x0400);
3592         udelay(40);
3593         tg3_writephy(tp, 0x13, 0x0000);
3594
3595         tg3_writephy(tp, 0x11, 0x0a50);
3596         udelay(40);
3597         tg3_writephy(tp, 0x11, 0x0a10);
3598
3599         /* Wait for signal to stabilize */
3600         /* XXX schedule_timeout() ... */
3601         for (i = 0; i < 15000; i++)
3602                 udelay(10);
3603
3604         /* Deselect the channel register so we can read the PHYID
3605          * later.
3606          */
3607         tg3_writephy(tp, 0x10, 0x8011);
3608 }
3609
3610 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3611 {
3612         u16 flowctrl;
3613         u32 sg_dig_ctrl, sg_dig_status;
3614         u32 serdes_cfg, expected_sg_dig_ctrl;
3615         int workaround, port_a;
3616         int current_link_up;
3617
3618         serdes_cfg = 0;
3619         expected_sg_dig_ctrl = 0;
3620         workaround = 0;
3621         port_a = 1;
3622         current_link_up = 0;
3623
3624         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3625             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3626                 workaround = 1;
3627                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3628                         port_a = 0;
3629
3630                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3631                 /* preserve bits 20-23 for voltage regulator */
3632                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3633         }
3634
3635         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3636
3637         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3638                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3639                         if (workaround) {
3640                                 u32 val = serdes_cfg;
3641
3642                                 if (port_a)
3643                                         val |= 0xc010000;
3644                                 else
3645                                         val |= 0x4010000;
3646                                 tw32_f(MAC_SERDES_CFG, val);
3647                         }
3648
3649                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3650                 }
3651                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3652                         tg3_setup_flow_control(tp, 0, 0);
3653                         current_link_up = 1;
3654                 }
3655                 goto out;
3656         }
3657
3658         /* Want auto-negotiation.  */
3659         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3660
3661         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3662         if (flowctrl & ADVERTISE_1000XPAUSE)
3663                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3664         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3665                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3666
3667         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3668                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3669                     tp->serdes_counter &&
3670                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3671                                     MAC_STATUS_RCVD_CFG)) ==
3672                      MAC_STATUS_PCS_SYNCED)) {
3673                         tp->serdes_counter--;
3674                         current_link_up = 1;
3675                         goto out;
3676                 }
3677 restart_autoneg:
3678                 if (workaround)
3679                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3680                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3681                 udelay(5);
3682                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3683
3684                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3685                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3686         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3687                                  MAC_STATUS_SIGNAL_DET)) {
3688                 sg_dig_status = tr32(SG_DIG_STATUS);
3689                 mac_status = tr32(MAC_STATUS);
3690
3691                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3692                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3693                         u32 local_adv = 0, remote_adv = 0;
3694
3695                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3696                                 local_adv |= ADVERTISE_1000XPAUSE;
3697                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3698                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3699
3700                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3701                                 remote_adv |= LPA_1000XPAUSE;
3702                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3703                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3704
3705                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3706                         current_link_up = 1;
3707                         tp->serdes_counter = 0;
3708                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3709                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3710                         if (tp->serdes_counter)
3711                                 tp->serdes_counter--;
3712                         else {
3713                                 if (workaround) {
3714                                         u32 val = serdes_cfg;
3715
3716                                         if (port_a)
3717                                                 val |= 0xc010000;
3718                                         else
3719                                                 val |= 0x4010000;
3720
3721                                         tw32_f(MAC_SERDES_CFG, val);
3722                                 }
3723
3724                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3725                                 udelay(40);
3726
3727                                 /* Link parallel detection - link is up */
3728                                 /* only if we have PCS_SYNC and not */
3729                                 /* receiving config code words */
3730                                 mac_status = tr32(MAC_STATUS);
3731                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3732                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3733                                         tg3_setup_flow_control(tp, 0, 0);
3734                                         current_link_up = 1;
3735                                         tp->tg3_flags2 |=
3736                                                 TG3_FLG2_PARALLEL_DETECT;
3737                                         tp->serdes_counter =
3738                                                 SERDES_PARALLEL_DET_TIMEOUT;
3739                                 } else
3740                                         goto restart_autoneg;
3741                         }
3742                 }
3743         } else {
3744                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3745                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3746         }
3747
3748 out:
3749         return current_link_up;
3750 }
3751
3752 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3753 {
3754         int current_link_up = 0;
3755
3756         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3757                 goto out;
3758
3759         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3760                 u32 txflags, rxflags;
3761                 int i;
3762
3763                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3764                         u32 local_adv = 0, remote_adv = 0;
3765
3766                         if (txflags & ANEG_CFG_PS1)
3767                                 local_adv |= ADVERTISE_1000XPAUSE;
3768                         if (txflags & ANEG_CFG_PS2)
3769                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3770
3771                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3772                                 remote_adv |= LPA_1000XPAUSE;
3773                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3774                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3775
3776                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3777
3778                         current_link_up = 1;
3779                 }
3780                 for (i = 0; i < 30; i++) {
3781                         udelay(20);
3782                         tw32_f(MAC_STATUS,
3783                                (MAC_STATUS_SYNC_CHANGED |
3784                                 MAC_STATUS_CFG_CHANGED));
3785                         udelay(40);
3786                         if ((tr32(MAC_STATUS) &
3787                              (MAC_STATUS_SYNC_CHANGED |
3788                               MAC_STATUS_CFG_CHANGED)) == 0)
3789                                 break;
3790                 }
3791
3792                 mac_status = tr32(MAC_STATUS);
3793                 if (current_link_up == 0 &&
3794                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3795                     !(mac_status & MAC_STATUS_RCVD_CFG))
3796                         current_link_up = 1;
3797         } else {
3798                 tg3_setup_flow_control(tp, 0, 0);
3799
3800                 /* Forcing 1000FD link up. */
3801                 current_link_up = 1;
3802
3803                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3804                 udelay(40);
3805
3806                 tw32_f(MAC_MODE, tp->mac_mode);
3807                 udelay(40);
3808         }
3809
3810 out:
3811         return current_link_up;
3812 }
3813
3814 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3815 {
3816         u32 orig_pause_cfg;
3817         u16 orig_active_speed;
3818         u8 orig_active_duplex;
3819         u32 mac_status;
3820         int current_link_up;
3821         int i;
3822
3823         orig_pause_cfg = tp->link_config.active_flowctrl;
3824         orig_active_speed = tp->link_config.active_speed;
3825         orig_active_duplex = tp->link_config.active_duplex;
3826
3827         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3828             netif_carrier_ok(tp->dev) &&
3829             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3830                 mac_status = tr32(MAC_STATUS);
3831                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3832                                MAC_STATUS_SIGNAL_DET |
3833                                MAC_STATUS_CFG_CHANGED |
3834                                MAC_STATUS_RCVD_CFG);
3835                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3836                                    MAC_STATUS_SIGNAL_DET)) {
3837                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3838                                             MAC_STATUS_CFG_CHANGED));
3839                         return 0;
3840                 }
3841         }
3842
3843         tw32_f(MAC_TX_AUTO_NEG, 0);
3844
3845         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3846         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3847         tw32_f(MAC_MODE, tp->mac_mode);
3848         udelay(40);
3849
3850         if (tp->phy_id == PHY_ID_BCM8002)
3851                 tg3_init_bcm8002(tp);
3852
3853         /* Enable link change event even when serdes polling.  */
3854         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3855         udelay(40);
3856
3857         current_link_up = 0;
3858         mac_status = tr32(MAC_STATUS);
3859
3860         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3861                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3862         else
3863                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3864
3865         tp->hw_status->status =
3866                 (SD_STATUS_UPDATED |
3867                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3868
3869         for (i = 0; i < 100; i++) {
3870                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3871                                     MAC_STATUS_CFG_CHANGED));
3872                 udelay(5);
3873                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3874                                          MAC_STATUS_CFG_CHANGED |
3875                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3876                         break;
3877         }
3878
3879         mac_status = tr32(MAC_STATUS);
3880         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3881                 current_link_up = 0;
3882                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3883                     tp->serdes_counter == 0) {
3884                         tw32_f(MAC_MODE, (tp->mac_mode |
3885                                           MAC_MODE_SEND_CONFIGS));
3886                         udelay(1);
3887                         tw32_f(MAC_MODE, tp->mac_mode);
3888                 }
3889         }
3890
3891         if (current_link_up == 1) {
3892                 tp->link_config.active_speed = SPEED_1000;
3893                 tp->link_config.active_duplex = DUPLEX_FULL;
3894                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3895                                     LED_CTRL_LNKLED_OVERRIDE |
3896                                     LED_CTRL_1000MBPS_ON));
3897         } else {
3898                 tp->link_config.active_speed = SPEED_INVALID;
3899                 tp->link_config.active_duplex = DUPLEX_INVALID;
3900                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3901                                     LED_CTRL_LNKLED_OVERRIDE |
3902                                     LED_CTRL_TRAFFIC_OVERRIDE));
3903         }
3904
3905         if (current_link_up != netif_carrier_ok(tp->dev)) {
3906                 if (current_link_up)
3907                         netif_carrier_on(tp->dev);
3908                 else
3909                         netif_carrier_off(tp->dev);
3910                 tg3_link_report(tp);
3911         } else {
3912                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3913                 if (orig_pause_cfg != now_pause_cfg ||
3914                     orig_active_speed != tp->link_config.active_speed ||
3915                     orig_active_duplex != tp->link_config.active_duplex)
3916                         tg3_link_report(tp);
3917         }
3918
3919         return 0;
3920 }
3921
3922 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3923 {
3924         int current_link_up, err = 0;
3925         u32 bmsr, bmcr;
3926         u16 current_speed;
3927         u8 current_duplex;
3928         u32 local_adv, remote_adv;
3929
3930         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3931         tw32_f(MAC_MODE, tp->mac_mode);
3932         udelay(40);
3933
3934         tw32(MAC_EVENT, 0);
3935
3936         tw32_f(MAC_STATUS,
3937              (MAC_STATUS_SYNC_CHANGED |
3938               MAC_STATUS_CFG_CHANGED |
3939               MAC_STATUS_MI_COMPLETION |
3940               MAC_STATUS_LNKSTATE_CHANGED));
3941         udelay(40);
3942
3943         if (force_reset)
3944                 tg3_phy_reset(tp);
3945
3946         current_link_up = 0;
3947         current_speed = SPEED_INVALID;
3948         current_duplex = DUPLEX_INVALID;
3949
3950         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3951         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3952         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3953                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3954                         bmsr |= BMSR_LSTATUS;
3955                 else
3956                         bmsr &= ~BMSR_LSTATUS;
3957         }
3958
3959         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3960
3961         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3962             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3963                 /* do nothing, just check for link up at the end */
3964         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3965                 u32 adv, new_adv;
3966
3967                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3968                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3969                                   ADVERTISE_1000XPAUSE |
3970                                   ADVERTISE_1000XPSE_ASYM |
3971                                   ADVERTISE_SLCT);
3972
3973                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3974
3975                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3976                         new_adv |= ADVERTISE_1000XHALF;
3977                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3978                         new_adv |= ADVERTISE_1000XFULL;
3979
3980                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3981                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3982                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3983                         tg3_writephy(tp, MII_BMCR, bmcr);
3984
3985                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3986                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3987                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3988
3989                         return err;
3990                 }
3991         } else {
3992                 u32 new_bmcr;
3993
3994                 bmcr &= ~BMCR_SPEED1000;
3995                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3996
3997                 if (tp->link_config.duplex == DUPLEX_FULL)
3998                         new_bmcr |= BMCR_FULLDPLX;
3999
4000                 if (new_bmcr != bmcr) {
4001                         /* BMCR_SPEED1000 is a reserved bit that needs
4002                          * to be set on write.
4003                          */
4004                         new_bmcr |= BMCR_SPEED1000;
4005
4006                         /* Force a linkdown */
4007                         if (netif_carrier_ok(tp->dev)) {
4008                                 u32 adv;
4009
4010                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4011                                 adv &= ~(ADVERTISE_1000XFULL |
4012                                          ADVERTISE_1000XHALF |
4013                                          ADVERTISE_SLCT);
4014                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4015                                 tg3_writephy(tp, MII_BMCR, bmcr |
4016                                                            BMCR_ANRESTART |
4017                                                            BMCR_ANENABLE);
4018                                 udelay(10);
4019                                 netif_carrier_off(tp->dev);
4020                         }
4021                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4022                         bmcr = new_bmcr;
4023                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4024                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4025                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4026                             ASIC_REV_5714) {
4027                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4028                                         bmsr |= BMSR_LSTATUS;
4029                                 else
4030                                         bmsr &= ~BMSR_LSTATUS;
4031                         }
4032                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4033                 }
4034         }
4035
4036         if (bmsr & BMSR_LSTATUS) {
4037                 current_speed = SPEED_1000;
4038                 current_link_up = 1;
4039                 if (bmcr & BMCR_FULLDPLX)
4040                         current_duplex = DUPLEX_FULL;
4041                 else
4042                         current_duplex = DUPLEX_HALF;
4043
4044                 local_adv = 0;
4045                 remote_adv = 0;
4046
4047                 if (bmcr & BMCR_ANENABLE) {
4048                         u32 common;
4049
4050                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4051                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4052                         common = local_adv & remote_adv;
4053                         if (common & (ADVERTISE_1000XHALF |
4054                                       ADVERTISE_1000XFULL)) {
4055                                 if (common & ADVERTISE_1000XFULL)
4056                                         current_duplex = DUPLEX_FULL;
4057                                 else
4058                                         current_duplex = DUPLEX_HALF;
4059                         }
4060                         else
4061                                 current_link_up = 0;
4062                 }
4063         }
4064
4065         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4066                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4067
4068         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4069         if (tp->link_config.active_duplex == DUPLEX_HALF)
4070                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4071
4072         tw32_f(MAC_MODE, tp->mac_mode);
4073         udelay(40);
4074
4075         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4076
4077         tp->link_config.active_speed = current_speed;
4078         tp->link_config.active_duplex = current_duplex;
4079
4080         if (current_link_up != netif_carrier_ok(tp->dev)) {
4081                 if (current_link_up)
4082                         netif_carrier_on(tp->dev);
4083                 else {
4084                         netif_carrier_off(tp->dev);
4085                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4086                 }
4087                 tg3_link_report(tp);
4088         }
4089         return err;
4090 }
4091
4092 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4093 {
4094         if (tp->serdes_counter) {
4095                 /* Give autoneg time to complete. */
4096                 tp->serdes_counter--;
4097                 return;
4098         }
4099         if (!netif_carrier_ok(tp->dev) &&
4100             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4101                 u32 bmcr;
4102
4103                 tg3_readphy(tp, MII_BMCR, &bmcr);
4104                 if (bmcr & BMCR_ANENABLE) {
4105                         u32 phy1, phy2;
4106
4107                         /* Select shadow register 0x1f */
4108                         tg3_writephy(tp, 0x1c, 0x7c00);
4109                         tg3_readphy(tp, 0x1c, &phy1);
4110
4111                         /* Select expansion interrupt status register */
4112                         tg3_writephy(tp, 0x17, 0x0f01);
4113                         tg3_readphy(tp, 0x15, &phy2);
4114                         tg3_readphy(tp, 0x15, &phy2);
4115
4116                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4117                                 /* We have signal detect and not receiving
4118                                  * config code words, link is up by parallel
4119                                  * detection.
4120                                  */
4121
4122                                 bmcr &= ~BMCR_ANENABLE;
4123                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4124                                 tg3_writephy(tp, MII_BMCR, bmcr);
4125                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4126                         }
4127                 }
4128         }
4129         else if (netif_carrier_ok(tp->dev) &&
4130                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4131                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4132                 u32 phy2;
4133
4134                 /* Select expansion interrupt status register */
4135                 tg3_writephy(tp, 0x17, 0x0f01);
4136                 tg3_readphy(tp, 0x15, &phy2);
4137                 if (phy2 & 0x20) {
4138                         u32 bmcr;
4139
4140                         /* Config code words received, turn on autoneg. */
4141                         tg3_readphy(tp, MII_BMCR, &bmcr);
4142                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4143
4144                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4145
4146                 }
4147         }
4148 }
4149
4150 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4151 {
4152         int err;
4153
4154         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4155                 err = tg3_setup_fiber_phy(tp, force_reset);
4156         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4157                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4158         } else {
4159                 err = tg3_setup_copper_phy(tp, force_reset);
4160         }
4161
4162         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4163                 u32 val, scale;
4164
4165                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4166                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4167                         scale = 65;
4168                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4169                         scale = 6;
4170                 else
4171                         scale = 12;
4172
4173                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4174                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4175                 tw32(GRC_MISC_CFG, val);
4176         }
4177
4178         if (tp->link_config.active_speed == SPEED_1000 &&
4179             tp->link_config.active_duplex == DUPLEX_HALF)
4180                 tw32(MAC_TX_LENGTHS,
4181                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4182                       (6 << TX_LENGTHS_IPG_SHIFT) |
4183                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4184         else
4185                 tw32(MAC_TX_LENGTHS,
4186                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4187                       (6 << TX_LENGTHS_IPG_SHIFT) |
4188                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4189
4190         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4191                 if (netif_carrier_ok(tp->dev)) {
4192                         tw32(HOSTCC_STAT_COAL_TICKS,
4193                              tp->coal.stats_block_coalesce_usecs);
4194                 } else {
4195                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4196                 }
4197         }
4198
4199         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4200                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4201                 if (!netif_carrier_ok(tp->dev))
4202                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4203                               tp->pwrmgmt_thresh;
4204                 else
4205                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4206                 tw32(PCIE_PWR_MGMT_THRESH, val);
4207         }
4208
4209         return err;
4210 }
4211
4212 /* This is called whenever we suspect that the system chipset is re-
4213  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4214  * is bogus tx completions. We try to recover by setting the
4215  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4216  * in the workqueue.
4217  */
4218 static void tg3_tx_recover(struct tg3 *tp)
4219 {
4220         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4221                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4222
4223         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4224                "mapped I/O cycles to the network device, attempting to "
4225                "recover. Please report the problem to the driver maintainer "
4226                "and include system chipset information.\n", tp->dev->name);
4227
4228         spin_lock(&tp->lock);
4229         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4230         spin_unlock(&tp->lock);
4231 }
4232
4233 static inline u32 tg3_tx_avail(struct tg3 *tp)
4234 {
4235         smp_mb();
4236         return (tp->tx_pending -
4237                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4238 }
4239
4240 /* Tigon3 never reports partial packet sends.  So we do not
4241  * need special logic to handle SKBs that have not had all
4242  * of their frags sent yet, like SunGEM does.
4243  */
4244 static void tg3_tx(struct tg3 *tp)
4245 {
4246         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4247         u32 sw_idx = tp->tx_cons;
4248
4249         while (sw_idx != hw_idx) {
4250                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4251                 struct sk_buff *skb = ri->skb;
4252                 int i, tx_bug = 0;
4253
4254                 if (unlikely(skb == NULL)) {
4255                         tg3_tx_recover(tp);
4256                         return;
4257                 }
4258
4259                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4260
4261                 ri->skb = NULL;
4262
4263                 sw_idx = NEXT_TX(sw_idx);
4264
4265                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4266                         ri = &tp->tx_buffers[sw_idx];
4267                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4268                                 tx_bug = 1;
4269                         sw_idx = NEXT_TX(sw_idx);
4270                 }
4271
4272                 dev_kfree_skb(skb);
4273
4274                 if (unlikely(tx_bug)) {
4275                         tg3_tx_recover(tp);
4276                         return;
4277                 }
4278         }
4279
4280         tp->tx_cons = sw_idx;
4281
4282         /* Need to make the tx_cons update visible to tg3_start_xmit()
4283          * before checking for netif_queue_stopped().  Without the
4284          * memory barrier, there is a small possibility that tg3_start_xmit()
4285          * will miss it and cause the queue to be stopped forever.
4286          */
4287         smp_mb();
4288
4289         if (unlikely(netif_queue_stopped(tp->dev) &&
4290                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4291                 netif_tx_lock(tp->dev);
4292                 if (netif_queue_stopped(tp->dev) &&
4293                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4294                         netif_wake_queue(tp->dev);
4295                 netif_tx_unlock(tp->dev);
4296         }
4297 }
4298
4299 /* Returns size of skb allocated or < 0 on error.
4300  *
4301  * We only need to fill in the address because the other members
4302  * of the RX descriptor are invariant, see tg3_init_rings.
4303  *
4304  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4305  * posting buffers we only dirty the first cache line of the RX
4306  * descriptor (containing the address).  Whereas for the RX status
4307  * buffers the cpu only reads the last cacheline of the RX descriptor
4308  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4309  */
4310 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4311                             int src_idx, u32 dest_idx_unmasked)
4312 {
4313         struct tg3_rx_buffer_desc *desc;
4314         struct ring_info *map, *src_map;
4315         struct sk_buff *skb;
4316         dma_addr_t mapping;
4317         int skb_size, dest_idx;
4318
4319         src_map = NULL;
4320         switch (opaque_key) {
4321         case RXD_OPAQUE_RING_STD:
4322                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4323                 desc = &tp->rx_std[dest_idx];
4324                 map = &tp->rx_std_buffers[dest_idx];
4325                 if (src_idx >= 0)
4326                         src_map = &tp->rx_std_buffers[src_idx];
4327                 skb_size = tp->rx_pkt_buf_sz;
4328                 break;
4329
4330         case RXD_OPAQUE_RING_JUMBO:
4331                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4332                 desc = &tp->rx_jumbo[dest_idx];
4333                 map = &tp->rx_jumbo_buffers[dest_idx];
4334                 if (src_idx >= 0)
4335                         src_map = &tp->rx_jumbo_buffers[src_idx];
4336                 skb_size = RX_JUMBO_PKT_BUF_SZ;
4337                 break;
4338
4339         default:
4340                 return -EINVAL;
4341         }
4342
4343         /* Do not overwrite any of the map or rp information
4344          * until we are sure we can commit to a new buffer.
4345          *
4346          * Callers depend upon this behavior and assume that
4347          * we leave everything unchanged if we fail.
4348          */
4349         skb = netdev_alloc_skb(tp->dev, skb_size);
4350         if (skb == NULL)
4351                 return -ENOMEM;
4352
4353         skb_reserve(skb, tp->rx_offset);
4354
4355         mapping = pci_map_single(tp->pdev, skb->data,
4356                                  skb_size - tp->rx_offset,
4357                                  PCI_DMA_FROMDEVICE);
4358
4359         map->skb = skb;
4360         pci_unmap_addr_set(map, mapping, mapping);
4361
4362         if (src_map != NULL)
4363                 src_map->skb = NULL;
4364
4365         desc->addr_hi = ((u64)mapping >> 32);
4366         desc->addr_lo = ((u64)mapping & 0xffffffff);
4367
4368         return skb_size;
4369 }
4370
4371 /* We only need to move over in the address because the other
4372  * members of the RX descriptor are invariant.  See notes above
4373  * tg3_alloc_rx_skb for full details.
4374  */
4375 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4376                            int src_idx, u32 dest_idx_unmasked)
4377 {
4378         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4379         struct ring_info *src_map, *dest_map;
4380         int dest_idx;
4381
4382         switch (opaque_key) {
4383         case RXD_OPAQUE_RING_STD:
4384                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4385                 dest_desc = &tp->rx_std[dest_idx];
4386                 dest_map = &tp->rx_std_buffers[dest_idx];
4387                 src_desc = &tp->rx_std[src_idx];
4388                 src_map = &tp->rx_std_buffers[src_idx];
4389                 break;
4390
4391         case RXD_OPAQUE_RING_JUMBO:
4392                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4393                 dest_desc = &tp->rx_jumbo[dest_idx];
4394                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4395                 src_desc = &tp->rx_jumbo[src_idx];
4396                 src_map = &tp->rx_jumbo_buffers[src_idx];
4397                 break;
4398
4399         default:
4400                 return;
4401         }
4402
4403         dest_map->skb = src_map->skb;
4404         pci_unmap_addr_set(dest_map, mapping,
4405                            pci_unmap_addr(src_map, mapping));
4406         dest_desc->addr_hi = src_desc->addr_hi;
4407         dest_desc->addr_lo = src_desc->addr_lo;
4408
4409         src_map->skb = NULL;
4410 }
4411
4412 #if TG3_VLAN_TAG_USED
4413 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4414 {
4415         return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
4416 }
4417 #endif
4418
4419 /* The RX ring scheme is composed of multiple rings which post fresh
4420  * buffers to the chip, and one special ring the chip uses to report
4421  * status back to the host.
4422  *
4423  * The special ring reports the status of received packets to the
4424  * host.  The chip does not write into the original descriptor the
4425  * RX buffer was obtained from.  The chip simply takes the original
4426  * descriptor as provided by the host, updates the status and length
4427  * field, then writes this into the next status ring entry.
4428  *
4429  * Each ring the host uses to post buffers to the chip is described
4430  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4431  * it is first placed into the on-chip ram.  When the packet's length
4432  * is known, it walks down the TG3_BDINFO entries to select the ring.
4433  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4434  * which is within the range of the new packet's length is chosen.
4435  *
4436  * The "separate ring for rx status" scheme may sound queer, but it makes
4437  * sense from a cache coherency perspective.  If only the host writes
4438  * to the buffer post rings, and only the chip writes to the rx status
4439  * rings, then cache lines never move beyond shared-modified state.
4440  * If both the host and chip were to write into the same ring, cache line
4441  * eviction could occur since both entities want it in an exclusive state.
4442  */
4443 static int tg3_rx(struct tg3 *tp, int budget)
4444 {
4445         u32 work_mask, rx_std_posted = 0;
4446         u32 sw_idx = tp->rx_rcb_ptr;
4447         u16 hw_idx;
4448         int received;
4449
4450         hw_idx = tp->hw_status->idx[0].rx_producer;
4451         /*
4452          * We need to order the read of hw_idx and the read of
4453          * the opaque cookie.
4454          */
4455         rmb();
4456         work_mask = 0;
4457         received = 0;
4458         while (sw_idx != hw_idx && budget > 0) {
4459                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4460                 unsigned int len;
4461                 struct sk_buff *skb;
4462                 dma_addr_t dma_addr;
4463                 u32 opaque_key, desc_idx, *post_ptr;
4464
4465                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4466                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4467                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4468                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4469                                                   mapping);
4470                         skb = tp->rx_std_buffers[desc_idx].skb;
4471                         post_ptr = &tp->rx_std_ptr;
4472                         rx_std_posted++;
4473                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4474                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4475                                                   mapping);
4476                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4477                         post_ptr = &tp->rx_jumbo_ptr;
4478                 }
4479                 else {
4480                         goto next_pkt_nopost;
4481                 }
4482
4483                 work_mask |= opaque_key;
4484
4485                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4486                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4487                 drop_it:
4488                         tg3_recycle_rx(tp, opaque_key,
4489                                        desc_idx, *post_ptr);
4490                 drop_it_no_recycle:
4491                         /* Other statistics kept track of by card. */
4492                         tp->net_stats.rx_dropped++;
4493                         goto next_pkt;
4494                 }
4495
4496                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4497                       ETH_FCS_LEN;
4498
4499                 if (len > RX_COPY_THRESHOLD
4500                         && tp->rx_offset == NET_IP_ALIGN
4501                         /* rx_offset will likely not equal NET_IP_ALIGN
4502                          * if this is a 5701 card running in PCI-X mode
4503                          * [see tg3_get_invariants()]
4504                          */
4505                 ) {
4506                         int skb_size;
4507
4508                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4509                                                     desc_idx, *post_ptr);
4510                         if (skb_size < 0)
4511                                 goto drop_it;
4512
4513                         pci_unmap_single(tp->pdev, dma_addr,
4514                                          skb_size - tp->rx_offset,
4515                                          PCI_DMA_FROMDEVICE);
4516
4517                         skb_put(skb, len);
4518                 } else {
4519                         struct sk_buff *copy_skb;
4520
4521                         tg3_recycle_rx(tp, opaque_key,
4522                                        desc_idx, *post_ptr);
4523
4524                         copy_skb = netdev_alloc_skb(tp->dev,
4525                                                     len + TG3_RAW_IP_ALIGN);
4526                         if (copy_skb == NULL)
4527                                 goto drop_it_no_recycle;
4528
4529                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4530                         skb_put(copy_skb, len);
4531                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4532                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4533                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4534
4535                         /* We'll reuse the original ring buffer. */
4536                         skb = copy_skb;
4537                 }
4538
4539                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4540                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4541                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4542                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4543                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4544                 else
4545                         skb->ip_summed = CHECKSUM_NONE;
4546
4547                 skb->protocol = eth_type_trans(skb, tp->dev);
4548
4549                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4550                     skb->protocol != htons(ETH_P_8021Q)) {
4551                         dev_kfree_skb(skb);
4552                         goto next_pkt;
4553                 }
4554
4555 #if TG3_VLAN_TAG_USED
4556                 if (tp->vlgrp != NULL &&
4557                     desc->type_flags & RXD_FLAG_VLAN) {
4558                         tg3_vlan_rx(tp, skb,
4559                                     desc->err_vlan & RXD_VLAN_MASK);
4560                 } else
4561 #endif
4562                         napi_gro_receive(&tp->napi, skb);
4563
4564                 received++;
4565                 budget--;
4566
4567 next_pkt:
4568                 (*post_ptr)++;
4569
4570                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4571                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4572
4573                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4574                                      TG3_64BIT_REG_LOW, idx);
4575                         work_mask &= ~RXD_OPAQUE_RING_STD;
4576                         rx_std_posted = 0;
4577                 }
4578 next_pkt_nopost:
4579                 sw_idx++;
4580                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4581
4582                 /* Refresh hw_idx to see if there is new work */
4583                 if (sw_idx == hw_idx) {
4584                         hw_idx = tp->hw_status->idx[0].rx_producer;
4585                         rmb();
4586                 }
4587         }
4588
4589         /* ACK the status ring. */
4590         tp->rx_rcb_ptr = sw_idx;
4591         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4592
4593         /* Refill RX ring(s). */
4594         if (work_mask & RXD_OPAQUE_RING_STD) {
4595                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4596                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4597                              sw_idx);
4598         }
4599         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4600                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4601                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4602                              sw_idx);
4603         }
4604         mmiowb();
4605
4606         return received;
4607 }
4608
4609 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4610 {
4611         struct tg3_hw_status *sblk = tp->hw_status;
4612
4613         /* handle link change and other phy events */
4614         if (!(tp->tg3_flags &
4615               (TG3_FLAG_USE_LINKCHG_REG |
4616                TG3_FLAG_POLL_SERDES))) {
4617                 if (sblk->status & SD_STATUS_LINK_CHG) {
4618                         sblk->status = SD_STATUS_UPDATED |
4619                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4620                         spin_lock(&tp->lock);
4621                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4622                                 tw32_f(MAC_STATUS,
4623                                      (MAC_STATUS_SYNC_CHANGED |
4624                                       MAC_STATUS_CFG_CHANGED |
4625                                       MAC_STATUS_MI_COMPLETION |
4626                                       MAC_STATUS_LNKSTATE_CHANGED));
4627                                 udelay(40);
4628                         } else
4629                                 tg3_setup_phy(tp, 0);
4630                         spin_unlock(&tp->lock);
4631                 }
4632         }
4633
4634         /* run TX completion thread */
4635         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4636                 tg3_tx(tp);
4637                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4638                         return work_done;
4639         }
4640
4641         /* run RX thread, within the bounds set by NAPI.
4642          * All RX "locking" is done by ensuring outside
4643          * code synchronizes with tg3->napi.poll()
4644          */
4645         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4646                 work_done += tg3_rx(tp, budget - work_done);
4647
4648         return work_done;
4649 }
4650
4651 static int tg3_poll(struct napi_struct *napi, int budget)
4652 {
4653         struct tg3 *tp = container_of(napi, struct tg3, napi);
4654         int work_done = 0;
4655         struct tg3_hw_status *sblk = tp->hw_status;
4656
4657         while (1) {
4658                 work_done = tg3_poll_work(tp, work_done, budget);
4659
4660                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4661                         goto tx_recovery;
4662
4663                 if (unlikely(work_done >= budget))
4664                         break;
4665
4666                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4667                         /* tp->last_tag is used in tg3_restart_ints() below
4668                          * to tell the hw how much work has been processed,
4669                          * so we must read it before checking for more work.
4670                          */
4671                         tp->last_tag = sblk->status_tag;
4672                         tp->last_irq_tag = tp->last_tag;
4673                         rmb();
4674                 } else
4675                         sblk->status &= ~SD_STATUS_UPDATED;
4676
4677                 if (likely(!tg3_has_work(tp))) {
4678                         napi_complete(napi);
4679                         tg3_restart_ints(tp);
4680                         break;
4681                 }
4682         }
4683
4684         return work_done;
4685
4686 tx_recovery:
4687         /* work_done is guaranteed to be less than budget. */
4688         napi_complete(napi);
4689         schedule_work(&tp->reset_task);
4690         return work_done;
4691 }
4692
4693 static void tg3_irq_quiesce(struct tg3 *tp)
4694 {
4695         BUG_ON(tp->irq_sync);
4696
4697         tp->irq_sync = 1;
4698         smp_mb();
4699
4700         synchronize_irq(tp->pdev->irq);
4701 }
4702
4703 static inline int tg3_irq_sync(struct tg3 *tp)
4704 {
4705         return tp->irq_sync;
4706 }
4707
4708 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4709  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4710  * with as well.  Most of the time, this is not necessary except when
4711  * shutting down the device.
4712  */
4713 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4714 {
4715         spin_lock_bh(&tp->lock);
4716         if (irq_sync)
4717                 tg3_irq_quiesce(tp);
4718 }
4719
4720 static inline void tg3_full_unlock(struct tg3 *tp)
4721 {
4722         spin_unlock_bh(&tp->lock);
4723 }
4724
4725 /* One-shot MSI handler - Chip automatically disables interrupt
4726  * after sending MSI so driver doesn't have to do it.
4727  */
4728 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4729 {
4730         struct net_device *dev = dev_id;
4731         struct tg3 *tp = netdev_priv(dev);
4732
4733         prefetch(tp->hw_status);
4734         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4735
4736         if (likely(!tg3_irq_sync(tp)))
4737                 napi_schedule(&tp->napi);
4738
4739         return IRQ_HANDLED;
4740 }
4741
4742 /* MSI ISR - No need to check for interrupt sharing and no need to
4743  * flush status block and interrupt mailbox. PCI ordering rules
4744  * guarantee that MSI will arrive after the status block.
4745  */
4746 static irqreturn_t tg3_msi(int irq, void *dev_id)
4747 {
4748         struct net_device *dev = dev_id;
4749         struct tg3 *tp = netdev_priv(dev);
4750
4751         prefetch(tp->hw_status);
4752         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4753         /*
4754          * Writing any value to intr-mbox-0 clears PCI INTA# and
4755          * chip-internal interrupt pending events.
4756          * Writing non-zero to intr-mbox-0 additional tells the
4757          * NIC to stop sending us irqs, engaging "in-intr-handler"
4758          * event coalescing.
4759          */
4760         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4761         if (likely(!tg3_irq_sync(tp)))
4762                 napi_schedule(&tp->napi);
4763
4764         return IRQ_RETVAL(1);
4765 }
4766
4767 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4768 {
4769         struct net_device *dev = dev_id;
4770         struct tg3 *tp = netdev_priv(dev);
4771         struct tg3_hw_status *sblk = tp->hw_status;
4772         unsigned int handled = 1;
4773
4774         /* In INTx mode, it is possible for the interrupt to arrive at
4775          * the CPU before the status block posted prior to the interrupt.
4776          * Reading the PCI State register will confirm whether the
4777          * interrupt is ours and will flush the status block.
4778          */
4779         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4780                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4781                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4782                         handled = 0;
4783                         goto out;
4784                 }
4785         }
4786
4787         /*
4788          * Writing any value to intr-mbox-0 clears PCI INTA# and
4789          * chip-internal interrupt pending events.
4790          * Writing non-zero to intr-mbox-0 additional tells the
4791          * NIC to stop sending us irqs, engaging "in-intr-handler"
4792          * event coalescing.
4793          *
4794          * Flush the mailbox to de-assert the IRQ immediately to prevent
4795          * spurious interrupts.  The flush impacts performance but
4796          * excessive spurious interrupts can be worse in some cases.
4797          */
4798         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4799         if (tg3_irq_sync(tp))
4800                 goto out;
4801         sblk->status &= ~SD_STATUS_UPDATED;
4802         if (likely(tg3_has_work(tp))) {
4803                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4804                 napi_schedule(&tp->napi);
4805         } else {
4806                 /* No work, shared interrupt perhaps?  re-enable
4807                  * interrupts, and flush that PCI write
4808                  */
4809                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4810                                0x00000000);
4811         }
4812 out:
4813         return IRQ_RETVAL(handled);
4814 }
4815
4816 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4817 {
4818         struct net_device *dev = dev_id;
4819         struct tg3 *tp = netdev_priv(dev);
4820         struct tg3_hw_status *sblk = tp->hw_status;
4821         unsigned int handled = 1;
4822
4823         /* In INTx mode, it is possible for the interrupt to arrive at
4824          * the CPU before the status block posted prior to the interrupt.
4825          * Reading the PCI State register will confirm whether the
4826          * interrupt is ours and will flush the status block.
4827          */
4828         if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
4829                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4830                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4831                         handled = 0;
4832                         goto out;
4833                 }
4834         }
4835
4836         /*
4837          * writing any value to intr-mbox-0 clears PCI INTA# and
4838          * chip-internal interrupt pending events.
4839          * writing non-zero to intr-mbox-0 additional tells the
4840          * NIC to stop sending us irqs, engaging "in-intr-handler"
4841          * event coalescing.
4842          *
4843          * Flush the mailbox to de-assert the IRQ immediately to prevent
4844          * spurious interrupts.  The flush impacts performance but
4845          * excessive spurious interrupts can be worse in some cases.
4846          */
4847         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4848
4849         /*
4850          * In a shared interrupt configuration, sometimes other devices'
4851          * interrupts will scream.  We record the current status tag here
4852          * so that the above check can report that the screaming interrupts
4853          * are unhandled.  Eventually they will be silenced.
4854          */
4855         tp->last_irq_tag = sblk->status_tag;
4856
4857         if (tg3_irq_sync(tp))
4858                 goto out;
4859
4860         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4861
4862         napi_schedule(&tp->napi);
4863
4864 out:
4865         return IRQ_RETVAL(handled);
4866 }
4867
4868 /* ISR for interrupt test */
4869 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4870 {
4871         struct net_device *dev = dev_id;
4872         struct tg3 *tp = netdev_priv(dev);
4873         struct tg3_hw_status *sblk = tp->hw_status;
4874
4875         if ((sblk->status & SD_STATUS_UPDATED) ||
4876             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4877                 tg3_disable_ints(tp);
4878                 return IRQ_RETVAL(1);
4879         }
4880         return IRQ_RETVAL(0);
4881 }
4882
4883 static int tg3_init_hw(struct tg3 *, int);
4884 static int tg3_halt(struct tg3 *, int, int);
4885
4886 /* Restart hardware after configuration changes, self-test, etc.
4887  * Invoked with tp->lock held.
4888  */
4889 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4890         __releases(tp->lock)
4891         __acquires(tp->lock)
4892 {
4893         int err;
4894
4895         err = tg3_init_hw(tp, reset_phy);
4896         if (err) {
4897                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4898                        "aborting.\n", tp->dev->name);
4899                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4900                 tg3_full_unlock(tp);
4901                 del_timer_sync(&tp->timer);
4902                 tp->irq_sync = 0;
4903                 napi_enable(&tp->napi);
4904                 dev_close(tp->dev);
4905                 tg3_full_lock(tp, 0);
4906         }
4907         return err;
4908 }
4909
4910 #ifdef CONFIG_NET_POLL_CONTROLLER
4911 static void tg3_poll_controller(struct net_device *dev)
4912 {
4913         struct tg3 *tp = netdev_priv(dev);
4914
4915         tg3_interrupt(tp->pdev->irq, dev);
4916 }
4917 #endif
4918
4919 static void tg3_reset_task(struct work_struct *work)
4920 {
4921         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4922         int err;
4923         unsigned int restart_timer;
4924
4925         tg3_full_lock(tp, 0);
4926
4927         if (!netif_running(tp->dev)) {
4928                 tg3_full_unlock(tp);
4929                 return;
4930         }
4931
4932         tg3_full_unlock(tp);
4933
4934         tg3_phy_stop(tp);
4935
4936         tg3_netif_stop(tp);
4937
4938         tg3_full_lock(tp, 1);
4939
4940         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4941         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4942
4943         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4944                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4945                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4946                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4947                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4948         }
4949
4950         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4951         err = tg3_init_hw(tp, 1);
4952         if (err)
4953                 goto out;
4954
4955         tg3_netif_start(tp);
4956
4957         if (restart_timer)
4958                 mod_timer(&tp->timer, jiffies + 1);
4959
4960 out:
4961         tg3_full_unlock(tp);
4962
4963         if (!err)
4964                 tg3_phy_start(tp);
4965 }
4966
4967 static void tg3_dump_short_state(struct tg3 *tp)
4968 {
4969         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4970                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4971         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4972                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4973 }
4974
4975 static void tg3_tx_timeout(struct net_device *dev)
4976 {
4977         struct tg3 *tp = netdev_priv(dev);
4978
4979         if (netif_msg_tx_err(tp)) {
4980                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4981                        dev->name);
4982                 tg3_dump_short_state(tp);
4983         }
4984
4985         schedule_work(&tp->reset_task);
4986 }
4987
4988 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4989 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4990 {
4991         u32 base = (u32) mapping & 0xffffffff;
4992
4993         return ((base > 0xffffdcc0) &&
4994                 (base + len + 8 < base));
4995 }
4996
4997 /* Test for DMA addresses > 40-bit */
4998 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4999                                           int len)
5000 {
5001 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5002         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5003                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5004         return 0;
5005 #else
5006         return 0;
5007 #endif
5008 }
5009
5010 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5011
5012 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5013 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5014                                        u32 last_plus_one, u32 *start,
5015                                        u32 base_flags, u32 mss)
5016 {
5017         struct sk_buff *new_skb;
5018         dma_addr_t new_addr = 0;
5019         u32 entry = *start;
5020         int i, ret = 0;
5021
5022         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5023                 new_skb = skb_copy(skb, GFP_ATOMIC);
5024         else {
5025                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5026
5027                 new_skb = skb_copy_expand(skb,
5028                                           skb_headroom(skb) + more_headroom,
5029                                           skb_tailroom(skb), GFP_ATOMIC);
5030         }
5031
5032         if (!new_skb) {
5033                 ret = -1;
5034         } else {
5035                 /* New SKB is guaranteed to be linear. */
5036                 entry = *start;
5037                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5038                 new_addr = skb_shinfo(new_skb)->dma_head;
5039
5040                 /* Make sure new skb does not cross any 4G boundaries.
5041                  * Drop the packet if it does.
5042                  */
5043                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5044                         if (!ret)
5045                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5046                                               DMA_TO_DEVICE);
5047                         ret = -1;
5048                         dev_kfree_skb(new_skb);
5049                         new_skb = NULL;
5050                 } else {
5051                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
5052                                     base_flags, 1 | (mss << 1));
5053                         *start = NEXT_TX(entry);
5054                 }
5055         }
5056
5057         /* Now clean up the sw ring entries. */
5058         i = 0;
5059         while (entry != last_plus_one) {
5060                 if (i == 0) {
5061                         tp->tx_buffers[entry].skb = new_skb;
5062                 } else {
5063                         tp->tx_buffers[entry].skb = NULL;
5064                 }
5065                 entry = NEXT_TX(entry);
5066                 i++;
5067         }
5068
5069         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5070         dev_kfree_skb(skb);
5071
5072         return ret;
5073 }
5074
5075 static void tg3_set_txd(struct tg3 *tp, int entry,
5076                         dma_addr_t mapping, int len, u32 flags,
5077                         u32 mss_and_is_end)
5078 {
5079         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5080         int is_end = (mss_and_is_end & 0x1);
5081         u32 mss = (mss_and_is_end >> 1);
5082         u32 vlan_tag = 0;
5083
5084         if (is_end)
5085                 flags |= TXD_FLAG_END;
5086         if (flags & TXD_FLAG_VLAN) {
5087                 vlan_tag = flags >> 16;
5088                 flags &= 0xffff;
5089         }
5090         vlan_tag |= (mss << TXD_MSS_SHIFT);
5091
5092         txd->addr_hi = ((u64) mapping >> 32);
5093         txd->addr_lo = ((u64) mapping & 0xffffffff);
5094         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5095         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5096 }
5097
5098 /* hard_start_xmit for devices that don't have any bugs and
5099  * support TG3_FLG2_HW_TSO_2 only.
5100  */
5101 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5102 {
5103         struct tg3 *tp = netdev_priv(dev);
5104         u32 len, entry, base_flags, mss;
5105         struct skb_shared_info *sp;
5106         dma_addr_t mapping;
5107
5108         len = skb_headlen(skb);
5109
5110         /* We are running in BH disabled context with netif_tx_lock
5111          * and TX reclaim runs via tp->napi.poll inside of a software
5112          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5113          * no IRQ context deadlocks to worry about either.  Rejoice!
5114          */
5115         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5116                 if (!netif_queue_stopped(dev)) {
5117                         netif_stop_queue(dev);
5118
5119                         /* This is a hard error, log it. */
5120                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5121                                "queue awake!\n", dev->name);
5122                 }
5123                 return NETDEV_TX_BUSY;
5124         }
5125
5126         entry = tp->tx_prod;
5127         base_flags = 0;
5128         mss = 0;
5129         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5130                 int tcp_opt_len, ip_tcp_len;
5131
5132                 if (skb_header_cloned(skb) &&
5133                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5134                         dev_kfree_skb(skb);
5135                         goto out_unlock;
5136                 }
5137
5138                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5139                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5140                 else {
5141                         struct iphdr *iph = ip_hdr(skb);
5142
5143                         tcp_opt_len = tcp_optlen(skb);
5144                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5145
5146                         iph->check = 0;
5147                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5148                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
5149                 }
5150
5151                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5152                                TXD_FLAG_CPU_POST_DMA);
5153
5154                 tcp_hdr(skb)->check = 0;
5155
5156         }
5157         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5158                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5159 #if TG3_VLAN_TAG_USED
5160         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5161                 base_flags |= (TXD_FLAG_VLAN |
5162                                (vlan_tx_tag_get(skb) << 16));
5163 #endif
5164
5165         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5166                 dev_kfree_skb(skb);
5167                 goto out_unlock;
5168         }
5169
5170         sp = skb_shinfo(skb);
5171
5172         mapping = sp->dma_head;
5173
5174         tp->tx_buffers[entry].skb = skb;
5175
5176         tg3_set_txd(tp, entry, mapping, len, base_flags,
5177                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5178
5179         entry = NEXT_TX(entry);
5180
5181         /* Now loop through additional data fragments, and queue them. */
5182         if (skb_shinfo(skb)->nr_frags > 0) {
5183                 unsigned int i, last;
5184
5185                 last = skb_shinfo(skb)->nr_frags - 1;
5186                 for (i = 0; i <= last; i++) {
5187                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5188
5189                         len = frag->size;
5190                         mapping = sp->dma_maps[i];
5191                         tp->tx_buffers[entry].skb = NULL;
5192
5193                         tg3_set_txd(tp, entry, mapping, len,
5194                                     base_flags, (i == last) | (mss << 1));
5195
5196                         entry = NEXT_TX(entry);
5197                 }
5198         }
5199
5200         /* Packets are ready, update Tx producer idx local and on card. */
5201         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5202
5203         tp->tx_prod = entry;
5204         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5205                 netif_stop_queue(dev);
5206                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5207                         netif_wake_queue(tp->dev);
5208         }
5209
5210 out_unlock:
5211         mmiowb();
5212
5213         return NETDEV_TX_OK;
5214 }
5215
5216 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5217
5218 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5219  * TSO header is greater than 80 bytes.
5220  */
5221 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5222 {
5223         struct sk_buff *segs, *nskb;
5224
5225         /* Estimate the number of fragments in the worst case */
5226         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5227                 netif_stop_queue(tp->dev);
5228                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5229                         return NETDEV_TX_BUSY;
5230
5231                 netif_wake_queue(tp->dev);
5232         }
5233
5234         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5235         if (IS_ERR(segs))
5236                 goto tg3_tso_bug_end;
5237
5238         do {
5239                 nskb = segs;
5240                 segs = segs->next;
5241                 nskb->next = NULL;
5242                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5243         } while (segs);
5244
5245 tg3_tso_bug_end:
5246         dev_kfree_skb(skb);
5247
5248         return NETDEV_TX_OK;
5249 }
5250
5251 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5252  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5253  */
5254 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5255 {
5256         struct tg3 *tp = netdev_priv(dev);
5257         u32 len, entry, base_flags, mss;
5258         struct skb_shared_info *sp;
5259         int would_hit_hwbug;
5260         dma_addr_t mapping;
5261
5262         len = skb_headlen(skb);
5263
5264         /* We are running in BH disabled context with netif_tx_lock
5265          * and TX reclaim runs via tp->napi.poll inside of a software
5266          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5267          * no IRQ context deadlocks to worry about either.  Rejoice!
5268          */
5269         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5270                 if (!netif_queue_stopped(dev)) {
5271                         netif_stop_queue(dev);
5272
5273                         /* This is a hard error, log it. */
5274                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5275                                "queue awake!\n", dev->name);
5276                 }
5277                 return NETDEV_TX_BUSY;
5278         }
5279
5280         entry = tp->tx_prod;
5281         base_flags = 0;
5282         if (skb->ip_summed == CHECKSUM_PARTIAL)
5283                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5284         mss = 0;
5285         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5286                 struct iphdr *iph;
5287                 int tcp_opt_len, ip_tcp_len, hdr_len;
5288
5289                 if (skb_header_cloned(skb) &&
5290                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5291                         dev_kfree_skb(skb);
5292                         goto out_unlock;
5293                 }
5294
5295                 tcp_opt_len = tcp_optlen(skb);
5296                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5297
5298                 hdr_len = ip_tcp_len + tcp_opt_len;
5299                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5300                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5301                         return (tg3_tso_bug(tp, skb));
5302
5303                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5304                                TXD_FLAG_CPU_POST_DMA);
5305
5306                 iph = ip_hdr(skb);
5307                 iph->check = 0;
5308                 iph->tot_len = htons(mss + hdr_len);
5309                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5310                         tcp_hdr(skb)->check = 0;
5311                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5312                 } else
5313                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5314                                                                  iph->daddr, 0,
5315                                                                  IPPROTO_TCP,
5316                                                                  0);
5317
5318                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5319                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5320                         if (tcp_opt_len || iph->ihl > 5) {
5321                                 int tsflags;
5322
5323                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5324                                 mss |= (tsflags << 11);
5325                         }
5326                 } else {
5327                         if (tcp_opt_len || iph->ihl > 5) {
5328                                 int tsflags;
5329
5330                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5331                                 base_flags |= tsflags << 12;
5332                         }
5333                 }
5334         }
5335 #if TG3_VLAN_TAG_USED
5336         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5337                 base_flags |= (TXD_FLAG_VLAN |
5338                                (vlan_tx_tag_get(skb) << 16));
5339 #endif
5340
5341         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5342                 dev_kfree_skb(skb);
5343                 goto out_unlock;
5344         }
5345
5346         sp = skb_shinfo(skb);
5347
5348         mapping = sp->dma_head;
5349
5350         tp->tx_buffers[entry].skb = skb;
5351
5352         would_hit_hwbug = 0;
5353
5354         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5355                 would_hit_hwbug = 1;
5356         else if (tg3_4g_overflow_test(mapping, len))
5357                 would_hit_hwbug = 1;
5358
5359         tg3_set_txd(tp, entry, mapping, len, base_flags,
5360                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5361
5362         entry = NEXT_TX(entry);
5363
5364         /* Now loop through additional data fragments, and queue them. */
5365         if (skb_shinfo(skb)->nr_frags > 0) {
5366                 unsigned int i, last;
5367
5368                 last = skb_shinfo(skb)->nr_frags - 1;
5369                 for (i = 0; i <= last; i++) {
5370                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5371
5372                         len = frag->size;
5373                         mapping = sp->dma_maps[i];
5374
5375                         tp->tx_buffers[entry].skb = NULL;
5376
5377                         if (tg3_4g_overflow_test(mapping, len))
5378                                 would_hit_hwbug = 1;
5379
5380                         if (tg3_40bit_overflow_test(tp, mapping, len))
5381                                 would_hit_hwbug = 1;
5382
5383                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5384                                 tg3_set_txd(tp, entry, mapping, len,
5385                                             base_flags, (i == last)|(mss << 1));
5386                         else
5387                                 tg3_set_txd(tp, entry, mapping, len,
5388                                             base_flags, (i == last));
5389
5390                         entry = NEXT_TX(entry);
5391                 }
5392         }
5393
5394         if (would_hit_hwbug) {
5395                 u32 last_plus_one = entry;
5396                 u32 start;
5397
5398                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5399                 start &= (TG3_TX_RING_SIZE - 1);
5400
5401                 /* If the workaround fails due to memory/mapping
5402                  * failure, silently drop this packet.
5403                  */
5404                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5405                                                 &start, base_flags, mss))
5406                         goto out_unlock;
5407
5408                 entry = start;
5409         }
5410
5411         /* Packets are ready, update Tx producer idx local and on card. */
5412         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5413
5414         tp->tx_prod = entry;
5415         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5416                 netif_stop_queue(dev);
5417                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5418                         netif_wake_queue(tp->dev);
5419         }
5420
5421 out_unlock:
5422         mmiowb();
5423
5424         return NETDEV_TX_OK;
5425 }
5426
5427 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5428                                int new_mtu)
5429 {
5430         dev->mtu = new_mtu;
5431
5432         if (new_mtu > ETH_DATA_LEN) {
5433                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5434                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5435                         ethtool_op_set_tso(dev, 0);
5436                 }
5437                 else
5438                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5439         } else {
5440                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5441                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5442                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5443         }
5444 }
5445
5446 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5447 {
5448         struct tg3 *tp = netdev_priv(dev);
5449         int err;
5450
5451         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5452                 return -EINVAL;
5453
5454         if (!netif_running(dev)) {
5455                 /* We'll just catch it later when the
5456                  * device is up'd.
5457                  */
5458                 tg3_set_mtu(dev, tp, new_mtu);
5459                 return 0;
5460         }
5461
5462         tg3_phy_stop(tp);
5463
5464         tg3_netif_stop(tp);
5465
5466         tg3_full_lock(tp, 1);
5467
5468         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5469
5470         tg3_set_mtu(dev, tp, new_mtu);
5471
5472         err = tg3_restart_hw(tp, 0);
5473
5474         if (!err)
5475                 tg3_netif_start(tp);
5476
5477         tg3_full_unlock(tp);
5478
5479         if (!err)
5480                 tg3_phy_start(tp);
5481
5482         return err;
5483 }
5484
5485 /* Free up pending packets in all rx/tx rings.
5486  *
5487  * The chip has been shut down and the driver detached from
5488  * the networking, so no interrupts or new tx packets will
5489  * end up in the driver.  tp->{tx,}lock is not held and we are not
5490  * in an interrupt context and thus may sleep.
5491  */
5492 static void tg3_free_rings(struct tg3 *tp)
5493 {
5494         struct ring_info *rxp;
5495         int i;
5496
5497         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5498                 rxp = &tp->rx_std_buffers[i];
5499
5500                 if (rxp->skb == NULL)
5501                         continue;
5502                 pci_unmap_single(tp->pdev,
5503                                  pci_unmap_addr(rxp, mapping),
5504                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5505                                  PCI_DMA_FROMDEVICE);
5506                 dev_kfree_skb_any(rxp->skb);
5507                 rxp->skb = NULL;
5508         }
5509
5510         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5511                 rxp = &tp->rx_jumbo_buffers[i];
5512
5513                 if (rxp->skb == NULL)
5514                         continue;
5515                 pci_unmap_single(tp->pdev,
5516                                  pci_unmap_addr(rxp, mapping),
5517                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5518                                  PCI_DMA_FROMDEVICE);
5519                 dev_kfree_skb_any(rxp->skb);
5520                 rxp->skb = NULL;
5521         }
5522
5523         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5524                 struct tx_ring_info *txp;
5525                 struct sk_buff *skb;
5526
5527                 txp = &tp->tx_buffers[i];
5528                 skb = txp->skb;
5529
5530                 if (skb == NULL) {
5531                         i++;
5532                         continue;
5533                 }
5534
5535                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5536
5537                 txp->skb = NULL;
5538
5539                 i += skb_shinfo(skb)->nr_frags + 1;
5540
5541                 dev_kfree_skb_any(skb);
5542         }
5543 }
5544
5545 /* Initialize tx/rx rings for packet processing.
5546  *
5547  * The chip has been shut down and the driver detached from
5548  * the networking, so no interrupts or new tx packets will
5549  * end up in the driver.  tp->{tx,}lock are held and thus
5550  * we may not sleep.
5551  */
5552 static int tg3_init_rings(struct tg3 *tp)
5553 {
5554         u32 i;
5555
5556         /* Free up all the SKBs. */
5557         tg3_free_rings(tp);
5558
5559         /* Zero out all descriptors. */
5560         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5561         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5562         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5563         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5564
5565         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5566         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5567             (tp->dev->mtu > ETH_DATA_LEN))
5568                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5569
5570         /* Initialize invariants of the rings, we only set this
5571          * stuff once.  This works because the card does not
5572          * write into the rx buffer posting rings.
5573          */
5574         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5575                 struct tg3_rx_buffer_desc *rxd;
5576
5577                 rxd = &tp->rx_std[i];
5578                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5579                         << RXD_LEN_SHIFT;
5580                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5581                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5582                                (i << RXD_OPAQUE_INDEX_SHIFT));
5583         }
5584
5585         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5586                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5587                         struct tg3_rx_buffer_desc *rxd;
5588
5589                         rxd = &tp->rx_jumbo[i];
5590                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5591                                 << RXD_LEN_SHIFT;
5592                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5593                                 RXD_FLAG_JUMBO;
5594                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5595                                (i << RXD_OPAQUE_INDEX_SHIFT));
5596                 }
5597         }
5598
5599         /* Now allocate fresh SKBs for each rx ring. */
5600         for (i = 0; i < tp->rx_pending; i++) {
5601                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5602                         printk(KERN_WARNING PFX
5603                                "%s: Using a smaller RX standard ring, "
5604                                "only %d out of %d buffers were allocated "
5605                                "successfully.\n",
5606                                tp->dev->name, i, tp->rx_pending);
5607                         if (i == 0)
5608                                 return -ENOMEM;
5609                         tp->rx_pending = i;
5610                         break;
5611                 }
5612         }
5613
5614         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5615                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5616                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5617                                              -1, i) < 0) {
5618                                 printk(KERN_WARNING PFX
5619                                        "%s: Using a smaller RX jumbo ring, "
5620                                        "only %d out of %d buffers were "
5621                                        "allocated successfully.\n",
5622                                        tp->dev->name, i, tp->rx_jumbo_pending);
5623                                 if (i == 0) {
5624                                         tg3_free_rings(tp);
5625                                         return -ENOMEM;
5626                                 }
5627                                 tp->rx_jumbo_pending = i;
5628                                 break;
5629                         }
5630                 }
5631         }
5632         return 0;
5633 }
5634
5635 /*
5636  * Must not be invoked with interrupt sources disabled and
5637  * the hardware shutdown down.
5638  */
5639 static void tg3_free_consistent(struct tg3 *tp)
5640 {
5641         kfree(tp->rx_std_buffers);
5642         tp->rx_std_buffers = NULL;
5643         if (tp->rx_std) {
5644                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5645                                     tp->rx_std, tp->rx_std_mapping);
5646                 tp->rx_std = NULL;
5647         }
5648         if (tp->rx_jumbo) {
5649                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5650                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5651                 tp->rx_jumbo = NULL;
5652         }
5653         if (tp->rx_rcb) {
5654                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5655                                     tp->rx_rcb, tp->rx_rcb_mapping);
5656                 tp->rx_rcb = NULL;
5657         }
5658         if (tp->tx_ring) {
5659                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5660                         tp->tx_ring, tp->tx_desc_mapping);
5661                 tp->tx_ring = NULL;
5662         }
5663         if (tp->hw_status) {
5664                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5665                                     tp->hw_status, tp->status_mapping);
5666                 tp->hw_status = NULL;
5667         }
5668         if (tp->hw_stats) {
5669                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5670                                     tp->hw_stats, tp->stats_mapping);
5671                 tp->hw_stats = NULL;
5672         }
5673 }
5674
5675 /*
5676  * Must not be invoked with interrupt sources disabled and
5677  * the hardware shutdown down.  Can sleep.
5678  */
5679 static int tg3_alloc_consistent(struct tg3 *tp)
5680 {
5681         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5682                                       (TG3_RX_RING_SIZE +
5683                                        TG3_RX_JUMBO_RING_SIZE)) +
5684                                      (sizeof(struct tx_ring_info) *
5685                                       TG3_TX_RING_SIZE),
5686                                      GFP_KERNEL);
5687         if (!tp->rx_std_buffers)
5688                 return -ENOMEM;
5689
5690         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5691         tp->tx_buffers = (struct tx_ring_info *)
5692                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5693
5694         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5695                                           &tp->rx_std_mapping);
5696         if (!tp->rx_std)
5697                 goto err_out;
5698
5699         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5700                                             &tp->rx_jumbo_mapping);
5701
5702         if (!tp->rx_jumbo)
5703                 goto err_out;
5704
5705         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5706                                           &tp->rx_rcb_mapping);
5707         if (!tp->rx_rcb)
5708                 goto err_out;
5709
5710         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5711                                            &tp->tx_desc_mapping);
5712         if (!tp->tx_ring)
5713                 goto err_out;
5714
5715         tp->hw_status = pci_alloc_consistent(tp->pdev,
5716                                              TG3_HW_STATUS_SIZE,
5717                                              &tp->status_mapping);
5718         if (!tp->hw_status)
5719                 goto err_out;
5720
5721         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5722                                             sizeof(struct tg3_hw_stats),
5723                                             &tp->stats_mapping);
5724         if (!tp->hw_stats)
5725                 goto err_out;
5726
5727         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5728         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5729
5730         return 0;
5731
5732 err_out:
5733         tg3_free_consistent(tp);
5734         return -ENOMEM;
5735 }
5736
5737 #define MAX_WAIT_CNT 1000
5738
5739 /* To stop a block, clear the enable bit and poll till it
5740  * clears.  tp->lock is held.
5741  */
5742 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5743 {
5744         unsigned int i;
5745         u32 val;
5746
5747         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5748                 switch (ofs) {
5749                 case RCVLSC_MODE:
5750                 case DMAC_MODE:
5751                 case MBFREE_MODE:
5752                 case BUFMGR_MODE:
5753                 case MEMARB_MODE:
5754                         /* We can't enable/disable these bits of the
5755                          * 5705/5750, just say success.
5756                          */
5757                         return 0;
5758
5759                 default:
5760                         break;
5761                 }
5762         }
5763
5764         val = tr32(ofs);
5765         val &= ~enable_bit;
5766         tw32_f(ofs, val);
5767
5768         for (i = 0; i < MAX_WAIT_CNT; i++) {
5769                 udelay(100);
5770                 val = tr32(ofs);
5771                 if ((val & enable_bit) == 0)
5772                         break;
5773         }
5774
5775         if (i == MAX_WAIT_CNT && !silent) {
5776                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5777                        "ofs=%lx enable_bit=%x\n",
5778                        ofs, enable_bit);
5779                 return -ENODEV;
5780         }
5781
5782         return 0;
5783 }
5784
5785 /* tp->lock is held. */
5786 static int tg3_abort_hw(struct tg3 *tp, int silent)
5787 {
5788         int i, err;
5789
5790         tg3_disable_ints(tp);
5791
5792         tp->rx_mode &= ~RX_MODE_ENABLE;
5793         tw32_f(MAC_RX_MODE, tp->rx_mode);
5794         udelay(10);
5795
5796         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5797         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5798         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5799         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5800         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5801         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5802
5803         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5804         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5805         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5806         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5807         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5808         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5809         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5810
5811         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5812         tw32_f(MAC_MODE, tp->mac_mode);
5813         udelay(40);
5814
5815         tp->tx_mode &= ~TX_MODE_ENABLE;
5816         tw32_f(MAC_TX_MODE, tp->tx_mode);
5817
5818         for (i = 0; i < MAX_WAIT_CNT; i++) {
5819                 udelay(100);
5820                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5821                         break;
5822         }
5823         if (i >= MAX_WAIT_CNT) {
5824                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5825                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5826                        tp->dev->name, tr32(MAC_TX_MODE));
5827                 err |= -ENODEV;
5828         }
5829
5830         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5831         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5832         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5833
5834         tw32(FTQ_RESET, 0xffffffff);
5835         tw32(FTQ_RESET, 0x00000000);
5836
5837         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5838         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5839
5840         if (tp->hw_status)
5841                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5842         if (tp->hw_stats)
5843                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5844
5845         return err;
5846 }
5847
5848 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5849 {
5850         int i;
5851         u32 apedata;
5852
5853         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5854         if (apedata != APE_SEG_SIG_MAGIC)
5855                 return;
5856
5857         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5858         if (!(apedata & APE_FW_STATUS_READY))
5859                 return;
5860
5861         /* Wait for up to 1 millisecond for APE to service previous event. */
5862         for (i = 0; i < 10; i++) {
5863                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5864                         return;
5865
5866                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5867
5868                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5869                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5870                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5871
5872                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5873
5874                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5875                         break;
5876
5877                 udelay(100);
5878         }
5879
5880         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5881                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5882 }
5883
5884 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5885 {
5886         u32 event;
5887         u32 apedata;
5888
5889         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5890                 return;
5891
5892         switch (kind) {
5893                 case RESET_KIND_INIT:
5894                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5895                                         APE_HOST_SEG_SIG_MAGIC);
5896                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5897                                         APE_HOST_SEG_LEN_MAGIC);
5898                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5899                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5900                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5901                                         APE_HOST_DRIVER_ID_MAGIC);
5902                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5903                                         APE_HOST_BEHAV_NO_PHYLOCK);
5904
5905                         event = APE_EVENT_STATUS_STATE_START;
5906                         break;
5907                 case RESET_KIND_SHUTDOWN:
5908                         /* With the interface we are currently using,
5909                          * APE does not track driver state.  Wiping
5910                          * out the HOST SEGMENT SIGNATURE forces
5911                          * the APE to assume OS absent status.
5912                          */
5913                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5914
5915                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5916                         break;
5917                 case RESET_KIND_SUSPEND:
5918                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5919                         break;
5920                 default:
5921                         return;
5922         }
5923
5924         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5925
5926         tg3_ape_send_event(tp, event);
5927 }
5928
5929 /* tp->lock is held. */
5930 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5931 {
5932         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5933                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5934
5935         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5936                 switch (kind) {
5937                 case RESET_KIND_INIT:
5938                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5939                                       DRV_STATE_START);
5940                         break;
5941
5942                 case RESET_KIND_SHUTDOWN:
5943                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5944                                       DRV_STATE_UNLOAD);
5945                         break;
5946
5947                 case RESET_KIND_SUSPEND:
5948                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5949                                       DRV_STATE_SUSPEND);
5950                         break;
5951
5952                 default:
5953                         break;
5954                 }
5955         }
5956
5957         if (kind == RESET_KIND_INIT ||
5958             kind == RESET_KIND_SUSPEND)
5959                 tg3_ape_driver_state_change(tp, kind);
5960 }
5961
5962 /* tp->lock is held. */
5963 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5964 {
5965         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5966                 switch (kind) {
5967                 case RESET_KIND_INIT:
5968                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5969                                       DRV_STATE_START_DONE);
5970                         break;
5971
5972                 case RESET_KIND_SHUTDOWN:
5973                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5974                                       DRV_STATE_UNLOAD_DONE);
5975                         break;
5976
5977                 default:
5978                         break;
5979                 }
5980         }
5981
5982         if (kind == RESET_KIND_SHUTDOWN)
5983                 tg3_ape_driver_state_change(tp, kind);
5984 }
5985
5986 /* tp->lock is held. */
5987 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5988 {
5989         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5990                 switch (kind) {
5991                 case RESET_KIND_INIT:
5992                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5993                                       DRV_STATE_START);
5994                         break;
5995
5996                 case RESET_KIND_SHUTDOWN:
5997                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5998                                       DRV_STATE_UNLOAD);
5999                         break;
6000
6001                 case RESET_KIND_SUSPEND:
6002                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6003                                       DRV_STATE_SUSPEND);
6004                         break;
6005
6006                 default:
6007                         break;
6008                 }
6009         }
6010 }
6011
6012 static int tg3_poll_fw(struct tg3 *tp)
6013 {
6014         int i;
6015         u32 val;
6016
6017         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6018                 /* Wait up to 20ms for init done. */
6019                 for (i = 0; i < 200; i++) {
6020                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6021                                 return 0;
6022                         udelay(100);
6023                 }
6024                 return -ENODEV;
6025         }
6026
6027         /* Wait for firmware initialization to complete. */
6028         for (i = 0; i < 100000; i++) {
6029                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6030                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6031                         break;
6032                 udelay(10);
6033         }
6034
6035         /* Chip might not be fitted with firmware.  Some Sun onboard
6036          * parts are configured like that.  So don't signal the timeout
6037          * of the above loop as an error, but do report the lack of
6038          * running firmware once.
6039          */
6040         if (i >= 100000 &&
6041             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6042                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6043
6044                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6045                        tp->dev->name);
6046         }
6047
6048         return 0;
6049 }
6050
6051 /* Save PCI command register before chip reset */
6052 static void tg3_save_pci_state(struct tg3 *tp)
6053 {
6054         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6055 }
6056
6057 /* Restore PCI state after chip reset */
6058 static void tg3_restore_pci_state(struct tg3 *tp)
6059 {
6060         u32 val;
6061
6062         /* Re-enable indirect register accesses. */
6063         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6064                                tp->misc_host_ctrl);
6065
6066         /* Set MAX PCI retry to zero. */
6067         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6068         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6069             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6070                 val |= PCISTATE_RETRY_SAME_DMA;
6071         /* Allow reads and writes to the APE register and memory space. */
6072         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6073                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6074                        PCISTATE_ALLOW_APE_SHMEM_WR;
6075         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6076
6077         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6078
6079         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6080                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6081                         pcie_set_readrq(tp->pdev, 4096);
6082                 else {
6083                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6084                                               tp->pci_cacheline_sz);
6085                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6086                                               tp->pci_lat_timer);
6087                 }
6088         }
6089
6090         /* Make sure PCI-X relaxed ordering bit is clear. */
6091         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6092                 u16 pcix_cmd;
6093
6094                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6095                                      &pcix_cmd);
6096                 pcix_cmd &= ~PCI_X_CMD_ERO;
6097                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6098                                       pcix_cmd);
6099         }
6100
6101         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6102
6103                 /* Chip reset on 5780 will reset MSI enable bit,
6104                  * so need to restore it.
6105                  */
6106                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6107                         u16 ctrl;
6108
6109                         pci_read_config_word(tp->pdev,
6110                                              tp->msi_cap + PCI_MSI_FLAGS,
6111                                              &ctrl);
6112                         pci_write_config_word(tp->pdev,
6113                                               tp->msi_cap + PCI_MSI_FLAGS,
6114                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6115                         val = tr32(MSGINT_MODE);
6116                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6117                 }
6118         }
6119 }
6120
6121 static void tg3_stop_fw(struct tg3 *);
6122
6123 /* tp->lock is held. */
6124 static int tg3_chip_reset(struct tg3 *tp)
6125 {
6126         u32 val;
6127         void (*write_op)(struct tg3 *, u32, u32);
6128         int err;
6129
6130         tg3_nvram_lock(tp);
6131
6132         tg3_mdio_stop(tp);
6133
6134         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6135
6136         /* No matching tg3_nvram_unlock() after this because
6137          * chip reset below will undo the nvram lock.
6138          */
6139         tp->nvram_lock_cnt = 0;
6140
6141         /* GRC_MISC_CFG core clock reset will clear the memory
6142          * enable bit in PCI register 4 and the MSI enable bit
6143          * on some chips, so we save relevant registers here.
6144          */
6145         tg3_save_pci_state(tp);
6146
6147         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6148             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6149                 tw32(GRC_FASTBOOT_PC, 0);
6150
6151         /*
6152          * We must avoid the readl() that normally takes place.
6153          * It locks machines, causes machine checks, and other
6154          * fun things.  So, temporarily disable the 5701
6155          * hardware workaround, while we do the reset.
6156          */
6157         write_op = tp->write32;
6158         if (write_op == tg3_write_flush_reg32)
6159                 tp->write32 = tg3_write32;
6160
6161         /* Prevent the irq handler from reading or writing PCI registers
6162          * during chip reset when the memory enable bit in the PCI command
6163          * register may be cleared.  The chip does not generate interrupt
6164          * at this time, but the irq handler may still be called due to irq
6165          * sharing or irqpoll.
6166          */
6167         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6168         if (tp->hw_status) {
6169                 tp->hw_status->status = 0;
6170                 tp->hw_status->status_tag = 0;
6171         }
6172         tp->last_tag = 0;
6173         tp->last_irq_tag = 0;
6174         smp_mb();
6175         synchronize_irq(tp->pdev->irq);
6176
6177         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6178                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6179                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6180         }
6181
6182         /* do the reset */
6183         val = GRC_MISC_CFG_CORECLK_RESET;
6184
6185         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6186                 if (tr32(0x7e2c) == 0x60) {
6187                         tw32(0x7e2c, 0x20);
6188                 }
6189                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6190                         tw32(GRC_MISC_CFG, (1 << 29));
6191                         val |= (1 << 29);
6192                 }
6193         }
6194
6195         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6196                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6197                 tw32(GRC_VCPU_EXT_CTRL,
6198                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6199         }
6200
6201         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6202                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6203         tw32(GRC_MISC_CFG, val);
6204
6205         /* restore 5701 hardware bug workaround write method */
6206         tp->write32 = write_op;
6207
6208         /* Unfortunately, we have to delay before the PCI read back.
6209          * Some 575X chips even will not respond to a PCI cfg access
6210          * when the reset command is given to the chip.
6211          *
6212          * How do these hardware designers expect things to work
6213          * properly if the PCI write is posted for a long period
6214          * of time?  It is always necessary to have some method by
6215          * which a register read back can occur to push the write
6216          * out which does the reset.
6217          *
6218          * For most tg3 variants the trick below was working.
6219          * Ho hum...
6220          */
6221         udelay(120);
6222
6223         /* Flush PCI posted writes.  The normal MMIO registers
6224          * are inaccessible at this time so this is the only
6225          * way to make this reliably (actually, this is no longer
6226          * the case, see above).  I tried to use indirect
6227          * register read/write but this upset some 5701 variants.
6228          */
6229         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6230
6231         udelay(120);
6232
6233         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6234                 u16 val16;
6235
6236                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6237                         int i;
6238                         u32 cfg_val;
6239
6240                         /* Wait for link training to complete.  */
6241                         for (i = 0; i < 5000; i++)
6242                                 udelay(100);
6243
6244                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6245                         pci_write_config_dword(tp->pdev, 0xc4,
6246                                                cfg_val | (1 << 15));
6247                 }
6248
6249                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6250                 pci_read_config_word(tp->pdev,
6251                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6252                                      &val16);
6253                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6254                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6255                 /*
6256                  * Older PCIe devices only support the 128 byte
6257                  * MPS setting.  Enforce the restriction.
6258                  */
6259                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6260                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6261                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6262                 pci_write_config_word(tp->pdev,
6263                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6264                                       val16);
6265
6266                 pcie_set_readrq(tp->pdev, 4096);
6267
6268                 /* Clear error status */
6269                 pci_write_config_word(tp->pdev,
6270                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6271                                       PCI_EXP_DEVSTA_CED |
6272                                       PCI_EXP_DEVSTA_NFED |
6273                                       PCI_EXP_DEVSTA_FED |
6274                                       PCI_EXP_DEVSTA_URD);
6275         }
6276
6277         tg3_restore_pci_state(tp);
6278
6279         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6280
6281         val = 0;
6282         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6283                 val = tr32(MEMARB_MODE);
6284         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6285
6286         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6287                 tg3_stop_fw(tp);
6288                 tw32(0x5000, 0x400);
6289         }
6290
6291         tw32(GRC_MODE, tp->grc_mode);
6292
6293         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6294                 val = tr32(0xc4);
6295
6296                 tw32(0xc4, val | (1 << 15));
6297         }
6298
6299         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6300             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6301                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6302                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6303                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6304                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6305         }
6306
6307         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6308                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6309                 tw32_f(MAC_MODE, tp->mac_mode);
6310         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6311                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6312                 tw32_f(MAC_MODE, tp->mac_mode);
6313         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6314                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6315                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6316                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6317                 tw32_f(MAC_MODE, tp->mac_mode);
6318         } else
6319                 tw32_f(MAC_MODE, 0);
6320         udelay(40);
6321
6322         tg3_mdio_start(tp);
6323
6324         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6325
6326         err = tg3_poll_fw(tp);
6327         if (err)
6328                 return err;
6329
6330         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6331             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6332                 val = tr32(0x7c00);
6333
6334                 tw32(0x7c00, val | (1 << 25));
6335         }
6336
6337         /* Reprobe ASF enable state.  */
6338         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6339         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6340         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6341         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6342                 u32 nic_cfg;
6343
6344                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6345                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6346                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6347                         tp->last_event_jiffies = jiffies;
6348                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6349                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6350                 }
6351         }
6352
6353         return 0;
6354 }
6355
6356 /* tp->lock is held. */
6357 static void tg3_stop_fw(struct tg3 *tp)
6358 {
6359         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6360            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6361                 /* Wait for RX cpu to ACK the previous event. */
6362                 tg3_wait_for_event_ack(tp);
6363
6364                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6365
6366                 tg3_generate_fw_event(tp);
6367
6368                 /* Wait for RX cpu to ACK this event. */
6369                 tg3_wait_for_event_ack(tp);
6370         }
6371 }
6372
6373 /* tp->lock is held. */
6374 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6375 {
6376         int err;
6377
6378         tg3_stop_fw(tp);
6379
6380         tg3_write_sig_pre_reset(tp, kind);
6381
6382         tg3_abort_hw(tp, silent);
6383         err = tg3_chip_reset(tp);
6384
6385         __tg3_set_mac_addr(tp, 0);
6386
6387         tg3_write_sig_legacy(tp, kind);
6388         tg3_write_sig_post_reset(tp, kind);
6389
6390         if (err)
6391                 return err;
6392
6393         return 0;
6394 }
6395
6396 #define RX_CPU_SCRATCH_BASE     0x30000
6397 #define RX_CPU_SCRATCH_SIZE     0x04000
6398 #define TX_CPU_SCRATCH_BASE     0x34000
6399 #define TX_CPU_SCRATCH_SIZE     0x04000
6400
6401 /* tp->lock is held. */
6402 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6403 {
6404         int i;
6405
6406         BUG_ON(offset == TX_CPU_BASE &&
6407             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6408
6409         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6410                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6411
6412                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6413                 return 0;
6414         }
6415         if (offset == RX_CPU_BASE) {
6416                 for (i = 0; i < 10000; i++) {
6417                         tw32(offset + CPU_STATE, 0xffffffff);
6418                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6419                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6420                                 break;
6421                 }
6422
6423                 tw32(offset + CPU_STATE, 0xffffffff);
6424                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6425                 udelay(10);
6426         } else {
6427                 for (i = 0; i < 10000; i++) {
6428                         tw32(offset + CPU_STATE, 0xffffffff);
6429                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6430                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6431                                 break;
6432                 }
6433         }
6434
6435         if (i >= 10000) {
6436                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6437                        "and %s CPU\n",
6438                        tp->dev->name,
6439                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6440                 return -ENODEV;
6441         }
6442
6443         /* Clear firmware's nvram arbitration. */
6444         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6445                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6446         return 0;
6447 }
6448
6449 struct fw_info {
6450         unsigned int fw_base;
6451         unsigned int fw_len;
6452         const __be32 *fw_data;
6453 };
6454
6455 /* tp->lock is held. */
6456 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6457                                  int cpu_scratch_size, struct fw_info *info)
6458 {
6459         int err, lock_err, i;
6460         void (*write_op)(struct tg3 *, u32, u32);
6461
6462         if (cpu_base == TX_CPU_BASE &&
6463             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6464                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6465                        "TX cpu firmware on %s which is 5705.\n",
6466                        tp->dev->name);
6467                 return -EINVAL;
6468         }
6469
6470         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6471                 write_op = tg3_write_mem;
6472         else
6473                 write_op = tg3_write_indirect_reg32;
6474
6475         /* It is possible that bootcode is still loading at this point.
6476          * Get the nvram lock first before halting the cpu.
6477          */
6478         lock_err = tg3_nvram_lock(tp);
6479         err = tg3_halt_cpu(tp, cpu_base);
6480         if (!lock_err)
6481                 tg3_nvram_unlock(tp);
6482         if (err)
6483                 goto out;
6484
6485         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6486                 write_op(tp, cpu_scratch_base + i, 0);
6487         tw32(cpu_base + CPU_STATE, 0xffffffff);
6488         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6489         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6490                 write_op(tp, (cpu_scratch_base +
6491                               (info->fw_base & 0xffff) +
6492                               (i * sizeof(u32))),
6493                               be32_to_cpu(info->fw_data[i]));
6494
6495         err = 0;
6496
6497 out:
6498         return err;
6499 }
6500
6501 /* tp->lock is held. */
6502 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6503 {
6504         struct fw_info info;
6505         const __be32 *fw_data;
6506         int err, i;
6507
6508         fw_data = (void *)tp->fw->data;
6509
6510         /* Firmware blob starts with version numbers, followed by
6511            start address and length. We are setting complete length.
6512            length = end_address_of_bss - start_address_of_text.
6513            Remainder is the blob to be loaded contiguously
6514            from start address. */
6515
6516         info.fw_base = be32_to_cpu(fw_data[1]);
6517         info.fw_len = tp->fw->size - 12;
6518         info.fw_data = &fw_data[3];
6519
6520         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6521                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6522                                     &info);
6523         if (err)
6524                 return err;
6525
6526         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6527                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6528                                     &info);
6529         if (err)
6530                 return err;
6531
6532         /* Now startup only the RX cpu. */
6533         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6534         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6535
6536         for (i = 0; i < 5; i++) {
6537                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6538                         break;
6539                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6540                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6541                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6542                 udelay(1000);
6543         }
6544         if (i >= 5) {
6545                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6546                        "to set RX CPU PC, is %08x should be %08x\n",
6547                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6548                        info.fw_base);
6549                 return -ENODEV;
6550         }
6551         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6552         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6553
6554         return 0;
6555 }
6556
6557 /* 5705 needs a special version of the TSO firmware.  */
6558
6559 /* tp->lock is held. */
6560 static int tg3_load_tso_firmware(struct tg3 *tp)
6561 {
6562         struct fw_info info;
6563         const __be32 *fw_data;
6564         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6565         int err, i;
6566
6567         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6568                 return 0;
6569
6570         fw_data = (void *)tp->fw->data;
6571
6572         /* Firmware blob starts with version numbers, followed by
6573            start address and length. We are setting complete length.
6574            length = end_address_of_bss - start_address_of_text.
6575            Remainder is the blob to be loaded contiguously
6576            from start address. */
6577
6578         info.fw_base = be32_to_cpu(fw_data[1]);
6579         cpu_scratch_size = tp->fw_len;
6580         info.fw_len = tp->fw->size - 12;
6581         info.fw_data = &fw_data[3];
6582
6583         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6584                 cpu_base = RX_CPU_BASE;
6585                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6586         } else {
6587                 cpu_base = TX_CPU_BASE;
6588                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6589                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6590         }
6591
6592         err = tg3_load_firmware_cpu(tp, cpu_base,
6593                                     cpu_scratch_base, cpu_scratch_size,
6594                                     &info);
6595         if (err)
6596                 return err;
6597
6598         /* Now startup the cpu. */
6599         tw32(cpu_base + CPU_STATE, 0xffffffff);
6600         tw32_f(cpu_base + CPU_PC, info.fw_base);
6601
6602         for (i = 0; i < 5; i++) {
6603                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6604                         break;
6605                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6606                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6607                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6608                 udelay(1000);
6609         }
6610         if (i >= 5) {
6611                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6612                        "to set CPU PC, is %08x should be %08x\n",
6613                        tp->dev->name, tr32(cpu_base + CPU_PC),
6614                        info.fw_base);
6615                 return -ENODEV;
6616         }
6617         tw32(cpu_base + CPU_STATE, 0xffffffff);
6618         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6619         return 0;
6620 }
6621
6622
6623 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6624 {
6625         struct tg3 *tp = netdev_priv(dev);
6626         struct sockaddr *addr = p;
6627         int err = 0, skip_mac_1 = 0;
6628
6629         if (!is_valid_ether_addr(addr->sa_data))
6630                 return -EINVAL;
6631
6632         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6633
6634         if (!netif_running(dev))
6635                 return 0;
6636
6637         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6638                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6639
6640                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6641                 addr0_low = tr32(MAC_ADDR_0_LOW);
6642                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6643                 addr1_low = tr32(MAC_ADDR_1_LOW);
6644
6645                 /* Skip MAC addr 1 if ASF is using it. */
6646                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6647                     !(addr1_high == 0 && addr1_low == 0))
6648                         skip_mac_1 = 1;
6649         }
6650         spin_lock_bh(&tp->lock);
6651         __tg3_set_mac_addr(tp, skip_mac_1);
6652         spin_unlock_bh(&tp->lock);
6653
6654         return err;
6655 }
6656
6657 /* tp->lock is held. */
6658 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6659                            dma_addr_t mapping, u32 maxlen_flags,
6660                            u32 nic_addr)
6661 {
6662         tg3_write_mem(tp,
6663                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6664                       ((u64) mapping >> 32));
6665         tg3_write_mem(tp,
6666                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6667                       ((u64) mapping & 0xffffffff));
6668         tg3_write_mem(tp,
6669                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6670                        maxlen_flags);
6671
6672         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6673                 tg3_write_mem(tp,
6674                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6675                               nic_addr);
6676 }
6677
6678 static void __tg3_set_rx_mode(struct net_device *);
6679 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6680 {
6681         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6682         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6683         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6684         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6685         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6686                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6687                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6688         }
6689         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6690         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6691         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6692                 u32 val = ec->stats_block_coalesce_usecs;
6693
6694                 if (!netif_carrier_ok(tp->dev))
6695                         val = 0;
6696
6697                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6698         }
6699 }
6700
6701 /* tp->lock is held. */
6702 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6703 {
6704         u32 val, rdmac_mode;
6705         int i, err, limit;
6706
6707         tg3_disable_ints(tp);
6708
6709         tg3_stop_fw(tp);
6710
6711         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6712
6713         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6714                 tg3_abort_hw(tp, 1);
6715         }
6716
6717         if (reset_phy &&
6718             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6719                 tg3_phy_reset(tp);
6720
6721         err = tg3_chip_reset(tp);
6722         if (err)
6723                 return err;
6724
6725         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6726
6727         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6728                 val = tr32(TG3_CPMU_CTRL);
6729                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6730                 tw32(TG3_CPMU_CTRL, val);
6731
6732                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6733                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6734                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6735                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6736
6737                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6738                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6739                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6740                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6741
6742                 val = tr32(TG3_CPMU_HST_ACC);
6743                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6744                 val |= CPMU_HST_ACC_MACCLK_6_25;
6745                 tw32(TG3_CPMU_HST_ACC, val);
6746         }
6747
6748         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6749                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6750                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6751                        PCIE_PWR_MGMT_L1_THRESH_4MS;
6752                 tw32(PCIE_PWR_MGMT_THRESH, val);
6753
6754                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6755                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6756
6757                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
6758         }
6759
6760         if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6761                 val = tr32(TG3_PCIE_LNKCTL);
6762                 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6763                         val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6764                 else
6765                         val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6766                 tw32(TG3_PCIE_LNKCTL, val);
6767         }
6768
6769         /* This works around an issue with Athlon chipsets on
6770          * B3 tigon3 silicon.  This bit has no effect on any
6771          * other revision.  But do not set this on PCI Express
6772          * chips and don't even touch the clocks if the CPMU is present.
6773          */
6774         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6775                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6776                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6777                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6778         }
6779
6780         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6781             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6782                 val = tr32(TG3PCI_PCISTATE);
6783                 val |= PCISTATE_RETRY_SAME_DMA;
6784                 tw32(TG3PCI_PCISTATE, val);
6785         }
6786
6787         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6788                 /* Allow reads and writes to the
6789                  * APE register and memory space.
6790                  */
6791                 val = tr32(TG3PCI_PCISTATE);
6792                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6793                        PCISTATE_ALLOW_APE_SHMEM_WR;
6794                 tw32(TG3PCI_PCISTATE, val);
6795         }
6796
6797         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6798                 /* Enable some hw fixes.  */
6799                 val = tr32(TG3PCI_MSI_DATA);
6800                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6801                 tw32(TG3PCI_MSI_DATA, val);
6802         }
6803
6804         /* Descriptor ring init may make accesses to the
6805          * NIC SRAM area to setup the TX descriptors, so we
6806          * can only do this after the hardware has been
6807          * successfully reset.
6808          */
6809         err = tg3_init_rings(tp);
6810         if (err)
6811                 return err;
6812
6813         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6814             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6815                 /* This value is determined during the probe time DMA
6816                  * engine test, tg3_test_dma.
6817                  */
6818                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6819         }
6820
6821         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6822                           GRC_MODE_4X_NIC_SEND_RINGS |
6823                           GRC_MODE_NO_TX_PHDR_CSUM |
6824                           GRC_MODE_NO_RX_PHDR_CSUM);
6825         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6826
6827         /* Pseudo-header checksum is done by hardware logic and not
6828          * the offload processers, so make the chip do the pseudo-
6829          * header checksums on receive.  For transmit it is more
6830          * convenient to do the pseudo-header checksum in software
6831          * as Linux does that on transmit for us in all cases.
6832          */
6833         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6834
6835         tw32(GRC_MODE,
6836              tp->grc_mode |
6837              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6838
6839         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6840         val = tr32(GRC_MISC_CFG);
6841         val &= ~0xff;
6842         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6843         tw32(GRC_MISC_CFG, val);
6844
6845         /* Initialize MBUF/DESC pool. */
6846         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6847                 /* Do nothing.  */
6848         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6849                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6850                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6851                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6852                 else
6853                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6854                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6855                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6856         }
6857         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6858                 int fw_len;
6859
6860                 fw_len = tp->fw_len;
6861                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6862                 tw32(BUFMGR_MB_POOL_ADDR,
6863                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6864                 tw32(BUFMGR_MB_POOL_SIZE,
6865                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6866         }
6867
6868         if (tp->dev->mtu <= ETH_DATA_LEN) {
6869                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6870                      tp->bufmgr_config.mbuf_read_dma_low_water);
6871                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6872                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6873                 tw32(BUFMGR_MB_HIGH_WATER,
6874                      tp->bufmgr_config.mbuf_high_water);
6875         } else {
6876                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6877                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6878                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6879                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6880                 tw32(BUFMGR_MB_HIGH_WATER,
6881                      tp->bufmgr_config.mbuf_high_water_jumbo);
6882         }
6883         tw32(BUFMGR_DMA_LOW_WATER,
6884              tp->bufmgr_config.dma_low_water);
6885         tw32(BUFMGR_DMA_HIGH_WATER,
6886              tp->bufmgr_config.dma_high_water);
6887
6888         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6889         for (i = 0; i < 2000; i++) {
6890                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6891                         break;
6892                 udelay(10);
6893         }
6894         if (i >= 2000) {
6895                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6896                        tp->dev->name);
6897                 return -ENODEV;
6898         }
6899
6900         /* Setup replenish threshold. */
6901         val = tp->rx_pending / 8;
6902         if (val == 0)
6903                 val = 1;
6904         else if (val > tp->rx_std_max_post)
6905                 val = tp->rx_std_max_post;
6906         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6907                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6908                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6909
6910                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6911                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6912         }
6913
6914         tw32(RCVBDI_STD_THRESH, val);
6915
6916         /* Initialize TG3_BDINFO's at:
6917          *  RCVDBDI_STD_BD:     standard eth size rx ring
6918          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6919          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6920          *
6921          * like so:
6922          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6923          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6924          *                              ring attribute flags
6925          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6926          *
6927          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6928          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6929          *
6930          * The size of each ring is fixed in the firmware, but the location is
6931          * configurable.
6932          */
6933         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6934              ((u64) tp->rx_std_mapping >> 32));
6935         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6936              ((u64) tp->rx_std_mapping & 0xffffffff));
6937         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6938              NIC_SRAM_RX_BUFFER_DESC);
6939
6940         /* Don't even try to program the JUMBO/MINI buffer descriptor
6941          * configs on 5705.
6942          */
6943         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6944                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6945                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6946         } else {
6947                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6948                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6949
6950                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6951                      BDINFO_FLAGS_DISABLED);
6952
6953                 /* Setup replenish threshold. */
6954                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6955
6956                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6957                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6958                              ((u64) tp->rx_jumbo_mapping >> 32));
6959                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6960                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6961                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6962                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6963                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6964                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6965                 } else {
6966                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6967                              BDINFO_FLAGS_DISABLED);
6968                 }
6969
6970         }
6971
6972         /* There is only one send ring on 5705/5750, no need to explicitly
6973          * disable the others.
6974          */
6975         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6976                 /* Clear out send RCB ring in SRAM. */
6977                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6978                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6979                                       BDINFO_FLAGS_DISABLED);
6980         }
6981
6982         tp->tx_prod = 0;
6983         tp->tx_cons = 0;
6984         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6985         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6986
6987         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6988                        tp->tx_desc_mapping,
6989                        (TG3_TX_RING_SIZE <<
6990                         BDINFO_FLAGS_MAXLEN_SHIFT),
6991                        NIC_SRAM_TX_BUFFER_DESC);
6992
6993         /* There is only one receive return ring on 5705/5750, no need
6994          * to explicitly disable the others.
6995          */
6996         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6997                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6998                      i += TG3_BDINFO_SIZE) {
6999                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7000                                       BDINFO_FLAGS_DISABLED);
7001                 }
7002         }
7003
7004         tp->rx_rcb_ptr = 0;
7005         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7006
7007         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7008                        tp->rx_rcb_mapping,
7009                        (TG3_RX_RCB_RING_SIZE(tp) <<
7010                         BDINFO_FLAGS_MAXLEN_SHIFT),
7011                        0);
7012
7013         tp->rx_std_ptr = tp->rx_pending;
7014         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7015                      tp->rx_std_ptr);
7016
7017         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7018                                                 tp->rx_jumbo_pending : 0;
7019         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7020                      tp->rx_jumbo_ptr);
7021
7022         /* Initialize MAC address and backoff seed. */
7023         __tg3_set_mac_addr(tp, 0);
7024
7025         /* MTU + ethernet header + FCS + optional VLAN tag */
7026         tw32(MAC_RX_MTU_SIZE,
7027              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7028
7029         /* The slot time is changed by tg3_setup_phy if we
7030          * run at gigabit with half duplex.
7031          */
7032         tw32(MAC_TX_LENGTHS,
7033              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7034              (6 << TX_LENGTHS_IPG_SHIFT) |
7035              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7036
7037         /* Receive rules. */
7038         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7039         tw32(RCVLPC_CONFIG, 0x0181);
7040
7041         /* Calculate RDMAC_MODE setting early, we need it to determine
7042          * the RCVLPC_STATE_ENABLE mask.
7043          */
7044         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7045                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7046                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7047                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7048                       RDMAC_MODE_LNGREAD_ENAB);
7049
7050         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7051             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7052             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7053                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7054                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7055                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7056
7057         /* If statement applies to 5705 and 5750 PCI devices only */
7058         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7059              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7060             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7061                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7062                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7063                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7064                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7065                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7066                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7067                 }
7068         }
7069
7070         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7071                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7072
7073         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7074                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7075
7076         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7077             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7078                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7079
7080         /* Receive/send statistics. */
7081         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7082                 val = tr32(RCVLPC_STATS_ENABLE);
7083                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7084                 tw32(RCVLPC_STATS_ENABLE, val);
7085         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7086                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7087                 val = tr32(RCVLPC_STATS_ENABLE);
7088                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7089                 tw32(RCVLPC_STATS_ENABLE, val);
7090         } else {
7091                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7092         }
7093         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7094         tw32(SNDDATAI_STATSENAB, 0xffffff);
7095         tw32(SNDDATAI_STATSCTRL,
7096              (SNDDATAI_SCTRL_ENABLE |
7097               SNDDATAI_SCTRL_FASTUPD));
7098
7099         /* Setup host coalescing engine. */
7100         tw32(HOSTCC_MODE, 0);
7101         for (i = 0; i < 2000; i++) {
7102                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7103                         break;
7104                 udelay(10);
7105         }
7106
7107         __tg3_set_coalesce(tp, &tp->coal);
7108
7109         /* set status block DMA address */
7110         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7111              ((u64) tp->status_mapping >> 32));
7112         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7113              ((u64) tp->status_mapping & 0xffffffff));
7114
7115         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7116                 /* Status/statistics block address.  See tg3_timer,
7117                  * the tg3_periodic_fetch_stats call there, and
7118                  * tg3_get_stats to see how this works for 5705/5750 chips.
7119                  */
7120                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7121                      ((u64) tp->stats_mapping >> 32));
7122                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7123                      ((u64) tp->stats_mapping & 0xffffffff));
7124                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7125                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7126         }
7127
7128         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7129
7130         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7131         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7132         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7133                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7134
7135         /* Clear statistics/status block in chip, and status block in ram. */
7136         for (i = NIC_SRAM_STATS_BLK;
7137              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7138              i += sizeof(u32)) {
7139                 tg3_write_mem(tp, i, 0);
7140                 udelay(40);
7141         }
7142         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7143
7144         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7145                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7146                 /* reset to prevent losing 1st rx packet intermittently */
7147                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7148                 udelay(10);
7149         }
7150
7151         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7152                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7153         else
7154                 tp->mac_mode = 0;
7155         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7156                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7157         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7158             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7159             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7160                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7161         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7162         udelay(40);
7163
7164         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7165          * If TG3_FLG2_IS_NIC is zero, we should read the
7166          * register to preserve the GPIO settings for LOMs. The GPIOs,
7167          * whether used as inputs or outputs, are set by boot code after
7168          * reset.
7169          */
7170         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7171                 u32 gpio_mask;
7172
7173                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7174                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7175                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7176
7177                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7178                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7179                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7180
7181                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7182                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7183
7184                 tp->grc_local_ctrl &= ~gpio_mask;
7185                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7186
7187                 /* GPIO1 must be driven high for eeprom write protect */
7188                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7189                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7190                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7191         }
7192         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7193         udelay(100);
7194
7195         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7196
7197         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7198                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7199                 udelay(40);
7200         }
7201
7202         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7203                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7204                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7205                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7206                WDMAC_MODE_LNGREAD_ENAB);
7207
7208         /* If statement applies to 5705 and 5750 PCI devices only */
7209         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7210              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7211             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7212                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7213                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7214                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7215                         /* nothing */
7216                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7217                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7218                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7219                         val |= WDMAC_MODE_RX_ACCEL;
7220                 }
7221         }
7222
7223         /* Enable host coalescing bug fix */
7224         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7225                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7226
7227         tw32_f(WDMAC_MODE, val);
7228         udelay(40);
7229
7230         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7231                 u16 pcix_cmd;
7232
7233                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7234                                      &pcix_cmd);
7235                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7236                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7237                         pcix_cmd |= PCI_X_CMD_READ_2K;
7238                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7239                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7240                         pcix_cmd |= PCI_X_CMD_READ_2K;
7241                 }
7242                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7243                                       pcix_cmd);
7244         }
7245
7246         tw32_f(RDMAC_MODE, rdmac_mode);
7247         udelay(40);
7248
7249         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7250         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7251                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7252
7253         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7254                 tw32(SNDDATAC_MODE,
7255                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7256         else
7257                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7258
7259         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7260         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7261         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7262         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7263         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7264                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7265         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7266         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7267
7268         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7269                 err = tg3_load_5701_a0_firmware_fix(tp);
7270                 if (err)
7271                         return err;
7272         }
7273
7274         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7275                 err = tg3_load_tso_firmware(tp);
7276                 if (err)
7277                         return err;
7278         }
7279
7280         tp->tx_mode = TX_MODE_ENABLE;
7281         tw32_f(MAC_TX_MODE, tp->tx_mode);
7282         udelay(100);
7283
7284         tp->rx_mode = RX_MODE_ENABLE;
7285         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7286                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7287
7288         tw32_f(MAC_RX_MODE, tp->rx_mode);
7289         udelay(10);
7290
7291         tw32(MAC_LED_CTRL, tp->led_ctrl);
7292
7293         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7294         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7295                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7296                 udelay(10);
7297         }
7298         tw32_f(MAC_RX_MODE, tp->rx_mode);
7299         udelay(10);
7300
7301         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7302                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7303                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7304                         /* Set drive transmission level to 1.2V  */
7305                         /* only if the signal pre-emphasis bit is not set  */
7306                         val = tr32(MAC_SERDES_CFG);
7307                         val &= 0xfffff000;
7308                         val |= 0x880;
7309                         tw32(MAC_SERDES_CFG, val);
7310                 }
7311                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7312                         tw32(MAC_SERDES_CFG, 0x616000);
7313         }
7314
7315         /* Prevent chip from dropping frames when flow control
7316          * is enabled.
7317          */
7318         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7319
7320         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7321             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7322                 /* Use hardware link auto-negotiation */
7323                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7324         }
7325
7326         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7327             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7328                 u32 tmp;
7329
7330                 tmp = tr32(SERDES_RX_CTRL);
7331                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7332                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7333                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7334                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7335         }
7336
7337         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7338                 if (tp->link_config.phy_is_low_power) {
7339                         tp->link_config.phy_is_low_power = 0;
7340                         tp->link_config.speed = tp->link_config.orig_speed;
7341                         tp->link_config.duplex = tp->link_config.orig_duplex;
7342                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7343                 }
7344
7345                 err = tg3_setup_phy(tp, 0);
7346                 if (err)
7347                         return err;
7348
7349                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7350                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7351                         u32 tmp;
7352
7353                         /* Clear CRC stats. */
7354                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7355                                 tg3_writephy(tp, MII_TG3_TEST1,
7356                                              tmp | MII_TG3_TEST1_CRC_EN);
7357                                 tg3_readphy(tp, 0x14, &tmp);
7358                         }
7359                 }
7360         }
7361
7362         __tg3_set_rx_mode(tp->dev);
7363
7364         /* Initialize receive rules. */
7365         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7366         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7367         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7368         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7369
7370         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7371             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7372                 limit = 8;
7373         else
7374                 limit = 16;
7375         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7376                 limit -= 4;
7377         switch (limit) {
7378         case 16:
7379                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7380         case 15:
7381                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7382         case 14:
7383                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7384         case 13:
7385                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7386         case 12:
7387                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7388         case 11:
7389                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7390         case 10:
7391                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7392         case 9:
7393                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7394         case 8:
7395                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7396         case 7:
7397                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7398         case 6:
7399                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7400         case 5:
7401                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7402         case 4:
7403                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7404         case 3:
7405                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7406         case 2:
7407         case 1:
7408
7409         default:
7410                 break;
7411         }
7412
7413         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7414                 /* Write our heartbeat update interval to APE. */
7415                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7416                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7417
7418         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7419
7420         return 0;
7421 }
7422
7423 /* Called at device open time to get the chip ready for
7424  * packet processing.  Invoked with tp->lock held.
7425  */
7426 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7427 {
7428         tg3_switch_clocks(tp);
7429
7430         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7431
7432         return tg3_reset_hw(tp, reset_phy);
7433 }
7434
7435 #define TG3_STAT_ADD32(PSTAT, REG) \
7436 do {    u32 __val = tr32(REG); \
7437         (PSTAT)->low += __val; \
7438         if ((PSTAT)->low < __val) \
7439                 (PSTAT)->high += 1; \
7440 } while (0)
7441
7442 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7443 {
7444         struct tg3_hw_stats *sp = tp->hw_stats;
7445
7446         if (!netif_carrier_ok(tp->dev))
7447                 return;
7448
7449         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7450         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7451         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7452         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7453         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7454         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7455         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7456         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7457         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7458         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7459         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7460         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7461         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7462
7463         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7464         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7465         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7466         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7467         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7468         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7469         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7470         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7471         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7472         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7473         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7474         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7475         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7476         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7477
7478         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7479         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7480         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7481 }
7482
7483 static void tg3_timer(unsigned long __opaque)
7484 {
7485         struct tg3 *tp = (struct tg3 *) __opaque;
7486
7487         if (tp->irq_sync)
7488                 goto restart_timer;
7489
7490         spin_lock(&tp->lock);
7491
7492         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7493                 /* All of this garbage is because when using non-tagged
7494                  * IRQ status the mailbox/status_block protocol the chip
7495                  * uses with the cpu is race prone.
7496                  */
7497                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7498                         tw32(GRC_LOCAL_CTRL,
7499                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7500                 } else {
7501                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7502                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7503                 }
7504
7505                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7506                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7507                         spin_unlock(&tp->lock);
7508                         schedule_work(&tp->reset_task);
7509                         return;
7510                 }
7511         }
7512
7513         /* This part only runs once per second. */
7514         if (!--tp->timer_counter) {
7515                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7516                         tg3_periodic_fetch_stats(tp);
7517
7518                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7519                         u32 mac_stat;
7520                         int phy_event;
7521
7522                         mac_stat = tr32(MAC_STATUS);
7523
7524                         phy_event = 0;
7525                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7526                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7527                                         phy_event = 1;
7528                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7529                                 phy_event = 1;
7530
7531                         if (phy_event)
7532                                 tg3_setup_phy(tp, 0);
7533                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7534                         u32 mac_stat = tr32(MAC_STATUS);
7535                         int need_setup = 0;
7536
7537                         if (netif_carrier_ok(tp->dev) &&
7538                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7539                                 need_setup = 1;
7540                         }
7541                         if (! netif_carrier_ok(tp->dev) &&
7542                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7543                                          MAC_STATUS_SIGNAL_DET))) {
7544                                 need_setup = 1;
7545                         }
7546                         if (need_setup) {
7547                                 if (!tp->serdes_counter) {
7548                                         tw32_f(MAC_MODE,
7549                                              (tp->mac_mode &
7550                                               ~MAC_MODE_PORT_MODE_MASK));
7551                                         udelay(40);
7552                                         tw32_f(MAC_MODE, tp->mac_mode);
7553                                         udelay(40);
7554                                 }
7555                                 tg3_setup_phy(tp, 0);
7556                         }
7557                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7558                         tg3_serdes_parallel_detect(tp);
7559
7560                 tp->timer_counter = tp->timer_multiplier;
7561         }
7562
7563         /* Heartbeat is only sent once every 2 seconds.
7564          *
7565          * The heartbeat is to tell the ASF firmware that the host
7566          * driver is still alive.  In the event that the OS crashes,
7567          * ASF needs to reset the hardware to free up the FIFO space
7568          * that may be filled with rx packets destined for the host.
7569          * If the FIFO is full, ASF will no longer function properly.
7570          *
7571          * Unintended resets have been reported on real time kernels
7572          * where the timer doesn't run on time.  Netpoll will also have
7573          * same problem.
7574          *
7575          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7576          * to check the ring condition when the heartbeat is expiring
7577          * before doing the reset.  This will prevent most unintended
7578          * resets.
7579          */
7580         if (!--tp->asf_counter) {
7581                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7582                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7583                         tg3_wait_for_event_ack(tp);
7584
7585                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7586                                       FWCMD_NICDRV_ALIVE3);
7587                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7588                         /* 5 seconds timeout */
7589                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7590
7591                         tg3_generate_fw_event(tp);
7592                 }
7593                 tp->asf_counter = tp->asf_multiplier;
7594         }
7595
7596         spin_unlock(&tp->lock);
7597
7598 restart_timer:
7599         tp->timer.expires = jiffies + tp->timer_offset;
7600         add_timer(&tp->timer);
7601 }
7602
7603 static int tg3_request_irq(struct tg3 *tp)
7604 {
7605         irq_handler_t fn;
7606         unsigned long flags;
7607         struct net_device *dev = tp->dev;
7608
7609         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7610                 fn = tg3_msi;
7611                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7612                         fn = tg3_msi_1shot;
7613                 flags = IRQF_SAMPLE_RANDOM;
7614         } else {
7615                 fn = tg3_interrupt;
7616                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7617                         fn = tg3_interrupt_tagged;
7618                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7619         }
7620         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7621 }
7622
7623 static int tg3_test_interrupt(struct tg3 *tp)
7624 {
7625         struct net_device *dev = tp->dev;
7626         int err, i, intr_ok = 0;
7627
7628         if (!netif_running(dev))
7629                 return -ENODEV;
7630
7631         tg3_disable_ints(tp);
7632
7633         free_irq(tp->pdev->irq, dev);
7634
7635         err = request_irq(tp->pdev->irq, tg3_test_isr,
7636                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7637         if (err)
7638                 return err;
7639
7640         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7641         tg3_enable_ints(tp);
7642
7643         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7644                HOSTCC_MODE_NOW);
7645
7646         for (i = 0; i < 5; i++) {
7647                 u32 int_mbox, misc_host_ctrl;
7648
7649                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7650                                         TG3_64BIT_REG_LOW);
7651                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7652
7653                 if ((int_mbox != 0) ||
7654                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7655                         intr_ok = 1;
7656                         break;
7657                 }
7658
7659                 msleep(10);
7660         }
7661
7662         tg3_disable_ints(tp);
7663
7664         free_irq(tp->pdev->irq, dev);
7665
7666         err = tg3_request_irq(tp);
7667
7668         if (err)
7669                 return err;
7670
7671         if (intr_ok)
7672                 return 0;
7673
7674         return -EIO;
7675 }
7676
7677 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7678  * successfully restored
7679  */
7680 static int tg3_test_msi(struct tg3 *tp)
7681 {
7682         struct net_device *dev = tp->dev;
7683         int err;
7684         u16 pci_cmd;
7685
7686         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7687                 return 0;
7688
7689         /* Turn off SERR reporting in case MSI terminates with Master
7690          * Abort.
7691          */
7692         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7693         pci_write_config_word(tp->pdev, PCI_COMMAND,
7694                               pci_cmd & ~PCI_COMMAND_SERR);
7695
7696         err = tg3_test_interrupt(tp);
7697
7698         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7699
7700         if (!err)
7701                 return 0;
7702
7703         /* other failures */
7704         if (err != -EIO)
7705                 return err;
7706
7707         /* MSI test failed, go back to INTx mode */
7708         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7709                "switching to INTx mode. Please report this failure to "
7710                "the PCI maintainer and include system chipset information.\n",
7711                        tp->dev->name);
7712
7713         free_irq(tp->pdev->irq, dev);
7714         pci_disable_msi(tp->pdev);
7715
7716         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7717
7718         err = tg3_request_irq(tp);
7719         if (err)
7720                 return err;
7721
7722         /* Need to reset the chip because the MSI cycle may have terminated
7723          * with Master Abort.
7724          */
7725         tg3_full_lock(tp, 1);
7726
7727         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7728         err = tg3_init_hw(tp, 1);
7729
7730         tg3_full_unlock(tp);
7731
7732         if (err)
7733                 free_irq(tp->pdev->irq, dev);
7734
7735         return err;
7736 }
7737
7738 static int tg3_request_firmware(struct tg3 *tp)
7739 {
7740         const __be32 *fw_data;
7741
7742         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7743                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7744                        tp->dev->name, tp->fw_needed);
7745                 return -ENOENT;
7746         }
7747
7748         fw_data = (void *)tp->fw->data;
7749
7750         /* Firmware blob starts with version numbers, followed by
7751          * start address and _full_ length including BSS sections
7752          * (which must be longer than the actual data, of course
7753          */
7754
7755         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
7756         if (tp->fw_len < (tp->fw->size - 12)) {
7757                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7758                        tp->dev->name, tp->fw_len, tp->fw_needed);
7759                 release_firmware(tp->fw);
7760                 tp->fw = NULL;
7761                 return -EINVAL;
7762         }
7763
7764         /* We no longer need firmware; we have it. */
7765         tp->fw_needed = NULL;
7766         return 0;
7767 }
7768
7769 static int tg3_open(struct net_device *dev)
7770 {
7771         struct tg3 *tp = netdev_priv(dev);
7772         int err;
7773
7774         if (tp->fw_needed) {
7775                 err = tg3_request_firmware(tp);
7776                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7777                         if (err)
7778                                 return err;
7779                 } else if (err) {
7780                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
7781                                tp->dev->name);
7782                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7783                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7784                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
7785                                tp->dev->name);
7786                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7787                 }
7788         }
7789
7790         netif_carrier_off(tp->dev);
7791
7792         err = tg3_set_power_state(tp, PCI_D0);
7793         if (err)
7794                 return err;
7795
7796         tg3_full_lock(tp, 0);
7797
7798         tg3_disable_ints(tp);
7799         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7800
7801         tg3_full_unlock(tp);
7802
7803         /* The placement of this call is tied
7804          * to the setup and use of Host TX descriptors.
7805          */
7806         err = tg3_alloc_consistent(tp);
7807         if (err)
7808                 return err;
7809
7810         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7811                 /* All MSI supporting chips should support tagged
7812                  * status.  Assert that this is the case.
7813                  */
7814                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7815                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7816                                "Not using MSI.\n", tp->dev->name);
7817                 } else if (pci_enable_msi(tp->pdev) == 0) {
7818                         u32 msi_mode;
7819
7820                         msi_mode = tr32(MSGINT_MODE);
7821                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7822                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7823                 }
7824         }
7825         err = tg3_request_irq(tp);
7826
7827         if (err) {
7828                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7829                         pci_disable_msi(tp->pdev);
7830                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7831                 }
7832                 tg3_free_consistent(tp);
7833                 return err;
7834         }
7835
7836         napi_enable(&tp->napi);
7837
7838         tg3_full_lock(tp, 0);
7839
7840         err = tg3_init_hw(tp, 1);
7841         if (err) {
7842                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7843                 tg3_free_rings(tp);
7844         } else {
7845                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7846                         tp->timer_offset = HZ;
7847                 else
7848                         tp->timer_offset = HZ / 10;
7849
7850                 BUG_ON(tp->timer_offset > HZ);
7851                 tp->timer_counter = tp->timer_multiplier =
7852                         (HZ / tp->timer_offset);
7853                 tp->asf_counter = tp->asf_multiplier =
7854                         ((HZ / tp->timer_offset) * 2);
7855
7856                 init_timer(&tp->timer);
7857                 tp->timer.expires = jiffies + tp->timer_offset;
7858                 tp->timer.data = (unsigned long) tp;
7859                 tp->timer.function = tg3_timer;
7860         }
7861
7862         tg3_full_unlock(tp);
7863
7864         if (err) {
7865                 napi_disable(&tp->napi);
7866                 free_irq(tp->pdev->irq, dev);
7867                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7868                         pci_disable_msi(tp->pdev);
7869                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7870                 }
7871                 tg3_free_consistent(tp);
7872                 return err;
7873         }
7874
7875         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7876                 err = tg3_test_msi(tp);
7877
7878                 if (err) {
7879                         tg3_full_lock(tp, 0);
7880
7881                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7882                                 pci_disable_msi(tp->pdev);
7883                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7884                         }
7885                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7886                         tg3_free_rings(tp);
7887                         tg3_free_consistent(tp);
7888
7889                         tg3_full_unlock(tp);
7890
7891                         napi_disable(&tp->napi);
7892
7893                         return err;
7894                 }
7895
7896                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7897                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7898                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7899
7900                                 tw32(PCIE_TRANSACTION_CFG,
7901                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7902                         }
7903                 }
7904         }
7905
7906         tg3_phy_start(tp);
7907
7908         tg3_full_lock(tp, 0);
7909
7910         add_timer(&tp->timer);
7911         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7912         tg3_enable_ints(tp);
7913
7914         tg3_full_unlock(tp);
7915
7916         netif_start_queue(dev);
7917
7918         return 0;
7919 }
7920
7921 #if 0
7922 /*static*/ void tg3_dump_state(struct tg3 *tp)
7923 {
7924         u32 val32, val32_2, val32_3, val32_4, val32_5;
7925         u16 val16;
7926         int i;
7927
7928         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7929         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7930         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7931                val16, val32);
7932
7933         /* MAC block */
7934         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7935                tr32(MAC_MODE), tr32(MAC_STATUS));
7936         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7937                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7938         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7939                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7940         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7941                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7942
7943         /* Send data initiator control block */
7944         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7945                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7946         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7947                tr32(SNDDATAI_STATSCTRL));
7948
7949         /* Send data completion control block */
7950         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7951
7952         /* Send BD ring selector block */
7953         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7954                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7955
7956         /* Send BD initiator control block */
7957         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7958                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7959
7960         /* Send BD completion control block */
7961         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7962
7963         /* Receive list placement control block */
7964         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7965                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7966         printk("       RCVLPC_STATSCTRL[%08x]\n",
7967                tr32(RCVLPC_STATSCTRL));
7968
7969         /* Receive data and receive BD initiator control block */
7970         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7971                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7972
7973         /* Receive data completion control block */
7974         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7975                tr32(RCVDCC_MODE));
7976
7977         /* Receive BD initiator control block */
7978         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7979                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7980
7981         /* Receive BD completion control block */
7982         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7983                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7984
7985         /* Receive list selector control block */
7986         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7987                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7988
7989         /* Mbuf cluster free block */
7990         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7991                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7992
7993         /* Host coalescing control block */
7994         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7995                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7996         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7997                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7998                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7999         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8000                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8001                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8002         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8003                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8004         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8005                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8006
8007         /* Memory arbiter control block */
8008         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8009                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8010
8011         /* Buffer manager control block */
8012         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8013                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8014         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8015                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8016         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8017                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8018                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8019                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8020
8021         /* Read DMA control block */
8022         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8023                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8024
8025         /* Write DMA control block */
8026         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8027                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8028
8029         /* DMA completion block */
8030         printk("DEBUG: DMAC_MODE[%08x]\n",
8031                tr32(DMAC_MODE));
8032
8033         /* GRC block */
8034         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8035                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8036         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8037                tr32(GRC_LOCAL_CTRL));
8038
8039         /* TG3_BDINFOs */
8040         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8041                tr32(RCVDBDI_JUMBO_BD + 0x0),
8042                tr32(RCVDBDI_JUMBO_BD + 0x4),
8043                tr32(RCVDBDI_JUMBO_BD + 0x8),
8044                tr32(RCVDBDI_JUMBO_BD + 0xc));
8045         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8046                tr32(RCVDBDI_STD_BD + 0x0),
8047                tr32(RCVDBDI_STD_BD + 0x4),
8048                tr32(RCVDBDI_STD_BD + 0x8),
8049                tr32(RCVDBDI_STD_BD + 0xc));
8050         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8051                tr32(RCVDBDI_MINI_BD + 0x0),
8052                tr32(RCVDBDI_MINI_BD + 0x4),
8053                tr32(RCVDBDI_MINI_BD + 0x8),
8054                tr32(RCVDBDI_MINI_BD + 0xc));
8055
8056         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8057         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8058         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8059         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8060         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8061                val32, val32_2, val32_3, val32_4);
8062
8063         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8064         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8065         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8066         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8067         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8068                val32, val32_2, val32_3, val32_4);
8069
8070         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8071         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8072         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8073         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8074         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8075         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8076                val32, val32_2, val32_3, val32_4, val32_5);
8077
8078         /* SW status block */
8079         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8080                tp->hw_status->status,
8081                tp->hw_status->status_tag,
8082                tp->hw_status->rx_jumbo_consumer,
8083                tp->hw_status->rx_consumer,
8084                tp->hw_status->rx_mini_consumer,
8085                tp->hw_status->idx[0].rx_producer,
8086                tp->hw_status->idx[0].tx_consumer);
8087
8088         /* SW statistics block */
8089         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8090                ((u32 *)tp->hw_stats)[0],
8091                ((u32 *)tp->hw_stats)[1],
8092                ((u32 *)tp->hw_stats)[2],
8093                ((u32 *)tp->hw_stats)[3]);
8094
8095         /* Mailboxes */
8096         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8097                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8098                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8099                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8100                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8101
8102         /* NIC side send descriptors. */
8103         for (i = 0; i < 6; i++) {
8104                 unsigned long txd;
8105
8106                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8107                         + (i * sizeof(struct tg3_tx_buffer_desc));
8108                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8109                        i,
8110                        readl(txd + 0x0), readl(txd + 0x4),
8111                        readl(txd + 0x8), readl(txd + 0xc));
8112         }
8113
8114         /* NIC side RX descriptors. */
8115         for (i = 0; i < 6; i++) {
8116                 unsigned long rxd;
8117
8118                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8119                         + (i * sizeof(struct tg3_rx_buffer_desc));
8120                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8121                        i,
8122                        readl(rxd + 0x0), readl(rxd + 0x4),
8123                        readl(rxd + 0x8), readl(rxd + 0xc));
8124                 rxd += (4 * sizeof(u32));
8125                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8126                        i,
8127                        readl(rxd + 0x0), readl(rxd + 0x4),
8128                        readl(rxd + 0x8), readl(rxd + 0xc));
8129         }
8130
8131         for (i = 0; i < 6; i++) {
8132                 unsigned long rxd;
8133
8134                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8135                         + (i * sizeof(struct tg3_rx_buffer_desc));
8136                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8137                        i,
8138                        readl(rxd + 0x0), readl(rxd + 0x4),
8139                        readl(rxd + 0x8), readl(rxd + 0xc));
8140                 rxd += (4 * sizeof(u32));
8141                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8142                        i,
8143                        readl(rxd + 0x0), readl(rxd + 0x4),
8144                        readl(rxd + 0x8), readl(rxd + 0xc));
8145         }
8146 }
8147 #endif
8148
8149 static struct net_device_stats *tg3_get_stats(struct net_device *);
8150 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8151
8152 static int tg3_close(struct net_device *dev)
8153 {
8154         struct tg3 *tp = netdev_priv(dev);
8155
8156         napi_disable(&tp->napi);
8157         cancel_work_sync(&tp->reset_task);
8158
8159         netif_stop_queue(dev);
8160
8161         del_timer_sync(&tp->timer);
8162
8163         tg3_full_lock(tp, 1);
8164 #if 0
8165         tg3_dump_state(tp);
8166 #endif
8167
8168         tg3_disable_ints(tp);
8169
8170         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8171         tg3_free_rings(tp);
8172         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8173
8174         tg3_full_unlock(tp);
8175
8176         free_irq(tp->pdev->irq, dev);
8177         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8178                 pci_disable_msi(tp->pdev);
8179                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8180         }
8181
8182         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8183                sizeof(tp->net_stats_prev));
8184         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8185                sizeof(tp->estats_prev));
8186
8187         tg3_free_consistent(tp);
8188
8189         tg3_set_power_state(tp, PCI_D3hot);
8190
8191         netif_carrier_off(tp->dev);
8192
8193         return 0;
8194 }
8195
8196 static inline unsigned long get_stat64(tg3_stat64_t *val)
8197 {
8198         unsigned long ret;
8199
8200 #if (BITS_PER_LONG == 32)
8201         ret = val->low;
8202 #else
8203         ret = ((u64)val->high << 32) | ((u64)val->low);
8204 #endif
8205         return ret;
8206 }
8207
8208 static inline u64 get_estat64(tg3_stat64_t *val)
8209 {
8210        return ((u64)val->high << 32) | ((u64)val->low);
8211 }
8212
8213 static unsigned long calc_crc_errors(struct tg3 *tp)
8214 {
8215         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8216
8217         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8218             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8219              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8220                 u32 val;
8221
8222                 spin_lock_bh(&tp->lock);
8223                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8224                         tg3_writephy(tp, MII_TG3_TEST1,
8225                                      val | MII_TG3_TEST1_CRC_EN);
8226                         tg3_readphy(tp, 0x14, &val);
8227                 } else
8228                         val = 0;
8229                 spin_unlock_bh(&tp->lock);
8230
8231                 tp->phy_crc_errors += val;
8232
8233                 return tp->phy_crc_errors;
8234         }
8235
8236         return get_stat64(&hw_stats->rx_fcs_errors);
8237 }
8238
8239 #define ESTAT_ADD(member) \
8240         estats->member =        old_estats->member + \
8241                                 get_estat64(&hw_stats->member)
8242
8243 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8244 {
8245         struct tg3_ethtool_stats *estats = &tp->estats;
8246         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8247         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8248
8249         if (!hw_stats)
8250                 return old_estats;
8251
8252         ESTAT_ADD(rx_octets);
8253         ESTAT_ADD(rx_fragments);
8254         ESTAT_ADD(rx_ucast_packets);
8255         ESTAT_ADD(rx_mcast_packets);
8256         ESTAT_ADD(rx_bcast_packets);
8257         ESTAT_ADD(rx_fcs_errors);
8258         ESTAT_ADD(rx_align_errors);
8259         ESTAT_ADD(rx_xon_pause_rcvd);
8260         ESTAT_ADD(rx_xoff_pause_rcvd);
8261         ESTAT_ADD(rx_mac_ctrl_rcvd);
8262         ESTAT_ADD(rx_xoff_entered);
8263         ESTAT_ADD(rx_frame_too_long_errors);
8264         ESTAT_ADD(rx_jabbers);
8265         ESTAT_ADD(rx_undersize_packets);
8266         ESTAT_ADD(rx_in_length_errors);
8267         ESTAT_ADD(rx_out_length_errors);
8268         ESTAT_ADD(rx_64_or_less_octet_packets);
8269         ESTAT_ADD(rx_65_to_127_octet_packets);
8270         ESTAT_ADD(rx_128_to_255_octet_packets);
8271         ESTAT_ADD(rx_256_to_511_octet_packets);
8272         ESTAT_ADD(rx_512_to_1023_octet_packets);
8273         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8274         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8275         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8276         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8277         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8278
8279         ESTAT_ADD(tx_octets);
8280         ESTAT_ADD(tx_collisions);
8281         ESTAT_ADD(tx_xon_sent);
8282         ESTAT_ADD(tx_xoff_sent);
8283         ESTAT_ADD(tx_flow_control);
8284         ESTAT_ADD(tx_mac_errors);
8285         ESTAT_ADD(tx_single_collisions);
8286         ESTAT_ADD(tx_mult_collisions);
8287         ESTAT_ADD(tx_deferred);
8288         ESTAT_ADD(tx_excessive_collisions);
8289         ESTAT_ADD(tx_late_collisions);
8290         ESTAT_ADD(tx_collide_2times);
8291         ESTAT_ADD(tx_collide_3times);
8292         ESTAT_ADD(tx_collide_4times);
8293         ESTAT_ADD(tx_collide_5times);
8294         ESTAT_ADD(tx_collide_6times);
8295         ESTAT_ADD(tx_collide_7times);
8296         ESTAT_ADD(tx_collide_8times);
8297         ESTAT_ADD(tx_collide_9times);
8298         ESTAT_ADD(tx_collide_10times);
8299         ESTAT_ADD(tx_collide_11times);
8300         ESTAT_ADD(tx_collide_12times);
8301         ESTAT_ADD(tx_collide_13times);
8302         ESTAT_ADD(tx_collide_14times);
8303         ESTAT_ADD(tx_collide_15times);
8304         ESTAT_ADD(tx_ucast_packets);
8305         ESTAT_ADD(tx_mcast_packets);
8306         ESTAT_ADD(tx_bcast_packets);
8307         ESTAT_ADD(tx_carrier_sense_errors);
8308         ESTAT_ADD(tx_discards);
8309         ESTAT_ADD(tx_errors);
8310
8311         ESTAT_ADD(dma_writeq_full);
8312         ESTAT_ADD(dma_write_prioq_full);
8313         ESTAT_ADD(rxbds_empty);
8314         ESTAT_ADD(rx_discards);
8315         ESTAT_ADD(rx_errors);
8316         ESTAT_ADD(rx_threshold_hit);
8317
8318         ESTAT_ADD(dma_readq_full);
8319         ESTAT_ADD(dma_read_prioq_full);
8320         ESTAT_ADD(tx_comp_queue_full);
8321
8322         ESTAT_ADD(ring_set_send_prod_index);
8323         ESTAT_ADD(ring_status_update);
8324         ESTAT_ADD(nic_irqs);
8325         ESTAT_ADD(nic_avoided_irqs);
8326         ESTAT_ADD(nic_tx_threshold_hit);
8327
8328         return estats;
8329 }
8330
8331 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8332 {
8333         struct tg3 *tp = netdev_priv(dev);
8334         struct net_device_stats *stats = &tp->net_stats;
8335         struct net_device_stats *old_stats = &tp->net_stats_prev;
8336         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8337
8338         if (!hw_stats)
8339                 return old_stats;
8340
8341         stats->rx_packets = old_stats->rx_packets +
8342                 get_stat64(&hw_stats->rx_ucast_packets) +
8343                 get_stat64(&hw_stats->rx_mcast_packets) +
8344                 get_stat64(&hw_stats->rx_bcast_packets);
8345
8346         stats->tx_packets = old_stats->tx_packets +
8347                 get_stat64(&hw_stats->tx_ucast_packets) +
8348                 get_stat64(&hw_stats->tx_mcast_packets) +
8349                 get_stat64(&hw_stats->tx_bcast_packets);
8350
8351         stats->rx_bytes = old_stats->rx_bytes +
8352                 get_stat64(&hw_stats->rx_octets);
8353         stats->tx_bytes = old_stats->tx_bytes +
8354                 get_stat64(&hw_stats->tx_octets);
8355
8356         stats->rx_errors = old_stats->rx_errors +
8357                 get_stat64(&hw_stats->rx_errors);
8358         stats->tx_errors = old_stats->tx_errors +
8359                 get_stat64(&hw_stats->tx_errors) +
8360                 get_stat64(&hw_stats->tx_mac_errors) +
8361                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8362                 get_stat64(&hw_stats->tx_discards);
8363
8364         stats->multicast = old_stats->multicast +
8365                 get_stat64(&hw_stats->rx_mcast_packets);
8366         stats->collisions = old_stats->collisions +
8367                 get_stat64(&hw_stats->tx_collisions);
8368
8369         stats->rx_length_errors = old_stats->rx_length_errors +
8370                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8371                 get_stat64(&hw_stats->rx_undersize_packets);
8372
8373         stats->rx_over_errors = old_stats->rx_over_errors +
8374                 get_stat64(&hw_stats->rxbds_empty);
8375         stats->rx_frame_errors = old_stats->rx_frame_errors +
8376                 get_stat64(&hw_stats->rx_align_errors);
8377         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8378                 get_stat64(&hw_stats->tx_discards);
8379         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8380                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8381
8382         stats->rx_crc_errors = old_stats->rx_crc_errors +
8383                 calc_crc_errors(tp);
8384
8385         stats->rx_missed_errors = old_stats->rx_missed_errors +
8386                 get_stat64(&hw_stats->rx_discards);
8387
8388         return stats;
8389 }
8390
8391 static inline u32 calc_crc(unsigned char *buf, int len)
8392 {
8393         u32 reg;
8394         u32 tmp;
8395         int j, k;
8396
8397         reg = 0xffffffff;
8398
8399         for (j = 0; j < len; j++) {
8400                 reg ^= buf[j];
8401
8402                 for (k = 0; k < 8; k++) {
8403                         tmp = reg & 0x01;
8404
8405                         reg >>= 1;
8406
8407                         if (tmp) {
8408                                 reg ^= 0xedb88320;
8409                         }
8410                 }
8411         }
8412
8413         return ~reg;
8414 }
8415
8416 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8417 {
8418         /* accept or reject all multicast frames */
8419         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8420         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8421         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8422         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8423 }
8424
8425 static void __tg3_set_rx_mode(struct net_device *dev)
8426 {
8427         struct tg3 *tp = netdev_priv(dev);
8428         u32 rx_mode;
8429
8430         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8431                                   RX_MODE_KEEP_VLAN_TAG);
8432
8433         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8434          * flag clear.
8435          */
8436 #if TG3_VLAN_TAG_USED
8437         if (!tp->vlgrp &&
8438             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8439                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8440 #else
8441         /* By definition, VLAN is disabled always in this
8442          * case.
8443          */
8444         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8445                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8446 #endif
8447
8448         if (dev->flags & IFF_PROMISC) {
8449                 /* Promiscuous mode. */
8450                 rx_mode |= RX_MODE_PROMISC;
8451         } else if (dev->flags & IFF_ALLMULTI) {
8452                 /* Accept all multicast. */
8453                 tg3_set_multi (tp, 1);
8454         } else if (dev->mc_count < 1) {
8455                 /* Reject all multicast. */
8456                 tg3_set_multi (tp, 0);
8457         } else {
8458                 /* Accept one or more multicast(s). */
8459                 struct dev_mc_list *mclist;
8460                 unsigned int i;
8461                 u32 mc_filter[4] = { 0, };
8462                 u32 regidx;
8463                 u32 bit;
8464                 u32 crc;
8465
8466                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8467                      i++, mclist = mclist->next) {
8468
8469                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8470                         bit = ~crc & 0x7f;
8471                         regidx = (bit & 0x60) >> 5;
8472                         bit &= 0x1f;
8473                         mc_filter[regidx] |= (1 << bit);
8474                 }
8475
8476                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8477                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8478                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8479                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8480         }
8481
8482         if (rx_mode != tp->rx_mode) {
8483                 tp->rx_mode = rx_mode;
8484                 tw32_f(MAC_RX_MODE, rx_mode);
8485                 udelay(10);
8486         }
8487 }
8488
8489 static void tg3_set_rx_mode(struct net_device *dev)
8490 {
8491         struct tg3 *tp = netdev_priv(dev);
8492
8493         if (!netif_running(dev))
8494                 return;
8495
8496         tg3_full_lock(tp, 0);
8497         __tg3_set_rx_mode(dev);
8498         tg3_full_unlock(tp);
8499 }
8500
8501 #define TG3_REGDUMP_LEN         (32 * 1024)
8502
8503 static int tg3_get_regs_len(struct net_device *dev)
8504 {
8505         return TG3_REGDUMP_LEN;
8506 }
8507
8508 static void tg3_get_regs(struct net_device *dev,
8509                 struct ethtool_regs *regs, void *_p)
8510 {
8511         u32 *p = _p;
8512         struct tg3 *tp = netdev_priv(dev);
8513         u8 *orig_p = _p;
8514         int i;
8515
8516         regs->version = 0;
8517
8518         memset(p, 0, TG3_REGDUMP_LEN);
8519
8520         if (tp->link_config.phy_is_low_power)
8521                 return;
8522
8523         tg3_full_lock(tp, 0);
8524
8525 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8526 #define GET_REG32_LOOP(base,len)                \
8527 do {    p = (u32 *)(orig_p + (base));           \
8528         for (i = 0; i < len; i += 4)            \
8529                 __GET_REG32((base) + i);        \
8530 } while (0)
8531 #define GET_REG32_1(reg)                        \
8532 do {    p = (u32 *)(orig_p + (reg));            \
8533         __GET_REG32((reg));                     \
8534 } while (0)
8535
8536         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8537         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8538         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8539         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8540         GET_REG32_1(SNDDATAC_MODE);
8541         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8542         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8543         GET_REG32_1(SNDBDC_MODE);
8544         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8545         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8546         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8547         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8548         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8549         GET_REG32_1(RCVDCC_MODE);
8550         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8551         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8552         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8553         GET_REG32_1(MBFREE_MODE);
8554         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8555         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8556         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8557         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8558         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8559         GET_REG32_1(RX_CPU_MODE);
8560         GET_REG32_1(RX_CPU_STATE);
8561         GET_REG32_1(RX_CPU_PGMCTR);
8562         GET_REG32_1(RX_CPU_HWBKPT);
8563         GET_REG32_1(TX_CPU_MODE);
8564         GET_REG32_1(TX_CPU_STATE);
8565         GET_REG32_1(TX_CPU_PGMCTR);
8566         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8567         GET_REG32_LOOP(FTQ_RESET, 0x120);
8568         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8569         GET_REG32_1(DMAC_MODE);
8570         GET_REG32_LOOP(GRC_MODE, 0x4c);
8571         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8572                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8573
8574 #undef __GET_REG32
8575 #undef GET_REG32_LOOP
8576 #undef GET_REG32_1
8577
8578         tg3_full_unlock(tp);
8579 }
8580
8581 static int tg3_get_eeprom_len(struct net_device *dev)
8582 {
8583         struct tg3 *tp = netdev_priv(dev);
8584
8585         return tp->nvram_size;
8586 }
8587
8588 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8589 {
8590         struct tg3 *tp = netdev_priv(dev);
8591         int ret;
8592         u8  *pd;
8593         u32 i, offset, len, b_offset, b_count;
8594         __be32 val;
8595
8596         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8597                 return -EINVAL;
8598
8599         if (tp->link_config.phy_is_low_power)
8600                 return -EAGAIN;
8601
8602         offset = eeprom->offset;
8603         len = eeprom->len;
8604         eeprom->len = 0;
8605
8606         eeprom->magic = TG3_EEPROM_MAGIC;
8607
8608         if (offset & 3) {
8609                 /* adjustments to start on required 4 byte boundary */
8610                 b_offset = offset & 3;
8611                 b_count = 4 - b_offset;
8612                 if (b_count > len) {
8613                         /* i.e. offset=1 len=2 */
8614                         b_count = len;
8615                 }
8616                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8617                 if (ret)
8618                         return ret;
8619                 memcpy(data, ((char*)&val) + b_offset, b_count);
8620                 len -= b_count;
8621                 offset += b_count;
8622                 eeprom->len += b_count;
8623         }
8624
8625         /* read bytes upto the last 4 byte boundary */
8626         pd = &data[eeprom->len];
8627         for (i = 0; i < (len - (len & 3)); i += 4) {
8628                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8629                 if (ret) {
8630                         eeprom->len += i;
8631                         return ret;
8632                 }
8633                 memcpy(pd + i, &val, 4);
8634         }
8635         eeprom->len += i;
8636
8637         if (len & 3) {
8638                 /* read last bytes not ending on 4 byte boundary */
8639                 pd = &data[eeprom->len];
8640                 b_count = len & 3;
8641                 b_offset = offset + len - b_count;
8642                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8643                 if (ret)
8644                         return ret;
8645                 memcpy(pd, &val, b_count);
8646                 eeprom->len += b_count;
8647         }
8648         return 0;
8649 }
8650
8651 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8652
8653 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8654 {
8655         struct tg3 *tp = netdev_priv(dev);
8656         int ret;
8657         u32 offset, len, b_offset, odd_len;
8658         u8 *buf;
8659         __be32 start, end;
8660
8661         if (tp->link_config.phy_is_low_power)
8662                 return -EAGAIN;
8663
8664         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8665             eeprom->magic != TG3_EEPROM_MAGIC)
8666                 return -EINVAL;
8667
8668         offset = eeprom->offset;
8669         len = eeprom->len;
8670
8671         if ((b_offset = (offset & 3))) {
8672                 /* adjustments to start on required 4 byte boundary */
8673                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8674                 if (ret)
8675                         return ret;
8676                 len += b_offset;
8677                 offset &= ~3;
8678                 if (len < 4)
8679                         len = 4;
8680         }
8681
8682         odd_len = 0;
8683         if (len & 3) {
8684                 /* adjustments to end on required 4 byte boundary */
8685                 odd_len = 1;
8686                 len = (len + 3) & ~3;
8687                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8688                 if (ret)
8689                         return ret;
8690         }
8691
8692         buf = data;
8693         if (b_offset || odd_len) {
8694                 buf = kmalloc(len, GFP_KERNEL);
8695                 if (!buf)
8696                         return -ENOMEM;
8697                 if (b_offset)
8698                         memcpy(buf, &start, 4);
8699                 if (odd_len)
8700                         memcpy(buf+len-4, &end, 4);
8701                 memcpy(buf + b_offset, data, eeprom->len);
8702         }
8703
8704         ret = tg3_nvram_write_block(tp, offset, len, buf);
8705
8706         if (buf != data)
8707                 kfree(buf);
8708
8709         return ret;
8710 }
8711
8712 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8713 {
8714         struct tg3 *tp = netdev_priv(dev);
8715
8716         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8717                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8718                         return -EAGAIN;
8719                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8720         }
8721
8722         cmd->supported = (SUPPORTED_Autoneg);
8723
8724         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8725                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8726                                    SUPPORTED_1000baseT_Full);
8727
8728         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8729                 cmd->supported |= (SUPPORTED_100baseT_Half |
8730                                   SUPPORTED_100baseT_Full |
8731                                   SUPPORTED_10baseT_Half |
8732                                   SUPPORTED_10baseT_Full |
8733                                   SUPPORTED_TP);
8734                 cmd->port = PORT_TP;
8735         } else {
8736                 cmd->supported |= SUPPORTED_FIBRE;
8737                 cmd->port = PORT_FIBRE;
8738         }
8739
8740         cmd->advertising = tp->link_config.advertising;
8741         if (netif_running(dev)) {
8742                 cmd->speed = tp->link_config.active_speed;
8743                 cmd->duplex = tp->link_config.active_duplex;
8744         }
8745         cmd->phy_address = PHY_ADDR;
8746         cmd->transceiver = XCVR_INTERNAL;
8747         cmd->autoneg = tp->link_config.autoneg;
8748         cmd->maxtxpkt = 0;
8749         cmd->maxrxpkt = 0;
8750         return 0;
8751 }
8752
8753 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8754 {
8755         struct tg3 *tp = netdev_priv(dev);
8756
8757         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8758                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8759                         return -EAGAIN;
8760                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8761         }
8762
8763         if (cmd->autoneg != AUTONEG_ENABLE &&
8764             cmd->autoneg != AUTONEG_DISABLE)
8765                 return -EINVAL;
8766
8767         if (cmd->autoneg == AUTONEG_DISABLE &&
8768             cmd->duplex != DUPLEX_FULL &&
8769             cmd->duplex != DUPLEX_HALF)
8770                 return -EINVAL;
8771
8772         if (cmd->autoneg == AUTONEG_ENABLE) {
8773                 u32 mask = ADVERTISED_Autoneg |
8774                            ADVERTISED_Pause |
8775                            ADVERTISED_Asym_Pause;
8776
8777                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8778                         mask |= ADVERTISED_1000baseT_Half |
8779                                 ADVERTISED_1000baseT_Full;
8780
8781                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8782                         mask |= ADVERTISED_100baseT_Half |
8783                                 ADVERTISED_100baseT_Full |
8784                                 ADVERTISED_10baseT_Half |
8785                                 ADVERTISED_10baseT_Full |
8786                                 ADVERTISED_TP;
8787                 else
8788                         mask |= ADVERTISED_FIBRE;
8789
8790                 if (cmd->advertising & ~mask)
8791                         return -EINVAL;
8792
8793                 mask &= (ADVERTISED_1000baseT_Half |
8794                          ADVERTISED_1000baseT_Full |
8795                          ADVERTISED_100baseT_Half |
8796                          ADVERTISED_100baseT_Full |
8797                          ADVERTISED_10baseT_Half |
8798                          ADVERTISED_10baseT_Full);
8799
8800                 cmd->advertising &= mask;
8801         } else {
8802                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8803                         if (cmd->speed != SPEED_1000)
8804                                 return -EINVAL;
8805
8806                         if (cmd->duplex != DUPLEX_FULL)
8807                                 return -EINVAL;
8808                 } else {
8809                         if (cmd->speed != SPEED_100 &&
8810                             cmd->speed != SPEED_10)
8811                                 return -EINVAL;
8812                 }
8813         }
8814
8815         tg3_full_lock(tp, 0);
8816
8817         tp->link_config.autoneg = cmd->autoneg;
8818         if (cmd->autoneg == AUTONEG_ENABLE) {
8819                 tp->link_config.advertising = (cmd->advertising |
8820                                               ADVERTISED_Autoneg);
8821                 tp->link_config.speed = SPEED_INVALID;
8822                 tp->link_config.duplex = DUPLEX_INVALID;
8823         } else {
8824                 tp->link_config.advertising = 0;
8825                 tp->link_config.speed = cmd->speed;
8826                 tp->link_config.duplex = cmd->duplex;
8827         }
8828
8829         tp->link_config.orig_speed = tp->link_config.speed;
8830         tp->link_config.orig_duplex = tp->link_config.duplex;
8831         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8832
8833         if (netif_running(dev))
8834                 tg3_setup_phy(tp, 1);
8835
8836         tg3_full_unlock(tp);
8837
8838         return 0;
8839 }
8840
8841 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8842 {
8843         struct tg3 *tp = netdev_priv(dev);
8844
8845         strcpy(info->driver, DRV_MODULE_NAME);
8846         strcpy(info->version, DRV_MODULE_VERSION);
8847         strcpy(info->fw_version, tp->fw_ver);
8848         strcpy(info->bus_info, pci_name(tp->pdev));
8849 }
8850
8851 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8852 {
8853         struct tg3 *tp = netdev_priv(dev);
8854
8855         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8856             device_can_wakeup(&tp->pdev->dev))
8857                 wol->supported = WAKE_MAGIC;
8858         else
8859                 wol->supported = 0;
8860         wol->wolopts = 0;
8861         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8862             device_can_wakeup(&tp->pdev->dev))
8863                 wol->wolopts = WAKE_MAGIC;
8864         memset(&wol->sopass, 0, sizeof(wol->sopass));
8865 }
8866
8867 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8868 {
8869         struct tg3 *tp = netdev_priv(dev);
8870         struct device *dp = &tp->pdev->dev;
8871
8872         if (wol->wolopts & ~WAKE_MAGIC)
8873                 return -EINVAL;
8874         if ((wol->wolopts & WAKE_MAGIC) &&
8875             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8876                 return -EINVAL;
8877
8878         spin_lock_bh(&tp->lock);
8879         if (wol->wolopts & WAKE_MAGIC) {
8880                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8881                 device_set_wakeup_enable(dp, true);
8882         } else {
8883                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8884                 device_set_wakeup_enable(dp, false);
8885         }
8886         spin_unlock_bh(&tp->lock);
8887
8888         return 0;
8889 }
8890
8891 static u32 tg3_get_msglevel(struct net_device *dev)
8892 {
8893         struct tg3 *tp = netdev_priv(dev);
8894         return tp->msg_enable;
8895 }
8896
8897 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8898 {
8899         struct tg3 *tp = netdev_priv(dev);
8900         tp->msg_enable = value;
8901 }
8902
8903 static int tg3_set_tso(struct net_device *dev, u32 value)
8904 {
8905         struct tg3 *tp = netdev_priv(dev);
8906
8907         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8908                 if (value)
8909                         return -EINVAL;
8910                 return 0;
8911         }
8912         if ((dev->features & NETIF_F_IPV6_CSUM) &&
8913             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
8914                 if (value) {
8915                         dev->features |= NETIF_F_TSO6;
8916                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8917                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8918                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
8919                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8920                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8921                                 dev->features |= NETIF_F_TSO_ECN;
8922                 } else
8923                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8924         }
8925         return ethtool_op_set_tso(dev, value);
8926 }
8927
8928 static int tg3_nway_reset(struct net_device *dev)
8929 {
8930         struct tg3 *tp = netdev_priv(dev);
8931         int r;
8932
8933         if (!netif_running(dev))
8934                 return -EAGAIN;
8935
8936         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8937                 return -EINVAL;
8938
8939         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8940                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8941                         return -EAGAIN;
8942                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
8943         } else {
8944                 u32 bmcr;
8945
8946                 spin_lock_bh(&tp->lock);
8947                 r = -EINVAL;
8948                 tg3_readphy(tp, MII_BMCR, &bmcr);
8949                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8950                     ((bmcr & BMCR_ANENABLE) ||
8951                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8952                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8953                                                    BMCR_ANENABLE);
8954                         r = 0;
8955                 }
8956                 spin_unlock_bh(&tp->lock);
8957         }
8958
8959         return r;
8960 }
8961
8962 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8963 {
8964         struct tg3 *tp = netdev_priv(dev);
8965
8966         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8967         ering->rx_mini_max_pending = 0;
8968         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8969                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8970         else
8971                 ering->rx_jumbo_max_pending = 0;
8972
8973         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8974
8975         ering->rx_pending = tp->rx_pending;
8976         ering->rx_mini_pending = 0;
8977         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8978                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8979         else
8980                 ering->rx_jumbo_pending = 0;
8981
8982         ering->tx_pending = tp->tx_pending;
8983 }
8984
8985 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8986 {
8987         struct tg3 *tp = netdev_priv(dev);
8988         int irq_sync = 0, err = 0;
8989
8990         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8991             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8992             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8993             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8994             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8995              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8996                 return -EINVAL;
8997
8998         if (netif_running(dev)) {
8999                 tg3_phy_stop(tp);
9000                 tg3_netif_stop(tp);
9001                 irq_sync = 1;
9002         }
9003
9004         tg3_full_lock(tp, irq_sync);
9005
9006         tp->rx_pending = ering->rx_pending;
9007
9008         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9009             tp->rx_pending > 63)
9010                 tp->rx_pending = 63;
9011         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9012         tp->tx_pending = ering->tx_pending;
9013
9014         if (netif_running(dev)) {
9015                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9016                 err = tg3_restart_hw(tp, 1);
9017                 if (!err)
9018                         tg3_netif_start(tp);
9019         }
9020
9021         tg3_full_unlock(tp);
9022
9023         if (irq_sync && !err)
9024                 tg3_phy_start(tp);
9025
9026         return err;
9027 }
9028
9029 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9030 {
9031         struct tg3 *tp = netdev_priv(dev);
9032
9033         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9034
9035         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9036                 epause->rx_pause = 1;
9037         else
9038                 epause->rx_pause = 0;
9039
9040         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9041                 epause->tx_pause = 1;
9042         else
9043                 epause->tx_pause = 0;
9044 }
9045
9046 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9047 {
9048         struct tg3 *tp = netdev_priv(dev);
9049         int err = 0;
9050
9051         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9052                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9053                         return -EAGAIN;
9054
9055                 if (epause->autoneg) {
9056                         u32 newadv;
9057                         struct phy_device *phydev;
9058
9059                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9060
9061                         if (epause->rx_pause) {
9062                                 if (epause->tx_pause)
9063                                         newadv = ADVERTISED_Pause;
9064                                 else
9065                                         newadv = ADVERTISED_Pause |
9066                                                  ADVERTISED_Asym_Pause;
9067                         } else if (epause->tx_pause) {
9068                                 newadv = ADVERTISED_Asym_Pause;
9069                         } else
9070                                 newadv = 0;
9071
9072                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9073                                 u32 oldadv = phydev->advertising &
9074                                              (ADVERTISED_Pause |
9075                                               ADVERTISED_Asym_Pause);
9076                                 if (oldadv != newadv) {
9077                                         phydev->advertising &=
9078                                                 ~(ADVERTISED_Pause |
9079                                                   ADVERTISED_Asym_Pause);
9080                                         phydev->advertising |= newadv;
9081                                         err = phy_start_aneg(phydev);
9082                                 }
9083                         } else {
9084                                 tp->link_config.advertising &=
9085                                                 ~(ADVERTISED_Pause |
9086                                                   ADVERTISED_Asym_Pause);
9087                                 tp->link_config.advertising |= newadv;
9088                         }
9089                 } else {
9090                         if (epause->rx_pause)
9091                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9092                         else
9093                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9094
9095                         if (epause->tx_pause)
9096                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9097                         else
9098                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9099
9100                         if (netif_running(dev))
9101                                 tg3_setup_flow_control(tp, 0, 0);
9102                 }
9103         } else {
9104                 int irq_sync = 0;
9105
9106                 if (netif_running(dev)) {
9107                         tg3_netif_stop(tp);
9108                         irq_sync = 1;
9109                 }
9110
9111                 tg3_full_lock(tp, irq_sync);
9112
9113                 if (epause->autoneg)
9114                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9115                 else
9116                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9117                 if (epause->rx_pause)
9118                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9119                 else
9120                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9121                 if (epause->tx_pause)
9122                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9123                 else
9124                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9125
9126                 if (netif_running(dev)) {
9127                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9128                         err = tg3_restart_hw(tp, 1);
9129                         if (!err)
9130                                 tg3_netif_start(tp);
9131                 }
9132
9133                 tg3_full_unlock(tp);
9134         }
9135
9136         return err;
9137 }
9138
9139 static u32 tg3_get_rx_csum(struct net_device *dev)
9140 {
9141         struct tg3 *tp = netdev_priv(dev);
9142         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9143 }
9144
9145 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9146 {
9147         struct tg3 *tp = netdev_priv(dev);
9148
9149         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9150                 if (data != 0)
9151                         return -EINVAL;
9152                 return 0;
9153         }
9154
9155         spin_lock_bh(&tp->lock);
9156         if (data)
9157                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9158         else
9159                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9160         spin_unlock_bh(&tp->lock);
9161
9162         return 0;
9163 }
9164
9165 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9166 {
9167         struct tg3 *tp = netdev_priv(dev);
9168
9169         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9170                 if (data != 0)
9171                         return -EINVAL;
9172                 return 0;
9173         }
9174
9175         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9176                 ethtool_op_set_tx_ipv6_csum(dev, data);
9177         else
9178                 ethtool_op_set_tx_csum(dev, data);
9179
9180         return 0;
9181 }
9182
9183 static int tg3_get_sset_count (struct net_device *dev, int sset)
9184 {
9185         switch (sset) {
9186         case ETH_SS_TEST:
9187                 return TG3_NUM_TEST;
9188         case ETH_SS_STATS:
9189                 return TG3_NUM_STATS;
9190         default:
9191                 return -EOPNOTSUPP;
9192         }
9193 }
9194
9195 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9196 {
9197         switch (stringset) {
9198         case ETH_SS_STATS:
9199                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9200                 break;
9201         case ETH_SS_TEST:
9202                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9203                 break;
9204         default:
9205                 WARN_ON(1);     /* we need a WARN() */
9206                 break;
9207         }
9208 }
9209
9210 static int tg3_phys_id(struct net_device *dev, u32 data)
9211 {
9212         struct tg3 *tp = netdev_priv(dev);
9213         int i;
9214
9215         if (!netif_running(tp->dev))
9216                 return -EAGAIN;
9217
9218         if (data == 0)
9219                 data = UINT_MAX / 2;
9220
9221         for (i = 0; i < (data * 2); i++) {
9222                 if ((i % 2) == 0)
9223                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9224                                            LED_CTRL_1000MBPS_ON |
9225                                            LED_CTRL_100MBPS_ON |
9226                                            LED_CTRL_10MBPS_ON |
9227                                            LED_CTRL_TRAFFIC_OVERRIDE |
9228                                            LED_CTRL_TRAFFIC_BLINK |
9229                                            LED_CTRL_TRAFFIC_LED);
9230
9231                 else
9232                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9233                                            LED_CTRL_TRAFFIC_OVERRIDE);
9234
9235                 if (msleep_interruptible(500))
9236                         break;
9237         }
9238         tw32(MAC_LED_CTRL, tp->led_ctrl);
9239         return 0;
9240 }
9241
9242 static void tg3_get_ethtool_stats (struct net_device *dev,
9243                                    struct ethtool_stats *estats, u64 *tmp_stats)
9244 {
9245         struct tg3 *tp = netdev_priv(dev);
9246         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9247 }
9248
9249 #define NVRAM_TEST_SIZE 0x100
9250 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9251 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9252 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9253 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9254 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9255
9256 static int tg3_test_nvram(struct tg3 *tp)
9257 {
9258         u32 csum, magic;
9259         __be32 *buf;
9260         int i, j, k, err = 0, size;
9261
9262         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9263                 return 0;
9264
9265         if (tg3_nvram_read(tp, 0, &magic) != 0)
9266                 return -EIO;
9267
9268         if (magic == TG3_EEPROM_MAGIC)
9269                 size = NVRAM_TEST_SIZE;
9270         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9271                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9272                     TG3_EEPROM_SB_FORMAT_1) {
9273                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9274                         case TG3_EEPROM_SB_REVISION_0:
9275                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9276                                 break;
9277                         case TG3_EEPROM_SB_REVISION_2:
9278                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9279                                 break;
9280                         case TG3_EEPROM_SB_REVISION_3:
9281                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9282                                 break;
9283                         default:
9284                                 return 0;
9285                         }
9286                 } else
9287                         return 0;
9288         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9289                 size = NVRAM_SELFBOOT_HW_SIZE;
9290         else
9291                 return -EIO;
9292
9293         buf = kmalloc(size, GFP_KERNEL);
9294         if (buf == NULL)
9295                 return -ENOMEM;
9296
9297         err = -EIO;
9298         for (i = 0, j = 0; i < size; i += 4, j++) {
9299                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9300                 if (err)
9301                         break;
9302         }
9303         if (i < size)
9304                 goto out;
9305
9306         /* Selfboot format */
9307         magic = be32_to_cpu(buf[0]);
9308         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9309             TG3_EEPROM_MAGIC_FW) {
9310                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9311
9312                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9313                     TG3_EEPROM_SB_REVISION_2) {
9314                         /* For rev 2, the csum doesn't include the MBA. */
9315                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9316                                 csum8 += buf8[i];
9317                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9318                                 csum8 += buf8[i];
9319                 } else {
9320                         for (i = 0; i < size; i++)
9321                                 csum8 += buf8[i];
9322                 }
9323
9324                 if (csum8 == 0) {
9325                         err = 0;
9326                         goto out;
9327                 }
9328
9329                 err = -EIO;
9330                 goto out;
9331         }
9332
9333         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9334             TG3_EEPROM_MAGIC_HW) {
9335                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9336                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9337                 u8 *buf8 = (u8 *) buf;
9338
9339                 /* Separate the parity bits and the data bytes.  */
9340                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9341                         if ((i == 0) || (i == 8)) {
9342                                 int l;
9343                                 u8 msk;
9344
9345                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9346                                         parity[k++] = buf8[i] & msk;
9347                                 i++;
9348                         }
9349                         else if (i == 16) {
9350                                 int l;
9351                                 u8 msk;
9352
9353                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9354                                         parity[k++] = buf8[i] & msk;
9355                                 i++;
9356
9357                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9358                                         parity[k++] = buf8[i] & msk;
9359                                 i++;
9360                         }
9361                         data[j++] = buf8[i];
9362                 }
9363
9364                 err = -EIO;
9365                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9366                         u8 hw8 = hweight8(data[i]);
9367
9368                         if ((hw8 & 0x1) && parity[i])
9369                                 goto out;
9370                         else if (!(hw8 & 0x1) && !parity[i])
9371                                 goto out;
9372                 }
9373                 err = 0;
9374                 goto out;
9375         }
9376
9377         /* Bootstrap checksum at offset 0x10 */
9378         csum = calc_crc((unsigned char *) buf, 0x10);
9379         if (csum != be32_to_cpu(buf[0x10/4]))
9380                 goto out;
9381
9382         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9383         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9384         if (csum != be32_to_cpu(buf[0xfc/4]))
9385                 goto out;
9386
9387         err = 0;
9388
9389 out:
9390         kfree(buf);
9391         return err;
9392 }
9393
9394 #define TG3_SERDES_TIMEOUT_SEC  2
9395 #define TG3_COPPER_TIMEOUT_SEC  6
9396
9397 static int tg3_test_link(struct tg3 *tp)
9398 {
9399         int i, max;
9400
9401         if (!netif_running(tp->dev))
9402                 return -ENODEV;
9403
9404         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9405                 max = TG3_SERDES_TIMEOUT_SEC;
9406         else
9407                 max = TG3_COPPER_TIMEOUT_SEC;
9408
9409         for (i = 0; i < max; i++) {
9410                 if (netif_carrier_ok(tp->dev))
9411                         return 0;
9412
9413                 if (msleep_interruptible(1000))
9414                         break;
9415         }
9416
9417         return -EIO;
9418 }
9419
9420 /* Only test the commonly used registers */
9421 static int tg3_test_registers(struct tg3 *tp)
9422 {
9423         int i, is_5705, is_5750;
9424         u32 offset, read_mask, write_mask, val, save_val, read_val;
9425         static struct {
9426                 u16 offset;
9427                 u16 flags;
9428 #define TG3_FL_5705     0x1
9429 #define TG3_FL_NOT_5705 0x2
9430 #define TG3_FL_NOT_5788 0x4
9431 #define TG3_FL_NOT_5750 0x8
9432                 u32 read_mask;
9433                 u32 write_mask;
9434         } reg_tbl[] = {
9435                 /* MAC Control Registers */
9436                 { MAC_MODE, TG3_FL_NOT_5705,
9437                         0x00000000, 0x00ef6f8c },
9438                 { MAC_MODE, TG3_FL_5705,
9439                         0x00000000, 0x01ef6b8c },
9440                 { MAC_STATUS, TG3_FL_NOT_5705,
9441                         0x03800107, 0x00000000 },
9442                 { MAC_STATUS, TG3_FL_5705,
9443                         0x03800100, 0x00000000 },
9444                 { MAC_ADDR_0_HIGH, 0x0000,
9445                         0x00000000, 0x0000ffff },
9446                 { MAC_ADDR_0_LOW, 0x0000,
9447                         0x00000000, 0xffffffff },
9448                 { MAC_RX_MTU_SIZE, 0x0000,
9449                         0x00000000, 0x0000ffff },
9450                 { MAC_TX_MODE, 0x0000,
9451                         0x00000000, 0x00000070 },
9452                 { MAC_TX_LENGTHS, 0x0000,
9453                         0x00000000, 0x00003fff },
9454                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9455                         0x00000000, 0x000007fc },
9456                 { MAC_RX_MODE, TG3_FL_5705,
9457                         0x00000000, 0x000007dc },
9458                 { MAC_HASH_REG_0, 0x0000,
9459                         0x00000000, 0xffffffff },
9460                 { MAC_HASH_REG_1, 0x0000,
9461                         0x00000000, 0xffffffff },
9462                 { MAC_HASH_REG_2, 0x0000,
9463                         0x00000000, 0xffffffff },
9464                 { MAC_HASH_REG_3, 0x0000,
9465                         0x00000000, 0xffffffff },
9466
9467                 /* Receive Data and Receive BD Initiator Control Registers. */
9468                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9469                         0x00000000, 0xffffffff },
9470                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9471                         0x00000000, 0xffffffff },
9472                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9473                         0x00000000, 0x00000003 },
9474                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9475                         0x00000000, 0xffffffff },
9476                 { RCVDBDI_STD_BD+0, 0x0000,
9477                         0x00000000, 0xffffffff },
9478                 { RCVDBDI_STD_BD+4, 0x0000,
9479                         0x00000000, 0xffffffff },
9480                 { RCVDBDI_STD_BD+8, 0x0000,
9481                         0x00000000, 0xffff0002 },
9482                 { RCVDBDI_STD_BD+0xc, 0x0000,
9483                         0x00000000, 0xffffffff },
9484
9485                 /* Receive BD Initiator Control Registers. */
9486                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9487                         0x00000000, 0xffffffff },
9488                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9489                         0x00000000, 0x000003ff },
9490                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9491                         0x00000000, 0xffffffff },
9492
9493                 /* Host Coalescing Control Registers. */
9494                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9495                         0x00000000, 0x00000004 },
9496                 { HOSTCC_MODE, TG3_FL_5705,
9497                         0x00000000, 0x000000f6 },
9498                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9499                         0x00000000, 0xffffffff },
9500                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9501                         0x00000000, 0x000003ff },
9502                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9503                         0x00000000, 0xffffffff },
9504                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9505                         0x00000000, 0x000003ff },
9506                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9507                         0x00000000, 0xffffffff },
9508                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9509                         0x00000000, 0x000000ff },
9510                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9511                         0x00000000, 0xffffffff },
9512                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9513                         0x00000000, 0x000000ff },
9514                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9515                         0x00000000, 0xffffffff },
9516                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9517                         0x00000000, 0xffffffff },
9518                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9519                         0x00000000, 0xffffffff },
9520                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9521                         0x00000000, 0x000000ff },
9522                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9523                         0x00000000, 0xffffffff },
9524                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9525                         0x00000000, 0x000000ff },
9526                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9527                         0x00000000, 0xffffffff },
9528                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9529                         0x00000000, 0xffffffff },
9530                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9531                         0x00000000, 0xffffffff },
9532                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9533                         0x00000000, 0xffffffff },
9534                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9535                         0x00000000, 0xffffffff },
9536                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9537                         0xffffffff, 0x00000000 },
9538                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9539                         0xffffffff, 0x00000000 },
9540
9541                 /* Buffer Manager Control Registers. */
9542                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9543                         0x00000000, 0x007fff80 },
9544                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9545                         0x00000000, 0x007fffff },
9546                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9547                         0x00000000, 0x0000003f },
9548                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9549                         0x00000000, 0x000001ff },
9550                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9551                         0x00000000, 0x000001ff },
9552                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9553                         0xffffffff, 0x00000000 },
9554                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9555                         0xffffffff, 0x00000000 },
9556
9557                 /* Mailbox Registers */
9558                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9559                         0x00000000, 0x000001ff },
9560                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9561                         0x00000000, 0x000001ff },
9562                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9563                         0x00000000, 0x000007ff },
9564                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9565                         0x00000000, 0x000001ff },
9566
9567                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9568         };
9569
9570         is_5705 = is_5750 = 0;
9571         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9572                 is_5705 = 1;
9573                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9574                         is_5750 = 1;
9575         }
9576
9577         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9578                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9579                         continue;
9580
9581                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9582                         continue;
9583
9584                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9585                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9586                         continue;
9587
9588                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9589                         continue;
9590
9591                 offset = (u32) reg_tbl[i].offset;
9592                 read_mask = reg_tbl[i].read_mask;
9593                 write_mask = reg_tbl[i].write_mask;
9594
9595                 /* Save the original register content */
9596                 save_val = tr32(offset);
9597
9598                 /* Determine the read-only value. */
9599                 read_val = save_val & read_mask;
9600
9601                 /* Write zero to the register, then make sure the read-only bits
9602                  * are not changed and the read/write bits are all zeros.
9603                  */
9604                 tw32(offset, 0);
9605
9606                 val = tr32(offset);
9607
9608                 /* Test the read-only and read/write bits. */
9609                 if (((val & read_mask) != read_val) || (val & write_mask))
9610                         goto out;
9611
9612                 /* Write ones to all the bits defined by RdMask and WrMask, then
9613                  * make sure the read-only bits are not changed and the
9614                  * read/write bits are all ones.
9615                  */
9616                 tw32(offset, read_mask | write_mask);
9617
9618                 val = tr32(offset);
9619
9620                 /* Test the read-only bits. */
9621                 if ((val & read_mask) != read_val)
9622                         goto out;
9623
9624                 /* Test the read/write bits. */
9625                 if ((val & write_mask) != write_mask)
9626                         goto out;
9627
9628                 tw32(offset, save_val);
9629         }
9630
9631         return 0;
9632
9633 out:
9634         if (netif_msg_hw(tp))
9635                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9636                        offset);
9637         tw32(offset, save_val);
9638         return -EIO;
9639 }
9640
9641 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9642 {
9643         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9644         int i;
9645         u32 j;
9646
9647         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9648                 for (j = 0; j < len; j += 4) {
9649                         u32 val;
9650
9651                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9652                         tg3_read_mem(tp, offset + j, &val);
9653                         if (val != test_pattern[i])
9654                                 return -EIO;
9655                 }
9656         }
9657         return 0;
9658 }
9659
9660 static int tg3_test_memory(struct tg3 *tp)
9661 {
9662         static struct mem_entry {
9663                 u32 offset;
9664                 u32 len;
9665         } mem_tbl_570x[] = {
9666                 { 0x00000000, 0x00b50},
9667                 { 0x00002000, 0x1c000},
9668                 { 0xffffffff, 0x00000}
9669         }, mem_tbl_5705[] = {
9670                 { 0x00000100, 0x0000c},
9671                 { 0x00000200, 0x00008},
9672                 { 0x00004000, 0x00800},
9673                 { 0x00006000, 0x01000},
9674                 { 0x00008000, 0x02000},
9675                 { 0x00010000, 0x0e000},
9676                 { 0xffffffff, 0x00000}
9677         }, mem_tbl_5755[] = {
9678                 { 0x00000200, 0x00008},
9679                 { 0x00004000, 0x00800},
9680                 { 0x00006000, 0x00800},
9681                 { 0x00008000, 0x02000},
9682                 { 0x00010000, 0x0c000},
9683                 { 0xffffffff, 0x00000}
9684         }, mem_tbl_5906[] = {
9685                 { 0x00000200, 0x00008},
9686                 { 0x00004000, 0x00400},
9687                 { 0x00006000, 0x00400},
9688                 { 0x00008000, 0x01000},
9689                 { 0x00010000, 0x01000},
9690                 { 0xffffffff, 0x00000}
9691         };
9692         struct mem_entry *mem_tbl;
9693         int err = 0;
9694         int i;
9695
9696         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9697                 mem_tbl = mem_tbl_5755;
9698         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9699                 mem_tbl = mem_tbl_5906;
9700         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9701                 mem_tbl = mem_tbl_5705;
9702         else
9703                 mem_tbl = mem_tbl_570x;
9704
9705         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9706                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9707                     mem_tbl[i].len)) != 0)
9708                         break;
9709         }
9710
9711         return err;
9712 }
9713
9714 #define TG3_MAC_LOOPBACK        0
9715 #define TG3_PHY_LOOPBACK        1
9716
9717 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9718 {
9719         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9720         u32 desc_idx;
9721         struct sk_buff *skb, *rx_skb;
9722         u8 *tx_data;
9723         dma_addr_t map;
9724         int num_pkts, tx_len, rx_len, i, err;
9725         struct tg3_rx_buffer_desc *desc;
9726
9727         if (loopback_mode == TG3_MAC_LOOPBACK) {
9728                 /* HW errata - mac loopback fails in some cases on 5780.
9729                  * Normal traffic and PHY loopback are not affected by
9730                  * errata.
9731                  */
9732                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9733                         return 0;
9734
9735                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9736                            MAC_MODE_PORT_INT_LPBACK;
9737                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9738                         mac_mode |= MAC_MODE_LINK_POLARITY;
9739                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9740                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9741                 else
9742                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9743                 tw32(MAC_MODE, mac_mode);
9744         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9745                 u32 val;
9746
9747                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9748                         u32 phytest;
9749
9750                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9751                                 u32 phy;
9752
9753                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9754                                              phytest | MII_TG3_EPHY_SHADOW_EN);
9755                                 if (!tg3_readphy(tp, 0x1b, &phy))
9756                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
9757                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9758                         }
9759                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9760                 } else
9761                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9762
9763                 tg3_phy_toggle_automdix(tp, 0);
9764
9765                 tg3_writephy(tp, MII_BMCR, val);
9766                 udelay(40);
9767
9768                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9769                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9770                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9771                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9772                 } else
9773                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9774
9775                 /* reset to prevent losing 1st rx packet intermittently */
9776                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9777                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9778                         udelay(10);
9779                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9780                 }
9781                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9782                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9783                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9784                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9785                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9786                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9787                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9788                 }
9789                 tw32(MAC_MODE, mac_mode);
9790         }
9791         else
9792                 return -EINVAL;
9793
9794         err = -EIO;
9795
9796         tx_len = 1514;
9797         skb = netdev_alloc_skb(tp->dev, tx_len);
9798         if (!skb)
9799                 return -ENOMEM;
9800
9801         tx_data = skb_put(skb, tx_len);
9802         memcpy(tx_data, tp->dev->dev_addr, 6);
9803         memset(tx_data + 6, 0x0, 8);
9804
9805         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9806
9807         for (i = 14; i < tx_len; i++)
9808                 tx_data[i] = (u8) (i & 0xff);
9809
9810         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9811
9812         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9813              HOSTCC_MODE_NOW);
9814
9815         udelay(10);
9816
9817         rx_start_idx = tp->hw_status->idx[0].rx_producer;
9818
9819         num_pkts = 0;
9820
9821         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9822
9823         tp->tx_prod++;
9824         num_pkts++;
9825
9826         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9827                      tp->tx_prod);
9828         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9829
9830         udelay(10);
9831
9832         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
9833         for (i = 0; i < 25; i++) {
9834                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9835                        HOSTCC_MODE_NOW);
9836
9837                 udelay(10);
9838
9839                 tx_idx = tp->hw_status->idx[0].tx_consumer;
9840                 rx_idx = tp->hw_status->idx[0].rx_producer;
9841                 if ((tx_idx == tp->tx_prod) &&
9842                     (rx_idx == (rx_start_idx + num_pkts)))
9843                         break;
9844         }
9845
9846         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9847         dev_kfree_skb(skb);
9848
9849         if (tx_idx != tp->tx_prod)
9850                 goto out;
9851
9852         if (rx_idx != rx_start_idx + num_pkts)
9853                 goto out;
9854
9855         desc = &tp->rx_rcb[rx_start_idx];
9856         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9857         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9858         if (opaque_key != RXD_OPAQUE_RING_STD)
9859                 goto out;
9860
9861         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9862             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9863                 goto out;
9864
9865         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9866         if (rx_len != tx_len)
9867                 goto out;
9868
9869         rx_skb = tp->rx_std_buffers[desc_idx].skb;
9870
9871         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9872         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9873
9874         for (i = 14; i < tx_len; i++) {
9875                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9876                         goto out;
9877         }
9878         err = 0;
9879
9880         /* tg3_free_rings will unmap and free the rx_skb */
9881 out:
9882         return err;
9883 }
9884
9885 #define TG3_MAC_LOOPBACK_FAILED         1
9886 #define TG3_PHY_LOOPBACK_FAILED         2
9887 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
9888                                          TG3_PHY_LOOPBACK_FAILED)
9889
9890 static int tg3_test_loopback(struct tg3 *tp)
9891 {
9892         int err = 0;
9893         u32 cpmuctrl = 0;
9894
9895         if (!netif_running(tp->dev))
9896                 return TG3_LOOPBACK_FAILED;
9897
9898         err = tg3_reset_hw(tp, 1);
9899         if (err)
9900                 return TG3_LOOPBACK_FAILED;
9901
9902         /* Turn off gphy autopowerdown. */
9903         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9904                 tg3_phy_toggle_apd(tp, false);
9905
9906         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9907                 int i;
9908                 u32 status;
9909
9910                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9911
9912                 /* Wait for up to 40 microseconds to acquire lock. */
9913                 for (i = 0; i < 4; i++) {
9914                         status = tr32(TG3_CPMU_MUTEX_GNT);
9915                         if (status == CPMU_MUTEX_GNT_DRIVER)
9916                                 break;
9917                         udelay(10);
9918                 }
9919
9920                 if (status != CPMU_MUTEX_GNT_DRIVER)
9921                         return TG3_LOOPBACK_FAILED;
9922
9923                 /* Turn off link-based power management. */
9924                 cpmuctrl = tr32(TG3_CPMU_CTRL);
9925                 tw32(TG3_CPMU_CTRL,
9926                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9927                                   CPMU_CTRL_LINK_AWARE_MODE));
9928         }
9929
9930         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9931                 err |= TG3_MAC_LOOPBACK_FAILED;
9932
9933         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9934                 tw32(TG3_CPMU_CTRL, cpmuctrl);
9935
9936                 /* Release the mutex */
9937                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9938         }
9939
9940         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9941             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9942                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9943                         err |= TG3_PHY_LOOPBACK_FAILED;
9944         }
9945
9946         /* Re-enable gphy autopowerdown. */
9947         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9948                 tg3_phy_toggle_apd(tp, true);
9949
9950         return err;
9951 }
9952
9953 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9954                           u64 *data)
9955 {
9956         struct tg3 *tp = netdev_priv(dev);
9957
9958         if (tp->link_config.phy_is_low_power)
9959                 tg3_set_power_state(tp, PCI_D0);
9960
9961         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9962
9963         if (tg3_test_nvram(tp) != 0) {
9964                 etest->flags |= ETH_TEST_FL_FAILED;
9965                 data[0] = 1;
9966         }
9967         if (tg3_test_link(tp) != 0) {
9968                 etest->flags |= ETH_TEST_FL_FAILED;
9969                 data[1] = 1;
9970         }
9971         if (etest->flags & ETH_TEST_FL_OFFLINE) {
9972                 int err, err2 = 0, irq_sync = 0;
9973
9974                 if (netif_running(dev)) {
9975                         tg3_phy_stop(tp);
9976                         tg3_netif_stop(tp);
9977                         irq_sync = 1;
9978                 }
9979
9980                 tg3_full_lock(tp, irq_sync);
9981
9982                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9983                 err = tg3_nvram_lock(tp);
9984                 tg3_halt_cpu(tp, RX_CPU_BASE);
9985                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9986                         tg3_halt_cpu(tp, TX_CPU_BASE);
9987                 if (!err)
9988                         tg3_nvram_unlock(tp);
9989
9990                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9991                         tg3_phy_reset(tp);
9992
9993                 if (tg3_test_registers(tp) != 0) {
9994                         etest->flags |= ETH_TEST_FL_FAILED;
9995                         data[2] = 1;
9996                 }
9997                 if (tg3_test_memory(tp) != 0) {
9998                         etest->flags |= ETH_TEST_FL_FAILED;
9999                         data[3] = 1;
10000                 }
10001                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10002                         etest->flags |= ETH_TEST_FL_FAILED;
10003
10004                 tg3_full_unlock(tp);
10005
10006                 if (tg3_test_interrupt(tp) != 0) {
10007                         etest->flags |= ETH_TEST_FL_FAILED;
10008                         data[5] = 1;
10009                 }
10010
10011                 tg3_full_lock(tp, 0);
10012
10013                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10014                 if (netif_running(dev)) {
10015                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10016                         err2 = tg3_restart_hw(tp, 1);
10017                         if (!err2)
10018                                 tg3_netif_start(tp);
10019                 }
10020
10021                 tg3_full_unlock(tp);
10022
10023                 if (irq_sync && !err2)
10024                         tg3_phy_start(tp);
10025         }
10026         if (tp->link_config.phy_is_low_power)
10027                 tg3_set_power_state(tp, PCI_D3hot);
10028
10029 }
10030
10031 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10032 {
10033         struct mii_ioctl_data *data = if_mii(ifr);
10034         struct tg3 *tp = netdev_priv(dev);
10035         int err;
10036
10037         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10038                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10039                         return -EAGAIN;
10040                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10041         }
10042
10043         switch(cmd) {
10044         case SIOCGMIIPHY:
10045                 data->phy_id = PHY_ADDR;
10046
10047                 /* fallthru */
10048         case SIOCGMIIREG: {
10049                 u32 mii_regval;
10050
10051                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10052                         break;                  /* We have no PHY */
10053
10054                 if (tp->link_config.phy_is_low_power)
10055                         return -EAGAIN;
10056
10057                 spin_lock_bh(&tp->lock);
10058                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10059                 spin_unlock_bh(&tp->lock);
10060
10061                 data->val_out = mii_regval;
10062
10063                 return err;
10064         }
10065
10066         case SIOCSMIIREG:
10067                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10068                         break;                  /* We have no PHY */
10069
10070                 if (!capable(CAP_NET_ADMIN))
10071                         return -EPERM;
10072
10073                 if (tp->link_config.phy_is_low_power)
10074                         return -EAGAIN;
10075
10076                 spin_lock_bh(&tp->lock);
10077                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10078                 spin_unlock_bh(&tp->lock);
10079
10080                 return err;
10081
10082         default:
10083                 /* do nothing */
10084                 break;
10085         }
10086         return -EOPNOTSUPP;
10087 }
10088
10089 #if TG3_VLAN_TAG_USED
10090 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10091 {
10092         struct tg3 *tp = netdev_priv(dev);
10093
10094         if (!netif_running(dev)) {
10095                 tp->vlgrp = grp;
10096                 return;
10097         }
10098
10099         tg3_netif_stop(tp);
10100
10101         tg3_full_lock(tp, 0);
10102
10103         tp->vlgrp = grp;
10104
10105         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10106         __tg3_set_rx_mode(dev);
10107
10108         tg3_netif_start(tp);
10109
10110         tg3_full_unlock(tp);
10111 }
10112 #endif
10113
10114 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10115 {
10116         struct tg3 *tp = netdev_priv(dev);
10117
10118         memcpy(ec, &tp->coal, sizeof(*ec));
10119         return 0;
10120 }
10121
10122 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10123 {
10124         struct tg3 *tp = netdev_priv(dev);
10125         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10126         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10127
10128         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10129                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10130                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10131                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10132                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10133         }
10134
10135         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10136             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10137             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10138             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10139             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10140             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10141             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10142             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10143             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10144             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10145                 return -EINVAL;
10146
10147         /* No rx interrupts will be generated if both are zero */
10148         if ((ec->rx_coalesce_usecs == 0) &&
10149             (ec->rx_max_coalesced_frames == 0))
10150                 return -EINVAL;
10151
10152         /* No tx interrupts will be generated if both are zero */
10153         if ((ec->tx_coalesce_usecs == 0) &&
10154             (ec->tx_max_coalesced_frames == 0))
10155                 return -EINVAL;
10156
10157         /* Only copy relevant parameters, ignore all others. */
10158         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10159         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10160         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10161         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10162         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10163         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10164         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10165         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10166         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10167
10168         if (netif_running(dev)) {
10169                 tg3_full_lock(tp, 0);
10170                 __tg3_set_coalesce(tp, &tp->coal);
10171                 tg3_full_unlock(tp);
10172         }
10173         return 0;
10174 }
10175
10176 static const struct ethtool_ops tg3_ethtool_ops = {
10177         .get_settings           = tg3_get_settings,
10178         .set_settings           = tg3_set_settings,
10179         .get_drvinfo            = tg3_get_drvinfo,
10180         .get_regs_len           = tg3_get_regs_len,
10181         .get_regs               = tg3_get_regs,
10182         .get_wol                = tg3_get_wol,
10183         .set_wol                = tg3_set_wol,
10184         .get_msglevel           = tg3_get_msglevel,
10185         .set_msglevel           = tg3_set_msglevel,
10186         .nway_reset             = tg3_nway_reset,
10187         .get_link               = ethtool_op_get_link,
10188         .get_eeprom_len         = tg3_get_eeprom_len,
10189         .get_eeprom             = tg3_get_eeprom,
10190         .set_eeprom             = tg3_set_eeprom,
10191         .get_ringparam          = tg3_get_ringparam,
10192         .set_ringparam          = tg3_set_ringparam,
10193         .get_pauseparam         = tg3_get_pauseparam,
10194         .set_pauseparam         = tg3_set_pauseparam,
10195         .get_rx_csum            = tg3_get_rx_csum,
10196         .set_rx_csum            = tg3_set_rx_csum,
10197         .set_tx_csum            = tg3_set_tx_csum,
10198         .set_sg                 = ethtool_op_set_sg,
10199         .set_tso                = tg3_set_tso,
10200         .self_test              = tg3_self_test,
10201         .get_strings            = tg3_get_strings,
10202         .phys_id                = tg3_phys_id,
10203         .get_ethtool_stats      = tg3_get_ethtool_stats,
10204         .get_coalesce           = tg3_get_coalesce,
10205         .set_coalesce           = tg3_set_coalesce,
10206         .get_sset_count         = tg3_get_sset_count,
10207 };
10208
10209 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10210 {
10211         u32 cursize, val, magic;
10212
10213         tp->nvram_size = EEPROM_CHIP_SIZE;
10214
10215         if (tg3_nvram_read(tp, 0, &magic) != 0)
10216                 return;
10217
10218         if ((magic != TG3_EEPROM_MAGIC) &&
10219             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10220             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10221                 return;
10222
10223         /*
10224          * Size the chip by reading offsets at increasing powers of two.
10225          * When we encounter our validation signature, we know the addressing
10226          * has wrapped around, and thus have our chip size.
10227          */
10228         cursize = 0x10;
10229
10230         while (cursize < tp->nvram_size) {
10231                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10232                         return;
10233
10234                 if (val == magic)
10235                         break;
10236
10237                 cursize <<= 1;
10238         }
10239
10240         tp->nvram_size = cursize;
10241 }
10242
10243 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10244 {
10245         u32 val;
10246
10247         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10248             tg3_nvram_read(tp, 0, &val) != 0)
10249                 return;
10250
10251         /* Selfboot format */
10252         if (val != TG3_EEPROM_MAGIC) {
10253                 tg3_get_eeprom_size(tp);
10254                 return;
10255         }
10256
10257         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10258                 if (val != 0) {
10259                         /* This is confusing.  We want to operate on the
10260                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10261                          * call will read from NVRAM and byteswap the data
10262                          * according to the byteswapping settings for all
10263                          * other register accesses.  This ensures the data we
10264                          * want will always reside in the lower 16-bits.
10265                          * However, the data in NVRAM is in LE format, which
10266                          * means the data from the NVRAM read will always be
10267                          * opposite the endianness of the CPU.  The 16-bit
10268                          * byteswap then brings the data to CPU endianness.
10269                          */
10270                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10271                         return;
10272                 }
10273         }
10274         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10275 }
10276
10277 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10278 {
10279         u32 nvcfg1;
10280
10281         nvcfg1 = tr32(NVRAM_CFG1);
10282         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10283                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10284         }
10285         else {
10286                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10287                 tw32(NVRAM_CFG1, nvcfg1);
10288         }
10289
10290         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10291             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10292                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10293                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10294                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10295                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10296                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10297                                 break;
10298                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10299                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10300                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10301                                 break;
10302                         case FLASH_VENDOR_ATMEL_EEPROM:
10303                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10304                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10305                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10306                                 break;
10307                         case FLASH_VENDOR_ST:
10308                                 tp->nvram_jedecnum = JEDEC_ST;
10309                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10310                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10311                                 break;
10312                         case FLASH_VENDOR_SAIFUN:
10313                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
10314                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10315                                 break;
10316                         case FLASH_VENDOR_SST_SMALL:
10317                         case FLASH_VENDOR_SST_LARGE:
10318                                 tp->nvram_jedecnum = JEDEC_SST;
10319                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10320                                 break;
10321                 }
10322         }
10323         else {
10324                 tp->nvram_jedecnum = JEDEC_ATMEL;
10325                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10326                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10327         }
10328 }
10329
10330 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10331 {
10332         u32 nvcfg1;
10333
10334         nvcfg1 = tr32(NVRAM_CFG1);
10335
10336         /* NVRAM protection for TPM */
10337         if (nvcfg1 & (1 << 27))
10338                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10339
10340         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10341                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10342                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10343                         tp->nvram_jedecnum = JEDEC_ATMEL;
10344                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10345                         break;
10346                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10347                         tp->nvram_jedecnum = JEDEC_ATMEL;
10348                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10349                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10350                         break;
10351                 case FLASH_5752VENDOR_ST_M45PE10:
10352                 case FLASH_5752VENDOR_ST_M45PE20:
10353                 case FLASH_5752VENDOR_ST_M45PE40:
10354                         tp->nvram_jedecnum = JEDEC_ST;
10355                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10356                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10357                         break;
10358         }
10359
10360         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10361                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10362                         case FLASH_5752PAGE_SIZE_256:
10363                                 tp->nvram_pagesize = 256;
10364                                 break;
10365                         case FLASH_5752PAGE_SIZE_512:
10366                                 tp->nvram_pagesize = 512;
10367                                 break;
10368                         case FLASH_5752PAGE_SIZE_1K:
10369                                 tp->nvram_pagesize = 1024;
10370                                 break;
10371                         case FLASH_5752PAGE_SIZE_2K:
10372                                 tp->nvram_pagesize = 2048;
10373                                 break;
10374                         case FLASH_5752PAGE_SIZE_4K:
10375                                 tp->nvram_pagesize = 4096;
10376                                 break;
10377                         case FLASH_5752PAGE_SIZE_264:
10378                                 tp->nvram_pagesize = 264;
10379                                 break;
10380                 }
10381         }
10382         else {
10383                 /* For eeprom, set pagesize to maximum eeprom size */
10384                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10385
10386                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10387                 tw32(NVRAM_CFG1, nvcfg1);
10388         }
10389 }
10390
10391 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10392 {
10393         u32 nvcfg1, protect = 0;
10394
10395         nvcfg1 = tr32(NVRAM_CFG1);
10396
10397         /* NVRAM protection for TPM */
10398         if (nvcfg1 & (1 << 27)) {
10399                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10400                 protect = 1;
10401         }
10402
10403         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10404         switch (nvcfg1) {
10405                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10406                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10407                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10408                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10409                         tp->nvram_jedecnum = JEDEC_ATMEL;
10410                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10411                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10412                         tp->nvram_pagesize = 264;
10413                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10414                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10415                                 tp->nvram_size = (protect ? 0x3e200 :
10416                                                   TG3_NVRAM_SIZE_512KB);
10417                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10418                                 tp->nvram_size = (protect ? 0x1f200 :
10419                                                   TG3_NVRAM_SIZE_256KB);
10420                         else
10421                                 tp->nvram_size = (protect ? 0x1f200 :
10422                                                   TG3_NVRAM_SIZE_128KB);
10423                         break;
10424                 case FLASH_5752VENDOR_ST_M45PE10:
10425                 case FLASH_5752VENDOR_ST_M45PE20:
10426                 case FLASH_5752VENDOR_ST_M45PE40:
10427                         tp->nvram_jedecnum = JEDEC_ST;
10428                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10429                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10430                         tp->nvram_pagesize = 256;
10431                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10432                                 tp->nvram_size = (protect ?
10433                                                   TG3_NVRAM_SIZE_64KB :
10434                                                   TG3_NVRAM_SIZE_128KB);
10435                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10436                                 tp->nvram_size = (protect ?
10437                                                   TG3_NVRAM_SIZE_64KB :
10438                                                   TG3_NVRAM_SIZE_256KB);
10439                         else
10440                                 tp->nvram_size = (protect ?
10441                                                   TG3_NVRAM_SIZE_128KB :
10442                                                   TG3_NVRAM_SIZE_512KB);
10443                         break;
10444         }
10445 }
10446
10447 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10448 {
10449         u32 nvcfg1;
10450
10451         nvcfg1 = tr32(NVRAM_CFG1);
10452
10453         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10454                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10455                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10456                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10457                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10458                         tp->nvram_jedecnum = JEDEC_ATMEL;
10459                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10460                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10461
10462                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10463                         tw32(NVRAM_CFG1, nvcfg1);
10464                         break;
10465                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10466                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10467                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10468                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10469                         tp->nvram_jedecnum = JEDEC_ATMEL;
10470                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10471                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10472                         tp->nvram_pagesize = 264;
10473                         break;
10474                 case FLASH_5752VENDOR_ST_M45PE10:
10475                 case FLASH_5752VENDOR_ST_M45PE20:
10476                 case FLASH_5752VENDOR_ST_M45PE40:
10477                         tp->nvram_jedecnum = JEDEC_ST;
10478                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10479                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10480                         tp->nvram_pagesize = 256;
10481                         break;
10482         }
10483 }
10484
10485 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10486 {
10487         u32 nvcfg1, protect = 0;
10488
10489         nvcfg1 = tr32(NVRAM_CFG1);
10490
10491         /* NVRAM protection for TPM */
10492         if (nvcfg1 & (1 << 27)) {
10493                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10494                 protect = 1;
10495         }
10496
10497         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10498         switch (nvcfg1) {
10499                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10500                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10501                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10502                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10503                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10504                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10505                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10506                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10507                         tp->nvram_jedecnum = JEDEC_ATMEL;
10508                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10509                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10510                         tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10511                         tp->nvram_pagesize = 256;
10512                         break;
10513                 case FLASH_5761VENDOR_ST_A_M45PE20:
10514                 case FLASH_5761VENDOR_ST_A_M45PE40:
10515                 case FLASH_5761VENDOR_ST_A_M45PE80:
10516                 case FLASH_5761VENDOR_ST_A_M45PE16:
10517                 case FLASH_5761VENDOR_ST_M_M45PE20:
10518                 case FLASH_5761VENDOR_ST_M_M45PE40:
10519                 case FLASH_5761VENDOR_ST_M_M45PE80:
10520                 case FLASH_5761VENDOR_ST_M_M45PE16:
10521                         tp->nvram_jedecnum = JEDEC_ST;
10522                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10523                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10524                         tp->nvram_pagesize = 256;
10525                         break;
10526         }
10527
10528         if (protect) {
10529                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10530         } else {
10531                 switch (nvcfg1) {
10532                         case FLASH_5761VENDOR_ATMEL_ADB161D:
10533                         case FLASH_5761VENDOR_ATMEL_MDB161D:
10534                         case FLASH_5761VENDOR_ST_A_M45PE16:
10535                         case FLASH_5761VENDOR_ST_M_M45PE16:
10536                                 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10537                                 break;
10538                         case FLASH_5761VENDOR_ATMEL_ADB081D:
10539                         case FLASH_5761VENDOR_ATMEL_MDB081D:
10540                         case FLASH_5761VENDOR_ST_A_M45PE80:
10541                         case FLASH_5761VENDOR_ST_M_M45PE80:
10542                                 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10543                                 break;
10544                         case FLASH_5761VENDOR_ATMEL_ADB041D:
10545                         case FLASH_5761VENDOR_ATMEL_MDB041D:
10546                         case FLASH_5761VENDOR_ST_A_M45PE40:
10547                         case FLASH_5761VENDOR_ST_M_M45PE40:
10548                                 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10549                                 break;
10550                         case FLASH_5761VENDOR_ATMEL_ADB021D:
10551                         case FLASH_5761VENDOR_ATMEL_MDB021D:
10552                         case FLASH_5761VENDOR_ST_A_M45PE20:
10553                         case FLASH_5761VENDOR_ST_M_M45PE20:
10554                                 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10555                                 break;
10556                 }
10557         }
10558 }
10559
10560 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10561 {
10562         tp->nvram_jedecnum = JEDEC_ATMEL;
10563         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10564         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10565 }
10566
10567 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10568 {
10569         u32 nvcfg1;
10570
10571         nvcfg1 = tr32(NVRAM_CFG1);
10572
10573         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10574         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10575         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10576                 tp->nvram_jedecnum = JEDEC_ATMEL;
10577                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10578                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10579
10580                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10581                 tw32(NVRAM_CFG1, nvcfg1);
10582                 return;
10583         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10584         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10585         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10586         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10587         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10588         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10589         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10590                 tp->nvram_jedecnum = JEDEC_ATMEL;
10591                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10592                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10593
10594                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10595                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10596                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10597                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10598                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10599                         break;
10600                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10601                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10602                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10603                         break;
10604                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10605                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10606                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10607                         break;
10608                 }
10609                 break;
10610         case FLASH_5752VENDOR_ST_M45PE10:
10611         case FLASH_5752VENDOR_ST_M45PE20:
10612         case FLASH_5752VENDOR_ST_M45PE40:
10613                 tp->nvram_jedecnum = JEDEC_ST;
10614                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10615                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10616
10617                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10618                 case FLASH_5752VENDOR_ST_M45PE10:
10619                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10620                         break;
10621                 case FLASH_5752VENDOR_ST_M45PE20:
10622                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10623                         break;
10624                 case FLASH_5752VENDOR_ST_M45PE40:
10625                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10626                         break;
10627                 }
10628                 break;
10629         default:
10630                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10631                 return;
10632         }
10633
10634         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10635         case FLASH_5752PAGE_SIZE_256:
10636                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10637                 tp->nvram_pagesize = 256;
10638                 break;
10639         case FLASH_5752PAGE_SIZE_512:
10640                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10641                 tp->nvram_pagesize = 512;
10642                 break;
10643         case FLASH_5752PAGE_SIZE_1K:
10644                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10645                 tp->nvram_pagesize = 1024;
10646                 break;
10647         case FLASH_5752PAGE_SIZE_2K:
10648                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10649                 tp->nvram_pagesize = 2048;
10650                 break;
10651         case FLASH_5752PAGE_SIZE_4K:
10652                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10653                 tp->nvram_pagesize = 4096;
10654                 break;
10655         case FLASH_5752PAGE_SIZE_264:
10656                 tp->nvram_pagesize = 264;
10657                 break;
10658         case FLASH_5752PAGE_SIZE_528:
10659                 tp->nvram_pagesize = 528;
10660                 break;
10661         }
10662 }
10663
10664 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10665 static void __devinit tg3_nvram_init(struct tg3 *tp)
10666 {
10667         tw32_f(GRC_EEPROM_ADDR,
10668              (EEPROM_ADDR_FSM_RESET |
10669               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10670                EEPROM_ADDR_CLKPERD_SHIFT)));
10671
10672         msleep(1);
10673
10674         /* Enable seeprom accesses. */
10675         tw32_f(GRC_LOCAL_CTRL,
10676              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10677         udelay(100);
10678
10679         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10680             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10681                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10682
10683                 if (tg3_nvram_lock(tp)) {
10684                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10685                                "tg3_nvram_init failed.\n", tp->dev->name);
10686                         return;
10687                 }
10688                 tg3_enable_nvram_access(tp);
10689
10690                 tp->nvram_size = 0;
10691
10692                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10693                         tg3_get_5752_nvram_info(tp);
10694                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10695                         tg3_get_5755_nvram_info(tp);
10696                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10697                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10698                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10699                         tg3_get_5787_nvram_info(tp);
10700                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10701                         tg3_get_5761_nvram_info(tp);
10702                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10703                         tg3_get_5906_nvram_info(tp);
10704                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10705                         tg3_get_57780_nvram_info(tp);
10706                 else
10707                         tg3_get_nvram_info(tp);
10708
10709                 if (tp->nvram_size == 0)
10710                         tg3_get_nvram_size(tp);
10711
10712                 tg3_disable_nvram_access(tp);
10713                 tg3_nvram_unlock(tp);
10714
10715         } else {
10716                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10717
10718                 tg3_get_eeprom_size(tp);
10719         }
10720 }
10721
10722 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10723                                     u32 offset, u32 len, u8 *buf)
10724 {
10725         int i, j, rc = 0;
10726         u32 val;
10727
10728         for (i = 0; i < len; i += 4) {
10729                 u32 addr;
10730                 __be32 data;
10731
10732                 addr = offset + i;
10733
10734                 memcpy(&data, buf + i, 4);
10735
10736                 /*
10737                  * The SEEPROM interface expects the data to always be opposite
10738                  * the native endian format.  We accomplish this by reversing
10739                  * all the operations that would have been performed on the
10740                  * data from a call to tg3_nvram_read_be32().
10741                  */
10742                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
10743
10744                 val = tr32(GRC_EEPROM_ADDR);
10745                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10746
10747                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10748                         EEPROM_ADDR_READ);
10749                 tw32(GRC_EEPROM_ADDR, val |
10750                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10751                         (addr & EEPROM_ADDR_ADDR_MASK) |
10752                         EEPROM_ADDR_START |
10753                         EEPROM_ADDR_WRITE);
10754
10755                 for (j = 0; j < 1000; j++) {
10756                         val = tr32(GRC_EEPROM_ADDR);
10757
10758                         if (val & EEPROM_ADDR_COMPLETE)
10759                                 break;
10760                         msleep(1);
10761                 }
10762                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10763                         rc = -EBUSY;
10764                         break;
10765                 }
10766         }
10767
10768         return rc;
10769 }
10770
10771 /* offset and length are dword aligned */
10772 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10773                 u8 *buf)
10774 {
10775         int ret = 0;
10776         u32 pagesize = tp->nvram_pagesize;
10777         u32 pagemask = pagesize - 1;
10778         u32 nvram_cmd;
10779         u8 *tmp;
10780
10781         tmp = kmalloc(pagesize, GFP_KERNEL);
10782         if (tmp == NULL)
10783                 return -ENOMEM;
10784
10785         while (len) {
10786                 int j;
10787                 u32 phy_addr, page_off, size;
10788
10789                 phy_addr = offset & ~pagemask;
10790
10791                 for (j = 0; j < pagesize; j += 4) {
10792                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
10793                                                   (__be32 *) (tmp + j));
10794                         if (ret)
10795                                 break;
10796                 }
10797                 if (ret)
10798                         break;
10799
10800                 page_off = offset & pagemask;
10801                 size = pagesize;
10802                 if (len < size)
10803                         size = len;
10804
10805                 len -= size;
10806
10807                 memcpy(tmp + page_off, buf, size);
10808
10809                 offset = offset + (pagesize - page_off);
10810
10811                 tg3_enable_nvram_access(tp);
10812
10813                 /*
10814                  * Before we can erase the flash page, we need
10815                  * to issue a special "write enable" command.
10816                  */
10817                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10818
10819                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10820                         break;
10821
10822                 /* Erase the target page */
10823                 tw32(NVRAM_ADDR, phy_addr);
10824
10825                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10826                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10827
10828                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10829                         break;
10830
10831                 /* Issue another write enable to start the write. */
10832                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10833
10834                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10835                         break;
10836
10837                 for (j = 0; j < pagesize; j += 4) {
10838                         __be32 data;
10839
10840                         data = *((__be32 *) (tmp + j));
10841
10842                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
10843
10844                         tw32(NVRAM_ADDR, phy_addr + j);
10845
10846                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10847                                 NVRAM_CMD_WR;
10848
10849                         if (j == 0)
10850                                 nvram_cmd |= NVRAM_CMD_FIRST;
10851                         else if (j == (pagesize - 4))
10852                                 nvram_cmd |= NVRAM_CMD_LAST;
10853
10854                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10855                                 break;
10856                 }
10857                 if (ret)
10858                         break;
10859         }
10860
10861         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10862         tg3_nvram_exec_cmd(tp, nvram_cmd);
10863
10864         kfree(tmp);
10865
10866         return ret;
10867 }
10868
10869 /* offset and length are dword aligned */
10870 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10871                 u8 *buf)
10872 {
10873         int i, ret = 0;
10874
10875         for (i = 0; i < len; i += 4, offset += 4) {
10876                 u32 page_off, phy_addr, nvram_cmd;
10877                 __be32 data;
10878
10879                 memcpy(&data, buf + i, 4);
10880                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10881
10882                 page_off = offset % tp->nvram_pagesize;
10883
10884                 phy_addr = tg3_nvram_phys_addr(tp, offset);
10885
10886                 tw32(NVRAM_ADDR, phy_addr);
10887
10888                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10889
10890                 if ((page_off == 0) || (i == 0))
10891                         nvram_cmd |= NVRAM_CMD_FIRST;
10892                 if (page_off == (tp->nvram_pagesize - 4))
10893                         nvram_cmd |= NVRAM_CMD_LAST;
10894
10895                 if (i == (len - 4))
10896                         nvram_cmd |= NVRAM_CMD_LAST;
10897
10898                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10899                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10900                     (tp->nvram_jedecnum == JEDEC_ST) &&
10901                     (nvram_cmd & NVRAM_CMD_FIRST)) {
10902
10903                         if ((ret = tg3_nvram_exec_cmd(tp,
10904                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10905                                 NVRAM_CMD_DONE)))
10906
10907                                 break;
10908                 }
10909                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10910                         /* We always do complete word writes to eeprom. */
10911                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10912                 }
10913
10914                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10915                         break;
10916         }
10917         return ret;
10918 }
10919
10920 /* offset and length are dword aligned */
10921 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10922 {
10923         int ret;
10924
10925         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10926                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10927                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
10928                 udelay(40);
10929         }
10930
10931         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10932                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10933         }
10934         else {
10935                 u32 grc_mode;
10936
10937                 ret = tg3_nvram_lock(tp);
10938                 if (ret)
10939                         return ret;
10940
10941                 tg3_enable_nvram_access(tp);
10942                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10943                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10944                         tw32(NVRAM_WRITE1, 0x406);
10945
10946                 grc_mode = tr32(GRC_MODE);
10947                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10948
10949                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10950                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10951
10952                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
10953                                 buf);
10954                 }
10955                 else {
10956                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10957                                 buf);
10958                 }
10959
10960                 grc_mode = tr32(GRC_MODE);
10961                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10962
10963                 tg3_disable_nvram_access(tp);
10964                 tg3_nvram_unlock(tp);
10965         }
10966
10967         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10968                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10969                 udelay(40);
10970         }
10971
10972         return ret;
10973 }
10974
10975 struct subsys_tbl_ent {
10976         u16 subsys_vendor, subsys_devid;
10977         u32 phy_id;
10978 };
10979
10980 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10981         /* Broadcom boards. */
10982         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10983         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10984         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10985         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
10986         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10987         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10988         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
10989         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10990         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10991         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10992         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10993
10994         /* 3com boards. */
10995         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10996         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10997         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
10998         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10999         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11000
11001         /* DELL boards. */
11002         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11003         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11004         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11005         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11006
11007         /* Compaq boards. */
11008         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11009         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11010         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11011         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11012         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11013
11014         /* IBM boards. */
11015         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11016 };
11017
11018 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11019 {
11020         int i;
11021
11022         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11023                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11024                      tp->pdev->subsystem_vendor) &&
11025                     (subsys_id_to_phy_id[i].subsys_devid ==
11026                      tp->pdev->subsystem_device))
11027                         return &subsys_id_to_phy_id[i];
11028         }
11029         return NULL;
11030 }
11031
11032 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11033 {
11034         u32 val;
11035         u16 pmcsr;
11036
11037         /* On some early chips the SRAM cannot be accessed in D3hot state,
11038          * so need make sure we're in D0.
11039          */
11040         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11041         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11042         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11043         msleep(1);
11044
11045         /* Make sure register accesses (indirect or otherwise)
11046          * will function correctly.
11047          */
11048         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11049                                tp->misc_host_ctrl);
11050
11051         /* The memory arbiter has to be enabled in order for SRAM accesses
11052          * to succeed.  Normally on powerup the tg3 chip firmware will make
11053          * sure it is enabled, but other entities such as system netboot
11054          * code might disable it.
11055          */
11056         val = tr32(MEMARB_MODE);
11057         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11058
11059         tp->phy_id = PHY_ID_INVALID;
11060         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11061
11062         /* Assume an onboard device and WOL capable by default.  */
11063         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11064
11065         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11066                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11067                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11068                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11069                 }
11070                 val = tr32(VCPU_CFGSHDW);
11071                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11072                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11073                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11074                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11075                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11076                 goto done;
11077         }
11078
11079         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11080         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11081                 u32 nic_cfg, led_cfg;
11082                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11083                 int eeprom_phy_serdes = 0;
11084
11085                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11086                 tp->nic_sram_data_cfg = nic_cfg;
11087
11088                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11089                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11090                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11091                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11092                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11093                     (ver > 0) && (ver < 0x100))
11094                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11095
11096                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11097                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11098
11099                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11100                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11101                         eeprom_phy_serdes = 1;
11102
11103                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11104                 if (nic_phy_id != 0) {
11105                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11106                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11107
11108                         eeprom_phy_id  = (id1 >> 16) << 10;
11109                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11110                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11111                 } else
11112                         eeprom_phy_id = 0;
11113
11114                 tp->phy_id = eeprom_phy_id;
11115                 if (eeprom_phy_serdes) {
11116                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11117                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11118                         else
11119                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11120                 }
11121
11122                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11123                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11124                                     SHASTA_EXT_LED_MODE_MASK);
11125                 else
11126                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11127
11128                 switch (led_cfg) {
11129                 default:
11130                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11131                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11132                         break;
11133
11134                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11135                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11136                         break;
11137
11138                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11139                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11140
11141                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11142                          * read on some older 5700/5701 bootcode.
11143                          */
11144                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11145                             ASIC_REV_5700 ||
11146                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11147                             ASIC_REV_5701)
11148                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11149
11150                         break;
11151
11152                 case SHASTA_EXT_LED_SHARED:
11153                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11154                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11155                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11156                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11157                                                  LED_CTRL_MODE_PHY_2);
11158                         break;
11159
11160                 case SHASTA_EXT_LED_MAC:
11161                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11162                         break;
11163
11164                 case SHASTA_EXT_LED_COMBO:
11165                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11166                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11167                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11168                                                  LED_CTRL_MODE_PHY_2);
11169                         break;
11170
11171                 }
11172
11173                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11174                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11175                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11176                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11177
11178                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11179                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11180
11181                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11182                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11183                         if ((tp->pdev->subsystem_vendor ==
11184                              PCI_VENDOR_ID_ARIMA) &&
11185                             (tp->pdev->subsystem_device == 0x205a ||
11186                              tp->pdev->subsystem_device == 0x2063))
11187                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11188                 } else {
11189                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11190                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11191                 }
11192
11193                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11194                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11195                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11196                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11197                 }
11198
11199                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11200                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11201                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11202
11203                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11204                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11205                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11206
11207                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11208                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11209                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11210
11211                 if (cfg2 & (1 << 17))
11212                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11213
11214                 /* serdes signal pre-emphasis in register 0x590 set by */
11215                 /* bootcode if bit 18 is set */
11216                 if (cfg2 & (1 << 18))
11217                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11218
11219                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11220                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11221                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11222                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11223
11224                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11225                         u32 cfg3;
11226
11227                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11228                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11229                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11230                 }
11231
11232                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11233                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11234                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11235                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11236                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11237                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11238         }
11239 done:
11240         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11241         device_set_wakeup_enable(&tp->pdev->dev,
11242                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11243 }
11244
11245 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11246 {
11247         int i;
11248         u32 val;
11249
11250         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11251         tw32(OTP_CTRL, cmd);
11252
11253         /* Wait for up to 1 ms for command to execute. */
11254         for (i = 0; i < 100; i++) {
11255                 val = tr32(OTP_STATUS);
11256                 if (val & OTP_STATUS_CMD_DONE)
11257                         break;
11258                 udelay(10);
11259         }
11260
11261         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11262 }
11263
11264 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11265  * configuration is a 32-bit value that straddles the alignment boundary.
11266  * We do two 32-bit reads and then shift and merge the results.
11267  */
11268 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11269 {
11270         u32 bhalf_otp, thalf_otp;
11271
11272         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11273
11274         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11275                 return 0;
11276
11277         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11278
11279         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11280                 return 0;
11281
11282         thalf_otp = tr32(OTP_READ_DATA);
11283
11284         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11285
11286         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11287                 return 0;
11288
11289         bhalf_otp = tr32(OTP_READ_DATA);
11290
11291         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11292 }
11293
11294 static int __devinit tg3_phy_probe(struct tg3 *tp)
11295 {
11296         u32 hw_phy_id_1, hw_phy_id_2;
11297         u32 hw_phy_id, hw_phy_id_masked;
11298         int err;
11299
11300         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11301                 return tg3_phy_init(tp);
11302
11303         /* Reading the PHY ID register can conflict with ASF
11304          * firmware access to the PHY hardware.
11305          */
11306         err = 0;
11307         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11308             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11309                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11310         } else {
11311                 /* Now read the physical PHY_ID from the chip and verify
11312                  * that it is sane.  If it doesn't look good, we fall back
11313                  * to either the hard-coded table based PHY_ID and failing
11314                  * that the value found in the eeprom area.
11315                  */
11316                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11317                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11318
11319                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11320                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11321                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11322
11323                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11324         }
11325
11326         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11327                 tp->phy_id = hw_phy_id;
11328                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11329                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11330                 else
11331                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11332         } else {
11333                 if (tp->phy_id != PHY_ID_INVALID) {
11334                         /* Do nothing, phy ID already set up in
11335                          * tg3_get_eeprom_hw_cfg().
11336                          */
11337                 } else {
11338                         struct subsys_tbl_ent *p;
11339
11340                         /* No eeprom signature?  Try the hardcoded
11341                          * subsys device table.
11342                          */
11343                         p = lookup_by_subsys(tp);
11344                         if (!p)
11345                                 return -ENODEV;
11346
11347                         tp->phy_id = p->phy_id;
11348                         if (!tp->phy_id ||
11349                             tp->phy_id == PHY_ID_BCM8002)
11350                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11351                 }
11352         }
11353
11354         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11355             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11356             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11357                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11358
11359                 tg3_readphy(tp, MII_BMSR, &bmsr);
11360                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11361                     (bmsr & BMSR_LSTATUS))
11362                         goto skip_phy_reset;
11363
11364                 err = tg3_phy_reset(tp);
11365                 if (err)
11366                         return err;
11367
11368                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11369                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11370                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11371                 tg3_ctrl = 0;
11372                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11373                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11374                                     MII_TG3_CTRL_ADV_1000_FULL);
11375                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11376                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11377                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11378                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11379                 }
11380
11381                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11382                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11383                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11384                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11385                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11386
11387                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11388                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11389
11390                         tg3_writephy(tp, MII_BMCR,
11391                                      BMCR_ANENABLE | BMCR_ANRESTART);
11392                 }
11393                 tg3_phy_set_wirespeed(tp);
11394
11395                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11396                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11397                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11398         }
11399
11400 skip_phy_reset:
11401         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11402                 err = tg3_init_5401phy_dsp(tp);
11403                 if (err)
11404                         return err;
11405         }
11406
11407         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11408                 err = tg3_init_5401phy_dsp(tp);
11409         }
11410
11411         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11412                 tp->link_config.advertising =
11413                         (ADVERTISED_1000baseT_Half |
11414                          ADVERTISED_1000baseT_Full |
11415                          ADVERTISED_Autoneg |
11416                          ADVERTISED_FIBRE);
11417         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11418                 tp->link_config.advertising &=
11419                         ~(ADVERTISED_1000baseT_Half |
11420                           ADVERTISED_1000baseT_Full);
11421
11422         return err;
11423 }
11424
11425 static void __devinit tg3_read_partno(struct tg3 *tp)
11426 {
11427         unsigned char vpd_data[256];   /* in little-endian format */
11428         unsigned int i;
11429         u32 magic;
11430
11431         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11432             tg3_nvram_read(tp, 0x0, &magic))
11433                 goto out_not_found;
11434
11435         if (magic == TG3_EEPROM_MAGIC) {
11436                 for (i = 0; i < 256; i += 4) {
11437                         u32 tmp;
11438
11439                         /* The data is in little-endian format in NVRAM.
11440                          * Use the big-endian read routines to preserve
11441                          * the byte order as it exists in NVRAM.
11442                          */
11443                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11444                                 goto out_not_found;
11445
11446                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11447                 }
11448         } else {
11449                 int vpd_cap;
11450
11451                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11452                 for (i = 0; i < 256; i += 4) {
11453                         u32 tmp, j = 0;
11454                         __le32 v;
11455                         u16 tmp16;
11456
11457                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11458                                               i);
11459                         while (j++ < 100) {
11460                                 pci_read_config_word(tp->pdev, vpd_cap +
11461                                                      PCI_VPD_ADDR, &tmp16);
11462                                 if (tmp16 & 0x8000)
11463                                         break;
11464                                 msleep(1);
11465                         }
11466                         if (!(tmp16 & 0x8000))
11467                                 goto out_not_found;
11468
11469                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11470                                               &tmp);
11471                         v = cpu_to_le32(tmp);
11472                         memcpy(&vpd_data[i], &v, sizeof(v));
11473                 }
11474         }
11475
11476         /* Now parse and find the part number. */
11477         for (i = 0; i < 254; ) {
11478                 unsigned char val = vpd_data[i];
11479                 unsigned int block_end;
11480
11481                 if (val == 0x82 || val == 0x91) {
11482                         i = (i + 3 +
11483                              (vpd_data[i + 1] +
11484                               (vpd_data[i + 2] << 8)));
11485                         continue;
11486                 }
11487
11488                 if (val != 0x90)
11489                         goto out_not_found;
11490
11491                 block_end = (i + 3 +
11492                              (vpd_data[i + 1] +
11493                               (vpd_data[i + 2] << 8)));
11494                 i += 3;
11495
11496                 if (block_end > 256)
11497                         goto out_not_found;
11498
11499                 while (i < (block_end - 2)) {
11500                         if (vpd_data[i + 0] == 'P' &&
11501                             vpd_data[i + 1] == 'N') {
11502                                 int partno_len = vpd_data[i + 2];
11503
11504                                 i += 3;
11505                                 if (partno_len > 24 || (partno_len + i) > 256)
11506                                         goto out_not_found;
11507
11508                                 memcpy(tp->board_part_number,
11509                                        &vpd_data[i], partno_len);
11510
11511                                 /* Success. */
11512                                 return;
11513                         }
11514                         i += 3 + vpd_data[i + 2];
11515                 }
11516
11517                 /* Part number not found. */
11518                 goto out_not_found;
11519         }
11520
11521 out_not_found:
11522         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11523                 strcpy(tp->board_part_number, "BCM95906");
11524         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11525                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11526                 strcpy(tp->board_part_number, "BCM57780");
11527         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11528                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11529                 strcpy(tp->board_part_number, "BCM57760");
11530         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11531                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11532                 strcpy(tp->board_part_number, "BCM57790");
11533         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11534                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11535                 strcpy(tp->board_part_number, "BCM57788");
11536         else
11537                 strcpy(tp->board_part_number, "none");
11538 }
11539
11540 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11541 {
11542         u32 val;
11543
11544         if (tg3_nvram_read(tp, offset, &val) ||
11545             (val & 0xfc000000) != 0x0c000000 ||
11546             tg3_nvram_read(tp, offset + 4, &val) ||
11547             val != 0)
11548                 return 0;
11549
11550         return 1;
11551 }
11552
11553 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11554 {
11555         u32 val, offset, start, ver_offset;
11556         int i;
11557         bool newver = false;
11558
11559         if (tg3_nvram_read(tp, 0xc, &offset) ||
11560             tg3_nvram_read(tp, 0x4, &start))
11561                 return;
11562
11563         offset = tg3_nvram_logical_addr(tp, offset);
11564
11565         if (tg3_nvram_read(tp, offset, &val))
11566                 return;
11567
11568         if ((val & 0xfc000000) == 0x0c000000) {
11569                 if (tg3_nvram_read(tp, offset + 4, &val))
11570                         return;
11571
11572                 if (val == 0)
11573                         newver = true;
11574         }
11575
11576         if (newver) {
11577                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11578                         return;
11579
11580                 offset = offset + ver_offset - start;
11581                 for (i = 0; i < 16; i += 4) {
11582                         __be32 v;
11583                         if (tg3_nvram_read_be32(tp, offset + i, &v))
11584                                 return;
11585
11586                         memcpy(tp->fw_ver + i, &v, sizeof(v));
11587                 }
11588         } else {
11589                 u32 major, minor;
11590
11591                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11592                         return;
11593
11594                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11595                         TG3_NVM_BCVER_MAJSFT;
11596                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11597                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11598         }
11599 }
11600
11601 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11602 {
11603         u32 val, major, minor;
11604
11605         /* Use native endian representation */
11606         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11607                 return;
11608
11609         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11610                 TG3_NVM_HWSB_CFG1_MAJSFT;
11611         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11612                 TG3_NVM_HWSB_CFG1_MINSFT;
11613
11614         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11615 }
11616
11617 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11618 {
11619         u32 offset, major, minor, build;
11620
11621         tp->fw_ver[0] = 's';
11622         tp->fw_ver[1] = 'b';
11623         tp->fw_ver[2] = '\0';
11624
11625         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11626                 return;
11627
11628         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11629         case TG3_EEPROM_SB_REVISION_0:
11630                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11631                 break;
11632         case TG3_EEPROM_SB_REVISION_2:
11633                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11634                 break;
11635         case TG3_EEPROM_SB_REVISION_3:
11636                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11637                 break;
11638         default:
11639                 return;
11640         }
11641
11642         if (tg3_nvram_read(tp, offset, &val))
11643                 return;
11644
11645         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11646                 TG3_EEPROM_SB_EDH_BLD_SHFT;
11647         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11648                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11649         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
11650
11651         if (minor > 99 || build > 26)
11652                 return;
11653
11654         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11655
11656         if (build > 0) {
11657                 tp->fw_ver[8] = 'a' + build - 1;
11658                 tp->fw_ver[9] = '\0';
11659         }
11660 }
11661
11662 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11663 {
11664         u32 val, offset, start;
11665         int i, vlen;
11666
11667         for (offset = TG3_NVM_DIR_START;
11668              offset < TG3_NVM_DIR_END;
11669              offset += TG3_NVM_DIRENT_SIZE) {
11670                 if (tg3_nvram_read(tp, offset, &val))
11671                         return;
11672
11673                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11674                         break;
11675         }
11676
11677         if (offset == TG3_NVM_DIR_END)
11678                 return;
11679
11680         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11681                 start = 0x08000000;
11682         else if (tg3_nvram_read(tp, offset - 4, &start))
11683                 return;
11684
11685         if (tg3_nvram_read(tp, offset + 4, &offset) ||
11686             !tg3_fw_img_is_valid(tp, offset) ||
11687             tg3_nvram_read(tp, offset + 8, &val))
11688                 return;
11689
11690         offset += val - start;
11691
11692         vlen = strlen(tp->fw_ver);
11693
11694         tp->fw_ver[vlen++] = ',';
11695         tp->fw_ver[vlen++] = ' ';
11696
11697         for (i = 0; i < 4; i++) {
11698                 __be32 v;
11699                 if (tg3_nvram_read_be32(tp, offset, &v))
11700                         return;
11701
11702                 offset += sizeof(v);
11703
11704                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11705                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11706                         break;
11707                 }
11708
11709                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11710                 vlen += sizeof(v);
11711         }
11712 }
11713
11714 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11715 {
11716         int vlen;
11717         u32 apedata;
11718
11719         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11720             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
11721                 return;
11722
11723         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11724         if (apedata != APE_SEG_SIG_MAGIC)
11725                 return;
11726
11727         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11728         if (!(apedata & APE_FW_STATUS_READY))
11729                 return;
11730
11731         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11732
11733         vlen = strlen(tp->fw_ver);
11734
11735         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11736                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11737                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11738                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11739                  (apedata & APE_FW_VERSION_BLDMSK));
11740 }
11741
11742 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11743 {
11744         u32 val;
11745
11746         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11747                 tp->fw_ver[0] = 's';
11748                 tp->fw_ver[1] = 'b';
11749                 tp->fw_ver[2] = '\0';
11750
11751                 return;
11752         }
11753
11754         if (tg3_nvram_read(tp, 0, &val))
11755                 return;
11756
11757         if (val == TG3_EEPROM_MAGIC)
11758                 tg3_read_bc_ver(tp);
11759         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11760                 tg3_read_sb_ver(tp, val);
11761         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11762                 tg3_read_hwsb_ver(tp);
11763         else
11764                 return;
11765
11766         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11767              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11768                 return;
11769
11770         tg3_read_mgmtfw_ver(tp);
11771
11772         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11773 }
11774
11775 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11776
11777 static int __devinit tg3_get_invariants(struct tg3 *tp)
11778 {
11779         static struct pci_device_id write_reorder_chipsets[] = {
11780                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11781                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11782                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11783                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11784                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11785                              PCI_DEVICE_ID_VIA_8385_0) },
11786                 { },
11787         };
11788         u32 misc_ctrl_reg;
11789         u32 pci_state_reg, grc_misc_cfg;
11790         u32 val;
11791         u16 pci_cmd;
11792         int err;
11793
11794         /* Force memory write invalidate off.  If we leave it on,
11795          * then on 5700_BX chips we have to enable a workaround.
11796          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11797          * to match the cacheline size.  The Broadcom driver have this
11798          * workaround but turns MWI off all the times so never uses
11799          * it.  This seems to suggest that the workaround is insufficient.
11800          */
11801         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11802         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11803         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11804
11805         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11806          * has the register indirect write enable bit set before
11807          * we try to access any of the MMIO registers.  It is also
11808          * critical that the PCI-X hw workaround situation is decided
11809          * before that as well.
11810          */
11811         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11812                               &misc_ctrl_reg);
11813
11814         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11815                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11816         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11817                 u32 prod_id_asic_rev;
11818
11819                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11820                                       &prod_id_asic_rev);
11821                 tp->pci_chip_rev_id = prod_id_asic_rev;
11822         }
11823
11824         /* Wrong chip ID in 5752 A0. This code can be removed later
11825          * as A0 is not in production.
11826          */
11827         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11828                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11829
11830         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11831          * we need to disable memory and use config. cycles
11832          * only to access all registers. The 5702/03 chips
11833          * can mistakenly decode the special cycles from the
11834          * ICH chipsets as memory write cycles, causing corruption
11835          * of register and memory space. Only certain ICH bridges
11836          * will drive special cycles with non-zero data during the
11837          * address phase which can fall within the 5703's address
11838          * range. This is not an ICH bug as the PCI spec allows
11839          * non-zero address during special cycles. However, only
11840          * these ICH bridges are known to drive non-zero addresses
11841          * during special cycles.
11842          *
11843          * Since special cycles do not cross PCI bridges, we only
11844          * enable this workaround if the 5703 is on the secondary
11845          * bus of these ICH bridges.
11846          */
11847         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11848             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11849                 static struct tg3_dev_id {
11850                         u32     vendor;
11851                         u32     device;
11852                         u32     rev;
11853                 } ich_chipsets[] = {
11854                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11855                           PCI_ANY_ID },
11856                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11857                           PCI_ANY_ID },
11858                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11859                           0xa },
11860                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11861                           PCI_ANY_ID },
11862                         { },
11863                 };
11864                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11865                 struct pci_dev *bridge = NULL;
11866
11867                 while (pci_id->vendor != 0) {
11868                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11869                                                 bridge);
11870                         if (!bridge) {
11871                                 pci_id++;
11872                                 continue;
11873                         }
11874                         if (pci_id->rev != PCI_ANY_ID) {
11875                                 if (bridge->revision > pci_id->rev)
11876                                         continue;
11877                         }
11878                         if (bridge->subordinate &&
11879                             (bridge->subordinate->number ==
11880                              tp->pdev->bus->number)) {
11881
11882                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11883                                 pci_dev_put(bridge);
11884                                 break;
11885                         }
11886                 }
11887         }
11888
11889         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11890                 static struct tg3_dev_id {
11891                         u32     vendor;
11892                         u32     device;
11893                 } bridge_chipsets[] = {
11894                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11895                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11896                         { },
11897                 };
11898                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11899                 struct pci_dev *bridge = NULL;
11900
11901                 while (pci_id->vendor != 0) {
11902                         bridge = pci_get_device(pci_id->vendor,
11903                                                 pci_id->device,
11904                                                 bridge);
11905                         if (!bridge) {
11906                                 pci_id++;
11907                                 continue;
11908                         }
11909                         if (bridge->subordinate &&
11910                             (bridge->subordinate->number <=
11911                              tp->pdev->bus->number) &&
11912                             (bridge->subordinate->subordinate >=
11913                              tp->pdev->bus->number)) {
11914                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11915                                 pci_dev_put(bridge);
11916                                 break;
11917                         }
11918                 }
11919         }
11920
11921         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11922          * DMA addresses > 40-bit. This bridge may have other additional
11923          * 57xx devices behind it in some 4-port NIC designs for example.
11924          * Any tg3 device found behind the bridge will also need the 40-bit
11925          * DMA workaround.
11926          */
11927         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11928             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11929                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11930                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11931                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11932         }
11933         else {
11934                 struct pci_dev *bridge = NULL;
11935
11936                 do {
11937                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11938                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
11939                                                 bridge);
11940                         if (bridge && bridge->subordinate &&
11941                             (bridge->subordinate->number <=
11942                              tp->pdev->bus->number) &&
11943                             (bridge->subordinate->subordinate >=
11944                              tp->pdev->bus->number)) {
11945                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11946                                 pci_dev_put(bridge);
11947                                 break;
11948                         }
11949                 } while (bridge);
11950         }
11951
11952         /* Initialize misc host control in PCI block. */
11953         tp->misc_host_ctrl |= (misc_ctrl_reg &
11954                                MISC_HOST_CTRL_CHIPREV);
11955         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11956                                tp->misc_host_ctrl);
11957
11958         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11959             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11960                 tp->pdev_peer = tg3_find_peer(tp);
11961
11962         /* Intentionally exclude ASIC_REV_5906 */
11963         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11964             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11965             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11966             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11967             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11968             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11969                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11970
11971         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11972             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11973             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11974             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11975             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11976                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11977
11978         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11979             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11980                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11981
11982         /* 5700 B0 chips do not support checksumming correctly due
11983          * to hardware bugs.
11984          */
11985         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11986                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11987         else {
11988                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11989                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11990                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11991                         tp->dev->features |= NETIF_F_IPV6_CSUM;
11992         }
11993
11994         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11995                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11996                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11997                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11998                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11999                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12000                      tp->pdev_peer == tp->pdev))
12001                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12002
12003                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12004                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12005                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12006                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12007                 } else {
12008                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12009                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12010                                 ASIC_REV_5750 &&
12011                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12012                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12013                 }
12014         }
12015
12016         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12017              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12018                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12019
12020         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12021                               &pci_state_reg);
12022
12023         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12024         if (tp->pcie_cap != 0) {
12025                 u16 lnkctl;
12026
12027                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12028
12029                 pcie_set_readrq(tp->pdev, 4096);
12030
12031                 pci_read_config_word(tp->pdev,
12032                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12033                                      &lnkctl);
12034                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12035                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12036                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12037                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12038                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12039                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12040                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12041                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12042                 }
12043         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12044                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12045         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12046                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12047                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12048                 if (!tp->pcix_cap) {
12049                         printk(KERN_ERR PFX "Cannot find PCI-X "
12050                                             "capability, aborting.\n");
12051                         return -EIO;
12052                 }
12053
12054                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12055                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12056         }
12057
12058         /* If we have an AMD 762 or VIA K8T800 chipset, write
12059          * reordering to the mailbox registers done by the host
12060          * controller can cause major troubles.  We read back from
12061          * every mailbox register write to force the writes to be
12062          * posted to the chip in order.
12063          */
12064         if (pci_dev_present(write_reorder_chipsets) &&
12065             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12066                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12067
12068         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12069                              &tp->pci_cacheline_sz);
12070         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12071                              &tp->pci_lat_timer);
12072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12073             tp->pci_lat_timer < 64) {
12074                 tp->pci_lat_timer = 64;
12075                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12076                                       tp->pci_lat_timer);
12077         }
12078
12079         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12080                 /* 5700 BX chips need to have their TX producer index
12081                  * mailboxes written twice to workaround a bug.
12082                  */
12083                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12084
12085                 /* If we are in PCI-X mode, enable register write workaround.
12086                  *
12087                  * The workaround is to use indirect register accesses
12088                  * for all chip writes not to mailbox registers.
12089                  */
12090                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12091                         u32 pm_reg;
12092
12093                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12094
12095                         /* The chip can have it's power management PCI config
12096                          * space registers clobbered due to this bug.
12097                          * So explicitly force the chip into D0 here.
12098                          */
12099                         pci_read_config_dword(tp->pdev,
12100                                               tp->pm_cap + PCI_PM_CTRL,
12101                                               &pm_reg);
12102                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12103                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12104                         pci_write_config_dword(tp->pdev,
12105                                                tp->pm_cap + PCI_PM_CTRL,
12106                                                pm_reg);
12107
12108                         /* Also, force SERR#/PERR# in PCI command. */
12109                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12110                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12111                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12112                 }
12113         }
12114
12115         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12116                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12117         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12118                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12119
12120         /* Chip-specific fixup from Broadcom driver */
12121         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12122             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12123                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12124                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12125         }
12126
12127         /* Default fast path register access methods */
12128         tp->read32 = tg3_read32;
12129         tp->write32 = tg3_write32;
12130         tp->read32_mbox = tg3_read32;
12131         tp->write32_mbox = tg3_write32;
12132         tp->write32_tx_mbox = tg3_write32;
12133         tp->write32_rx_mbox = tg3_write32;
12134
12135         /* Various workaround register access methods */
12136         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12137                 tp->write32 = tg3_write_indirect_reg32;
12138         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12139                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12140                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12141                 /*
12142                  * Back to back register writes can cause problems on these
12143                  * chips, the workaround is to read back all reg writes
12144                  * except those to mailbox regs.
12145                  *
12146                  * See tg3_write_indirect_reg32().
12147                  */
12148                 tp->write32 = tg3_write_flush_reg32;
12149         }
12150
12151
12152         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12153             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12154                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12155                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12156                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12157         }
12158
12159         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12160                 tp->read32 = tg3_read_indirect_reg32;
12161                 tp->write32 = tg3_write_indirect_reg32;
12162                 tp->read32_mbox = tg3_read_indirect_mbox;
12163                 tp->write32_mbox = tg3_write_indirect_mbox;
12164                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12165                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12166
12167                 iounmap(tp->regs);
12168                 tp->regs = NULL;
12169
12170                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12171                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12172                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12173         }
12174         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12175                 tp->read32_mbox = tg3_read32_mbox_5906;
12176                 tp->write32_mbox = tg3_write32_mbox_5906;
12177                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12178                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12179         }
12180
12181         if (tp->write32 == tg3_write_indirect_reg32 ||
12182             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12183              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12184               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12185                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12186
12187         /* Get eeprom hw config before calling tg3_set_power_state().
12188          * In particular, the TG3_FLG2_IS_NIC flag must be
12189          * determined before calling tg3_set_power_state() so that
12190          * we know whether or not to switch out of Vaux power.
12191          * When the flag is set, it means that GPIO1 is used for eeprom
12192          * write protect and also implies that it is a LOM where GPIOs
12193          * are not used to switch power.
12194          */
12195         tg3_get_eeprom_hw_cfg(tp);
12196
12197         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12198                 /* Allow reads and writes to the
12199                  * APE register and memory space.
12200                  */
12201                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12202                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12203                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12204                                        pci_state_reg);
12205         }
12206
12207         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12208             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12209             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12210             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12211                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12212
12213         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12214          * GPIO1 driven high will bring 5700's external PHY out of reset.
12215          * It is also used as eeprom write protect on LOMs.
12216          */
12217         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12218         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12219             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12220                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12221                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12222         /* Unused GPIO3 must be driven as output on 5752 because there
12223          * are no pull-up resistors on unused GPIO pins.
12224          */
12225         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12226                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12227
12228         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12229             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12230                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12231
12232         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12233             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12234                 /* Turn off the debug UART. */
12235                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12236                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12237                         /* Keep VMain power. */
12238                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12239                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12240         }
12241
12242         /* Force the chip into D0. */
12243         err = tg3_set_power_state(tp, PCI_D0);
12244         if (err) {
12245                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12246                        pci_name(tp->pdev));
12247                 return err;
12248         }
12249
12250         /* Derive initial jumbo mode from MTU assigned in
12251          * ether_setup() via the alloc_etherdev() call
12252          */
12253         if (tp->dev->mtu > ETH_DATA_LEN &&
12254             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12255                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12256
12257         /* Determine WakeOnLan speed to use. */
12258         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12259             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12260             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12261             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12262                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12263         } else {
12264                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12265         }
12266
12267         /* A few boards don't want Ethernet@WireSpeed phy feature */
12268         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12269             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12270              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12271              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12272             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12273             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12274                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12275
12276         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12277             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12278                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12279         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12280                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12281
12282         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12283             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12284             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12285             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12286                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12287                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12288                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12289                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12290                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12291                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12292                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12293                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12294                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12295                 } else
12296                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12297         }
12298
12299         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12300             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12301                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12302                 if (tp->phy_otp == 0)
12303                         tp->phy_otp = TG3_OTP_DEFAULT;
12304         }
12305
12306         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12307                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12308         else
12309                 tp->mi_mode = MAC_MI_MODE_BASE;
12310
12311         tp->coalesce_mode = 0;
12312         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12313             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12314                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12315
12316         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12317             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12318                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12319
12320         if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12321              tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12322             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12323                 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12324
12325         err = tg3_mdio_init(tp);
12326         if (err)
12327                 return err;
12328
12329         /* Initialize data/descriptor byte/word swapping. */
12330         val = tr32(GRC_MODE);
12331         val &= GRC_MODE_HOST_STACKUP;
12332         tw32(GRC_MODE, val | tp->grc_mode);
12333
12334         tg3_switch_clocks(tp);
12335
12336         /* Clear this out for sanity. */
12337         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12338
12339         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12340                               &pci_state_reg);
12341         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12342             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12343                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12344
12345                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12346                     chiprevid == CHIPREV_ID_5701_B0 ||
12347                     chiprevid == CHIPREV_ID_5701_B2 ||
12348                     chiprevid == CHIPREV_ID_5701_B5) {
12349                         void __iomem *sram_base;
12350
12351                         /* Write some dummy words into the SRAM status block
12352                          * area, see if it reads back correctly.  If the return
12353                          * value is bad, force enable the PCIX workaround.
12354                          */
12355                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12356
12357                         writel(0x00000000, sram_base);
12358                         writel(0x00000000, sram_base + 4);
12359                         writel(0xffffffff, sram_base + 4);
12360                         if (readl(sram_base) != 0x00000000)
12361                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12362                 }
12363         }
12364
12365         udelay(50);
12366         tg3_nvram_init(tp);
12367
12368         grc_misc_cfg = tr32(GRC_MISC_CFG);
12369         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12370
12371         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12372             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12373              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12374                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12375
12376         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12377             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12378                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12379         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12380                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12381                                       HOSTCC_MODE_CLRTICK_TXBD);
12382
12383                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12384                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12385                                        tp->misc_host_ctrl);
12386         }
12387
12388         /* Preserve the APE MAC_MODE bits */
12389         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12390                 tp->mac_mode = tr32(MAC_MODE) |
12391                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12392         else
12393                 tp->mac_mode = TG3_DEF_MAC_MODE;
12394
12395         /* these are limited to 10/100 only */
12396         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12397              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12398             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12399              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12400              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12401               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12402               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12403             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12404              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12405               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12406               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12407             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12408             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12409                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12410
12411         err = tg3_phy_probe(tp);
12412         if (err) {
12413                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12414                        pci_name(tp->pdev), err);
12415                 /* ... but do not return immediately ... */
12416                 tg3_mdio_fini(tp);
12417         }
12418
12419         tg3_read_partno(tp);
12420         tg3_read_fw_ver(tp);
12421
12422         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12423                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12424         } else {
12425                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12426                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12427                 else
12428                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12429         }
12430
12431         /* 5700 {AX,BX} chips have a broken status block link
12432          * change bit implementation, so we must use the
12433          * status register in those cases.
12434          */
12435         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12436                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12437         else
12438                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12439
12440         /* The led_ctrl is set during tg3_phy_probe, here we might
12441          * have to force the link status polling mechanism based
12442          * upon subsystem IDs.
12443          */
12444         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12445             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12446             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12447                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12448                                   TG3_FLAG_USE_LINKCHG_REG);
12449         }
12450
12451         /* For all SERDES we poll the MAC status register. */
12452         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12453                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12454         else
12455                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12456
12457         tp->rx_offset = NET_IP_ALIGN;
12458         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12459             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12460                 tp->rx_offset = 0;
12461
12462         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12463
12464         /* Increment the rx prod index on the rx std ring by at most
12465          * 8 for these chips to workaround hw errata.
12466          */
12467         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12468             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12469             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12470                 tp->rx_std_max_post = 8;
12471
12472         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12473                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12474                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12475
12476         return err;
12477 }
12478
12479 #ifdef CONFIG_SPARC
12480 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12481 {
12482         struct net_device *dev = tp->dev;
12483         struct pci_dev *pdev = tp->pdev;
12484         struct device_node *dp = pci_device_to_OF_node(pdev);
12485         const unsigned char *addr;
12486         int len;
12487
12488         addr = of_get_property(dp, "local-mac-address", &len);
12489         if (addr && len == 6) {
12490                 memcpy(dev->dev_addr, addr, 6);
12491                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12492                 return 0;
12493         }
12494         return -ENODEV;
12495 }
12496
12497 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12498 {
12499         struct net_device *dev = tp->dev;
12500
12501         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12502         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12503         return 0;
12504 }
12505 #endif
12506
12507 static int __devinit tg3_get_device_address(struct tg3 *tp)
12508 {
12509         struct net_device *dev = tp->dev;
12510         u32 hi, lo, mac_offset;
12511         int addr_ok = 0;
12512
12513 #ifdef CONFIG_SPARC
12514         if (!tg3_get_macaddr_sparc(tp))
12515                 return 0;
12516 #endif
12517
12518         mac_offset = 0x7c;
12519         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12520             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12521                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12522                         mac_offset = 0xcc;
12523                 if (tg3_nvram_lock(tp))
12524                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12525                 else
12526                         tg3_nvram_unlock(tp);
12527         }
12528         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12529                 mac_offset = 0x10;
12530
12531         /* First try to get it from MAC address mailbox. */
12532         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12533         if ((hi >> 16) == 0x484b) {
12534                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12535                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12536
12537                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12538                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12539                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12540                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12541                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12542
12543                 /* Some old bootcode may report a 0 MAC address in SRAM */
12544                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12545         }
12546         if (!addr_ok) {
12547                 /* Next, try NVRAM. */
12548                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12549                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12550                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12551                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12552                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12553                 }
12554                 /* Finally just fetch it out of the MAC control regs. */
12555                 else {
12556                         hi = tr32(MAC_ADDR_0_HIGH);
12557                         lo = tr32(MAC_ADDR_0_LOW);
12558
12559                         dev->dev_addr[5] = lo & 0xff;
12560                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12561                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12562                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12563                         dev->dev_addr[1] = hi & 0xff;
12564                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12565                 }
12566         }
12567
12568         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12569 #ifdef CONFIG_SPARC
12570                 if (!tg3_get_default_macaddr_sparc(tp))
12571                         return 0;
12572 #endif
12573                 return -EINVAL;
12574         }
12575         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12576         return 0;
12577 }
12578
12579 #define BOUNDARY_SINGLE_CACHELINE       1
12580 #define BOUNDARY_MULTI_CACHELINE        2
12581
12582 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12583 {
12584         int cacheline_size;
12585         u8 byte;
12586         int goal;
12587
12588         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12589         if (byte == 0)
12590                 cacheline_size = 1024;
12591         else
12592                 cacheline_size = (int) byte * 4;
12593
12594         /* On 5703 and later chips, the boundary bits have no
12595          * effect.
12596          */
12597         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12598             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12599             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12600                 goto out;
12601
12602 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12603         goal = BOUNDARY_MULTI_CACHELINE;
12604 #else
12605 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12606         goal = BOUNDARY_SINGLE_CACHELINE;
12607 #else
12608         goal = 0;
12609 #endif
12610 #endif
12611
12612         if (!goal)
12613                 goto out;
12614
12615         /* PCI controllers on most RISC systems tend to disconnect
12616          * when a device tries to burst across a cache-line boundary.
12617          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12618          *
12619          * Unfortunately, for PCI-E there are only limited
12620          * write-side controls for this, and thus for reads
12621          * we will still get the disconnects.  We'll also waste
12622          * these PCI cycles for both read and write for chips
12623          * other than 5700 and 5701 which do not implement the
12624          * boundary bits.
12625          */
12626         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12627             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12628                 switch (cacheline_size) {
12629                 case 16:
12630                 case 32:
12631                 case 64:
12632                 case 128:
12633                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12634                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12635                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12636                         } else {
12637                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12638                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12639                         }
12640                         break;
12641
12642                 case 256:
12643                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12644                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12645                         break;
12646
12647                 default:
12648                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12649                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12650                         break;
12651                 }
12652         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12653                 switch (cacheline_size) {
12654                 case 16:
12655                 case 32:
12656                 case 64:
12657                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12658                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12659                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12660                                 break;
12661                         }
12662                         /* fallthrough */
12663                 case 128:
12664                 default:
12665                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12666                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12667                         break;
12668                 }
12669         } else {
12670                 switch (cacheline_size) {
12671                 case 16:
12672                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12673                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12674                                         DMA_RWCTRL_WRITE_BNDRY_16);
12675                                 break;
12676                         }
12677                         /* fallthrough */
12678                 case 32:
12679                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12680                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12681                                         DMA_RWCTRL_WRITE_BNDRY_32);
12682                                 break;
12683                         }
12684                         /* fallthrough */
12685                 case 64:
12686                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12687                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12688                                         DMA_RWCTRL_WRITE_BNDRY_64);
12689                                 break;
12690                         }
12691                         /* fallthrough */
12692                 case 128:
12693                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12694                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12695                                         DMA_RWCTRL_WRITE_BNDRY_128);
12696                                 break;
12697                         }
12698                         /* fallthrough */
12699                 case 256:
12700                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12701                                 DMA_RWCTRL_WRITE_BNDRY_256);
12702                         break;
12703                 case 512:
12704                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12705                                 DMA_RWCTRL_WRITE_BNDRY_512);
12706                         break;
12707                 case 1024:
12708                 default:
12709                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12710                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12711                         break;
12712                 }
12713         }
12714
12715 out:
12716         return val;
12717 }
12718
12719 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12720 {
12721         struct tg3_internal_buffer_desc test_desc;
12722         u32 sram_dma_descs;
12723         int i, ret;
12724
12725         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12726
12727         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12728         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12729         tw32(RDMAC_STATUS, 0);
12730         tw32(WDMAC_STATUS, 0);
12731
12732         tw32(BUFMGR_MODE, 0);
12733         tw32(FTQ_RESET, 0);
12734
12735         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12736         test_desc.addr_lo = buf_dma & 0xffffffff;
12737         test_desc.nic_mbuf = 0x00002100;
12738         test_desc.len = size;
12739
12740         /*
12741          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12742          * the *second* time the tg3 driver was getting loaded after an
12743          * initial scan.
12744          *
12745          * Broadcom tells me:
12746          *   ...the DMA engine is connected to the GRC block and a DMA
12747          *   reset may affect the GRC block in some unpredictable way...
12748          *   The behavior of resets to individual blocks has not been tested.
12749          *
12750          * Broadcom noted the GRC reset will also reset all sub-components.
12751          */
12752         if (to_device) {
12753                 test_desc.cqid_sqid = (13 << 8) | 2;
12754
12755                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12756                 udelay(40);
12757         } else {
12758                 test_desc.cqid_sqid = (16 << 8) | 7;
12759
12760                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12761                 udelay(40);
12762         }
12763         test_desc.flags = 0x00000005;
12764
12765         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12766                 u32 val;
12767
12768                 val = *(((u32 *)&test_desc) + i);
12769                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12770                                        sram_dma_descs + (i * sizeof(u32)));
12771                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12772         }
12773         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12774
12775         if (to_device) {
12776                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12777         } else {
12778                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12779         }
12780
12781         ret = -ENODEV;
12782         for (i = 0; i < 40; i++) {
12783                 u32 val;
12784
12785                 if (to_device)
12786                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12787                 else
12788                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12789                 if ((val & 0xffff) == sram_dma_descs) {
12790                         ret = 0;
12791                         break;
12792                 }
12793
12794                 udelay(100);
12795         }
12796
12797         return ret;
12798 }
12799
12800 #define TEST_BUFFER_SIZE        0x2000
12801
12802 static int __devinit tg3_test_dma(struct tg3 *tp)
12803 {
12804         dma_addr_t buf_dma;
12805         u32 *buf, saved_dma_rwctrl;
12806         int ret;
12807
12808         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12809         if (!buf) {
12810                 ret = -ENOMEM;
12811                 goto out_nofree;
12812         }
12813
12814         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12815                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12816
12817         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12818
12819         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12820                 /* DMA read watermark not used on PCIE */
12821                 tp->dma_rwctrl |= 0x00180000;
12822         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12823                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12824                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12825                         tp->dma_rwctrl |= 0x003f0000;
12826                 else
12827                         tp->dma_rwctrl |= 0x003f000f;
12828         } else {
12829                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12830                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12831                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12832                         u32 read_water = 0x7;
12833
12834                         /* If the 5704 is behind the EPB bridge, we can
12835                          * do the less restrictive ONE_DMA workaround for
12836                          * better performance.
12837                          */
12838                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12839                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12840                                 tp->dma_rwctrl |= 0x8000;
12841                         else if (ccval == 0x6 || ccval == 0x7)
12842                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12843
12844                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12845                                 read_water = 4;
12846                         /* Set bit 23 to enable PCIX hw bug fix */
12847                         tp->dma_rwctrl |=
12848                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12849                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12850                                 (1 << 23);
12851                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12852                         /* 5780 always in PCIX mode */
12853                         tp->dma_rwctrl |= 0x00144000;
12854                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12855                         /* 5714 always in PCIX mode */
12856                         tp->dma_rwctrl |= 0x00148000;
12857                 } else {
12858                         tp->dma_rwctrl |= 0x001b000f;
12859                 }
12860         }
12861
12862         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12863             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12864                 tp->dma_rwctrl &= 0xfffffff0;
12865
12866         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12867             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12868                 /* Remove this if it causes problems for some boards. */
12869                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12870
12871                 /* On 5700/5701 chips, we need to set this bit.
12872                  * Otherwise the chip will issue cacheline transactions
12873                  * to streamable DMA memory with not all the byte
12874                  * enables turned on.  This is an error on several
12875                  * RISC PCI controllers, in particular sparc64.
12876                  *
12877                  * On 5703/5704 chips, this bit has been reassigned
12878                  * a different meaning.  In particular, it is used
12879                  * on those chips to enable a PCI-X workaround.
12880                  */
12881                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12882         }
12883
12884         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12885
12886 #if 0
12887         /* Unneeded, already done by tg3_get_invariants.  */
12888         tg3_switch_clocks(tp);
12889 #endif
12890
12891         ret = 0;
12892         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12893             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12894                 goto out;
12895
12896         /* It is best to perform DMA test with maximum write burst size
12897          * to expose the 5700/5701 write DMA bug.
12898          */
12899         saved_dma_rwctrl = tp->dma_rwctrl;
12900         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12901         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12902
12903         while (1) {
12904                 u32 *p = buf, i;
12905
12906                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12907                         p[i] = i;
12908
12909                 /* Send the buffer to the chip. */
12910                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12911                 if (ret) {
12912                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12913                         break;
12914                 }
12915
12916 #if 0
12917                 /* validate data reached card RAM correctly. */
12918                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12919                         u32 val;
12920                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
12921                         if (le32_to_cpu(val) != p[i]) {
12922                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
12923                                 /* ret = -ENODEV here? */
12924                         }
12925                         p[i] = 0;
12926                 }
12927 #endif
12928                 /* Now read it back. */
12929                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12930                 if (ret) {
12931                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12932
12933                         break;
12934                 }
12935
12936                 /* Verify it. */
12937                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12938                         if (p[i] == i)
12939                                 continue;
12940
12941                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12942                             DMA_RWCTRL_WRITE_BNDRY_16) {
12943                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12944                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12945                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12946                                 break;
12947                         } else {
12948                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12949                                 ret = -ENODEV;
12950                                 goto out;
12951                         }
12952                 }
12953
12954                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12955                         /* Success. */
12956                         ret = 0;
12957                         break;
12958                 }
12959         }
12960         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12961             DMA_RWCTRL_WRITE_BNDRY_16) {
12962                 static struct pci_device_id dma_wait_state_chipsets[] = {
12963                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12964                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12965                         { },
12966                 };
12967
12968                 /* DMA test passed without adjusting DMA boundary,
12969                  * now look for chipsets that are known to expose the
12970                  * DMA bug without failing the test.
12971                  */
12972                 if (pci_dev_present(dma_wait_state_chipsets)) {
12973                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12974                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12975                 }
12976                 else
12977                         /* Safe to use the calculated DMA boundary. */
12978                         tp->dma_rwctrl = saved_dma_rwctrl;
12979
12980                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12981         }
12982
12983 out:
12984         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12985 out_nofree:
12986         return ret;
12987 }
12988
12989 static void __devinit tg3_init_link_config(struct tg3 *tp)
12990 {
12991         tp->link_config.advertising =
12992                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12993                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12994                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12995                  ADVERTISED_Autoneg | ADVERTISED_MII);
12996         tp->link_config.speed = SPEED_INVALID;
12997         tp->link_config.duplex = DUPLEX_INVALID;
12998         tp->link_config.autoneg = AUTONEG_ENABLE;
12999         tp->link_config.active_speed = SPEED_INVALID;
13000         tp->link_config.active_duplex = DUPLEX_INVALID;
13001         tp->link_config.phy_is_low_power = 0;
13002         tp->link_config.orig_speed = SPEED_INVALID;
13003         tp->link_config.orig_duplex = DUPLEX_INVALID;
13004         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13005 }
13006
13007 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13008 {
13009         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13010                 tp->bufmgr_config.mbuf_read_dma_low_water =
13011                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13012                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13013                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13014                 tp->bufmgr_config.mbuf_high_water =
13015                         DEFAULT_MB_HIGH_WATER_5705;
13016                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13017                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13018                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13019                         tp->bufmgr_config.mbuf_high_water =
13020                                 DEFAULT_MB_HIGH_WATER_5906;
13021                 }
13022
13023                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13024                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13025                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13026                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13027                 tp->bufmgr_config.mbuf_high_water_jumbo =
13028                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13029         } else {
13030                 tp->bufmgr_config.mbuf_read_dma_low_water =
13031                         DEFAULT_MB_RDMA_LOW_WATER;
13032                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13033                         DEFAULT_MB_MACRX_LOW_WATER;
13034                 tp->bufmgr_config.mbuf_high_water =
13035                         DEFAULT_MB_HIGH_WATER;
13036
13037                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13038                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13039                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13040                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13041                 tp->bufmgr_config.mbuf_high_water_jumbo =
13042                         DEFAULT_MB_HIGH_WATER_JUMBO;
13043         }
13044
13045         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13046         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13047 }
13048
13049 static char * __devinit tg3_phy_string(struct tg3 *tp)
13050 {
13051         switch (tp->phy_id & PHY_ID_MASK) {
13052         case PHY_ID_BCM5400:    return "5400";
13053         case PHY_ID_BCM5401:    return "5401";
13054         case PHY_ID_BCM5411:    return "5411";
13055         case PHY_ID_BCM5701:    return "5701";
13056         case PHY_ID_BCM5703:    return "5703";
13057         case PHY_ID_BCM5704:    return "5704";
13058         case PHY_ID_BCM5705:    return "5705";
13059         case PHY_ID_BCM5750:    return "5750";
13060         case PHY_ID_BCM5752:    return "5752";
13061         case PHY_ID_BCM5714:    return "5714";
13062         case PHY_ID_BCM5780:    return "5780";
13063         case PHY_ID_BCM5755:    return "5755";
13064         case PHY_ID_BCM5787:    return "5787";
13065         case PHY_ID_BCM5784:    return "5784";
13066         case PHY_ID_BCM5756:    return "5722/5756";
13067         case PHY_ID_BCM5906:    return "5906";
13068         case PHY_ID_BCM5761:    return "5761";
13069         case PHY_ID_BCM8002:    return "8002/serdes";
13070         case 0:                 return "serdes";
13071         default:                return "unknown";
13072         }
13073 }
13074
13075 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13076 {
13077         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13078                 strcpy(str, "PCI Express");
13079                 return str;
13080         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13081                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13082
13083                 strcpy(str, "PCIX:");
13084
13085                 if ((clock_ctrl == 7) ||
13086                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13087                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13088                         strcat(str, "133MHz");
13089                 else if (clock_ctrl == 0)
13090                         strcat(str, "33MHz");
13091                 else if (clock_ctrl == 2)
13092                         strcat(str, "50MHz");
13093                 else if (clock_ctrl == 4)
13094                         strcat(str, "66MHz");
13095                 else if (clock_ctrl == 6)
13096                         strcat(str, "100MHz");
13097         } else {
13098                 strcpy(str, "PCI:");
13099                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13100                         strcat(str, "66MHz");
13101                 else
13102                         strcat(str, "33MHz");
13103         }
13104         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13105                 strcat(str, ":32-bit");
13106         else
13107                 strcat(str, ":64-bit");
13108         return str;
13109 }
13110
13111 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13112 {
13113         struct pci_dev *peer;
13114         unsigned int func, devnr = tp->pdev->devfn & ~7;
13115
13116         for (func = 0; func < 8; func++) {
13117                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13118                 if (peer && peer != tp->pdev)
13119                         break;
13120                 pci_dev_put(peer);
13121         }
13122         /* 5704 can be configured in single-port mode, set peer to
13123          * tp->pdev in that case.
13124          */
13125         if (!peer) {
13126                 peer = tp->pdev;
13127                 return peer;
13128         }
13129
13130         /*
13131          * We don't need to keep the refcount elevated; there's no way
13132          * to remove one half of this device without removing the other
13133          */
13134         pci_dev_put(peer);
13135
13136         return peer;
13137 }
13138
13139 static void __devinit tg3_init_coal(struct tg3 *tp)
13140 {
13141         struct ethtool_coalesce *ec = &tp->coal;
13142
13143         memset(ec, 0, sizeof(*ec));
13144         ec->cmd = ETHTOOL_GCOALESCE;
13145         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13146         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13147         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13148         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13149         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13150         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13151         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13152         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13153         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13154
13155         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13156                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13157                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13158                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13159                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13160                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13161         }
13162
13163         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13164                 ec->rx_coalesce_usecs_irq = 0;
13165                 ec->tx_coalesce_usecs_irq = 0;
13166                 ec->stats_block_coalesce_usecs = 0;
13167         }
13168 }
13169
13170 static const struct net_device_ops tg3_netdev_ops = {
13171         .ndo_open               = tg3_open,
13172         .ndo_stop               = tg3_close,
13173         .ndo_start_xmit         = tg3_start_xmit,
13174         .ndo_get_stats          = tg3_get_stats,
13175         .ndo_validate_addr      = eth_validate_addr,
13176         .ndo_set_multicast_list = tg3_set_rx_mode,
13177         .ndo_set_mac_address    = tg3_set_mac_addr,
13178         .ndo_do_ioctl           = tg3_ioctl,
13179         .ndo_tx_timeout         = tg3_tx_timeout,
13180         .ndo_change_mtu         = tg3_change_mtu,
13181 #if TG3_VLAN_TAG_USED
13182         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13183 #endif
13184 #ifdef CONFIG_NET_POLL_CONTROLLER
13185         .ndo_poll_controller    = tg3_poll_controller,
13186 #endif
13187 };
13188
13189 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13190         .ndo_open               = tg3_open,
13191         .ndo_stop               = tg3_close,
13192         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13193         .ndo_get_stats          = tg3_get_stats,
13194         .ndo_validate_addr      = eth_validate_addr,
13195         .ndo_set_multicast_list = tg3_set_rx_mode,
13196         .ndo_set_mac_address    = tg3_set_mac_addr,
13197         .ndo_do_ioctl           = tg3_ioctl,
13198         .ndo_tx_timeout         = tg3_tx_timeout,
13199         .ndo_change_mtu         = tg3_change_mtu,
13200 #if TG3_VLAN_TAG_USED
13201         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13202 #endif
13203 #ifdef CONFIG_NET_POLL_CONTROLLER
13204         .ndo_poll_controller    = tg3_poll_controller,
13205 #endif
13206 };
13207
13208 static int __devinit tg3_init_one(struct pci_dev *pdev,
13209                                   const struct pci_device_id *ent)
13210 {
13211         static int tg3_version_printed = 0;
13212         struct net_device *dev;
13213         struct tg3 *tp;
13214         int err, pm_cap;
13215         char str[40];
13216         u64 dma_mask, persist_dma_mask;
13217
13218         if (tg3_version_printed++ == 0)
13219                 printk(KERN_INFO "%s", version);
13220
13221         err = pci_enable_device(pdev);
13222         if (err) {
13223                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13224                        "aborting.\n");
13225                 return err;
13226         }
13227
13228         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13229         if (err) {
13230                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13231                        "aborting.\n");
13232                 goto err_out_disable_pdev;
13233         }
13234
13235         pci_set_master(pdev);
13236
13237         /* Find power-management capability. */
13238         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13239         if (pm_cap == 0) {
13240                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13241                        "aborting.\n");
13242                 err = -EIO;
13243                 goto err_out_free_res;
13244         }
13245
13246         dev = alloc_etherdev(sizeof(*tp));
13247         if (!dev) {
13248                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13249                 err = -ENOMEM;
13250                 goto err_out_free_res;
13251         }
13252
13253         SET_NETDEV_DEV(dev, &pdev->dev);
13254
13255 #if TG3_VLAN_TAG_USED
13256         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13257 #endif
13258
13259         tp = netdev_priv(dev);
13260         tp->pdev = pdev;
13261         tp->dev = dev;
13262         tp->pm_cap = pm_cap;
13263         tp->rx_mode = TG3_DEF_RX_MODE;
13264         tp->tx_mode = TG3_DEF_TX_MODE;
13265
13266         if (tg3_debug > 0)
13267                 tp->msg_enable = tg3_debug;
13268         else
13269                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13270
13271         /* The word/byte swap controls here control register access byte
13272          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13273          * setting below.
13274          */
13275         tp->misc_host_ctrl =
13276                 MISC_HOST_CTRL_MASK_PCI_INT |
13277                 MISC_HOST_CTRL_WORD_SWAP |
13278                 MISC_HOST_CTRL_INDIR_ACCESS |
13279                 MISC_HOST_CTRL_PCISTATE_RW;
13280
13281         /* The NONFRM (non-frame) byte/word swap controls take effect
13282          * on descriptor entries, anything which isn't packet data.
13283          *
13284          * The StrongARM chips on the board (one for tx, one for rx)
13285          * are running in big-endian mode.
13286          */
13287         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13288                         GRC_MODE_WSWAP_NONFRM_DATA);
13289 #ifdef __BIG_ENDIAN
13290         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13291 #endif
13292         spin_lock_init(&tp->lock);
13293         spin_lock_init(&tp->indirect_lock);
13294         INIT_WORK(&tp->reset_task, tg3_reset_task);
13295
13296         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13297         if (!tp->regs) {
13298                 printk(KERN_ERR PFX "Cannot map device registers, "
13299                        "aborting.\n");
13300                 err = -ENOMEM;
13301                 goto err_out_free_dev;
13302         }
13303
13304         tg3_init_link_config(tp);
13305
13306         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13307         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13308         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13309
13310         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13311         dev->ethtool_ops = &tg3_ethtool_ops;
13312         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13313         dev->irq = pdev->irq;
13314
13315         err = tg3_get_invariants(tp);
13316         if (err) {
13317                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13318                        "aborting.\n");
13319                 goto err_out_iounmap;
13320         }
13321
13322         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13323             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13324                 dev->netdev_ops = &tg3_netdev_ops;
13325         else
13326                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13327
13328
13329         /* The EPB bridge inside 5714, 5715, and 5780 and any
13330          * device behind the EPB cannot support DMA addresses > 40-bit.
13331          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13332          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13333          * do DMA address check in tg3_start_xmit().
13334          */
13335         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13336                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13337         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13338                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13339 #ifdef CONFIG_HIGHMEM
13340                 dma_mask = DMA_BIT_MASK(64);
13341 #endif
13342         } else
13343                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13344
13345         /* Configure DMA attributes. */
13346         if (dma_mask > DMA_BIT_MASK(32)) {
13347                 err = pci_set_dma_mask(pdev, dma_mask);
13348                 if (!err) {
13349                         dev->features |= NETIF_F_HIGHDMA;
13350                         err = pci_set_consistent_dma_mask(pdev,
13351                                                           persist_dma_mask);
13352                         if (err < 0) {
13353                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13354                                        "DMA for consistent allocations\n");
13355                                 goto err_out_iounmap;
13356                         }
13357                 }
13358         }
13359         if (err || dma_mask == DMA_BIT_MASK(32)) {
13360                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13361                 if (err) {
13362                         printk(KERN_ERR PFX "No usable DMA configuration, "
13363                                "aborting.\n");
13364                         goto err_out_iounmap;
13365                 }
13366         }
13367
13368         tg3_init_bufmgr_config(tp);
13369
13370         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13371                 tp->fw_needed = FIRMWARE_TG3;
13372
13373         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13374                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13375         }
13376         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13377             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13378             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13379             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13380             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13381                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13382         } else {
13383                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13384                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13385                         tp->fw_needed = FIRMWARE_TG3TSO5;
13386                 else
13387                         tp->fw_needed = FIRMWARE_TG3TSO;
13388         }
13389
13390         /* TSO is on by default on chips that support hardware TSO.
13391          * Firmware TSO on older chips gives lower performance, so it
13392          * is off by default, but can be enabled using ethtool.
13393          */
13394         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13395                 if (dev->features & NETIF_F_IP_CSUM)
13396                         dev->features |= NETIF_F_TSO;
13397                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13398                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13399                         dev->features |= NETIF_F_TSO6;
13400                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13401                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13402                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13403                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13404                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13405                         dev->features |= NETIF_F_TSO_ECN;
13406         }
13407
13408
13409         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13410             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13411             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13412                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13413                 tp->rx_pending = 63;
13414         }
13415
13416         err = tg3_get_device_address(tp);
13417         if (err) {
13418                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13419                        "aborting.\n");
13420                 goto err_out_fw;
13421         }
13422
13423         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13424                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13425                 if (!tp->aperegs) {
13426                         printk(KERN_ERR PFX "Cannot map APE registers, "
13427                                "aborting.\n");
13428                         err = -ENOMEM;
13429                         goto err_out_fw;
13430                 }
13431
13432                 tg3_ape_lock_init(tp);
13433
13434                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13435                         tg3_read_dash_ver(tp);
13436         }
13437
13438         /*
13439          * Reset chip in case UNDI or EFI driver did not shutdown
13440          * DMA self test will enable WDMAC and we'll see (spurious)
13441          * pending DMA on the PCI bus at that point.
13442          */
13443         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13444             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13445                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13446                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13447         }
13448
13449         err = tg3_test_dma(tp);
13450         if (err) {
13451                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13452                 goto err_out_apeunmap;
13453         }
13454
13455         /* flow control autonegotiation is default behavior */
13456         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13457         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13458
13459         tg3_init_coal(tp);
13460
13461         pci_set_drvdata(pdev, dev);
13462
13463         err = register_netdev(dev);
13464         if (err) {
13465                 printk(KERN_ERR PFX "Cannot register net device, "
13466                        "aborting.\n");
13467                 goto err_out_apeunmap;
13468         }
13469
13470         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13471                dev->name,
13472                tp->board_part_number,
13473                tp->pci_chip_rev_id,
13474                tg3_bus_string(tp, str),
13475                dev->dev_addr);
13476
13477         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13478                 printk(KERN_INFO
13479                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13480                        tp->dev->name,
13481                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13482                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13483         else
13484                 printk(KERN_INFO
13485                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13486                        tp->dev->name, tg3_phy_string(tp),
13487                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13488                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13489                          "10/100/1000Base-T")),
13490                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13491
13492         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13493                dev->name,
13494                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13495                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13496                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13497                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13498                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13499         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13500                dev->name, tp->dma_rwctrl,
13501                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13502                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13503
13504         return 0;
13505
13506 err_out_apeunmap:
13507         if (tp->aperegs) {
13508                 iounmap(tp->aperegs);
13509                 tp->aperegs = NULL;
13510         }
13511
13512 err_out_fw:
13513         if (tp->fw)
13514                 release_firmware(tp->fw);
13515
13516 err_out_iounmap:
13517         if (tp->regs) {
13518                 iounmap(tp->regs);
13519                 tp->regs = NULL;
13520         }
13521
13522 err_out_free_dev:
13523         free_netdev(dev);
13524
13525 err_out_free_res:
13526         pci_release_regions(pdev);
13527
13528 err_out_disable_pdev:
13529         pci_disable_device(pdev);
13530         pci_set_drvdata(pdev, NULL);
13531         return err;
13532 }
13533
13534 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13535 {
13536         struct net_device *dev = pci_get_drvdata(pdev);
13537
13538         if (dev) {
13539                 struct tg3 *tp = netdev_priv(dev);
13540
13541                 if (tp->fw)
13542                         release_firmware(tp->fw);
13543
13544                 flush_scheduled_work();
13545
13546                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13547                         tg3_phy_fini(tp);
13548                         tg3_mdio_fini(tp);
13549                 }
13550
13551                 unregister_netdev(dev);
13552                 if (tp->aperegs) {
13553                         iounmap(tp->aperegs);
13554                         tp->aperegs = NULL;
13555                 }
13556                 if (tp->regs) {
13557                         iounmap(tp->regs);
13558                         tp->regs = NULL;
13559                 }
13560                 free_netdev(dev);
13561                 pci_release_regions(pdev);
13562                 pci_disable_device(pdev);
13563                 pci_set_drvdata(pdev, NULL);
13564         }
13565 }
13566
13567 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13568 {
13569         struct net_device *dev = pci_get_drvdata(pdev);
13570         struct tg3 *tp = netdev_priv(dev);
13571         pci_power_t target_state;
13572         int err;
13573
13574         /* PCI register 4 needs to be saved whether netif_running() or not.
13575          * MSI address and data need to be saved if using MSI and
13576          * netif_running().
13577          */
13578         pci_save_state(pdev);
13579
13580         if (!netif_running(dev))
13581                 return 0;
13582
13583         flush_scheduled_work();
13584         tg3_phy_stop(tp);
13585         tg3_netif_stop(tp);
13586
13587         del_timer_sync(&tp->timer);
13588
13589         tg3_full_lock(tp, 1);
13590         tg3_disable_ints(tp);
13591         tg3_full_unlock(tp);
13592
13593         netif_device_detach(dev);
13594
13595         tg3_full_lock(tp, 0);
13596         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13597         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13598         tg3_full_unlock(tp);
13599
13600         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13601
13602         err = tg3_set_power_state(tp, target_state);
13603         if (err) {
13604                 int err2;
13605
13606                 tg3_full_lock(tp, 0);
13607
13608                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13609                 err2 = tg3_restart_hw(tp, 1);
13610                 if (err2)
13611                         goto out;
13612
13613                 tp->timer.expires = jiffies + tp->timer_offset;
13614                 add_timer(&tp->timer);
13615
13616                 netif_device_attach(dev);
13617                 tg3_netif_start(tp);
13618
13619 out:
13620                 tg3_full_unlock(tp);
13621
13622                 if (!err2)
13623                         tg3_phy_start(tp);
13624         }
13625
13626         return err;
13627 }
13628
13629 static int tg3_resume(struct pci_dev *pdev)
13630 {
13631         struct net_device *dev = pci_get_drvdata(pdev);
13632         struct tg3 *tp = netdev_priv(dev);
13633         int err;
13634
13635         pci_restore_state(tp->pdev);
13636
13637         if (!netif_running(dev))
13638                 return 0;
13639
13640         err = tg3_set_power_state(tp, PCI_D0);
13641         if (err)
13642                 return err;
13643
13644         netif_device_attach(dev);
13645
13646         tg3_full_lock(tp, 0);
13647
13648         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13649         err = tg3_restart_hw(tp, 1);
13650         if (err)
13651                 goto out;
13652
13653         tp->timer.expires = jiffies + tp->timer_offset;
13654         add_timer(&tp->timer);
13655
13656         tg3_netif_start(tp);
13657
13658 out:
13659         tg3_full_unlock(tp);
13660
13661         if (!err)
13662                 tg3_phy_start(tp);
13663
13664         return err;
13665 }
13666
13667 static struct pci_driver tg3_driver = {
13668         .name           = DRV_MODULE_NAME,
13669         .id_table       = tg3_pci_tbl,
13670         .probe          = tg3_init_one,
13671         .remove         = __devexit_p(tg3_remove_one),
13672         .suspend        = tg3_suspend,
13673         .resume         = tg3_resume
13674 };
13675
13676 static int __init tg3_init(void)
13677 {
13678         return pci_register_driver(&tg3_driver);
13679 }
13680
13681 static void __exit tg3_cleanup(void)
13682 {
13683         pci_unregister_driver(&tg3_driver);
13684 }
13685
13686 module_init(tg3_init);
13687 module_exit(tg3_cleanup);