drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43 #include <net/ip.h>
  44
  45 #include <asm/system.h>
  46 #include <asm/io.h>
  47 #include <asm/byteorder.h>
  48 #include <asm/uaccess.h>
  49
  50 #ifdef CONFIG_SPARC64
  51 #include <asm/idprom.h>
  52 #include <asm/oplib.h>
  53 #include <asm/pbm.h>
  54 #endif
  55
  56 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  57 #define TG3_VLAN_TAG_USED 1
  58 #else
  59 #define TG3_VLAN_TAG_USED 0
  60 #endif
  61
  62 #define TG3_TSO_SUPPORT 1
  63
  64 #include "tg3.h"
  65
  66 #define DRV_MODULE_NAME         "tg3"
  67 #define PFX DRV_MODULE_NAME     ": "
  68 #define DRV_MODULE_VERSION      "3.75"
  69 #define DRV_MODULE_RELDATE      "March 23, 2007"
  70
  71 #define TG3_DEF_MAC_MODE        0
  72 #define TG3_DEF_RX_MODE         0
  73 #define TG3_DEF_TX_MODE         0
  74 #define TG3_DEF_MSG_ENABLE        \
  75         (NETIF_MSG_DRV          | \
  76          NETIF_MSG_PROBE        | \
  77          NETIF_MSG_LINK         | \
  78          NETIF_MSG_TIMER        | \
  79          NETIF_MSG_IFDOWN       | \
  80          NETIF_MSG_IFUP         | \
  81          NETIF_MSG_RX_ERR       | \
  82          NETIF_MSG_TX_ERR)
  83
  84 /* length of time before we decide the hardware is borked,
  85  * and dev->tx_timeout() should be called to fix the problem
  86  */
  87 #define TG3_TX_TIMEOUT                  (5 * HZ)
  88
  89 /* hardware minimum and maximum for a single frame's data payload */
  90 #define TG3_MIN_MTU                     60
  91 #define TG3_MAX_MTU(tp) \
  92         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  93
  94 /* These numbers seem to be hard coded in the NIC firmware somehow.
  95  * You can't change the ring sizes, but you can change where you place
  96  * them in the NIC onboard memory.
  97  */
  98 #define TG3_RX_RING_SIZE                512
  99 #define TG3_DEF_RX_RING_PENDING         200
 100 #define TG3_RX_JUMBO_RING_SIZE          256
 101 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 102
 103 /* Do not place this n-ring entries value into the tp struct itself,
 104  * we really want to expose these constants to GCC so that modulo et
 105  * al.  operations are done with shifts and masks instead of with
 106  * hw multiply/modulo instructions.  Another solution would be to
 107  * replace things like '% foo' with '& (foo - 1)'.
 108  */
 109 #define TG3_RX_RCB_RING_SIZE(tp)        \
 110         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 111
 112 #define TG3_TX_RING_SIZE                512
 113 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 114
 115 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 116                                  TG3_RX_RING_SIZE)
 117 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 118                                  TG3_RX_JUMBO_RING_SIZE)
 119 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 120                                    TG3_RX_RCB_RING_SIZE(tp))
 121 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 122                                  TG3_TX_RING_SIZE)
 123 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 124
 125 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 126 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 127
 128 /* minimum number of free TX descriptors required to wake up TX process */
 129 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 130
 131 /* number of ETHTOOL_GSTATS u64's */
 132 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 133
 134 #define TG3_NUM_TEST            6
 135
 136 static char version[] __devinitdata =
 137         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 138
 139 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 140 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 141 MODULE_LICENSE("GPL");
 142 MODULE_VERSION(DRV_MODULE_VERSION);
 143
 144 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 145 module_param(tg3_debug, int, 0);
 146 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 147
 148 static struct pci_device_id tg3_pci_tbl[] = {
 149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 209         {}
 210 };
 211
 212 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 213
 214 static const struct {
 215         const char string[ETH_GSTRING_LEN];
 216 } ethtool_stats_keys[TG3_NUM_STATS] = {
 217         { "rx_octets" },
 218         { "rx_fragments" },
 219         { "rx_ucast_packets" },
 220         { "rx_mcast_packets" },
 221         { "rx_bcast_packets" },
 222         { "rx_fcs_errors" },
 223         { "rx_align_errors" },
 224         { "rx_xon_pause_rcvd" },
 225         { "rx_xoff_pause_rcvd" },
 226         { "rx_mac_ctrl_rcvd" },
 227         { "rx_xoff_entered" },
 228         { "rx_frame_too_long_errors" },
 229         { "rx_jabbers" },
 230         { "rx_undersize_packets" },
 231         { "rx_in_length_errors" },
 232         { "rx_out_length_errors" },
 233         { "rx_64_or_less_octet_packets" },
 234         { "rx_65_to_127_octet_packets" },
 235         { "rx_128_to_255_octet_packets" },
 236         { "rx_256_to_511_octet_packets" },
 237         { "rx_512_to_1023_octet_packets" },
 238         { "rx_1024_to_1522_octet_packets" },
 239         { "rx_1523_to_2047_octet_packets" },
 240         { "rx_2048_to_4095_octet_packets" },
 241         { "rx_4096_to_8191_octet_packets" },
 242         { "rx_8192_to_9022_octet_packets" },
 243
 244         { "tx_octets" },
 245         { "tx_collisions" },
 246
 247         { "tx_xon_sent" },
 248         { "tx_xoff_sent" },
 249         { "tx_flow_control" },
 250         { "tx_mac_errors" },
 251         { "tx_single_collisions" },
 252         { "tx_mult_collisions" },
 253         { "tx_deferred" },
 254         { "tx_excessive_collisions" },
 255         { "tx_late_collisions" },
 256         { "tx_collide_2times" },
 257         { "tx_collide_3times" },
 258         { "tx_collide_4times" },
 259         { "tx_collide_5times" },
 260         { "tx_collide_6times" },
 261         { "tx_collide_7times" },
 262         { "tx_collide_8times" },
 263         { "tx_collide_9times" },
 264         { "tx_collide_10times" },
 265         { "tx_collide_11times" },
 266         { "tx_collide_12times" },
 267         { "tx_collide_13times" },
 268         { "tx_collide_14times" },
 269         { "tx_collide_15times" },
 270         { "tx_ucast_packets" },
 271         { "tx_mcast_packets" },
 272         { "tx_bcast_packets" },
 273         { "tx_carrier_sense_errors" },
 274         { "tx_discards" },
 275         { "tx_errors" },
 276
 277         { "dma_writeq_full" },
 278         { "dma_write_prioq_full" },
 279         { "rxbds_empty" },
 280         { "rx_discards" },
 281         { "rx_errors" },
 282         { "rx_threshold_hit" },
 283
 284         { "dma_readq_full" },
 285         { "dma_read_prioq_full" },
 286         { "tx_comp_queue_full" },
 287
 288         { "ring_set_send_prod_index" },
 289         { "ring_status_update" },
 290         { "nic_irqs" },
 291         { "nic_avoided_irqs" },
 292         { "nic_tx_threshold_hit" }
 293 };
 294
 295 static const struct {
 296         const char string[ETH_GSTRING_LEN];
 297 } ethtool_test_keys[TG3_NUM_TEST] = {
 298         { "nvram test     (online) " },
 299         { "link test      (online) " },
 300         { "register test  (offline)" },
 301         { "memory test    (offline)" },
 302         { "loopback test  (offline)" },
 303         { "interrupt test (offline)" },
 304 };
 305
 306 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 307 {
 308         writel(val, tp->regs + off);
 309 }
 310
 311 static u32 tg3_read32(struct tg3 *tp, u32 off)
 312 {
 313         return (readl(tp->regs + off));
 314 }
 315
 316 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 317 {
 318         unsigned long flags;
 319
 320         spin_lock_irqsave(&tp->indirect_lock, flags);
 321         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 322         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 323         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 324 }
 325
 326 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 327 {
 328         writel(val, tp->regs + off);
 329         readl(tp->regs + off);
 330 }
 331
 332 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 333 {
 334         unsigned long flags;
 335         u32 val;
 336
 337         spin_lock_irqsave(&tp->indirect_lock, flags);
 338         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 339         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 340         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 341         return val;
 342 }
 343
 344 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 345 {
 346         unsigned long flags;
 347
 348         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 349                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 350                                        TG3_64BIT_REG_LOW, val);
 351                 return;
 352         }
 353         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 354                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 355                                        TG3_64BIT_REG_LOW, val);
 356                 return;
 357         }
 358
 359         spin_lock_irqsave(&tp->indirect_lock, flags);
 360         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 361         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 362         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 363
 364         /* In indirect mode when disabling interrupts, we also need
 365          * to clear the interrupt bit in the GRC local ctrl register.
 366          */
 367         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 368             (val == 0x1)) {
 369                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 370                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 371         }
 372 }
 373
 374 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 375 {
 376         unsigned long flags;
 377         u32 val;
 378
 379         spin_lock_irqsave(&tp->indirect_lock, flags);
 380         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 381         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 382         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 383         return val;
 384 }
 385
 386 /* usec_wait specifies the wait time in usec when writing to certain registers
 387  * where it is unsafe to read back the register without some delay.
 388  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 389  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 390  */
 391 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 392 {
 393         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 394             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 395                 /* Non-posted methods */
 396                 tp->write32(tp, off, val);
 397         else {
 398                 /* Posted method */
 399                 tg3_write32(tp, off, val);
 400                 if (usec_wait)
 401                         udelay(usec_wait);
 402                 tp->read32(tp, off);
 403         }
 404         /* Wait again after the read for the posted method to guarantee that
 405          * the wait time is met.
 406          */
 407         if (usec_wait)
 408                 udelay(usec_wait);
 409 }
 410
 411 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 412 {
 413         tp->write32_mbox(tp, off, val);
 414         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 415             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 416                 tp->read32_mbox(tp, off);
 417 }
 418
 419 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 420 {
 421         void __iomem *mbox = tp->regs + off;
 422         writel(val, mbox);
 423         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 424                 writel(val, mbox);
 425         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 426                 readl(mbox);
 427 }
 428
 429 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 430 {
 431         return (readl(tp->regs + off + GRCMBOX_BASE));
 432 }
 433
 434 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 435 {
 436         writel(val, tp->regs + off + GRCMBOX_BASE);
 437 }
 438
 439 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 440 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 441 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 442 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 443 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 444
 445 #define tw32(reg,val)           tp->write32(tp, reg, val)
 446 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 447 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 448 #define tr32(reg)               tp->read32(tp, reg)
 449
 450 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 451 {
 452         unsigned long flags;
 453
 454         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 455             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 456                 return;
 457
 458         spin_lock_irqsave(&tp->indirect_lock, flags);
 459         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 460                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 461                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 462
 463                 /* Always leave this as zero. */
 464                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 465         } else {
 466                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 467                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 468
 469                 /* Always leave this as zero. */
 470                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 471         }
 472         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 473 }
 474
 475 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 476 {
 477         unsigned long flags;
 478
 479         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 480             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 481                 *val = 0;
 482                 return;
 483         }
 484
 485         spin_lock_irqsave(&tp->indirect_lock, flags);
 486         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 487                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 488                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 489
 490                 /* Always leave this as zero. */
 491                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 492         } else {
 493                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 494                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 495
 496                 /* Always leave this as zero. */
 497                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 498         }
 499         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 500 }
 501
 502 static void tg3_disable_ints(struct tg3 *tp)
 503 {
 504         tw32(TG3PCI_MISC_HOST_CTRL,
 505              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 506         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 507 }
 508
 509 static inline void tg3_cond_int(struct tg3 *tp)
 510 {
 511         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 512             (tp->hw_status->status & SD_STATUS_UPDATED))
 513                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 514         else
 515                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 516                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 517 }
 518
 519 static void tg3_enable_ints(struct tg3 *tp)
 520 {
 521         tp->irq_sync = 0;
 522         wmb();
 523
 524         tw32(TG3PCI_MISC_HOST_CTRL,
 525              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 526         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 527                        (tp->last_tag << 24));
 528         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 529                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 530                                (tp->last_tag << 24));
 531         tg3_cond_int(tp);
 532 }
 533
 534 static inline unsigned int tg3_has_work(struct tg3 *tp)
 535 {
 536         struct tg3_hw_status *sblk = tp->hw_status;
 537         unsigned int work_exists = 0;
 538
 539         /* check for phy events */
 540         if (!(tp->tg3_flags &
 541               (TG3_FLAG_USE_LINKCHG_REG |
 542                TG3_FLAG_POLL_SERDES))) {
 543                 if (sblk->status & SD_STATUS_LINK_CHG)
 544                         work_exists = 1;
 545         }
 546         /* check for RX/TX work to do */
 547         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 548             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 549                 work_exists = 1;
 550
 551         return work_exists;
 552 }
 553
 554 /* tg3_restart_ints
 555  *  similar to tg3_enable_ints, but it accurately determines whether there
 556  *  is new work pending and can return without flushing the PIO write
 557  *  which reenables interrupts
 558  */
 559 static void tg3_restart_ints(struct tg3 *tp)
 560 {
 561         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 562                      tp->last_tag << 24);
 563         mmiowb();
 564
 565         /* When doing tagged status, this work check is unnecessary.
 566          * The last_tag we write above tells the chip which piece of
 567          * work we've completed.
 568          */
 569         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 570             tg3_has_work(tp))
 571                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 572                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 573 }
 574
 575 static inline void tg3_netif_stop(struct tg3 *tp)
 576 {
 577         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 578         netif_poll_disable(tp->dev);
 579         netif_tx_disable(tp->dev);
 580 }
 581
 582 static inline void tg3_netif_start(struct tg3 *tp)
 583 {
 584         netif_wake_queue(tp->dev);
 585         /* NOTE: unconditional netif_wake_queue is only appropriate
 586          * so long as all callers are assured to have free tx slots
 587          * (such as after tg3_init_hw)
 588          */
 589         netif_poll_enable(tp->dev);
 590         tp->hw_status->status |= SD_STATUS_UPDATED;
 591         tg3_enable_ints(tp);
 592 }
 593
 594 static void tg3_switch_clocks(struct tg3 *tp)
 595 {
 596         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 597         u32 orig_clock_ctrl;
 598
 599         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 600                 return;
 601
 602         orig_clock_ctrl = clock_ctrl;
 603         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 604                        CLOCK_CTRL_CLKRUN_OENABLE |
 605                        0x1f);
 606         tp->pci_clock_ctrl = clock_ctrl;
 607
 608         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 609                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 610                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 611                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 612                 }
 613         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 614                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 615                             clock_ctrl |
 616                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 617                             40);
 618                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 619                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 620                             40);
 621         }
 622         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 623 }
 624
 625 #define PHY_BUSY_LOOPS  5000
 626
 627 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 628 {
 629         u32 frame_val;
 630         unsigned int loops;
 631         int ret;
 632
 633         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 634                 tw32_f(MAC_MI_MODE,
 635                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 636                 udelay(80);
 637         }
 638
 639         *val = 0x0;
 640
 641         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 642                       MI_COM_PHY_ADDR_MASK);
 643         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 644                       MI_COM_REG_ADDR_MASK);
 645         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 646
 647         tw32_f(MAC_MI_COM, frame_val);
 648
 649         loops = PHY_BUSY_LOOPS;
 650         while (loops != 0) {
 651                 udelay(10);
 652                 frame_val = tr32(MAC_MI_COM);
 653
 654                 if ((frame_val & MI_COM_BUSY) == 0) {
 655                         udelay(5);
 656                         frame_val = tr32(MAC_MI_COM);
 657                         break;
 658                 }
 659                 loops -= 1;
 660         }
 661
 662         ret = -EBUSY;
 663         if (loops != 0) {
 664                 *val = frame_val & MI_COM_DATA_MASK;
 665                 ret = 0;
 666         }
 667
 668         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 669                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 670                 udelay(80);
 671         }
 672
 673         return ret;
 674 }
 675
 676 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 677 {
 678         u32 frame_val;
 679         unsigned int loops;
 680         int ret;
 681
 682         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 683             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 684                 return 0;
 685
 686         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 687                 tw32_f(MAC_MI_MODE,
 688                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 689                 udelay(80);
 690         }
 691
 692         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 693                       MI_COM_PHY_ADDR_MASK);
 694         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 695                       MI_COM_REG_ADDR_MASK);
 696         frame_val |= (val & MI_COM_DATA_MASK);
 697         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 698
 699         tw32_f(MAC_MI_COM, frame_val);
 700
 701         loops = PHY_BUSY_LOOPS;
 702         while (loops != 0) {
 703                 udelay(10);
 704                 frame_val = tr32(MAC_MI_COM);
 705                 if ((frame_val & MI_COM_BUSY) == 0) {
 706                         udelay(5);
 707                         frame_val = tr32(MAC_MI_COM);
 708                         break;
 709                 }
 710                 loops -= 1;
 711         }
 712
 713         ret = -EBUSY;
 714         if (loops != 0)
 715                 ret = 0;
 716
 717         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 718                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 719                 udelay(80);
 720         }
 721
 722         return ret;
 723 }
 724
 725 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 726 {
 727         u32 val;
 728
 729         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 730                 return;
 731
 732         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 733             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 734                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 735                              (val | (1 << 15) | (1 << 4)));
 736 }
 737
 738 static int tg3_bmcr_reset(struct tg3 *tp)
 739 {
 740         u32 phy_control;
 741         int limit, err;
 742
 743         /* OK, reset it, and poll the BMCR_RESET bit until it
 744          * clears or we time out.
 745          */
 746         phy_control = BMCR_RESET;
 747         err = tg3_writephy(tp, MII_BMCR, phy_control);
 748         if (err != 0)
 749                 return -EBUSY;
 750
 751         limit = 5000;
 752         while (limit--) {
 753                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 754                 if (err != 0)
 755                         return -EBUSY;
 756
 757                 if ((phy_control & BMCR_RESET) == 0) {
 758                         udelay(40);
 759                         break;
 760                 }
 761                 udelay(10);
 762         }
 763         if (limit <= 0)
 764                 return -EBUSY;
 765
 766         return 0;
 767 }
 768
 769 static int tg3_wait_macro_done(struct tg3 *tp)
 770 {
 771         int limit = 100;
 772
 773         while (limit--) {
 774                 u32 tmp32;
 775
 776                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 777                         if ((tmp32 & 0x1000) == 0)
 778                                 break;
 779                 }
 780         }
 781         if (limit <= 0)
 782                 return -EBUSY;
 783
 784         return 0;
 785 }
 786
 787 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 788 {
 789         static const u32 test_pat[4][6] = {
 790         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 791         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 792         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 793         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 794         };
 795         int chan;
 796
 797         for (chan = 0; chan < 4; chan++) {
 798                 int i;
 799
 800                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 801                              (chan * 0x2000) | 0x0200);
 802                 tg3_writephy(tp, 0x16, 0x0002);
 803
 804                 for (i = 0; i < 6; i++)
 805                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 806                                      test_pat[chan][i]);
 807
 808                 tg3_writephy(tp, 0x16, 0x0202);
 809                 if (tg3_wait_macro_done(tp)) {
 810                         *resetp = 1;
 811                         return -EBUSY;
 812                 }
 813
 814                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 815                              (chan * 0x2000) | 0x0200);
 816                 tg3_writephy(tp, 0x16, 0x0082);
 817                 if (tg3_wait_macro_done(tp)) {
 818                         *resetp = 1;
 819                         return -EBUSY;
 820                 }
 821
 822                 tg3_writephy(tp, 0x16, 0x0802);
 823                 if (tg3_wait_macro_done(tp)) {
 824                         *resetp = 1;
 825                         return -EBUSY;
 826                 }
 827
 828                 for (i = 0; i < 6; i += 2) {
 829                         u32 low, high;
 830
 831                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 832                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 833                             tg3_wait_macro_done(tp)) {
 834                                 *resetp = 1;
 835                                 return -EBUSY;
 836                         }
 837                         low &= 0x7fff;
 838                         high &= 0x000f;
 839                         if (low != test_pat[chan][i] ||
 840                             high != test_pat[chan][i+1]) {
 841                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 842                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 843                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 844
 845                                 return -EBUSY;
 846                         }
 847                 }
 848         }
 849
 850         return 0;
 851 }
 852
 853 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 854 {
 855         int chan;
 856
 857         for (chan = 0; chan < 4; chan++) {
 858                 int i;
 859
 860                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 861                              (chan * 0x2000) | 0x0200);
 862                 tg3_writephy(tp, 0x16, 0x0002);
 863                 for (i = 0; i < 6; i++)
 864                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 865                 tg3_writephy(tp, 0x16, 0x0202);
 866                 if (tg3_wait_macro_done(tp))
 867                         return -EBUSY;
 868         }
 869
 870         return 0;
 871 }
 872
 873 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 874 {
 875         u32 reg32, phy9_orig;
 876         int retries, do_phy_reset, err;
 877
 878         retries = 10;
 879         do_phy_reset = 1;
 880         do {
 881                 if (do_phy_reset) {
 882                         err = tg3_bmcr_reset(tp);
 883                         if (err)
 884                                 return err;
 885                         do_phy_reset = 0;
 886                 }
 887
 888                 /* Disable transmitter and interrupt.  */
 889                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 890                         continue;
 891
 892                 reg32 |= 0x3000;
 893                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 894
 895                 /* Set full-duplex, 1000 mbps.  */
 896                 tg3_writephy(tp, MII_BMCR,
 897                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 898
 899                 /* Set to master mode.  */
 900                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 901                         continue;
 902
 903                 tg3_writephy(tp, MII_TG3_CTRL,
 904                              (MII_TG3_CTRL_AS_MASTER |
 905                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 906
 907                 /* Enable SM_DSP_CLOCK and 6dB.  */
 908                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 909
 910                 /* Block the PHY control access.  */
 911                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 912                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 913
 914                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 915                 if (!err)
 916                         break;
 917         } while (--retries);
 918
 919         err = tg3_phy_reset_chanpat(tp);
 920         if (err)
 921                 return err;
 922
 923         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 924         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 925
 926         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 927         tg3_writephy(tp, 0x16, 0x0000);
 928
 929         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 930             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 931                 /* Set Extended packet length bit for jumbo frames */
 932                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 933         }
 934         else {
 935                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 936         }
 937
 938         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 939
 940         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 941                 reg32 &= ~0x3000;
 942                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 943         } else if (!err)
 944                 err = -EBUSY;
 945
 946         return err;
 947 }
 948
 949 static void tg3_link_report(struct tg3 *);
 950
 951 /* This will reset the tigon3 PHY if there is no valid
 952  * link unless the FORCE argument is non-zero.
 953  */
 954 static int tg3_phy_reset(struct tg3 *tp)
 955 {
 956         u32 phy_status;
 957         int err;
 958
 959         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 960                 u32 val;
 961
 962                 val = tr32(GRC_MISC_CFG);
 963                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
 964                 udelay(40);
 965         }
 966         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 967         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 968         if (err != 0)
 969                 return -EBUSY;
 970
 971         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 972                 netif_carrier_off(tp->dev);
 973                 tg3_link_report(tp);
 974         }
 975
 976         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 978             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 979                 err = tg3_phy_reset_5703_4_5(tp);
 980                 if (err)
 981                         return err;
 982                 goto out;
 983         }
 984
 985         err = tg3_bmcr_reset(tp);
 986         if (err)
 987                 return err;
 988
 989 out:
 990         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 991                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 992                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 993                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 994                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 995                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 996                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 997         }
 998         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 999                 tg3_writephy(tp, 0x1c, 0x8d68);
1000                 tg3_writephy(tp, 0x1c, 0x8d68);
1001         }
1002         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1003                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1004                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1005                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1006                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1007                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1008                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1009                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1010                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1011         }
1012         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1013                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1014                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1015                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1016                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1017                         tg3_writephy(tp, MII_TG3_TEST1,
1018                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1019                 } else
1020                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1021                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1022         }
1023         /* Set Extended packet length bit (bit 14) on all chips that */
1024         /* support jumbo frames */
1025         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1026                 /* Cannot do read-modify-write on 5401 */
1027                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1028         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1029                 u32 phy_reg;
1030
1031                 /* Set bit 14 with read-modify-write to preserve other bits */
1032                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1033                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1034                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1035         }
1036
1037         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1038          * jumbo frames transmission.
1039          */
1040         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1041                 u32 phy_reg;
1042
1043                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1044                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1045                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1046         }
1047
1048         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1049                 u32 phy_reg;
1050
1051                 /* adjust output voltage */
1052                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1053
1054                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1055                         u32 phy_reg2;
1056
1057                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1058                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1059                         /* Enable auto-MDIX */
1060                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1061                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1062                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1063                 }
1064         }
1065
1066         tg3_phy_set_wirespeed(tp);
1067         return 0;
1068 }
1069
1070 static void tg3_frob_aux_power(struct tg3 *tp)
1071 {
1072         struct tg3 *tp_peer = tp;
1073
1074         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1075                 return;
1076
1077         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1078             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1079                 struct net_device *dev_peer;
1080
1081                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1082                 /* remove_one() may have been run on the peer. */
1083                 if (!dev_peer)
1084                         tp_peer = tp;
1085                 else
1086                         tp_peer = netdev_priv(dev_peer);
1087         }
1088
1089         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1090             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1091             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1092             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1093                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1094                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1095                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1096                                     (GRC_LCLCTRL_GPIO_OE0 |
1097                                      GRC_LCLCTRL_GPIO_OE1 |
1098                                      GRC_LCLCTRL_GPIO_OE2 |
1099                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1100                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1101                                     100);
1102                 } else {
1103                         u32 no_gpio2;
1104                         u32 grc_local_ctrl = 0;
1105
1106                         if (tp_peer != tp &&
1107                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1108                                 return;
1109
1110                         /* Workaround to prevent overdrawing Amps. */
1111                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1112                             ASIC_REV_5714) {
1113                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1114                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1115                                             grc_local_ctrl, 100);
1116                         }
1117
1118                         /* On 5753 and variants, GPIO2 cannot be used. */
1119                         no_gpio2 = tp->nic_sram_data_cfg &
1120                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1121
1122                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1123                                          GRC_LCLCTRL_GPIO_OE1 |
1124                                          GRC_LCLCTRL_GPIO_OE2 |
1125                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1126                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1127                         if (no_gpio2) {
1128                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1129                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1130                         }
1131                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1132                                                     grc_local_ctrl, 100);
1133
1134                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1135
1136                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1137                                                     grc_local_ctrl, 100);
1138
1139                         if (!no_gpio2) {
1140                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1141                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1142                                             grc_local_ctrl, 100);
1143                         }
1144                 }
1145         } else {
1146                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1147                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1148                         if (tp_peer != tp &&
1149                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1150                                 return;
1151
1152                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1153                                     (GRC_LCLCTRL_GPIO_OE1 |
1154                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1155
1156                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1157                                     GRC_LCLCTRL_GPIO_OE1, 100);
1158
1159                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1160                                     (GRC_LCLCTRL_GPIO_OE1 |
1161                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1162                 }
1163         }
1164 }
1165
1166 static int tg3_setup_phy(struct tg3 *, int);
1167
1168 #define RESET_KIND_SHUTDOWN     0
1169 #define RESET_KIND_INIT         1
1170 #define RESET_KIND_SUSPEND      2
1171
1172 static void tg3_write_sig_post_reset(struct tg3 *, int);
1173 static int tg3_halt_cpu(struct tg3 *, u32);
1174 static int tg3_nvram_lock(struct tg3 *);
1175 static void tg3_nvram_unlock(struct tg3 *);
1176
1177 static void tg3_power_down_phy(struct tg3 *tp)
1178 {
1179         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1180                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1181                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1182                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1183
1184                         sg_dig_ctrl |=
1185                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1186                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1187                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1188                 }
1189                 return;
1190         }
1191
1192         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1193                 u32 val;
1194
1195                 tg3_bmcr_reset(tp);
1196                 val = tr32(GRC_MISC_CFG);
1197                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1198                 udelay(40);
1199                 return;
1200         } else {
1201                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1202                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1203                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1204         }
1205
1206         /* The PHY should not be powered down on some chips because
1207          * of bugs.
1208          */
1209         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1210             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1211             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1212              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1213                 return;
1214         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1215 }
1216
1217 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1218 {
1219         u32 misc_host_ctrl;
1220         u16 power_control, power_caps;
1221         int pm = tp->pm_cap;
1222
1223         /* Make sure register accesses (indirect or otherwise)
1224          * will function correctly.
1225          */
1226         pci_write_config_dword(tp->pdev,
1227                                TG3PCI_MISC_HOST_CTRL,
1228                                tp->misc_host_ctrl);
1229
1230         pci_read_config_word(tp->pdev,
1231                              pm + PCI_PM_CTRL,
1232                              &power_control);
1233         power_control |= PCI_PM_CTRL_PME_STATUS;
1234         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1235         switch (state) {
1236         case PCI_D0:
1237                 power_control |= 0;
1238                 pci_write_config_word(tp->pdev,
1239                                       pm + PCI_PM_CTRL,
1240                                       power_control);
1241                 udelay(100);    /* Delay after power state change */
1242
1243                 /* Switch out of Vaux if it is a NIC */
1244                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1245                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1246
1247                 return 0;
1248
1249         case PCI_D1:
1250                 power_control |= 1;
1251                 break;
1252
1253         case PCI_D2:
1254                 power_control |= 2;
1255                 break;
1256
1257         case PCI_D3hot:
1258                 power_control |= 3;
1259                 break;
1260
1261         default:
1262                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1263                        "requested.\n",
1264                        tp->dev->name, state);
1265                 return -EINVAL;
1266         };
1267
1268         power_control |= PCI_PM_CTRL_PME_ENABLE;
1269
1270         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1271         tw32(TG3PCI_MISC_HOST_CTRL,
1272              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1273
1274         if (tp->link_config.phy_is_low_power == 0) {
1275                 tp->link_config.phy_is_low_power = 1;
1276                 tp->link_config.orig_speed = tp->link_config.speed;
1277                 tp->link_config.orig_duplex = tp->link_config.duplex;
1278                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1279         }
1280
1281         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1282                 tp->link_config.speed = SPEED_10;
1283                 tp->link_config.duplex = DUPLEX_HALF;
1284                 tp->link_config.autoneg = AUTONEG_ENABLE;
1285                 tg3_setup_phy(tp, 0);
1286         }
1287
1288         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1289                 u32 val;
1290
1291                 val = tr32(GRC_VCPU_EXT_CTRL);
1292                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1293         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1294                 int i;
1295                 u32 val;
1296
1297                 for (i = 0; i < 200; i++) {
1298                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1299                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1300                                 break;
1301                         msleep(1);
1302                 }
1303         }
1304         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1305                                              WOL_DRV_STATE_SHUTDOWN |
1306                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1307
1308         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1309
1310         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1311                 u32 mac_mode;
1312
1313                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1314                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1315                         udelay(40);
1316
1317                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1318                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1319                         else
1320                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1321
1322                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1323                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1324                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1325                 } else {
1326                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1327                 }
1328
1329                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1330                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1331
1332                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1333                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1334                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1335
1336                 tw32_f(MAC_MODE, mac_mode);
1337                 udelay(100);
1338
1339                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1340                 udelay(10);
1341         }
1342
1343         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1344             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1345              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1346                 u32 base_val;
1347
1348                 base_val = tp->pci_clock_ctrl;
1349                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1350                              CLOCK_CTRL_TXCLK_DISABLE);
1351
1352                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1353                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1354         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1355                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1356                 /* do nothing */
1357         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1358                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1359                 u32 newbits1, newbits2;
1360
1361                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1362                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1363                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1364                                     CLOCK_CTRL_TXCLK_DISABLE |
1365                                     CLOCK_CTRL_ALTCLK);
1366                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1367                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1368                         newbits1 = CLOCK_CTRL_625_CORE;
1369                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1370                 } else {
1371                         newbits1 = CLOCK_CTRL_ALTCLK;
1372                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1373                 }
1374
1375                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1376                             40);
1377
1378                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1379                             40);
1380
1381                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1382                         u32 newbits3;
1383
1384                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1385                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1386                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1387                                             CLOCK_CTRL_TXCLK_DISABLE |
1388                                             CLOCK_CTRL_44MHZ_CORE);
1389                         } else {
1390                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1391                         }
1392
1393                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1394                                     tp->pci_clock_ctrl | newbits3, 40);
1395                 }
1396         }
1397
1398         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1399             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1400                 tg3_power_down_phy(tp);
1401
1402         tg3_frob_aux_power(tp);
1403
1404         /* Workaround for unstable PLL clock */
1405         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1406             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1407                 u32 val = tr32(0x7d00);
1408
1409                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1410                 tw32(0x7d00, val);
1411                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1412                         int err;
1413
1414                         err = tg3_nvram_lock(tp);
1415                         tg3_halt_cpu(tp, RX_CPU_BASE);
1416                         if (!err)
1417                                 tg3_nvram_unlock(tp);
1418                 }
1419         }
1420
1421         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1422
1423         /* Finally, set the new power state. */
1424         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1425         udelay(100);    /* Delay after power state change */
1426
1427         return 0;
1428 }
1429
1430 static void tg3_link_report(struct tg3 *tp)
1431 {
1432         if (!netif_carrier_ok(tp->dev)) {
1433                 if (netif_msg_link(tp))
1434                         printk(KERN_INFO PFX "%s: Link is down.\n",
1435                                tp->dev->name);
1436         } else if (netif_msg_link(tp)) {
1437                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1438                        tp->dev->name,
1439                        (tp->link_config.active_speed == SPEED_1000 ?
1440                         1000 :
1441                         (tp->link_config.active_speed == SPEED_100 ?
1442                          100 : 10)),
1443                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1444                         "full" : "half"));
1445
1446                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1447                        "%s for RX.\n",
1448                        tp->dev->name,
1449                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1450                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1451         }
1452 }
1453
1454 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1455 {
1456         u32 new_tg3_flags = 0;
1457         u32 old_rx_mode = tp->rx_mode;
1458         u32 old_tx_mode = tp->tx_mode;
1459
1460         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1461
1462                 /* Convert 1000BaseX flow control bits to 1000BaseT
1463                  * bits before resolving flow control.
1464                  */
1465                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1466                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1467                                        ADVERTISE_PAUSE_ASYM);
1468                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1469
1470                         if (local_adv & ADVERTISE_1000XPAUSE)
1471                                 local_adv |= ADVERTISE_PAUSE_CAP;
1472                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1473                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1474                         if (remote_adv & LPA_1000XPAUSE)
1475                                 remote_adv |= LPA_PAUSE_CAP;
1476                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1477                                 remote_adv |= LPA_PAUSE_ASYM;
1478                 }
1479
1480                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1481                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1482                                 if (remote_adv & LPA_PAUSE_CAP)
1483                                         new_tg3_flags |=
1484                                                 (TG3_FLAG_RX_PAUSE |
1485                                                 TG3_FLAG_TX_PAUSE);
1486                                 else if (remote_adv & LPA_PAUSE_ASYM)
1487                                         new_tg3_flags |=
1488                                                 (TG3_FLAG_RX_PAUSE);
1489                         } else {
1490                                 if (remote_adv & LPA_PAUSE_CAP)
1491                                         new_tg3_flags |=
1492                                                 (TG3_FLAG_RX_PAUSE |
1493                                                 TG3_FLAG_TX_PAUSE);
1494                         }
1495                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1496                         if ((remote_adv & LPA_PAUSE_CAP) &&
1497                         (remote_adv & LPA_PAUSE_ASYM))
1498                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1499                 }
1500
1501                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1502                 tp->tg3_flags |= new_tg3_flags;
1503         } else {
1504                 new_tg3_flags = tp->tg3_flags;
1505         }
1506
1507         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1508                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1509         else
1510                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1511
1512         if (old_rx_mode != tp->rx_mode) {
1513                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1514         }
1515
1516         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1517                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1518         else
1519                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1520
1521         if (old_tx_mode != tp->tx_mode) {
1522                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1523         }
1524 }
1525
1526 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1527 {
1528         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1529         case MII_TG3_AUX_STAT_10HALF:
1530                 *speed = SPEED_10;
1531                 *duplex = DUPLEX_HALF;
1532                 break;
1533
1534         case MII_TG3_AUX_STAT_10FULL:
1535                 *speed = SPEED_10;
1536                 *duplex = DUPLEX_FULL;
1537                 break;
1538
1539         case MII_TG3_AUX_STAT_100HALF:
1540                 *speed = SPEED_100;
1541                 *duplex = DUPLEX_HALF;
1542                 break;
1543
1544         case MII_TG3_AUX_STAT_100FULL:
1545                 *speed = SPEED_100;
1546                 *duplex = DUPLEX_FULL;
1547                 break;
1548
1549         case MII_TG3_AUX_STAT_1000HALF:
1550                 *speed = SPEED_1000;
1551                 *duplex = DUPLEX_HALF;
1552                 break;
1553
1554         case MII_TG3_AUX_STAT_1000FULL:
1555                 *speed = SPEED_1000;
1556                 *duplex = DUPLEX_FULL;
1557                 break;
1558
1559         default:
1560                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1561                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1562                                  SPEED_10;
1563                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1564                                   DUPLEX_HALF;
1565                         break;
1566                 }
1567                 *speed = SPEED_INVALID;
1568                 *duplex = DUPLEX_INVALID;
1569                 break;
1570         };
1571 }
1572
1573 static void tg3_phy_copper_begin(struct tg3 *tp)
1574 {
1575         u32 new_adv;
1576         int i;
1577
1578         if (tp->link_config.phy_is_low_power) {
1579                 /* Entering low power mode.  Disable gigabit and
1580                  * 100baseT advertisements.
1581                  */
1582                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1583
1584                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1585                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1586                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1587                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1588
1589                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1590         } else if (tp->link_config.speed == SPEED_INVALID) {
1591                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1592                         tp->link_config.advertising &=
1593                                 ~(ADVERTISED_1000baseT_Half |
1594                                   ADVERTISED_1000baseT_Full);
1595
1596                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1597                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1598                         new_adv |= ADVERTISE_10HALF;
1599                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1600                         new_adv |= ADVERTISE_10FULL;
1601                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1602                         new_adv |= ADVERTISE_100HALF;
1603                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1604                         new_adv |= ADVERTISE_100FULL;
1605                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1606
1607                 if (tp->link_config.advertising &
1608                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1609                         new_adv = 0;
1610                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1611                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1612                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1613                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1614                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1615                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1616                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1617                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1618                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1619                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1620                 } else {
1621                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1622                 }
1623         } else {
1624                 /* Asking for a specific link mode. */
1625                 if (tp->link_config.speed == SPEED_1000) {
1626                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1627                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1628
1629                         if (tp->link_config.duplex == DUPLEX_FULL)
1630                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1631                         else
1632                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1633                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1634                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1635                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1636                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1637                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1638                 } else {
1639                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1640
1641                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1642                         if (tp->link_config.speed == SPEED_100) {
1643                                 if (tp->link_config.duplex == DUPLEX_FULL)
1644                                         new_adv |= ADVERTISE_100FULL;
1645                                 else
1646                                         new_adv |= ADVERTISE_100HALF;
1647                         } else {
1648                                 if (tp->link_config.duplex == DUPLEX_FULL)
1649                                         new_adv |= ADVERTISE_10FULL;
1650                                 else
1651                                         new_adv |= ADVERTISE_10HALF;
1652                         }
1653                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1654                 }
1655         }
1656
1657         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1658             tp->link_config.speed != SPEED_INVALID) {
1659                 u32 bmcr, orig_bmcr;
1660
1661                 tp->link_config.active_speed = tp->link_config.speed;
1662                 tp->link_config.active_duplex = tp->link_config.duplex;
1663
1664                 bmcr = 0;
1665                 switch (tp->link_config.speed) {
1666                 default:
1667                 case SPEED_10:
1668                         break;
1669
1670                 case SPEED_100:
1671                         bmcr |= BMCR_SPEED100;
1672                         break;
1673
1674                 case SPEED_1000:
1675                         bmcr |= TG3_BMCR_SPEED1000;
1676                         break;
1677                 };
1678
1679                 if (tp->link_config.duplex == DUPLEX_FULL)
1680                         bmcr |= BMCR_FULLDPLX;
1681
1682                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1683                     (bmcr != orig_bmcr)) {
1684                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1685                         for (i = 0; i < 1500; i++) {
1686                                 u32 tmp;
1687
1688                                 udelay(10);
1689                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1690                                     tg3_readphy(tp, MII_BMSR, &tmp))
1691                                         continue;
1692                                 if (!(tmp & BMSR_LSTATUS)) {
1693                                         udelay(40);
1694                                         break;
1695                                 }
1696                         }
1697                         tg3_writephy(tp, MII_BMCR, bmcr);
1698                         udelay(40);
1699                 }
1700         } else {
1701                 tg3_writephy(tp, MII_BMCR,
1702                              BMCR_ANENABLE | BMCR_ANRESTART);
1703         }
1704 }
1705
1706 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1707 {
1708         int err;
1709
1710         /* Turn off tap power management. */
1711         /* Set Extended packet length bit */
1712         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1713
1714         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1715         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1716
1717         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1718         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1719
1720         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1721         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1722
1723         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1724         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1725
1726         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1727         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1728
1729         udelay(40);
1730
1731         return err;
1732 }
1733
1734 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1735 {
1736         u32 adv_reg, all_mask = 0;
1737
1738         if (mask & ADVERTISED_10baseT_Half)
1739                 all_mask |= ADVERTISE_10HALF;
1740         if (mask & ADVERTISED_10baseT_Full)
1741                 all_mask |= ADVERTISE_10FULL;
1742         if (mask & ADVERTISED_100baseT_Half)
1743                 all_mask |= ADVERTISE_100HALF;
1744         if (mask & ADVERTISED_100baseT_Full)
1745                 all_mask |= ADVERTISE_100FULL;
1746
1747         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1748                 return 0;
1749
1750         if ((adv_reg & all_mask) != all_mask)
1751                 return 0;
1752         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1753                 u32 tg3_ctrl;
1754
1755                 all_mask = 0;
1756                 if (mask & ADVERTISED_1000baseT_Half)
1757                         all_mask |= ADVERTISE_1000HALF;
1758                 if (mask & ADVERTISED_1000baseT_Full)
1759                         all_mask |= ADVERTISE_1000FULL;
1760
1761                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1762                         return 0;
1763
1764                 if ((tg3_ctrl & all_mask) != all_mask)
1765                         return 0;
1766         }
1767         return 1;
1768 }
1769
1770 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1771 {
1772         int current_link_up;
1773         u32 bmsr, dummy;
1774         u16 current_speed;
1775         u8 current_duplex;
1776         int i, err;
1777
1778         tw32(MAC_EVENT, 0);
1779
1780         tw32_f(MAC_STATUS,
1781              (MAC_STATUS_SYNC_CHANGED |
1782               MAC_STATUS_CFG_CHANGED |
1783               MAC_STATUS_MI_COMPLETION |
1784               MAC_STATUS_LNKSTATE_CHANGED));
1785         udelay(40);
1786
1787         tp->mi_mode = MAC_MI_MODE_BASE;
1788         tw32_f(MAC_MI_MODE, tp->mi_mode);
1789         udelay(80);
1790
1791         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1792
1793         /* Some third-party PHYs need to be reset on link going
1794          * down.
1795          */
1796         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1797              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1798              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1799             netif_carrier_ok(tp->dev)) {
1800                 tg3_readphy(tp, MII_BMSR, &bmsr);
1801                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1802                     !(bmsr & BMSR_LSTATUS))
1803                         force_reset = 1;
1804         }
1805         if (force_reset)
1806                 tg3_phy_reset(tp);
1807
1808         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1809                 tg3_readphy(tp, MII_BMSR, &bmsr);
1810                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1811                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1812                         bmsr = 0;
1813
1814                 if (!(bmsr & BMSR_LSTATUS)) {
1815                         err = tg3_init_5401phy_dsp(tp);
1816                         if (err)
1817                                 return err;
1818
1819                         tg3_readphy(tp, MII_BMSR, &bmsr);
1820                         for (i = 0; i < 1000; i++) {
1821                                 udelay(10);
1822                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1823                                     (bmsr & BMSR_LSTATUS)) {
1824                                         udelay(40);
1825                                         break;
1826                                 }
1827                         }
1828
1829                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1830                             !(bmsr & BMSR_LSTATUS) &&
1831                             tp->link_config.active_speed == SPEED_1000) {
1832                                 err = tg3_phy_reset(tp);
1833                                 if (!err)
1834                                         err = tg3_init_5401phy_dsp(tp);
1835                                 if (err)
1836                                         return err;
1837                         }
1838                 }
1839         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1840                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1841                 /* 5701 {A0,B0} CRC bug workaround */
1842                 tg3_writephy(tp, 0x15, 0x0a75);
1843                 tg3_writephy(tp, 0x1c, 0x8c68);
1844                 tg3_writephy(tp, 0x1c, 0x8d68);
1845                 tg3_writephy(tp, 0x1c, 0x8c68);
1846         }
1847
1848         /* Clear pending interrupts... */
1849         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1850         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1851
1852         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1853                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1854         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1855                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1856
1857         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1858             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1859                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1860                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1861                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1862                 else
1863                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1864         }
1865
1866         current_link_up = 0;
1867         current_speed = SPEED_INVALID;
1868         current_duplex = DUPLEX_INVALID;
1869
1870         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1871                 u32 val;
1872
1873                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1874                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1875                 if (!(val & (1 << 10))) {
1876                         val |= (1 << 10);
1877                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1878                         goto relink;
1879                 }
1880         }
1881
1882         bmsr = 0;
1883         for (i = 0; i < 100; i++) {
1884                 tg3_readphy(tp, MII_BMSR, &bmsr);
1885                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1886                     (bmsr & BMSR_LSTATUS))
1887                         break;
1888                 udelay(40);
1889         }
1890
1891         if (bmsr & BMSR_LSTATUS) {
1892                 u32 aux_stat, bmcr;
1893
1894                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1895                 for (i = 0; i < 2000; i++) {
1896                         udelay(10);
1897                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1898                             aux_stat)
1899                                 break;
1900                 }
1901
1902                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1903                                              &current_speed,
1904                                              &current_duplex);
1905
1906                 bmcr = 0;
1907                 for (i = 0; i < 200; i++) {
1908                         tg3_readphy(tp, MII_BMCR, &bmcr);
1909                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1910                                 continue;
1911                         if (bmcr && bmcr != 0x7fff)
1912                                 break;
1913                         udelay(10);
1914                 }
1915
1916                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1917                         if (bmcr & BMCR_ANENABLE) {
1918                                 current_link_up = 1;
1919
1920                                 /* Force autoneg restart if we are exiting
1921                                  * low power mode.
1922                                  */
1923                                 if (!tg3_copper_is_advertising_all(tp,
1924                                                 tp->link_config.advertising))
1925                                         current_link_up = 0;
1926                         } else {
1927                                 current_link_up = 0;
1928                         }
1929                 } else {
1930                         if (!(bmcr & BMCR_ANENABLE) &&
1931                             tp->link_config.speed == current_speed &&
1932                             tp->link_config.duplex == current_duplex) {
1933                                 current_link_up = 1;
1934                         } else {
1935                                 current_link_up = 0;
1936                         }
1937                 }
1938
1939                 tp->link_config.active_speed = current_speed;
1940                 tp->link_config.active_duplex = current_duplex;
1941         }
1942
1943         if (current_link_up == 1 &&
1944             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1945             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1946                 u32 local_adv, remote_adv;
1947
1948                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1949                         local_adv = 0;
1950                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1951
1952                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1953                         remote_adv = 0;
1954
1955                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1956
1957                 /* If we are not advertising full pause capability,
1958                  * something is wrong.  Bring the link down and reconfigure.
1959                  */
1960                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1961                         current_link_up = 0;
1962                 } else {
1963                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1964                 }
1965         }
1966 relink:
1967         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1968                 u32 tmp;
1969
1970                 tg3_phy_copper_begin(tp);
1971
1972                 tg3_readphy(tp, MII_BMSR, &tmp);
1973                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1974                     (tmp & BMSR_LSTATUS))
1975                         current_link_up = 1;
1976         }
1977
1978         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1979         if (current_link_up == 1) {
1980                 if (tp->link_config.active_speed == SPEED_100 ||
1981                     tp->link_config.active_speed == SPEED_10)
1982                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1983                 else
1984                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1985         } else
1986                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1987
1988         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1989         if (tp->link_config.active_duplex == DUPLEX_HALF)
1990                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1991
1992         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1993         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1994                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1995                     (current_link_up == 1 &&
1996                      tp->link_config.active_speed == SPEED_10))
1997                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1998         } else {
1999                 if (current_link_up == 1)
2000                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2001         }
2002
2003         /* ??? Without this setting Netgear GA302T PHY does not
2004          * ??? send/receive packets...
2005          */
2006         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2007             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2008                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2009                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2010                 udelay(80);
2011         }
2012
2013         tw32_f(MAC_MODE, tp->mac_mode);
2014         udelay(40);
2015
2016         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2017                 /* Polled via timer. */
2018                 tw32_f(MAC_EVENT, 0);
2019         } else {
2020                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2021         }
2022         udelay(40);
2023
2024         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2025             current_link_up == 1 &&
2026             tp->link_config.active_speed == SPEED_1000 &&
2027             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2028              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2029                 udelay(120);
2030                 tw32_f(MAC_STATUS,
2031                      (MAC_STATUS_SYNC_CHANGED |
2032                       MAC_STATUS_CFG_CHANGED));
2033                 udelay(40);
2034                 tg3_write_mem(tp,
2035                               NIC_SRAM_FIRMWARE_MBOX,
2036                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2037         }
2038
2039         if (current_link_up != netif_carrier_ok(tp->dev)) {
2040                 if (current_link_up)
2041                         netif_carrier_on(tp->dev);
2042                 else
2043                         netif_carrier_off(tp->dev);
2044                 tg3_link_report(tp);
2045         }
2046
2047         return 0;
2048 }
2049
2050 struct tg3_fiber_aneginfo {
2051         int state;
2052 #define ANEG_STATE_UNKNOWN              0
2053 #define ANEG_STATE_AN_ENABLE            1
2054 #define ANEG_STATE_RESTART_INIT         2
2055 #define ANEG_STATE_RESTART              3
2056 #define ANEG_STATE_DISABLE_LINK_OK      4
2057 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2058 #define ANEG_STATE_ABILITY_DETECT       6
2059 #define ANEG_STATE_ACK_DETECT_INIT      7
2060 #define ANEG_STATE_ACK_DETECT           8
2061 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2062 #define ANEG_STATE_COMPLETE_ACK         10
2063 #define ANEG_STATE_IDLE_DETECT_INIT     11
2064 #define ANEG_STATE_IDLE_DETECT          12
2065 #define ANEG_STATE_LINK_OK              13
2066 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2067 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2068
2069         u32 flags;
2070 #define MR_AN_ENABLE            0x00000001
2071 #define MR_RESTART_AN           0x00000002
2072 #define MR_AN_COMPLETE          0x00000004
2073 #define MR_PAGE_RX              0x00000008
2074 #define MR_NP_LOADED            0x00000010
2075 #define MR_TOGGLE_TX            0x00000020
2076 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2077 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2078 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2079 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2080 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2081 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2082 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2083 #define MR_TOGGLE_RX            0x00002000
2084 #define MR_NP_RX                0x00004000
2085
2086 #define MR_LINK_OK              0x80000000
2087
2088         unsigned long link_time, cur_time;
2089
2090         u32 ability_match_cfg;
2091         int ability_match_count;
2092
2093         char ability_match, idle_match, ack_match;
2094
2095         u32 txconfig, rxconfig;
2096 #define ANEG_CFG_NP             0x00000080
2097 #define ANEG_CFG_ACK            0x00000040
2098 #define ANEG_CFG_RF2            0x00000020
2099 #define ANEG_CFG_RF1            0x00000010
2100 #define ANEG_CFG_PS2            0x00000001
2101 #define ANEG_CFG_PS1            0x00008000
2102 #define ANEG_CFG_HD             0x00004000
2103 #define ANEG_CFG_FD             0x00002000
2104 #define ANEG_CFG_INVAL          0x00001f06
2105
2106 };
2107 #define ANEG_OK         0
2108 #define ANEG_DONE       1
2109 #define ANEG_TIMER_ENAB 2
2110 #define ANEG_FAILED     -1
2111
2112 #define ANEG_STATE_SETTLE_TIME  10000
2113
2114 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2115                                    struct tg3_fiber_aneginfo *ap)
2116 {
2117         unsigned long delta;
2118         u32 rx_cfg_reg;
2119         int ret;
2120
2121         if (ap->state == ANEG_STATE_UNKNOWN) {
2122                 ap->rxconfig = 0;
2123                 ap->link_time = 0;
2124                 ap->cur_time = 0;
2125                 ap->ability_match_cfg = 0;
2126                 ap->ability_match_count = 0;
2127                 ap->ability_match = 0;
2128                 ap->idle_match = 0;
2129                 ap->ack_match = 0;
2130         }
2131         ap->cur_time++;
2132
2133         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2134                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2135
2136                 if (rx_cfg_reg != ap->ability_match_cfg) {
2137                         ap->ability_match_cfg = rx_cfg_reg;
2138                         ap->ability_match = 0;
2139                         ap->ability_match_count = 0;
2140                 } else {
2141                         if (++ap->ability_match_count > 1) {
2142                                 ap->ability_match = 1;
2143                                 ap->ability_match_cfg = rx_cfg_reg;
2144                         }
2145                 }
2146                 if (rx_cfg_reg & ANEG_CFG_ACK)
2147                         ap->ack_match = 1;
2148                 else
2149                         ap->ack_match = 0;
2150
2151                 ap->idle_match = 0;
2152         } else {
2153                 ap->idle_match = 1;
2154                 ap->ability_match_cfg = 0;
2155                 ap->ability_match_count = 0;
2156                 ap->ability_match = 0;
2157                 ap->ack_match = 0;
2158
2159                 rx_cfg_reg = 0;
2160         }
2161
2162         ap->rxconfig = rx_cfg_reg;
2163         ret = ANEG_OK;
2164
2165         switch(ap->state) {
2166         case ANEG_STATE_UNKNOWN:
2167                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2168                         ap->state = ANEG_STATE_AN_ENABLE;
2169
2170                 /* fallthru */
2171         case ANEG_STATE_AN_ENABLE:
2172                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2173                 if (ap->flags & MR_AN_ENABLE) {
2174                         ap->link_time = 0;
2175                         ap->cur_time = 0;
2176                         ap->ability_match_cfg = 0;
2177                         ap->ability_match_count = 0;
2178                         ap->ability_match = 0;
2179                         ap->idle_match = 0;
2180                         ap->ack_match = 0;
2181
2182                         ap->state = ANEG_STATE_RESTART_INIT;
2183                 } else {
2184                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2185                 }
2186                 break;
2187
2188         case ANEG_STATE_RESTART_INIT:
2189                 ap->link_time = ap->cur_time;
2190                 ap->flags &= ~(MR_NP_LOADED);
2191                 ap->txconfig = 0;
2192                 tw32(MAC_TX_AUTO_NEG, 0);
2193                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2194                 tw32_f(MAC_MODE, tp->mac_mode);
2195                 udelay(40);
2196
2197                 ret = ANEG_TIMER_ENAB;
2198                 ap->state = ANEG_STATE_RESTART;
2199
2200                 /* fallthru */
2201         case ANEG_STATE_RESTART:
2202                 delta = ap->cur_time - ap->link_time;
2203                 if (delta > ANEG_STATE_SETTLE_TIME) {
2204                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2205                 } else {
2206                         ret = ANEG_TIMER_ENAB;
2207                 }
2208                 break;
2209
2210         case ANEG_STATE_DISABLE_LINK_OK:
2211                 ret = ANEG_DONE;
2212                 break;
2213
2214         case ANEG_STATE_ABILITY_DETECT_INIT:
2215                 ap->flags &= ~(MR_TOGGLE_TX);
2216                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2217                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2218                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2219                 tw32_f(MAC_MODE, tp->mac_mode);
2220                 udelay(40);
2221
2222                 ap->state = ANEG_STATE_ABILITY_DETECT;
2223                 break;
2224
2225         case ANEG_STATE_ABILITY_DETECT:
2226                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2227                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2228                 }
2229                 break;
2230
2231         case ANEG_STATE_ACK_DETECT_INIT:
2232                 ap->txconfig |= ANEG_CFG_ACK;
2233                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2234                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2235                 tw32_f(MAC_MODE, tp->mac_mode);
2236                 udelay(40);
2237
2238                 ap->state = ANEG_STATE_ACK_DETECT;
2239
2240                 /* fallthru */
2241         case ANEG_STATE_ACK_DETECT:
2242                 if (ap->ack_match != 0) {
2243                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2244                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2245                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2246                         } else {
2247                                 ap->state = ANEG_STATE_AN_ENABLE;
2248                         }
2249                 } else if (ap->ability_match != 0 &&
2250                            ap->rxconfig == 0) {
2251                         ap->state = ANEG_STATE_AN_ENABLE;
2252                 }
2253                 break;
2254
2255         case ANEG_STATE_COMPLETE_ACK_INIT:
2256                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2257                         ret = ANEG_FAILED;
2258                         break;
2259                 }
2260                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2261                                MR_LP_ADV_HALF_DUPLEX |
2262                                MR_LP_ADV_SYM_PAUSE |
2263                                MR_LP_ADV_ASYM_PAUSE |
2264                                MR_LP_ADV_REMOTE_FAULT1 |
2265                                MR_LP_ADV_REMOTE_FAULT2 |
2266                                MR_LP_ADV_NEXT_PAGE |
2267                                MR_TOGGLE_RX |
2268                                MR_NP_RX);
2269                 if (ap->rxconfig & ANEG_CFG_FD)
2270                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2271                 if (ap->rxconfig & ANEG_CFG_HD)
2272                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2273                 if (ap->rxconfig & ANEG_CFG_PS1)
2274                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2275                 if (ap->rxconfig & ANEG_CFG_PS2)
2276                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2277                 if (ap->rxconfig & ANEG_CFG_RF1)
2278                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2279                 if (ap->rxconfig & ANEG_CFG_RF2)
2280                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2281                 if (ap->rxconfig & ANEG_CFG_NP)
2282                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2283
2284                 ap->link_time = ap->cur_time;
2285
2286                 ap->flags ^= (MR_TOGGLE_TX);
2287                 if (ap->rxconfig & 0x0008)
2288                         ap->flags |= MR_TOGGLE_RX;
2289                 if (ap->rxconfig & ANEG_CFG_NP)
2290                         ap->flags |= MR_NP_RX;
2291                 ap->flags |= MR_PAGE_RX;
2292
2293                 ap->state = ANEG_STATE_COMPLETE_ACK;
2294                 ret = ANEG_TIMER_ENAB;
2295                 break;
2296
2297         case ANEG_STATE_COMPLETE_ACK:
2298                 if (ap->ability_match != 0 &&
2299                     ap->rxconfig == 0) {
2300                         ap->state = ANEG_STATE_AN_ENABLE;
2301                         break;
2302                 }
2303                 delta = ap->cur_time - ap->link_time;
2304                 if (delta > ANEG_STATE_SETTLE_TIME) {
2305                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2306                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2307                         } else {
2308                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2309                                     !(ap->flags & MR_NP_RX)) {
2310                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2311                                 } else {
2312                                         ret = ANEG_FAILED;
2313                                 }
2314                         }
2315                 }
2316                 break;
2317
2318         case ANEG_STATE_IDLE_DETECT_INIT:
2319                 ap->link_time = ap->cur_time;
2320                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2321                 tw32_f(MAC_MODE, tp->mac_mode);
2322                 udelay(40);
2323
2324                 ap->state = ANEG_STATE_IDLE_DETECT;
2325                 ret = ANEG_TIMER_ENAB;
2326                 break;
2327
2328         case ANEG_STATE_IDLE_DETECT:
2329                 if (ap->ability_match != 0 &&
2330                     ap->rxconfig == 0) {
2331                         ap->state = ANEG_STATE_AN_ENABLE;
2332                         break;
2333                 }
2334                 delta = ap->cur_time - ap->link_time;
2335                 if (delta > ANEG_STATE_SETTLE_TIME) {
2336                         /* XXX another gem from the Broadcom driver :( */
2337                         ap->state = ANEG_STATE_LINK_OK;
2338                 }
2339                 break;
2340
2341         case ANEG_STATE_LINK_OK:
2342                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2343                 ret = ANEG_DONE;
2344                 break;
2345
2346         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2347                 /* ??? unimplemented */
2348                 break;
2349
2350         case ANEG_STATE_NEXT_PAGE_WAIT:
2351                 /* ??? unimplemented */
2352                 break;
2353
2354         default:
2355                 ret = ANEG_FAILED;
2356                 break;
2357         };
2358
2359         return ret;
2360 }
2361
2362 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2363 {
2364         int res = 0;
2365         struct tg3_fiber_aneginfo aninfo;
2366         int status = ANEG_FAILED;
2367         unsigned int tick;
2368         u32 tmp;
2369
2370         tw32_f(MAC_TX_AUTO_NEG, 0);
2371
2372         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2373         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2374         udelay(40);
2375
2376         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2377         udelay(40);
2378
2379         memset(&aninfo, 0, sizeof(aninfo));
2380         aninfo.flags |= MR_AN_ENABLE;
2381         aninfo.state = ANEG_STATE_UNKNOWN;
2382         aninfo.cur_time = 0;
2383         tick = 0;
2384         while (++tick < 195000) {
2385                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2386                 if (status == ANEG_DONE || status == ANEG_FAILED)
2387                         break;
2388
2389                 udelay(1);
2390         }
2391
2392         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2393         tw32_f(MAC_MODE, tp->mac_mode);
2394         udelay(40);
2395
2396         *flags = aninfo.flags;
2397
2398         if (status == ANEG_DONE &&
2399             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2400                              MR_LP_ADV_FULL_DUPLEX)))
2401                 res = 1;
2402
2403         return res;
2404 }
2405
2406 static void tg3_init_bcm8002(struct tg3 *tp)
2407 {
2408         u32 mac_status = tr32(MAC_STATUS);
2409         int i;
2410
2411         /* Reset when initting first time or we have a link. */
2412         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2413             !(mac_status & MAC_STATUS_PCS_SYNCED))
2414                 return;
2415
2416         /* Set PLL lock range. */
2417         tg3_writephy(tp, 0x16, 0x8007);
2418
2419         /* SW reset */
2420         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2421
2422         /* Wait for reset to complete. */
2423         /* XXX schedule_timeout() ... */
2424         for (i = 0; i < 500; i++)
2425                 udelay(10);
2426
2427         /* Config mode; select PMA/Ch 1 regs. */
2428         tg3_writephy(tp, 0x10, 0x8411);
2429
2430         /* Enable auto-lock and comdet, select txclk for tx. */
2431         tg3_writephy(tp, 0x11, 0x0a10);
2432
2433         tg3_writephy(tp, 0x18, 0x00a0);
2434         tg3_writephy(tp, 0x16, 0x41ff);
2435
2436         /* Assert and deassert POR. */
2437         tg3_writephy(tp, 0x13, 0x0400);
2438         udelay(40);
2439         tg3_writephy(tp, 0x13, 0x0000);
2440
2441         tg3_writephy(tp, 0x11, 0x0a50);
2442         udelay(40);
2443         tg3_writephy(tp, 0x11, 0x0a10);
2444
2445         /* Wait for signal to stabilize */
2446         /* XXX schedule_timeout() ... */
2447         for (i = 0; i < 15000; i++)
2448                 udelay(10);
2449
2450         /* Deselect the channel register so we can read the PHYID
2451          * later.
2452          */
2453         tg3_writephy(tp, 0x10, 0x8011);
2454 }
2455
2456 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2457 {
2458         u32 sg_dig_ctrl, sg_dig_status;
2459         u32 serdes_cfg, expected_sg_dig_ctrl;
2460         int workaround, port_a;
2461         int current_link_up;
2462
2463         serdes_cfg = 0;
2464         expected_sg_dig_ctrl = 0;
2465         workaround = 0;
2466         port_a = 1;
2467         current_link_up = 0;
2468
2469         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2470             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2471                 workaround = 1;
2472                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2473                         port_a = 0;
2474
2475                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2476                 /* preserve bits 20-23 for voltage regulator */
2477                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2478         }
2479
2480         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2481
2482         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2483                 if (sg_dig_ctrl & (1 << 31)) {
2484                         if (workaround) {
2485                                 u32 val = serdes_cfg;
2486
2487                                 if (port_a)
2488                                         val |= 0xc010000;
2489                                 else
2490                                         val |= 0x4010000;
2491                                 tw32_f(MAC_SERDES_CFG, val);
2492                         }
2493                         tw32_f(SG_DIG_CTRL, 0x01388400);
2494                 }
2495                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2496                         tg3_setup_flow_control(tp, 0, 0);
2497                         current_link_up = 1;
2498                 }
2499                 goto out;
2500         }
2501
2502         /* Want auto-negotiation.  */
2503         expected_sg_dig_ctrl = 0x81388400;
2504
2505         /* Pause capability */
2506         expected_sg_dig_ctrl |= (1 << 11);
2507
2508         /* Asymettric pause */
2509         expected_sg_dig_ctrl |= (1 << 12);
2510
2511         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2512                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2513                     tp->serdes_counter &&
2514                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2515                                     MAC_STATUS_RCVD_CFG)) ==
2516                      MAC_STATUS_PCS_SYNCED)) {
2517                         tp->serdes_counter--;
2518                         current_link_up = 1;
2519                         goto out;
2520                 }
2521 restart_autoneg:
2522                 if (workaround)
2523                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2524                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2525                 udelay(5);
2526                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2527
2528                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2529                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2530         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2531                                  MAC_STATUS_SIGNAL_DET)) {
2532                 sg_dig_status = tr32(SG_DIG_STATUS);
2533                 mac_status = tr32(MAC_STATUS);
2534
2535                 if ((sg_dig_status & (1 << 1)) &&
2536                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2537                         u32 local_adv, remote_adv;
2538
2539                         local_adv = ADVERTISE_PAUSE_CAP;
2540                         remote_adv = 0;
2541                         if (sg_dig_status & (1 << 19))
2542                                 remote_adv |= LPA_PAUSE_CAP;
2543                         if (sg_dig_status & (1 << 20))
2544                                 remote_adv |= LPA_PAUSE_ASYM;
2545
2546                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2547                         current_link_up = 1;
2548                         tp->serdes_counter = 0;
2549                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2550                 } else if (!(sg_dig_status & (1 << 1))) {
2551                         if (tp->serdes_counter)
2552                                 tp->serdes_counter--;
2553                         else {
2554                                 if (workaround) {
2555                                         u32 val = serdes_cfg;
2556
2557                                         if (port_a)
2558                                                 val |= 0xc010000;
2559                                         else
2560                                                 val |= 0x4010000;
2561
2562                                         tw32_f(MAC_SERDES_CFG, val);
2563                                 }
2564
2565                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2566                                 udelay(40);
2567
2568                                 /* Link parallel detection - link is up */
2569                                 /* only if we have PCS_SYNC and not */
2570                                 /* receiving config code words */
2571                                 mac_status = tr32(MAC_STATUS);
2572                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2573                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2574                                         tg3_setup_flow_control(tp, 0, 0);
2575                                         current_link_up = 1;
2576                                         tp->tg3_flags2 |=
2577                                                 TG3_FLG2_PARALLEL_DETECT;
2578                                         tp->serdes_counter =
2579                                                 SERDES_PARALLEL_DET_TIMEOUT;
2580                                 } else
2581                                         goto restart_autoneg;
2582                         }
2583                 }
2584         } else {
2585                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2586                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2587         }
2588
2589 out:
2590         return current_link_up;
2591 }
2592
2593 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2594 {
2595         int current_link_up = 0;
2596
2597         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2598                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2599                 goto out;
2600         }
2601
2602         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2603                 u32 flags;
2604                 int i;
2605
2606                 if (fiber_autoneg(tp, &flags)) {
2607                         u32 local_adv, remote_adv;
2608
2609                         local_adv = ADVERTISE_PAUSE_CAP;
2610                         remote_adv = 0;
2611                         if (flags & MR_LP_ADV_SYM_PAUSE)
2612                                 remote_adv |= LPA_PAUSE_CAP;
2613                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2614                                 remote_adv |= LPA_PAUSE_ASYM;
2615
2616                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2617
2618                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2619                         current_link_up = 1;
2620                 }
2621                 for (i = 0; i < 30; i++) {
2622                         udelay(20);
2623                         tw32_f(MAC_STATUS,
2624                                (MAC_STATUS_SYNC_CHANGED |
2625                                 MAC_STATUS_CFG_CHANGED));
2626                         udelay(40);
2627                         if ((tr32(MAC_STATUS) &
2628                              (MAC_STATUS_SYNC_CHANGED |
2629                               MAC_STATUS_CFG_CHANGED)) == 0)
2630                                 break;
2631                 }
2632
2633                 mac_status = tr32(MAC_STATUS);
2634                 if (current_link_up == 0 &&
2635                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2636                     !(mac_status & MAC_STATUS_RCVD_CFG))
2637                         current_link_up = 1;
2638         } else {
2639                 /* Forcing 1000FD link up. */
2640                 current_link_up = 1;
2641                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2642
2643                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2644                 udelay(40);
2645         }
2646
2647 out:
2648         return current_link_up;
2649 }
2650
2651 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2652 {
2653         u32 orig_pause_cfg;
2654         u16 orig_active_speed;
2655         u8 orig_active_duplex;
2656         u32 mac_status;
2657         int current_link_up;
2658         int i;
2659
2660         orig_pause_cfg =
2661                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2662                                   TG3_FLAG_TX_PAUSE));
2663         orig_active_speed = tp->link_config.active_speed;
2664         orig_active_duplex = tp->link_config.active_duplex;
2665
2666         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2667             netif_carrier_ok(tp->dev) &&
2668             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2669                 mac_status = tr32(MAC_STATUS);
2670                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2671                                MAC_STATUS_SIGNAL_DET |
2672                                MAC_STATUS_CFG_CHANGED |
2673                                MAC_STATUS_RCVD_CFG);
2674                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2675                                    MAC_STATUS_SIGNAL_DET)) {
2676                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2677                                             MAC_STATUS_CFG_CHANGED));
2678                         return 0;
2679                 }
2680         }
2681
2682         tw32_f(MAC_TX_AUTO_NEG, 0);
2683
2684         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2685         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2686         tw32_f(MAC_MODE, tp->mac_mode);
2687         udelay(40);
2688
2689         if (tp->phy_id == PHY_ID_BCM8002)
2690                 tg3_init_bcm8002(tp);
2691
2692         /* Enable link change event even when serdes polling.  */
2693         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2694         udelay(40);
2695
2696         current_link_up = 0;
2697         mac_status = tr32(MAC_STATUS);
2698
2699         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2700                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2701         else
2702                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2703
2704         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2705         tw32_f(MAC_MODE, tp->mac_mode);
2706         udelay(40);
2707
2708         tp->hw_status->status =
2709                 (SD_STATUS_UPDATED |
2710                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2711
2712         for (i = 0; i < 100; i++) {
2713                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2714                                     MAC_STATUS_CFG_CHANGED));
2715                 udelay(5);
2716                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2717                                          MAC_STATUS_CFG_CHANGED |
2718                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2719                         break;
2720         }
2721
2722         mac_status = tr32(MAC_STATUS);
2723         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2724                 current_link_up = 0;
2725                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2726                     tp->serdes_counter == 0) {
2727                         tw32_f(MAC_MODE, (tp->mac_mode |
2728                                           MAC_MODE_SEND_CONFIGS));
2729                         udelay(1);
2730                         tw32_f(MAC_MODE, tp->mac_mode);
2731                 }
2732         }
2733
2734         if (current_link_up == 1) {
2735                 tp->link_config.active_speed = SPEED_1000;
2736                 tp->link_config.active_duplex = DUPLEX_FULL;
2737                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2738                                     LED_CTRL_LNKLED_OVERRIDE |
2739                                     LED_CTRL_1000MBPS_ON));
2740         } else {
2741                 tp->link_config.active_speed = SPEED_INVALID;
2742                 tp->link_config.active_duplex = DUPLEX_INVALID;
2743                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2744                                     LED_CTRL_LNKLED_OVERRIDE |
2745                                     LED_CTRL_TRAFFIC_OVERRIDE));
2746         }
2747
2748         if (current_link_up != netif_carrier_ok(tp->dev)) {
2749                 if (current_link_up)
2750                         netif_carrier_on(tp->dev);
2751                 else
2752                         netif_carrier_off(tp->dev);
2753                 tg3_link_report(tp);
2754         } else {
2755                 u32 now_pause_cfg =
2756                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2757                                          TG3_FLAG_TX_PAUSE);
2758                 if (orig_pause_cfg != now_pause_cfg ||
2759                     orig_active_speed != tp->link_config.active_speed ||
2760                     orig_active_duplex != tp->link_config.active_duplex)
2761                         tg3_link_report(tp);
2762         }
2763
2764         return 0;
2765 }
2766
2767 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2768 {
2769         int current_link_up, err = 0;
2770         u32 bmsr, bmcr;
2771         u16 current_speed;
2772         u8 current_duplex;
2773
2774         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2775         tw32_f(MAC_MODE, tp->mac_mode);
2776         udelay(40);
2777
2778         tw32(MAC_EVENT, 0);
2779
2780         tw32_f(MAC_STATUS,
2781              (MAC_STATUS_SYNC_CHANGED |
2782               MAC_STATUS_CFG_CHANGED |
2783               MAC_STATUS_MI_COMPLETION |
2784               MAC_STATUS_LNKSTATE_CHANGED));
2785         udelay(40);
2786
2787         if (force_reset)
2788                 tg3_phy_reset(tp);
2789
2790         current_link_up = 0;
2791         current_speed = SPEED_INVALID;
2792         current_duplex = DUPLEX_INVALID;
2793
2794         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2795         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2796         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2797                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2798                         bmsr |= BMSR_LSTATUS;
2799                 else
2800                         bmsr &= ~BMSR_LSTATUS;
2801         }
2802
2803         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2804
2805         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2806             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2807                 /* do nothing, just check for link up at the end */
2808         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2809                 u32 adv, new_adv;
2810
2811                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2812                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2813                                   ADVERTISE_1000XPAUSE |
2814                                   ADVERTISE_1000XPSE_ASYM |
2815                                   ADVERTISE_SLCT);
2816
2817                 /* Always advertise symmetric PAUSE just like copper */
2818                 new_adv |= ADVERTISE_1000XPAUSE;
2819
2820                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2821                         new_adv |= ADVERTISE_1000XHALF;
2822                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2823                         new_adv |= ADVERTISE_1000XFULL;
2824
2825                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2826                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2827                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2828                         tg3_writephy(tp, MII_BMCR, bmcr);
2829
2830                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2831                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2832                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2833
2834                         return err;
2835                 }
2836         } else {
2837                 u32 new_bmcr;
2838
2839                 bmcr &= ~BMCR_SPEED1000;
2840                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2841
2842                 if (tp->link_config.duplex == DUPLEX_FULL)
2843                         new_bmcr |= BMCR_FULLDPLX;
2844
2845                 if (new_bmcr != bmcr) {
2846                         /* BMCR_SPEED1000 is a reserved bit that needs
2847                          * to be set on write.
2848                          */
2849                         new_bmcr |= BMCR_SPEED1000;
2850
2851                         /* Force a linkdown */
2852                         if (netif_carrier_ok(tp->dev)) {
2853                                 u32 adv;
2854
2855                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2856                                 adv &= ~(ADVERTISE_1000XFULL |
2857                                          ADVERTISE_1000XHALF |
2858                                          ADVERTISE_SLCT);
2859                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2860                                 tg3_writephy(tp, MII_BMCR, bmcr |
2861                                                            BMCR_ANRESTART |
2862                                                            BMCR_ANENABLE);
2863                                 udelay(10);
2864                                 netif_carrier_off(tp->dev);
2865                         }
2866                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2867                         bmcr = new_bmcr;
2868                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2869                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2870                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2871                             ASIC_REV_5714) {
2872                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2873                                         bmsr |= BMSR_LSTATUS;
2874                                 else
2875                                         bmsr &= ~BMSR_LSTATUS;
2876                         }
2877                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2878                 }
2879         }
2880
2881         if (bmsr & BMSR_LSTATUS) {
2882                 current_speed = SPEED_1000;
2883                 current_link_up = 1;
2884                 if (bmcr & BMCR_FULLDPLX)
2885                         current_duplex = DUPLEX_FULL;
2886                 else
2887                         current_duplex = DUPLEX_HALF;
2888
2889                 if (bmcr & BMCR_ANENABLE) {
2890                         u32 local_adv, remote_adv, common;
2891
2892                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2893                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2894                         common = local_adv & remote_adv;
2895                         if (common & (ADVERTISE_1000XHALF |
2896                                       ADVERTISE_1000XFULL)) {
2897                                 if (common & ADVERTISE_1000XFULL)
2898                                         current_duplex = DUPLEX_FULL;
2899                                 else
2900                                         current_duplex = DUPLEX_HALF;
2901
2902                                 tg3_setup_flow_control(tp, local_adv,
2903                                                        remote_adv);
2904                         }
2905                         else
2906                                 current_link_up = 0;
2907                 }
2908         }
2909
2910         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2911         if (tp->link_config.active_duplex == DUPLEX_HALF)
2912                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2913
2914         tw32_f(MAC_MODE, tp->mac_mode);
2915         udelay(40);
2916
2917         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2918
2919         tp->link_config.active_speed = current_speed;
2920         tp->link_config.active_duplex = current_duplex;
2921
2922         if (current_link_up != netif_carrier_ok(tp->dev)) {
2923                 if (current_link_up)
2924                         netif_carrier_on(tp->dev);
2925                 else {
2926                         netif_carrier_off(tp->dev);
2927                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2928                 }
2929                 tg3_link_report(tp);
2930         }
2931         return err;
2932 }
2933
2934 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2935 {
2936         if (tp->serdes_counter) {
2937                 /* Give autoneg time to complete. */
2938                 tp->serdes_counter--;
2939                 return;
2940         }
2941         if (!netif_carrier_ok(tp->dev) &&
2942             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2943                 u32 bmcr;
2944
2945                 tg3_readphy(tp, MII_BMCR, &bmcr);
2946                 if (bmcr & BMCR_ANENABLE) {
2947                         u32 phy1, phy2;
2948
2949                         /* Select shadow register 0x1f */
2950                         tg3_writephy(tp, 0x1c, 0x7c00);
2951                         tg3_readphy(tp, 0x1c, &phy1);
2952
2953                         /* Select expansion interrupt status register */
2954                         tg3_writephy(tp, 0x17, 0x0f01);
2955                         tg3_readphy(tp, 0x15, &phy2);
2956                         tg3_readphy(tp, 0x15, &phy2);
2957
2958                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2959                                 /* We have signal detect and not receiving
2960                                  * config code words, link is up by parallel
2961                                  * detection.
2962                                  */
2963
2964                                 bmcr &= ~BMCR_ANENABLE;
2965                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2966                                 tg3_writephy(tp, MII_BMCR, bmcr);
2967                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2968                         }
2969                 }
2970         }
2971         else if (netif_carrier_ok(tp->dev) &&
2972                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2973                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2974                 u32 phy2;
2975
2976                 /* Select expansion interrupt status register */
2977                 tg3_writephy(tp, 0x17, 0x0f01);
2978                 tg3_readphy(tp, 0x15, &phy2);
2979                 if (phy2 & 0x20) {
2980                         u32 bmcr;
2981
2982                         /* Config code words received, turn on autoneg. */
2983                         tg3_readphy(tp, MII_BMCR, &bmcr);
2984                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2985
2986                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2987
2988                 }
2989         }
2990 }
2991
2992 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2993 {
2994         int err;
2995
2996         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2997                 err = tg3_setup_fiber_phy(tp, force_reset);
2998         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2999                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3000         } else {
3001                 err = tg3_setup_copper_phy(tp, force_reset);
3002         }
3003
3004         if (tp->link_config.active_speed == SPEED_1000 &&
3005             tp->link_config.active_duplex == DUPLEX_HALF)
3006                 tw32(MAC_TX_LENGTHS,
3007                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3008                       (6 << TX_LENGTHS_IPG_SHIFT) |
3009                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3010         else
3011                 tw32(MAC_TX_LENGTHS,
3012                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3013                       (6 << TX_LENGTHS_IPG_SHIFT) |
3014                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3015
3016         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3017                 if (netif_carrier_ok(tp->dev)) {
3018                         tw32(HOSTCC_STAT_COAL_TICKS,
3019                              tp->coal.stats_block_coalesce_usecs);
3020                 } else {
3021                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3022                 }
3023         }
3024
3025         return err;
3026 }
3027
3028 /* This is called whenever we suspect that the system chipset is re-
3029  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3030  * is bogus tx completions. We try to recover by setting the
3031  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3032  * in the workqueue.
3033  */
3034 static void tg3_tx_recover(struct tg3 *tp)
3035 {
3036         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3037                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3038
3039         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3040                "mapped I/O cycles to the network device, attempting to "
3041                "recover. Please report the problem to the driver maintainer "
3042                "and include system chipset information.\n", tp->dev->name);
3043
3044         spin_lock(&tp->lock);
3045         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3046         spin_unlock(&tp->lock);
3047 }
3048
3049 static inline u32 tg3_tx_avail(struct tg3 *tp)
3050 {
3051         smp_mb();
3052         return (tp->tx_pending -
3053                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3054 }
3055
3056 /* Tigon3 never reports partial packet sends.  So we do not
3057  * need special logic to handle SKBs that have not had all
3058  * of their frags sent yet, like SunGEM does.
3059  */
3060 static void tg3_tx(struct tg3 *tp)
3061 {
3062         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3063         u32 sw_idx = tp->tx_cons;
3064
3065         while (sw_idx != hw_idx) {
3066                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3067                 struct sk_buff *skb = ri->skb;
3068                 int i, tx_bug = 0;
3069
3070                 if (unlikely(skb == NULL)) {
3071                         tg3_tx_recover(tp);
3072                         return;
3073                 }
3074
3075                 pci_unmap_single(tp->pdev,
3076                                  pci_unmap_addr(ri, mapping),
3077                                  skb_headlen(skb),
3078                                  PCI_DMA_TODEVICE);
3079
3080                 ri->skb = NULL;
3081
3082                 sw_idx = NEXT_TX(sw_idx);
3083
3084                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3085                         ri = &tp->tx_buffers[sw_idx];
3086                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3087                                 tx_bug = 1;
3088
3089                         pci_unmap_page(tp->pdev,
3090                                        pci_unmap_addr(ri, mapping),
3091                                        skb_shinfo(skb)->frags[i].size,
3092                                        PCI_DMA_TODEVICE);
3093
3094                         sw_idx = NEXT_TX(sw_idx);
3095                 }
3096
3097                 dev_kfree_skb(skb);
3098
3099                 if (unlikely(tx_bug)) {
3100                         tg3_tx_recover(tp);
3101                         return;
3102                 }
3103         }
3104
3105         tp->tx_cons = sw_idx;
3106
3107         /* Need to make the tx_cons update visible to tg3_start_xmit()
3108          * before checking for netif_queue_stopped().  Without the
3109          * memory barrier, there is a small possibility that tg3_start_xmit()
3110          * will miss it and cause the queue to be stopped forever.
3111          */
3112         smp_mb();
3113
3114         if (unlikely(netif_queue_stopped(tp->dev) &&
3115                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3116                 netif_tx_lock(tp->dev);
3117                 if (netif_queue_stopped(tp->dev) &&
3118                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3119                         netif_wake_queue(tp->dev);
3120                 netif_tx_unlock(tp->dev);
3121         }
3122 }
3123
3124 /* Returns size of skb allocated or < 0 on error.
3125  *
3126  * We only need to fill in the address because the other members
3127  * of the RX descriptor are invariant, see tg3_init_rings.
3128  *
3129  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3130  * posting buffers we only dirty the first cache line of the RX
3131  * descriptor (containing the address).  Whereas for the RX status
3132  * buffers the cpu only reads the last cacheline of the RX descriptor
3133  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3134  */
3135 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3136                             int src_idx, u32 dest_idx_unmasked)
3137 {
3138         struct tg3_rx_buffer_desc *desc;
3139         struct ring_info *map, *src_map;
3140         struct sk_buff *skb;
3141         dma_addr_t mapping;
3142         int skb_size, dest_idx;
3143
3144         src_map = NULL;
3145         switch (opaque_key) {
3146         case RXD_OPAQUE_RING_STD:
3147                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3148                 desc = &tp->rx_std[dest_idx];
3149                 map = &tp->rx_std_buffers[dest_idx];
3150                 if (src_idx >= 0)
3151                         src_map = &tp->rx_std_buffers[src_idx];
3152                 skb_size = tp->rx_pkt_buf_sz;
3153                 break;
3154
3155         case RXD_OPAQUE_RING_JUMBO:
3156                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3157                 desc = &tp->rx_jumbo[dest_idx];
3158                 map = &tp->rx_jumbo_buffers[dest_idx];
3159                 if (src_idx >= 0)
3160                         src_map = &tp->rx_jumbo_buffers[src_idx];
3161                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3162                 break;
3163
3164         default:
3165                 return -EINVAL;
3166         };
3167
3168         /* Do not overwrite any of the map or rp information
3169          * until we are sure we can commit to a new buffer.
3170          *
3171          * Callers depend upon this behavior and assume that
3172          * we leave everything unchanged if we fail.
3173          */
3174         skb = netdev_alloc_skb(tp->dev, skb_size);
3175         if (skb == NULL)
3176                 return -ENOMEM;
3177
3178         skb_reserve(skb, tp->rx_offset);
3179
3180         mapping = pci_map_single(tp->pdev, skb->data,
3181                                  skb_size - tp->rx_offset,
3182                                  PCI_DMA_FROMDEVICE);
3183
3184         map->skb = skb;
3185         pci_unmap_addr_set(map, mapping, mapping);
3186
3187         if (src_map != NULL)
3188                 src_map->skb = NULL;
3189
3190         desc->addr_hi = ((u64)mapping >> 32);
3191         desc->addr_lo = ((u64)mapping & 0xffffffff);
3192
3193         return skb_size;
3194 }
3195
3196 /* We only need to move over in the address because the other
3197  * members of the RX descriptor are invariant.  See notes above
3198  * tg3_alloc_rx_skb for full details.
3199  */
3200 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3201                            int src_idx, u32 dest_idx_unmasked)
3202 {
3203         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3204         struct ring_info *src_map, *dest_map;
3205         int dest_idx;
3206
3207         switch (opaque_key) {
3208         case RXD_OPAQUE_RING_STD:
3209                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3210                 dest_desc = &tp->rx_std[dest_idx];
3211                 dest_map = &tp->rx_std_buffers[dest_idx];
3212                 src_desc = &tp->rx_std[src_idx];
3213                 src_map = &tp->rx_std_buffers[src_idx];
3214                 break;
3215
3216         case RXD_OPAQUE_RING_JUMBO:
3217                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3218                 dest_desc = &tp->rx_jumbo[dest_idx];
3219                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3220                 src_desc = &tp->rx_jumbo[src_idx];
3221                 src_map = &tp->rx_jumbo_buffers[src_idx];
3222                 break;
3223
3224         default:
3225                 return;
3226         };
3227
3228         dest_map->skb = src_map->skb;
3229         pci_unmap_addr_set(dest_map, mapping,
3230                            pci_unmap_addr(src_map, mapping));
3231         dest_desc->addr_hi = src_desc->addr_hi;
3232         dest_desc->addr_lo = src_desc->addr_lo;
3233
3234         src_map->skb = NULL;
3235 }
3236
3237 #if TG3_VLAN_TAG_USED
3238 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3239 {
3240         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3241 }
3242 #endif
3243
3244 /* The RX ring scheme is composed of multiple rings which post fresh
3245  * buffers to the chip, and one special ring the chip uses to report
3246  * status back to the host.
3247  *
3248  * The special ring reports the status of received packets to the
3249  * host.  The chip does not write into the original descriptor the
3250  * RX buffer was obtained from.  The chip simply takes the original
3251  * descriptor as provided by the host, updates the status and length
3252  * field, then writes this into the next status ring entry.
3253  *
3254  * Each ring the host uses to post buffers to the chip is described
3255  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3256  * it is first placed into the on-chip ram.  When the packet's length
3257  * is known, it walks down the TG3_BDINFO entries to select the ring.
3258  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3259  * which is within the range of the new packet's length is chosen.
3260  *
3261  * The "separate ring for rx status" scheme may sound queer, but it makes
3262  * sense from a cache coherency perspective.  If only the host writes
3263  * to the buffer post rings, and only the chip writes to the rx status
3264  * rings, then cache lines never move beyond shared-modified state.
3265  * If both the host and chip were to write into the same ring, cache line
3266  * eviction could occur since both entities want it in an exclusive state.
3267  */
3268 static int tg3_rx(struct tg3 *tp, int budget)
3269 {
3270         u32 work_mask, rx_std_posted = 0;
3271         u32 sw_idx = tp->rx_rcb_ptr;
3272         u16 hw_idx;
3273         int received;
3274
3275         hw_idx = tp->hw_status->idx[0].rx_producer;
3276         /*
3277          * We need to order the read of hw_idx and the read of
3278          * the opaque cookie.
3279          */
3280         rmb();
3281         work_mask = 0;
3282         received = 0;
3283         while (sw_idx != hw_idx && budget > 0) {
3284                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3285                 unsigned int len;
3286                 struct sk_buff *skb;
3287                 dma_addr_t dma_addr;
3288                 u32 opaque_key, desc_idx, *post_ptr;
3289
3290                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3291                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3292                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3293                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3294                                                   mapping);
3295                         skb = tp->rx_std_buffers[desc_idx].skb;
3296                         post_ptr = &tp->rx_std_ptr;
3297                         rx_std_posted++;
3298                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3299                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3300                                                   mapping);
3301                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3302                         post_ptr = &tp->rx_jumbo_ptr;
3303                 }
3304                 else {
3305                         goto next_pkt_nopost;
3306                 }
3307
3308                 work_mask |= opaque_key;
3309
3310                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3311                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3312                 drop_it:
3313                         tg3_recycle_rx(tp, opaque_key,
3314                                        desc_idx, *post_ptr);
3315                 drop_it_no_recycle:
3316                         /* Other statistics kept track of by card. */
3317                         tp->net_stats.rx_dropped++;
3318                         goto next_pkt;
3319                 }
3320
3321                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3322
3323                 if (len > RX_COPY_THRESHOLD
3324                         && tp->rx_offset == 2
3325                         /* rx_offset != 2 iff this is a 5701 card running
3326                          * in PCI-X mode [see tg3_get_invariants()] */
3327                 ) {
3328                         int skb_size;
3329
3330                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3331                                                     desc_idx, *post_ptr);
3332                         if (skb_size < 0)
3333                                 goto drop_it;
3334
3335                         pci_unmap_single(tp->pdev, dma_addr,
3336                                          skb_size - tp->rx_offset,
3337                                          PCI_DMA_FROMDEVICE);
3338
3339                         skb_put(skb, len);
3340                 } else {
3341                         struct sk_buff *copy_skb;
3342
3343                         tg3_recycle_rx(tp, opaque_key,
3344                                        desc_idx, *post_ptr);
3345
3346                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3347                         if (copy_skb == NULL)
3348                                 goto drop_it_no_recycle;
3349
3350                         skb_reserve(copy_skb, 2);
3351                         skb_put(copy_skb, len);
3352                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3353                         skb_copy_from_linear_data(skb, copy_skb->data, len);
3354                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3355
3356                         /* We'll reuse the original ring buffer. */
3357                         skb = copy_skb;
3358                 }
3359
3360                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3361                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3362                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3363                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3364                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3365                 else
3366                         skb->ip_summed = CHECKSUM_NONE;
3367
3368                 skb->protocol = eth_type_trans(skb, tp->dev);
3369 #if TG3_VLAN_TAG_USED
3370                 if (tp->vlgrp != NULL &&
3371                     desc->type_flags & RXD_FLAG_VLAN) {
3372                         tg3_vlan_rx(tp, skb,
3373                                     desc->err_vlan & RXD_VLAN_MASK);
3374                 } else
3375 #endif
3376                         netif_receive_skb(skb);
3377
3378                 tp->dev->last_rx = jiffies;
3379                 received++;
3380                 budget--;
3381
3382 next_pkt:
3383                 (*post_ptr)++;
3384
3385                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3386                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3387
3388                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3389                                      TG3_64BIT_REG_LOW, idx);
3390                         work_mask &= ~RXD_OPAQUE_RING_STD;
3391                         rx_std_posted = 0;
3392                 }
3393 next_pkt_nopost:
3394                 sw_idx++;
3395                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3396
3397                 /* Refresh hw_idx to see if there is new work */
3398                 if (sw_idx == hw_idx) {
3399                         hw_idx = tp->hw_status->idx[0].rx_producer;
3400                         rmb();
3401                 }
3402         }
3403
3404         /* ACK the status ring. */
3405         tp->rx_rcb_ptr = sw_idx;
3406         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3407
3408         /* Refill RX ring(s). */
3409         if (work_mask & RXD_OPAQUE_RING_STD) {
3410                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3411                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3412                              sw_idx);
3413         }
3414         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3415                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3416                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3417                              sw_idx);
3418         }
3419         mmiowb();
3420
3421         return received;
3422 }
3423
3424 static int tg3_poll(struct net_device *netdev, int *budget)
3425 {
3426         struct tg3 *tp = netdev_priv(netdev);
3427         struct tg3_hw_status *sblk = tp->hw_status;
3428         int done;
3429
3430         /* handle link change and other phy events */
3431         if (!(tp->tg3_flags &
3432               (TG3_FLAG_USE_LINKCHG_REG |
3433                TG3_FLAG_POLL_SERDES))) {
3434                 if (sblk->status & SD_STATUS_LINK_CHG) {
3435                         sblk->status = SD_STATUS_UPDATED |
3436                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3437                         spin_lock(&tp->lock);
3438                         tg3_setup_phy(tp, 0);
3439                         spin_unlock(&tp->lock);
3440                 }
3441         }
3442
3443         /* run TX completion thread */
3444         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3445                 tg3_tx(tp);
3446                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3447                         netif_rx_complete(netdev);
3448                         schedule_work(&tp->reset_task);
3449                         return 0;
3450                 }
3451         }
3452
3453         /* run RX thread, within the bounds set by NAPI.
3454          * All RX "locking" is done by ensuring outside
3455          * code synchronizes with dev->poll()
3456          */
3457         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3458                 int orig_budget = *budget;
3459                 int work_done;
3460
3461                 if (orig_budget > netdev->quota)
3462                         orig_budget = netdev->quota;
3463
3464                 work_done = tg3_rx(tp, orig_budget);
3465
3466                 *budget -= work_done;
3467                 netdev->quota -= work_done;
3468         }
3469
3470         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3471                 tp->last_tag = sblk->status_tag;
3472                 rmb();
3473         } else
3474                 sblk->status &= ~SD_STATUS_UPDATED;
3475
3476         /* if no more work, tell net stack and NIC we're done */
3477         done = !tg3_has_work(tp);
3478         if (done) {
3479                 netif_rx_complete(netdev);
3480                 tg3_restart_ints(tp);
3481         }
3482
3483         return (done ? 0 : 1);
3484 }
3485
3486 static void tg3_irq_quiesce(struct tg3 *tp)
3487 {
3488         BUG_ON(tp->irq_sync);
3489
3490         tp->irq_sync = 1;
3491         smp_mb();
3492
3493         synchronize_irq(tp->pdev->irq);
3494 }
3495
3496 static inline int tg3_irq_sync(struct tg3 *tp)
3497 {
3498         return tp->irq_sync;
3499 }
3500
3501 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3502  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3503  * with as well.  Most of the time, this is not necessary except when
3504  * shutting down the device.
3505  */
3506 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3507 {
3508         if (irq_sync)
3509                 tg3_irq_quiesce(tp);
3510         spin_lock_bh(&tp->lock);
3511 }
3512
3513 static inline void tg3_full_unlock(struct tg3 *tp)
3514 {
3515         spin_unlock_bh(&tp->lock);
3516 }
3517
3518 /* One-shot MSI handler - Chip automatically disables interrupt
3519  * after sending MSI so driver doesn't have to do it.
3520  */
3521 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3522 {
3523         struct net_device *dev = dev_id;
3524         struct tg3 *tp = netdev_priv(dev);
3525
3526         prefetch(tp->hw_status);
3527         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3528
3529         if (likely(!tg3_irq_sync(tp)))
3530                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3531
3532         return IRQ_HANDLED;
3533 }
3534
3535 /* MSI ISR - No need to check for interrupt sharing and no need to
3536  * flush status block and interrupt mailbox. PCI ordering rules
3537  * guarantee that MSI will arrive after the status block.
3538  */
3539 static irqreturn_t tg3_msi(int irq, void *dev_id)
3540 {
3541         struct net_device *dev = dev_id;
3542         struct tg3 *tp = netdev_priv(dev);
3543
3544         prefetch(tp->hw_status);
3545         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3546         /*
3547          * Writing any value to intr-mbox-0 clears PCI INTA# and
3548          * chip-internal interrupt pending events.
3549          * Writing non-zero to intr-mbox-0 additional tells the
3550          * NIC to stop sending us irqs, engaging "in-intr-handler"
3551          * event coalescing.
3552          */
3553         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3554         if (likely(!tg3_irq_sync(tp)))
3555                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3556
3557         return IRQ_RETVAL(1);
3558 }
3559
3560 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3561 {
3562         struct net_device *dev = dev_id;
3563         struct tg3 *tp = netdev_priv(dev);
3564         struct tg3_hw_status *sblk = tp->hw_status;
3565         unsigned int handled = 1;
3566
3567         /* In INTx mode, it is possible for the interrupt to arrive at
3568          * the CPU before the status block posted prior to the interrupt.
3569          * Reading the PCI State register will confirm whether the
3570          * interrupt is ours and will flush the status block.
3571          */
3572         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3573                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3574                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3575                         handled = 0;
3576                         goto out;
3577                 }
3578         }
3579
3580         /*
3581          * Writing any value to intr-mbox-0 clears PCI INTA# and
3582          * chip-internal interrupt pending events.
3583          * Writing non-zero to intr-mbox-0 additional tells the
3584          * NIC to stop sending us irqs, engaging "in-intr-handler"
3585          * event coalescing.
3586          */
3587         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3588         if (tg3_irq_sync(tp))
3589                 goto out;
3590         sblk->status &= ~SD_STATUS_UPDATED;
3591         if (likely(tg3_has_work(tp))) {
3592                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3593                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3594         } else {
3595                 /* No work, shared interrupt perhaps?  re-enable
3596                  * interrupts, and flush that PCI write
3597                  */
3598                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3599                                0x00000000);
3600         }
3601 out:
3602         return IRQ_RETVAL(handled);
3603 }
3604
3605 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3606 {
3607         struct net_device *dev = dev_id;
3608         struct tg3 *tp = netdev_priv(dev);
3609         struct tg3_hw_status *sblk = tp->hw_status;
3610         unsigned int handled = 1;
3611
3612         /* In INTx mode, it is possible for the interrupt to arrive at
3613          * the CPU before the status block posted prior to the interrupt.
3614          * Reading the PCI State register will confirm whether the
3615          * interrupt is ours and will flush the status block.
3616          */
3617         if (unlikely(sblk->status_tag == tp->last_tag)) {
3618                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3619                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3620                         handled = 0;
3621                         goto out;
3622                 }
3623         }
3624
3625         /*
3626          * writing any value to intr-mbox-0 clears PCI INTA# and
3627          * chip-internal interrupt pending events.
3628          * writing non-zero to intr-mbox-0 additional tells the
3629          * NIC to stop sending us irqs, engaging "in-intr-handler"
3630          * event coalescing.
3631          */
3632         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3633         if (tg3_irq_sync(tp))
3634                 goto out;
3635         if (netif_rx_schedule_prep(dev)) {
3636                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3637                 /* Update last_tag to mark that this status has been
3638                  * seen. Because interrupt may be shared, we may be
3639                  * racing with tg3_poll(), so only update last_tag
3640                  * if tg3_poll() is not scheduled.
3641                  */
3642                 tp->last_tag = sblk->status_tag;
3643                 __netif_rx_schedule(dev);
3644         }
3645 out:
3646         return IRQ_RETVAL(handled);
3647 }
3648
3649 /* ISR for interrupt test */
3650 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3651 {
3652         struct net_device *dev = dev_id;
3653         struct tg3 *tp = netdev_priv(dev);
3654         struct tg3_hw_status *sblk = tp->hw_status;
3655
3656         if ((sblk->status & SD_STATUS_UPDATED) ||
3657             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3658                 tg3_disable_ints(tp);
3659                 return IRQ_RETVAL(1);
3660         }
3661         return IRQ_RETVAL(0);
3662 }
3663
3664 static int tg3_init_hw(struct tg3 *, int);
3665 static int tg3_halt(struct tg3 *, int, int);
3666
3667 /* Restart hardware after configuration changes, self-test, etc.
3668  * Invoked with tp->lock held.
3669  */
3670 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3671 {
3672         int err;
3673
3674         err = tg3_init_hw(tp, reset_phy);
3675         if (err) {
3676                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3677                        "aborting.\n", tp->dev->name);
3678                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3679                 tg3_full_unlock(tp);
3680                 del_timer_sync(&tp->timer);
3681                 tp->irq_sync = 0;
3682                 netif_poll_enable(tp->dev);
3683                 dev_close(tp->dev);
3684                 tg3_full_lock(tp, 0);
3685         }
3686         return err;
3687 }
3688
3689 #ifdef CONFIG_NET_POLL_CONTROLLER
3690 static void tg3_poll_controller(struct net_device *dev)
3691 {
3692         struct tg3 *tp = netdev_priv(dev);
3693
3694         tg3_interrupt(tp->pdev->irq, dev);
3695 }
3696 #endif
3697
3698 static void tg3_reset_task(struct work_struct *work)
3699 {
3700         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3701         unsigned int restart_timer;
3702
3703         tg3_full_lock(tp, 0);
3704         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3705
3706         if (!netif_running(tp->dev)) {
3707                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3708                 tg3_full_unlock(tp);
3709                 return;
3710         }
3711
3712         tg3_full_unlock(tp);
3713
3714         tg3_netif_stop(tp);
3715
3716         tg3_full_lock(tp, 1);
3717
3718         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3719         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3720
3721         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3722                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3723                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3724                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3725                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3726         }
3727
3728         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3729         if (tg3_init_hw(tp, 1))
3730                 goto out;
3731
3732         tg3_netif_start(tp);
3733
3734         if (restart_timer)
3735                 mod_timer(&tp->timer, jiffies + 1);
3736
3737 out:
3738         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3739
3740         tg3_full_unlock(tp);
3741 }
3742
3743 static void tg3_dump_short_state(struct tg3 *tp)
3744 {
3745         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3746                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3747         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3748                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3749 }
3750
3751 static void tg3_tx_timeout(struct net_device *dev)
3752 {
3753         struct tg3 *tp = netdev_priv(dev);
3754
3755         if (netif_msg_tx_err(tp)) {
3756                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3757                        dev->name);
3758                 tg3_dump_short_state(tp);
3759         }
3760
3761         schedule_work(&tp->reset_task);
3762 }
3763
3764 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3765 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3766 {
3767         u32 base = (u32) mapping & 0xffffffff;
3768
3769         return ((base > 0xffffdcc0) &&
3770                 (base + len + 8 < base));
3771 }
3772
3773 /* Test for DMA addresses > 40-bit */
3774 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3775                                           int len)
3776 {
3777 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3778         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3779                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3780         return 0;
3781 #else
3782         return 0;
3783 #endif
3784 }
3785
3786 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3787
3788 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3789 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3790                                        u32 last_plus_one, u32 *start,
3791                                        u32 base_flags, u32 mss)
3792 {
3793         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3794         dma_addr_t new_addr = 0;
3795         u32 entry = *start;
3796         int i, ret = 0;
3797
3798         if (!new_skb) {
3799                 ret = -1;
3800         } else {
3801                 /* New SKB is guaranteed to be linear. */
3802                 entry = *start;
3803                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3804                                           PCI_DMA_TODEVICE);
3805                 /* Make sure new skb does not cross any 4G boundaries.
3806                  * Drop the packet if it does.
3807                  */
3808                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3809                         ret = -1;
3810                         dev_kfree_skb(new_skb);
3811                         new_skb = NULL;
3812                 } else {
3813                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3814                                     base_flags, 1 | (mss << 1));
3815                         *start = NEXT_TX(entry);
3816                 }
3817         }
3818
3819         /* Now clean up the sw ring entries. */
3820         i = 0;
3821         while (entry != last_plus_one) {
3822                 int len;
3823
3824                 if (i == 0)
3825                         len = skb_headlen(skb);
3826                 else
3827                         len = skb_shinfo(skb)->frags[i-1].size;
3828                 pci_unmap_single(tp->pdev,
3829                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3830                                  len, PCI_DMA_TODEVICE);
3831                 if (i == 0) {
3832                         tp->tx_buffers[entry].skb = new_skb;
3833                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3834                 } else {
3835                         tp->tx_buffers[entry].skb = NULL;
3836                 }
3837                 entry = NEXT_TX(entry);
3838                 i++;
3839         }
3840
3841         dev_kfree_skb(skb);
3842
3843         return ret;
3844 }
3845
3846 static void tg3_set_txd(struct tg3 *tp, int entry,
3847                         dma_addr_t mapping, int len, u32 flags,
3848                         u32 mss_and_is_end)
3849 {
3850         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3851         int is_end = (mss_and_is_end & 0x1);
3852         u32 mss = (mss_and_is_end >> 1);
3853         u32 vlan_tag = 0;
3854
3855         if (is_end)
3856                 flags |= TXD_FLAG_END;
3857         if (flags & TXD_FLAG_VLAN) {
3858                 vlan_tag = flags >> 16;
3859                 flags &= 0xffff;
3860         }
3861         vlan_tag |= (mss << TXD_MSS_SHIFT);
3862
3863         txd->addr_hi = ((u64) mapping >> 32);
3864         txd->addr_lo = ((u64) mapping & 0xffffffff);
3865         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3866         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3867 }
3868
3869 /* hard_start_xmit for devices that don't have any bugs and
3870  * support TG3_FLG2_HW_TSO_2 only.
3871  */
3872 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3873 {
3874         struct tg3 *tp = netdev_priv(dev);
3875         dma_addr_t mapping;
3876         u32 len, entry, base_flags, mss;
3877
3878         len = skb_headlen(skb);
3879
3880         /* We are running in BH disabled context with netif_tx_lock
3881          * and TX reclaim runs via tp->poll inside of a software
3882          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3883          * no IRQ context deadlocks to worry about either.  Rejoice!
3884          */
3885         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3886                 if (!netif_queue_stopped(dev)) {
3887                         netif_stop_queue(dev);
3888
3889                         /* This is a hard error, log it. */
3890                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3891                                "queue awake!\n", dev->name);
3892                 }
3893                 return NETDEV_TX_BUSY;
3894         }
3895
3896         entry = tp->tx_prod;
3897         base_flags = 0;
3898         mss = 0;
3899         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3900             (mss = skb_shinfo(skb)->gso_size) != 0) {
3901                 int tcp_opt_len, ip_tcp_len;
3902
3903                 if (skb_header_cloned(skb) &&
3904                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3905                         dev_kfree_skb(skb);
3906                         goto out_unlock;
3907                 }
3908
3909                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3910                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3911                 else {
3912                         struct iphdr *iph = ip_hdr(skb);
3913
3914                         tcp_opt_len = tcp_optlen(skb);
3915                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3916
3917                         iph->check = 0;
3918                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3919                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3920                 }
3921
3922                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3923                                TXD_FLAG_CPU_POST_DMA);
3924
3925                 tcp_hdr(skb)->check = 0;
3926
3927         }
3928         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3929                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3930 #if TG3_VLAN_TAG_USED
3931         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3932                 base_flags |= (TXD_FLAG_VLAN |
3933                                (vlan_tx_tag_get(skb) << 16));
3934 #endif
3935
3936         /* Queue skb data, a.k.a. the main skb fragment. */
3937         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3938
3939         tp->tx_buffers[entry].skb = skb;
3940         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3941
3942         tg3_set_txd(tp, entry, mapping, len, base_flags,
3943                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3944
3945         entry = NEXT_TX(entry);
3946
3947         /* Now loop through additional data fragments, and queue them. */
3948         if (skb_shinfo(skb)->nr_frags > 0) {
3949                 unsigned int i, last;
3950
3951                 last = skb_shinfo(skb)->nr_frags - 1;
3952                 for (i = 0; i <= last; i++) {
3953                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3954
3955                         len = frag->size;
3956                         mapping = pci_map_page(tp->pdev,
3957                                                frag->page,
3958                                                frag->page_offset,
3959                                                len, PCI_DMA_TODEVICE);
3960
3961                         tp->tx_buffers[entry].skb = NULL;
3962                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3963
3964                         tg3_set_txd(tp, entry, mapping, len,
3965                                     base_flags, (i == last) | (mss << 1));
3966
3967                         entry = NEXT_TX(entry);
3968                 }
3969         }
3970
3971         /* Packets are ready, update Tx producer idx local and on card. */
3972         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3973
3974         tp->tx_prod = entry;
3975         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3976                 netif_stop_queue(dev);
3977                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3978                         netif_wake_queue(tp->dev);
3979         }
3980
3981 out_unlock:
3982         mmiowb();
3983
3984         dev->trans_start = jiffies;
3985
3986         return NETDEV_TX_OK;
3987 }
3988
3989 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3990
3991 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3992  * TSO header is greater than 80 bytes.
3993  */
3994 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3995 {
3996         struct sk_buff *segs, *nskb;
3997
3998         /* Estimate the number of fragments in the worst case */
3999         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4000                 netif_stop_queue(tp->dev);
4001                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4002                         return NETDEV_TX_BUSY;
4003
4004                 netif_wake_queue(tp->dev);
4005         }
4006
4007         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4008         if (unlikely(IS_ERR(segs)))
4009                 goto tg3_tso_bug_end;
4010
4011         do {
4012                 nskb = segs;
4013                 segs = segs->next;
4014                 nskb->next = NULL;
4015                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4016         } while (segs);
4017
4018 tg3_tso_bug_end:
4019         dev_kfree_skb(skb);
4020
4021         return NETDEV_TX_OK;
4022 }
4023
4024 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4025  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4026  */
4027 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4028 {
4029         struct tg3 *tp = netdev_priv(dev);
4030         dma_addr_t mapping;
4031         u32 len, entry, base_flags, mss;
4032         int would_hit_hwbug;
4033
4034         len = skb_headlen(skb);
4035
4036         /* We are running in BH disabled context with netif_tx_lock
4037          * and TX reclaim runs via tp->poll inside of a software
4038          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4039          * no IRQ context deadlocks to worry about either.  Rejoice!
4040          */
4041         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4042                 if (!netif_queue_stopped(dev)) {
4043                         netif_stop_queue(dev);
4044
4045                         /* This is a hard error, log it. */
4046                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4047                                "queue awake!\n", dev->name);
4048                 }
4049                 return NETDEV_TX_BUSY;
4050         }
4051
4052         entry = tp->tx_prod;
4053         base_flags = 0;
4054         if (skb->ip_summed == CHECKSUM_PARTIAL)
4055                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4056         mss = 0;
4057         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4058             (mss = skb_shinfo(skb)->gso_size) != 0) {
4059                 struct iphdr *iph;
4060                 int tcp_opt_len, ip_tcp_len, hdr_len;
4061
4062                 if (skb_header_cloned(skb) &&
4063                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4064                         dev_kfree_skb(skb);
4065                         goto out_unlock;
4066                 }
4067
4068                 tcp_opt_len = tcp_optlen(skb);
4069                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4070
4071                 hdr_len = ip_tcp_len + tcp_opt_len;
4072                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4073                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4074                         return (tg3_tso_bug(tp, skb));
4075
4076                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4077                                TXD_FLAG_CPU_POST_DMA);
4078
4079                 iph = ip_hdr(skb);
4080                 iph->check = 0;
4081                 iph->tot_len = htons(mss + hdr_len);
4082                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4083                         tcp_hdr(skb)->check = 0;
4084                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4085                 } else
4086                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4087                                                                  iph->daddr, 0,
4088                                                                  IPPROTO_TCP,
4089                                                                  0);
4090
4091                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4092                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4093                         if (tcp_opt_len || iph->ihl > 5) {
4094                                 int tsflags;
4095
4096                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4097                                 mss |= (tsflags << 11);
4098                         }
4099                 } else {
4100                         if (tcp_opt_len || iph->ihl > 5) {
4101                                 int tsflags;
4102
4103                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4104                                 base_flags |= tsflags << 12;
4105                         }
4106                 }
4107         }
4108 #if TG3_VLAN_TAG_USED
4109         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4110                 base_flags |= (TXD_FLAG_VLAN |
4111                                (vlan_tx_tag_get(skb) << 16));
4112 #endif
4113
4114         /* Queue skb data, a.k.a. the main skb fragment. */
4115         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4116
4117         tp->tx_buffers[entry].skb = skb;
4118         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4119
4120         would_hit_hwbug = 0;
4121
4122         if (tg3_4g_overflow_test(mapping, len))
4123                 would_hit_hwbug = 1;
4124
4125         tg3_set_txd(tp, entry, mapping, len, base_flags,
4126                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4127
4128         entry = NEXT_TX(entry);
4129
4130         /* Now loop through additional data fragments, and queue them. */
4131         if (skb_shinfo(skb)->nr_frags > 0) {
4132                 unsigned int i, last;
4133
4134                 last = skb_shinfo(skb)->nr_frags - 1;
4135                 for (i = 0; i <= last; i++) {
4136                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4137
4138                         len = frag->size;
4139                         mapping = pci_map_page(tp->pdev,
4140                                                frag->page,
4141                                                frag->page_offset,
4142                                                len, PCI_DMA_TODEVICE);
4143
4144                         tp->tx_buffers[entry].skb = NULL;
4145                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4146
4147                         if (tg3_4g_overflow_test(mapping, len))
4148                                 would_hit_hwbug = 1;
4149
4150                         if (tg3_40bit_overflow_test(tp, mapping, len))
4151                                 would_hit_hwbug = 1;
4152
4153                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4154                                 tg3_set_txd(tp, entry, mapping, len,
4155                                             base_flags, (i == last)|(mss << 1));
4156                         else
4157                                 tg3_set_txd(tp, entry, mapping, len,
4158                                             base_flags, (i == last));
4159
4160                         entry = NEXT_TX(entry);
4161                 }
4162         }
4163
4164         if (would_hit_hwbug) {
4165                 u32 last_plus_one = entry;
4166                 u32 start;
4167
4168                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4169                 start &= (TG3_TX_RING_SIZE - 1);
4170
4171                 /* If the workaround fails due to memory/mapping
4172                  * failure, silently drop this packet.
4173                  */
4174                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4175                                                 &start, base_flags, mss))
4176                         goto out_unlock;
4177
4178                 entry = start;
4179         }
4180
4181         /* Packets are ready, update Tx producer idx local and on card. */
4182         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4183
4184         tp->tx_prod = entry;
4185         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4186                 netif_stop_queue(dev);
4187                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4188                         netif_wake_queue(tp->dev);
4189         }
4190
4191 out_unlock:
4192         mmiowb();
4193
4194         dev->trans_start = jiffies;
4195
4196         return NETDEV_TX_OK;
4197 }
4198
4199 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4200                                int new_mtu)
4201 {
4202         dev->mtu = new_mtu;
4203
4204         if (new_mtu > ETH_DATA_LEN) {
4205                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4206                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4207                         ethtool_op_set_tso(dev, 0);
4208                 }
4209                 else
4210                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4211         } else {
4212                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4213                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4214                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4215         }
4216 }
4217
4218 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4219 {
4220         struct tg3 *tp = netdev_priv(dev);
4221         int err;
4222
4223         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4224                 return -EINVAL;
4225
4226         if (!netif_running(dev)) {
4227                 /* We'll just catch it later when the
4228                  * device is up'd.
4229                  */
4230                 tg3_set_mtu(dev, tp, new_mtu);
4231                 return 0;
4232         }
4233
4234         tg3_netif_stop(tp);
4235
4236         tg3_full_lock(tp, 1);
4237
4238         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4239
4240         tg3_set_mtu(dev, tp, new_mtu);
4241
4242         err = tg3_restart_hw(tp, 0);
4243
4244         if (!err)
4245                 tg3_netif_start(tp);
4246
4247         tg3_full_unlock(tp);
4248
4249         return err;
4250 }
4251
4252 /* Free up pending packets in all rx/tx rings.
4253  *
4254  * The chip has been shut down and the driver detached from
4255  * the networking, so no interrupts or new tx packets will
4256  * end up in the driver.  tp->{tx,}lock is not held and we are not
4257  * in an interrupt context and thus may sleep.
4258  */
4259 static void tg3_free_rings(struct tg3 *tp)
4260 {
4261         struct ring_info *rxp;
4262         int i;
4263
4264         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4265                 rxp = &tp->rx_std_buffers[i];
4266
4267                 if (rxp->skb == NULL)
4268                         continue;
4269                 pci_unmap_single(tp->pdev,
4270                                  pci_unmap_addr(rxp, mapping),
4271                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4272                                  PCI_DMA_FROMDEVICE);
4273                 dev_kfree_skb_any(rxp->skb);
4274                 rxp->skb = NULL;
4275         }
4276
4277         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4278                 rxp = &tp->rx_jumbo_buffers[i];
4279
4280                 if (rxp->skb == NULL)
4281                         continue;
4282                 pci_unmap_single(tp->pdev,
4283                                  pci_unmap_addr(rxp, mapping),
4284                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4285                                  PCI_DMA_FROMDEVICE);
4286                 dev_kfree_skb_any(rxp->skb);
4287                 rxp->skb = NULL;
4288         }
4289
4290         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4291                 struct tx_ring_info *txp;
4292                 struct sk_buff *skb;
4293                 int j;
4294
4295                 txp = &tp->tx_buffers[i];
4296                 skb = txp->skb;
4297
4298                 if (skb == NULL) {
4299                         i++;
4300                         continue;
4301                 }
4302
4303                 pci_unmap_single(tp->pdev,
4304                                  pci_unmap_addr(txp, mapping),
4305                                  skb_headlen(skb),
4306                                  PCI_DMA_TODEVICE);
4307                 txp->skb = NULL;
4308
4309                 i++;
4310
4311                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4312                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4313                         pci_unmap_page(tp->pdev,
4314                                        pci_unmap_addr(txp, mapping),
4315                                        skb_shinfo(skb)->frags[j].size,
4316                                        PCI_DMA_TODEVICE);
4317                         i++;
4318                 }
4319
4320                 dev_kfree_skb_any(skb);
4321         }
4322 }
4323
4324 /* Initialize tx/rx rings for packet processing.
4325  *
4326  * The chip has been shut down and the driver detached from
4327  * the networking, so no interrupts or new tx packets will
4328  * end up in the driver.  tp->{tx,}lock are held and thus
4329  * we may not sleep.
4330  */
4331 static int tg3_init_rings(struct tg3 *tp)
4332 {
4333         u32 i;
4334
4335         /* Free up all the SKBs. */
4336         tg3_free_rings(tp);
4337
4338         /* Zero out all descriptors. */
4339         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4340         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4341         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4342         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4343
4344         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4345         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4346             (tp->dev->mtu > ETH_DATA_LEN))
4347                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4348
4349         /* Initialize invariants of the rings, we only set this
4350          * stuff once.  This works because the card does not
4351          * write into the rx buffer posting rings.
4352          */
4353         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4354                 struct tg3_rx_buffer_desc *rxd;
4355
4356                 rxd = &tp->rx_std[i];
4357                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4358                         << RXD_LEN_SHIFT;
4359                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4360                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4361                                (i << RXD_OPAQUE_INDEX_SHIFT));
4362         }
4363
4364         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4365                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4366                         struct tg3_rx_buffer_desc *rxd;
4367
4368                         rxd = &tp->rx_jumbo[i];
4369                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4370                                 << RXD_LEN_SHIFT;
4371                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4372                                 RXD_FLAG_JUMBO;
4373                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4374                                (i << RXD_OPAQUE_INDEX_SHIFT));
4375                 }
4376         }
4377
4378         /* Now allocate fresh SKBs for each rx ring. */
4379         for (i = 0; i < tp->rx_pending; i++) {
4380                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4381                         printk(KERN_WARNING PFX
4382                                "%s: Using a smaller RX standard ring, "
4383                                "only %d out of %d buffers were allocated "
4384                                "successfully.\n",
4385                                tp->dev->name, i, tp->rx_pending);
4386                         if (i == 0)
4387                                 return -ENOMEM;
4388                         tp->rx_pending = i;
4389                         break;
4390                 }
4391         }
4392
4393         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4394                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4395                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4396                                              -1, i) < 0) {
4397                                 printk(KERN_WARNING PFX
4398                                        "%s: Using a smaller RX jumbo ring, "
4399                                        "only %d out of %d buffers were "
4400                                        "allocated successfully.\n",
4401                                        tp->dev->name, i, tp->rx_jumbo_pending);
4402                                 if (i == 0) {
4403                                         tg3_free_rings(tp);
4404                                         return -ENOMEM;
4405                                 }
4406                                 tp->rx_jumbo_pending = i;
4407                                 break;
4408                         }
4409                 }
4410         }
4411         return 0;
4412 }
4413
4414 /*
4415  * Must not be invoked with interrupt sources disabled and
4416  * the hardware shutdown down.
4417  */
4418 static void tg3_free_consistent(struct tg3 *tp)
4419 {
4420         kfree(tp->rx_std_buffers);
4421         tp->rx_std_buffers = NULL;
4422         if (tp->rx_std) {
4423                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4424                                     tp->rx_std, tp->rx_std_mapping);
4425                 tp->rx_std = NULL;
4426         }
4427         if (tp->rx_jumbo) {
4428                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4429                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4430                 tp->rx_jumbo = NULL;
4431         }
4432         if (tp->rx_rcb) {
4433                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4434                                     tp->rx_rcb, tp->rx_rcb_mapping);
4435                 tp->rx_rcb = NULL;
4436         }
4437         if (tp->tx_ring) {
4438                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4439                         tp->tx_ring, tp->tx_desc_mapping);
4440                 tp->tx_ring = NULL;
4441         }
4442         if (tp->hw_status) {
4443                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4444                                     tp->hw_status, tp->status_mapping);
4445                 tp->hw_status = NULL;
4446         }
4447         if (tp->hw_stats) {
4448                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4449                                     tp->hw_stats, tp->stats_mapping);
4450                 tp->hw_stats = NULL;
4451         }
4452 }
4453
4454 /*
4455  * Must not be invoked with interrupt sources disabled and
4456  * the hardware shutdown down.  Can sleep.
4457  */
4458 static int tg3_alloc_consistent(struct tg3 *tp)
4459 {
4460         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4461                                       (TG3_RX_RING_SIZE +
4462                                        TG3_RX_JUMBO_RING_SIZE)) +
4463                                      (sizeof(struct tx_ring_info) *
4464                                       TG3_TX_RING_SIZE),
4465                                      GFP_KERNEL);
4466         if (!tp->rx_std_buffers)
4467                 return -ENOMEM;
4468
4469         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4470         tp->tx_buffers = (struct tx_ring_info *)
4471                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4472
4473         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4474                                           &tp->rx_std_mapping);
4475         if (!tp->rx_std)
4476                 goto err_out;
4477
4478         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4479                                             &tp->rx_jumbo_mapping);
4480
4481         if (!tp->rx_jumbo)
4482                 goto err_out;
4483
4484         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4485                                           &tp->rx_rcb_mapping);
4486         if (!tp->rx_rcb)
4487                 goto err_out;
4488
4489         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4490                                            &tp->tx_desc_mapping);
4491         if (!tp->tx_ring)
4492                 goto err_out;
4493
4494         tp->hw_status = pci_alloc_consistent(tp->pdev,
4495                                              TG3_HW_STATUS_SIZE,
4496                                              &tp->status_mapping);
4497         if (!tp->hw_status)
4498                 goto err_out;
4499
4500         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4501                                             sizeof(struct tg3_hw_stats),
4502                                             &tp->stats_mapping);
4503         if (!tp->hw_stats)
4504                 goto err_out;
4505
4506         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4507         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4508
4509         return 0;
4510
4511 err_out:
4512         tg3_free_consistent(tp);
4513         return -ENOMEM;
4514 }
4515
4516 #define MAX_WAIT_CNT 1000
4517
4518 /* To stop a block, clear the enable bit and poll till it
4519  * clears.  tp->lock is held.
4520  */
4521 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4522 {
4523         unsigned int i;
4524         u32 val;
4525
4526         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4527                 switch (ofs) {
4528                 case RCVLSC_MODE:
4529                 case DMAC_MODE:
4530                 case MBFREE_MODE:
4531                 case BUFMGR_MODE:
4532                 case MEMARB_MODE:
4533                         /* We can't enable/disable these bits of the
4534                          * 5705/5750, just say success.
4535                          */
4536                         return 0;
4537
4538                 default:
4539                         break;
4540                 };
4541         }
4542
4543         val = tr32(ofs);
4544         val &= ~enable_bit;
4545         tw32_f(ofs, val);
4546
4547         for (i = 0; i < MAX_WAIT_CNT; i++) {
4548                 udelay(100);
4549                 val = tr32(ofs);
4550                 if ((val & enable_bit) == 0)
4551                         break;
4552         }
4553
4554         if (i == MAX_WAIT_CNT && !silent) {
4555                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4556                        "ofs=%lx enable_bit=%x\n",
4557                        ofs, enable_bit);
4558                 return -ENODEV;
4559         }
4560
4561         return 0;
4562 }
4563
4564 /* tp->lock is held. */
4565 static int tg3_abort_hw(struct tg3 *tp, int silent)
4566 {
4567         int i, err;
4568
4569         tg3_disable_ints(tp);
4570
4571         tp->rx_mode &= ~RX_MODE_ENABLE;
4572         tw32_f(MAC_RX_MODE, tp->rx_mode);
4573         udelay(10);
4574
4575         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4576         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4577         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4578         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4579         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4580         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4581
4582         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4583         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4584         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4585         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4586         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4587         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4588         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4589
4590         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4591         tw32_f(MAC_MODE, tp->mac_mode);
4592         udelay(40);
4593
4594         tp->tx_mode &= ~TX_MODE_ENABLE;
4595         tw32_f(MAC_TX_MODE, tp->tx_mode);
4596
4597         for (i = 0; i < MAX_WAIT_CNT; i++) {
4598                 udelay(100);
4599                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4600                         break;
4601         }
4602         if (i >= MAX_WAIT_CNT) {
4603                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4604                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4605                        tp->dev->name, tr32(MAC_TX_MODE));
4606                 err |= -ENODEV;
4607         }
4608
4609         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4610         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4611         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4612
4613         tw32(FTQ_RESET, 0xffffffff);
4614         tw32(FTQ_RESET, 0x00000000);
4615
4616         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4617         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4618
4619         if (tp->hw_status)
4620                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4621         if (tp->hw_stats)
4622                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4623
4624         return err;
4625 }
4626
4627 /* tp->lock is held. */
4628 static int tg3_nvram_lock(struct tg3 *tp)
4629 {
4630         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4631                 int i;
4632
4633                 if (tp->nvram_lock_cnt == 0) {
4634                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4635                         for (i = 0; i < 8000; i++) {
4636                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4637                                         break;
4638                                 udelay(20);
4639                         }
4640                         if (i == 8000) {
4641                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4642                                 return -ENODEV;
4643                         }
4644                 }
4645                 tp->nvram_lock_cnt++;
4646         }
4647         return 0;
4648 }
4649
4650 /* tp->lock is held. */
4651 static void tg3_nvram_unlock(struct tg3 *tp)
4652 {
4653         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4654                 if (tp->nvram_lock_cnt > 0)
4655                         tp->nvram_lock_cnt--;
4656                 if (tp->nvram_lock_cnt == 0)
4657                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4658         }
4659 }
4660
4661 /* tp->lock is held. */
4662 static void tg3_enable_nvram_access(struct tg3 *tp)
4663 {
4664         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4665             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4666                 u32 nvaccess = tr32(NVRAM_ACCESS);
4667
4668                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4669         }
4670 }
4671
4672 /* tp->lock is held. */
4673 static void tg3_disable_nvram_access(struct tg3 *tp)
4674 {
4675         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4676             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4677                 u32 nvaccess = tr32(NVRAM_ACCESS);
4678
4679                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4680         }
4681 }
4682
4683 /* tp->lock is held. */
4684 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4685 {
4686         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4687                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4688
4689         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4690                 switch (kind) {
4691                 case RESET_KIND_INIT:
4692                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4693                                       DRV_STATE_START);
4694                         break;
4695
4696                 case RESET_KIND_SHUTDOWN:
4697                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4698                                       DRV_STATE_UNLOAD);
4699                         break;
4700
4701                 case RESET_KIND_SUSPEND:
4702                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4703                                       DRV_STATE_SUSPEND);
4704                         break;
4705
4706                 default:
4707                         break;
4708                 };
4709         }
4710 }
4711
4712 /* tp->lock is held. */
4713 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4714 {
4715         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4716                 switch (kind) {
4717                 case RESET_KIND_INIT:
4718                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4719                                       DRV_STATE_START_DONE);
4720                         break;
4721
4722                 case RESET_KIND_SHUTDOWN:
4723                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4724                                       DRV_STATE_UNLOAD_DONE);
4725                         break;
4726
4727                 default:
4728                         break;
4729                 };
4730         }
4731 }
4732
4733 /* tp->lock is held. */
4734 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4735 {
4736         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4737                 switch (kind) {
4738                 case RESET_KIND_INIT:
4739                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4740                                       DRV_STATE_START);
4741                         break;
4742
4743                 case RESET_KIND_SHUTDOWN:
4744                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4745                                       DRV_STATE_UNLOAD);
4746                         break;
4747
4748                 case RESET_KIND_SUSPEND:
4749                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4750                                       DRV_STATE_SUSPEND);
4751                         break;
4752
4753                 default:
4754                         break;
4755                 };
4756         }
4757 }
4758
4759 static int tg3_poll_fw(struct tg3 *tp)
4760 {
4761         int i;
4762         u32 val;
4763
4764         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4765                 /* Wait up to 20ms for init done. */
4766                 for (i = 0; i < 200; i++) {
4767                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4768                                 return 0;
4769                         udelay(100);
4770                 }
4771                 return -ENODEV;
4772         }
4773
4774         /* Wait for firmware initialization to complete. */
4775         for (i = 0; i < 100000; i++) {
4776                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4777                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4778                         break;
4779                 udelay(10);
4780         }
4781
4782         /* Chip might not be fitted with firmware.  Some Sun onboard
4783          * parts are configured like that.  So don't signal the timeout
4784          * of the above loop as an error, but do report the lack of
4785          * running firmware once.
4786          */
4787         if (i >= 100000 &&
4788             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4789                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4790
4791                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4792                        tp->dev->name);
4793         }
4794
4795         return 0;
4796 }
4797
4798 static void tg3_stop_fw(struct tg3 *);
4799
4800 /* tp->lock is held. */
4801 static int tg3_chip_reset(struct tg3 *tp)
4802 {
4803         u32 val;
4804         void (*write_op)(struct tg3 *, u32, u32);
4805         int err;
4806
4807         tg3_nvram_lock(tp);
4808
4809         /* No matching tg3_nvram_unlock() after this because
4810          * chip reset below will undo the nvram lock.
4811          */
4812         tp->nvram_lock_cnt = 0;
4813
4814         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4815             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4816             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4817                 tw32(GRC_FASTBOOT_PC, 0);
4818
4819         /*
4820          * We must avoid the readl() that normally takes place.
4821          * It locks machines, causes machine checks, and other
4822          * fun things.  So, temporarily disable the 5701
4823          * hardware workaround, while we do the reset.
4824          */
4825         write_op = tp->write32;
4826         if (write_op == tg3_write_flush_reg32)
4827                 tp->write32 = tg3_write32;
4828
4829         /* Prevent the irq handler from reading or writing PCI registers
4830          * during chip reset when the memory enable bit in the PCI command
4831          * register may be cleared.  The chip does not generate interrupt
4832          * at this time, but the irq handler may still be called due to irq
4833          * sharing or irqpoll.
4834          */
4835         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4836         if (tp->hw_status) {
4837                 tp->hw_status->status = 0;
4838                 tp->hw_status->status_tag = 0;
4839         }
4840         tp->last_tag = 0;
4841         smp_mb();
4842         synchronize_irq(tp->pdev->irq);
4843
4844         /* do the reset */
4845         val = GRC_MISC_CFG_CORECLK_RESET;
4846
4847         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4848                 if (tr32(0x7e2c) == 0x60) {
4849                         tw32(0x7e2c, 0x20);
4850                 }
4851                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4852                         tw32(GRC_MISC_CFG, (1 << 29));
4853                         val |= (1 << 29);
4854                 }
4855         }
4856
4857         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4858                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4859                 tw32(GRC_VCPU_EXT_CTRL,
4860                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4861         }
4862
4863         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4864                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4865         tw32(GRC_MISC_CFG, val);
4866
4867         /* restore 5701 hardware bug workaround write method */
4868         tp->write32 = write_op;
4869
4870         /* Unfortunately, we have to delay before the PCI read back.
4871          * Some 575X chips even will not respond to a PCI cfg access
4872          * when the reset command is given to the chip.
4873          *
4874          * How do these hardware designers expect things to work
4875          * properly if the PCI write is posted for a long period
4876          * of time?  It is always necessary to have some method by
4877          * which a register read back can occur to push the write
4878          * out which does the reset.
4879          *
4880          * For most tg3 variants the trick below was working.
4881          * Ho hum...
4882          */
4883         udelay(120);
4884
4885         /* Flush PCI posted writes.  The normal MMIO registers
4886          * are inaccessible at this time so this is the only
4887          * way to make this reliably (actually, this is no longer
4888          * the case, see above).  I tried to use indirect
4889          * register read/write but this upset some 5701 variants.
4890          */
4891         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4892
4893         udelay(120);
4894
4895         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4896                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4897                         int i;
4898                         u32 cfg_val;
4899
4900                         /* Wait for link training to complete.  */
4901                         for (i = 0; i < 5000; i++)
4902                                 udelay(100);
4903
4904                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4905                         pci_write_config_dword(tp->pdev, 0xc4,
4906                                                cfg_val | (1 << 15));
4907                 }
4908                 /* Set PCIE max payload size and clear error status.  */
4909                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4910         }
4911
4912         /* Re-enable indirect register accesses. */
4913         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4914                                tp->misc_host_ctrl);
4915
4916         /* Set MAX PCI retry to zero. */
4917         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4918         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4919             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4920                 val |= PCISTATE_RETRY_SAME_DMA;
4921         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4922
4923         pci_restore_state(tp->pdev);
4924
4925         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4926
4927         /* Make sure PCI-X relaxed ordering bit is clear. */
4928         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4929         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4930         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4931
4932         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4933                 u32 val;
4934
4935                 /* Chip reset on 5780 will reset MSI enable bit,
4936                  * so need to restore it.
4937                  */
4938                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4939                         u16 ctrl;
4940
4941                         pci_read_config_word(tp->pdev,
4942                                              tp->msi_cap + PCI_MSI_FLAGS,
4943                                              &ctrl);
4944                         pci_write_config_word(tp->pdev,
4945                                               tp->msi_cap + PCI_MSI_FLAGS,
4946                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4947                         val = tr32(MSGINT_MODE);
4948                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4949                 }
4950
4951                 val = tr32(MEMARB_MODE);
4952                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4953
4954         } else
4955                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4956
4957         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4958                 tg3_stop_fw(tp);
4959                 tw32(0x5000, 0x400);
4960         }
4961
4962         tw32(GRC_MODE, tp->grc_mode);
4963
4964         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4965                 u32 val = tr32(0xc4);
4966
4967                 tw32(0xc4, val | (1 << 15));
4968         }
4969
4970         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4971             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4972                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4973                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4974                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4975                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4976         }
4977
4978         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4979                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4980                 tw32_f(MAC_MODE, tp->mac_mode);
4981         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4982                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4983                 tw32_f(MAC_MODE, tp->mac_mode);
4984         } else
4985                 tw32_f(MAC_MODE, 0);
4986         udelay(40);
4987
4988         err = tg3_poll_fw(tp);
4989         if (err)
4990                 return err;
4991
4992         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4993             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4994                 u32 val = tr32(0x7c00);
4995
4996                 tw32(0x7c00, val | (1 << 25));
4997         }
4998
4999         /* Reprobe ASF enable state.  */
5000         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5001         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5002         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5003         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5004                 u32 nic_cfg;
5005
5006                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5007                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5008                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5009                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5010                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5011                 }
5012         }
5013
5014         return 0;
5015 }
5016
5017 /* tp->lock is held. */
5018 static void tg3_stop_fw(struct tg3 *tp)
5019 {
5020         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5021                 u32 val;
5022                 int i;
5023
5024                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5025                 val = tr32(GRC_RX_CPU_EVENT);
5026                 val |= (1 << 14);
5027                 tw32(GRC_RX_CPU_EVENT, val);
5028
5029                 /* Wait for RX cpu to ACK the event.  */
5030                 for (i = 0; i < 100; i++) {
5031                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5032                                 break;
5033                         udelay(1);
5034                 }
5035         }
5036 }
5037
5038 /* tp->lock is held. */
5039 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5040 {
5041         int err;
5042
5043         tg3_stop_fw(tp);
5044
5045         tg3_write_sig_pre_reset(tp, kind);
5046
5047         tg3_abort_hw(tp, silent);
5048         err = tg3_chip_reset(tp);
5049
5050         tg3_write_sig_legacy(tp, kind);
5051         tg3_write_sig_post_reset(tp, kind);
5052
5053         if (err)
5054                 return err;
5055
5056         return 0;
5057 }
5058
5059 #define TG3_FW_RELEASE_MAJOR    0x0
5060 #define TG3_FW_RELASE_MINOR     0x0
5061 #define TG3_FW_RELEASE_FIX      0x0
5062 #define TG3_FW_START_ADDR       0x08000000
5063 #define TG3_FW_TEXT_ADDR        0x08000000
5064 #define TG3_FW_TEXT_LEN         0x9c0
5065 #define TG3_FW_RODATA_ADDR      0x080009c0
5066 #define TG3_FW_RODATA_LEN       0x60
5067 #define TG3_FW_DATA_ADDR        0x08000a40
5068 #define TG3_FW_DATA_LEN         0x20
5069 #define TG3_FW_SBSS_ADDR        0x08000a60
5070 #define TG3_FW_SBSS_LEN         0xc
5071 #define TG3_FW_BSS_ADDR         0x08000a70
5072 #define TG3_FW_BSS_LEN          0x10
5073
5074 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5075         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5076         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5077         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5078         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5079         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5080         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5081         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5082         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5083         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5084         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5085         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5086         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5087         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5088         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5089         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5090         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5091         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5092         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5093         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5094         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5095         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5096         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5097         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5098         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5099         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5100         0, 0, 0, 0, 0, 0,
5101         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5102         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5103         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5104         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5105         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5106         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5107         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5108         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5109         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5110         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5111         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5112         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5113         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5114         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5115         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5116         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5117         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5118         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5119         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5120         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5121         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5122         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5123         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5124         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5125         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5126         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5127         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5128         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5129         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5130         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5131         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5132         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5133         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5134         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5135         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5136         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5137         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5138         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5139         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5140         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5141         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5142         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5143         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5144         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5145         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5146         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5147         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5148         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5149         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5150         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5151         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5152         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5153         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5154         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5155         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5156         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5157         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5158         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5159         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5160         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5161         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5162         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5163         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5164         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5165         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5166 };
5167
5168 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5169         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5170         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5171         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5172         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5173         0x00000000
5174 };
5175
5176 #if 0 /* All zeros, don't eat up space with it. */
5177 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5178         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5179         0x00000000, 0x00000000, 0x00000000, 0x00000000
5180 };
5181 #endif
5182
5183 #define RX_CPU_SCRATCH_BASE     0x30000
5184 #define RX_CPU_SCRATCH_SIZE     0x04000
5185 #define TX_CPU_SCRATCH_BASE     0x34000
5186 #define TX_CPU_SCRATCH_SIZE     0x04000
5187
5188 /* tp->lock is held. */
5189 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5190 {
5191         int i;
5192
5193         BUG_ON(offset == TX_CPU_BASE &&
5194             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5195
5196         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5197                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5198
5199                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5200                 return 0;
5201         }
5202         if (offset == RX_CPU_BASE) {
5203                 for (i = 0; i < 10000; i++) {
5204                         tw32(offset + CPU_STATE, 0xffffffff);
5205                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5206                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5207                                 break;
5208                 }
5209
5210                 tw32(offset + CPU_STATE, 0xffffffff);
5211                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5212                 udelay(10);
5213         } else {
5214                 for (i = 0; i < 10000; i++) {
5215                         tw32(offset + CPU_STATE, 0xffffffff);
5216                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5217                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5218                                 break;
5219                 }
5220         }
5221
5222         if (i >= 10000) {
5223                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5224                        "and %s CPU\n",
5225                        tp->dev->name,
5226                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5227                 return -ENODEV;
5228         }
5229
5230         /* Clear firmware's nvram arbitration. */
5231         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5232                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5233         return 0;
5234 }
5235
5236 struct fw_info {
5237         unsigned int text_base;
5238         unsigned int text_len;
5239         const u32 *text_data;
5240         unsigned int rodata_base;
5241         unsigned int rodata_len;
5242         const u32 *rodata_data;
5243         unsigned int data_base;
5244         unsigned int data_len;
5245         const u32 *data_data;
5246 };
5247
5248 /* tp->lock is held. */
5249 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5250                                  int cpu_scratch_size, struct fw_info *info)
5251 {
5252         int err, lock_err, i;
5253         void (*write_op)(struct tg3 *, u32, u32);
5254
5255         if (cpu_base == TX_CPU_BASE &&
5256             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5257                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5258                        "TX cpu firmware on %s which is 5705.\n",
5259                        tp->dev->name);
5260                 return -EINVAL;
5261         }
5262
5263         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5264                 write_op = tg3_write_mem;
5265         else
5266                 write_op = tg3_write_indirect_reg32;
5267
5268         /* It is possible that bootcode is still loading at this point.
5269          * Get the nvram lock first before halting the cpu.
5270          */
5271         lock_err = tg3_nvram_lock(tp);
5272         err = tg3_halt_cpu(tp, cpu_base);
5273         if (!lock_err)
5274                 tg3_nvram_unlock(tp);
5275         if (err)
5276                 goto out;
5277
5278         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5279                 write_op(tp, cpu_scratch_base + i, 0);
5280         tw32(cpu_base + CPU_STATE, 0xffffffff);
5281         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5282         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5283                 write_op(tp, (cpu_scratch_base +
5284                               (info->text_base & 0xffff) +
5285                               (i * sizeof(u32))),
5286                          (info->text_data ?
5287                           info->text_data[i] : 0));
5288         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5289                 write_op(tp, (cpu_scratch_base +
5290                               (info->rodata_base & 0xffff) +
5291                               (i * sizeof(u32))),
5292                          (info->rodata_data ?
5293                           info->rodata_data[i] : 0));
5294         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5295                 write_op(tp, (cpu_scratch_base +
5296                               (info->data_base & 0xffff) +
5297                               (i * sizeof(u32))),
5298                          (info->data_data ?
5299                           info->data_data[i] : 0));
5300
5301         err = 0;
5302
5303 out:
5304         return err;
5305 }
5306
5307 /* tp->lock is held. */
5308 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5309 {
5310         struct fw_info info;
5311         int err, i;
5312
5313         info.text_base = TG3_FW_TEXT_ADDR;
5314         info.text_len = TG3_FW_TEXT_LEN;
5315         info.text_data = &tg3FwText[0];
5316         info.rodata_base = TG3_FW_RODATA_ADDR;
5317         info.rodata_len = TG3_FW_RODATA_LEN;
5318         info.rodata_data = &tg3FwRodata[0];
5319         info.data_base = TG3_FW_DATA_ADDR;
5320         info.data_len = TG3_FW_DATA_LEN;
5321         info.data_data = NULL;
5322
5323         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5324                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5325                                     &info);
5326         if (err)
5327                 return err;
5328
5329         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5330                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5331                                     &info);
5332         if (err)
5333                 return err;
5334
5335         /* Now startup only the RX cpu. */
5336         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5337         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5338
5339         for (i = 0; i < 5; i++) {
5340                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5341                         break;
5342                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5343                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5344                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5345                 udelay(1000);
5346         }
5347         if (i >= 5) {
5348                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5349                        "to set RX CPU PC, is %08x should be %08x\n",
5350                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5351                        TG3_FW_TEXT_ADDR);
5352                 return -ENODEV;
5353         }
5354         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5355         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5356
5357         return 0;
5358 }
5359
5360
5361 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5362 #define TG3_TSO_FW_RELASE_MINOR         0x6
5363 #define TG3_TSO_FW_RELEASE_FIX          0x0
5364 #define TG3_TSO_FW_START_ADDR           0x08000000
5365 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5366 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5367 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5368 #define TG3_TSO_FW_RODATA_LEN           0x60
5369 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5370 #define TG3_TSO_FW_DATA_LEN             0x30
5371 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5372 #define TG3_TSO_FW_SBSS_LEN             0x2c
5373 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5374 #define TG3_TSO_FW_BSS_LEN              0x894
5375
5376 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5377         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5378         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5379         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5380         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5381         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5382         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5383         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5384         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5385         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5386         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5387         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5388         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5389         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5390         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5391         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5392         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5393         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5394         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5395         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5396         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5397         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5398         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5399         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5400         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5401         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5402         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5403         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5404         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5405         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5406         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5407         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5408         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5409         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5410         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5411         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5412         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5413         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5414         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5415         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5416         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5417         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5418         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5419         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5420         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5421         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5422         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5423         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5424         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5425         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5426         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5427         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5428         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5429         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5430         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5431         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5432         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5433         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5434         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5435         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5436         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5437         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5438         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5439         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5440         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5441         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5442         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5443         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5444         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5445         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5446         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5447         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5448         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5449         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5450         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5451         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5452         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5453         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5454         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5455         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5456         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5457         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5458         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5459         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5460         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5461         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5462         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5463         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5464         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5465         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5466         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5467         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5468         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5469         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5470         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5471         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5472         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5473         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5474         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5475         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5476         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5477         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5478         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5479         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5480         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5481         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5482         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5483         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5484         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5485         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5486         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5487         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5488         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5489         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5490         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5491         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5492         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5493         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5494         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5495         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5496         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5497         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5498         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5499         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5500         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5501         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5502         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5503         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5504         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5505         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5506         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5507         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5508         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5509         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5510         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5511         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5512         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5513         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5514         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5515         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5516         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5517         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5518         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5519         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5520         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5521         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5522         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5523         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5524         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5525         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5526         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5527         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5528         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5529         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5530         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5531         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5532         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5533         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5534         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5535         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5536         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5537         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5538         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5539         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5540         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5541         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5542         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5543         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5544         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5545         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5546         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5547         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5548         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5549         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5550         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5551         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5552         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5553         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5554         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5555         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5556         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5557         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5558         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5559         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5560         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5561         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5562         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5563         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5564         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5565         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5566         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5567         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5568         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5569         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5570         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5571         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5572         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5573         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5574         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5575         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5576         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5577         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5578         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5579         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5580         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5581         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5582         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5583         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5584         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5585         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5586         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5587         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5588         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5589         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5590         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5591         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5592         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5593         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5594         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5595         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5596         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5597         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5598         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5599         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5600         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5601         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5602         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5603         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5604         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5605         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5606         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5607         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5608         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5609         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5610         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5611         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5612         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5613         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5614         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5615         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5616         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5617         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5618         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5619         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5620         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5621         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5622         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5623         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5624         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5625         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5626         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5627         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5628         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5629         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5630         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5631         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5632         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5633         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5634         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5635         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5636         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5637         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5638         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5639         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5640         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5641         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5642         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5643         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5644         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5645         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5646         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5647         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5648         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5649         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5650         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5651         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5652         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5653         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5654         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5655         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5656         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5657         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5658         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5659         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5660         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5661 };
5662
5663 static const u32 tg3TsoFwRodata[] = {
5664         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5665         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5666         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5667         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5668         0x00000000,
5669 };
5670
5671 static const u32 tg3TsoFwData[] = {
5672         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5673         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5674         0x00000000,
5675 };
5676
5677 /* 5705 needs a special version of the TSO firmware.  */
5678 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5679 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5680 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5681 #define TG3_TSO5_FW_START_ADDR          0x00010000
5682 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5683 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5684 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5685 #define TG3_TSO5_FW_RODATA_LEN          0x50
5686 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5687 #define TG3_TSO5_FW_DATA_LEN            0x20
5688 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5689 #define TG3_TSO5_FW_SBSS_LEN            0x28
5690 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5691 #define TG3_TSO5_FW_BSS_LEN             0x88
5692
5693 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5694         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5695         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5696         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5697         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5698         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5699         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5700         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5701         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5702         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5703         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5704         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5705         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5706         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5707         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5708         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5709         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5710         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5711         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5712         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5713         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5714         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5715         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5716         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5717         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5718         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5719         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5720         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5721         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5722         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5723         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5724         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5725         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5726         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5727         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5728         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5729         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5730         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5731         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5732         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5733         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5734         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5735         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5736         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5737         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5738         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5739         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5740         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5741         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5742         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5743         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5744         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5745         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5746         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5747         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5748         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5749         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5750         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5751         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5752         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5753         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5754         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5755         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5756         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5757         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5758         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5759         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5760         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5761         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5762         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5763         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5764         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5765         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5766         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5767         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5768         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5769         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5770         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5771         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5772         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5773         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5774         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5775         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5776         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5777         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5778         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5779         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5780         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5781         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5782         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5783         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5784         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5785         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5786         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5787         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5788         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5789         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5790         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5791         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5792         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5793         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5794         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5795         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5796         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5797         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5798         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5799         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5800         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5801         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5802         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5803         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5804         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5805         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5806         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5807         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5808         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5809         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5810         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5811         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5812         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5813         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5814         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5815         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5816         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5817         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5818         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5819         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5820         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5821         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5822         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5823         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5824         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5825         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5826         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5827         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5828         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5829         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5830         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5831         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5832         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5833         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5834         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5835         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5836         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5837         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5838         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5839         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5840         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5841         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5842         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5843         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5844         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5845         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5846         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5847         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5848         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5849         0x00000000, 0x00000000, 0x00000000,
5850 };
5851
5852 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5853         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5854         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5855         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5856         0x00000000, 0x00000000, 0x00000000,
5857 };
5858
5859 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5860         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5861         0x00000000, 0x00000000, 0x00000000,
5862 };
5863
5864 /* tp->lock is held. */
5865 static int tg3_load_tso_firmware(struct tg3 *tp)
5866 {
5867         struct fw_info info;
5868         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5869         int err, i;
5870
5871         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5872                 return 0;
5873
5874         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5875                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5876                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5877                 info.text_data = &tg3Tso5FwText[0];
5878                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5879                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5880                 info.rodata_data = &tg3Tso5FwRodata[0];
5881                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5882                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5883                 info.data_data = &tg3Tso5FwData[0];
5884                 cpu_base = RX_CPU_BASE;
5885                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5886                 cpu_scratch_size = (info.text_len +
5887                                     info.rodata_len +
5888                                     info.data_len +
5889                                     TG3_TSO5_FW_SBSS_LEN +
5890                                     TG3_TSO5_FW_BSS_LEN);
5891         } else {
5892                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5893                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5894                 info.text_data = &tg3TsoFwText[0];
5895                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5896                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5897                 info.rodata_data = &tg3TsoFwRodata[0];
5898                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5899                 info.data_len = TG3_TSO_FW_DATA_LEN;
5900                 info.data_data = &tg3TsoFwData[0];
5901                 cpu_base = TX_CPU_BASE;
5902                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5903                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5904         }
5905
5906         err = tg3_load_firmware_cpu(tp, cpu_base,
5907                                     cpu_scratch_base, cpu_scratch_size,
5908                                     &info);
5909         if (err)
5910                 return err;
5911
5912         /* Now startup the cpu. */
5913         tw32(cpu_base + CPU_STATE, 0xffffffff);
5914         tw32_f(cpu_base + CPU_PC,    info.text_base);
5915
5916         for (i = 0; i < 5; i++) {
5917                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5918                         break;
5919                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5920                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5921                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5922                 udelay(1000);
5923         }
5924         if (i >= 5) {
5925                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5926                        "to set CPU PC, is %08x should be %08x\n",
5927                        tp->dev->name, tr32(cpu_base + CPU_PC),
5928                        info.text_base);
5929                 return -ENODEV;
5930         }
5931         tw32(cpu_base + CPU_STATE, 0xffffffff);
5932         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5933         return 0;
5934 }
5935
5936
5937 /* tp->lock is held. */
5938 static void __tg3_set_mac_addr(struct tg3 *tp)
5939 {
5940         u32 addr_high, addr_low;
5941         int i;
5942
5943         addr_high = ((tp->dev->dev_addr[0] << 8) |
5944                      tp->dev->dev_addr[1]);
5945         addr_low = ((tp->dev->dev_addr[2] << 24) |
5946                     (tp->dev->dev_addr[3] << 16) |
5947                     (tp->dev->dev_addr[4] <<  8) |
5948                     (tp->dev->dev_addr[5] <<  0));
5949         for (i = 0; i < 4; i++) {
5950                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5951                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5952         }
5953
5954         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5955             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5956                 for (i = 0; i < 12; i++) {
5957                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5958                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5959                 }
5960         }
5961
5962         addr_high = (tp->dev->dev_addr[0] +
5963                      tp->dev->dev_addr[1] +
5964                      tp->dev->dev_addr[2] +
5965                      tp->dev->dev_addr[3] +
5966                      tp->dev->dev_addr[4] +
5967                      tp->dev->dev_addr[5]) &
5968                 TX_BACKOFF_SEED_MASK;
5969         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5970 }
5971
5972 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5973 {
5974         struct tg3 *tp = netdev_priv(dev);
5975         struct sockaddr *addr = p;
5976         int err = 0;
5977
5978         if (!is_valid_ether_addr(addr->sa_data))
5979                 return -EINVAL;
5980
5981         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5982
5983         if (!netif_running(dev))
5984                 return 0;
5985
5986         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5987                 /* Reset chip so that ASF can re-init any MAC addresses it
5988                  * needs.
5989                  */
5990                 tg3_netif_stop(tp);
5991                 tg3_full_lock(tp, 1);
5992
5993                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5994                 err = tg3_restart_hw(tp, 0);
5995                 if (!err)
5996                         tg3_netif_start(tp);
5997                 tg3_full_unlock(tp);
5998         } else {
5999                 spin_lock_bh(&tp->lock);
6000                 __tg3_set_mac_addr(tp);
6001                 spin_unlock_bh(&tp->lock);
6002         }
6003
6004         return err;
6005 }
6006
6007 /* tp->lock is held. */
6008 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6009                            dma_addr_t mapping, u32 maxlen_flags,
6010                            u32 nic_addr)
6011 {
6012         tg3_write_mem(tp,
6013                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6014                       ((u64) mapping >> 32));
6015         tg3_write_mem(tp,
6016                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6017                       ((u64) mapping & 0xffffffff));
6018         tg3_write_mem(tp,
6019                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6020                        maxlen_flags);
6021
6022         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6023                 tg3_write_mem(tp,
6024                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6025                               nic_addr);
6026 }
6027
6028 static void __tg3_set_rx_mode(struct net_device *);
6029 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6030 {
6031         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6032         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6033         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6034         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6035         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6036                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6037                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6038         }
6039         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6040         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6041         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6042                 u32 val = ec->stats_block_coalesce_usecs;
6043
6044                 if (!netif_carrier_ok(tp->dev))
6045                         val = 0;
6046
6047                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6048         }
6049 }
6050
6051 /* tp->lock is held. */
6052 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6053 {
6054         u32 val, rdmac_mode;
6055         int i, err, limit;
6056
6057         tg3_disable_ints(tp);
6058
6059         tg3_stop_fw(tp);
6060
6061         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6062
6063         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6064                 tg3_abort_hw(tp, 1);
6065         }
6066
6067         if (reset_phy)
6068                 tg3_phy_reset(tp);
6069
6070         err = tg3_chip_reset(tp);
6071         if (err)
6072                 return err;
6073
6074         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6075
6076         /* This works around an issue with Athlon chipsets on
6077          * B3 tigon3 silicon.  This bit has no effect on any
6078          * other revision.  But do not set this on PCI Express
6079          * chips.
6080          */
6081         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6082                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6083         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6084
6085         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6086             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6087                 val = tr32(TG3PCI_PCISTATE);
6088                 val |= PCISTATE_RETRY_SAME_DMA;
6089                 tw32(TG3PCI_PCISTATE, val);
6090         }
6091
6092         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6093                 /* Enable some hw fixes.  */
6094                 val = tr32(TG3PCI_MSI_DATA);
6095                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6096                 tw32(TG3PCI_MSI_DATA, val);
6097         }
6098
6099         /* Descriptor ring init may make accesses to the
6100          * NIC SRAM area to setup the TX descriptors, so we
6101          * can only do this after the hardware has been
6102          * successfully reset.
6103          */
6104         err = tg3_init_rings(tp);
6105         if (err)
6106                 return err;
6107
6108         /* This value is determined during the probe time DMA
6109          * engine test, tg3_test_dma.
6110          */
6111         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6112
6113         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6114                           GRC_MODE_4X_NIC_SEND_RINGS |
6115                           GRC_MODE_NO_TX_PHDR_CSUM |
6116                           GRC_MODE_NO_RX_PHDR_CSUM);
6117         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6118
6119         /* Pseudo-header checksum is done by hardware logic and not
6120          * the offload processers, so make the chip do the pseudo-
6121          * header checksums on receive.  For transmit it is more
6122          * convenient to do the pseudo-header checksum in software
6123          * as Linux does that on transmit for us in all cases.
6124          */
6125         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6126
6127         tw32(GRC_MODE,
6128              tp->grc_mode |
6129              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6130
6131         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6132         val = tr32(GRC_MISC_CFG);
6133         val &= ~0xff;
6134         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6135         tw32(GRC_MISC_CFG, val);
6136
6137         /* Initialize MBUF/DESC pool. */
6138         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6139                 /* Do nothing.  */
6140         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6141                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6142                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6143                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6144                 else
6145                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6146                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6147                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6148         }
6149         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6150                 int fw_len;
6151
6152                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6153                           TG3_TSO5_FW_RODATA_LEN +
6154                           TG3_TSO5_FW_DATA_LEN +
6155                           TG3_TSO5_FW_SBSS_LEN +
6156                           TG3_TSO5_FW_BSS_LEN);
6157                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6158                 tw32(BUFMGR_MB_POOL_ADDR,
6159                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6160                 tw32(BUFMGR_MB_POOL_SIZE,
6161                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6162         }
6163
6164         if (tp->dev->mtu <= ETH_DATA_LEN) {
6165                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6166                      tp->bufmgr_config.mbuf_read_dma_low_water);
6167                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6168                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6169                 tw32(BUFMGR_MB_HIGH_WATER,
6170                      tp->bufmgr_config.mbuf_high_water);
6171         } else {
6172                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6173                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6174                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6175                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6176                 tw32(BUFMGR_MB_HIGH_WATER,
6177                      tp->bufmgr_config.mbuf_high_water_jumbo);
6178         }
6179         tw32(BUFMGR_DMA_LOW_WATER,
6180              tp->bufmgr_config.dma_low_water);
6181         tw32(BUFMGR_DMA_HIGH_WATER,
6182              tp->bufmgr_config.dma_high_water);
6183
6184         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6185         for (i = 0; i < 2000; i++) {
6186                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6187                         break;
6188                 udelay(10);
6189         }
6190         if (i >= 2000) {
6191                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6192                        tp->dev->name);
6193                 return -ENODEV;
6194         }
6195
6196         /* Setup replenish threshold. */
6197         val = tp->rx_pending / 8;
6198         if (val == 0)
6199                 val = 1;
6200         else if (val > tp->rx_std_max_post)
6201                 val = tp->rx_std_max_post;
6202         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6203                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6204                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6205
6206                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6207                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6208         }
6209
6210         tw32(RCVBDI_STD_THRESH, val);
6211
6212         /* Initialize TG3_BDINFO's at:
6213          *  RCVDBDI_STD_BD:     standard eth size rx ring
6214          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6215          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6216          *
6217          * like so:
6218          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6219          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6220          *                              ring attribute flags
6221          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6222          *
6223          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6224          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6225          *
6226          * The size of each ring is fixed in the firmware, but the location is
6227          * configurable.
6228          */
6229         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6230              ((u64) tp->rx_std_mapping >> 32));
6231         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6232              ((u64) tp->rx_std_mapping & 0xffffffff));
6233         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6234              NIC_SRAM_RX_BUFFER_DESC);
6235
6236         /* Don't even try to program the JUMBO/MINI buffer descriptor
6237          * configs on 5705.
6238          */
6239         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6240                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6241                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6242         } else {
6243                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6244                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6245
6246                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6247                      BDINFO_FLAGS_DISABLED);
6248
6249                 /* Setup replenish threshold. */
6250                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6251
6252                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6253                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6254                              ((u64) tp->rx_jumbo_mapping >> 32));
6255                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6256                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6257                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6258                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6259                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6260                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6261                 } else {
6262                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6263                              BDINFO_FLAGS_DISABLED);
6264                 }
6265
6266         }
6267
6268         /* There is only one send ring on 5705/5750, no need to explicitly
6269          * disable the others.
6270          */
6271         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6272                 /* Clear out send RCB ring in SRAM. */
6273                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6274                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6275                                       BDINFO_FLAGS_DISABLED);
6276         }
6277
6278         tp->tx_prod = 0;
6279         tp->tx_cons = 0;
6280         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6281         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6282
6283         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6284                        tp->tx_desc_mapping,
6285                        (TG3_TX_RING_SIZE <<
6286                         BDINFO_FLAGS_MAXLEN_SHIFT),
6287                        NIC_SRAM_TX_BUFFER_DESC);
6288
6289         /* There is only one receive return ring on 5705/5750, no need
6290          * to explicitly disable the others.
6291          */
6292         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6293                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6294                      i += TG3_BDINFO_SIZE) {
6295                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6296                                       BDINFO_FLAGS_DISABLED);
6297                 }
6298         }
6299
6300         tp->rx_rcb_ptr = 0;
6301         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6302
6303         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6304                        tp->rx_rcb_mapping,
6305                        (TG3_RX_RCB_RING_SIZE(tp) <<
6306                         BDINFO_FLAGS_MAXLEN_SHIFT),
6307                        0);
6308
6309         tp->rx_std_ptr = tp->rx_pending;
6310         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6311                      tp->rx_std_ptr);
6312
6313         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6314                                                 tp->rx_jumbo_pending : 0;
6315         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6316                      tp->rx_jumbo_ptr);
6317
6318         /* Initialize MAC address and backoff seed. */
6319         __tg3_set_mac_addr(tp);
6320
6321         /* MTU + ethernet header + FCS + optional VLAN tag */
6322         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6323
6324         /* The slot time is changed by tg3_setup_phy if we
6325          * run at gigabit with half duplex.
6326          */
6327         tw32(MAC_TX_LENGTHS,
6328              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6329              (6 << TX_LENGTHS_IPG_SHIFT) |
6330              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6331
6332         /* Receive rules. */
6333         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6334         tw32(RCVLPC_CONFIG, 0x0181);
6335
6336         /* Calculate RDMAC_MODE setting early, we need it to determine
6337          * the RCVLPC_STATE_ENABLE mask.
6338          */
6339         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6340                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6341                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6342                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6343                       RDMAC_MODE_LNGREAD_ENAB);
6344
6345         /* If statement applies to 5705 and 5750 PCI devices only */
6346         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6347              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6348             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6349                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6350                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6351                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6352                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6353                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6354                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6355                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6356                 }
6357         }
6358
6359         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6360                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6361
6362         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6363                 rdmac_mode |= (1 << 27);
6364
6365         /* Receive/send statistics. */
6366         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6367                 val = tr32(RCVLPC_STATS_ENABLE);
6368                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6369                 tw32(RCVLPC_STATS_ENABLE, val);
6370         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6371                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6372                 val = tr32(RCVLPC_STATS_ENABLE);
6373                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6374                 tw32(RCVLPC_STATS_ENABLE, val);
6375         } else {
6376                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6377         }
6378         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6379         tw32(SNDDATAI_STATSENAB, 0xffffff);
6380         tw32(SNDDATAI_STATSCTRL,
6381              (SNDDATAI_SCTRL_ENABLE |
6382               SNDDATAI_SCTRL_FASTUPD));
6383
6384         /* Setup host coalescing engine. */
6385         tw32(HOSTCC_MODE, 0);
6386         for (i = 0; i < 2000; i++) {
6387                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6388                         break;
6389                 udelay(10);
6390         }
6391
6392         __tg3_set_coalesce(tp, &tp->coal);
6393
6394         /* set status block DMA address */
6395         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6396              ((u64) tp->status_mapping >> 32));
6397         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6398              ((u64) tp->status_mapping & 0xffffffff));
6399
6400         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6401                 /* Status/statistics block address.  See tg3_timer,
6402                  * the tg3_periodic_fetch_stats call there, and
6403                  * tg3_get_stats to see how this works for 5705/5750 chips.
6404                  */
6405                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6406                      ((u64) tp->stats_mapping >> 32));
6407                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6408                      ((u64) tp->stats_mapping & 0xffffffff));
6409                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6410                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6411         }
6412
6413         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6414
6415         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6416         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6417         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6418                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6419
6420         /* Clear statistics/status block in chip, and status block in ram. */
6421         for (i = NIC_SRAM_STATS_BLK;
6422              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6423              i += sizeof(u32)) {
6424                 tg3_write_mem(tp, i, 0);
6425                 udelay(40);
6426         }
6427         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6428
6429         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6430                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6431                 /* reset to prevent losing 1st rx packet intermittently */
6432                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6433                 udelay(10);
6434         }
6435
6436         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6437                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6438         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6439         udelay(40);
6440
6441         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6442          * If TG3_FLG2_IS_NIC is zero, we should read the
6443          * register to preserve the GPIO settings for LOMs. The GPIOs,
6444          * whether used as inputs or outputs, are set by boot code after
6445          * reset.
6446          */
6447         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6448                 u32 gpio_mask;
6449
6450                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6451                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6452                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6453
6454                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6455                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6456                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6457
6458                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6459                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6460
6461                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6462
6463                 /* GPIO1 must be driven high for eeprom write protect */
6464                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6465                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6466                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6467         }
6468         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6469         udelay(100);
6470
6471         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6472         tp->last_tag = 0;
6473
6474         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6475                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6476                 udelay(40);
6477         }
6478
6479         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6480                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6481                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6482                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6483                WDMAC_MODE_LNGREAD_ENAB);
6484
6485         /* If statement applies to 5705 and 5750 PCI devices only */
6486         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6487              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6488             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6489                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6490                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6491                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6492                         /* nothing */
6493                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6494                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6495                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6496                         val |= WDMAC_MODE_RX_ACCEL;
6497                 }
6498         }
6499
6500         /* Enable host coalescing bug fix */
6501         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6502             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6503                 val |= (1 << 29);
6504
6505         tw32_f(WDMAC_MODE, val);
6506         udelay(40);
6507
6508         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6509                 val = tr32(TG3PCI_X_CAPS);
6510                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6511                         val &= ~PCIX_CAPS_BURST_MASK;
6512                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6513                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6514                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6515                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6516                 }
6517                 tw32(TG3PCI_X_CAPS, val);
6518         }
6519
6520         tw32_f(RDMAC_MODE, rdmac_mode);
6521         udelay(40);
6522
6523         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6524         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6525                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6526         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6527         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6528         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6529         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6530         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6531         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6532                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6533         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6534         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6535
6536         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6537                 err = tg3_load_5701_a0_firmware_fix(tp);
6538                 if (err)
6539                         return err;
6540         }
6541
6542         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6543                 err = tg3_load_tso_firmware(tp);
6544                 if (err)
6545                         return err;
6546         }
6547
6548         tp->tx_mode = TX_MODE_ENABLE;
6549         tw32_f(MAC_TX_MODE, tp->tx_mode);
6550         udelay(100);
6551
6552         tp->rx_mode = RX_MODE_ENABLE;
6553         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6554                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6555
6556         tw32_f(MAC_RX_MODE, tp->rx_mode);
6557         udelay(10);
6558
6559         if (tp->link_config.phy_is_low_power) {
6560                 tp->link_config.phy_is_low_power = 0;
6561                 tp->link_config.speed = tp->link_config.orig_speed;
6562                 tp->link_config.duplex = tp->link_config.orig_duplex;
6563                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6564         }
6565
6566         tp->mi_mode = MAC_MI_MODE_BASE;
6567         tw32_f(MAC_MI_MODE, tp->mi_mode);
6568         udelay(80);
6569
6570         tw32(MAC_LED_CTRL, tp->led_ctrl);
6571
6572         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6573         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6574                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6575                 udelay(10);
6576         }
6577         tw32_f(MAC_RX_MODE, tp->rx_mode);
6578         udelay(10);
6579
6580         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6581                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6582                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6583                         /* Set drive transmission level to 1.2V  */
6584                         /* only if the signal pre-emphasis bit is not set  */
6585                         val = tr32(MAC_SERDES_CFG);
6586                         val &= 0xfffff000;
6587                         val |= 0x880;
6588                         tw32(MAC_SERDES_CFG, val);
6589                 }
6590                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6591                         tw32(MAC_SERDES_CFG, 0x616000);
6592         }
6593
6594         /* Prevent chip from dropping frames when flow control
6595          * is enabled.
6596          */
6597         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6598
6599         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6600             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6601                 /* Use hardware link auto-negotiation */
6602                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6603         }
6604
6605         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6606             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6607                 u32 tmp;
6608
6609                 tmp = tr32(SERDES_RX_CTRL);
6610                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6611                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6612                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6613                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6614         }
6615
6616         err = tg3_setup_phy(tp, 0);
6617         if (err)
6618                 return err;
6619
6620         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6621             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6622                 u32 tmp;
6623
6624                 /* Clear CRC stats. */
6625                 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6626                         tg3_writephy(tp, MII_TG3_TEST1,
6627                                      tmp | MII_TG3_TEST1_CRC_EN);
6628                         tg3_readphy(tp, 0x14, &tmp);
6629                 }
6630         }
6631
6632         __tg3_set_rx_mode(tp->dev);
6633
6634         /* Initialize receive rules. */
6635         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6636         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6637         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6638         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6639
6640         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6641             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6642                 limit = 8;
6643         else
6644                 limit = 16;
6645         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6646                 limit -= 4;
6647         switch (limit) {
6648         case 16:
6649                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6650         case 15:
6651                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6652         case 14:
6653                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6654         case 13:
6655                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6656         case 12:
6657                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6658         case 11:
6659                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6660         case 10:
6661                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6662         case 9:
6663                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6664         case 8:
6665                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6666         case 7:
6667                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6668         case 6:
6669                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6670         case 5:
6671                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6672         case 4:
6673                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6674         case 3:
6675                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6676         case 2:
6677         case 1:
6678
6679         default:
6680                 break;
6681         };
6682
6683         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6684
6685         return 0;
6686 }
6687
6688 /* Called at device open time to get the chip ready for
6689  * packet processing.  Invoked with tp->lock held.
6690  */
6691 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6692 {
6693         int err;
6694
6695         /* Force the chip into D0. */
6696         err = tg3_set_power_state(tp, PCI_D0);
6697         if (err)
6698                 goto out;
6699
6700         tg3_switch_clocks(tp);
6701
6702         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6703
6704         err = tg3_reset_hw(tp, reset_phy);
6705
6706 out:
6707         return err;
6708 }
6709
6710 #define TG3_STAT_ADD32(PSTAT, REG) \
6711 do {    u32 __val = tr32(REG); \
6712         (PSTAT)->low += __val; \
6713         if ((PSTAT)->low < __val) \
6714                 (PSTAT)->high += 1; \
6715 } while (0)
6716
6717 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6718 {
6719         struct tg3_hw_stats *sp = tp->hw_stats;
6720
6721         if (!netif_carrier_ok(tp->dev))
6722                 return;
6723
6724         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6725         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6726         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6727         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6728         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6729         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6730         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6731         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6732         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6733         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6734         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6735         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6736         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6737
6738         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6739         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6740         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6741         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6742         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6743         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6744         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6745         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6746         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6747         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6748         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6749         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6750         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6751         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6752
6753         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6754         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6755         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6756 }
6757
6758 static void tg3_timer(unsigned long __opaque)
6759 {
6760         struct tg3 *tp = (struct tg3 *) __opaque;
6761
6762         if (tp->irq_sync)
6763                 goto restart_timer;
6764
6765         spin_lock(&tp->lock);
6766
6767         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6768                 /* All of this garbage is because when using non-tagged
6769                  * IRQ status the mailbox/status_block protocol the chip
6770                  * uses with the cpu is race prone.
6771                  */
6772                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6773                         tw32(GRC_LOCAL_CTRL,
6774                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6775                 } else {
6776                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6777                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6778                 }
6779
6780                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6781                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6782                         spin_unlock(&tp->lock);
6783                         schedule_work(&tp->reset_task);
6784                         return;
6785                 }
6786         }
6787
6788         /* This part only runs once per second. */
6789         if (!--tp->timer_counter) {
6790                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6791                         tg3_periodic_fetch_stats(tp);
6792
6793                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6794                         u32 mac_stat;
6795                         int phy_event;
6796
6797                         mac_stat = tr32(MAC_STATUS);
6798
6799                         phy_event = 0;
6800                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6801                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6802                                         phy_event = 1;
6803                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6804                                 phy_event = 1;
6805
6806                         if (phy_event)
6807                                 tg3_setup_phy(tp, 0);
6808                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6809                         u32 mac_stat = tr32(MAC_STATUS);
6810                         int need_setup = 0;
6811
6812                         if (netif_carrier_ok(tp->dev) &&
6813                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6814                                 need_setup = 1;
6815                         }
6816                         if (! netif_carrier_ok(tp->dev) &&
6817                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6818                                          MAC_STATUS_SIGNAL_DET))) {
6819                                 need_setup = 1;
6820                         }
6821                         if (need_setup) {
6822                                 if (!tp->serdes_counter) {
6823                                         tw32_f(MAC_MODE,
6824                                              (tp->mac_mode &
6825                                               ~MAC_MODE_PORT_MODE_MASK));
6826                                         udelay(40);
6827                                         tw32_f(MAC_MODE, tp->mac_mode);
6828                                         udelay(40);
6829                                 }
6830                                 tg3_setup_phy(tp, 0);
6831                         }
6832                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6833                         tg3_serdes_parallel_detect(tp);
6834
6835                 tp->timer_counter = tp->timer_multiplier;
6836         }
6837
6838         /* Heartbeat is only sent once every 2 seconds.
6839          *
6840          * The heartbeat is to tell the ASF firmware that the host
6841          * driver is still alive.  In the event that the OS crashes,
6842          * ASF needs to reset the hardware to free up the FIFO space
6843          * that may be filled with rx packets destined for the host.
6844          * If the FIFO is full, ASF will no longer function properly.
6845          *
6846          * Unintended resets have been reported on real time kernels
6847          * where the timer doesn't run on time.  Netpoll will also have
6848          * same problem.
6849          *
6850          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6851          * to check the ring condition when the heartbeat is expiring
6852          * before doing the reset.  This will prevent most unintended
6853          * resets.
6854          */
6855         if (!--tp->asf_counter) {
6856                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6857                         u32 val;
6858
6859                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6860                                       FWCMD_NICDRV_ALIVE3);
6861                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6862                         /* 5 seconds timeout */
6863                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6864                         val = tr32(GRC_RX_CPU_EVENT);
6865                         val |= (1 << 14);
6866                         tw32(GRC_RX_CPU_EVENT, val);
6867                 }
6868                 tp->asf_counter = tp->asf_multiplier;
6869         }
6870
6871         spin_unlock(&tp->lock);
6872
6873 restart_timer:
6874         tp->timer.expires = jiffies + tp->timer_offset;
6875         add_timer(&tp->timer);
6876 }
6877
6878 static int tg3_request_irq(struct tg3 *tp)
6879 {
6880         irq_handler_t fn;
6881         unsigned long flags;
6882         struct net_device *dev = tp->dev;
6883
6884         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6885                 fn = tg3_msi;
6886                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6887                         fn = tg3_msi_1shot;
6888                 flags = IRQF_SAMPLE_RANDOM;
6889         } else {
6890                 fn = tg3_interrupt;
6891                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6892                         fn = tg3_interrupt_tagged;
6893                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6894         }
6895         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6896 }
6897
6898 static int tg3_test_interrupt(struct tg3 *tp)
6899 {
6900         struct net_device *dev = tp->dev;
6901         int err, i, intr_ok = 0;
6902
6903         if (!netif_running(dev))
6904                 return -ENODEV;
6905
6906         tg3_disable_ints(tp);
6907
6908         free_irq(tp->pdev->irq, dev);
6909
6910         err = request_irq(tp->pdev->irq, tg3_test_isr,
6911                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6912         if (err)
6913                 return err;
6914
6915         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6916         tg3_enable_ints(tp);
6917
6918         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6919                HOSTCC_MODE_NOW);
6920
6921         for (i = 0; i < 5; i++) {
6922                 u32 int_mbox, misc_host_ctrl;
6923
6924                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6925                                         TG3_64BIT_REG_LOW);
6926                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6927
6928                 if ((int_mbox != 0) ||
6929                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6930                         intr_ok = 1;
6931                         break;
6932                 }
6933
6934                 msleep(10);
6935         }
6936
6937         tg3_disable_ints(tp);
6938
6939         free_irq(tp->pdev->irq, dev);
6940
6941         err = tg3_request_irq(tp);
6942
6943         if (err)
6944                 return err;
6945
6946         if (intr_ok)
6947                 return 0;
6948
6949         return -EIO;
6950 }
6951
6952 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6953  * successfully restored
6954  */
6955 static int tg3_test_msi(struct tg3 *tp)
6956 {
6957         struct net_device *dev = tp->dev;
6958         int err;
6959         u16 pci_cmd;
6960
6961         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6962                 return 0;
6963
6964         /* Turn off SERR reporting in case MSI terminates with Master
6965          * Abort.
6966          */
6967         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6968         pci_write_config_word(tp->pdev, PCI_COMMAND,
6969                               pci_cmd & ~PCI_COMMAND_SERR);
6970
6971         err = tg3_test_interrupt(tp);
6972
6973         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6974
6975         if (!err)
6976                 return 0;
6977
6978         /* other failures */
6979         if (err != -EIO)
6980                 return err;
6981
6982         /* MSI test failed, go back to INTx mode */
6983         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6984                "switching to INTx mode. Please report this failure to "
6985                "the PCI maintainer and include system chipset information.\n",
6986                        tp->dev->name);
6987
6988         free_irq(tp->pdev->irq, dev);
6989         pci_disable_msi(tp->pdev);
6990
6991         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6992
6993         err = tg3_request_irq(tp);
6994         if (err)
6995                 return err;
6996
6997         /* Need to reset the chip because the MSI cycle may have terminated
6998          * with Master Abort.
6999          */
7000         tg3_full_lock(tp, 1);
7001
7002         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7003         err = tg3_init_hw(tp, 1);
7004
7005         tg3_full_unlock(tp);
7006
7007         if (err)
7008                 free_irq(tp->pdev->irq, dev);
7009
7010         return err;
7011 }
7012
7013 static int tg3_open(struct net_device *dev)
7014 {
7015         struct tg3 *tp = netdev_priv(dev);
7016         int err;
7017
7018         netif_carrier_off(tp->dev);
7019
7020         tg3_full_lock(tp, 0);
7021
7022         err = tg3_set_power_state(tp, PCI_D0);
7023         if (err) {
7024                 tg3_full_unlock(tp);
7025                 return err;
7026         }
7027
7028         tg3_disable_ints(tp);
7029         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7030
7031         tg3_full_unlock(tp);
7032
7033         /* The placement of this call is tied
7034          * to the setup and use of Host TX descriptors.
7035          */
7036         err = tg3_alloc_consistent(tp);
7037         if (err)
7038                 return err;
7039
7040         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7041             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
7042             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7043             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7044               (tp->pdev_peer == tp->pdev))) {
7045                 /* All MSI supporting chips should support tagged
7046                  * status.  Assert that this is the case.
7047                  */
7048                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7049                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7050                                "Not using MSI.\n", tp->dev->name);
7051                 } else if (pci_enable_msi(tp->pdev) == 0) {
7052                         u32 msi_mode;
7053
7054                         msi_mode = tr32(MSGINT_MODE);
7055                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7056                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7057                 }
7058         }
7059         err = tg3_request_irq(tp);
7060
7061         if (err) {
7062                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7063                         pci_disable_msi(tp->pdev);
7064                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7065                 }
7066                 tg3_free_consistent(tp);
7067                 return err;
7068         }
7069
7070         tg3_full_lock(tp, 0);
7071
7072         err = tg3_init_hw(tp, 1);
7073         if (err) {
7074                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7075                 tg3_free_rings(tp);
7076         } else {
7077                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7078                         tp->timer_offset = HZ;
7079                 else
7080                         tp->timer_offset = HZ / 10;
7081
7082                 BUG_ON(tp->timer_offset > HZ);
7083                 tp->timer_counter = tp->timer_multiplier =
7084                         (HZ / tp->timer_offset);
7085                 tp->asf_counter = tp->asf_multiplier =
7086                         ((HZ / tp->timer_offset) * 2);
7087
7088                 init_timer(&tp->timer);
7089                 tp->timer.expires = jiffies + tp->timer_offset;
7090                 tp->timer.data = (unsigned long) tp;
7091                 tp->timer.function = tg3_timer;
7092         }
7093
7094         tg3_full_unlock(tp);
7095
7096         if (err) {
7097                 free_irq(tp->pdev->irq, dev);
7098                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7099                         pci_disable_msi(tp->pdev);
7100                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7101                 }
7102                 tg3_free_consistent(tp);
7103                 return err;
7104         }
7105
7106         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7107                 err = tg3_test_msi(tp);
7108
7109                 if (err) {
7110                         tg3_full_lock(tp, 0);
7111
7112                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7113                                 pci_disable_msi(tp->pdev);
7114                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7115                         }
7116                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7117                         tg3_free_rings(tp);
7118                         tg3_free_consistent(tp);
7119
7120                         tg3_full_unlock(tp);
7121
7122                         return err;
7123                 }
7124
7125                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7126                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7127                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7128
7129                                 tw32(PCIE_TRANSACTION_CFG,
7130                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7131                         }
7132                 }
7133         }
7134
7135         tg3_full_lock(tp, 0);
7136
7137         add_timer(&tp->timer);
7138         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7139         tg3_enable_ints(tp);
7140
7141         tg3_full_unlock(tp);
7142
7143         netif_start_queue(dev);
7144
7145         return 0;
7146 }
7147
7148 #if 0
7149 /*static*/ void tg3_dump_state(struct tg3 *tp)
7150 {
7151         u32 val32, val32_2, val32_3, val32_4, val32_5;
7152         u16 val16;
7153         int i;
7154
7155         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7156         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7157         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7158                val16, val32);
7159
7160         /* MAC block */
7161         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7162                tr32(MAC_MODE), tr32(MAC_STATUS));
7163         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7164                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7165         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7166                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7167         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7168                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7169
7170         /* Send data initiator control block */
7171         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7172                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7173         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7174                tr32(SNDDATAI_STATSCTRL));
7175
7176         /* Send data completion control block */
7177         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7178
7179         /* Send BD ring selector block */
7180         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7181                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7182
7183         /* Send BD initiator control block */
7184         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7185                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7186
7187         /* Send BD completion control block */
7188         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7189
7190         /* Receive list placement control block */
7191         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7192                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7193         printk("       RCVLPC_STATSCTRL[%08x]\n",
7194                tr32(RCVLPC_STATSCTRL));
7195
7196         /* Receive data and receive BD initiator control block */
7197         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7198                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7199
7200         /* Receive data completion control block */
7201         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7202                tr32(RCVDCC_MODE));
7203
7204         /* Receive BD initiator control block */
7205         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7206                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7207
7208         /* Receive BD completion control block */
7209         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7210                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7211
7212         /* Receive list selector control block */
7213         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7214                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7215
7216         /* Mbuf cluster free block */
7217         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7218                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7219
7220         /* Host coalescing control block */
7221         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7222                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7223         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7224                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7225                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7226         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7227                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7228                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7229         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7230                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7231         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7232                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7233
7234         /* Memory arbiter control block */
7235         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7236                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7237
7238         /* Buffer manager control block */
7239         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7240                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7241         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7242                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7243         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7244                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7245                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7246                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7247
7248         /* Read DMA control block */
7249         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7250                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7251
7252         /* Write DMA control block */
7253         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7254                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7255
7256         /* DMA completion block */
7257         printk("DEBUG: DMAC_MODE[%08x]\n",
7258                tr32(DMAC_MODE));
7259
7260         /* GRC block */
7261         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7262                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7263         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7264                tr32(GRC_LOCAL_CTRL));
7265
7266         /* TG3_BDINFOs */
7267         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7268                tr32(RCVDBDI_JUMBO_BD + 0x0),
7269                tr32(RCVDBDI_JUMBO_BD + 0x4),
7270                tr32(RCVDBDI_JUMBO_BD + 0x8),
7271                tr32(RCVDBDI_JUMBO_BD + 0xc));
7272         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7273                tr32(RCVDBDI_STD_BD + 0x0),
7274                tr32(RCVDBDI_STD_BD + 0x4),
7275                tr32(RCVDBDI_STD_BD + 0x8),
7276                tr32(RCVDBDI_STD_BD + 0xc));
7277         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7278                tr32(RCVDBDI_MINI_BD + 0x0),
7279                tr32(RCVDBDI_MINI_BD + 0x4),
7280                tr32(RCVDBDI_MINI_BD + 0x8),
7281                tr32(RCVDBDI_MINI_BD + 0xc));
7282
7283         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7284         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7285         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7286         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7287         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7288                val32, val32_2, val32_3, val32_4);
7289
7290         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7291         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7292         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7293         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7294         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7295                val32, val32_2, val32_3, val32_4);
7296
7297         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7298         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7299         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7300         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7301         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7302         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7303                val32, val32_2, val32_3, val32_4, val32_5);
7304
7305         /* SW status block */
7306         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7307                tp->hw_status->status,
7308                tp->hw_status->status_tag,
7309                tp->hw_status->rx_jumbo_consumer,
7310                tp->hw_status->rx_consumer,
7311                tp->hw_status->rx_mini_consumer,
7312                tp->hw_status->idx[0].rx_producer,
7313                tp->hw_status->idx[0].tx_consumer);
7314
7315         /* SW statistics block */
7316         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7317                ((u32 *)tp->hw_stats)[0],
7318                ((u32 *)tp->hw_stats)[1],
7319                ((u32 *)tp->hw_stats)[2],
7320                ((u32 *)tp->hw_stats)[3]);
7321
7322         /* Mailboxes */
7323         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7324                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7325                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7326                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7327                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7328
7329         /* NIC side send descriptors. */
7330         for (i = 0; i < 6; i++) {
7331                 unsigned long txd;
7332
7333                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7334                         + (i * sizeof(struct tg3_tx_buffer_desc));
7335                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7336                        i,
7337                        readl(txd + 0x0), readl(txd + 0x4),
7338                        readl(txd + 0x8), readl(txd + 0xc));
7339         }
7340
7341         /* NIC side RX descriptors. */
7342         for (i = 0; i < 6; i++) {
7343                 unsigned long rxd;
7344
7345                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7346                         + (i * sizeof(struct tg3_rx_buffer_desc));
7347                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7348                        i,
7349                        readl(rxd + 0x0), readl(rxd + 0x4),
7350                        readl(rxd + 0x8), readl(rxd + 0xc));
7351                 rxd += (4 * sizeof(u32));
7352                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7353                        i,
7354                        readl(rxd + 0x0), readl(rxd + 0x4),
7355                        readl(rxd + 0x8), readl(rxd + 0xc));
7356         }
7357
7358         for (i = 0; i < 6; i++) {
7359                 unsigned long rxd;
7360
7361                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7362                         + (i * sizeof(struct tg3_rx_buffer_desc));
7363                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7364                        i,
7365                        readl(rxd + 0x0), readl(rxd + 0x4),
7366                        readl(rxd + 0x8), readl(rxd + 0xc));
7367                 rxd += (4 * sizeof(u32));
7368                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7369                        i,
7370                        readl(rxd + 0x0), readl(rxd + 0x4),
7371                        readl(rxd + 0x8), readl(rxd + 0xc));
7372         }
7373 }
7374 #endif
7375
7376 static struct net_device_stats *tg3_get_stats(struct net_device *);
7377 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7378
7379 static int tg3_close(struct net_device *dev)
7380 {
7381         struct tg3 *tp = netdev_priv(dev);
7382
7383         /* Calling flush_scheduled_work() may deadlock because
7384          * linkwatch_event() may be on the workqueue and it will try to get
7385          * the rtnl_lock which we are holding.
7386          */
7387         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7388                 msleep(1);
7389
7390         netif_stop_queue(dev);
7391
7392         del_timer_sync(&tp->timer);
7393
7394         tg3_full_lock(tp, 1);
7395 #if 0
7396         tg3_dump_state(tp);
7397 #endif
7398
7399         tg3_disable_ints(tp);
7400
7401         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7402         tg3_free_rings(tp);
7403         tp->tg3_flags &=
7404                 ~(TG3_FLAG_INIT_COMPLETE |
7405                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7406
7407         tg3_full_unlock(tp);
7408
7409         free_irq(tp->pdev->irq, dev);
7410         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7411                 pci_disable_msi(tp->pdev);
7412                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7413         }
7414
7415         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7416                sizeof(tp->net_stats_prev));
7417         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7418                sizeof(tp->estats_prev));
7419
7420         tg3_free_consistent(tp);
7421
7422         tg3_set_power_state(tp, PCI_D3hot);
7423
7424         netif_carrier_off(tp->dev);
7425
7426         return 0;
7427 }
7428
7429 static inline unsigned long get_stat64(tg3_stat64_t *val)
7430 {
7431         unsigned long ret;
7432
7433 #if (BITS_PER_LONG == 32)
7434         ret = val->low;
7435 #else
7436         ret = ((u64)val->high << 32) | ((u64)val->low);
7437 #endif
7438         return ret;
7439 }
7440
7441 static unsigned long calc_crc_errors(struct tg3 *tp)
7442 {
7443         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7444
7445         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7446             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7447              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7448                 u32 val;
7449
7450                 spin_lock_bh(&tp->lock);
7451                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7452                         tg3_writephy(tp, MII_TG3_TEST1,
7453                                      val | MII_TG3_TEST1_CRC_EN);
7454                         tg3_readphy(tp, 0x14, &val);
7455                 } else
7456                         val = 0;
7457                 spin_unlock_bh(&tp->lock);
7458
7459                 tp->phy_crc_errors += val;
7460
7461                 return tp->phy_crc_errors;
7462         }
7463
7464         return get_stat64(&hw_stats->rx_fcs_errors);
7465 }
7466
7467 #define ESTAT_ADD(member) \
7468         estats->member =        old_estats->member + \
7469                                 get_stat64(&hw_stats->member)
7470
7471 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7472 {
7473         struct tg3_ethtool_stats *estats = &tp->estats;
7474         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7475         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7476
7477         if (!hw_stats)
7478                 return old_estats;
7479
7480         ESTAT_ADD(rx_octets);
7481         ESTAT_ADD(rx_fragments);
7482         ESTAT_ADD(rx_ucast_packets);
7483         ESTAT_ADD(rx_mcast_packets);
7484         ESTAT_ADD(rx_bcast_packets);
7485         ESTAT_ADD(rx_fcs_errors);
7486         ESTAT_ADD(rx_align_errors);
7487         ESTAT_ADD(rx_xon_pause_rcvd);
7488         ESTAT_ADD(rx_xoff_pause_rcvd);
7489         ESTAT_ADD(rx_mac_ctrl_rcvd);
7490         ESTAT_ADD(rx_xoff_entered);
7491         ESTAT_ADD(rx_frame_too_long_errors);
7492         ESTAT_ADD(rx_jabbers);
7493         ESTAT_ADD(rx_undersize_packets);
7494         ESTAT_ADD(rx_in_length_errors);
7495         ESTAT_ADD(rx_out_length_errors);
7496         ESTAT_ADD(rx_64_or_less_octet_packets);
7497         ESTAT_ADD(rx_65_to_127_octet_packets);
7498         ESTAT_ADD(rx_128_to_255_octet_packets);
7499         ESTAT_ADD(rx_256_to_511_octet_packets);
7500         ESTAT_ADD(rx_512_to_1023_octet_packets);
7501         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7502         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7503         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7504         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7505         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7506
7507         ESTAT_ADD(tx_octets);
7508         ESTAT_ADD(tx_collisions);
7509         ESTAT_ADD(tx_xon_sent);
7510         ESTAT_ADD(tx_xoff_sent);
7511         ESTAT_ADD(tx_flow_control);
7512         ESTAT_ADD(tx_mac_errors);
7513         ESTAT_ADD(tx_single_collisions);
7514         ESTAT_ADD(tx_mult_collisions);
7515         ESTAT_ADD(tx_deferred);
7516         ESTAT_ADD(tx_excessive_collisions);
7517         ESTAT_ADD(tx_late_collisions);
7518         ESTAT_ADD(tx_collide_2times);
7519         ESTAT_ADD(tx_collide_3times);
7520         ESTAT_ADD(tx_collide_4times);
7521         ESTAT_ADD(tx_collide_5times);
7522         ESTAT_ADD(tx_collide_6times);
7523         ESTAT_ADD(tx_collide_7times);
7524         ESTAT_ADD(tx_collide_8times);
7525         ESTAT_ADD(tx_collide_9times);
7526         ESTAT_ADD(tx_collide_10times);
7527         ESTAT_ADD(tx_collide_11times);
7528         ESTAT_ADD(tx_collide_12times);
7529         ESTAT_ADD(tx_collide_13times);
7530         ESTAT_ADD(tx_collide_14times);
7531         ESTAT_ADD(tx_collide_15times);
7532         ESTAT_ADD(tx_ucast_packets);
7533         ESTAT_ADD(tx_mcast_packets);
7534         ESTAT_ADD(tx_bcast_packets);
7535         ESTAT_ADD(tx_carrier_sense_errors);
7536         ESTAT_ADD(tx_discards);
7537         ESTAT_ADD(tx_errors);
7538
7539         ESTAT_ADD(dma_writeq_full);
7540         ESTAT_ADD(dma_write_prioq_full);
7541         ESTAT_ADD(rxbds_empty);
7542         ESTAT_ADD(rx_discards);
7543         ESTAT_ADD(rx_errors);
7544         ESTAT_ADD(rx_threshold_hit);
7545
7546         ESTAT_ADD(dma_readq_full);
7547         ESTAT_ADD(dma_read_prioq_full);
7548         ESTAT_ADD(tx_comp_queue_full);
7549
7550         ESTAT_ADD(ring_set_send_prod_index);
7551         ESTAT_ADD(ring_status_update);
7552         ESTAT_ADD(nic_irqs);
7553         ESTAT_ADD(nic_avoided_irqs);
7554         ESTAT_ADD(nic_tx_threshold_hit);
7555
7556         return estats;
7557 }
7558
7559 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7560 {
7561         struct tg3 *tp = netdev_priv(dev);
7562         struct net_device_stats *stats = &tp->net_stats;
7563         struct net_device_stats *old_stats = &tp->net_stats_prev;
7564         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7565
7566         if (!hw_stats)
7567                 return old_stats;
7568
7569         stats->rx_packets = old_stats->rx_packets +
7570                 get_stat64(&hw_stats->rx_ucast_packets) +
7571                 get_stat64(&hw_stats->rx_mcast_packets) +
7572                 get_stat64(&hw_stats->rx_bcast_packets);
7573
7574         stats->tx_packets = old_stats->tx_packets +
7575                 get_stat64(&hw_stats->tx_ucast_packets) +
7576                 get_stat64(&hw_stats->tx_mcast_packets) +
7577                 get_stat64(&hw_stats->tx_bcast_packets);
7578
7579         stats->rx_bytes = old_stats->rx_bytes +
7580                 get_stat64(&hw_stats->rx_octets);
7581         stats->tx_bytes = old_stats->tx_bytes +
7582                 get_stat64(&hw_stats->tx_octets);
7583
7584         stats->rx_errors = old_stats->rx_errors +
7585                 get_stat64(&hw_stats->rx_errors);
7586         stats->tx_errors = old_stats->tx_errors +
7587                 get_stat64(&hw_stats->tx_errors) +
7588                 get_stat64(&hw_stats->tx_mac_errors) +
7589                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7590                 get_stat64(&hw_stats->tx_discards);
7591
7592         stats->multicast = old_stats->multicast +
7593                 get_stat64(&hw_stats->rx_mcast_packets);
7594         stats->collisions = old_stats->collisions +
7595                 get_stat64(&hw_stats->tx_collisions);
7596
7597         stats->rx_length_errors = old_stats->rx_length_errors +
7598                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7599                 get_stat64(&hw_stats->rx_undersize_packets);
7600
7601         stats->rx_over_errors = old_stats->rx_over_errors +
7602                 get_stat64(&hw_stats->rxbds_empty);
7603         stats->rx_frame_errors = old_stats->rx_frame_errors +
7604                 get_stat64(&hw_stats->rx_align_errors);
7605         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7606                 get_stat64(&hw_stats->tx_discards);
7607         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7608                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7609
7610         stats->rx_crc_errors = old_stats->rx_crc_errors +
7611                 calc_crc_errors(tp);
7612
7613         stats->rx_missed_errors = old_stats->rx_missed_errors +
7614                 get_stat64(&hw_stats->rx_discards);
7615
7616         return stats;
7617 }
7618
7619 static inline u32 calc_crc(unsigned char *buf, int len)
7620 {
7621         u32 reg;
7622         u32 tmp;
7623         int j, k;
7624
7625         reg = 0xffffffff;
7626
7627         for (j = 0; j < len; j++) {
7628                 reg ^= buf[j];
7629
7630                 for (k = 0; k < 8; k++) {
7631                         tmp = reg & 0x01;
7632
7633                         reg >>= 1;
7634
7635                         if (tmp) {
7636                                 reg ^= 0xedb88320;
7637                         }
7638                 }
7639         }
7640
7641         return ~reg;
7642 }
7643
7644 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7645 {
7646         /* accept or reject all multicast frames */
7647         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7648         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7649         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7650         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7651 }
7652
7653 static void __tg3_set_rx_mode(struct net_device *dev)
7654 {
7655         struct tg3 *tp = netdev_priv(dev);
7656         u32 rx_mode;
7657
7658         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7659                                   RX_MODE_KEEP_VLAN_TAG);
7660
7661         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7662          * flag clear.
7663          */
7664 #if TG3_VLAN_TAG_USED
7665         if (!tp->vlgrp &&
7666             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7667                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7668 #else
7669         /* By definition, VLAN is disabled always in this
7670          * case.
7671          */
7672         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7673                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7674 #endif
7675
7676         if (dev->flags & IFF_PROMISC) {
7677                 /* Promiscuous mode. */
7678                 rx_mode |= RX_MODE_PROMISC;
7679         } else if (dev->flags & IFF_ALLMULTI) {
7680                 /* Accept all multicast. */
7681                 tg3_set_multi (tp, 1);
7682         } else if (dev->mc_count < 1) {
7683                 /* Reject all multicast. */
7684                 tg3_set_multi (tp, 0);
7685         } else {
7686                 /* Accept one or more multicast(s). */
7687                 struct dev_mc_list *mclist;
7688                 unsigned int i;
7689                 u32 mc_filter[4] = { 0, };
7690                 u32 regidx;
7691                 u32 bit;
7692                 u32 crc;
7693
7694                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7695                      i++, mclist = mclist->next) {
7696
7697                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7698                         bit = ~crc & 0x7f;
7699                         regidx = (bit & 0x60) >> 5;
7700                         bit &= 0x1f;
7701                         mc_filter[regidx] |= (1 << bit);
7702                 }
7703
7704                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7705                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7706                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7707                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7708         }
7709
7710         if (rx_mode != tp->rx_mode) {
7711                 tp->rx_mode = rx_mode;
7712                 tw32_f(MAC_RX_MODE, rx_mode);
7713                 udelay(10);
7714         }
7715 }
7716
7717 static void tg3_set_rx_mode(struct net_device *dev)
7718 {
7719         struct tg3 *tp = netdev_priv(dev);
7720
7721         if (!netif_running(dev))
7722                 return;
7723
7724         tg3_full_lock(tp, 0);
7725         __tg3_set_rx_mode(dev);
7726         tg3_full_unlock(tp);
7727 }
7728
7729 #define TG3_REGDUMP_LEN         (32 * 1024)
7730
7731 static int tg3_get_regs_len(struct net_device *dev)
7732 {
7733         return TG3_REGDUMP_LEN;
7734 }
7735
7736 static void tg3_get_regs(struct net_device *dev,
7737                 struct ethtool_regs *regs, void *_p)
7738 {
7739         u32 *p = _p;
7740         struct tg3 *tp = netdev_priv(dev);
7741         u8 *orig_p = _p;
7742         int i;
7743
7744         regs->version = 0;
7745
7746         memset(p, 0, TG3_REGDUMP_LEN);
7747
7748         if (tp->link_config.phy_is_low_power)
7749                 return;
7750
7751         tg3_full_lock(tp, 0);
7752
7753 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7754 #define GET_REG32_LOOP(base,len)                \
7755 do {    p = (u32 *)(orig_p + (base));           \
7756         for (i = 0; i < len; i += 4)            \
7757                 __GET_REG32((base) + i);        \
7758 } while (0)
7759 #define GET_REG32_1(reg)                        \
7760 do {    p = (u32 *)(orig_p + (reg));            \
7761         __GET_REG32((reg));                     \
7762 } while (0)
7763
7764         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7765         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7766         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7767         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7768         GET_REG32_1(SNDDATAC_MODE);
7769         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7770         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7771         GET_REG32_1(SNDBDC_MODE);
7772         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7773         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7774         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7775         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7776         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7777         GET_REG32_1(RCVDCC_MODE);
7778         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7779         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7780         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7781         GET_REG32_1(MBFREE_MODE);
7782         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7783         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7784         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7785         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7786         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7787         GET_REG32_1(RX_CPU_MODE);
7788         GET_REG32_1(RX_CPU_STATE);
7789         GET_REG32_1(RX_CPU_PGMCTR);
7790         GET_REG32_1(RX_CPU_HWBKPT);
7791         GET_REG32_1(TX_CPU_MODE);
7792         GET_REG32_1(TX_CPU_STATE);
7793         GET_REG32_1(TX_CPU_PGMCTR);
7794         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7795         GET_REG32_LOOP(FTQ_RESET, 0x120);
7796         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7797         GET_REG32_1(DMAC_MODE);
7798         GET_REG32_LOOP(GRC_MODE, 0x4c);
7799         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7800                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7801
7802 #undef __GET_REG32
7803 #undef GET_REG32_LOOP
7804 #undef GET_REG32_1
7805
7806         tg3_full_unlock(tp);
7807 }
7808
7809 static int tg3_get_eeprom_len(struct net_device *dev)
7810 {
7811         struct tg3 *tp = netdev_priv(dev);
7812
7813         return tp->nvram_size;
7814 }
7815
7816 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7817 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7818
7819 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7820 {
7821         struct tg3 *tp = netdev_priv(dev);
7822         int ret;
7823         u8  *pd;
7824         u32 i, offset, len, val, b_offset, b_count;
7825
7826         if (tp->link_config.phy_is_low_power)
7827                 return -EAGAIN;
7828
7829         offset = eeprom->offset;
7830         len = eeprom->len;
7831         eeprom->len = 0;
7832
7833         eeprom->magic = TG3_EEPROM_MAGIC;
7834
7835         if (offset & 3) {
7836                 /* adjustments to start on required 4 byte boundary */
7837                 b_offset = offset & 3;
7838                 b_count = 4 - b_offset;
7839                 if (b_count > len) {
7840                         /* i.e. offset=1 len=2 */
7841                         b_count = len;
7842                 }
7843                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7844                 if (ret)
7845                         return ret;
7846                 val = cpu_to_le32(val);
7847                 memcpy(data, ((char*)&val) + b_offset, b_count);
7848                 len -= b_count;
7849                 offset += b_count;
7850                 eeprom->len += b_count;
7851         }
7852
7853         /* read bytes upto the last 4 byte boundary */
7854         pd = &data[eeprom->len];
7855         for (i = 0; i < (len - (len & 3)); i += 4) {
7856                 ret = tg3_nvram_read(tp, offset + i, &val);
7857                 if (ret) {
7858                         eeprom->len += i;
7859                         return ret;
7860                 }
7861                 val = cpu_to_le32(val);
7862                 memcpy(pd + i, &val, 4);
7863         }
7864         eeprom->len += i;
7865
7866         if (len & 3) {
7867                 /* read last bytes not ending on 4 byte boundary */
7868                 pd = &data[eeprom->len];
7869                 b_count = len & 3;
7870                 b_offset = offset + len - b_count;
7871                 ret = tg3_nvram_read(tp, b_offset, &val);
7872                 if (ret)
7873                         return ret;
7874                 val = cpu_to_le32(val);
7875                 memcpy(pd, ((char*)&val), b_count);
7876                 eeprom->len += b_count;
7877         }
7878         return 0;
7879 }
7880
7881 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7882
7883 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7884 {
7885         struct tg3 *tp = netdev_priv(dev);
7886         int ret;
7887         u32 offset, len, b_offset, odd_len, start, end;
7888         u8 *buf;
7889
7890         if (tp->link_config.phy_is_low_power)
7891                 return -EAGAIN;
7892
7893         if (eeprom->magic != TG3_EEPROM_MAGIC)
7894                 return -EINVAL;
7895
7896         offset = eeprom->offset;
7897         len = eeprom->len;
7898
7899         if ((b_offset = (offset & 3))) {
7900                 /* adjustments to start on required 4 byte boundary */
7901                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7902                 if (ret)
7903                         return ret;
7904                 start = cpu_to_le32(start);
7905                 len += b_offset;
7906                 offset &= ~3;
7907                 if (len < 4)
7908                         len = 4;
7909         }
7910
7911         odd_len = 0;
7912         if (len & 3) {
7913                 /* adjustments to end on required 4 byte boundary */
7914                 odd_len = 1;
7915                 len = (len + 3) & ~3;
7916                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7917                 if (ret)
7918                         return ret;
7919                 end = cpu_to_le32(end);
7920         }
7921
7922         buf = data;
7923         if (b_offset || odd_len) {
7924                 buf = kmalloc(len, GFP_KERNEL);
7925                 if (buf == 0)
7926                         return -ENOMEM;
7927                 if (b_offset)
7928                         memcpy(buf, &start, 4);
7929                 if (odd_len)
7930                         memcpy(buf+len-4, &end, 4);
7931                 memcpy(buf + b_offset, data, eeprom->len);
7932         }
7933
7934         ret = tg3_nvram_write_block(tp, offset, len, buf);
7935
7936         if (buf != data)
7937                 kfree(buf);
7938
7939         return ret;
7940 }
7941
7942 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7943 {
7944         struct tg3 *tp = netdev_priv(dev);
7945
7946         cmd->supported = (SUPPORTED_Autoneg);
7947
7948         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7949                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7950                                    SUPPORTED_1000baseT_Full);
7951
7952         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7953                 cmd->supported |= (SUPPORTED_100baseT_Half |
7954                                   SUPPORTED_100baseT_Full |
7955                                   SUPPORTED_10baseT_Half |
7956                                   SUPPORTED_10baseT_Full |
7957                                   SUPPORTED_MII);
7958                 cmd->port = PORT_TP;
7959         } else {
7960                 cmd->supported |= SUPPORTED_FIBRE;
7961                 cmd->port = PORT_FIBRE;
7962         }
7963
7964         cmd->advertising = tp->link_config.advertising;
7965         if (netif_running(dev)) {
7966                 cmd->speed = tp->link_config.active_speed;
7967                 cmd->duplex = tp->link_config.active_duplex;
7968         }
7969         cmd->phy_address = PHY_ADDR;
7970         cmd->transceiver = 0;
7971         cmd->autoneg = tp->link_config.autoneg;
7972         cmd->maxtxpkt = 0;
7973         cmd->maxrxpkt = 0;
7974         return 0;
7975 }
7976
7977 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7978 {
7979         struct tg3 *tp = netdev_priv(dev);
7980
7981         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7982                 /* These are the only valid advertisement bits allowed.  */
7983                 if (cmd->autoneg == AUTONEG_ENABLE &&
7984                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7985                                           ADVERTISED_1000baseT_Full |
7986                                           ADVERTISED_Autoneg |
7987                                           ADVERTISED_FIBRE)))
7988                         return -EINVAL;
7989                 /* Fiber can only do SPEED_1000.  */
7990                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7991                          (cmd->speed != SPEED_1000))
7992                         return -EINVAL;
7993         /* Copper cannot force SPEED_1000.  */
7994         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7995                    (cmd->speed == SPEED_1000))
7996                 return -EINVAL;
7997         else if ((cmd->speed == SPEED_1000) &&
7998                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7999                 return -EINVAL;
8000
8001         tg3_full_lock(tp, 0);
8002
8003         tp->link_config.autoneg = cmd->autoneg;
8004         if (cmd->autoneg == AUTONEG_ENABLE) {
8005                 tp->link_config.advertising = cmd->advertising;
8006                 tp->link_config.speed = SPEED_INVALID;
8007                 tp->link_config.duplex = DUPLEX_INVALID;
8008         } else {
8009                 tp->link_config.advertising = 0;
8010                 tp->link_config.speed = cmd->speed;
8011                 tp->link_config.duplex = cmd->duplex;
8012         }
8013
8014         tp->link_config.orig_speed = tp->link_config.speed;
8015         tp->link_config.orig_duplex = tp->link_config.duplex;
8016         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8017
8018         if (netif_running(dev))
8019                 tg3_setup_phy(tp, 1);
8020
8021         tg3_full_unlock(tp);
8022
8023         return 0;
8024 }
8025
8026 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8027 {
8028         struct tg3 *tp = netdev_priv(dev);
8029
8030         strcpy(info->driver, DRV_MODULE_NAME);
8031         strcpy(info->version, DRV_MODULE_VERSION);
8032         strcpy(info->fw_version, tp->fw_ver);
8033         strcpy(info->bus_info, pci_name(tp->pdev));
8034 }
8035
8036 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8037 {
8038         struct tg3 *tp = netdev_priv(dev);
8039
8040         wol->supported = WAKE_MAGIC;
8041         wol->wolopts = 0;
8042         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8043                 wol->wolopts = WAKE_MAGIC;
8044         memset(&wol->sopass, 0, sizeof(wol->sopass));
8045 }
8046
8047 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8048 {
8049         struct tg3 *tp = netdev_priv(dev);
8050
8051         if (wol->wolopts & ~WAKE_MAGIC)
8052                 return -EINVAL;
8053         if ((wol->wolopts & WAKE_MAGIC) &&
8054             tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
8055             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8056                 return -EINVAL;
8057
8058         spin_lock_bh(&tp->lock);
8059         if (wol->wolopts & WAKE_MAGIC)
8060                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8061         else
8062                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8063         spin_unlock_bh(&tp->lock);
8064
8065         return 0;
8066 }
8067
8068 static u32 tg3_get_msglevel(struct net_device *dev)
8069 {
8070         struct tg3 *tp = netdev_priv(dev);
8071         return tp->msg_enable;
8072 }
8073
8074 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8075 {
8076         struct tg3 *tp = netdev_priv(dev);
8077         tp->msg_enable = value;
8078 }
8079
8080 static int tg3_set_tso(struct net_device *dev, u32 value)
8081 {
8082         struct tg3 *tp = netdev_priv(dev);
8083
8084         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8085                 if (value)
8086                         return -EINVAL;
8087                 return 0;
8088         }
8089         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8090             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8091                 if (value)
8092                         dev->features |= NETIF_F_TSO6;
8093                 else
8094                         dev->features &= ~NETIF_F_TSO6;
8095         }
8096         return ethtool_op_set_tso(dev, value);
8097 }
8098
8099 static int tg3_nway_reset(struct net_device *dev)
8100 {
8101         struct tg3 *tp = netdev_priv(dev);
8102         u32 bmcr;
8103         int r;
8104
8105         if (!netif_running(dev))
8106                 return -EAGAIN;
8107
8108         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8109                 return -EINVAL;
8110
8111         spin_lock_bh(&tp->lock);
8112         r = -EINVAL;
8113         tg3_readphy(tp, MII_BMCR, &bmcr);
8114         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8115             ((bmcr & BMCR_ANENABLE) ||
8116              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8117                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8118                                            BMCR_ANENABLE);
8119                 r = 0;
8120         }
8121         spin_unlock_bh(&tp->lock);
8122
8123         return r;
8124 }
8125
8126 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8127 {
8128         struct tg3 *tp = netdev_priv(dev);
8129
8130         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8131         ering->rx_mini_max_pending = 0;
8132         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8133                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8134         else
8135                 ering->rx_jumbo_max_pending = 0;
8136
8137         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8138
8139         ering->rx_pending = tp->rx_pending;
8140         ering->rx_mini_pending = 0;
8141         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8142                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8143         else
8144                 ering->rx_jumbo_pending = 0;
8145
8146         ering->tx_pending = tp->tx_pending;
8147 }
8148
8149 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8150 {
8151         struct tg3 *tp = netdev_priv(dev);
8152         int irq_sync = 0, err = 0;
8153
8154         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8155             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8156             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8157             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8158             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8159              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8160                 return -EINVAL;
8161
8162         if (netif_running(dev)) {
8163                 tg3_netif_stop(tp);
8164                 irq_sync = 1;
8165         }
8166
8167         tg3_full_lock(tp, irq_sync);
8168
8169         tp->rx_pending = ering->rx_pending;
8170
8171         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8172             tp->rx_pending > 63)
8173                 tp->rx_pending = 63;
8174         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8175         tp->tx_pending = ering->tx_pending;
8176
8177         if (netif_running(dev)) {
8178                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8179                 err = tg3_restart_hw(tp, 1);
8180                 if (!err)
8181                         tg3_netif_start(tp);
8182         }
8183
8184         tg3_full_unlock(tp);
8185
8186         return err;
8187 }
8188
8189 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8190 {
8191         struct tg3 *tp = netdev_priv(dev);
8192
8193         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8194         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8195         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8196 }
8197
8198 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8199 {
8200         struct tg3 *tp = netdev_priv(dev);
8201         int irq_sync = 0, err = 0;
8202
8203         if (netif_running(dev)) {
8204                 tg3_netif_stop(tp);
8205                 irq_sync = 1;
8206         }
8207
8208         tg3_full_lock(tp, irq_sync);
8209
8210         if (epause->autoneg)
8211                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8212         else
8213                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8214         if (epause->rx_pause)
8215                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8216         else
8217                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8218         if (epause->tx_pause)
8219                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8220         else
8221                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8222
8223         if (netif_running(dev)) {
8224                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8225                 err = tg3_restart_hw(tp, 1);
8226                 if (!err)
8227                         tg3_netif_start(tp);
8228         }
8229
8230         tg3_full_unlock(tp);
8231
8232         return err;
8233 }
8234
8235 static u32 tg3_get_rx_csum(struct net_device *dev)
8236 {
8237         struct tg3 *tp = netdev_priv(dev);
8238         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8239 }
8240
8241 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8242 {
8243         struct tg3 *tp = netdev_priv(dev);
8244
8245         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8246                 if (data != 0)
8247                         return -EINVAL;
8248                 return 0;
8249         }
8250
8251         spin_lock_bh(&tp->lock);
8252         if (data)
8253                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8254         else
8255                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8256         spin_unlock_bh(&tp->lock);
8257
8258         return 0;
8259 }
8260
8261 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8262 {
8263         struct tg3 *tp = netdev_priv(dev);
8264
8265         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8266                 if (data != 0)
8267                         return -EINVAL;
8268                 return 0;
8269         }
8270
8271         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8272             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8273                 ethtool_op_set_tx_hw_csum(dev, data);
8274         else
8275                 ethtool_op_set_tx_csum(dev, data);
8276
8277         return 0;
8278 }
8279
8280 static int tg3_get_stats_count (struct net_device *dev)
8281 {
8282         return TG3_NUM_STATS;
8283 }
8284
8285 static int tg3_get_test_count (struct net_device *dev)
8286 {
8287         return TG3_NUM_TEST;
8288 }
8289
8290 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8291 {
8292         switch (stringset) {
8293         case ETH_SS_STATS:
8294                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8295                 break;
8296         case ETH_SS_TEST:
8297                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8298                 break;
8299         default:
8300                 WARN_ON(1);     /* we need a WARN() */
8301                 break;
8302         }
8303 }
8304
8305 static int tg3_phys_id(struct net_device *dev, u32 data)
8306 {
8307         struct tg3 *tp = netdev_priv(dev);
8308         int i;
8309
8310         if (!netif_running(tp->dev))
8311                 return -EAGAIN;
8312
8313         if (data == 0)
8314                 data = 2;
8315
8316         for (i = 0; i < (data * 2); i++) {
8317                 if ((i % 2) == 0)
8318                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8319                                            LED_CTRL_1000MBPS_ON |
8320                                            LED_CTRL_100MBPS_ON |
8321                                            LED_CTRL_10MBPS_ON |
8322                                            LED_CTRL_TRAFFIC_OVERRIDE |
8323                                            LED_CTRL_TRAFFIC_BLINK |
8324                                            LED_CTRL_TRAFFIC_LED);
8325
8326                 else
8327                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8328                                            LED_CTRL_TRAFFIC_OVERRIDE);
8329
8330                 if (msleep_interruptible(500))
8331                         break;
8332         }
8333         tw32(MAC_LED_CTRL, tp->led_ctrl);
8334         return 0;
8335 }
8336
8337 static void tg3_get_ethtool_stats (struct net_device *dev,
8338                                    struct ethtool_stats *estats, u64 *tmp_stats)
8339 {
8340         struct tg3 *tp = netdev_priv(dev);
8341         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8342 }
8343
8344 #define NVRAM_TEST_SIZE 0x100
8345 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8346 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8347 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8348
8349 static int tg3_test_nvram(struct tg3 *tp)
8350 {
8351         u32 *buf, csum, magic;
8352         int i, j, err = 0, size;
8353
8354         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8355                 return -EIO;
8356
8357         if (magic == TG3_EEPROM_MAGIC)
8358                 size = NVRAM_TEST_SIZE;
8359         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8360                 if ((magic & 0xe00000) == 0x200000)
8361                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8362                 else
8363                         return 0;
8364         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8365                 size = NVRAM_SELFBOOT_HW_SIZE;
8366         else
8367                 return -EIO;
8368
8369         buf = kmalloc(size, GFP_KERNEL);
8370         if (buf == NULL)
8371                 return -ENOMEM;
8372
8373         err = -EIO;
8374         for (i = 0, j = 0; i < size; i += 4, j++) {
8375                 u32 val;
8376
8377                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8378                         break;
8379                 buf[j] = cpu_to_le32(val);
8380         }
8381         if (i < size)
8382                 goto out;
8383
8384         /* Selfboot format */
8385         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8386             TG3_EEPROM_MAGIC_FW) {
8387                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8388
8389                 for (i = 0; i < size; i++)
8390                         csum8 += buf8[i];
8391
8392                 if (csum8 == 0) {
8393                         err = 0;
8394                         goto out;
8395                 }
8396
8397                 err = -EIO;
8398                 goto out;
8399         }
8400
8401         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8402             TG3_EEPROM_MAGIC_HW) {
8403                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8404                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8405                 u8 *buf8 = (u8 *) buf;
8406                 int j, k;
8407
8408                 /* Separate the parity bits and the data bytes.  */
8409                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8410                         if ((i == 0) || (i == 8)) {
8411                                 int l;
8412                                 u8 msk;
8413
8414                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8415                                         parity[k++] = buf8[i] & msk;
8416                                 i++;
8417                         }
8418                         else if (i == 16) {
8419                                 int l;
8420                                 u8 msk;
8421
8422                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8423                                         parity[k++] = buf8[i] & msk;
8424                                 i++;
8425
8426                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8427                                         parity[k++] = buf8[i] & msk;
8428                                 i++;
8429                         }
8430                         data[j++] = buf8[i];
8431                 }
8432
8433                 err = -EIO;
8434                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8435                         u8 hw8 = hweight8(data[i]);
8436
8437                         if ((hw8 & 0x1) && parity[i])
8438                                 goto out;
8439                         else if (!(hw8 & 0x1) && !parity[i])
8440                                 goto out;
8441                 }
8442                 err = 0;
8443                 goto out;
8444         }
8445
8446         /* Bootstrap checksum at offset 0x10 */
8447         csum = calc_crc((unsigned char *) buf, 0x10);
8448         if(csum != cpu_to_le32(buf[0x10/4]))
8449                 goto out;
8450
8451         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8452         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8453         if (csum != cpu_to_le32(buf[0xfc/4]))
8454                  goto out;
8455
8456         err = 0;
8457
8458 out:
8459         kfree(buf);
8460         return err;
8461 }
8462
8463 #define TG3_SERDES_TIMEOUT_SEC  2
8464 #define TG3_COPPER_TIMEOUT_SEC  6
8465
8466 static int tg3_test_link(struct tg3 *tp)
8467 {
8468         int i, max;
8469
8470         if (!netif_running(tp->dev))
8471                 return -ENODEV;
8472
8473         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8474                 max = TG3_SERDES_TIMEOUT_SEC;
8475         else
8476                 max = TG3_COPPER_TIMEOUT_SEC;
8477
8478         for (i = 0; i < max; i++) {
8479                 if (netif_carrier_ok(tp->dev))
8480                         return 0;
8481
8482                 if (msleep_interruptible(1000))
8483                         break;
8484         }
8485
8486         return -EIO;
8487 }
8488
8489 /* Only test the commonly used registers */
8490 static int tg3_test_registers(struct tg3 *tp)
8491 {
8492         int i, is_5705, is_5750;
8493         u32 offset, read_mask, write_mask, val, save_val, read_val;
8494         static struct {
8495                 u16 offset;
8496                 u16 flags;
8497 #define TG3_FL_5705     0x1
8498 #define TG3_FL_NOT_5705 0x2
8499 #define TG3_FL_NOT_5788 0x4
8500 #define TG3_FL_NOT_5750 0x8
8501                 u32 read_mask;
8502                 u32 write_mask;
8503         } reg_tbl[] = {
8504                 /* MAC Control Registers */
8505                 { MAC_MODE, TG3_FL_NOT_5705,
8506                         0x00000000, 0x00ef6f8c },
8507                 { MAC_MODE, TG3_FL_5705,
8508                         0x00000000, 0x01ef6b8c },
8509                 { MAC_STATUS, TG3_FL_NOT_5705,
8510                         0x03800107, 0x00000000 },
8511                 { MAC_STATUS, TG3_FL_5705,
8512                         0x03800100, 0x00000000 },
8513                 { MAC_ADDR_0_HIGH, 0x0000,
8514                         0x00000000, 0x0000ffff },
8515                 { MAC_ADDR_0_LOW, 0x0000,
8516                         0x00000000, 0xffffffff },
8517                 { MAC_RX_MTU_SIZE, 0x0000,
8518                         0x00000000, 0x0000ffff },
8519                 { MAC_TX_MODE, 0x0000,
8520                         0x00000000, 0x00000070 },
8521                 { MAC_TX_LENGTHS, 0x0000,
8522                         0x00000000, 0x00003fff },
8523                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8524                         0x00000000, 0x000007fc },
8525                 { MAC_RX_MODE, TG3_FL_5705,
8526                         0x00000000, 0x000007dc },
8527                 { MAC_HASH_REG_0, 0x0000,
8528                         0x00000000, 0xffffffff },
8529                 { MAC_HASH_REG_1, 0x0000,
8530                         0x00000000, 0xffffffff },
8531                 { MAC_HASH_REG_2, 0x0000,
8532                         0x00000000, 0xffffffff },
8533                 { MAC_HASH_REG_3, 0x0000,
8534                         0x00000000, 0xffffffff },
8535
8536                 /* Receive Data and Receive BD Initiator Control Registers. */
8537                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8538                         0x00000000, 0xffffffff },
8539                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8540                         0x00000000, 0xffffffff },
8541                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8542                         0x00000000, 0x00000003 },
8543                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8544                         0x00000000, 0xffffffff },
8545                 { RCVDBDI_STD_BD+0, 0x0000,
8546                         0x00000000, 0xffffffff },
8547                 { RCVDBDI_STD_BD+4, 0x0000,
8548                         0x00000000, 0xffffffff },
8549                 { RCVDBDI_STD_BD+8, 0x0000,
8550                         0x00000000, 0xffff0002 },
8551                 { RCVDBDI_STD_BD+0xc, 0x0000,
8552                         0x00000000, 0xffffffff },
8553
8554                 /* Receive BD Initiator Control Registers. */
8555                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8556                         0x00000000, 0xffffffff },
8557                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8558                         0x00000000, 0x000003ff },
8559                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8560                         0x00000000, 0xffffffff },
8561
8562                 /* Host Coalescing Control Registers. */
8563                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8564                         0x00000000, 0x00000004 },
8565                 { HOSTCC_MODE, TG3_FL_5705,
8566                         0x00000000, 0x000000f6 },
8567                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8568                         0x00000000, 0xffffffff },
8569                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8570                         0x00000000, 0x000003ff },
8571                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8572                         0x00000000, 0xffffffff },
8573                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8574                         0x00000000, 0x000003ff },
8575                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8576                         0x00000000, 0xffffffff },
8577                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8578                         0x00000000, 0x000000ff },
8579                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8580                         0x00000000, 0xffffffff },
8581                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8582                         0x00000000, 0x000000ff },
8583                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8584                         0x00000000, 0xffffffff },
8585                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8586                         0x00000000, 0xffffffff },
8587                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8588                         0x00000000, 0xffffffff },
8589                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8590                         0x00000000, 0x000000ff },
8591                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8592                         0x00000000, 0xffffffff },
8593                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8594                         0x00000000, 0x000000ff },
8595                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8596                         0x00000000, 0xffffffff },
8597                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8598                         0x00000000, 0xffffffff },
8599                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8600                         0x00000000, 0xffffffff },
8601                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8602                         0x00000000, 0xffffffff },
8603                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8604                         0x00000000, 0xffffffff },
8605                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8606                         0xffffffff, 0x00000000 },
8607                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8608                         0xffffffff, 0x00000000 },
8609
8610                 /* Buffer Manager Control Registers. */
8611                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8612                         0x00000000, 0x007fff80 },
8613                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8614                         0x00000000, 0x007fffff },
8615                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8616                         0x00000000, 0x0000003f },
8617                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8618                         0x00000000, 0x000001ff },
8619                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8620                         0x00000000, 0x000001ff },
8621                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8622                         0xffffffff, 0x00000000 },
8623                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8624                         0xffffffff, 0x00000000 },
8625
8626                 /* Mailbox Registers */
8627                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8628                         0x00000000, 0x000001ff },
8629                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8630                         0x00000000, 0x000001ff },
8631                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8632                         0x00000000, 0x000007ff },
8633                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8634                         0x00000000, 0x000001ff },
8635
8636                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8637         };
8638
8639         is_5705 = is_5750 = 0;
8640         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8641                 is_5705 = 1;
8642                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8643                         is_5750 = 1;
8644         }
8645
8646         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8647                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8648                         continue;
8649
8650                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8651                         continue;
8652
8653                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8654                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8655                         continue;
8656
8657                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8658                         continue;
8659
8660                 offset = (u32) reg_tbl[i].offset;
8661                 read_mask = reg_tbl[i].read_mask;
8662                 write_mask = reg_tbl[i].write_mask;
8663
8664                 /* Save the original register content */
8665                 save_val = tr32(offset);
8666
8667                 /* Determine the read-only value. */
8668                 read_val = save_val & read_mask;
8669
8670                 /* Write zero to the register, then make sure the read-only bits
8671                  * are not changed and the read/write bits are all zeros.
8672                  */
8673                 tw32(offset, 0);
8674
8675                 val = tr32(offset);
8676
8677                 /* Test the read-only and read/write bits. */
8678                 if (((val & read_mask) != read_val) || (val & write_mask))
8679                         goto out;
8680
8681                 /* Write ones to all the bits defined by RdMask and WrMask, then
8682                  * make sure the read-only bits are not changed and the
8683                  * read/write bits are all ones.
8684                  */
8685                 tw32(offset, read_mask | write_mask);
8686
8687                 val = tr32(offset);
8688
8689                 /* Test the read-only bits. */
8690                 if ((val & read_mask) != read_val)
8691                         goto out;
8692
8693                 /* Test the read/write bits. */
8694                 if ((val & write_mask) != write_mask)
8695                         goto out;
8696
8697                 tw32(offset, save_val);
8698         }
8699
8700         return 0;
8701
8702 out:
8703         if (netif_msg_hw(tp))
8704                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8705                        offset);
8706         tw32(offset, save_val);
8707         return -EIO;
8708 }
8709
8710 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8711 {
8712         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8713         int i;
8714         u32 j;
8715
8716         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8717                 for (j = 0; j < len; j += 4) {
8718                         u32 val;
8719
8720                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8721                         tg3_read_mem(tp, offset + j, &val);
8722                         if (val != test_pattern[i])
8723                                 return -EIO;
8724                 }
8725         }
8726         return 0;
8727 }
8728
8729 static int tg3_test_memory(struct tg3 *tp)
8730 {
8731         static struct mem_entry {
8732                 u32 offset;
8733                 u32 len;
8734         } mem_tbl_570x[] = {
8735                 { 0x00000000, 0x00b50},
8736                 { 0x00002000, 0x1c000},
8737                 { 0xffffffff, 0x00000}
8738         }, mem_tbl_5705[] = {
8739                 { 0x00000100, 0x0000c},
8740                 { 0x00000200, 0x00008},
8741                 { 0x00004000, 0x00800},
8742                 { 0x00006000, 0x01000},
8743                 { 0x00008000, 0x02000},
8744                 { 0x00010000, 0x0e000},
8745                 { 0xffffffff, 0x00000}
8746         }, mem_tbl_5755[] = {
8747                 { 0x00000200, 0x00008},
8748                 { 0x00004000, 0x00800},
8749                 { 0x00006000, 0x00800},
8750                 { 0x00008000, 0x02000},
8751                 { 0x00010000, 0x0c000},
8752                 { 0xffffffff, 0x00000}
8753         }, mem_tbl_5906[] = {
8754                 { 0x00000200, 0x00008},
8755                 { 0x00004000, 0x00400},
8756                 { 0x00006000, 0x00400},
8757                 { 0x00008000, 0x01000},
8758                 { 0x00010000, 0x01000},
8759                 { 0xffffffff, 0x00000}
8760         };
8761         struct mem_entry *mem_tbl;
8762         int err = 0;
8763         int i;
8764
8765         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8766                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8767                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8768                         mem_tbl = mem_tbl_5755;
8769                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8770                         mem_tbl = mem_tbl_5906;
8771                 else
8772                         mem_tbl = mem_tbl_5705;
8773         } else
8774                 mem_tbl = mem_tbl_570x;
8775
8776         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8777                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8778                     mem_tbl[i].len)) != 0)
8779                         break;
8780         }
8781
8782         return err;
8783 }
8784
8785 #define TG3_MAC_LOOPBACK        0
8786 #define TG3_PHY_LOOPBACK        1
8787
8788 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8789 {
8790         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8791         u32 desc_idx;
8792         struct sk_buff *skb, *rx_skb;
8793         u8 *tx_data;
8794         dma_addr_t map;
8795         int num_pkts, tx_len, rx_len, i, err;
8796         struct tg3_rx_buffer_desc *desc;
8797
8798         if (loopback_mode == TG3_MAC_LOOPBACK) {
8799                 /* HW errata - mac loopback fails in some cases on 5780.
8800                  * Normal traffic and PHY loopback are not affected by
8801                  * errata.
8802                  */
8803                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8804                         return 0;
8805
8806                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8807                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8808                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8809                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8810                 else
8811                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8812                 tw32(MAC_MODE, mac_mode);
8813         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8814                 u32 val;
8815
8816                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8817                         u32 phytest;
8818
8819                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8820                                 u32 phy;
8821
8822                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8823                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8824                                 if (!tg3_readphy(tp, 0x1b, &phy))
8825                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8826                                 if (!tg3_readphy(tp, 0x10, &phy))
8827                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
8828                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8829                         }
8830                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8831                 } else
8832                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8833
8834                 tg3_writephy(tp, MII_BMCR, val);
8835                 udelay(40);
8836
8837                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8838                            MAC_MODE_LINK_POLARITY;
8839                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8840                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8841                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8842                 } else
8843                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8844
8845                 /* reset to prevent losing 1st rx packet intermittently */
8846                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8847                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8848                         udelay(10);
8849                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8850                 }
8851                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8852                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8853                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8854                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8855                 }
8856                 tw32(MAC_MODE, mac_mode);
8857         }
8858         else
8859                 return -EINVAL;
8860
8861         err = -EIO;
8862
8863         tx_len = 1514;
8864         skb = netdev_alloc_skb(tp->dev, tx_len);
8865         if (!skb)
8866                 return -ENOMEM;
8867
8868         tx_data = skb_put(skb, tx_len);
8869         memcpy(tx_data, tp->dev->dev_addr, 6);
8870         memset(tx_data + 6, 0x0, 8);
8871
8872         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8873
8874         for (i = 14; i < tx_len; i++)
8875                 tx_data[i] = (u8) (i & 0xff);
8876
8877         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8878
8879         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8880              HOSTCC_MODE_NOW);
8881
8882         udelay(10);
8883
8884         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8885
8886         num_pkts = 0;
8887
8888         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8889
8890         tp->tx_prod++;
8891         num_pkts++;
8892
8893         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8894                      tp->tx_prod);
8895         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8896
8897         udelay(10);
8898
8899         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8900         for (i = 0; i < 25; i++) {
8901                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8902                        HOSTCC_MODE_NOW);
8903
8904                 udelay(10);
8905
8906                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8907                 rx_idx = tp->hw_status->idx[0].rx_producer;
8908                 if ((tx_idx == tp->tx_prod) &&
8909                     (rx_idx == (rx_start_idx + num_pkts)))
8910                         break;
8911         }
8912
8913         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8914         dev_kfree_skb(skb);
8915
8916         if (tx_idx != tp->tx_prod)
8917                 goto out;
8918
8919         if (rx_idx != rx_start_idx + num_pkts)
8920                 goto out;
8921
8922         desc = &tp->rx_rcb[rx_start_idx];
8923         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8924         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8925         if (opaque_key != RXD_OPAQUE_RING_STD)
8926                 goto out;
8927
8928         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8929             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8930                 goto out;
8931
8932         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8933         if (rx_len != tx_len)
8934                 goto out;
8935
8936         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8937
8938         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8939         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8940
8941         for (i = 14; i < tx_len; i++) {
8942                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8943                         goto out;
8944         }
8945         err = 0;
8946
8947         /* tg3_free_rings will unmap and free the rx_skb */
8948 out:
8949         return err;
8950 }
8951
8952 #define TG3_MAC_LOOPBACK_FAILED         1
8953 #define TG3_PHY_LOOPBACK_FAILED         2
8954 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8955                                          TG3_PHY_LOOPBACK_FAILED)
8956
8957 static int tg3_test_loopback(struct tg3 *tp)
8958 {
8959         int err = 0;
8960
8961         if (!netif_running(tp->dev))
8962                 return TG3_LOOPBACK_FAILED;
8963
8964         err = tg3_reset_hw(tp, 1);
8965         if (err)
8966                 return TG3_LOOPBACK_FAILED;
8967
8968         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8969                 err |= TG3_MAC_LOOPBACK_FAILED;
8970         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8971                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8972                         err |= TG3_PHY_LOOPBACK_FAILED;
8973         }
8974
8975         return err;
8976 }
8977
8978 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8979                           u64 *data)
8980 {
8981         struct tg3 *tp = netdev_priv(dev);
8982
8983         if (tp->link_config.phy_is_low_power)
8984                 tg3_set_power_state(tp, PCI_D0);
8985
8986         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8987
8988         if (tg3_test_nvram(tp) != 0) {
8989                 etest->flags |= ETH_TEST_FL_FAILED;
8990                 data[0] = 1;
8991         }
8992         if (tg3_test_link(tp) != 0) {
8993                 etest->flags |= ETH_TEST_FL_FAILED;
8994                 data[1] = 1;
8995         }
8996         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8997                 int err, irq_sync = 0;
8998
8999                 if (netif_running(dev)) {
9000                         tg3_netif_stop(tp);
9001                         irq_sync = 1;
9002                 }
9003
9004                 tg3_full_lock(tp, irq_sync);
9005
9006                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9007                 err = tg3_nvram_lock(tp);
9008                 tg3_halt_cpu(tp, RX_CPU_BASE);
9009                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9010                         tg3_halt_cpu(tp, TX_CPU_BASE);
9011                 if (!err)
9012                         tg3_nvram_unlock(tp);
9013
9014                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9015                         tg3_phy_reset(tp);
9016
9017                 if (tg3_test_registers(tp) != 0) {
9018                         etest->flags |= ETH_TEST_FL_FAILED;
9019                         data[2] = 1;
9020                 }
9021                 if (tg3_test_memory(tp) != 0) {
9022                         etest->flags |= ETH_TEST_FL_FAILED;
9023                         data[3] = 1;
9024                 }
9025                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9026                         etest->flags |= ETH_TEST_FL_FAILED;
9027
9028                 tg3_full_unlock(tp);
9029
9030                 if (tg3_test_interrupt(tp) != 0) {
9031                         etest->flags |= ETH_TEST_FL_FAILED;
9032                         data[5] = 1;
9033                 }
9034
9035                 tg3_full_lock(tp, 0);
9036
9037                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9038                 if (netif_running(dev)) {
9039                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9040                         if (!tg3_restart_hw(tp, 1))
9041                                 tg3_netif_start(tp);
9042                 }
9043
9044                 tg3_full_unlock(tp);
9045         }
9046         if (tp->link_config.phy_is_low_power)
9047                 tg3_set_power_state(tp, PCI_D3hot);
9048
9049 }
9050
9051 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9052 {
9053         struct mii_ioctl_data *data = if_mii(ifr);
9054         struct tg3 *tp = netdev_priv(dev);
9055         int err;
9056
9057         switch(cmd) {
9058         case SIOCGMIIPHY:
9059                 data->phy_id = PHY_ADDR;
9060
9061                 /* fallthru */
9062         case SIOCGMIIREG: {
9063                 u32 mii_regval;
9064
9065                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9066                         break;                  /* We have no PHY */
9067
9068                 if (tp->link_config.phy_is_low_power)
9069                         return -EAGAIN;
9070
9071                 spin_lock_bh(&tp->lock);
9072                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9073                 spin_unlock_bh(&tp->lock);
9074
9075                 data->val_out = mii_regval;
9076
9077                 return err;
9078         }
9079
9080         case SIOCSMIIREG:
9081                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9082                         break;                  /* We have no PHY */
9083
9084                 if (!capable(CAP_NET_ADMIN))
9085                         return -EPERM;
9086
9087                 if (tp->link_config.phy_is_low_power)
9088                         return -EAGAIN;
9089
9090                 spin_lock_bh(&tp->lock);
9091                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9092                 spin_unlock_bh(&tp->lock);
9093
9094                 return err;
9095
9096         default:
9097                 /* do nothing */
9098                 break;
9099         }
9100         return -EOPNOTSUPP;
9101 }
9102
9103 #if TG3_VLAN_TAG_USED
9104 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9105 {
9106         struct tg3 *tp = netdev_priv(dev);
9107
9108         if (netif_running(dev))
9109                 tg3_netif_stop(tp);
9110
9111         tg3_full_lock(tp, 0);
9112
9113         tp->vlgrp = grp;
9114
9115         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9116         __tg3_set_rx_mode(dev);
9117
9118         tg3_full_unlock(tp);
9119
9120         if (netif_running(dev))
9121                 tg3_netif_start(tp);
9122 }
9123
9124 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9125 {
9126         struct tg3 *tp = netdev_priv(dev);
9127
9128         if (netif_running(dev))
9129                 tg3_netif_stop(tp);
9130
9131         tg3_full_lock(tp, 0);
9132         vlan_group_set_device(tp->vlgrp, vid, NULL);
9133         tg3_full_unlock(tp);
9134
9135         if (netif_running(dev))
9136                 tg3_netif_start(tp);
9137 }
9138 #endif
9139
9140 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9141 {
9142         struct tg3 *tp = netdev_priv(dev);
9143
9144         memcpy(ec, &tp->coal, sizeof(*ec));
9145         return 0;
9146 }
9147
9148 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9149 {
9150         struct tg3 *tp = netdev_priv(dev);
9151         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9152         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9153
9154         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9155                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9156                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9157                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9158                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9159         }
9160
9161         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9162             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9163             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9164             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9165             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9166             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9167             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9168             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9169             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9170             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9171                 return -EINVAL;
9172
9173         /* No rx interrupts will be generated if both are zero */
9174         if ((ec->rx_coalesce_usecs == 0) &&
9175             (ec->rx_max_coalesced_frames == 0))
9176                 return -EINVAL;
9177
9178         /* No tx interrupts will be generated if both are zero */
9179         if ((ec->tx_coalesce_usecs == 0) &&
9180             (ec->tx_max_coalesced_frames == 0))
9181                 return -EINVAL;
9182
9183         /* Only copy relevant parameters, ignore all others. */
9184         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9185         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9186         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9187         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9188         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9189         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9190         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9191         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9192         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9193
9194         if (netif_running(dev)) {
9195                 tg3_full_lock(tp, 0);
9196                 __tg3_set_coalesce(tp, &tp->coal);
9197                 tg3_full_unlock(tp);
9198         }
9199         return 0;
9200 }
9201
9202 static const struct ethtool_ops tg3_ethtool_ops = {
9203         .get_settings           = tg3_get_settings,
9204         .set_settings           = tg3_set_settings,
9205         .get_drvinfo            = tg3_get_drvinfo,
9206         .get_regs_len           = tg3_get_regs_len,
9207         .get_regs               = tg3_get_regs,
9208         .get_wol                = tg3_get_wol,
9209         .set_wol                = tg3_set_wol,
9210         .get_msglevel           = tg3_get_msglevel,
9211         .set_msglevel           = tg3_set_msglevel,
9212         .nway_reset             = tg3_nway_reset,
9213         .get_link               = ethtool_op_get_link,
9214         .get_eeprom_len         = tg3_get_eeprom_len,
9215         .get_eeprom             = tg3_get_eeprom,
9216         .set_eeprom             = tg3_set_eeprom,
9217         .get_ringparam          = tg3_get_ringparam,
9218         .set_ringparam          = tg3_set_ringparam,
9219         .get_pauseparam         = tg3_get_pauseparam,
9220         .set_pauseparam         = tg3_set_pauseparam,
9221         .get_rx_csum            = tg3_get_rx_csum,
9222         .set_rx_csum            = tg3_set_rx_csum,
9223         .get_tx_csum            = ethtool_op_get_tx_csum,
9224         .set_tx_csum            = tg3_set_tx_csum,
9225         .get_sg                 = ethtool_op_get_sg,
9226         .set_sg                 = ethtool_op_set_sg,
9227         .get_tso                = ethtool_op_get_tso,
9228         .set_tso                = tg3_set_tso,
9229         .self_test_count        = tg3_get_test_count,
9230         .self_test              = tg3_self_test,
9231         .get_strings            = tg3_get_strings,
9232         .phys_id                = tg3_phys_id,
9233         .get_stats_count        = tg3_get_stats_count,
9234         .get_ethtool_stats      = tg3_get_ethtool_stats,
9235         .get_coalesce           = tg3_get_coalesce,
9236         .set_coalesce           = tg3_set_coalesce,
9237         .get_perm_addr          = ethtool_op_get_perm_addr,
9238 };
9239
9240 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9241 {
9242         u32 cursize, val, magic;
9243
9244         tp->nvram_size = EEPROM_CHIP_SIZE;
9245
9246         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9247                 return;
9248
9249         if ((magic != TG3_EEPROM_MAGIC) &&
9250             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9251             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9252                 return;
9253
9254         /*
9255          * Size the chip by reading offsets at increasing powers of two.
9256          * When we encounter our validation signature, we know the addressing
9257          * has wrapped around, and thus have our chip size.
9258          */
9259         cursize = 0x10;
9260
9261         while (cursize < tp->nvram_size) {
9262                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9263                         return;
9264
9265                 if (val == magic)
9266                         break;
9267
9268                 cursize <<= 1;
9269         }
9270
9271         tp->nvram_size = cursize;
9272 }
9273
9274 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9275 {
9276         u32 val;
9277
9278         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9279                 return;
9280
9281         /* Selfboot format */
9282         if (val != TG3_EEPROM_MAGIC) {
9283                 tg3_get_eeprom_size(tp);
9284                 return;
9285         }
9286
9287         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9288                 if (val != 0) {
9289                         tp->nvram_size = (val >> 16) * 1024;
9290                         return;
9291                 }
9292         }
9293         tp->nvram_size = 0x20000;
9294 }
9295
9296 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9297 {
9298         u32 nvcfg1;
9299
9300         nvcfg1 = tr32(NVRAM_CFG1);
9301         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9302                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9303         }
9304         else {
9305                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9306                 tw32(NVRAM_CFG1, nvcfg1);
9307         }
9308
9309         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9310             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9311                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9312                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9313                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9314                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9315                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9316                                 break;
9317                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9318                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9319                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9320                                 break;
9321                         case FLASH_VENDOR_ATMEL_EEPROM:
9322                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9323                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9324                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9325                                 break;
9326                         case FLASH_VENDOR_ST:
9327                                 tp->nvram_jedecnum = JEDEC_ST;
9328                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9329                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9330                                 break;
9331                         case FLASH_VENDOR_SAIFUN:
9332                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9333                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9334                                 break;
9335                         case FLASH_VENDOR_SST_SMALL:
9336                         case FLASH_VENDOR_SST_LARGE:
9337                                 tp->nvram_jedecnum = JEDEC_SST;
9338                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9339                                 break;
9340                 }
9341         }
9342         else {
9343                 tp->nvram_jedecnum = JEDEC_ATMEL;
9344                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9345                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9346         }
9347 }
9348
9349 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9350 {
9351         u32 nvcfg1;
9352
9353         nvcfg1 = tr32(NVRAM_CFG1);
9354
9355         /* NVRAM protection for TPM */
9356         if (nvcfg1 & (1 << 27))
9357                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9358
9359         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9360                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9361                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9362                         tp->nvram_jedecnum = JEDEC_ATMEL;
9363                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9364                         break;
9365                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9366                         tp->nvram_jedecnum = JEDEC_ATMEL;
9367                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9368                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9369                         break;
9370                 case FLASH_5752VENDOR_ST_M45PE10:
9371                 case FLASH_5752VENDOR_ST_M45PE20:
9372                 case FLASH_5752VENDOR_ST_M45PE40:
9373                         tp->nvram_jedecnum = JEDEC_ST;
9374                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9375                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9376                         break;
9377         }
9378
9379         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9380                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9381                         case FLASH_5752PAGE_SIZE_256:
9382                                 tp->nvram_pagesize = 256;
9383                                 break;
9384                         case FLASH_5752PAGE_SIZE_512:
9385                                 tp->nvram_pagesize = 512;
9386                                 break;
9387                         case FLASH_5752PAGE_SIZE_1K:
9388                                 tp->nvram_pagesize = 1024;
9389                                 break;
9390                         case FLASH_5752PAGE_SIZE_2K:
9391                                 tp->nvram_pagesize = 2048;
9392                                 break;
9393                         case FLASH_5752PAGE_SIZE_4K:
9394                                 tp->nvram_pagesize = 4096;
9395                                 break;
9396                         case FLASH_5752PAGE_SIZE_264:
9397                                 tp->nvram_pagesize = 264;
9398                                 break;
9399                 }
9400         }
9401         else {
9402                 /* For eeprom, set pagesize to maximum eeprom size */
9403                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9404
9405                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9406                 tw32(NVRAM_CFG1, nvcfg1);
9407         }
9408 }
9409
9410 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9411 {
9412         u32 nvcfg1;
9413
9414         nvcfg1 = tr32(NVRAM_CFG1);
9415
9416         /* NVRAM protection for TPM */
9417         if (nvcfg1 & (1 << 27))
9418                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9419
9420         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9421                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9422                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9423                         tp->nvram_jedecnum = JEDEC_ATMEL;
9424                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9425                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9426
9427                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9428                         tw32(NVRAM_CFG1, nvcfg1);
9429                         break;
9430                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9431                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9432                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9433                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9434                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9435                         tp->nvram_jedecnum = JEDEC_ATMEL;
9436                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9437                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9438                         tp->nvram_pagesize = 264;
9439                         break;
9440                 case FLASH_5752VENDOR_ST_M45PE10:
9441                 case FLASH_5752VENDOR_ST_M45PE20:
9442                 case FLASH_5752VENDOR_ST_M45PE40:
9443                         tp->nvram_jedecnum = JEDEC_ST;
9444                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9445                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9446                         tp->nvram_pagesize = 256;
9447                         break;
9448         }
9449 }
9450
9451 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9452 {
9453         u32 nvcfg1;
9454
9455         nvcfg1 = tr32(NVRAM_CFG1);
9456
9457         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9458                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9459                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9460                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9461                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9462                         tp->nvram_jedecnum = JEDEC_ATMEL;
9463                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9464                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9465
9466                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9467                         tw32(NVRAM_CFG1, nvcfg1);
9468                         break;
9469                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9470                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9471                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9472                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9473                         tp->nvram_jedecnum = JEDEC_ATMEL;
9474                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9475                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9476                         tp->nvram_pagesize = 264;
9477                         break;
9478                 case FLASH_5752VENDOR_ST_M45PE10:
9479                 case FLASH_5752VENDOR_ST_M45PE20:
9480                 case FLASH_5752VENDOR_ST_M45PE40:
9481                         tp->nvram_jedecnum = JEDEC_ST;
9482                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9483                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9484                         tp->nvram_pagesize = 256;
9485                         break;
9486         }
9487 }
9488
9489 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9490 {
9491         tp->nvram_jedecnum = JEDEC_ATMEL;
9492         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9493         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9494 }
9495
9496 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9497 static void __devinit tg3_nvram_init(struct tg3 *tp)
9498 {
9499         tw32_f(GRC_EEPROM_ADDR,
9500              (EEPROM_ADDR_FSM_RESET |
9501               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9502                EEPROM_ADDR_CLKPERD_SHIFT)));
9503
9504         msleep(1);
9505
9506         /* Enable seeprom accesses. */
9507         tw32_f(GRC_LOCAL_CTRL,
9508              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9509         udelay(100);
9510
9511         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9512             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9513                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9514
9515                 if (tg3_nvram_lock(tp)) {
9516                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9517                                "tg3_nvram_init failed.\n", tp->dev->name);
9518                         return;
9519                 }
9520                 tg3_enable_nvram_access(tp);
9521
9522                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9523                         tg3_get_5752_nvram_info(tp);
9524                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9525                         tg3_get_5755_nvram_info(tp);
9526                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9527                         tg3_get_5787_nvram_info(tp);
9528                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9529                         tg3_get_5906_nvram_info(tp);
9530                 else
9531                         tg3_get_nvram_info(tp);
9532
9533                 tg3_get_nvram_size(tp);
9534
9535                 tg3_disable_nvram_access(tp);
9536                 tg3_nvram_unlock(tp);
9537
9538         } else {
9539                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9540
9541                 tg3_get_eeprom_size(tp);
9542         }
9543 }
9544
9545 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9546                                         u32 offset, u32 *val)
9547 {
9548         u32 tmp;
9549         int i;
9550
9551         if (offset > EEPROM_ADDR_ADDR_MASK ||
9552             (offset % 4) != 0)
9553                 return -EINVAL;
9554
9555         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9556                                         EEPROM_ADDR_DEVID_MASK |
9557                                         EEPROM_ADDR_READ);
9558         tw32(GRC_EEPROM_ADDR,
9559              tmp |
9560              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9561              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9562               EEPROM_ADDR_ADDR_MASK) |
9563              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9564
9565         for (i = 0; i < 1000; i++) {
9566                 tmp = tr32(GRC_EEPROM_ADDR);
9567
9568                 if (tmp & EEPROM_ADDR_COMPLETE)
9569                         break;
9570                 msleep(1);
9571         }
9572         if (!(tmp & EEPROM_ADDR_COMPLETE))
9573                 return -EBUSY;
9574
9575         *val = tr32(GRC_EEPROM_DATA);
9576         return 0;
9577 }
9578
9579 #define NVRAM_CMD_TIMEOUT 10000
9580
9581 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9582 {
9583         int i;
9584
9585         tw32(NVRAM_CMD, nvram_cmd);
9586         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9587                 udelay(10);
9588                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9589                         udelay(10);
9590                         break;
9591                 }
9592         }
9593         if (i == NVRAM_CMD_TIMEOUT) {
9594                 return -EBUSY;
9595         }
9596         return 0;
9597 }
9598
9599 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9600 {
9601         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9602             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9603             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9604             (tp->nvram_jedecnum == JEDEC_ATMEL))
9605
9606                 addr = ((addr / tp->nvram_pagesize) <<
9607                         ATMEL_AT45DB0X1B_PAGE_POS) +
9608                        (addr % tp->nvram_pagesize);
9609
9610         return addr;
9611 }
9612
9613 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9614 {
9615         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9616             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9617             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9618             (tp->nvram_jedecnum == JEDEC_ATMEL))
9619
9620                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9621                         tp->nvram_pagesize) +
9622                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9623
9624         return addr;
9625 }
9626
9627 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9628 {
9629         int ret;
9630
9631         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9632                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9633
9634         offset = tg3_nvram_phys_addr(tp, offset);
9635
9636         if (offset > NVRAM_ADDR_MSK)
9637                 return -EINVAL;
9638
9639         ret = tg3_nvram_lock(tp);
9640         if (ret)
9641                 return ret;
9642
9643         tg3_enable_nvram_access(tp);
9644
9645         tw32(NVRAM_ADDR, offset);
9646         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9647                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9648
9649         if (ret == 0)
9650                 *val = swab32(tr32(NVRAM_RDDATA));
9651
9652         tg3_disable_nvram_access(tp);
9653
9654         tg3_nvram_unlock(tp);
9655
9656         return ret;
9657 }
9658
9659 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9660 {
9661         int err;
9662         u32 tmp;
9663
9664         err = tg3_nvram_read(tp, offset, &tmp);
9665         *val = swab32(tmp);
9666         return err;
9667 }
9668
9669 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9670                                     u32 offset, u32 len, u8 *buf)
9671 {
9672         int i, j, rc = 0;
9673         u32 val;
9674
9675         for (i = 0; i < len; i += 4) {
9676                 u32 addr, data;
9677
9678                 addr = offset + i;
9679
9680                 memcpy(&data, buf + i, 4);
9681
9682                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9683
9684                 val = tr32(GRC_EEPROM_ADDR);
9685                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9686
9687                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9688                         EEPROM_ADDR_READ);
9689                 tw32(GRC_EEPROM_ADDR, val |
9690                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9691                         (addr & EEPROM_ADDR_ADDR_MASK) |
9692                         EEPROM_ADDR_START |
9693                         EEPROM_ADDR_WRITE);
9694
9695                 for (j = 0; j < 1000; j++) {
9696                         val = tr32(GRC_EEPROM_ADDR);
9697
9698                         if (val & EEPROM_ADDR_COMPLETE)
9699                                 break;
9700                         msleep(1);
9701                 }
9702                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9703                         rc = -EBUSY;
9704                         break;
9705                 }
9706         }
9707
9708         return rc;
9709 }
9710
9711 /* offset and length are dword aligned */
9712 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9713                 u8 *buf)
9714 {
9715         int ret = 0;
9716         u32 pagesize = tp->nvram_pagesize;
9717         u32 pagemask = pagesize - 1;
9718         u32 nvram_cmd;
9719         u8 *tmp;
9720
9721         tmp = kmalloc(pagesize, GFP_KERNEL);
9722         if (tmp == NULL)
9723                 return -ENOMEM;
9724
9725         while (len) {
9726                 int j;
9727                 u32 phy_addr, page_off, size;
9728
9729                 phy_addr = offset & ~pagemask;
9730
9731                 for (j = 0; j < pagesize; j += 4) {
9732                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9733                                                 (u32 *) (tmp + j))))
9734                                 break;
9735                 }
9736                 if (ret)
9737                         break;
9738
9739                 page_off = offset & pagemask;
9740                 size = pagesize;
9741                 if (len < size)
9742                         size = len;
9743
9744                 len -= size;
9745
9746                 memcpy(tmp + page_off, buf, size);
9747
9748                 offset = offset + (pagesize - page_off);
9749
9750                 tg3_enable_nvram_access(tp);
9751
9752                 /*
9753                  * Before we can erase the flash page, we need
9754                  * to issue a special "write enable" command.
9755                  */
9756                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9757
9758                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9759                         break;
9760
9761                 /* Erase the target page */
9762                 tw32(NVRAM_ADDR, phy_addr);
9763
9764                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9765                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9766
9767                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9768                         break;
9769
9770                 /* Issue another write enable to start the write. */
9771                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9772
9773                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9774                         break;
9775
9776                 for (j = 0; j < pagesize; j += 4) {
9777                         u32 data;
9778
9779                         data = *((u32 *) (tmp + j));
9780                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9781
9782                         tw32(NVRAM_ADDR, phy_addr + j);
9783
9784                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9785                                 NVRAM_CMD_WR;
9786
9787                         if (j == 0)
9788                                 nvram_cmd |= NVRAM_CMD_FIRST;
9789                         else if (j == (pagesize - 4))
9790                                 nvram_cmd |= NVRAM_CMD_LAST;
9791
9792                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9793                                 break;
9794                 }
9795                 if (ret)
9796                         break;
9797         }
9798
9799         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9800         tg3_nvram_exec_cmd(tp, nvram_cmd);
9801
9802         kfree(tmp);
9803
9804         return ret;
9805 }
9806
9807 /* offset and length are dword aligned */
9808 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9809                 u8 *buf)
9810 {
9811         int i, ret = 0;
9812
9813         for (i = 0; i < len; i += 4, offset += 4) {
9814                 u32 data, page_off, phy_addr, nvram_cmd;
9815
9816                 memcpy(&data, buf + i, 4);
9817                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9818
9819                 page_off = offset % tp->nvram_pagesize;
9820
9821                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9822
9823                 tw32(NVRAM_ADDR, phy_addr);
9824
9825                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9826
9827                 if ((page_off == 0) || (i == 0))
9828                         nvram_cmd |= NVRAM_CMD_FIRST;
9829                 if (page_off == (tp->nvram_pagesize - 4))
9830                         nvram_cmd |= NVRAM_CMD_LAST;
9831
9832                 if (i == (len - 4))
9833                         nvram_cmd |= NVRAM_CMD_LAST;
9834
9835                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9836                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9837                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9838                     (tp->nvram_jedecnum == JEDEC_ST) &&
9839                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9840
9841                         if ((ret = tg3_nvram_exec_cmd(tp,
9842                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9843                                 NVRAM_CMD_DONE)))
9844
9845                                 break;
9846                 }
9847                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9848                         /* We always do complete word writes to eeprom. */
9849                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9850                 }
9851
9852                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9853                         break;
9854         }
9855         return ret;
9856 }
9857
9858 /* offset and length are dword aligned */
9859 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9860 {
9861         int ret;
9862
9863         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9864                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9865                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9866                 udelay(40);
9867         }
9868
9869         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9870                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9871         }
9872         else {
9873                 u32 grc_mode;
9874
9875                 ret = tg3_nvram_lock(tp);
9876                 if (ret)
9877                         return ret;
9878
9879                 tg3_enable_nvram_access(tp);
9880                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9881                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9882                         tw32(NVRAM_WRITE1, 0x406);
9883
9884                 grc_mode = tr32(GRC_MODE);
9885                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9886
9887                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9888                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9889
9890                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9891                                 buf);
9892                 }
9893                 else {
9894                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9895                                 buf);
9896                 }
9897
9898                 grc_mode = tr32(GRC_MODE);
9899                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9900
9901                 tg3_disable_nvram_access(tp);
9902                 tg3_nvram_unlock(tp);
9903         }
9904
9905         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9906                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9907                 udelay(40);
9908         }
9909
9910         return ret;
9911 }
9912
9913 struct subsys_tbl_ent {
9914         u16 subsys_vendor, subsys_devid;
9915         u32 phy_id;
9916 };
9917
9918 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9919         /* Broadcom boards. */
9920         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9921         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9922         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9923         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9924         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9925         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9926         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9927         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9928         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9929         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9930         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9931
9932         /* 3com boards. */
9933         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9934         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9935         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9936         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9937         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9938
9939         /* DELL boards. */
9940         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9941         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9942         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9943         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9944
9945         /* Compaq boards. */
9946         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9947         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9948         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9949         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9950         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9951
9952         /* IBM boards. */
9953         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9954 };
9955
9956 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9957 {
9958         int i;
9959
9960         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9961                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9962                      tp->pdev->subsystem_vendor) &&
9963                     (subsys_id_to_phy_id[i].subsys_devid ==
9964                      tp->pdev->subsystem_device))
9965                         return &subsys_id_to_phy_id[i];
9966         }
9967         return NULL;
9968 }
9969
9970 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9971 {
9972         u32 val;
9973         u16 pmcsr;
9974
9975         /* On some early chips the SRAM cannot be accessed in D3hot state,
9976          * so need make sure we're in D0.
9977          */
9978         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9979         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9980         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9981         msleep(1);
9982
9983         /* Make sure register accesses (indirect or otherwise)
9984          * will function correctly.
9985          */
9986         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9987                                tp->misc_host_ctrl);
9988
9989         /* The memory arbiter has to be enabled in order for SRAM accesses
9990          * to succeed.  Normally on powerup the tg3 chip firmware will make
9991          * sure it is enabled, but other entities such as system netboot
9992          * code might disable it.
9993          */
9994         val = tr32(MEMARB_MODE);
9995         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9996
9997         tp->phy_id = PHY_ID_INVALID;
9998         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9999
10000         /* Assume an onboard device by default.  */
10001         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10002
10003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10004                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10005                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10006                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10007                 }
10008                 return;
10009         }
10010
10011         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10012         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10013                 u32 nic_cfg, led_cfg;
10014                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10015                 int eeprom_phy_serdes = 0;
10016
10017                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10018                 tp->nic_sram_data_cfg = nic_cfg;
10019
10020                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10021                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10022                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10023                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10024                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10025                     (ver > 0) && (ver < 0x100))
10026                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10027
10028                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10029                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10030                         eeprom_phy_serdes = 1;
10031
10032                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10033                 if (nic_phy_id != 0) {
10034                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10035                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10036
10037                         eeprom_phy_id  = (id1 >> 16) << 10;
10038                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10039                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10040                 } else
10041                         eeprom_phy_id = 0;
10042
10043                 tp->phy_id = eeprom_phy_id;
10044                 if (eeprom_phy_serdes) {
10045                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10046                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10047                         else
10048                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10049                 }
10050
10051                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10052                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10053                                     SHASTA_EXT_LED_MODE_MASK);
10054                 else
10055                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10056
10057                 switch (led_cfg) {
10058                 default:
10059                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10060                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10061                         break;
10062
10063                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10064                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10065                         break;
10066
10067                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10068                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10069
10070                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10071                          * read on some older 5700/5701 bootcode.
10072                          */
10073                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10074                             ASIC_REV_5700 ||
10075                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10076                             ASIC_REV_5701)
10077                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10078
10079                         break;
10080
10081                 case SHASTA_EXT_LED_SHARED:
10082                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10083                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10084                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10085                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10086                                                  LED_CTRL_MODE_PHY_2);
10087                         break;
10088
10089                 case SHASTA_EXT_LED_MAC:
10090                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10091                         break;
10092
10093                 case SHASTA_EXT_LED_COMBO:
10094                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10095                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10096                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10097                                                  LED_CTRL_MODE_PHY_2);
10098                         break;
10099
10100                 };
10101
10102                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10103                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10104                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10105                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10106
10107                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10108                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10109                         if ((tp->pdev->subsystem_vendor ==
10110                              PCI_VENDOR_ID_ARIMA) &&
10111                             (tp->pdev->subsystem_device == 0x205a ||
10112                              tp->pdev->subsystem_device == 0x2063))
10113                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10114                 } else {
10115                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10116                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10117                 }
10118
10119                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10120                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10121                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10122                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10123                 }
10124                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10125                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10126
10127                 if (cfg2 & (1 << 17))
10128                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10129
10130                 /* serdes signal pre-emphasis in register 0x590 set by */
10131                 /* bootcode if bit 18 is set */
10132                 if (cfg2 & (1 << 18))
10133                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10134         }
10135 }
10136
10137 static int __devinit tg3_phy_probe(struct tg3 *tp)
10138 {
10139         u32 hw_phy_id_1, hw_phy_id_2;
10140         u32 hw_phy_id, hw_phy_id_masked;
10141         int err;
10142
10143         /* Reading the PHY ID register can conflict with ASF
10144          * firwmare access to the PHY hardware.
10145          */
10146         err = 0;
10147         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10148                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10149         } else {
10150                 /* Now read the physical PHY_ID from the chip and verify
10151                  * that it is sane.  If it doesn't look good, we fall back
10152                  * to either the hard-coded table based PHY_ID and failing
10153                  * that the value found in the eeprom area.
10154                  */
10155                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10156                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10157
10158                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10159                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10160                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10161
10162                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10163         }
10164
10165         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10166                 tp->phy_id = hw_phy_id;
10167                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10168                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10169                 else
10170                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10171         } else {
10172                 if (tp->phy_id != PHY_ID_INVALID) {
10173                         /* Do nothing, phy ID already set up in
10174                          * tg3_get_eeprom_hw_cfg().
10175                          */
10176                 } else {
10177                         struct subsys_tbl_ent *p;
10178
10179                         /* No eeprom signature?  Try the hardcoded
10180                          * subsys device table.
10181                          */
10182                         p = lookup_by_subsys(tp);
10183                         if (!p)
10184                                 return -ENODEV;
10185
10186                         tp->phy_id = p->phy_id;
10187                         if (!tp->phy_id ||
10188                             tp->phy_id == PHY_ID_BCM8002)
10189                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10190                 }
10191         }
10192
10193         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10194             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10195                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10196
10197                 tg3_readphy(tp, MII_BMSR, &bmsr);
10198                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10199                     (bmsr & BMSR_LSTATUS))
10200                         goto skip_phy_reset;
10201
10202                 err = tg3_phy_reset(tp);
10203                 if (err)
10204                         return err;
10205
10206                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10207                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10208                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10209                 tg3_ctrl = 0;
10210                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10211                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10212                                     MII_TG3_CTRL_ADV_1000_FULL);
10213                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10214                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10215                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10216                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10217                 }
10218
10219                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10220                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10221                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10222                 if (!tg3_copper_is_advertising_all(tp, mask)) {
10223                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10224
10225                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10226                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10227
10228                         tg3_writephy(tp, MII_BMCR,
10229                                      BMCR_ANENABLE | BMCR_ANRESTART);
10230                 }
10231                 tg3_phy_set_wirespeed(tp);
10232
10233                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10234                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10235                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10236         }
10237
10238 skip_phy_reset:
10239         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10240                 err = tg3_init_5401phy_dsp(tp);
10241                 if (err)
10242                         return err;
10243         }
10244
10245         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10246                 err = tg3_init_5401phy_dsp(tp);
10247         }
10248
10249         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10250                 tp->link_config.advertising =
10251                         (ADVERTISED_1000baseT_Half |
10252                          ADVERTISED_1000baseT_Full |
10253                          ADVERTISED_Autoneg |
10254                          ADVERTISED_FIBRE);
10255         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10256                 tp->link_config.advertising &=
10257                         ~(ADVERTISED_1000baseT_Half |
10258                           ADVERTISED_1000baseT_Full);
10259
10260         return err;
10261 }
10262
10263 static void __devinit tg3_read_partno(struct tg3 *tp)
10264 {
10265         unsigned char vpd_data[256];
10266         unsigned int i;
10267         u32 magic;
10268
10269         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10270                 goto out_not_found;
10271
10272         if (magic == TG3_EEPROM_MAGIC) {
10273                 for (i = 0; i < 256; i += 4) {
10274                         u32 tmp;
10275
10276                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10277                                 goto out_not_found;
10278
10279                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10280                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10281                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10282                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10283                 }
10284         } else {
10285                 int vpd_cap;
10286
10287                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10288                 for (i = 0; i < 256; i += 4) {
10289                         u32 tmp, j = 0;
10290                         u16 tmp16;
10291
10292                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10293                                               i);
10294                         while (j++ < 100) {
10295                                 pci_read_config_word(tp->pdev, vpd_cap +
10296                                                      PCI_VPD_ADDR, &tmp16);
10297                                 if (tmp16 & 0x8000)
10298                                         break;
10299                                 msleep(1);
10300                         }
10301                         if (!(tmp16 & 0x8000))
10302                                 goto out_not_found;
10303
10304                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10305                                               &tmp);
10306                         tmp = cpu_to_le32(tmp);
10307                         memcpy(&vpd_data[i], &tmp, 4);
10308                 }
10309         }
10310
10311         /* Now parse and find the part number. */
10312         for (i = 0; i < 254; ) {
10313                 unsigned char val = vpd_data[i];
10314                 unsigned int block_end;
10315
10316                 if (val == 0x82 || val == 0x91) {
10317                         i = (i + 3 +
10318                              (vpd_data[i + 1] +
10319                               (vpd_data[i + 2] << 8)));
10320                         continue;
10321                 }
10322
10323                 if (val != 0x90)
10324                         goto out_not_found;
10325
10326                 block_end = (i + 3 +
10327                              (vpd_data[i + 1] +
10328                               (vpd_data[i + 2] << 8)));
10329                 i += 3;
10330
10331                 if (block_end > 256)
10332                         goto out_not_found;
10333
10334                 while (i < (block_end - 2)) {
10335                         if (vpd_data[i + 0] == 'P' &&
10336                             vpd_data[i + 1] == 'N') {
10337                                 int partno_len = vpd_data[i + 2];
10338
10339                                 i += 3;
10340                                 if (partno_len > 24 || (partno_len + i) > 256)
10341                                         goto out_not_found;
10342
10343                                 memcpy(tp->board_part_number,
10344                                        &vpd_data[i], partno_len);
10345
10346                                 /* Success. */
10347                                 return;
10348                         }
10349                         i += 3 + vpd_data[i + 2];
10350                 }
10351
10352                 /* Part number not found. */
10353                 goto out_not_found;
10354         }
10355
10356 out_not_found:
10357         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10358                 strcpy(tp->board_part_number, "BCM95906");
10359         else
10360                 strcpy(tp->board_part_number, "none");
10361 }
10362
10363 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10364 {
10365         u32 val, offset, start;
10366
10367         if (tg3_nvram_read_swab(tp, 0, &val))
10368                 return;
10369
10370         if (val != TG3_EEPROM_MAGIC)
10371                 return;
10372
10373         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10374             tg3_nvram_read_swab(tp, 0x4, &start))
10375                 return;
10376
10377         offset = tg3_nvram_logical_addr(tp, offset);
10378         if (tg3_nvram_read_swab(tp, offset, &val))
10379                 return;
10380
10381         if ((val & 0xfc000000) == 0x0c000000) {
10382                 u32 ver_offset, addr;
10383                 int i;
10384
10385                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10386                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10387                         return;
10388
10389                 if (val != 0)
10390                         return;
10391
10392                 addr = offset + ver_offset - start;
10393                 for (i = 0; i < 16; i += 4) {
10394                         if (tg3_nvram_read(tp, addr + i, &val))
10395                                 return;
10396
10397                         val = cpu_to_le32(val);
10398                         memcpy(tp->fw_ver + i, &val, 4);
10399                 }
10400         }
10401 }
10402
10403 static int __devinit tg3_get_invariants(struct tg3 *tp)
10404 {
10405         static struct pci_device_id write_reorder_chipsets[] = {
10406                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10407                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10408                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10409                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10410                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10411                              PCI_DEVICE_ID_VIA_8385_0) },
10412                 { },
10413         };
10414         u32 misc_ctrl_reg;
10415         u32 cacheline_sz_reg;
10416         u32 pci_state_reg, grc_misc_cfg;
10417         u32 val;
10418         u16 pci_cmd;
10419         int err, pcie_cap;
10420
10421         /* Force memory write invalidate off.  If we leave it on,
10422          * then on 5700_BX chips we have to enable a workaround.
10423          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10424          * to match the cacheline size.  The Broadcom driver have this
10425          * workaround but turns MWI off all the times so never uses
10426          * it.  This seems to suggest that the workaround is insufficient.
10427          */
10428         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10429         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10430         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10431
10432         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10433          * has the register indirect write enable bit set before
10434          * we try to access any of the MMIO registers.  It is also
10435          * critical that the PCI-X hw workaround situation is decided
10436          * before that as well.
10437          */
10438         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10439                               &misc_ctrl_reg);
10440
10441         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10442                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10443
10444         /* Wrong chip ID in 5752 A0. This code can be removed later
10445          * as A0 is not in production.
10446          */
10447         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10448                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10449
10450         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10451          * we need to disable memory and use config. cycles
10452          * only to access all registers. The 5702/03 chips
10453          * can mistakenly decode the special cycles from the
10454          * ICH chipsets as memory write cycles, causing corruption
10455          * of register and memory space. Only certain ICH bridges
10456          * will drive special cycles with non-zero data during the
10457          * address phase which can fall within the 5703's address
10458          * range. This is not an ICH bug as the PCI spec allows
10459          * non-zero address during special cycles. However, only
10460          * these ICH bridges are known to drive non-zero addresses
10461          * during special cycles.
10462          *
10463          * Since special cycles do not cross PCI bridges, we only
10464          * enable this workaround if the 5703 is on the secondary
10465          * bus of these ICH bridges.
10466          */
10467         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10468             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10469                 static struct tg3_dev_id {
10470                         u32     vendor;
10471                         u32     device;
10472                         u32     rev;
10473                 } ich_chipsets[] = {
10474                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10475                           PCI_ANY_ID },
10476                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10477                           PCI_ANY_ID },
10478                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10479                           0xa },
10480                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10481                           PCI_ANY_ID },
10482                         { },
10483                 };
10484                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10485                 struct pci_dev *bridge = NULL;
10486
10487                 while (pci_id->vendor != 0) {
10488                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10489                                                 bridge);
10490                         if (!bridge) {
10491                                 pci_id++;
10492                                 continue;
10493                         }
10494                         if (pci_id->rev != PCI_ANY_ID) {
10495                                 u8 rev;
10496
10497                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10498                                                      &rev);
10499                                 if (rev > pci_id->rev)
10500                                         continue;
10501                         }
10502                         if (bridge->subordinate &&
10503                             (bridge->subordinate->number ==
10504                              tp->pdev->bus->number)) {
10505
10506                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10507                                 pci_dev_put(bridge);
10508                                 break;
10509                         }
10510                 }
10511         }
10512
10513         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10514          * DMA addresses > 40-bit. This bridge may have other additional
10515          * 57xx devices behind it in some 4-port NIC designs for example.
10516          * Any tg3 device found behind the bridge will also need the 40-bit
10517          * DMA workaround.
10518          */
10519         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10520             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10521                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10522                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10523                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10524         }
10525         else {
10526                 struct pci_dev *bridge = NULL;
10527
10528                 do {
10529                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10530                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10531                                                 bridge);
10532                         if (bridge && bridge->subordinate &&
10533                             (bridge->subordinate->number <=
10534                              tp->pdev->bus->number) &&
10535                             (bridge->subordinate->subordinate >=
10536                              tp->pdev->bus->number)) {
10537                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10538                                 pci_dev_put(bridge);
10539                                 break;
10540                         }
10541                 } while (bridge);
10542         }
10543
10544         /* Initialize misc host control in PCI block. */
10545         tp->misc_host_ctrl |= (misc_ctrl_reg &
10546                                MISC_HOST_CTRL_CHIPREV);
10547         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10548                                tp->misc_host_ctrl);
10549
10550         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10551                               &cacheline_sz_reg);
10552
10553         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10554         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10555         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10556         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10557
10558         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10559             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10560             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10561             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10562             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10563             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10564                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10565
10566         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10567             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10568                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10569
10570         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10571                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10572                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10573                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10574                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10575                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10576                 } else {
10577                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10578                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10579                                 ASIC_REV_5750 &&
10580                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10581                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10582                 }
10583         }
10584
10585         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10586             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10587             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10588             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10589             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10590             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10591                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10592
10593         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10594         if (pcie_cap != 0) {
10595                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10596                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10597                         u16 lnkctl;
10598
10599                         pci_read_config_word(tp->pdev,
10600                                              pcie_cap + PCI_EXP_LNKCTL,
10601                                              &lnkctl);
10602                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10603                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10604                 }
10605         }
10606
10607         /* If we have an AMD 762 or VIA K8T800 chipset, write
10608          * reordering to the mailbox registers done by the host
10609          * controller can cause major troubles.  We read back from
10610          * every mailbox register write to force the writes to be
10611          * posted to the chip in order.
10612          */
10613         if (pci_dev_present(write_reorder_chipsets) &&
10614             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10615                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10616
10617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10618             tp->pci_lat_timer < 64) {
10619                 tp->pci_lat_timer = 64;
10620
10621                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10622                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10623                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10624                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10625
10626                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10627                                        cacheline_sz_reg);
10628         }
10629
10630         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10631                               &pci_state_reg);
10632
10633         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10634                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10635
10636                 /* If this is a 5700 BX chipset, and we are in PCI-X
10637                  * mode, enable register write workaround.
10638                  *
10639                  * The workaround is to use indirect register accesses
10640                  * for all chip writes not to mailbox registers.
10641                  */
10642                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10643                         u32 pm_reg;
10644                         u16 pci_cmd;
10645
10646                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10647
10648                         /* The chip can have it's power management PCI config
10649                          * space registers clobbered due to this bug.
10650                          * So explicitly force the chip into D0 here.
10651                          */
10652                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10653                                               &pm_reg);
10654                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10655                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10656                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10657                                                pm_reg);
10658
10659                         /* Also, force SERR#/PERR# in PCI command. */
10660                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10661                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10662                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10663                 }
10664         }
10665
10666         /* 5700 BX chips need to have their TX producer index mailboxes
10667          * written twice to workaround a bug.
10668          */
10669         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10670                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10671
10672         /* Back to back register writes can cause problems on this chip,
10673          * the workaround is to read back all reg writes except those to
10674          * mailbox regs.  See tg3_write_indirect_reg32().
10675          *
10676          * PCI Express 5750_A0 rev chips need this workaround too.
10677          */
10678         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10679             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10680              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10681                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10682
10683         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10684                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10685         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10686                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10687
10688         /* Chip-specific fixup from Broadcom driver */
10689         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10690             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10691                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10692                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10693         }
10694
10695         /* Default fast path register access methods */
10696         tp->read32 = tg3_read32;
10697         tp->write32 = tg3_write32;
10698         tp->read32_mbox = tg3_read32;
10699         tp->write32_mbox = tg3_write32;
10700         tp->write32_tx_mbox = tg3_write32;
10701         tp->write32_rx_mbox = tg3_write32;
10702
10703         /* Various workaround register access methods */
10704         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10705                 tp->write32 = tg3_write_indirect_reg32;
10706         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10707                 tp->write32 = tg3_write_flush_reg32;
10708
10709         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10710             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10711                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10712                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10713                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10714         }
10715
10716         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10717                 tp->read32 = tg3_read_indirect_reg32;
10718                 tp->write32 = tg3_write_indirect_reg32;
10719                 tp->read32_mbox = tg3_read_indirect_mbox;
10720                 tp->write32_mbox = tg3_write_indirect_mbox;
10721                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10722                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10723
10724                 iounmap(tp->regs);
10725                 tp->regs = NULL;
10726
10727                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10728                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10729                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10730         }
10731         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10732                 tp->read32_mbox = tg3_read32_mbox_5906;
10733                 tp->write32_mbox = tg3_write32_mbox_5906;
10734                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10735                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10736         }
10737
10738         if (tp->write32 == tg3_write_indirect_reg32 ||
10739             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10740              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10741               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10742                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10743
10744         /* Get eeprom hw config before calling tg3_set_power_state().
10745          * In particular, the TG3_FLG2_IS_NIC flag must be
10746          * determined before calling tg3_set_power_state() so that
10747          * we know whether or not to switch out of Vaux power.
10748          * When the flag is set, it means that GPIO1 is used for eeprom
10749          * write protect and also implies that it is a LOM where GPIOs
10750          * are not used to switch power.
10751          */
10752         tg3_get_eeprom_hw_cfg(tp);
10753
10754         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10755          * GPIO1 driven high will bring 5700's external PHY out of reset.
10756          * It is also used as eeprom write protect on LOMs.
10757          */
10758         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10759         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10760             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10761                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10762                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10763         /* Unused GPIO3 must be driven as output on 5752 because there
10764          * are no pull-up resistors on unused GPIO pins.
10765          */
10766         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10767                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10768
10769         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10770                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10771
10772         /* Force the chip into D0. */
10773         err = tg3_set_power_state(tp, PCI_D0);
10774         if (err) {
10775                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10776                        pci_name(tp->pdev));
10777                 return err;
10778         }
10779
10780         /* 5700 B0 chips do not support checksumming correctly due
10781          * to hardware bugs.
10782          */
10783         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10784                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10785
10786         /* Derive initial jumbo mode from MTU assigned in
10787          * ether_setup() via the alloc_etherdev() call
10788          */
10789         if (tp->dev->mtu > ETH_DATA_LEN &&
10790             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10791                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10792
10793         /* Determine WakeOnLan speed to use. */
10794         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10795             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10796             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10797             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10798                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10799         } else {
10800                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10801         }
10802
10803         /* A few boards don't want Ethernet@WireSpeed phy feature */
10804         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10805             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10806              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10807              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10808             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10809             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10810                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10811
10812         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10813             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10814                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10815         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10816                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10817
10818         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10819                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10820                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10821                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10822                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10823                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10824                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10825                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10826                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10827                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10828         }
10829
10830         tp->coalesce_mode = 0;
10831         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10832             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10833                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10834
10835         /* Initialize MAC MI mode, polling disabled. */
10836         tw32_f(MAC_MI_MODE, tp->mi_mode);
10837         udelay(80);
10838
10839         /* Initialize data/descriptor byte/word swapping. */
10840         val = tr32(GRC_MODE);
10841         val &= GRC_MODE_HOST_STACKUP;
10842         tw32(GRC_MODE, val | tp->grc_mode);
10843
10844         tg3_switch_clocks(tp);
10845
10846         /* Clear this out for sanity. */
10847         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10848
10849         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10850                               &pci_state_reg);
10851         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10852             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10853                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10854
10855                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10856                     chiprevid == CHIPREV_ID_5701_B0 ||
10857                     chiprevid == CHIPREV_ID_5701_B2 ||
10858                     chiprevid == CHIPREV_ID_5701_B5) {
10859                         void __iomem *sram_base;
10860
10861                         /* Write some dummy words into the SRAM status block
10862                          * area, see if it reads back correctly.  If the return
10863                          * value is bad, force enable the PCIX workaround.
10864                          */
10865                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10866
10867                         writel(0x00000000, sram_base);
10868                         writel(0x00000000, sram_base + 4);
10869                         writel(0xffffffff, sram_base + 4);
10870                         if (readl(sram_base) != 0x00000000)
10871                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10872                 }
10873         }
10874
10875         udelay(50);
10876         tg3_nvram_init(tp);
10877
10878         grc_misc_cfg = tr32(GRC_MISC_CFG);
10879         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10880
10881         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10882             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10883              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10884                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10885
10886         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10887             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10888                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10889         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10890                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10891                                       HOSTCC_MODE_CLRTICK_TXBD);
10892
10893                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10894                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10895                                        tp->misc_host_ctrl);
10896         }
10897
10898         /* these are limited to 10/100 only */
10899         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10900              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10901             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10902              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10903              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10904               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10905               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10906             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10907              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10908               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10909               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10910             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10911                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10912
10913         err = tg3_phy_probe(tp);
10914         if (err) {
10915                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10916                        pci_name(tp->pdev), err);
10917                 /* ... but do not return immediately ... */
10918         }
10919
10920         tg3_read_partno(tp);
10921         tg3_read_fw_ver(tp);
10922
10923         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10924                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10925         } else {
10926                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10927                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10928                 else
10929                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10930         }
10931
10932         /* 5700 {AX,BX} chips have a broken status block link
10933          * change bit implementation, so we must use the
10934          * status register in those cases.
10935          */
10936         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10937                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10938         else
10939                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10940
10941         /* The led_ctrl is set during tg3_phy_probe, here we might
10942          * have to force the link status polling mechanism based
10943          * upon subsystem IDs.
10944          */
10945         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10946             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10947                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10948                                   TG3_FLAG_USE_LINKCHG_REG);
10949         }
10950
10951         /* For all SERDES we poll the MAC status register. */
10952         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10953                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10954         else
10955                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10956
10957         /* All chips before 5787 can get confused if TX buffers
10958          * straddle the 4GB address boundary in some cases.
10959          */
10960         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10961             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10962             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10963                 tp->dev->hard_start_xmit = tg3_start_xmit;
10964         else
10965                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10966
10967         tp->rx_offset = 2;
10968         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10969             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10970                 tp->rx_offset = 0;
10971
10972         tp->rx_std_max_post = TG3_RX_RING_SIZE;
10973
10974         /* Increment the rx prod index on the rx std ring by at most
10975          * 8 for these chips to workaround hw errata.
10976          */
10977         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10978             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10979             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10980                 tp->rx_std_max_post = 8;
10981
10982         /* By default, disable wake-on-lan.  User can change this
10983          * using ETHTOOL_SWOL.
10984          */
10985         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10986
10987         return err;
10988 }
10989
10990 #ifdef CONFIG_SPARC64
10991 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10992 {
10993         struct net_device *dev = tp->dev;
10994         struct pci_dev *pdev = tp->pdev;
10995         struct pcidev_cookie *pcp = pdev->sysdata;
10996
10997         if (pcp != NULL) {
10998                 unsigned char *addr;
10999                 int len;
11000
11001                 addr = of_get_property(pcp->prom_node, "local-mac-address",
11002                                         &len);
11003                 if (addr && len == 6) {
11004                         memcpy(dev->dev_addr, addr, 6);
11005                         memcpy(dev->perm_addr, dev->dev_addr, 6);
11006                         return 0;
11007                 }
11008         }
11009         return -ENODEV;
11010 }
11011
11012 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11013 {
11014         struct net_device *dev = tp->dev;
11015
11016         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11017         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11018         return 0;
11019 }
11020 #endif
11021
11022 static int __devinit tg3_get_device_address(struct tg3 *tp)
11023 {
11024         struct net_device *dev = tp->dev;
11025         u32 hi, lo, mac_offset;
11026         int addr_ok = 0;
11027
11028 #ifdef CONFIG_SPARC64
11029         if (!tg3_get_macaddr_sparc(tp))
11030                 return 0;
11031 #endif
11032
11033         mac_offset = 0x7c;
11034         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11035             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11036                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11037                         mac_offset = 0xcc;
11038                 if (tg3_nvram_lock(tp))
11039                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11040                 else
11041                         tg3_nvram_unlock(tp);
11042         }
11043         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11044                 mac_offset = 0x10;
11045
11046         /* First try to get it from MAC address mailbox. */
11047         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11048         if ((hi >> 16) == 0x484b) {
11049                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11050                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11051
11052                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11053                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11054                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11055                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11056                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11057
11058                 /* Some old bootcode may report a 0 MAC address in SRAM */
11059                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11060         }
11061         if (!addr_ok) {
11062                 /* Next, try NVRAM. */
11063                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11064                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11065                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11066                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11067                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11068                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11069                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11070                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11071                 }
11072                 /* Finally just fetch it out of the MAC control regs. */
11073                 else {
11074                         hi = tr32(MAC_ADDR_0_HIGH);
11075                         lo = tr32(MAC_ADDR_0_LOW);
11076
11077                         dev->dev_addr[5] = lo & 0xff;
11078                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11079                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11080                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11081                         dev->dev_addr[1] = hi & 0xff;
11082                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11083                 }
11084         }
11085
11086         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11087 #ifdef CONFIG_SPARC64
11088                 if (!tg3_get_default_macaddr_sparc(tp))
11089                         return 0;
11090 #endif
11091                 return -EINVAL;
11092         }
11093         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11094         return 0;
11095 }
11096
11097 #define BOUNDARY_SINGLE_CACHELINE       1
11098 #define BOUNDARY_MULTI_CACHELINE        2
11099
11100 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11101 {
11102         int cacheline_size;
11103         u8 byte;
11104         int goal;
11105
11106         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11107         if (byte == 0)
11108                 cacheline_size = 1024;
11109         else
11110                 cacheline_size = (int) byte * 4;
11111
11112         /* On 5703 and later chips, the boundary bits have no
11113          * effect.
11114          */
11115         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11116             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11117             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11118                 goto out;
11119
11120 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11121         goal = BOUNDARY_MULTI_CACHELINE;
11122 #else
11123 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11124         goal = BOUNDARY_SINGLE_CACHELINE;
11125 #else
11126         goal = 0;
11127 #endif
11128 #endif
11129
11130         if (!goal)
11131                 goto out;
11132
11133         /* PCI controllers on most RISC systems tend to disconnect
11134          * when a device tries to burst across a cache-line boundary.
11135          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11136          *
11137          * Unfortunately, for PCI-E there are only limited
11138          * write-side controls for this, and thus for reads
11139          * we will still get the disconnects.  We'll also waste
11140          * these PCI cycles for both read and write for chips
11141          * other than 5700 and 5701 which do not implement the
11142          * boundary bits.
11143          */
11144         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11145             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11146                 switch (cacheline_size) {
11147                 case 16:
11148                 case 32:
11149                 case 64:
11150                 case 128:
11151                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11152                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11153                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11154                         } else {
11155                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11156                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11157                         }
11158                         break;
11159
11160                 case 256:
11161                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11162                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11163                         break;
11164
11165                 default:
11166                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11167                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11168                         break;
11169                 };
11170         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11171                 switch (cacheline_size) {
11172                 case 16:
11173                 case 32:
11174                 case 64:
11175                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11176                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11177                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11178                                 break;
11179                         }
11180                         /* fallthrough */
11181                 case 128:
11182                 default:
11183                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11184                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11185                         break;
11186                 };
11187         } else {
11188                 switch (cacheline_size) {
11189                 case 16:
11190                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11191                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11192                                         DMA_RWCTRL_WRITE_BNDRY_16);
11193                                 break;
11194                         }
11195                         /* fallthrough */
11196                 case 32:
11197                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11198                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11199                                         DMA_RWCTRL_WRITE_BNDRY_32);
11200                                 break;
11201                         }
11202                         /* fallthrough */
11203                 case 64:
11204                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11205                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11206                                         DMA_RWCTRL_WRITE_BNDRY_64);
11207                                 break;
11208                         }
11209                         /* fallthrough */
11210                 case 128:
11211                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11212                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11213                                         DMA_RWCTRL_WRITE_BNDRY_128);
11214                                 break;
11215                         }
11216                         /* fallthrough */
11217                 case 256:
11218                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11219                                 DMA_RWCTRL_WRITE_BNDRY_256);
11220                         break;
11221                 case 512:
11222                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11223                                 DMA_RWCTRL_WRITE_BNDRY_512);
11224                         break;
11225                 case 1024:
11226                 default:
11227                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11228                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11229                         break;
11230                 };
11231         }
11232
11233 out:
11234         return val;
11235 }
11236
11237 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11238 {
11239         struct tg3_internal_buffer_desc test_desc;
11240         u32 sram_dma_descs;
11241         int i, ret;
11242
11243         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11244
11245         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11246         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11247         tw32(RDMAC_STATUS, 0);
11248         tw32(WDMAC_STATUS, 0);
11249
11250         tw32(BUFMGR_MODE, 0);
11251         tw32(FTQ_RESET, 0);
11252
11253         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11254         test_desc.addr_lo = buf_dma & 0xffffffff;
11255         test_desc.nic_mbuf = 0x00002100;
11256         test_desc.len = size;
11257
11258         /*
11259          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11260          * the *second* time the tg3 driver was getting loaded after an
11261          * initial scan.
11262          *
11263          * Broadcom tells me:
11264          *   ...the DMA engine is connected to the GRC block and a DMA
11265          *   reset may affect the GRC block in some unpredictable way...
11266          *   The behavior of resets to individual blocks has not been tested.
11267          *
11268          * Broadcom noted the GRC reset will also reset all sub-components.
11269          */
11270         if (to_device) {
11271                 test_desc.cqid_sqid = (13 << 8) | 2;
11272
11273                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11274                 udelay(40);
11275         } else {
11276                 test_desc.cqid_sqid = (16 << 8) | 7;
11277
11278                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11279                 udelay(40);
11280         }
11281         test_desc.flags = 0x00000005;
11282
11283         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11284                 u32 val;
11285
11286                 val = *(((u32 *)&test_desc) + i);
11287                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11288                                        sram_dma_descs + (i * sizeof(u32)));
11289                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11290         }
11291         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11292
11293         if (to_device) {
11294                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11295         } else {
11296                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11297         }
11298
11299         ret = -ENODEV;
11300         for (i = 0; i < 40; i++) {
11301                 u32 val;
11302
11303                 if (to_device)
11304                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11305                 else
11306                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11307                 if ((val & 0xffff) == sram_dma_descs) {
11308                         ret = 0;
11309                         break;
11310                 }
11311
11312                 udelay(100);
11313         }
11314
11315         return ret;
11316 }
11317
11318 #define TEST_BUFFER_SIZE        0x2000
11319
11320 static int __devinit tg3_test_dma(struct tg3 *tp)
11321 {
11322         dma_addr_t buf_dma;
11323         u32 *buf, saved_dma_rwctrl;
11324         int ret;
11325
11326         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11327         if (!buf) {
11328                 ret = -ENOMEM;
11329                 goto out_nofree;
11330         }
11331
11332         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11333                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11334
11335         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11336
11337         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11338                 /* DMA read watermark not used on PCIE */
11339                 tp->dma_rwctrl |= 0x00180000;
11340         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11341                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11342                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11343                         tp->dma_rwctrl |= 0x003f0000;
11344                 else
11345                         tp->dma_rwctrl |= 0x003f000f;
11346         } else {
11347                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11348                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11349                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11350                         u32 read_water = 0x7;
11351
11352                         /* If the 5704 is behind the EPB bridge, we can
11353                          * do the less restrictive ONE_DMA workaround for
11354                          * better performance.
11355                          */
11356                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11357                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11358                                 tp->dma_rwctrl |= 0x8000;
11359                         else if (ccval == 0x6 || ccval == 0x7)
11360                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11361
11362                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11363                                 read_water = 4;
11364                         /* Set bit 23 to enable PCIX hw bug fix */
11365                         tp->dma_rwctrl |=
11366                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11367                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11368                                 (1 << 23);
11369                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11370                         /* 5780 always in PCIX mode */
11371                         tp->dma_rwctrl |= 0x00144000;
11372                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11373                         /* 5714 always in PCIX mode */
11374                         tp->dma_rwctrl |= 0x00148000;
11375                 } else {
11376                         tp->dma_rwctrl |= 0x001b000f;
11377                 }
11378         }
11379
11380         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11381             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11382                 tp->dma_rwctrl &= 0xfffffff0;
11383
11384         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11385             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11386                 /* Remove this if it causes problems for some boards. */
11387                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11388
11389                 /* On 5700/5701 chips, we need to set this bit.
11390                  * Otherwise the chip will issue cacheline transactions
11391                  * to streamable DMA memory with not all the byte
11392                  * enables turned on.  This is an error on several
11393                  * RISC PCI controllers, in particular sparc64.
11394                  *
11395                  * On 5703/5704 chips, this bit has been reassigned
11396                  * a different meaning.  In particular, it is used
11397                  * on those chips to enable a PCI-X workaround.
11398                  */
11399                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11400         }
11401
11402         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11403
11404 #if 0
11405         /* Unneeded, already done by tg3_get_invariants.  */
11406         tg3_switch_clocks(tp);
11407 #endif
11408
11409         ret = 0;
11410         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11411             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11412                 goto out;
11413
11414         /* It is best to perform DMA test with maximum write burst size
11415          * to expose the 5700/5701 write DMA bug.
11416          */
11417         saved_dma_rwctrl = tp->dma_rwctrl;
11418         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11419         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11420
11421         while (1) {
11422                 u32 *p = buf, i;
11423
11424                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11425                         p[i] = i;
11426
11427                 /* Send the buffer to the chip. */
11428                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11429                 if (ret) {
11430                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11431                         break;
11432                 }
11433
11434 #if 0
11435                 /* validate data reached card RAM correctly. */
11436                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11437                         u32 val;
11438                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11439                         if (le32_to_cpu(val) != p[i]) {
11440                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11441                                 /* ret = -ENODEV here? */
11442                         }
11443                         p[i] = 0;
11444                 }
11445 #endif
11446                 /* Now read it back. */
11447                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11448                 if (ret) {
11449                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11450
11451                         break;
11452                 }
11453
11454                 /* Verify it. */
11455                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11456                         if (p[i] == i)
11457                                 continue;
11458
11459                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11460                             DMA_RWCTRL_WRITE_BNDRY_16) {
11461                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11462                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11463                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11464                                 break;
11465                         } else {
11466                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11467                                 ret = -ENODEV;
11468                                 goto out;
11469                         }
11470                 }
11471
11472                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11473                         /* Success. */
11474                         ret = 0;
11475                         break;
11476                 }
11477         }
11478         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11479             DMA_RWCTRL_WRITE_BNDRY_16) {
11480                 static struct pci_device_id dma_wait_state_chipsets[] = {
11481                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11482                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11483                         { },
11484                 };
11485
11486                 /* DMA test passed without adjusting DMA boundary,
11487                  * now look for chipsets that are known to expose the
11488                  * DMA bug without failing the test.
11489                  */
11490                 if (pci_dev_present(dma_wait_state_chipsets)) {
11491                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11492                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11493                 }
11494                 else
11495                         /* Safe to use the calculated DMA boundary. */
11496                         tp->dma_rwctrl = saved_dma_rwctrl;
11497
11498                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11499         }
11500
11501 out:
11502         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11503 out_nofree:
11504         return ret;
11505 }
11506
11507 static void __devinit tg3_init_link_config(struct tg3 *tp)
11508 {
11509         tp->link_config.advertising =
11510                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11511                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11512                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11513                  ADVERTISED_Autoneg | ADVERTISED_MII);
11514         tp->link_config.speed = SPEED_INVALID;
11515         tp->link_config.duplex = DUPLEX_INVALID;
11516         tp->link_config.autoneg = AUTONEG_ENABLE;
11517         tp->link_config.active_speed = SPEED_INVALID;
11518         tp->link_config.active_duplex = DUPLEX_INVALID;
11519         tp->link_config.phy_is_low_power = 0;
11520         tp->link_config.orig_speed = SPEED_INVALID;
11521         tp->link_config.orig_duplex = DUPLEX_INVALID;
11522         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11523 }
11524
11525 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11526 {
11527         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11528                 tp->bufmgr_config.mbuf_read_dma_low_water =
11529                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11530                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11531                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11532                 tp->bufmgr_config.mbuf_high_water =
11533                         DEFAULT_MB_HIGH_WATER_5705;
11534                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11535                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11536                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11537                         tp->bufmgr_config.mbuf_high_water =
11538                                 DEFAULT_MB_HIGH_WATER_5906;
11539                 }
11540
11541                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11542                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11543                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11544                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11545                 tp->bufmgr_config.mbuf_high_water_jumbo =
11546                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11547         } else {
11548                 tp->bufmgr_config.mbuf_read_dma_low_water =
11549                         DEFAULT_MB_RDMA_LOW_WATER;
11550                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11551                         DEFAULT_MB_MACRX_LOW_WATER;
11552                 tp->bufmgr_config.mbuf_high_water =
11553                         DEFAULT_MB_HIGH_WATER;
11554
11555                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11556                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11557                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11558                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11559                 tp->bufmgr_config.mbuf_high_water_jumbo =
11560                         DEFAULT_MB_HIGH_WATER_JUMBO;
11561         }
11562
11563         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11564         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11565 }
11566
11567 static char * __devinit tg3_phy_string(struct tg3 *tp)
11568 {
11569         switch (tp->phy_id & PHY_ID_MASK) {
11570         case PHY_ID_BCM5400:    return "5400";
11571         case PHY_ID_BCM5401:    return "5401";
11572         case PHY_ID_BCM5411:    return "5411";
11573         case PHY_ID_BCM5701:    return "5701";
11574         case PHY_ID_BCM5703:    return "5703";
11575         case PHY_ID_BCM5704:    return "5704";
11576         case PHY_ID_BCM5705:    return "5705";
11577         case PHY_ID_BCM5750:    return "5750";
11578         case PHY_ID_BCM5752:    return "5752";
11579         case PHY_ID_BCM5714:    return "5714";
11580         case PHY_ID_BCM5780:    return "5780";
11581         case PHY_ID_BCM5755:    return "5755";
11582         case PHY_ID_BCM5787:    return "5787";
11583         case PHY_ID_BCM5756:    return "5722/5756";
11584         case PHY_ID_BCM5906:    return "5906";
11585         case PHY_ID_BCM8002:    return "8002/serdes";
11586         case 0:                 return "serdes";
11587         default:                return "unknown";
11588         };
11589 }
11590
11591 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11592 {
11593         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11594                 strcpy(str, "PCI Express");
11595                 return str;
11596         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11597                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11598
11599                 strcpy(str, "PCIX:");
11600
11601                 if ((clock_ctrl == 7) ||
11602                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11603                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11604                         strcat(str, "133MHz");
11605                 else if (clock_ctrl == 0)
11606                         strcat(str, "33MHz");
11607                 else if (clock_ctrl == 2)
11608                         strcat(str, "50MHz");
11609                 else if (clock_ctrl == 4)
11610                         strcat(str, "66MHz");
11611                 else if (clock_ctrl == 6)
11612                         strcat(str, "100MHz");
11613         } else {
11614                 strcpy(str, "PCI:");
11615                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11616                         strcat(str, "66MHz");
11617                 else
11618                         strcat(str, "33MHz");
11619         }
11620         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11621                 strcat(str, ":32-bit");
11622         else
11623                 strcat(str, ":64-bit");
11624         return str;
11625 }
11626
11627 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11628 {
11629         struct pci_dev *peer;
11630         unsigned int func, devnr = tp->pdev->devfn & ~7;
11631
11632         for (func = 0; func < 8; func++) {
11633                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11634                 if (peer && peer != tp->pdev)
11635                         break;
11636                 pci_dev_put(peer);
11637         }
11638         /* 5704 can be configured in single-port mode, set peer to
11639          * tp->pdev in that case.
11640          */
11641         if (!peer) {
11642                 peer = tp->pdev;
11643                 return peer;
11644         }
11645
11646         /*
11647          * We don't need to keep the refcount elevated; there's no way
11648          * to remove one half of this device without removing the other
11649          */
11650         pci_dev_put(peer);
11651
11652         return peer;
11653 }
11654
11655 static void __devinit tg3_init_coal(struct tg3 *tp)
11656 {
11657         struct ethtool_coalesce *ec = &tp->coal;
11658
11659         memset(ec, 0, sizeof(*ec));
11660         ec->cmd = ETHTOOL_GCOALESCE;
11661         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11662         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11663         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11664         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11665         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11666         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11667         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11668         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11669         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11670
11671         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11672                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11673                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11674                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11675                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11676                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11677         }
11678
11679         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11680                 ec->rx_coalesce_usecs_irq = 0;
11681                 ec->tx_coalesce_usecs_irq = 0;
11682                 ec->stats_block_coalesce_usecs = 0;
11683         }
11684 }
11685
11686 static int __devinit tg3_init_one(struct pci_dev *pdev,
11687                                   const struct pci_device_id *ent)
11688 {
11689         static int tg3_version_printed = 0;
11690         unsigned long tg3reg_base, tg3reg_len;
11691         struct net_device *dev;
11692         struct tg3 *tp;
11693         int i, err, pm_cap;
11694         char str[40];
11695         u64 dma_mask, persist_dma_mask;
11696
11697         if (tg3_version_printed++ == 0)
11698                 printk(KERN_INFO "%s", version);
11699
11700         err = pci_enable_device(pdev);
11701         if (err) {
11702                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11703                        "aborting.\n");
11704                 return err;
11705         }
11706
11707         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11708                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11709                        "base address, aborting.\n");
11710                 err = -ENODEV;
11711                 goto err_out_disable_pdev;
11712         }
11713
11714         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11715         if (err) {
11716                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11717                        "aborting.\n");
11718                 goto err_out_disable_pdev;
11719         }
11720
11721         pci_set_master(pdev);
11722
11723         /* Find power-management capability. */
11724         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11725         if (pm_cap == 0) {
11726                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11727                        "aborting.\n");
11728                 err = -EIO;
11729                 goto err_out_free_res;
11730         }
11731
11732         tg3reg_base = pci_resource_start(pdev, 0);
11733         tg3reg_len = pci_resource_len(pdev, 0);
11734
11735         dev = alloc_etherdev(sizeof(*tp));
11736         if (!dev) {
11737                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11738                 err = -ENOMEM;
11739                 goto err_out_free_res;
11740         }
11741
11742         SET_MODULE_OWNER(dev);
11743         SET_NETDEV_DEV(dev, &pdev->dev);
11744
11745 #if TG3_VLAN_TAG_USED
11746         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11747         dev->vlan_rx_register = tg3_vlan_rx_register;
11748         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11749 #endif
11750
11751         tp = netdev_priv(dev);
11752         tp->pdev = pdev;
11753         tp->dev = dev;
11754         tp->pm_cap = pm_cap;
11755         tp->mac_mode = TG3_DEF_MAC_MODE;
11756         tp->rx_mode = TG3_DEF_RX_MODE;
11757         tp->tx_mode = TG3_DEF_TX_MODE;
11758         tp->mi_mode = MAC_MI_MODE_BASE;
11759         if (tg3_debug > 0)
11760                 tp->msg_enable = tg3_debug;
11761         else
11762                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11763
11764         /* The word/byte swap controls here control register access byte
11765          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11766          * setting below.
11767          */
11768         tp->misc_host_ctrl =
11769                 MISC_HOST_CTRL_MASK_PCI_INT |
11770                 MISC_HOST_CTRL_WORD_SWAP |
11771                 MISC_HOST_CTRL_INDIR_ACCESS |
11772                 MISC_HOST_CTRL_PCISTATE_RW;
11773
11774         /* The NONFRM (non-frame) byte/word swap controls take effect
11775          * on descriptor entries, anything which isn't packet data.
11776          *
11777          * The StrongARM chips on the board (one for tx, one for rx)
11778          * are running in big-endian mode.
11779          */
11780         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11781                         GRC_MODE_WSWAP_NONFRM_DATA);
11782 #ifdef __BIG_ENDIAN
11783         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11784 #endif
11785         spin_lock_init(&tp->lock);
11786         spin_lock_init(&tp->indirect_lock);
11787         INIT_WORK(&tp->reset_task, tg3_reset_task);
11788
11789         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11790         if (tp->regs == 0UL) {
11791                 printk(KERN_ERR PFX "Cannot map device registers, "
11792                        "aborting.\n");
11793                 err = -ENOMEM;
11794                 goto err_out_free_dev;
11795         }
11796
11797         tg3_init_link_config(tp);
11798
11799         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11800         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11801         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11802
11803         dev->open = tg3_open;
11804         dev->stop = tg3_close;
11805         dev->get_stats = tg3_get_stats;
11806         dev->set_multicast_list = tg3_set_rx_mode;
11807         dev->set_mac_address = tg3_set_mac_addr;
11808         dev->do_ioctl = tg3_ioctl;
11809         dev->tx_timeout = tg3_tx_timeout;
11810         dev->poll = tg3_poll;
11811         dev->ethtool_ops = &tg3_ethtool_ops;
11812         dev->weight = 64;
11813         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11814         dev->change_mtu = tg3_change_mtu;
11815         dev->irq = pdev->irq;
11816 #ifdef CONFIG_NET_POLL_CONTROLLER
11817         dev->poll_controller = tg3_poll_controller;
11818 #endif
11819
11820         err = tg3_get_invariants(tp);
11821         if (err) {
11822                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11823                        "aborting.\n");
11824                 goto err_out_iounmap;
11825         }
11826
11827         /* The EPB bridge inside 5714, 5715, and 5780 and any
11828          * device behind the EPB cannot support DMA addresses > 40-bit.
11829          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11830          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11831          * do DMA address check in tg3_start_xmit().
11832          */
11833         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11834                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11835         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11836                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11837 #ifdef CONFIG_HIGHMEM
11838                 dma_mask = DMA_64BIT_MASK;
11839 #endif
11840         } else
11841                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11842
11843         /* Configure DMA attributes. */
11844         if (dma_mask > DMA_32BIT_MASK) {
11845                 err = pci_set_dma_mask(pdev, dma_mask);
11846                 if (!err) {
11847                         dev->features |= NETIF_F_HIGHDMA;
11848                         err = pci_set_consistent_dma_mask(pdev,
11849                                                           persist_dma_mask);
11850                         if (err < 0) {
11851                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11852                                        "DMA for consistent allocations\n");
11853                                 goto err_out_iounmap;
11854                         }
11855                 }
11856         }
11857         if (err || dma_mask == DMA_32BIT_MASK) {
11858                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11859                 if (err) {
11860                         printk(KERN_ERR PFX "No usable DMA configuration, "
11861                                "aborting.\n");
11862                         goto err_out_iounmap;
11863                 }
11864         }
11865
11866         tg3_init_bufmgr_config(tp);
11867
11868         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11869                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11870         }
11871         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11872             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11873             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11874             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11875             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11876                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11877         } else {
11878                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11879         }
11880
11881         /* TSO is on by default on chips that support hardware TSO.
11882          * Firmware TSO on older chips gives lower performance, so it
11883          * is off by default, but can be enabled using ethtool.
11884          */
11885         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11886                 dev->features |= NETIF_F_TSO;
11887                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11888                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11889                         dev->features |= NETIF_F_TSO6;
11890         }
11891
11892
11893         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11894             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11895             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11896                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11897                 tp->rx_pending = 63;
11898         }
11899
11900         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11901             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11902                 tp->pdev_peer = tg3_find_peer(tp);
11903
11904         err = tg3_get_device_address(tp);
11905         if (err) {
11906                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11907                        "aborting.\n");
11908                 goto err_out_iounmap;
11909         }
11910
11911         /*
11912          * Reset chip in case UNDI or EFI driver did not shutdown
11913          * DMA self test will enable WDMAC and we'll see (spurious)
11914          * pending DMA on the PCI bus at that point.
11915          */
11916         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11917             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11918                 pci_save_state(tp->pdev);
11919                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11920                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11921         }
11922
11923         err = tg3_test_dma(tp);
11924         if (err) {
11925                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11926                 goto err_out_iounmap;
11927         }
11928
11929         /* Tigon3 can do ipv4 only... and some chips have buggy
11930          * checksumming.
11931          */
11932         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11933                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11934                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11935                         dev->features |= NETIF_F_HW_CSUM;
11936                 else
11937                         dev->features |= NETIF_F_IP_CSUM;
11938                 dev->features |= NETIF_F_SG;
11939                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11940         } else
11941                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11942
11943         /* flow control autonegotiation is default behavior */
11944         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11945
11946         tg3_init_coal(tp);
11947
11948         /* Now that we have fully setup the chip, save away a snapshot
11949          * of the PCI config space.  We need to restore this after
11950          * GRC_MISC_CFG core clock resets and some resume events.
11951          */
11952         pci_save_state(tp->pdev);
11953
11954         pci_set_drvdata(pdev, dev);
11955
11956         err = register_netdev(dev);
11957         if (err) {
11958                 printk(KERN_ERR PFX "Cannot register net device, "
11959                        "aborting.\n");
11960                 goto err_out_iounmap;
11961         }
11962
11963         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
11964                dev->name,
11965                tp->board_part_number,
11966                tp->pci_chip_rev_id,
11967                tg3_phy_string(tp),
11968                tg3_bus_string(tp, str),
11969                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11970                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11971                  "10/100/1000Base-T")));
11972
11973         for (i = 0; i < 6; i++)
11974                 printk("%2.2x%c", dev->dev_addr[i],
11975                        i == 5 ? '\n' : ':');
11976
11977         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11978                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
11979                dev->name,
11980                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11981                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11982                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11983                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11984                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11985                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11986         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11987                dev->name, tp->dma_rwctrl,
11988                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11989                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11990
11991         return 0;
11992
11993 err_out_iounmap:
11994         if (tp->regs) {
11995                 iounmap(tp->regs);
11996                 tp->regs = NULL;
11997         }
11998
11999 err_out_free_dev:
12000         free_netdev(dev);
12001
12002 err_out_free_res:
12003         pci_release_regions(pdev);
12004
12005 err_out_disable_pdev:
12006         pci_disable_device(pdev);
12007         pci_set_drvdata(pdev, NULL);
12008         return err;
12009 }
12010
12011 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12012 {
12013         struct net_device *dev = pci_get_drvdata(pdev);
12014
12015         if (dev) {
12016                 struct tg3 *tp = netdev_priv(dev);
12017
12018                 flush_scheduled_work();
12019                 unregister_netdev(dev);
12020                 if (tp->regs) {
12021                         iounmap(tp->regs);
12022                         tp->regs = NULL;
12023                 }
12024                 free_netdev(dev);
12025                 pci_release_regions(pdev);
12026                 pci_disable_device(pdev);
12027                 pci_set_drvdata(pdev, NULL);
12028         }
12029 }
12030
12031 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12032 {
12033         struct net_device *dev = pci_get_drvdata(pdev);
12034         struct tg3 *tp = netdev_priv(dev);
12035         int err;
12036
12037         if (!netif_running(dev))
12038                 return 0;
12039
12040         flush_scheduled_work();
12041         tg3_netif_stop(tp);
12042
12043         del_timer_sync(&tp->timer);
12044
12045         tg3_full_lock(tp, 1);
12046         tg3_disable_ints(tp);
12047         tg3_full_unlock(tp);
12048
12049         netif_device_detach(dev);
12050
12051         tg3_full_lock(tp, 0);
12052         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12053         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12054         tg3_full_unlock(tp);
12055
12056         /* Save MSI address and data for resume.  */
12057         pci_save_state(pdev);
12058
12059         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12060         if (err) {
12061                 tg3_full_lock(tp, 0);
12062
12063                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12064                 if (tg3_restart_hw(tp, 1))
12065                         goto out;
12066
12067                 tp->timer.expires = jiffies + tp->timer_offset;
12068                 add_timer(&tp->timer);
12069
12070                 netif_device_attach(dev);
12071                 tg3_netif_start(tp);
12072
12073 out:
12074                 tg3_full_unlock(tp);
12075         }
12076
12077         return err;
12078 }
12079
12080 static int tg3_resume(struct pci_dev *pdev)
12081 {
12082         struct net_device *dev = pci_get_drvdata(pdev);
12083         struct tg3 *tp = netdev_priv(dev);
12084         int err;
12085
12086         if (!netif_running(dev))
12087                 return 0;
12088
12089         pci_restore_state(tp->pdev);
12090
12091         err = tg3_set_power_state(tp, PCI_D0);
12092         if (err)
12093                 return err;
12094
12095         netif_device_attach(dev);
12096
12097         tg3_full_lock(tp, 0);
12098
12099         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12100         err = tg3_restart_hw(tp, 1);
12101         if (err)
12102                 goto out;
12103
12104         tp->timer.expires = jiffies + tp->timer_offset;
12105         add_timer(&tp->timer);
12106
12107         tg3_netif_start(tp);
12108
12109 out:
12110         tg3_full_unlock(tp);
12111
12112         return err;
12113 }
12114
12115 static struct pci_driver tg3_driver = {
12116         .name           = DRV_MODULE_NAME,
12117         .id_table       = tg3_pci_tbl,
12118         .probe          = tg3_init_one,
12119         .remove         = __devexit_p(tg3_remove_one),
12120         .suspend        = tg3_suspend,
12121         .resume         = tg3_resume
12122 };
12123
12124 static int __init tg3_init(void)
12125 {
12126         return pci_register_driver(&tg3_driver);
12127 }
12128
12129 static void __exit tg3_cleanup(void)
12130 {
12131         pci_unregister_driver(&tg3_driver);
12132 }
12133
12134 module_init(tg3_init);
12135 module_exit(tg3_cleanup);