drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.101"
  72 #define DRV_MODULE_RELDATE      "August 28, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 120                                  TG3_RX_RING_SIZE)
 121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 122                                  TG3_RX_JUMBO_RING_SIZE)
 123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RCB_RING_SIZE(tp))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define TG3_DMA_BYTE_ENAB               64
 130
 131 #define TG3_RX_STD_DMA_SZ               1536
 132 #define TG3_RX_JMB_DMA_SZ               9046
 133
 134 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 135
 136 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 137 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 138
 139 /* minimum number of free TX descriptors required to wake up TX process */
 140 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 141
 142 #define TG3_RAW_IP_ALIGN 2
 143
 144 /* number of ETHTOOL_GSTATS u64's */
 145 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 146
 147 #define TG3_NUM_TEST            6
 148
 149 #define FIRMWARE_TG3            "tigon/tg3.bin"
 150 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 151 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 152
 153 static char version[] __devinitdata =
 154         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 155
 156 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 157 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 158 MODULE_LICENSE("GPL");
 159 MODULE_VERSION(DRV_MODULE_VERSION);
 160 MODULE_FIRMWARE(FIRMWARE_TG3);
 161 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 162 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 163
 164 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 165
 166 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 167 module_param(tg3_debug, int, 0);
 168 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 169
 170 static struct pci_device_id tg3_pci_tbl[] = {
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 244         {}
 245 };
 246
 247 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 248
 249 static const struct {
 250         const char string[ETH_GSTRING_LEN];
 251 } ethtool_stats_keys[TG3_NUM_STATS] = {
 252         { "rx_octets" },
 253         { "rx_fragments" },
 254         { "rx_ucast_packets" },
 255         { "rx_mcast_packets" },
 256         { "rx_bcast_packets" },
 257         { "rx_fcs_errors" },
 258         { "rx_align_errors" },
 259         { "rx_xon_pause_rcvd" },
 260         { "rx_xoff_pause_rcvd" },
 261         { "rx_mac_ctrl_rcvd" },
 262         { "rx_xoff_entered" },
 263         { "rx_frame_too_long_errors" },
 264         { "rx_jabbers" },
 265         { "rx_undersize_packets" },
 266         { "rx_in_length_errors" },
 267         { "rx_out_length_errors" },
 268         { "rx_64_or_less_octet_packets" },
 269         { "rx_65_to_127_octet_packets" },
 270         { "rx_128_to_255_octet_packets" },
 271         { "rx_256_to_511_octet_packets" },
 272         { "rx_512_to_1023_octet_packets" },
 273         { "rx_1024_to_1522_octet_packets" },
 274         { "rx_1523_to_2047_octet_packets" },
 275         { "rx_2048_to_4095_octet_packets" },
 276         { "rx_4096_to_8191_octet_packets" },
 277         { "rx_8192_to_9022_octet_packets" },
 278
 279         { "tx_octets" },
 280         { "tx_collisions" },
 281
 282         { "tx_xon_sent" },
 283         { "tx_xoff_sent" },
 284         { "tx_flow_control" },
 285         { "tx_mac_errors" },
 286         { "tx_single_collisions" },
 287         { "tx_mult_collisions" },
 288         { "tx_deferred" },
 289         { "tx_excessive_collisions" },
 290         { "tx_late_collisions" },
 291         { "tx_collide_2times" },
 292         { "tx_collide_3times" },
 293         { "tx_collide_4times" },
 294         { "tx_collide_5times" },
 295         { "tx_collide_6times" },
 296         { "tx_collide_7times" },
 297         { "tx_collide_8times" },
 298         { "tx_collide_9times" },
 299         { "tx_collide_10times" },
 300         { "tx_collide_11times" },
 301         { "tx_collide_12times" },
 302         { "tx_collide_13times" },
 303         { "tx_collide_14times" },
 304         { "tx_collide_15times" },
 305         { "tx_ucast_packets" },
 306         { "tx_mcast_packets" },
 307         { "tx_bcast_packets" },
 308         { "tx_carrier_sense_errors" },
 309         { "tx_discards" },
 310         { "tx_errors" },
 311
 312         { "dma_writeq_full" },
 313         { "dma_write_prioq_full" },
 314         { "rxbds_empty" },
 315         { "rx_discards" },
 316         { "rx_errors" },
 317         { "rx_threshold_hit" },
 318
 319         { "dma_readq_full" },
 320         { "dma_read_prioq_full" },
 321         { "tx_comp_queue_full" },
 322
 323         { "ring_set_send_prod_index" },
 324         { "ring_status_update" },
 325         { "nic_irqs" },
 326         { "nic_avoided_irqs" },
 327         { "nic_tx_threshold_hit" }
 328 };
 329
 330 static const struct {
 331         const char string[ETH_GSTRING_LEN];
 332 } ethtool_test_keys[TG3_NUM_TEST] = {
 333         { "nvram test     (online) " },
 334         { "link test      (online) " },
 335         { "register test  (offline)" },
 336         { "memory test    (offline)" },
 337         { "loopback test  (offline)" },
 338         { "interrupt test (offline)" },
 339 };
 340
 341 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 342 {
 343         writel(val, tp->regs + off);
 344 }
 345
 346 static u32 tg3_read32(struct tg3 *tp, u32 off)
 347 {
 348         return (readl(tp->regs + off));
 349 }
 350
 351 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         writel(val, tp->aperegs + off);
 354 }
 355
 356 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 357 {
 358         return (readl(tp->aperegs + off));
 359 }
 360
 361 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         unsigned long flags;
 364
 365         spin_lock_irqsave(&tp->indirect_lock, flags);
 366         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 367         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 368         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 369 }
 370
 371 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 372 {
 373         writel(val, tp->regs + off);
 374         readl(tp->regs + off);
 375 }
 376
 377 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 378 {
 379         unsigned long flags;
 380         u32 val;
 381
 382         spin_lock_irqsave(&tp->indirect_lock, flags);
 383         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 384         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 385         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 386         return val;
 387 }
 388
 389 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 390 {
 391         unsigned long flags;
 392
 393         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 394                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 395                                        TG3_64BIT_REG_LOW, val);
 396                 return;
 397         }
 398         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 399                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 400                                        TG3_64BIT_REG_LOW, val);
 401                 return;
 402         }
 403
 404         spin_lock_irqsave(&tp->indirect_lock, flags);
 405         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 407         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 408
 409         /* In indirect mode when disabling interrupts, we also need
 410          * to clear the interrupt bit in the GRC local ctrl register.
 411          */
 412         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 413             (val == 0x1)) {
 414                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 415                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 416         }
 417 }
 418
 419 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 420 {
 421         unsigned long flags;
 422         u32 val;
 423
 424         spin_lock_irqsave(&tp->indirect_lock, flags);
 425         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 426         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 427         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 428         return val;
 429 }
 430
 431 /* usec_wait specifies the wait time in usec when writing to certain registers
 432  * where it is unsafe to read back the register without some delay.
 433  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 434  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 435  */
 436 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 437 {
 438         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 439             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 440                 /* Non-posted methods */
 441                 tp->write32(tp, off, val);
 442         else {
 443                 /* Posted method */
 444                 tg3_write32(tp, off, val);
 445                 if (usec_wait)
 446                         udelay(usec_wait);
 447                 tp->read32(tp, off);
 448         }
 449         /* Wait again after the read for the posted method to guarantee that
 450          * the wait time is met.
 451          */
 452         if (usec_wait)
 453                 udelay(usec_wait);
 454 }
 455
 456 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 457 {
 458         tp->write32_mbox(tp, off, val);
 459         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 460             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 461                 tp->read32_mbox(tp, off);
 462 }
 463
 464 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 465 {
 466         void __iomem *mbox = tp->regs + off;
 467         writel(val, mbox);
 468         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 469                 writel(val, mbox);
 470         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 471                 readl(mbox);
 472 }
 473
 474 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 475 {
 476         return (readl(tp->regs + off + GRCMBOX_BASE));
 477 }
 478
 479 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 480 {
 481         writel(val, tp->regs + off + GRCMBOX_BASE);
 482 }
 483
 484 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 485 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 486 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 487 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 488 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 489
 490 #define tw32(reg,val)           tp->write32(tp, reg, val)
 491 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 492 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 493 #define tr32(reg)               tp->read32(tp, reg)
 494
 495 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 496 {
 497         unsigned long flags;
 498
 499         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 500             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 501                 return;
 502
 503         spin_lock_irqsave(&tp->indirect_lock, flags);
 504         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 505                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 507
 508                 /* Always leave this as zero. */
 509                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 510         } else {
 511                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 512                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 513
 514                 /* Always leave this as zero. */
 515                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 516         }
 517         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 518 }
 519
 520 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 521 {
 522         unsigned long flags;
 523
 524         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 525             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 526                 *val = 0;
 527                 return;
 528         }
 529
 530         spin_lock_irqsave(&tp->indirect_lock, flags);
 531         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 532                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 533                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 534
 535                 /* Always leave this as zero. */
 536                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 537         } else {
 538                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 539                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 540
 541                 /* Always leave this as zero. */
 542                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 543         }
 544         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 545 }
 546
 547 static void tg3_ape_lock_init(struct tg3 *tp)
 548 {
 549         int i;
 550
 551         /* Make sure the driver hasn't any stale locks. */
 552         for (i = 0; i < 8; i++)
 553                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 554                                 APE_LOCK_GRANT_DRIVER);
 555 }
 556
 557 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 558 {
 559         int i, off;
 560         int ret = 0;
 561         u32 status;
 562
 563         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 564                 return 0;
 565
 566         switch (locknum) {
 567                 case TG3_APE_LOCK_GRC:
 568                 case TG3_APE_LOCK_MEM:
 569                         break;
 570                 default:
 571                         return -EINVAL;
 572         }
 573
 574         off = 4 * locknum;
 575
 576         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 577
 578         /* Wait for up to 1 millisecond to acquire lock. */
 579         for (i = 0; i < 100; i++) {
 580                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 581                 if (status == APE_LOCK_GRANT_DRIVER)
 582                         break;
 583                 udelay(10);
 584         }
 585
 586         if (status != APE_LOCK_GRANT_DRIVER) {
 587                 /* Revoke the lock request. */
 588                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 589                                 APE_LOCK_GRANT_DRIVER);
 590
 591                 ret = -EBUSY;
 592         }
 593
 594         return ret;
 595 }
 596
 597 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 598 {
 599         int off;
 600
 601         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 602                 return;
 603
 604         switch (locknum) {
 605                 case TG3_APE_LOCK_GRC:
 606                 case TG3_APE_LOCK_MEM:
 607                         break;
 608                 default:
 609                         return;
 610         }
 611
 612         off = 4 * locknum;
 613         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 614 }
 615
 616 static void tg3_disable_ints(struct tg3 *tp)
 617 {
 618         int i;
 619
 620         tw32(TG3PCI_MISC_HOST_CTRL,
 621              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 622         for (i = 0; i < tp->irq_max; i++)
 623                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 624 }
 625
 626 static void tg3_enable_ints(struct tg3 *tp)
 627 {
 628         int i;
 629         u32 coal_now = 0;
 630
 631         tp->irq_sync = 0;
 632         wmb();
 633
 634         tw32(TG3PCI_MISC_HOST_CTRL,
 635              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 636
 637         for (i = 0; i < tp->irq_cnt; i++) {
 638                 struct tg3_napi *tnapi = &tp->napi[i];
 639                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 640                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 641                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 642
 643                 coal_now |= tnapi->coal_now;
 644         }
 645
 646         /* Force an initial interrupt */
 647         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 648             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 649                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 650         else
 651                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 652                      HOSTCC_MODE_ENABLE | coal_now);
 653 }
 654
 655 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 656 {
 657         struct tg3 *tp = tnapi->tp;
 658         struct tg3_hw_status *sblk = tnapi->hw_status;
 659         unsigned int work_exists = 0;
 660
 661         /* check for phy events */
 662         if (!(tp->tg3_flags &
 663               (TG3_FLAG_USE_LINKCHG_REG |
 664                TG3_FLAG_POLL_SERDES))) {
 665                 if (sblk->status & SD_STATUS_LINK_CHG)
 666                         work_exists = 1;
 667         }
 668         /* check for RX/TX work to do */
 669         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 670             sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
 671                 work_exists = 1;
 672
 673         return work_exists;
 674 }
 675
 676 /* tg3_int_reenable
 677  *  similar to tg3_enable_ints, but it accurately determines whether there
 678  *  is new work pending and can return without flushing the PIO write
 679  *  which reenables interrupts
 680  */
 681 static void tg3_int_reenable(struct tg3_napi *tnapi)
 682 {
 683         struct tg3 *tp = tnapi->tp;
 684
 685         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 686         mmiowb();
 687
 688         /* When doing tagged status, this work check is unnecessary.
 689          * The last_tag we write above tells the chip which piece of
 690          * work we've completed.
 691          */
 692         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 693             tg3_has_work(tnapi))
 694                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 695                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 696 }
 697
 698 static void tg3_napi_disable(struct tg3 *tp)
 699 {
 700         int i;
 701
 702         for (i = tp->irq_cnt - 1; i >= 0; i--)
 703                 napi_disable(&tp->napi[i].napi);
 704 }
 705
 706 static void tg3_napi_enable(struct tg3 *tp)
 707 {
 708         int i;
 709
 710         for (i = 0; i < tp->irq_cnt; i++)
 711                 napi_enable(&tp->napi[i].napi);
 712 }
 713
 714 static inline void tg3_netif_stop(struct tg3 *tp)
 715 {
 716         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 717         tg3_napi_disable(tp);
 718         netif_tx_disable(tp->dev);
 719 }
 720
 721 static inline void tg3_netif_start(struct tg3 *tp)
 722 {
 723         /* NOTE: unconditional netif_tx_wake_all_queues is only
 724          * appropriate so long as all callers are assured to
 725          * have free tx slots (such as after tg3_init_hw)
 726          */
 727         netif_tx_wake_all_queues(tp->dev);
 728
 729         tg3_napi_enable(tp);
 730         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 731         tg3_enable_ints(tp);
 732 }
 733
 734 static void tg3_switch_clocks(struct tg3 *tp)
 735 {
 736         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 737         u32 orig_clock_ctrl;
 738
 739         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 740             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 741                 return;
 742
 743         orig_clock_ctrl = clock_ctrl;
 744         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 745                        CLOCK_CTRL_CLKRUN_OENABLE |
 746                        0x1f);
 747         tp->pci_clock_ctrl = clock_ctrl;
 748
 749         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 750                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 751                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 752                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 753                 }
 754         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 755                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 756                             clock_ctrl |
 757                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 758                             40);
 759                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 760                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 761                             40);
 762         }
 763         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 764 }
 765
 766 #define PHY_BUSY_LOOPS  5000
 767
 768 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 769 {
 770         u32 frame_val;
 771         unsigned int loops;
 772         int ret;
 773
 774         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 775                 tw32_f(MAC_MI_MODE,
 776                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 777                 udelay(80);
 778         }
 779
 780         *val = 0x0;
 781
 782         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 783                       MI_COM_PHY_ADDR_MASK);
 784         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 785                       MI_COM_REG_ADDR_MASK);
 786         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 787
 788         tw32_f(MAC_MI_COM, frame_val);
 789
 790         loops = PHY_BUSY_LOOPS;
 791         while (loops != 0) {
 792                 udelay(10);
 793                 frame_val = tr32(MAC_MI_COM);
 794
 795                 if ((frame_val & MI_COM_BUSY) == 0) {
 796                         udelay(5);
 797                         frame_val = tr32(MAC_MI_COM);
 798                         break;
 799                 }
 800                 loops -= 1;
 801         }
 802
 803         ret = -EBUSY;
 804         if (loops != 0) {
 805                 *val = frame_val & MI_COM_DATA_MASK;
 806                 ret = 0;
 807         }
 808
 809         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 810                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 811                 udelay(80);
 812         }
 813
 814         return ret;
 815 }
 816
 817 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 818 {
 819         u32 frame_val;
 820         unsigned int loops;
 821         int ret;
 822
 823         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 824             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 825                 return 0;
 826
 827         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 828                 tw32_f(MAC_MI_MODE,
 829                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 830                 udelay(80);
 831         }
 832
 833         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 834                       MI_COM_PHY_ADDR_MASK);
 835         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 836                       MI_COM_REG_ADDR_MASK);
 837         frame_val |= (val & MI_COM_DATA_MASK);
 838         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 839
 840         tw32_f(MAC_MI_COM, frame_val);
 841
 842         loops = PHY_BUSY_LOOPS;
 843         while (loops != 0) {
 844                 udelay(10);
 845                 frame_val = tr32(MAC_MI_COM);
 846                 if ((frame_val & MI_COM_BUSY) == 0) {
 847                         udelay(5);
 848                         frame_val = tr32(MAC_MI_COM);
 849                         break;
 850                 }
 851                 loops -= 1;
 852         }
 853
 854         ret = -EBUSY;
 855         if (loops != 0)
 856                 ret = 0;
 857
 858         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 859                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 860                 udelay(80);
 861         }
 862
 863         return ret;
 864 }
 865
 866 static int tg3_bmcr_reset(struct tg3 *tp)
 867 {
 868         u32 phy_control;
 869         int limit, err;
 870
 871         /* OK, reset it, and poll the BMCR_RESET bit until it
 872          * clears or we time out.
 873          */
 874         phy_control = BMCR_RESET;
 875         err = tg3_writephy(tp, MII_BMCR, phy_control);
 876         if (err != 0)
 877                 return -EBUSY;
 878
 879         limit = 5000;
 880         while (limit--) {
 881                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 882                 if (err != 0)
 883                         return -EBUSY;
 884
 885                 if ((phy_control & BMCR_RESET) == 0) {
 886                         udelay(40);
 887                         break;
 888                 }
 889                 udelay(10);
 890         }
 891         if (limit < 0)
 892                 return -EBUSY;
 893
 894         return 0;
 895 }
 896
 897 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 898 {
 899         struct tg3 *tp = bp->priv;
 900         u32 val;
 901
 902         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 903                 return -EAGAIN;
 904
 905         if (tg3_readphy(tp, reg, &val))
 906                 return -EIO;
 907
 908         return val;
 909 }
 910
 911 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 912 {
 913         struct tg3 *tp = bp->priv;
 914
 915         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 916                 return -EAGAIN;
 917
 918         if (tg3_writephy(tp, reg, val))
 919                 return -EIO;
 920
 921         return 0;
 922 }
 923
 924 static int tg3_mdio_reset(struct mii_bus *bp)
 925 {
 926         return 0;
 927 }
 928
 929 static void tg3_mdio_config_5785(struct tg3 *tp)
 930 {
 931         u32 val;
 932         struct phy_device *phydev;
 933
 934         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 935         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 936         case TG3_PHY_ID_BCM50610:
 937                 val = MAC_PHYCFG2_50610_LED_MODES;
 938                 break;
 939         case TG3_PHY_ID_BCMAC131:
 940                 val = MAC_PHYCFG2_AC131_LED_MODES;
 941                 break;
 942         case TG3_PHY_ID_RTL8211C:
 943                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 944                 break;
 945         case TG3_PHY_ID_RTL8201E:
 946                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 947                 break;
 948         default:
 949                 return;
 950         }
 951
 952         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 953                 tw32(MAC_PHYCFG2, val);
 954
 955                 val = tr32(MAC_PHYCFG1);
 956                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 957                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 958                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 959                 tw32(MAC_PHYCFG1, val);
 960
 961                 return;
 962         }
 963
 964         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 965                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 966                        MAC_PHYCFG2_FMODE_MASK_MASK |
 967                        MAC_PHYCFG2_GMODE_MASK_MASK |
 968                        MAC_PHYCFG2_ACT_MASK_MASK   |
 969                        MAC_PHYCFG2_QUAL_MASK_MASK |
 970                        MAC_PHYCFG2_INBAND_ENABLE;
 971
 972         tw32(MAC_PHYCFG2, val);
 973
 974         val = tr32(MAC_PHYCFG1);
 975         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 976                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 977         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 978                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 979                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 980                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 981                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 982         }
 983         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 984                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 985         tw32(MAC_PHYCFG1, val);
 986
 987         val = tr32(MAC_EXT_RGMII_MODE);
 988         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 989                  MAC_RGMII_MODE_RX_QUALITY |
 990                  MAC_RGMII_MODE_RX_ACTIVITY |
 991                  MAC_RGMII_MODE_RX_ENG_DET |
 992                  MAC_RGMII_MODE_TX_ENABLE |
 993                  MAC_RGMII_MODE_TX_LOWPWR |
 994                  MAC_RGMII_MODE_TX_RESET);
 995         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 996                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 997                         val |= MAC_RGMII_MODE_RX_INT_B |
 998                                MAC_RGMII_MODE_RX_QUALITY |
 999                                MAC_RGMII_MODE_RX_ACTIVITY |
1000                                MAC_RGMII_MODE_RX_ENG_DET;
1001                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1002                         val |= MAC_RGMII_MODE_TX_ENABLE |
1003                                MAC_RGMII_MODE_TX_LOWPWR |
1004                                MAC_RGMII_MODE_TX_RESET;
1005         }
1006         tw32(MAC_EXT_RGMII_MODE, val);
1007 }
1008
1009 static void tg3_mdio_start(struct tg3 *tp)
1010 {
1011         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1012                 mutex_lock(&tp->mdio_bus->mdio_lock);
1013                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1014                 mutex_unlock(&tp->mdio_bus->mdio_lock);
1015         }
1016
1017         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1018         tw32_f(MAC_MI_MODE, tp->mi_mode);
1019         udelay(80);
1020
1021         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1022             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1023                 tg3_mdio_config_5785(tp);
1024 }
1025
1026 static void tg3_mdio_stop(struct tg3 *tp)
1027 {
1028         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1029                 mutex_lock(&tp->mdio_bus->mdio_lock);
1030                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
1031                 mutex_unlock(&tp->mdio_bus->mdio_lock);
1032         }
1033 }
1034
1035 static int tg3_mdio_init(struct tg3 *tp)
1036 {
1037         int i;
1038         u32 reg;
1039         struct phy_device *phydev;
1040
1041         tg3_mdio_start(tp);
1042
1043         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1044             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1045                 return 0;
1046
1047         tp->mdio_bus = mdiobus_alloc();
1048         if (tp->mdio_bus == NULL)
1049                 return -ENOMEM;
1050
1051         tp->mdio_bus->name     = "tg3 mdio bus";
1052         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1053                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1054         tp->mdio_bus->priv     = tp;
1055         tp->mdio_bus->parent   = &tp->pdev->dev;
1056         tp->mdio_bus->read     = &tg3_mdio_read;
1057         tp->mdio_bus->write    = &tg3_mdio_write;
1058         tp->mdio_bus->reset    = &tg3_mdio_reset;
1059         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1060         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1061
1062         for (i = 0; i < PHY_MAX_ADDR; i++)
1063                 tp->mdio_bus->irq[i] = PHY_POLL;
1064
1065         /* The bus registration will look for all the PHYs on the mdio bus.
1066          * Unfortunately, it does not ensure the PHY is powered up before
1067          * accessing the PHY ID registers.  A chip reset is the
1068          * quickest way to bring the device back to an operational state..
1069          */
1070         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1071                 tg3_bmcr_reset(tp);
1072
1073         i = mdiobus_register(tp->mdio_bus);
1074         if (i) {
1075                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1076                         tp->dev->name, i);
1077                 mdiobus_free(tp->mdio_bus);
1078                 return i;
1079         }
1080
1081         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1082
1083         if (!phydev || !phydev->drv) {
1084                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1085                 mdiobus_unregister(tp->mdio_bus);
1086                 mdiobus_free(tp->mdio_bus);
1087                 return -ENODEV;
1088         }
1089
1090         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1091         case TG3_PHY_ID_BCM57780:
1092                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1093                 break;
1094         case TG3_PHY_ID_BCM50610:
1095                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1096                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1097                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1098                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1099                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1100                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1101                 /* fallthru */
1102         case TG3_PHY_ID_RTL8211C:
1103                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1104                 break;
1105         case TG3_PHY_ID_RTL8201E:
1106         case TG3_PHY_ID_BCMAC131:
1107                 phydev->interface = PHY_INTERFACE_MODE_MII;
1108                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1109                 break;
1110         }
1111
1112         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1113
1114         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1115                 tg3_mdio_config_5785(tp);
1116
1117         return 0;
1118 }
1119
1120 static void tg3_mdio_fini(struct tg3 *tp)
1121 {
1122         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1123                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1124                 mdiobus_unregister(tp->mdio_bus);
1125                 mdiobus_free(tp->mdio_bus);
1126                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1127         }
1128 }
1129
1130 /* tp->lock is held. */
1131 static inline void tg3_generate_fw_event(struct tg3 *tp)
1132 {
1133         u32 val;
1134
1135         val = tr32(GRC_RX_CPU_EVENT);
1136         val |= GRC_RX_CPU_DRIVER_EVENT;
1137         tw32_f(GRC_RX_CPU_EVENT, val);
1138
1139         tp->last_event_jiffies = jiffies;
1140 }
1141
1142 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1143
1144 /* tp->lock is held. */
1145 static void tg3_wait_for_event_ack(struct tg3 *tp)
1146 {
1147         int i;
1148         unsigned int delay_cnt;
1149         long time_remain;
1150
1151         /* If enough time has passed, no wait is necessary. */
1152         time_remain = (long)(tp->last_event_jiffies + 1 +
1153                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1154                       (long)jiffies;
1155         if (time_remain < 0)
1156                 return;
1157
1158         /* Check if we can shorten the wait time. */
1159         delay_cnt = jiffies_to_usecs(time_remain);
1160         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1161                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1162         delay_cnt = (delay_cnt >> 3) + 1;
1163
1164         for (i = 0; i < delay_cnt; i++) {
1165                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1166                         break;
1167                 udelay(8);
1168         }
1169 }
1170
1171 /* tp->lock is held. */
1172 static void tg3_ump_link_report(struct tg3 *tp)
1173 {
1174         u32 reg;
1175         u32 val;
1176
1177         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1178             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1179                 return;
1180
1181         tg3_wait_for_event_ack(tp);
1182
1183         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1184
1185         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1186
1187         val = 0;
1188         if (!tg3_readphy(tp, MII_BMCR, &reg))
1189                 val = reg << 16;
1190         if (!tg3_readphy(tp, MII_BMSR, &reg))
1191                 val |= (reg & 0xffff);
1192         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1193
1194         val = 0;
1195         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1196                 val = reg << 16;
1197         if (!tg3_readphy(tp, MII_LPA, &reg))
1198                 val |= (reg & 0xffff);
1199         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1200
1201         val = 0;
1202         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1203                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1204                         val = reg << 16;
1205                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1206                         val |= (reg & 0xffff);
1207         }
1208         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1209
1210         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1211                 val = reg << 16;
1212         else
1213                 val = 0;
1214         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1215
1216         tg3_generate_fw_event(tp);
1217 }
1218
1219 static void tg3_link_report(struct tg3 *tp)
1220 {
1221         if (!netif_carrier_ok(tp->dev)) {
1222                 if (netif_msg_link(tp))
1223                         printk(KERN_INFO PFX "%s: Link is down.\n",
1224                                tp->dev->name);
1225                 tg3_ump_link_report(tp);
1226         } else if (netif_msg_link(tp)) {
1227                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1228                        tp->dev->name,
1229                        (tp->link_config.active_speed == SPEED_1000 ?
1230                         1000 :
1231                         (tp->link_config.active_speed == SPEED_100 ?
1232                          100 : 10)),
1233                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1234                         "full" : "half"));
1235
1236                 printk(KERN_INFO PFX
1237                        "%s: Flow control is %s for TX and %s for RX.\n",
1238                        tp->dev->name,
1239                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1240                        "on" : "off",
1241                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1242                        "on" : "off");
1243                 tg3_ump_link_report(tp);
1244         }
1245 }
1246
1247 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1248 {
1249         u16 miireg;
1250
1251         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1252                 miireg = ADVERTISE_PAUSE_CAP;
1253         else if (flow_ctrl & FLOW_CTRL_TX)
1254                 miireg = ADVERTISE_PAUSE_ASYM;
1255         else if (flow_ctrl & FLOW_CTRL_RX)
1256                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1257         else
1258                 miireg = 0;
1259
1260         return miireg;
1261 }
1262
1263 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1264 {
1265         u16 miireg;
1266
1267         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1268                 miireg = ADVERTISE_1000XPAUSE;
1269         else if (flow_ctrl & FLOW_CTRL_TX)
1270                 miireg = ADVERTISE_1000XPSE_ASYM;
1271         else if (flow_ctrl & FLOW_CTRL_RX)
1272                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1273         else
1274                 miireg = 0;
1275
1276         return miireg;
1277 }
1278
1279 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1280 {
1281         u8 cap = 0;
1282
1283         if (lcladv & ADVERTISE_1000XPAUSE) {
1284                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1285                         if (rmtadv & LPA_1000XPAUSE)
1286                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1287                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1288                                 cap = FLOW_CTRL_RX;
1289                 } else {
1290                         if (rmtadv & LPA_1000XPAUSE)
1291                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1292                 }
1293         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1294                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1295                         cap = FLOW_CTRL_TX;
1296         }
1297
1298         return cap;
1299 }
1300
1301 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1302 {
1303         u8 autoneg;
1304         u8 flowctrl = 0;
1305         u32 old_rx_mode = tp->rx_mode;
1306         u32 old_tx_mode = tp->tx_mode;
1307
1308         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1309                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1310         else
1311                 autoneg = tp->link_config.autoneg;
1312
1313         if (autoneg == AUTONEG_ENABLE &&
1314             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1315                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1316                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1317                 else
1318                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1319         } else
1320                 flowctrl = tp->link_config.flowctrl;
1321
1322         tp->link_config.active_flowctrl = flowctrl;
1323
1324         if (flowctrl & FLOW_CTRL_RX)
1325                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1326         else
1327                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1328
1329         if (old_rx_mode != tp->rx_mode)
1330                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1331
1332         if (flowctrl & FLOW_CTRL_TX)
1333                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1334         else
1335                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1336
1337         if (old_tx_mode != tp->tx_mode)
1338                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1339 }
1340
1341 static void tg3_adjust_link(struct net_device *dev)
1342 {
1343         u8 oldflowctrl, linkmesg = 0;
1344         u32 mac_mode, lcl_adv, rmt_adv;
1345         struct tg3 *tp = netdev_priv(dev);
1346         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1347
1348         spin_lock(&tp->lock);
1349
1350         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1351                                     MAC_MODE_HALF_DUPLEX);
1352
1353         oldflowctrl = tp->link_config.active_flowctrl;
1354
1355         if (phydev->link) {
1356                 lcl_adv = 0;
1357                 rmt_adv = 0;
1358
1359                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1360                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1361                 else
1362                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1363
1364                 if (phydev->duplex == DUPLEX_HALF)
1365                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1366                 else {
1367                         lcl_adv = tg3_advert_flowctrl_1000T(
1368                                   tp->link_config.flowctrl);
1369
1370                         if (phydev->pause)
1371                                 rmt_adv = LPA_PAUSE_CAP;
1372                         if (phydev->asym_pause)
1373                                 rmt_adv |= LPA_PAUSE_ASYM;
1374                 }
1375
1376                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1377         } else
1378                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1379
1380         if (mac_mode != tp->mac_mode) {
1381                 tp->mac_mode = mac_mode;
1382                 tw32_f(MAC_MODE, tp->mac_mode);
1383                 udelay(40);
1384         }
1385
1386         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1387                 if (phydev->speed == SPEED_10)
1388                         tw32(MAC_MI_STAT,
1389                              MAC_MI_STAT_10MBPS_MODE |
1390                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1391                 else
1392                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1393         }
1394
1395         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1396                 tw32(MAC_TX_LENGTHS,
1397                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1398                       (6 << TX_LENGTHS_IPG_SHIFT) |
1399                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1400         else
1401                 tw32(MAC_TX_LENGTHS,
1402                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1403                       (6 << TX_LENGTHS_IPG_SHIFT) |
1404                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1405
1406         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1407             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1408             phydev->speed != tp->link_config.active_speed ||
1409             phydev->duplex != tp->link_config.active_duplex ||
1410             oldflowctrl != tp->link_config.active_flowctrl)
1411             linkmesg = 1;
1412
1413         tp->link_config.active_speed = phydev->speed;
1414         tp->link_config.active_duplex = phydev->duplex;
1415
1416         spin_unlock(&tp->lock);
1417
1418         if (linkmesg)
1419                 tg3_link_report(tp);
1420 }
1421
1422 static int tg3_phy_init(struct tg3 *tp)
1423 {
1424         struct phy_device *phydev;
1425
1426         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1427                 return 0;
1428
1429         /* Bring the PHY back to a known state. */
1430         tg3_bmcr_reset(tp);
1431
1432         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1433
1434         /* Attach the MAC to the PHY. */
1435         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1436                              phydev->dev_flags, phydev->interface);
1437         if (IS_ERR(phydev)) {
1438                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1439                 return PTR_ERR(phydev);
1440         }
1441
1442         /* Mask with MAC supported features. */
1443         switch (phydev->interface) {
1444         case PHY_INTERFACE_MODE_GMII:
1445         case PHY_INTERFACE_MODE_RGMII:
1446                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1447                         phydev->supported &= (PHY_GBIT_FEATURES |
1448                                               SUPPORTED_Pause |
1449                                               SUPPORTED_Asym_Pause);
1450                         break;
1451                 }
1452                 /* fallthru */
1453         case PHY_INTERFACE_MODE_MII:
1454                 phydev->supported &= (PHY_BASIC_FEATURES |
1455                                       SUPPORTED_Pause |
1456                                       SUPPORTED_Asym_Pause);
1457                 break;
1458         default:
1459                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1460                 return -EINVAL;
1461         }
1462
1463         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1464
1465         phydev->advertising = phydev->supported;
1466
1467         return 0;
1468 }
1469
1470 static void tg3_phy_start(struct tg3 *tp)
1471 {
1472         struct phy_device *phydev;
1473
1474         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1475                 return;
1476
1477         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1478
1479         if (tp->link_config.phy_is_low_power) {
1480                 tp->link_config.phy_is_low_power = 0;
1481                 phydev->speed = tp->link_config.orig_speed;
1482                 phydev->duplex = tp->link_config.orig_duplex;
1483                 phydev->autoneg = tp->link_config.orig_autoneg;
1484                 phydev->advertising = tp->link_config.orig_advertising;
1485         }
1486
1487         phy_start(phydev);
1488
1489         phy_start_aneg(phydev);
1490 }
1491
1492 static void tg3_phy_stop(struct tg3 *tp)
1493 {
1494         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1495                 return;
1496
1497         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1498 }
1499
1500 static void tg3_phy_fini(struct tg3 *tp)
1501 {
1502         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1503                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1504                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1505         }
1506 }
1507
1508 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1509 {
1510         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1511         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1512 }
1513
1514 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1515 {
1516         u32 phytest;
1517
1518         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1519                 u32 phy;
1520
1521                 tg3_writephy(tp, MII_TG3_FET_TEST,
1522                              phytest | MII_TG3_FET_SHADOW_EN);
1523                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1524                         if (enable)
1525                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1526                         else
1527                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1528                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1529                 }
1530                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1531         }
1532 }
1533
1534 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1535 {
1536         u32 reg;
1537
1538         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1539                 return;
1540
1541         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1542                 tg3_phy_fet_toggle_apd(tp, enable);
1543                 return;
1544         }
1545
1546         reg = MII_TG3_MISC_SHDW_WREN |
1547               MII_TG3_MISC_SHDW_SCR5_SEL |
1548               MII_TG3_MISC_SHDW_SCR5_LPED |
1549               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1550               MII_TG3_MISC_SHDW_SCR5_SDTL |
1551               MII_TG3_MISC_SHDW_SCR5_C125OE;
1552         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1553                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1554
1555         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1556
1557
1558         reg = MII_TG3_MISC_SHDW_WREN |
1559               MII_TG3_MISC_SHDW_APD_SEL |
1560               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1561         if (enable)
1562                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1563
1564         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1565 }
1566
1567 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1568 {
1569         u32 phy;
1570
1571         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1572             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1573                 return;
1574
1575         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1576                 u32 ephy;
1577
1578                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1579                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1580
1581                         tg3_writephy(tp, MII_TG3_FET_TEST,
1582                                      ephy | MII_TG3_FET_SHADOW_EN);
1583                         if (!tg3_readphy(tp, reg, &phy)) {
1584                                 if (enable)
1585                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1586                                 else
1587                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1588                                 tg3_writephy(tp, reg, phy);
1589                         }
1590                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1591                 }
1592         } else {
1593                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1594                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1595                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1596                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1597                         if (enable)
1598                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1599                         else
1600                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1601                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1602                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1603                 }
1604         }
1605 }
1606
1607 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1608 {
1609         u32 val;
1610
1611         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1612                 return;
1613
1614         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1615             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1616                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1617                              (val | (1 << 15) | (1 << 4)));
1618 }
1619
1620 static void tg3_phy_apply_otp(struct tg3 *tp)
1621 {
1622         u32 otp, phy;
1623
1624         if (!tp->phy_otp)
1625                 return;
1626
1627         otp = tp->phy_otp;
1628
1629         /* Enable SM_DSP clock and tx 6dB coding. */
1630         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1631               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1632               MII_TG3_AUXCTL_ACTL_TX_6DB;
1633         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1634
1635         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1636         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1637         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1638
1639         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1640               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1641         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1642
1643         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1644         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1645         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1646
1647         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1648         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1649
1650         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1651         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1652
1653         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1654               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1655         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1656
1657         /* Turn off SM_DSP clock. */
1658         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1659               MII_TG3_AUXCTL_ACTL_TX_6DB;
1660         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1661 }
1662
1663 static int tg3_wait_macro_done(struct tg3 *tp)
1664 {
1665         int limit = 100;
1666
1667         while (limit--) {
1668                 u32 tmp32;
1669
1670                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1671                         if ((tmp32 & 0x1000) == 0)
1672                                 break;
1673                 }
1674         }
1675         if (limit < 0)
1676                 return -EBUSY;
1677
1678         return 0;
1679 }
1680
1681 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1682 {
1683         static const u32 test_pat[4][6] = {
1684         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1685         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1686         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1687         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1688         };
1689         int chan;
1690
1691         for (chan = 0; chan < 4; chan++) {
1692                 int i;
1693
1694                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1695                              (chan * 0x2000) | 0x0200);
1696                 tg3_writephy(tp, 0x16, 0x0002);
1697
1698                 for (i = 0; i < 6; i++)
1699                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1700                                      test_pat[chan][i]);
1701
1702                 tg3_writephy(tp, 0x16, 0x0202);
1703                 if (tg3_wait_macro_done(tp)) {
1704                         *resetp = 1;
1705                         return -EBUSY;
1706                 }
1707
1708                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1709                              (chan * 0x2000) | 0x0200);
1710                 tg3_writephy(tp, 0x16, 0x0082);
1711                 if (tg3_wait_macro_done(tp)) {
1712                         *resetp = 1;
1713                         return -EBUSY;
1714                 }
1715
1716                 tg3_writephy(tp, 0x16, 0x0802);
1717                 if (tg3_wait_macro_done(tp)) {
1718                         *resetp = 1;
1719                         return -EBUSY;
1720                 }
1721
1722                 for (i = 0; i < 6; i += 2) {
1723                         u32 low, high;
1724
1725                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1726                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1727                             tg3_wait_macro_done(tp)) {
1728                                 *resetp = 1;
1729                                 return -EBUSY;
1730                         }
1731                         low &= 0x7fff;
1732                         high &= 0x000f;
1733                         if (low != test_pat[chan][i] ||
1734                             high != test_pat[chan][i+1]) {
1735                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1736                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1737                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1738
1739                                 return -EBUSY;
1740                         }
1741                 }
1742         }
1743
1744         return 0;
1745 }
1746
1747 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1748 {
1749         int chan;
1750
1751         for (chan = 0; chan < 4; chan++) {
1752                 int i;
1753
1754                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1755                              (chan * 0x2000) | 0x0200);
1756                 tg3_writephy(tp, 0x16, 0x0002);
1757                 for (i = 0; i < 6; i++)
1758                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1759                 tg3_writephy(tp, 0x16, 0x0202);
1760                 if (tg3_wait_macro_done(tp))
1761                         return -EBUSY;
1762         }
1763
1764         return 0;
1765 }
1766
1767 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1768 {
1769         u32 reg32, phy9_orig;
1770         int retries, do_phy_reset, err;
1771
1772         retries = 10;
1773         do_phy_reset = 1;
1774         do {
1775                 if (do_phy_reset) {
1776                         err = tg3_bmcr_reset(tp);
1777                         if (err)
1778                                 return err;
1779                         do_phy_reset = 0;
1780                 }
1781
1782                 /* Disable transmitter and interrupt.  */
1783                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1784                         continue;
1785
1786                 reg32 |= 0x3000;
1787                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1788
1789                 /* Set full-duplex, 1000 mbps.  */
1790                 tg3_writephy(tp, MII_BMCR,
1791                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1792
1793                 /* Set to master mode.  */
1794                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1795                         continue;
1796
1797                 tg3_writephy(tp, MII_TG3_CTRL,
1798                              (MII_TG3_CTRL_AS_MASTER |
1799                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1800
1801                 /* Enable SM_DSP_CLOCK and 6dB.  */
1802                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1803
1804                 /* Block the PHY control access.  */
1805                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1806                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1807
1808                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1809                 if (!err)
1810                         break;
1811         } while (--retries);
1812
1813         err = tg3_phy_reset_chanpat(tp);
1814         if (err)
1815                 return err;
1816
1817         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1818         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1819
1820         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1821         tg3_writephy(tp, 0x16, 0x0000);
1822
1823         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1824             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1825                 /* Set Extended packet length bit for jumbo frames */
1826                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1827         }
1828         else {
1829                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1830         }
1831
1832         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1833
1834         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1835                 reg32 &= ~0x3000;
1836                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1837         } else if (!err)
1838                 err = -EBUSY;
1839
1840         return err;
1841 }
1842
1843 /* This will reset the tigon3 PHY if there is no valid
1844  * link unless the FORCE argument is non-zero.
1845  */
1846 static int tg3_phy_reset(struct tg3 *tp)
1847 {
1848         u32 cpmuctrl;
1849         u32 phy_status;
1850         int err;
1851
1852         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1853                 u32 val;
1854
1855                 val = tr32(GRC_MISC_CFG);
1856                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1857                 udelay(40);
1858         }
1859         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1860         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1861         if (err != 0)
1862                 return -EBUSY;
1863
1864         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1865                 netif_carrier_off(tp->dev);
1866                 tg3_link_report(tp);
1867         }
1868
1869         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1870             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1871             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1872                 err = tg3_phy_reset_5703_4_5(tp);
1873                 if (err)
1874                         return err;
1875                 goto out;
1876         }
1877
1878         cpmuctrl = 0;
1879         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1880             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1881                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1882                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1883                         tw32(TG3_CPMU_CTRL,
1884                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1885         }
1886
1887         err = tg3_bmcr_reset(tp);
1888         if (err)
1889                 return err;
1890
1891         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1892                 u32 phy;
1893
1894                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1895                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1896
1897                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1898         }
1899
1900         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1901             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1902                 u32 val;
1903
1904                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1905                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1906                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1907                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1908                         udelay(40);
1909                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1910                 }
1911         }
1912
1913         tg3_phy_apply_otp(tp);
1914
1915         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1916                 tg3_phy_toggle_apd(tp, true);
1917         else
1918                 tg3_phy_toggle_apd(tp, false);
1919
1920 out:
1921         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1922                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1923                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1924                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1925                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1926                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1927                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1928         }
1929         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1930                 tg3_writephy(tp, 0x1c, 0x8d68);
1931                 tg3_writephy(tp, 0x1c, 0x8d68);
1932         }
1933         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1934                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1935                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1936                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1937                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1938                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1939                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1940                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1941                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1942         }
1943         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1944                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1945                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1946                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1947                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1948                         tg3_writephy(tp, MII_TG3_TEST1,
1949                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1950                 } else
1951                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1952                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1953         }
1954         /* Set Extended packet length bit (bit 14) on all chips that */
1955         /* support jumbo frames */
1956         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1957                 /* Cannot do read-modify-write on 5401 */
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1959         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1960                 u32 phy_reg;
1961
1962                 /* Set bit 14 with read-modify-write to preserve other bits */
1963                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1964                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1965                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1966         }
1967
1968         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1969          * jumbo frames transmission.
1970          */
1971         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1972                 u32 phy_reg;
1973
1974                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1975                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1976                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1977         }
1978
1979         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1980                 /* adjust output voltage */
1981                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1982         }
1983
1984         tg3_phy_toggle_automdix(tp, 1);
1985         tg3_phy_set_wirespeed(tp);
1986         return 0;
1987 }
1988
1989 static void tg3_frob_aux_power(struct tg3 *tp)
1990 {
1991         struct tg3 *tp_peer = tp;
1992
1993         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1994                 return;
1995
1996         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1997             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1998                 struct net_device *dev_peer;
1999
2000                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2001                 /* remove_one() may have been run on the peer. */
2002                 if (!dev_peer)
2003                         tp_peer = tp;
2004                 else
2005                         tp_peer = netdev_priv(dev_peer);
2006         }
2007
2008         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2009             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2010             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2011             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2012                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2013                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2014                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2015                                     (GRC_LCLCTRL_GPIO_OE0 |
2016                                      GRC_LCLCTRL_GPIO_OE1 |
2017                                      GRC_LCLCTRL_GPIO_OE2 |
2018                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2019                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2020                                     100);
2021                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2022                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2023                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2024                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2025                                              GRC_LCLCTRL_GPIO_OE1 |
2026                                              GRC_LCLCTRL_GPIO_OE2 |
2027                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2028                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2029                                              tp->grc_local_ctrl;
2030                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2031
2032                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2033                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2034
2035                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2036                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2037                 } else {
2038                         u32 no_gpio2;
2039                         u32 grc_local_ctrl = 0;
2040
2041                         if (tp_peer != tp &&
2042                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2043                                 return;
2044
2045                         /* Workaround to prevent overdrawing Amps. */
2046                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2047                             ASIC_REV_5714) {
2048                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2049                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2050                                             grc_local_ctrl, 100);
2051                         }
2052
2053                         /* On 5753 and variants, GPIO2 cannot be used. */
2054                         no_gpio2 = tp->nic_sram_data_cfg &
2055                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2056
2057                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2058                                          GRC_LCLCTRL_GPIO_OE1 |
2059                                          GRC_LCLCTRL_GPIO_OE2 |
2060                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2061                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2062                         if (no_gpio2) {
2063                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2064                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2065                         }
2066                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067                                                     grc_local_ctrl, 100);
2068
2069                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2070
2071                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2072                                                     grc_local_ctrl, 100);
2073
2074                         if (!no_gpio2) {
2075                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2076                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2077                                             grc_local_ctrl, 100);
2078                         }
2079                 }
2080         } else {
2081                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2082                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2083                         if (tp_peer != tp &&
2084                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2085                                 return;
2086
2087                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2088                                     (GRC_LCLCTRL_GPIO_OE1 |
2089                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2090
2091                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2092                                     GRC_LCLCTRL_GPIO_OE1, 100);
2093
2094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095                                     (GRC_LCLCTRL_GPIO_OE1 |
2096                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2097                 }
2098         }
2099 }
2100
2101 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2102 {
2103         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2104                 return 1;
2105         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2106                 if (speed != SPEED_10)
2107                         return 1;
2108         } else if (speed == SPEED_10)
2109                 return 1;
2110
2111         return 0;
2112 }
2113
2114 static int tg3_setup_phy(struct tg3 *, int);
2115
2116 #define RESET_KIND_SHUTDOWN     0
2117 #define RESET_KIND_INIT         1
2118 #define RESET_KIND_SUSPEND      2
2119
2120 static void tg3_write_sig_post_reset(struct tg3 *, int);
2121 static int tg3_halt_cpu(struct tg3 *, u32);
2122
2123 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2124 {
2125         u32 val;
2126
2127         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2128                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2129                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2130                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2131
2132                         sg_dig_ctrl |=
2133                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2134                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2135                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2136                 }
2137                 return;
2138         }
2139
2140         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2141                 tg3_bmcr_reset(tp);
2142                 val = tr32(GRC_MISC_CFG);
2143                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2144                 udelay(40);
2145                 return;
2146         } else if (do_low_power) {
2147                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2148                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2149
2150                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2151                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2152                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2153                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2154                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2155         }
2156
2157         /* The PHY should not be powered down on some chips because
2158          * of bugs.
2159          */
2160         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2161             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2162             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2163              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2164                 return;
2165
2166         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2167             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2168                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2169                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2170                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2171                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2172         }
2173
2174         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2175 }
2176
2177 /* tp->lock is held. */
2178 static int tg3_nvram_lock(struct tg3 *tp)
2179 {
2180         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2181                 int i;
2182
2183                 if (tp->nvram_lock_cnt == 0) {
2184                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2185                         for (i = 0; i < 8000; i++) {
2186                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2187                                         break;
2188                                 udelay(20);
2189                         }
2190                         if (i == 8000) {
2191                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2192                                 return -ENODEV;
2193                         }
2194                 }
2195                 tp->nvram_lock_cnt++;
2196         }
2197         return 0;
2198 }
2199
2200 /* tp->lock is held. */
2201 static void tg3_nvram_unlock(struct tg3 *tp)
2202 {
2203         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2204                 if (tp->nvram_lock_cnt > 0)
2205                         tp->nvram_lock_cnt--;
2206                 if (tp->nvram_lock_cnt == 0)
2207                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2208         }
2209 }
2210
2211 /* tp->lock is held. */
2212 static void tg3_enable_nvram_access(struct tg3 *tp)
2213 {
2214         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2215             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2216                 u32 nvaccess = tr32(NVRAM_ACCESS);
2217
2218                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2219         }
2220 }
2221
2222 /* tp->lock is held. */
2223 static void tg3_disable_nvram_access(struct tg3 *tp)
2224 {
2225         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2226             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2227                 u32 nvaccess = tr32(NVRAM_ACCESS);
2228
2229                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2230         }
2231 }
2232
2233 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2234                                         u32 offset, u32 *val)
2235 {
2236         u32 tmp;
2237         int i;
2238
2239         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2240                 return -EINVAL;
2241
2242         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2243                                         EEPROM_ADDR_DEVID_MASK |
2244                                         EEPROM_ADDR_READ);
2245         tw32(GRC_EEPROM_ADDR,
2246              tmp |
2247              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2248              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2249               EEPROM_ADDR_ADDR_MASK) |
2250              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2251
2252         for (i = 0; i < 1000; i++) {
2253                 tmp = tr32(GRC_EEPROM_ADDR);
2254
2255                 if (tmp & EEPROM_ADDR_COMPLETE)
2256                         break;
2257                 msleep(1);
2258         }
2259         if (!(tmp & EEPROM_ADDR_COMPLETE))
2260                 return -EBUSY;
2261
2262         tmp = tr32(GRC_EEPROM_DATA);
2263
2264         /*
2265          * The data will always be opposite the native endian
2266          * format.  Perform a blind byteswap to compensate.
2267          */
2268         *val = swab32(tmp);
2269
2270         return 0;
2271 }
2272
2273 #define NVRAM_CMD_TIMEOUT 10000
2274
2275 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2276 {
2277         int i;
2278
2279         tw32(NVRAM_CMD, nvram_cmd);
2280         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2281                 udelay(10);
2282                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2283                         udelay(10);
2284                         break;
2285                 }
2286         }
2287
2288         if (i == NVRAM_CMD_TIMEOUT)
2289                 return -EBUSY;
2290
2291         return 0;
2292 }
2293
2294 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2295 {
2296         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2297             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2298             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2299            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2300             (tp->nvram_jedecnum == JEDEC_ATMEL))
2301
2302                 addr = ((addr / tp->nvram_pagesize) <<
2303                         ATMEL_AT45DB0X1B_PAGE_POS) +
2304                        (addr % tp->nvram_pagesize);
2305
2306         return addr;
2307 }
2308
2309 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2310 {
2311         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2312             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2313             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2314            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2315             (tp->nvram_jedecnum == JEDEC_ATMEL))
2316
2317                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2318                         tp->nvram_pagesize) +
2319                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2320
2321         return addr;
2322 }
2323
2324 /* NOTE: Data read in from NVRAM is byteswapped according to
2325  * the byteswapping settings for all other register accesses.
2326  * tg3 devices are BE devices, so on a BE machine, the data
2327  * returned will be exactly as it is seen in NVRAM.  On a LE
2328  * machine, the 32-bit value will be byteswapped.
2329  */
2330 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2331 {
2332         int ret;
2333
2334         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2335                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2336
2337         offset = tg3_nvram_phys_addr(tp, offset);
2338
2339         if (offset > NVRAM_ADDR_MSK)
2340                 return -EINVAL;
2341
2342         ret = tg3_nvram_lock(tp);
2343         if (ret)
2344                 return ret;
2345
2346         tg3_enable_nvram_access(tp);
2347
2348         tw32(NVRAM_ADDR, offset);
2349         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2350                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2351
2352         if (ret == 0)
2353                 *val = tr32(NVRAM_RDDATA);
2354
2355         tg3_disable_nvram_access(tp);
2356
2357         tg3_nvram_unlock(tp);
2358
2359         return ret;
2360 }
2361
2362 /* Ensures NVRAM data is in bytestream format. */
2363 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2364 {
2365         u32 v;
2366         int res = tg3_nvram_read(tp, offset, &v);
2367         if (!res)
2368                 *val = cpu_to_be32(v);
2369         return res;
2370 }
2371
2372 /* tp->lock is held. */
2373 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2374 {
2375         u32 addr_high, addr_low;
2376         int i;
2377
2378         addr_high = ((tp->dev->dev_addr[0] << 8) |
2379                      tp->dev->dev_addr[1]);
2380         addr_low = ((tp->dev->dev_addr[2] << 24) |
2381                     (tp->dev->dev_addr[3] << 16) |
2382                     (tp->dev->dev_addr[4] <<  8) |
2383                     (tp->dev->dev_addr[5] <<  0));
2384         for (i = 0; i < 4; i++) {
2385                 if (i == 1 && skip_mac_1)
2386                         continue;
2387                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2388                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2389         }
2390
2391         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2392             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2393                 for (i = 0; i < 12; i++) {
2394                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2395                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2396                 }
2397         }
2398
2399         addr_high = (tp->dev->dev_addr[0] +
2400                      tp->dev->dev_addr[1] +
2401                      tp->dev->dev_addr[2] +
2402                      tp->dev->dev_addr[3] +
2403                      tp->dev->dev_addr[4] +
2404                      tp->dev->dev_addr[5]) &
2405                 TX_BACKOFF_SEED_MASK;
2406         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2407 }
2408
2409 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2410 {
2411         u32 misc_host_ctrl;
2412         bool device_should_wake, do_low_power;
2413
2414         /* Make sure register accesses (indirect or otherwise)
2415          * will function correctly.
2416          */
2417         pci_write_config_dword(tp->pdev,
2418                                TG3PCI_MISC_HOST_CTRL,
2419                                tp->misc_host_ctrl);
2420
2421         switch (state) {
2422         case PCI_D0:
2423                 pci_enable_wake(tp->pdev, state, false);
2424                 pci_set_power_state(tp->pdev, PCI_D0);
2425
2426                 /* Switch out of Vaux if it is a NIC */
2427                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2428                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2429
2430                 return 0;
2431
2432         case PCI_D1:
2433         case PCI_D2:
2434         case PCI_D3hot:
2435                 break;
2436
2437         default:
2438                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2439                         tp->dev->name, state);
2440                 return -EINVAL;
2441         }
2442
2443         /* Restore the CLKREQ setting. */
2444         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2445                 u16 lnkctl;
2446
2447                 pci_read_config_word(tp->pdev,
2448                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2449                                      &lnkctl);
2450                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2451                 pci_write_config_word(tp->pdev,
2452                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2453                                       lnkctl);
2454         }
2455
2456         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2457         tw32(TG3PCI_MISC_HOST_CTRL,
2458              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2459
2460         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2461                              device_may_wakeup(&tp->pdev->dev) &&
2462                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2463
2464         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2465                 do_low_power = false;
2466                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2467                     !tp->link_config.phy_is_low_power) {
2468                         struct phy_device *phydev;
2469                         u32 phyid, advertising;
2470
2471                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2472
2473                         tp->link_config.phy_is_low_power = 1;
2474
2475                         tp->link_config.orig_speed = phydev->speed;
2476                         tp->link_config.orig_duplex = phydev->duplex;
2477                         tp->link_config.orig_autoneg = phydev->autoneg;
2478                         tp->link_config.orig_advertising = phydev->advertising;
2479
2480                         advertising = ADVERTISED_TP |
2481                                       ADVERTISED_Pause |
2482                                       ADVERTISED_Autoneg |
2483                                       ADVERTISED_10baseT_Half;
2484
2485                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2486                             device_should_wake) {
2487                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2488                                         advertising |=
2489                                                 ADVERTISED_100baseT_Half |
2490                                                 ADVERTISED_100baseT_Full |
2491                                                 ADVERTISED_10baseT_Full;
2492                                 else
2493                                         advertising |= ADVERTISED_10baseT_Full;
2494                         }
2495
2496                         phydev->advertising = advertising;
2497
2498                         phy_start_aneg(phydev);
2499
2500                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2501                         if (phyid != TG3_PHY_ID_BCMAC131) {
2502                                 phyid &= TG3_PHY_OUI_MASK;
2503                                 if (phyid == TG3_PHY_OUI_1 ||
2504                                     phyid == TG3_PHY_OUI_2 ||
2505                                     phyid == TG3_PHY_OUI_3)
2506                                         do_low_power = true;
2507                         }
2508                 }
2509         } else {
2510                 do_low_power = true;
2511
2512                 if (tp->link_config.phy_is_low_power == 0) {
2513                         tp->link_config.phy_is_low_power = 1;
2514                         tp->link_config.orig_speed = tp->link_config.speed;
2515                         tp->link_config.orig_duplex = tp->link_config.duplex;
2516                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2517                 }
2518
2519                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2520                         tp->link_config.speed = SPEED_10;
2521                         tp->link_config.duplex = DUPLEX_HALF;
2522                         tp->link_config.autoneg = AUTONEG_ENABLE;
2523                         tg3_setup_phy(tp, 0);
2524                 }
2525         }
2526
2527         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2528                 u32 val;
2529
2530                 val = tr32(GRC_VCPU_EXT_CTRL);
2531                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2532         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2533                 int i;
2534                 u32 val;
2535
2536                 for (i = 0; i < 200; i++) {
2537                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2538                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2539                                 break;
2540                         msleep(1);
2541                 }
2542         }
2543         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2544                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2545                                                      WOL_DRV_STATE_SHUTDOWN |
2546                                                      WOL_DRV_WOL |
2547                                                      WOL_SET_MAGIC_PKT);
2548
2549         if (device_should_wake) {
2550                 u32 mac_mode;
2551
2552                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2553                         if (do_low_power) {
2554                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2555                                 udelay(40);
2556                         }
2557
2558                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2559                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2560                         else
2561                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2562
2563                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2564                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2565                             ASIC_REV_5700) {
2566                                 u32 speed = (tp->tg3_flags &
2567                                              TG3_FLAG_WOL_SPEED_100MB) ?
2568                                              SPEED_100 : SPEED_10;
2569                                 if (tg3_5700_link_polarity(tp, speed))
2570                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2571                                 else
2572                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2573                         }
2574                 } else {
2575                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2576                 }
2577
2578                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2579                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2580
2581                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2582                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2583                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2584                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2585                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2586                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2587
2588                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2589                         mac_mode |= tp->mac_mode &
2590                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2591                         if (mac_mode & MAC_MODE_APE_TX_EN)
2592                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2593                 }
2594
2595                 tw32_f(MAC_MODE, mac_mode);
2596                 udelay(100);
2597
2598                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2599                 udelay(10);
2600         }
2601
2602         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2603             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2604              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2605                 u32 base_val;
2606
2607                 base_val = tp->pci_clock_ctrl;
2608                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2609                              CLOCK_CTRL_TXCLK_DISABLE);
2610
2611                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2612                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2613         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2614                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2615                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2616                 /* do nothing */
2617         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2618                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2619                 u32 newbits1, newbits2;
2620
2621                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2622                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2623                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2624                                     CLOCK_CTRL_TXCLK_DISABLE |
2625                                     CLOCK_CTRL_ALTCLK);
2626                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2627                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2628                         newbits1 = CLOCK_CTRL_625_CORE;
2629                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2630                 } else {
2631                         newbits1 = CLOCK_CTRL_ALTCLK;
2632                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2633                 }
2634
2635                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2636                             40);
2637
2638                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2639                             40);
2640
2641                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2642                         u32 newbits3;
2643
2644                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2645                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2646                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2647                                             CLOCK_CTRL_TXCLK_DISABLE |
2648                                             CLOCK_CTRL_44MHZ_CORE);
2649                         } else {
2650                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2651                         }
2652
2653                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2654                                     tp->pci_clock_ctrl | newbits3, 40);
2655                 }
2656         }
2657
2658         if (!(device_should_wake) &&
2659             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2660                 tg3_power_down_phy(tp, do_low_power);
2661
2662         tg3_frob_aux_power(tp);
2663
2664         /* Workaround for unstable PLL clock */
2665         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2666             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2667                 u32 val = tr32(0x7d00);
2668
2669                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2670                 tw32(0x7d00, val);
2671                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2672                         int err;
2673
2674                         err = tg3_nvram_lock(tp);
2675                         tg3_halt_cpu(tp, RX_CPU_BASE);
2676                         if (!err)
2677                                 tg3_nvram_unlock(tp);
2678                 }
2679         }
2680
2681         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2682
2683         if (device_should_wake)
2684                 pci_enable_wake(tp->pdev, state, true);
2685
2686         /* Finally, set the new power state. */
2687         pci_set_power_state(tp->pdev, state);
2688
2689         return 0;
2690 }
2691
2692 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2693 {
2694         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2695         case MII_TG3_AUX_STAT_10HALF:
2696                 *speed = SPEED_10;
2697                 *duplex = DUPLEX_HALF;
2698                 break;
2699
2700         case MII_TG3_AUX_STAT_10FULL:
2701                 *speed = SPEED_10;
2702                 *duplex = DUPLEX_FULL;
2703                 break;
2704
2705         case MII_TG3_AUX_STAT_100HALF:
2706                 *speed = SPEED_100;
2707                 *duplex = DUPLEX_HALF;
2708                 break;
2709
2710         case MII_TG3_AUX_STAT_100FULL:
2711                 *speed = SPEED_100;
2712                 *duplex = DUPLEX_FULL;
2713                 break;
2714
2715         case MII_TG3_AUX_STAT_1000HALF:
2716                 *speed = SPEED_1000;
2717                 *duplex = DUPLEX_HALF;
2718                 break;
2719
2720         case MII_TG3_AUX_STAT_1000FULL:
2721                 *speed = SPEED_1000;
2722                 *duplex = DUPLEX_FULL;
2723                 break;
2724
2725         default:
2726                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2727                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2728                                  SPEED_10;
2729                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2730                                   DUPLEX_HALF;
2731                         break;
2732                 }
2733                 *speed = SPEED_INVALID;
2734                 *duplex = DUPLEX_INVALID;
2735                 break;
2736         }
2737 }
2738
2739 static void tg3_phy_copper_begin(struct tg3 *tp)
2740 {
2741         u32 new_adv;
2742         int i;
2743
2744         if (tp->link_config.phy_is_low_power) {
2745                 /* Entering low power mode.  Disable gigabit and
2746                  * 100baseT advertisements.
2747                  */
2748                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2749
2750                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2751                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2752                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2753                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2754
2755                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2756         } else if (tp->link_config.speed == SPEED_INVALID) {
2757                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2758                         tp->link_config.advertising &=
2759                                 ~(ADVERTISED_1000baseT_Half |
2760                                   ADVERTISED_1000baseT_Full);
2761
2762                 new_adv = ADVERTISE_CSMA;
2763                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2764                         new_adv |= ADVERTISE_10HALF;
2765                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2766                         new_adv |= ADVERTISE_10FULL;
2767                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2768                         new_adv |= ADVERTISE_100HALF;
2769                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2770                         new_adv |= ADVERTISE_100FULL;
2771
2772                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2773
2774                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2775
2776                 if (tp->link_config.advertising &
2777                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2778                         new_adv = 0;
2779                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2780                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2781                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2782                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2783                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2784                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2785                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2786                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2787                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2788                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2789                 } else {
2790                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2791                 }
2792         } else {
2793                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2794                 new_adv |= ADVERTISE_CSMA;
2795
2796                 /* Asking for a specific link mode. */
2797                 if (tp->link_config.speed == SPEED_1000) {
2798                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2799
2800                         if (tp->link_config.duplex == DUPLEX_FULL)
2801                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2802                         else
2803                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2804                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2805                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2806                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2807                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2808                 } else {
2809                         if (tp->link_config.speed == SPEED_100) {
2810                                 if (tp->link_config.duplex == DUPLEX_FULL)
2811                                         new_adv |= ADVERTISE_100FULL;
2812                                 else
2813                                         new_adv |= ADVERTISE_100HALF;
2814                         } else {
2815                                 if (tp->link_config.duplex == DUPLEX_FULL)
2816                                         new_adv |= ADVERTISE_10FULL;
2817                                 else
2818                                         new_adv |= ADVERTISE_10HALF;
2819                         }
2820                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821
2822                         new_adv = 0;
2823                 }
2824
2825                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2826         }
2827
2828         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2829             tp->link_config.speed != SPEED_INVALID) {
2830                 u32 bmcr, orig_bmcr;
2831
2832                 tp->link_config.active_speed = tp->link_config.speed;
2833                 tp->link_config.active_duplex = tp->link_config.duplex;
2834
2835                 bmcr = 0;
2836                 switch (tp->link_config.speed) {
2837                 default:
2838                 case SPEED_10:
2839                         break;
2840
2841                 case SPEED_100:
2842                         bmcr |= BMCR_SPEED100;
2843                         break;
2844
2845                 case SPEED_1000:
2846                         bmcr |= TG3_BMCR_SPEED1000;
2847                         break;
2848                 }
2849
2850                 if (tp->link_config.duplex == DUPLEX_FULL)
2851                         bmcr |= BMCR_FULLDPLX;
2852
2853                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2854                     (bmcr != orig_bmcr)) {
2855                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2856                         for (i = 0; i < 1500; i++) {
2857                                 u32 tmp;
2858
2859                                 udelay(10);
2860                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2861                                     tg3_readphy(tp, MII_BMSR, &tmp))
2862                                         continue;
2863                                 if (!(tmp & BMSR_LSTATUS)) {
2864                                         udelay(40);
2865                                         break;
2866                                 }
2867                         }
2868                         tg3_writephy(tp, MII_BMCR, bmcr);
2869                         udelay(40);
2870                 }
2871         } else {
2872                 tg3_writephy(tp, MII_BMCR,
2873                              BMCR_ANENABLE | BMCR_ANRESTART);
2874         }
2875 }
2876
2877 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2878 {
2879         int err;
2880
2881         /* Turn off tap power management. */
2882         /* Set Extended packet length bit */
2883         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2884
2885         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2886         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2887
2888         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2889         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2890
2891         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2892         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2893
2894         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2895         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2896
2897         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2898         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2899
2900         udelay(40);
2901
2902         return err;
2903 }
2904
2905 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2906 {
2907         u32 adv_reg, all_mask = 0;
2908
2909         if (mask & ADVERTISED_10baseT_Half)
2910                 all_mask |= ADVERTISE_10HALF;
2911         if (mask & ADVERTISED_10baseT_Full)
2912                 all_mask |= ADVERTISE_10FULL;
2913         if (mask & ADVERTISED_100baseT_Half)
2914                 all_mask |= ADVERTISE_100HALF;
2915         if (mask & ADVERTISED_100baseT_Full)
2916                 all_mask |= ADVERTISE_100FULL;
2917
2918         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2919                 return 0;
2920
2921         if ((adv_reg & all_mask) != all_mask)
2922                 return 0;
2923         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2924                 u32 tg3_ctrl;
2925
2926                 all_mask = 0;
2927                 if (mask & ADVERTISED_1000baseT_Half)
2928                         all_mask |= ADVERTISE_1000HALF;
2929                 if (mask & ADVERTISED_1000baseT_Full)
2930                         all_mask |= ADVERTISE_1000FULL;
2931
2932                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2933                         return 0;
2934
2935                 if ((tg3_ctrl & all_mask) != all_mask)
2936                         return 0;
2937         }
2938         return 1;
2939 }
2940
2941 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2942 {
2943         u32 curadv, reqadv;
2944
2945         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2946                 return 1;
2947
2948         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2949         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2950
2951         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2952                 if (curadv != reqadv)
2953                         return 0;
2954
2955                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2956                         tg3_readphy(tp, MII_LPA, rmtadv);
2957         } else {
2958                 /* Reprogram the advertisement register, even if it
2959                  * does not affect the current link.  If the link
2960                  * gets renegotiated in the future, we can save an
2961                  * additional renegotiation cycle by advertising
2962                  * it correctly in the first place.
2963                  */
2964                 if (curadv != reqadv) {
2965                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2966                                      ADVERTISE_PAUSE_ASYM);
2967                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2968                 }
2969         }
2970
2971         return 1;
2972 }
2973
2974 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2975 {
2976         int current_link_up;
2977         u32 bmsr, dummy;
2978         u32 lcl_adv, rmt_adv;
2979         u16 current_speed;
2980         u8 current_duplex;
2981         int i, err;
2982
2983         tw32(MAC_EVENT, 0);
2984
2985         tw32_f(MAC_STATUS,
2986              (MAC_STATUS_SYNC_CHANGED |
2987               MAC_STATUS_CFG_CHANGED |
2988               MAC_STATUS_MI_COMPLETION |
2989               MAC_STATUS_LNKSTATE_CHANGED));
2990         udelay(40);
2991
2992         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2993                 tw32_f(MAC_MI_MODE,
2994                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2995                 udelay(80);
2996         }
2997
2998         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2999
3000         /* Some third-party PHYs need to be reset on link going
3001          * down.
3002          */
3003         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3004              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3005              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3006             netif_carrier_ok(tp->dev)) {
3007                 tg3_readphy(tp, MII_BMSR, &bmsr);
3008                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3009                     !(bmsr & BMSR_LSTATUS))
3010                         force_reset = 1;
3011         }
3012         if (force_reset)
3013                 tg3_phy_reset(tp);
3014
3015         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3016                 tg3_readphy(tp, MII_BMSR, &bmsr);
3017                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3018                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3019                         bmsr = 0;
3020
3021                 if (!(bmsr & BMSR_LSTATUS)) {
3022                         err = tg3_init_5401phy_dsp(tp);
3023                         if (err)
3024                                 return err;
3025
3026                         tg3_readphy(tp, MII_BMSR, &bmsr);
3027                         for (i = 0; i < 1000; i++) {
3028                                 udelay(10);
3029                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3030                                     (bmsr & BMSR_LSTATUS)) {
3031                                         udelay(40);
3032                                         break;
3033                                 }
3034                         }
3035
3036                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3037                             !(bmsr & BMSR_LSTATUS) &&
3038                             tp->link_config.active_speed == SPEED_1000) {
3039                                 err = tg3_phy_reset(tp);
3040                                 if (!err)
3041                                         err = tg3_init_5401phy_dsp(tp);
3042                                 if (err)
3043                                         return err;
3044                         }
3045                 }
3046         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3047                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3048                 /* 5701 {A0,B0} CRC bug workaround */
3049                 tg3_writephy(tp, 0x15, 0x0a75);
3050                 tg3_writephy(tp, 0x1c, 0x8c68);
3051                 tg3_writephy(tp, 0x1c, 0x8d68);
3052                 tg3_writephy(tp, 0x1c, 0x8c68);
3053         }
3054
3055         /* Clear pending interrupts... */
3056         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3057         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3058
3059         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3060                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3061         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3062                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3063
3064         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3065             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3066                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3067                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3068                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3069                 else
3070                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3071         }
3072
3073         current_link_up = 0;
3074         current_speed = SPEED_INVALID;
3075         current_duplex = DUPLEX_INVALID;
3076
3077         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3078                 u32 val;
3079
3080                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3081                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3082                 if (!(val & (1 << 10))) {
3083                         val |= (1 << 10);
3084                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3085                         goto relink;
3086                 }
3087         }
3088
3089         bmsr = 0;
3090         for (i = 0; i < 100; i++) {
3091                 tg3_readphy(tp, MII_BMSR, &bmsr);
3092                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3093                     (bmsr & BMSR_LSTATUS))
3094                         break;
3095                 udelay(40);
3096         }
3097
3098         if (bmsr & BMSR_LSTATUS) {
3099                 u32 aux_stat, bmcr;
3100
3101                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3102                 for (i = 0; i < 2000; i++) {
3103                         udelay(10);
3104                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3105                             aux_stat)
3106                                 break;
3107                 }
3108
3109                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3110                                              &current_speed,
3111                                              &current_duplex);
3112
3113                 bmcr = 0;
3114                 for (i = 0; i < 200; i++) {
3115                         tg3_readphy(tp, MII_BMCR, &bmcr);
3116                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3117                                 continue;
3118                         if (bmcr && bmcr != 0x7fff)
3119                                 break;
3120                         udelay(10);
3121                 }
3122
3123                 lcl_adv = 0;
3124                 rmt_adv = 0;
3125
3126                 tp->link_config.active_speed = current_speed;
3127                 tp->link_config.active_duplex = current_duplex;
3128
3129                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3130                         if ((bmcr & BMCR_ANENABLE) &&
3131                             tg3_copper_is_advertising_all(tp,
3132                                                 tp->link_config.advertising)) {
3133                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3134                                                                   &rmt_adv))
3135                                         current_link_up = 1;
3136                         }
3137                 } else {
3138                         if (!(bmcr & BMCR_ANENABLE) &&
3139                             tp->link_config.speed == current_speed &&
3140                             tp->link_config.duplex == current_duplex &&
3141                             tp->link_config.flowctrl ==
3142                             tp->link_config.active_flowctrl) {
3143                                 current_link_up = 1;
3144                         }
3145                 }
3146
3147                 if (current_link_up == 1 &&
3148                     tp->link_config.active_duplex == DUPLEX_FULL)
3149                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3150         }
3151
3152 relink:
3153         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3154                 u32 tmp;
3155
3156                 tg3_phy_copper_begin(tp);
3157
3158                 tg3_readphy(tp, MII_BMSR, &tmp);
3159                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3160                     (tmp & BMSR_LSTATUS))
3161                         current_link_up = 1;
3162         }
3163
3164         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3165         if (current_link_up == 1) {
3166                 if (tp->link_config.active_speed == SPEED_100 ||
3167                     tp->link_config.active_speed == SPEED_10)
3168                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3169                 else
3170                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3171         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3172                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3173         else
3174                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3175
3176         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3177         if (tp->link_config.active_duplex == DUPLEX_HALF)
3178                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3179
3180         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3181                 if (current_link_up == 1 &&
3182                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3183                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3184                 else
3185                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3186         }
3187
3188         /* ??? Without this setting Netgear GA302T PHY does not
3189          * ??? send/receive packets...
3190          */
3191         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3192             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3193                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3194                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3195                 udelay(80);
3196         }
3197
3198         tw32_f(MAC_MODE, tp->mac_mode);
3199         udelay(40);
3200
3201         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3202                 /* Polled via timer. */
3203                 tw32_f(MAC_EVENT, 0);
3204         } else {
3205                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3206         }
3207         udelay(40);
3208
3209         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3210             current_link_up == 1 &&
3211             tp->link_config.active_speed == SPEED_1000 &&
3212             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3213              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3214                 udelay(120);
3215                 tw32_f(MAC_STATUS,
3216                      (MAC_STATUS_SYNC_CHANGED |
3217                       MAC_STATUS_CFG_CHANGED));
3218                 udelay(40);
3219                 tg3_write_mem(tp,
3220                               NIC_SRAM_FIRMWARE_MBOX,
3221                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3222         }
3223
3224         /* Prevent send BD corruption. */
3225         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3226                 u16 oldlnkctl, newlnkctl;
3227
3228                 pci_read_config_word(tp->pdev,
3229                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3230                                      &oldlnkctl);
3231                 if (tp->link_config.active_speed == SPEED_100 ||
3232                     tp->link_config.active_speed == SPEED_10)
3233                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3234                 else
3235                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3236                 if (newlnkctl != oldlnkctl)
3237                         pci_write_config_word(tp->pdev,
3238                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3239                                               newlnkctl);
3240         } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3241                 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3242                 if (tp->link_config.active_speed == SPEED_100 ||
3243                     tp->link_config.active_speed == SPEED_10)
3244                         newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3245                 else
3246                         newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3247                 if (newreg != oldreg)
3248                         tw32(TG3_PCIE_LNKCTL, newreg);
3249         }
3250
3251         if (current_link_up != netif_carrier_ok(tp->dev)) {
3252                 if (current_link_up)
3253                         netif_carrier_on(tp->dev);
3254                 else
3255                         netif_carrier_off(tp->dev);
3256                 tg3_link_report(tp);
3257         }
3258
3259         return 0;
3260 }
3261
3262 struct tg3_fiber_aneginfo {
3263         int state;
3264 #define ANEG_STATE_UNKNOWN              0
3265 #define ANEG_STATE_AN_ENABLE            1
3266 #define ANEG_STATE_RESTART_INIT         2
3267 #define ANEG_STATE_RESTART              3
3268 #define ANEG_STATE_DISABLE_LINK_OK      4
3269 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3270 #define ANEG_STATE_ABILITY_DETECT       6
3271 #define ANEG_STATE_ACK_DETECT_INIT      7
3272 #define ANEG_STATE_ACK_DETECT           8
3273 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3274 #define ANEG_STATE_COMPLETE_ACK         10
3275 #define ANEG_STATE_IDLE_DETECT_INIT     11
3276 #define ANEG_STATE_IDLE_DETECT          12
3277 #define ANEG_STATE_LINK_OK              13
3278 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3279 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3280
3281         u32 flags;
3282 #define MR_AN_ENABLE            0x00000001
3283 #define MR_RESTART_AN           0x00000002
3284 #define MR_AN_COMPLETE          0x00000004
3285 #define MR_PAGE_RX              0x00000008
3286 #define MR_NP_LOADED            0x00000010
3287 #define MR_TOGGLE_TX            0x00000020
3288 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3289 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3290 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3291 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3292 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3293 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3294 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3295 #define MR_TOGGLE_RX            0x00002000
3296 #define MR_NP_RX                0x00004000
3297
3298 #define MR_LINK_OK              0x80000000
3299
3300         unsigned long link_time, cur_time;
3301
3302         u32 ability_match_cfg;
3303         int ability_match_count;
3304
3305         char ability_match, idle_match, ack_match;
3306
3307         u32 txconfig, rxconfig;
3308 #define ANEG_CFG_NP             0x00000080
3309 #define ANEG_CFG_ACK            0x00000040
3310 #define ANEG_CFG_RF2            0x00000020
3311 #define ANEG_CFG_RF1            0x00000010
3312 #define ANEG_CFG_PS2            0x00000001
3313 #define ANEG_CFG_PS1            0x00008000
3314 #define ANEG_CFG_HD             0x00004000
3315 #define ANEG_CFG_FD             0x00002000
3316 #define ANEG_CFG_INVAL          0x00001f06
3317
3318 };
3319 #define ANEG_OK         0
3320 #define ANEG_DONE       1
3321 #define ANEG_TIMER_ENAB 2
3322 #define ANEG_FAILED     -1
3323
3324 #define ANEG_STATE_SETTLE_TIME  10000
3325
3326 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3327                                    struct tg3_fiber_aneginfo *ap)
3328 {
3329         u16 flowctrl;
3330         unsigned long delta;
3331         u32 rx_cfg_reg;
3332         int ret;
3333
3334         if (ap->state == ANEG_STATE_UNKNOWN) {
3335                 ap->rxconfig = 0;
3336                 ap->link_time = 0;
3337                 ap->cur_time = 0;
3338                 ap->ability_match_cfg = 0;
3339                 ap->ability_match_count = 0;
3340                 ap->ability_match = 0;
3341                 ap->idle_match = 0;
3342                 ap->ack_match = 0;
3343         }
3344         ap->cur_time++;
3345
3346         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3347                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3348
3349                 if (rx_cfg_reg != ap->ability_match_cfg) {
3350                         ap->ability_match_cfg = rx_cfg_reg;
3351                         ap->ability_match = 0;
3352                         ap->ability_match_count = 0;
3353                 } else {
3354                         if (++ap->ability_match_count > 1) {
3355                                 ap->ability_match = 1;
3356                                 ap->ability_match_cfg = rx_cfg_reg;
3357                         }
3358                 }
3359                 if (rx_cfg_reg & ANEG_CFG_ACK)
3360                         ap->ack_match = 1;
3361                 else
3362                         ap->ack_match = 0;
3363
3364                 ap->idle_match = 0;
3365         } else {
3366                 ap->idle_match = 1;
3367                 ap->ability_match_cfg = 0;
3368                 ap->ability_match_count = 0;
3369                 ap->ability_match = 0;
3370                 ap->ack_match = 0;
3371
3372                 rx_cfg_reg = 0;
3373         }
3374
3375         ap->rxconfig = rx_cfg_reg;
3376         ret = ANEG_OK;
3377
3378         switch(ap->state) {
3379         case ANEG_STATE_UNKNOWN:
3380                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3381                         ap->state = ANEG_STATE_AN_ENABLE;
3382
3383                 /* fallthru */
3384         case ANEG_STATE_AN_ENABLE:
3385                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3386                 if (ap->flags & MR_AN_ENABLE) {
3387                         ap->link_time = 0;
3388                         ap->cur_time = 0;
3389                         ap->ability_match_cfg = 0;
3390                         ap->ability_match_count = 0;
3391                         ap->ability_match = 0;
3392                         ap->idle_match = 0;
3393                         ap->ack_match = 0;
3394
3395                         ap->state = ANEG_STATE_RESTART_INIT;
3396                 } else {
3397                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3398                 }
3399                 break;
3400
3401         case ANEG_STATE_RESTART_INIT:
3402                 ap->link_time = ap->cur_time;
3403                 ap->flags &= ~(MR_NP_LOADED);
3404                 ap->txconfig = 0;
3405                 tw32(MAC_TX_AUTO_NEG, 0);
3406                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3407                 tw32_f(MAC_MODE, tp->mac_mode);
3408                 udelay(40);
3409
3410                 ret = ANEG_TIMER_ENAB;
3411                 ap->state = ANEG_STATE_RESTART;
3412
3413                 /* fallthru */
3414         case ANEG_STATE_RESTART:
3415                 delta = ap->cur_time - ap->link_time;
3416                 if (delta > ANEG_STATE_SETTLE_TIME) {
3417                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3418                 } else {
3419                         ret = ANEG_TIMER_ENAB;
3420                 }
3421                 break;
3422
3423         case ANEG_STATE_DISABLE_LINK_OK:
3424                 ret = ANEG_DONE;
3425                 break;
3426
3427         case ANEG_STATE_ABILITY_DETECT_INIT:
3428                 ap->flags &= ~(MR_TOGGLE_TX);
3429                 ap->txconfig = ANEG_CFG_FD;
3430                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3431                 if (flowctrl & ADVERTISE_1000XPAUSE)
3432                         ap->txconfig |= ANEG_CFG_PS1;
3433                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3434                         ap->txconfig |= ANEG_CFG_PS2;
3435                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3436                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3437                 tw32_f(MAC_MODE, tp->mac_mode);
3438                 udelay(40);
3439
3440                 ap->state = ANEG_STATE_ABILITY_DETECT;
3441                 break;
3442
3443         case ANEG_STATE_ABILITY_DETECT:
3444                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3445                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3446                 }
3447                 break;
3448
3449         case ANEG_STATE_ACK_DETECT_INIT:
3450                 ap->txconfig |= ANEG_CFG_ACK;
3451                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3452                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3453                 tw32_f(MAC_MODE, tp->mac_mode);
3454                 udelay(40);
3455
3456                 ap->state = ANEG_STATE_ACK_DETECT;
3457
3458                 /* fallthru */
3459         case ANEG_STATE_ACK_DETECT:
3460                 if (ap->ack_match != 0) {
3461                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3462                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3463                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3464                         } else {
3465                                 ap->state = ANEG_STATE_AN_ENABLE;
3466                         }
3467                 } else if (ap->ability_match != 0 &&
3468                            ap->rxconfig == 0) {
3469                         ap->state = ANEG_STATE_AN_ENABLE;
3470                 }
3471                 break;
3472
3473         case ANEG_STATE_COMPLETE_ACK_INIT:
3474                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3475                         ret = ANEG_FAILED;
3476                         break;
3477                 }
3478                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3479                                MR_LP_ADV_HALF_DUPLEX |
3480                                MR_LP_ADV_SYM_PAUSE |
3481                                MR_LP_ADV_ASYM_PAUSE |
3482                                MR_LP_ADV_REMOTE_FAULT1 |
3483                                MR_LP_ADV_REMOTE_FAULT2 |
3484                                MR_LP_ADV_NEXT_PAGE |
3485                                MR_TOGGLE_RX |
3486                                MR_NP_RX);
3487                 if (ap->rxconfig & ANEG_CFG_FD)
3488                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3489                 if (ap->rxconfig & ANEG_CFG_HD)
3490                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3491                 if (ap->rxconfig & ANEG_CFG_PS1)
3492                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3493                 if (ap->rxconfig & ANEG_CFG_PS2)
3494                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3495                 if (ap->rxconfig & ANEG_CFG_RF1)
3496                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3497                 if (ap->rxconfig & ANEG_CFG_RF2)
3498                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3499                 if (ap->rxconfig & ANEG_CFG_NP)
3500                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3501
3502                 ap->link_time = ap->cur_time;
3503
3504                 ap->flags ^= (MR_TOGGLE_TX);
3505                 if (ap->rxconfig & 0x0008)
3506                         ap->flags |= MR_TOGGLE_RX;
3507                 if (ap->rxconfig & ANEG_CFG_NP)
3508                         ap->flags |= MR_NP_RX;
3509                 ap->flags |= MR_PAGE_RX;
3510
3511                 ap->state = ANEG_STATE_COMPLETE_ACK;
3512                 ret = ANEG_TIMER_ENAB;
3513                 break;
3514
3515         case ANEG_STATE_COMPLETE_ACK:
3516                 if (ap->ability_match != 0 &&
3517                     ap->rxconfig == 0) {
3518                         ap->state = ANEG_STATE_AN_ENABLE;
3519                         break;
3520                 }
3521                 delta = ap->cur_time - ap->link_time;
3522                 if (delta > ANEG_STATE_SETTLE_TIME) {
3523                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3524                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3525                         } else {
3526                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3527                                     !(ap->flags & MR_NP_RX)) {
3528                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3529                                 } else {
3530                                         ret = ANEG_FAILED;
3531                                 }
3532                         }
3533                 }
3534                 break;
3535
3536         case ANEG_STATE_IDLE_DETECT_INIT:
3537                 ap->link_time = ap->cur_time;
3538                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3539                 tw32_f(MAC_MODE, tp->mac_mode);
3540                 udelay(40);
3541
3542                 ap->state = ANEG_STATE_IDLE_DETECT;
3543                 ret = ANEG_TIMER_ENAB;
3544                 break;
3545
3546         case ANEG_STATE_IDLE_DETECT:
3547                 if (ap->ability_match != 0 &&
3548                     ap->rxconfig == 0) {
3549                         ap->state = ANEG_STATE_AN_ENABLE;
3550                         break;
3551                 }
3552                 delta = ap->cur_time - ap->link_time;
3553                 if (delta > ANEG_STATE_SETTLE_TIME) {
3554                         /* XXX another gem from the Broadcom driver :( */
3555                         ap->state = ANEG_STATE_LINK_OK;
3556                 }
3557                 break;
3558
3559         case ANEG_STATE_LINK_OK:
3560                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3561                 ret = ANEG_DONE;
3562                 break;
3563
3564         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3565                 /* ??? unimplemented */
3566                 break;
3567
3568         case ANEG_STATE_NEXT_PAGE_WAIT:
3569                 /* ??? unimplemented */
3570                 break;
3571
3572         default:
3573                 ret = ANEG_FAILED;
3574                 break;
3575         }
3576
3577         return ret;
3578 }
3579
3580 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3581 {
3582         int res = 0;
3583         struct tg3_fiber_aneginfo aninfo;
3584         int status = ANEG_FAILED;
3585         unsigned int tick;
3586         u32 tmp;
3587
3588         tw32_f(MAC_TX_AUTO_NEG, 0);
3589
3590         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3591         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3592         udelay(40);
3593
3594         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3595         udelay(40);
3596
3597         memset(&aninfo, 0, sizeof(aninfo));
3598         aninfo.flags |= MR_AN_ENABLE;
3599         aninfo.state = ANEG_STATE_UNKNOWN;
3600         aninfo.cur_time = 0;
3601         tick = 0;
3602         while (++tick < 195000) {
3603                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3604                 if (status == ANEG_DONE || status == ANEG_FAILED)
3605                         break;
3606
3607                 udelay(1);
3608         }
3609
3610         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3611         tw32_f(MAC_MODE, tp->mac_mode);
3612         udelay(40);
3613
3614         *txflags = aninfo.txconfig;
3615         *rxflags = aninfo.flags;
3616
3617         if (status == ANEG_DONE &&
3618             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3619                              MR_LP_ADV_FULL_DUPLEX)))
3620                 res = 1;
3621
3622         return res;
3623 }
3624
3625 static void tg3_init_bcm8002(struct tg3 *tp)
3626 {
3627         u32 mac_status = tr32(MAC_STATUS);
3628         int i;
3629
3630         /* Reset when initting first time or we have a link. */
3631         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3632             !(mac_status & MAC_STATUS_PCS_SYNCED))
3633                 return;
3634
3635         /* Set PLL lock range. */
3636         tg3_writephy(tp, 0x16, 0x8007);
3637
3638         /* SW reset */
3639         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3640
3641         /* Wait for reset to complete. */
3642         /* XXX schedule_timeout() ... */
3643         for (i = 0; i < 500; i++)
3644                 udelay(10);
3645
3646         /* Config mode; select PMA/Ch 1 regs. */
3647         tg3_writephy(tp, 0x10, 0x8411);
3648
3649         /* Enable auto-lock and comdet, select txclk for tx. */
3650         tg3_writephy(tp, 0x11, 0x0a10);
3651
3652         tg3_writephy(tp, 0x18, 0x00a0);
3653         tg3_writephy(tp, 0x16, 0x41ff);
3654
3655         /* Assert and deassert POR. */
3656         tg3_writephy(tp, 0x13, 0x0400);
3657         udelay(40);
3658         tg3_writephy(tp, 0x13, 0x0000);
3659
3660         tg3_writephy(tp, 0x11, 0x0a50);
3661         udelay(40);
3662         tg3_writephy(tp, 0x11, 0x0a10);
3663
3664         /* Wait for signal to stabilize */
3665         /* XXX schedule_timeout() ... */
3666         for (i = 0; i < 15000; i++)
3667                 udelay(10);
3668
3669         /* Deselect the channel register so we can read the PHYID
3670          * later.
3671          */
3672         tg3_writephy(tp, 0x10, 0x8011);
3673 }
3674
3675 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3676 {
3677         u16 flowctrl;
3678         u32 sg_dig_ctrl, sg_dig_status;
3679         u32 serdes_cfg, expected_sg_dig_ctrl;
3680         int workaround, port_a;
3681         int current_link_up;
3682
3683         serdes_cfg = 0;
3684         expected_sg_dig_ctrl = 0;
3685         workaround = 0;
3686         port_a = 1;
3687         current_link_up = 0;
3688
3689         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3690             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3691                 workaround = 1;
3692                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3693                         port_a = 0;
3694
3695                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3696                 /* preserve bits 20-23 for voltage regulator */
3697                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3698         }
3699
3700         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3701
3702         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3703                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3704                         if (workaround) {
3705                                 u32 val = serdes_cfg;
3706
3707                                 if (port_a)
3708                                         val |= 0xc010000;
3709                                 else
3710                                         val |= 0x4010000;
3711                                 tw32_f(MAC_SERDES_CFG, val);
3712                         }
3713
3714                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3715                 }
3716                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3717                         tg3_setup_flow_control(tp, 0, 0);
3718                         current_link_up = 1;
3719                 }
3720                 goto out;
3721         }
3722
3723         /* Want auto-negotiation.  */
3724         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3725
3726         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3727         if (flowctrl & ADVERTISE_1000XPAUSE)
3728                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3729         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3730                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3731
3732         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3733                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3734                     tp->serdes_counter &&
3735                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3736                                     MAC_STATUS_RCVD_CFG)) ==
3737                      MAC_STATUS_PCS_SYNCED)) {
3738                         tp->serdes_counter--;
3739                         current_link_up = 1;
3740                         goto out;
3741                 }
3742 restart_autoneg:
3743                 if (workaround)
3744                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3745                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3746                 udelay(5);
3747                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3748
3749                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3750                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3751         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3752                                  MAC_STATUS_SIGNAL_DET)) {
3753                 sg_dig_status = tr32(SG_DIG_STATUS);
3754                 mac_status = tr32(MAC_STATUS);
3755
3756                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3757                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3758                         u32 local_adv = 0, remote_adv = 0;
3759
3760                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3761                                 local_adv |= ADVERTISE_1000XPAUSE;
3762                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3763                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3764
3765                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3766                                 remote_adv |= LPA_1000XPAUSE;
3767                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3768                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3769
3770                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3771                         current_link_up = 1;
3772                         tp->serdes_counter = 0;
3773                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3774                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3775                         if (tp->serdes_counter)
3776                                 tp->serdes_counter--;
3777                         else {
3778                                 if (workaround) {
3779                                         u32 val = serdes_cfg;
3780
3781                                         if (port_a)
3782                                                 val |= 0xc010000;
3783                                         else
3784                                                 val |= 0x4010000;
3785
3786                                         tw32_f(MAC_SERDES_CFG, val);
3787                                 }
3788
3789                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3790                                 udelay(40);
3791
3792                                 /* Link parallel detection - link is up */
3793                                 /* only if we have PCS_SYNC and not */
3794                                 /* receiving config code words */
3795                                 mac_status = tr32(MAC_STATUS);
3796                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3797                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3798                                         tg3_setup_flow_control(tp, 0, 0);
3799                                         current_link_up = 1;
3800                                         tp->tg3_flags2 |=
3801                                                 TG3_FLG2_PARALLEL_DETECT;
3802                                         tp->serdes_counter =
3803                                                 SERDES_PARALLEL_DET_TIMEOUT;
3804                                 } else
3805                                         goto restart_autoneg;
3806                         }
3807                 }
3808         } else {
3809                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3810                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3811         }
3812
3813 out:
3814         return current_link_up;
3815 }
3816
3817 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3818 {
3819         int current_link_up = 0;
3820
3821         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3822                 goto out;
3823
3824         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3825                 u32 txflags, rxflags;
3826                 int i;
3827
3828                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3829                         u32 local_adv = 0, remote_adv = 0;
3830
3831                         if (txflags & ANEG_CFG_PS1)
3832                                 local_adv |= ADVERTISE_1000XPAUSE;
3833                         if (txflags & ANEG_CFG_PS2)
3834                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3835
3836                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3837                                 remote_adv |= LPA_1000XPAUSE;
3838                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3839                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3840
3841                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3842
3843                         current_link_up = 1;
3844                 }
3845                 for (i = 0; i < 30; i++) {
3846                         udelay(20);
3847                         tw32_f(MAC_STATUS,
3848                                (MAC_STATUS_SYNC_CHANGED |
3849                                 MAC_STATUS_CFG_CHANGED));
3850                         udelay(40);
3851                         if ((tr32(MAC_STATUS) &
3852                              (MAC_STATUS_SYNC_CHANGED |
3853                               MAC_STATUS_CFG_CHANGED)) == 0)
3854                                 break;
3855                 }
3856
3857                 mac_status = tr32(MAC_STATUS);
3858                 if (current_link_up == 0 &&
3859                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3860                     !(mac_status & MAC_STATUS_RCVD_CFG))
3861                         current_link_up = 1;
3862         } else {
3863                 tg3_setup_flow_control(tp, 0, 0);
3864
3865                 /* Forcing 1000FD link up. */
3866                 current_link_up = 1;
3867
3868                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3869                 udelay(40);
3870
3871                 tw32_f(MAC_MODE, tp->mac_mode);
3872                 udelay(40);
3873         }
3874
3875 out:
3876         return current_link_up;
3877 }
3878
3879 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3880 {
3881         u32 orig_pause_cfg;
3882         u16 orig_active_speed;
3883         u8 orig_active_duplex;
3884         u32 mac_status;
3885         int current_link_up;
3886         int i;
3887
3888         orig_pause_cfg = tp->link_config.active_flowctrl;
3889         orig_active_speed = tp->link_config.active_speed;
3890         orig_active_duplex = tp->link_config.active_duplex;
3891
3892         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3893             netif_carrier_ok(tp->dev) &&
3894             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3895                 mac_status = tr32(MAC_STATUS);
3896                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3897                                MAC_STATUS_SIGNAL_DET |
3898                                MAC_STATUS_CFG_CHANGED |
3899                                MAC_STATUS_RCVD_CFG);
3900                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3901                                    MAC_STATUS_SIGNAL_DET)) {
3902                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3903                                             MAC_STATUS_CFG_CHANGED));
3904                         return 0;
3905                 }
3906         }
3907
3908         tw32_f(MAC_TX_AUTO_NEG, 0);
3909
3910         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3911         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3912         tw32_f(MAC_MODE, tp->mac_mode);
3913         udelay(40);
3914
3915         if (tp->phy_id == PHY_ID_BCM8002)
3916                 tg3_init_bcm8002(tp);
3917
3918         /* Enable link change event even when serdes polling.  */
3919         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3920         udelay(40);
3921
3922         current_link_up = 0;
3923         mac_status = tr32(MAC_STATUS);
3924
3925         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3926                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3927         else
3928                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3929
3930         tp->napi[0].hw_status->status =
3931                 (SD_STATUS_UPDATED |
3932                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3933
3934         for (i = 0; i < 100; i++) {
3935                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3936                                     MAC_STATUS_CFG_CHANGED));
3937                 udelay(5);
3938                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3939                                          MAC_STATUS_CFG_CHANGED |
3940                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3941                         break;
3942         }
3943
3944         mac_status = tr32(MAC_STATUS);
3945         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3946                 current_link_up = 0;
3947                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3948                     tp->serdes_counter == 0) {
3949                         tw32_f(MAC_MODE, (tp->mac_mode |
3950                                           MAC_MODE_SEND_CONFIGS));
3951                         udelay(1);
3952                         tw32_f(MAC_MODE, tp->mac_mode);
3953                 }
3954         }
3955
3956         if (current_link_up == 1) {
3957                 tp->link_config.active_speed = SPEED_1000;
3958                 tp->link_config.active_duplex = DUPLEX_FULL;
3959                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3960                                     LED_CTRL_LNKLED_OVERRIDE |
3961                                     LED_CTRL_1000MBPS_ON));
3962         } else {
3963                 tp->link_config.active_speed = SPEED_INVALID;
3964                 tp->link_config.active_duplex = DUPLEX_INVALID;
3965                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3966                                     LED_CTRL_LNKLED_OVERRIDE |
3967                                     LED_CTRL_TRAFFIC_OVERRIDE));
3968         }
3969
3970         if (current_link_up != netif_carrier_ok(tp->dev)) {
3971                 if (current_link_up)
3972                         netif_carrier_on(tp->dev);
3973                 else
3974                         netif_carrier_off(tp->dev);
3975                 tg3_link_report(tp);
3976         } else {
3977                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3978                 if (orig_pause_cfg != now_pause_cfg ||
3979                     orig_active_speed != tp->link_config.active_speed ||
3980                     orig_active_duplex != tp->link_config.active_duplex)
3981                         tg3_link_report(tp);
3982         }
3983
3984         return 0;
3985 }
3986
3987 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3988 {
3989         int current_link_up, err = 0;
3990         u32 bmsr, bmcr;
3991         u16 current_speed;
3992         u8 current_duplex;
3993         u32 local_adv, remote_adv;
3994
3995         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3996         tw32_f(MAC_MODE, tp->mac_mode);
3997         udelay(40);
3998
3999         tw32(MAC_EVENT, 0);
4000
4001         tw32_f(MAC_STATUS,
4002              (MAC_STATUS_SYNC_CHANGED |
4003               MAC_STATUS_CFG_CHANGED |
4004               MAC_STATUS_MI_COMPLETION |
4005               MAC_STATUS_LNKSTATE_CHANGED));
4006         udelay(40);
4007
4008         if (force_reset)
4009                 tg3_phy_reset(tp);
4010
4011         current_link_up = 0;
4012         current_speed = SPEED_INVALID;
4013         current_duplex = DUPLEX_INVALID;
4014
4015         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4016         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4017         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4018                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4019                         bmsr |= BMSR_LSTATUS;
4020                 else
4021                         bmsr &= ~BMSR_LSTATUS;
4022         }
4023
4024         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4025
4026         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4027             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4028                 /* do nothing, just check for link up at the end */
4029         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4030                 u32 adv, new_adv;
4031
4032                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4033                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4034                                   ADVERTISE_1000XPAUSE |
4035                                   ADVERTISE_1000XPSE_ASYM |
4036                                   ADVERTISE_SLCT);
4037
4038                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4039
4040                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4041                         new_adv |= ADVERTISE_1000XHALF;
4042                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4043                         new_adv |= ADVERTISE_1000XFULL;
4044
4045                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4046                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4047                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4048                         tg3_writephy(tp, MII_BMCR, bmcr);
4049
4050                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4051                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4052                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4053
4054                         return err;
4055                 }
4056         } else {
4057                 u32 new_bmcr;
4058
4059                 bmcr &= ~BMCR_SPEED1000;
4060                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4061
4062                 if (tp->link_config.duplex == DUPLEX_FULL)
4063                         new_bmcr |= BMCR_FULLDPLX;
4064
4065                 if (new_bmcr != bmcr) {
4066                         /* BMCR_SPEED1000 is a reserved bit that needs
4067                          * to be set on write.
4068                          */
4069                         new_bmcr |= BMCR_SPEED1000;
4070
4071                         /* Force a linkdown */
4072                         if (netif_carrier_ok(tp->dev)) {
4073                                 u32 adv;
4074
4075                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4076                                 adv &= ~(ADVERTISE_1000XFULL |
4077                                          ADVERTISE_1000XHALF |
4078                                          ADVERTISE_SLCT);
4079                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4080                                 tg3_writephy(tp, MII_BMCR, bmcr |
4081                                                            BMCR_ANRESTART |
4082                                                            BMCR_ANENABLE);
4083                                 udelay(10);
4084                                 netif_carrier_off(tp->dev);
4085                         }
4086                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4087                         bmcr = new_bmcr;
4088                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4089                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4090                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4091                             ASIC_REV_5714) {
4092                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4093                                         bmsr |= BMSR_LSTATUS;
4094                                 else
4095                                         bmsr &= ~BMSR_LSTATUS;
4096                         }
4097                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4098                 }
4099         }
4100
4101         if (bmsr & BMSR_LSTATUS) {
4102                 current_speed = SPEED_1000;
4103                 current_link_up = 1;
4104                 if (bmcr & BMCR_FULLDPLX)
4105                         current_duplex = DUPLEX_FULL;
4106                 else
4107                         current_duplex = DUPLEX_HALF;
4108
4109                 local_adv = 0;
4110                 remote_adv = 0;
4111
4112                 if (bmcr & BMCR_ANENABLE) {
4113                         u32 common;
4114
4115                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4116                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4117                         common = local_adv & remote_adv;
4118                         if (common & (ADVERTISE_1000XHALF |
4119                                       ADVERTISE_1000XFULL)) {
4120                                 if (common & ADVERTISE_1000XFULL)
4121                                         current_duplex = DUPLEX_FULL;
4122                                 else
4123                                         current_duplex = DUPLEX_HALF;
4124                         }
4125                         else
4126                                 current_link_up = 0;
4127                 }
4128         }
4129
4130         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4131                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4132
4133         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4134         if (tp->link_config.active_duplex == DUPLEX_HALF)
4135                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4136
4137         tw32_f(MAC_MODE, tp->mac_mode);
4138         udelay(40);
4139
4140         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4141
4142         tp->link_config.active_speed = current_speed;
4143         tp->link_config.active_duplex = current_duplex;
4144
4145         if (current_link_up != netif_carrier_ok(tp->dev)) {
4146                 if (current_link_up)
4147                         netif_carrier_on(tp->dev);
4148                 else {
4149                         netif_carrier_off(tp->dev);
4150                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4151                 }
4152                 tg3_link_report(tp);
4153         }
4154         return err;
4155 }
4156
4157 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4158 {
4159         if (tp->serdes_counter) {
4160                 /* Give autoneg time to complete. */
4161                 tp->serdes_counter--;
4162                 return;
4163         }
4164         if (!netif_carrier_ok(tp->dev) &&
4165             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4166                 u32 bmcr;
4167
4168                 tg3_readphy(tp, MII_BMCR, &bmcr);
4169                 if (bmcr & BMCR_ANENABLE) {
4170                         u32 phy1, phy2;
4171
4172                         /* Select shadow register 0x1f */
4173                         tg3_writephy(tp, 0x1c, 0x7c00);
4174                         tg3_readphy(tp, 0x1c, &phy1);
4175
4176                         /* Select expansion interrupt status register */
4177                         tg3_writephy(tp, 0x17, 0x0f01);
4178                         tg3_readphy(tp, 0x15, &phy2);
4179                         tg3_readphy(tp, 0x15, &phy2);
4180
4181                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4182                                 /* We have signal detect and not receiving
4183                                  * config code words, link is up by parallel
4184                                  * detection.
4185                                  */
4186
4187                                 bmcr &= ~BMCR_ANENABLE;
4188                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4189                                 tg3_writephy(tp, MII_BMCR, bmcr);
4190                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4191                         }
4192                 }
4193         }
4194         else if (netif_carrier_ok(tp->dev) &&
4195                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4196                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4197                 u32 phy2;
4198
4199                 /* Select expansion interrupt status register */
4200                 tg3_writephy(tp, 0x17, 0x0f01);
4201                 tg3_readphy(tp, 0x15, &phy2);
4202                 if (phy2 & 0x20) {
4203                         u32 bmcr;
4204
4205                         /* Config code words received, turn on autoneg. */
4206                         tg3_readphy(tp, MII_BMCR, &bmcr);
4207                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4208
4209                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4210
4211                 }
4212         }
4213 }
4214
4215 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4216 {
4217         int err;
4218
4219         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4220                 err = tg3_setup_fiber_phy(tp, force_reset);
4221         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4222                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4223         } else {
4224                 err = tg3_setup_copper_phy(tp, force_reset);
4225         }
4226
4227         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4228                 u32 val, scale;
4229
4230                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4231                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4232                         scale = 65;
4233                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4234                         scale = 6;
4235                 else
4236                         scale = 12;
4237
4238                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4239                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4240                 tw32(GRC_MISC_CFG, val);
4241         }
4242
4243         if (tp->link_config.active_speed == SPEED_1000 &&
4244             tp->link_config.active_duplex == DUPLEX_HALF)
4245                 tw32(MAC_TX_LENGTHS,
4246                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4247                       (6 << TX_LENGTHS_IPG_SHIFT) |
4248                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4249         else
4250                 tw32(MAC_TX_LENGTHS,
4251                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4252                       (6 << TX_LENGTHS_IPG_SHIFT) |
4253                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4254
4255         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4256                 if (netif_carrier_ok(tp->dev)) {
4257                         tw32(HOSTCC_STAT_COAL_TICKS,
4258                              tp->coal.stats_block_coalesce_usecs);
4259                 } else {
4260                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4261                 }
4262         }
4263
4264         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4265                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4266                 if (!netif_carrier_ok(tp->dev))
4267                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4268                               tp->pwrmgmt_thresh;
4269                 else
4270                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4271                 tw32(PCIE_PWR_MGMT_THRESH, val);
4272         }
4273
4274         return err;
4275 }
4276
4277 /* This is called whenever we suspect that the system chipset is re-
4278  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4279  * is bogus tx completions. We try to recover by setting the
4280  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4281  * in the workqueue.
4282  */
4283 static void tg3_tx_recover(struct tg3 *tp)
4284 {
4285         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4286                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4287
4288         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4289                "mapped I/O cycles to the network device, attempting to "
4290                "recover. Please report the problem to the driver maintainer "
4291                "and include system chipset information.\n", tp->dev->name);
4292
4293         spin_lock(&tp->lock);
4294         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4295         spin_unlock(&tp->lock);
4296 }
4297
4298 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4299 {
4300         smp_mb();
4301         return tnapi->tx_pending -
4302                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4303 }
4304
4305 /* Tigon3 never reports partial packet sends.  So we do not
4306  * need special logic to handle SKBs that have not had all
4307  * of their frags sent yet, like SunGEM does.
4308  */
4309 static void tg3_tx(struct tg3_napi *tnapi)
4310 {
4311         struct tg3 *tp = tnapi->tp;
4312         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4313         u32 sw_idx = tnapi->tx_cons;
4314         struct netdev_queue *txq;
4315         int index = tnapi - tp->napi;
4316
4317         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4318                 index--;
4319
4320         txq = netdev_get_tx_queue(tp->dev, index);
4321
4322         while (sw_idx != hw_idx) {
4323                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4324                 struct sk_buff *skb = ri->skb;
4325                 int i, tx_bug = 0;
4326
4327                 if (unlikely(skb == NULL)) {
4328                         tg3_tx_recover(tp);
4329                         return;
4330                 }
4331
4332                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4333
4334                 ri->skb = NULL;
4335
4336                 sw_idx = NEXT_TX(sw_idx);
4337
4338                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4339                         ri = &tnapi->tx_buffers[sw_idx];
4340                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4341                                 tx_bug = 1;
4342                         sw_idx = NEXT_TX(sw_idx);
4343                 }
4344
4345                 dev_kfree_skb(skb);
4346
4347                 if (unlikely(tx_bug)) {
4348                         tg3_tx_recover(tp);
4349                         return;
4350                 }
4351         }
4352
4353         tnapi->tx_cons = sw_idx;
4354
4355         /* Need to make the tx_cons update visible to tg3_start_xmit()
4356          * before checking for netif_queue_stopped().  Without the
4357          * memory barrier, there is a small possibility that tg3_start_xmit()
4358          * will miss it and cause the queue to be stopped forever.
4359          */
4360         smp_mb();
4361
4362         if (unlikely(netif_tx_queue_stopped(txq) &&
4363                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4364                 __netif_tx_lock(txq, smp_processor_id());
4365                 if (netif_tx_queue_stopped(txq) &&
4366                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4367                         netif_tx_wake_queue(txq);
4368                 __netif_tx_unlock(txq);
4369         }
4370 }
4371
4372 /* Returns size of skb allocated or < 0 on error.
4373  *
4374  * We only need to fill in the address because the other members
4375  * of the RX descriptor are invariant, see tg3_init_rings.
4376  *
4377  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4378  * posting buffers we only dirty the first cache line of the RX
4379  * descriptor (containing the address).  Whereas for the RX status
4380  * buffers the cpu only reads the last cacheline of the RX descriptor
4381  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4382  */
4383 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4384                             int src_idx, u32 dest_idx_unmasked)
4385 {
4386         struct tg3 *tp = tnapi->tp;
4387         struct tg3_rx_buffer_desc *desc;
4388         struct ring_info *map, *src_map;
4389         struct sk_buff *skb;
4390         dma_addr_t mapping;
4391         int skb_size, dest_idx;
4392         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4393
4394         src_map = NULL;
4395         switch (opaque_key) {
4396         case RXD_OPAQUE_RING_STD:
4397                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4398                 desc = &tpr->rx_std[dest_idx];
4399                 map = &tpr->rx_std_buffers[dest_idx];
4400                 if (src_idx >= 0)
4401                         src_map = &tpr->rx_std_buffers[src_idx];
4402                 skb_size = tp->rx_pkt_map_sz;
4403                 break;
4404
4405         case RXD_OPAQUE_RING_JUMBO:
4406                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4407                 desc = &tpr->rx_jmb[dest_idx].std;
4408                 map = &tpr->rx_jmb_buffers[dest_idx];
4409                 if (src_idx >= 0)
4410                         src_map = &tpr->rx_jmb_buffers[src_idx];
4411                 skb_size = TG3_RX_JMB_MAP_SZ;
4412                 break;
4413
4414         default:
4415                 return -EINVAL;
4416         }
4417
4418         /* Do not overwrite any of the map or rp information
4419          * until we are sure we can commit to a new buffer.
4420          *
4421          * Callers depend upon this behavior and assume that
4422          * we leave everything unchanged if we fail.
4423          */
4424         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4425         if (skb == NULL)
4426                 return -ENOMEM;
4427
4428         skb_reserve(skb, tp->rx_offset);
4429
4430         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4431                                  PCI_DMA_FROMDEVICE);
4432
4433         map->skb = skb;
4434         pci_unmap_addr_set(map, mapping, mapping);
4435
4436         if (src_map != NULL)
4437                 src_map->skb = NULL;
4438
4439         desc->addr_hi = ((u64)mapping >> 32);
4440         desc->addr_lo = ((u64)mapping & 0xffffffff);
4441
4442         return skb_size;
4443 }
4444
4445 /* We only need to move over in the address because the other
4446  * members of the RX descriptor are invariant.  See notes above
4447  * tg3_alloc_rx_skb for full details.
4448  */
4449 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4450                            int src_idx, u32 dest_idx_unmasked)
4451 {
4452         struct tg3 *tp = tnapi->tp;
4453         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4454         struct ring_info *src_map, *dest_map;
4455         int dest_idx;
4456         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4457
4458         switch (opaque_key) {
4459         case RXD_OPAQUE_RING_STD:
4460                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4461                 dest_desc = &tpr->rx_std[dest_idx];
4462                 dest_map = &tpr->rx_std_buffers[dest_idx];
4463                 src_desc = &tpr->rx_std[src_idx];
4464                 src_map = &tpr->rx_std_buffers[src_idx];
4465                 break;
4466
4467         case RXD_OPAQUE_RING_JUMBO:
4468                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4469                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4470                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4471                 src_desc = &tpr->rx_jmb[src_idx].std;
4472                 src_map = &tpr->rx_jmb_buffers[src_idx];
4473                 break;
4474
4475         default:
4476                 return;
4477         }
4478
4479         dest_map->skb = src_map->skb;
4480         pci_unmap_addr_set(dest_map, mapping,
4481                            pci_unmap_addr(src_map, mapping));
4482         dest_desc->addr_hi = src_desc->addr_hi;
4483         dest_desc->addr_lo = src_desc->addr_lo;
4484
4485         src_map->skb = NULL;
4486 }
4487
4488 /* The RX ring scheme is composed of multiple rings which post fresh
4489  * buffers to the chip, and one special ring the chip uses to report
4490  * status back to the host.
4491  *
4492  * The special ring reports the status of received packets to the
4493  * host.  The chip does not write into the original descriptor the
4494  * RX buffer was obtained from.  The chip simply takes the original
4495  * descriptor as provided by the host, updates the status and length
4496  * field, then writes this into the next status ring entry.
4497  *
4498  * Each ring the host uses to post buffers to the chip is described
4499  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4500  * it is first placed into the on-chip ram.  When the packet's length
4501  * is known, it walks down the TG3_BDINFO entries to select the ring.
4502  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4503  * which is within the range of the new packet's length is chosen.
4504  *
4505  * The "separate ring for rx status" scheme may sound queer, but it makes
4506  * sense from a cache coherency perspective.  If only the host writes
4507  * to the buffer post rings, and only the chip writes to the rx status
4508  * rings, then cache lines never move beyond shared-modified state.
4509  * If both the host and chip were to write into the same ring, cache line
4510  * eviction could occur since both entities want it in an exclusive state.
4511  */
4512 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4513 {
4514         struct tg3 *tp = tnapi->tp;
4515         u32 work_mask, rx_std_posted = 0;
4516         u32 sw_idx = tnapi->rx_rcb_ptr;
4517         u16 hw_idx;
4518         int received;
4519         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4520
4521         hw_idx = tnapi->hw_status->idx[0].rx_producer;
4522         /*
4523          * We need to order the read of hw_idx and the read of
4524          * the opaque cookie.
4525          */
4526         rmb();
4527         work_mask = 0;
4528         received = 0;
4529         while (sw_idx != hw_idx && budget > 0) {
4530                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4531                 unsigned int len;
4532                 struct sk_buff *skb;
4533                 dma_addr_t dma_addr;
4534                 u32 opaque_key, desc_idx, *post_ptr;
4535
4536                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4537                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4538                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4539                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4540                         dma_addr = pci_unmap_addr(ri, mapping);
4541                         skb = ri->skb;
4542                         post_ptr = &tpr->rx_std_ptr;
4543                         rx_std_posted++;
4544                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4545                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4546                         dma_addr = pci_unmap_addr(ri, mapping);
4547                         skb = ri->skb;
4548                         post_ptr = &tpr->rx_jmb_ptr;
4549                 } else
4550                         goto next_pkt_nopost;
4551
4552                 work_mask |= opaque_key;
4553
4554                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4555                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4556                 drop_it:
4557                         tg3_recycle_rx(tnapi, opaque_key,
4558                                        desc_idx, *post_ptr);
4559                 drop_it_no_recycle:
4560                         /* Other statistics kept track of by card. */
4561                         tp->net_stats.rx_dropped++;
4562                         goto next_pkt;
4563                 }
4564
4565                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4566                       ETH_FCS_LEN;
4567
4568                 if (len > RX_COPY_THRESHOLD
4569                         && tp->rx_offset == NET_IP_ALIGN
4570                         /* rx_offset will likely not equal NET_IP_ALIGN
4571                          * if this is a 5701 card running in PCI-X mode
4572                          * [see tg3_get_invariants()]
4573                          */
4574                 ) {
4575                         int skb_size;
4576
4577                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4578                                                     desc_idx, *post_ptr);
4579                         if (skb_size < 0)
4580                                 goto drop_it;
4581
4582                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4583                                          PCI_DMA_FROMDEVICE);
4584
4585                         skb_put(skb, len);
4586                 } else {
4587                         struct sk_buff *copy_skb;
4588
4589                         tg3_recycle_rx(tnapi, opaque_key,
4590                                        desc_idx, *post_ptr);
4591
4592                         copy_skb = netdev_alloc_skb(tp->dev,
4593                                                     len + TG3_RAW_IP_ALIGN);
4594                         if (copy_skb == NULL)
4595                                 goto drop_it_no_recycle;
4596
4597                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4598                         skb_put(copy_skb, len);
4599                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4600                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4601                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4602
4603                         /* We'll reuse the original ring buffer. */
4604                         skb = copy_skb;
4605                 }
4606
4607                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4608                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4609                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4610                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4611                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4612                 else
4613                         skb->ip_summed = CHECKSUM_NONE;
4614
4615                 skb->protocol = eth_type_trans(skb, tp->dev);
4616
4617                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4618                     skb->protocol != htons(ETH_P_8021Q)) {
4619                         dev_kfree_skb(skb);
4620                         goto next_pkt;
4621                 }
4622
4623 #if TG3_VLAN_TAG_USED
4624                 if (tp->vlgrp != NULL &&
4625                     desc->type_flags & RXD_FLAG_VLAN) {
4626                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4627                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4628                 } else
4629 #endif
4630                         napi_gro_receive(&tnapi->napi, skb);
4631
4632                 received++;
4633                 budget--;
4634
4635 next_pkt:
4636                 (*post_ptr)++;
4637
4638                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4639                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4640
4641                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4642                                      TG3_64BIT_REG_LOW, idx);
4643                         work_mask &= ~RXD_OPAQUE_RING_STD;
4644                         rx_std_posted = 0;
4645                 }
4646 next_pkt_nopost:
4647                 sw_idx++;
4648                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4649
4650                 /* Refresh hw_idx to see if there is new work */
4651                 if (sw_idx == hw_idx) {
4652                         hw_idx = tnapi->hw_status->idx[0].rx_producer;
4653                         rmb();
4654                 }
4655         }
4656
4657         /* ACK the status ring. */
4658         tnapi->rx_rcb_ptr = sw_idx;
4659         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4660
4661         /* Refill RX ring(s). */
4662         if (work_mask & RXD_OPAQUE_RING_STD) {
4663                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4664                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4665                              sw_idx);
4666         }
4667         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4668                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4669                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4670                              sw_idx);
4671         }
4672         mmiowb();
4673
4674         return received;
4675 }
4676
4677 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4678 {
4679         struct tg3 *tp = tnapi->tp;
4680         struct tg3_hw_status *sblk = tnapi->hw_status;
4681
4682         /* handle link change and other phy events */
4683         if (!(tp->tg3_flags &
4684               (TG3_FLAG_USE_LINKCHG_REG |
4685                TG3_FLAG_POLL_SERDES))) {
4686                 if (sblk->status & SD_STATUS_LINK_CHG) {
4687                         sblk->status = SD_STATUS_UPDATED |
4688                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4689                         spin_lock(&tp->lock);
4690                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4691                                 tw32_f(MAC_STATUS,
4692                                      (MAC_STATUS_SYNC_CHANGED |
4693                                       MAC_STATUS_CFG_CHANGED |
4694                                       MAC_STATUS_MI_COMPLETION |
4695                                       MAC_STATUS_LNKSTATE_CHANGED));
4696                                 udelay(40);
4697                         } else
4698                                 tg3_setup_phy(tp, 0);
4699                         spin_unlock(&tp->lock);
4700                 }
4701         }
4702
4703         /* run TX completion thread */
4704         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4705                 tg3_tx(tnapi);
4706                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4707                         return work_done;
4708         }
4709
4710         /* run RX thread, within the bounds set by NAPI.
4711          * All RX "locking" is done by ensuring outside
4712          * code synchronizes with tg3->napi.poll()
4713          */
4714         if (sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
4715                 work_done += tg3_rx(tnapi, budget - work_done);
4716
4717         return work_done;
4718 }
4719
4720 static int tg3_poll(struct napi_struct *napi, int budget)
4721 {
4722         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4723         struct tg3 *tp = tnapi->tp;
4724         int work_done = 0;
4725         struct tg3_hw_status *sblk = tnapi->hw_status;
4726
4727         while (1) {
4728                 work_done = tg3_poll_work(tnapi, work_done, budget);
4729
4730                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4731                         goto tx_recovery;
4732
4733                 if (unlikely(work_done >= budget))
4734                         break;
4735
4736                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4737                         /* tp->last_tag is used in tg3_int_reenable() below
4738                          * to tell the hw how much work has been processed,
4739                          * so we must read it before checking for more work.
4740                          */
4741                         tnapi->last_tag = sblk->status_tag;
4742                         tnapi->last_irq_tag = tnapi->last_tag;
4743                         rmb();
4744                 } else
4745                         sblk->status &= ~SD_STATUS_UPDATED;
4746
4747                 if (likely(!tg3_has_work(tnapi))) {
4748                         napi_complete(napi);
4749                         tg3_int_reenable(tnapi);
4750                         break;
4751                 }
4752         }
4753
4754         return work_done;
4755
4756 tx_recovery:
4757         /* work_done is guaranteed to be less than budget. */
4758         napi_complete(napi);
4759         schedule_work(&tp->reset_task);
4760         return work_done;
4761 }
4762
4763 static void tg3_irq_quiesce(struct tg3 *tp)
4764 {
4765         int i;
4766
4767         BUG_ON(tp->irq_sync);
4768
4769         tp->irq_sync = 1;
4770         smp_mb();
4771
4772         for (i = 0; i < tp->irq_cnt; i++)
4773                 synchronize_irq(tp->napi[i].irq_vec);
4774 }
4775
4776 static inline int tg3_irq_sync(struct tg3 *tp)
4777 {
4778         return tp->irq_sync;
4779 }
4780
4781 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4782  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4783  * with as well.  Most of the time, this is not necessary except when
4784  * shutting down the device.
4785  */
4786 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4787 {
4788         spin_lock_bh(&tp->lock);
4789         if (irq_sync)
4790                 tg3_irq_quiesce(tp);
4791 }
4792
4793 static inline void tg3_full_unlock(struct tg3 *tp)
4794 {
4795         spin_unlock_bh(&tp->lock);
4796 }
4797
4798 /* One-shot MSI handler - Chip automatically disables interrupt
4799  * after sending MSI so driver doesn't have to do it.
4800  */
4801 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4802 {
4803         struct tg3_napi *tnapi = dev_id;
4804         struct tg3 *tp = tnapi->tp;
4805
4806         prefetch(tnapi->hw_status);
4807         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4808
4809         if (likely(!tg3_irq_sync(tp)))
4810                 napi_schedule(&tnapi->napi);
4811
4812         return IRQ_HANDLED;
4813 }
4814
4815 /* MSI ISR - No need to check for interrupt sharing and no need to
4816  * flush status block and interrupt mailbox. PCI ordering rules
4817  * guarantee that MSI will arrive after the status block.
4818  */
4819 static irqreturn_t tg3_msi(int irq, void *dev_id)
4820 {
4821         struct tg3_napi *tnapi = dev_id;
4822         struct tg3 *tp = tnapi->tp;
4823
4824         prefetch(tnapi->hw_status);
4825         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4826         /*
4827          * Writing any value to intr-mbox-0 clears PCI INTA# and
4828          * chip-internal interrupt pending events.
4829          * Writing non-zero to intr-mbox-0 additional tells the
4830          * NIC to stop sending us irqs, engaging "in-intr-handler"
4831          * event coalescing.
4832          */
4833         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4834         if (likely(!tg3_irq_sync(tp)))
4835                 napi_schedule(&tnapi->napi);
4836
4837         return IRQ_RETVAL(1);
4838 }
4839
4840 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4841 {
4842         struct tg3_napi *tnapi = dev_id;
4843         struct tg3 *tp = tnapi->tp;
4844         struct tg3_hw_status *sblk = tnapi->hw_status;
4845         unsigned int handled = 1;
4846
4847         /* In INTx mode, it is possible for the interrupt to arrive at
4848          * the CPU before the status block posted prior to the interrupt.
4849          * Reading the PCI State register will confirm whether the
4850          * interrupt is ours and will flush the status block.
4851          */
4852         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4853                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4854                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4855                         handled = 0;
4856                         goto out;
4857                 }
4858         }
4859
4860         /*
4861          * Writing any value to intr-mbox-0 clears PCI INTA# and
4862          * chip-internal interrupt pending events.
4863          * Writing non-zero to intr-mbox-0 additional tells the
4864          * NIC to stop sending us irqs, engaging "in-intr-handler"
4865          * event coalescing.
4866          *
4867          * Flush the mailbox to de-assert the IRQ immediately to prevent
4868          * spurious interrupts.  The flush impacts performance but
4869          * excessive spurious interrupts can be worse in some cases.
4870          */
4871         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4872         if (tg3_irq_sync(tp))
4873                 goto out;
4874         sblk->status &= ~SD_STATUS_UPDATED;
4875         if (likely(tg3_has_work(tnapi))) {
4876                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4877                 napi_schedule(&tnapi->napi);
4878         } else {
4879                 /* No work, shared interrupt perhaps?  re-enable
4880                  * interrupts, and flush that PCI write
4881                  */
4882                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4883                                0x00000000);
4884         }
4885 out:
4886         return IRQ_RETVAL(handled);
4887 }
4888
4889 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4890 {
4891         struct tg3_napi *tnapi = dev_id;
4892         struct tg3 *tp = tnapi->tp;
4893         struct tg3_hw_status *sblk = tnapi->hw_status;
4894         unsigned int handled = 1;
4895
4896         /* In INTx mode, it is possible for the interrupt to arrive at
4897          * the CPU before the status block posted prior to the interrupt.
4898          * Reading the PCI State register will confirm whether the
4899          * interrupt is ours and will flush the status block.
4900          */
4901         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4902                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4903                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4904                         handled = 0;
4905                         goto out;
4906                 }
4907         }
4908
4909         /*
4910          * writing any value to intr-mbox-0 clears PCI INTA# and
4911          * chip-internal interrupt pending events.
4912          * writing non-zero to intr-mbox-0 additional tells the
4913          * NIC to stop sending us irqs, engaging "in-intr-handler"
4914          * event coalescing.
4915          *
4916          * Flush the mailbox to de-assert the IRQ immediately to prevent
4917          * spurious interrupts.  The flush impacts performance but
4918          * excessive spurious interrupts can be worse in some cases.
4919          */
4920         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4921
4922         /*
4923          * In a shared interrupt configuration, sometimes other devices'
4924          * interrupts will scream.  We record the current status tag here
4925          * so that the above check can report that the screaming interrupts
4926          * are unhandled.  Eventually they will be silenced.
4927          */
4928         tnapi->last_irq_tag = sblk->status_tag;
4929
4930         if (tg3_irq_sync(tp))
4931                 goto out;
4932
4933         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4934
4935         napi_schedule(&tnapi->napi);
4936
4937 out:
4938         return IRQ_RETVAL(handled);
4939 }
4940
4941 /* ISR for interrupt test */
4942 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4943 {
4944         struct tg3_napi *tnapi = dev_id;
4945         struct tg3 *tp = tnapi->tp;
4946         struct tg3_hw_status *sblk = tnapi->hw_status;
4947
4948         if ((sblk->status & SD_STATUS_UPDATED) ||
4949             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4950                 tg3_disable_ints(tp);
4951                 return IRQ_RETVAL(1);
4952         }
4953         return IRQ_RETVAL(0);
4954 }
4955
4956 static int tg3_init_hw(struct tg3 *, int);
4957 static int tg3_halt(struct tg3 *, int, int);
4958
4959 /* Restart hardware after configuration changes, self-test, etc.
4960  * Invoked with tp->lock held.
4961  */
4962 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4963         __releases(tp->lock)
4964         __acquires(tp->lock)
4965 {
4966         int err;
4967
4968         err = tg3_init_hw(tp, reset_phy);
4969         if (err) {
4970                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4971                        "aborting.\n", tp->dev->name);
4972                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4973                 tg3_full_unlock(tp);
4974                 del_timer_sync(&tp->timer);
4975                 tp->irq_sync = 0;
4976                 tg3_napi_enable(tp);
4977                 dev_close(tp->dev);
4978                 tg3_full_lock(tp, 0);
4979         }
4980         return err;
4981 }
4982
4983 #ifdef CONFIG_NET_POLL_CONTROLLER
4984 static void tg3_poll_controller(struct net_device *dev)
4985 {
4986         int i;
4987         struct tg3 *tp = netdev_priv(dev);
4988
4989         for (i = 0; i < tp->irq_cnt; i++)
4990                 tg3_interrupt(tp->napi[i].irq_vec, dev);
4991 }
4992 #endif
4993
4994 static void tg3_reset_task(struct work_struct *work)
4995 {
4996         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4997         int err;
4998         unsigned int restart_timer;
4999
5000         tg3_full_lock(tp, 0);
5001
5002         if (!netif_running(tp->dev)) {
5003                 tg3_full_unlock(tp);
5004                 return;
5005         }
5006
5007         tg3_full_unlock(tp);
5008
5009         tg3_phy_stop(tp);
5010
5011         tg3_netif_stop(tp);
5012
5013         tg3_full_lock(tp, 1);
5014
5015         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5016         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5017
5018         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5019                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5020                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5021                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5022                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5023         }
5024
5025         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5026         err = tg3_init_hw(tp, 1);
5027         if (err)
5028                 goto out;
5029
5030         tg3_netif_start(tp);
5031
5032         if (restart_timer)
5033                 mod_timer(&tp->timer, jiffies + 1);
5034
5035 out:
5036         tg3_full_unlock(tp);
5037
5038         if (!err)
5039                 tg3_phy_start(tp);
5040 }
5041
5042 static void tg3_dump_short_state(struct tg3 *tp)
5043 {
5044         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5045                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5046         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5047                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5048 }
5049
5050 static void tg3_tx_timeout(struct net_device *dev)
5051 {
5052         struct tg3 *tp = netdev_priv(dev);
5053
5054         if (netif_msg_tx_err(tp)) {
5055                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5056                        dev->name);
5057                 tg3_dump_short_state(tp);
5058         }
5059
5060         schedule_work(&tp->reset_task);
5061 }
5062
5063 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5064 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5065 {
5066         u32 base = (u32) mapping & 0xffffffff;
5067
5068         return ((base > 0xffffdcc0) &&
5069                 (base + len + 8 < base));
5070 }
5071
5072 /* Test for DMA addresses > 40-bit */
5073 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5074                                           int len)
5075 {
5076 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5077         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5078                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5079         return 0;
5080 #else
5081         return 0;
5082 #endif
5083 }
5084
5085 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5086
5087 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5088 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5089                                        u32 last_plus_one, u32 *start,
5090                                        u32 base_flags, u32 mss)
5091 {
5092         struct tg3_napi *tnapi = &tp->napi[0];
5093         struct sk_buff *new_skb;
5094         dma_addr_t new_addr = 0;
5095         u32 entry = *start;
5096         int i, ret = 0;
5097
5098         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5099                 new_skb = skb_copy(skb, GFP_ATOMIC);
5100         else {
5101                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5102
5103                 new_skb = skb_copy_expand(skb,
5104                                           skb_headroom(skb) + more_headroom,
5105                                           skb_tailroom(skb), GFP_ATOMIC);
5106         }
5107
5108         if (!new_skb) {
5109                 ret = -1;
5110         } else {
5111                 /* New SKB is guaranteed to be linear. */
5112                 entry = *start;
5113                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5114                 new_addr = skb_shinfo(new_skb)->dma_head;
5115
5116                 /* Make sure new skb does not cross any 4G boundaries.
5117                  * Drop the packet if it does.
5118                  */
5119                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5120                         if (!ret)
5121                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5122                                               DMA_TO_DEVICE);
5123                         ret = -1;
5124                         dev_kfree_skb(new_skb);
5125                         new_skb = NULL;
5126                 } else {
5127                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5128                                     base_flags, 1 | (mss << 1));
5129                         *start = NEXT_TX(entry);
5130                 }
5131         }
5132
5133         /* Now clean up the sw ring entries. */
5134         i = 0;
5135         while (entry != last_plus_one) {
5136                 if (i == 0)
5137                         tnapi->tx_buffers[entry].skb = new_skb;
5138                 else
5139                         tnapi->tx_buffers[entry].skb = NULL;
5140                 entry = NEXT_TX(entry);
5141                 i++;
5142         }
5143
5144         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5145         dev_kfree_skb(skb);
5146
5147         return ret;
5148 }
5149
5150 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5151                         dma_addr_t mapping, int len, u32 flags,
5152                         u32 mss_and_is_end)
5153 {
5154         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5155         int is_end = (mss_and_is_end & 0x1);
5156         u32 mss = (mss_and_is_end >> 1);
5157         u32 vlan_tag = 0;
5158
5159         if (is_end)
5160                 flags |= TXD_FLAG_END;
5161         if (flags & TXD_FLAG_VLAN) {
5162                 vlan_tag = flags >> 16;
5163                 flags &= 0xffff;
5164         }
5165         vlan_tag |= (mss << TXD_MSS_SHIFT);
5166
5167         txd->addr_hi = ((u64) mapping >> 32);
5168         txd->addr_lo = ((u64) mapping & 0xffffffff);
5169         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5170         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5171 }
5172
5173 /* hard_start_xmit for devices that don't have any bugs and
5174  * support TG3_FLG2_HW_TSO_2 only.
5175  */
5176 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5177                                   struct net_device *dev)
5178 {
5179         struct tg3 *tp = netdev_priv(dev);
5180         u32 len, entry, base_flags, mss;
5181         struct skb_shared_info *sp;
5182         dma_addr_t mapping;
5183         struct tg3_napi *tnapi;
5184         struct netdev_queue *txq;
5185
5186         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5187         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5188         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5189                 tnapi++;
5190
5191         /* We are running in BH disabled context with netif_tx_lock
5192          * and TX reclaim runs via tp->napi.poll inside of a software
5193          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5194          * no IRQ context deadlocks to worry about either.  Rejoice!
5195          */
5196         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5197                 if (!netif_tx_queue_stopped(txq)) {
5198                         netif_tx_stop_queue(txq);
5199
5200                         /* This is a hard error, log it. */
5201                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5202                                "queue awake!\n", dev->name);
5203                 }
5204                 return NETDEV_TX_BUSY;
5205         }
5206
5207         entry = tnapi->tx_prod;
5208         base_flags = 0;
5209         mss = 0;
5210         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5211                 int tcp_opt_len, ip_tcp_len;
5212
5213                 if (skb_header_cloned(skb) &&
5214                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5215                         dev_kfree_skb(skb);
5216                         goto out_unlock;
5217                 }
5218
5219                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5220                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5221                 else {
5222                         struct iphdr *iph = ip_hdr(skb);
5223
5224                         tcp_opt_len = tcp_optlen(skb);
5225                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5226
5227                         iph->check = 0;
5228                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5229                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
5230                 }
5231
5232                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5233                                TXD_FLAG_CPU_POST_DMA);
5234
5235                 tcp_hdr(skb)->check = 0;
5236
5237         }
5238         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5239                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5240 #if TG3_VLAN_TAG_USED
5241         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5242                 base_flags |= (TXD_FLAG_VLAN |
5243                                (vlan_tx_tag_get(skb) << 16));
5244 #endif
5245
5246         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5247                 dev_kfree_skb(skb);
5248                 goto out_unlock;
5249         }
5250
5251         sp = skb_shinfo(skb);
5252
5253         mapping = sp->dma_head;
5254
5255         tnapi->tx_buffers[entry].skb = skb;
5256
5257         len = skb_headlen(skb);
5258
5259         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5260                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5261
5262         entry = NEXT_TX(entry);
5263
5264         /* Now loop through additional data fragments, and queue them. */
5265         if (skb_shinfo(skb)->nr_frags > 0) {
5266                 unsigned int i, last;
5267
5268                 last = skb_shinfo(skb)->nr_frags - 1;
5269                 for (i = 0; i <= last; i++) {
5270                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5271
5272                         len = frag->size;
5273                         mapping = sp->dma_maps[i];
5274                         tnapi->tx_buffers[entry].skb = NULL;
5275
5276                         tg3_set_txd(tnapi, entry, mapping, len,
5277                                     base_flags, (i == last) | (mss << 1));
5278
5279                         entry = NEXT_TX(entry);
5280                 }
5281         }
5282
5283         /* Packets are ready, update Tx producer idx local and on card. */
5284         tw32_tx_mbox(tnapi->prodmbox, entry);
5285
5286         tnapi->tx_prod = entry;
5287         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5288                 netif_tx_stop_queue(txq);
5289                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5290                         netif_tx_wake_queue(txq);
5291         }
5292
5293 out_unlock:
5294         mmiowb();
5295
5296         return NETDEV_TX_OK;
5297 }
5298
5299 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5300                                           struct net_device *);
5301
5302 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5303  * TSO header is greater than 80 bytes.
5304  */
5305 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5306 {
5307         struct sk_buff *segs, *nskb;
5308         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5309
5310         /* Estimate the number of fragments in the worst case */
5311         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5312                 netif_stop_queue(tp->dev);
5313                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5314                         return NETDEV_TX_BUSY;
5315
5316                 netif_wake_queue(tp->dev);
5317         }
5318
5319         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5320         if (IS_ERR(segs))
5321                 goto tg3_tso_bug_end;
5322
5323         do {
5324                 nskb = segs;
5325                 segs = segs->next;
5326                 nskb->next = NULL;
5327                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5328         } while (segs);
5329
5330 tg3_tso_bug_end:
5331         dev_kfree_skb(skb);
5332
5333         return NETDEV_TX_OK;
5334 }
5335
5336 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5337  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5338  */
5339 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5340                                           struct net_device *dev)
5341 {
5342         struct tg3 *tp = netdev_priv(dev);
5343         u32 len, entry, base_flags, mss;
5344         struct skb_shared_info *sp;
5345         int would_hit_hwbug;
5346         dma_addr_t mapping;
5347         struct tg3_napi *tnapi = &tp->napi[0];
5348
5349         len = skb_headlen(skb);
5350
5351         /* We are running in BH disabled context with netif_tx_lock
5352          * and TX reclaim runs via tp->napi.poll inside of a software
5353          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5354          * no IRQ context deadlocks to worry about either.  Rejoice!
5355          */
5356         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5357                 if (!netif_queue_stopped(dev)) {
5358                         netif_stop_queue(dev);
5359
5360                         /* This is a hard error, log it. */
5361                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5362                                "queue awake!\n", dev->name);
5363                 }
5364                 return NETDEV_TX_BUSY;
5365         }
5366
5367         entry = tnapi->tx_prod;
5368         base_flags = 0;
5369         if (skb->ip_summed == CHECKSUM_PARTIAL)
5370                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5371         mss = 0;
5372         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5373                 struct iphdr *iph;
5374                 int tcp_opt_len, ip_tcp_len, hdr_len;
5375
5376                 if (skb_header_cloned(skb) &&
5377                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5378                         dev_kfree_skb(skb);
5379                         goto out_unlock;
5380                 }
5381
5382                 tcp_opt_len = tcp_optlen(skb);
5383                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5384
5385                 hdr_len = ip_tcp_len + tcp_opt_len;
5386                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5387                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5388                         return (tg3_tso_bug(tp, skb));
5389
5390                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5391                                TXD_FLAG_CPU_POST_DMA);
5392
5393                 iph = ip_hdr(skb);
5394                 iph->check = 0;
5395                 iph->tot_len = htons(mss + hdr_len);
5396                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5397                         tcp_hdr(skb)->check = 0;
5398                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5399                 } else
5400                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5401                                                                  iph->daddr, 0,
5402                                                                  IPPROTO_TCP,
5403                                                                  0);
5404
5405                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5406                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5407                         if (tcp_opt_len || iph->ihl > 5) {
5408                                 int tsflags;
5409
5410                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5411                                 mss |= (tsflags << 11);
5412                         }
5413                 } else {
5414                         if (tcp_opt_len || iph->ihl > 5) {
5415                                 int tsflags;
5416
5417                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5418                                 base_flags |= tsflags << 12;
5419                         }
5420                 }
5421         }
5422 #if TG3_VLAN_TAG_USED
5423         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5424                 base_flags |= (TXD_FLAG_VLAN |
5425                                (vlan_tx_tag_get(skb) << 16));
5426 #endif
5427
5428         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5429                 dev_kfree_skb(skb);
5430                 goto out_unlock;
5431         }
5432
5433         sp = skb_shinfo(skb);
5434
5435         mapping = sp->dma_head;
5436
5437         tnapi->tx_buffers[entry].skb = skb;
5438
5439         would_hit_hwbug = 0;
5440
5441         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5442                 would_hit_hwbug = 1;
5443         else if (tg3_4g_overflow_test(mapping, len))
5444                 would_hit_hwbug = 1;
5445
5446         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5447                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5448
5449         entry = NEXT_TX(entry);
5450
5451         /* Now loop through additional data fragments, and queue them. */
5452         if (skb_shinfo(skb)->nr_frags > 0) {
5453                 unsigned int i, last;
5454
5455                 last = skb_shinfo(skb)->nr_frags - 1;
5456                 for (i = 0; i <= last; i++) {
5457                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5458
5459                         len = frag->size;
5460                         mapping = sp->dma_maps[i];
5461
5462                         tnapi->tx_buffers[entry].skb = NULL;
5463
5464                         if (tg3_4g_overflow_test(mapping, len))
5465                                 would_hit_hwbug = 1;
5466
5467                         if (tg3_40bit_overflow_test(tp, mapping, len))
5468                                 would_hit_hwbug = 1;
5469
5470                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5471                                 tg3_set_txd(tnapi, entry, mapping, len,
5472                                             base_flags, (i == last)|(mss << 1));
5473                         else
5474                                 tg3_set_txd(tnapi, entry, mapping, len,
5475                                             base_flags, (i == last));
5476
5477                         entry = NEXT_TX(entry);
5478                 }
5479         }
5480
5481         if (would_hit_hwbug) {
5482                 u32 last_plus_one = entry;
5483                 u32 start;
5484
5485                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5486                 start &= (TG3_TX_RING_SIZE - 1);
5487
5488                 /* If the workaround fails due to memory/mapping
5489                  * failure, silently drop this packet.
5490                  */
5491                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5492                                                 &start, base_flags, mss))
5493                         goto out_unlock;
5494
5495                 entry = start;
5496         }
5497
5498         /* Packets are ready, update Tx producer idx local and on card. */
5499         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5500
5501         tnapi->tx_prod = entry;
5502         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5503                 netif_stop_queue(dev);
5504                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5505                         netif_wake_queue(tp->dev);
5506         }
5507
5508 out_unlock:
5509         mmiowb();
5510
5511         return NETDEV_TX_OK;
5512 }
5513
5514 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5515                                int new_mtu)
5516 {
5517         dev->mtu = new_mtu;
5518
5519         if (new_mtu > ETH_DATA_LEN) {
5520                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5521                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5522                         ethtool_op_set_tso(dev, 0);
5523                 }
5524                 else
5525                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5526         } else {
5527                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5528                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5529                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5530         }
5531 }
5532
5533 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5534 {
5535         struct tg3 *tp = netdev_priv(dev);
5536         int err;
5537
5538         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5539                 return -EINVAL;
5540
5541         if (!netif_running(dev)) {
5542                 /* We'll just catch it later when the
5543                  * device is up'd.
5544                  */
5545                 tg3_set_mtu(dev, tp, new_mtu);
5546                 return 0;
5547         }
5548
5549         tg3_phy_stop(tp);
5550
5551         tg3_netif_stop(tp);
5552
5553         tg3_full_lock(tp, 1);
5554
5555         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5556
5557         tg3_set_mtu(dev, tp, new_mtu);
5558
5559         err = tg3_restart_hw(tp, 0);
5560
5561         if (!err)
5562                 tg3_netif_start(tp);
5563
5564         tg3_full_unlock(tp);
5565
5566         if (!err)
5567                 tg3_phy_start(tp);
5568
5569         return err;
5570 }
5571
5572 static void tg3_rx_prodring_free(struct tg3 *tp,
5573                                  struct tg3_rx_prodring_set *tpr)
5574 {
5575         int i;
5576         struct ring_info *rxp;
5577
5578         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5579                 rxp = &tpr->rx_std_buffers[i];
5580
5581                 if (rxp->skb == NULL)
5582                         continue;
5583
5584                 pci_unmap_single(tp->pdev,
5585                                  pci_unmap_addr(rxp, mapping),
5586                                  tp->rx_pkt_map_sz,
5587                                  PCI_DMA_FROMDEVICE);
5588                 dev_kfree_skb_any(rxp->skb);
5589                 rxp->skb = NULL;
5590         }
5591
5592         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5593                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5594                         rxp = &tpr->rx_jmb_buffers[i];
5595
5596                         if (rxp->skb == NULL)
5597                                 continue;
5598
5599                         pci_unmap_single(tp->pdev,
5600                                          pci_unmap_addr(rxp, mapping),
5601                                          TG3_RX_JMB_MAP_SZ,
5602                                          PCI_DMA_FROMDEVICE);
5603                         dev_kfree_skb_any(rxp->skb);
5604                         rxp->skb = NULL;
5605                 }
5606         }
5607 }
5608
5609 /* Initialize tx/rx rings for packet processing.
5610  *
5611  * The chip has been shut down and the driver detached from
5612  * the networking, so no interrupts or new tx packets will
5613  * end up in the driver.  tp->{tx,}lock are held and thus
5614  * we may not sleep.
5615  */
5616 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5617                                  struct tg3_rx_prodring_set *tpr)
5618 {
5619         u32 i, rx_pkt_dma_sz;
5620         struct tg3_napi *tnapi = &tp->napi[0];
5621
5622         /* Zero out all descriptors. */
5623         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5624
5625         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5626         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5627             tp->dev->mtu > ETH_DATA_LEN)
5628                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5629         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5630
5631         /* Initialize invariants of the rings, we only set this
5632          * stuff once.  This works because the card does not
5633          * write into the rx buffer posting rings.
5634          */
5635         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5636                 struct tg3_rx_buffer_desc *rxd;
5637
5638                 rxd = &tpr->rx_std[i];
5639                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5640                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5641                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5642                                (i << RXD_OPAQUE_INDEX_SHIFT));
5643         }
5644
5645         /* Now allocate fresh SKBs for each rx ring. */
5646         for (i = 0; i < tp->rx_pending; i++) {
5647                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5648                         printk(KERN_WARNING PFX
5649                                "%s: Using a smaller RX standard ring, "
5650                                "only %d out of %d buffers were allocated "
5651                                "successfully.\n",
5652                                tp->dev->name, i, tp->rx_pending);
5653                         if (i == 0)
5654                                 goto initfail;
5655                         tp->rx_pending = i;
5656                         break;
5657                 }
5658         }
5659
5660         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5661                 goto done;
5662
5663         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5664
5665         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5666                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5667                         struct tg3_rx_buffer_desc *rxd;
5668
5669                         rxd = &tpr->rx_jmb[i].std;
5670                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5671                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5672                                 RXD_FLAG_JUMBO;
5673                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5674                                (i << RXD_OPAQUE_INDEX_SHIFT));
5675                 }
5676
5677                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5678                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5679                                              -1, i) < 0) {
5680                                 printk(KERN_WARNING PFX
5681                                        "%s: Using a smaller RX jumbo ring, "
5682                                        "only %d out of %d buffers were "
5683                                        "allocated successfully.\n",
5684                                        tp->dev->name, i, tp->rx_jumbo_pending);
5685                                 if (i == 0)
5686                                         goto initfail;
5687                                 tp->rx_jumbo_pending = i;
5688                                 break;
5689                         }
5690                 }
5691         }
5692
5693 done:
5694         return 0;
5695
5696 initfail:
5697         tg3_rx_prodring_free(tp, tpr);
5698         return -ENOMEM;
5699 }
5700
5701 static void tg3_rx_prodring_fini(struct tg3 *tp,
5702                                  struct tg3_rx_prodring_set *tpr)
5703 {
5704         kfree(tpr->rx_std_buffers);
5705         tpr->rx_std_buffers = NULL;
5706         kfree(tpr->rx_jmb_buffers);
5707         tpr->rx_jmb_buffers = NULL;
5708         if (tpr->rx_std) {
5709                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5710                                     tpr->rx_std, tpr->rx_std_mapping);
5711                 tpr->rx_std = NULL;
5712         }
5713         if (tpr->rx_jmb) {
5714                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5715                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5716                 tpr->rx_jmb = NULL;
5717         }
5718 }
5719
5720 static int tg3_rx_prodring_init(struct tg3 *tp,
5721                                 struct tg3_rx_prodring_set *tpr)
5722 {
5723         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5724                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5725         if (!tpr->rx_std_buffers)
5726                 return -ENOMEM;
5727
5728         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5729                                            &tpr->rx_std_mapping);
5730         if (!tpr->rx_std)
5731                 goto err_out;
5732
5733         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5734                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5735                                               TG3_RX_JUMBO_RING_SIZE,
5736                                               GFP_KERNEL);
5737                 if (!tpr->rx_jmb_buffers)
5738                         goto err_out;
5739
5740                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5741                                                    TG3_RX_JUMBO_RING_BYTES,
5742                                                    &tpr->rx_jmb_mapping);
5743                 if (!tpr->rx_jmb)
5744                         goto err_out;
5745         }
5746
5747         return 0;
5748
5749 err_out:
5750         tg3_rx_prodring_fini(tp, tpr);
5751         return -ENOMEM;
5752 }
5753
5754 /* Free up pending packets in all rx/tx rings.
5755  *
5756  * The chip has been shut down and the driver detached from
5757  * the networking, so no interrupts or new tx packets will
5758  * end up in the driver.  tp->{tx,}lock is not held and we are not
5759  * in an interrupt context and thus may sleep.
5760  */
5761 static void tg3_free_rings(struct tg3 *tp)
5762 {
5763         int i, j;
5764
5765         for (j = 0; j < tp->irq_cnt; j++) {
5766                 struct tg3_napi *tnapi = &tp->napi[j];
5767
5768                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5769                         struct tx_ring_info *txp;
5770                         struct sk_buff *skb;
5771
5772                         txp = &tnapi->tx_buffers[i];
5773                         skb = txp->skb;
5774
5775                         if (skb == NULL) {
5776                                 i++;
5777                                 continue;
5778                         }
5779
5780                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5781
5782                         txp->skb = NULL;
5783
5784                         i += skb_shinfo(skb)->nr_frags + 1;
5785
5786                         dev_kfree_skb_any(skb);
5787                 }
5788         }
5789
5790         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5791 }
5792
5793 /* Initialize tx/rx rings for packet processing.
5794  *
5795  * The chip has been shut down and the driver detached from
5796  * the networking, so no interrupts or new tx packets will
5797  * end up in the driver.  tp->{tx,}lock are held and thus
5798  * we may not sleep.
5799  */
5800 static int tg3_init_rings(struct tg3 *tp)
5801 {
5802         int i;
5803
5804         /* Free up all the SKBs. */
5805         tg3_free_rings(tp);
5806
5807         for (i = 0; i < tp->irq_cnt; i++) {
5808                 struct tg3_napi *tnapi = &tp->napi[i];
5809
5810                 tnapi->last_tag = 0;
5811                 tnapi->last_irq_tag = 0;
5812                 tnapi->hw_status->status = 0;
5813                 tnapi->hw_status->status_tag = 0;
5814                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5815
5816                 tnapi->tx_prod = 0;
5817                 tnapi->tx_cons = 0;
5818                 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5819
5820                 tnapi->rx_rcb_ptr = 0;
5821                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5822         }
5823
5824         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5825 }
5826
5827 /*
5828  * Must not be invoked with interrupt sources disabled and
5829  * the hardware shutdown down.
5830  */
5831 static void tg3_free_consistent(struct tg3 *tp)
5832 {
5833         int i;
5834
5835         for (i = 0; i < tp->irq_cnt; i++) {
5836                 struct tg3_napi *tnapi = &tp->napi[i];
5837
5838                 if (tnapi->tx_ring) {
5839                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5840                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5841                         tnapi->tx_ring = NULL;
5842                 }
5843
5844                 kfree(tnapi->tx_buffers);
5845                 tnapi->tx_buffers = NULL;
5846
5847                 if (tnapi->rx_rcb) {
5848                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5849                                             tnapi->rx_rcb,
5850                                             tnapi->rx_rcb_mapping);
5851                         tnapi->rx_rcb = NULL;
5852                 }
5853
5854                 if (tnapi->hw_status) {
5855                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5856                                             tnapi->hw_status,
5857                                             tnapi->status_mapping);
5858                         tnapi->hw_status = NULL;
5859                 }
5860         }
5861
5862         if (tp->hw_stats) {
5863                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5864                                     tp->hw_stats, tp->stats_mapping);
5865                 tp->hw_stats = NULL;
5866         }
5867
5868         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5869 }
5870
5871 /*
5872  * Must not be invoked with interrupt sources disabled and
5873  * the hardware shutdown down.  Can sleep.
5874  */
5875 static int tg3_alloc_consistent(struct tg3 *tp)
5876 {
5877         int i;
5878
5879         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5880                 return -ENOMEM;
5881
5882         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5883                                             sizeof(struct tg3_hw_stats),
5884                                             &tp->stats_mapping);
5885         if (!tp->hw_stats)
5886                 goto err_out;
5887
5888         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5889
5890         for (i = 0; i < tp->irq_cnt; i++) {
5891                 struct tg3_napi *tnapi = &tp->napi[i];
5892
5893                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5894                                                         TG3_HW_STATUS_SIZE,
5895                                                         &tnapi->status_mapping);
5896                 if (!tnapi->hw_status)
5897                         goto err_out;
5898
5899                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5900
5901                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5902                                                      TG3_RX_RCB_RING_BYTES(tp),
5903                                                      &tnapi->rx_rcb_mapping);
5904                 if (!tnapi->rx_rcb)
5905                         goto err_out;
5906
5907                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5908
5909                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5910                                             TG3_TX_RING_SIZE, GFP_KERNEL);
5911                 if (!tnapi->tx_buffers)
5912                         goto err_out;
5913
5914                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
5915                                                       TG3_TX_RING_BYTES,
5916                                                       &tnapi->tx_desc_mapping);
5917                 if (!tnapi->tx_ring)
5918                         goto err_out;
5919         }
5920
5921         return 0;
5922
5923 err_out:
5924         tg3_free_consistent(tp);
5925         return -ENOMEM;
5926 }
5927
5928 #define MAX_WAIT_CNT 1000
5929
5930 /* To stop a block, clear the enable bit and poll till it
5931  * clears.  tp->lock is held.
5932  */
5933 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5934 {
5935         unsigned int i;
5936         u32 val;
5937
5938         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5939                 switch (ofs) {
5940                 case RCVLSC_MODE:
5941                 case DMAC_MODE:
5942                 case MBFREE_MODE:
5943                 case BUFMGR_MODE:
5944                 case MEMARB_MODE:
5945                         /* We can't enable/disable these bits of the
5946                          * 5705/5750, just say success.
5947                          */
5948                         return 0;
5949
5950                 default:
5951                         break;
5952                 }
5953         }
5954
5955         val = tr32(ofs);
5956         val &= ~enable_bit;
5957         tw32_f(ofs, val);
5958
5959         for (i = 0; i < MAX_WAIT_CNT; i++) {
5960                 udelay(100);
5961                 val = tr32(ofs);
5962                 if ((val & enable_bit) == 0)
5963                         break;
5964         }
5965
5966         if (i == MAX_WAIT_CNT && !silent) {
5967                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5968                        "ofs=%lx enable_bit=%x\n",
5969                        ofs, enable_bit);
5970                 return -ENODEV;
5971         }
5972
5973         return 0;
5974 }
5975
5976 /* tp->lock is held. */
5977 static int tg3_abort_hw(struct tg3 *tp, int silent)
5978 {
5979         int i, err;
5980
5981         tg3_disable_ints(tp);
5982
5983         tp->rx_mode &= ~RX_MODE_ENABLE;
5984         tw32_f(MAC_RX_MODE, tp->rx_mode);
5985         udelay(10);
5986
5987         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5988         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5989         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5990         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5991         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5992         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5993
5994         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5995         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5996         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5997         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5998         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5999         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6000         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6001
6002         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6003         tw32_f(MAC_MODE, tp->mac_mode);
6004         udelay(40);
6005
6006         tp->tx_mode &= ~TX_MODE_ENABLE;
6007         tw32_f(MAC_TX_MODE, tp->tx_mode);
6008
6009         for (i = 0; i < MAX_WAIT_CNT; i++) {
6010                 udelay(100);
6011                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6012                         break;
6013         }
6014         if (i >= MAX_WAIT_CNT) {
6015                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6016                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6017                        tp->dev->name, tr32(MAC_TX_MODE));
6018                 err |= -ENODEV;
6019         }
6020
6021         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6022         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6023         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6024
6025         tw32(FTQ_RESET, 0xffffffff);
6026         tw32(FTQ_RESET, 0x00000000);
6027
6028         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6029         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6030
6031         for (i = 0; i < tp->irq_cnt; i++) {
6032                 struct tg3_napi *tnapi = &tp->napi[i];
6033                 if (tnapi->hw_status)
6034                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6035         }
6036         if (tp->hw_stats)
6037                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6038
6039         return err;
6040 }
6041
6042 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6043 {
6044         int i;
6045         u32 apedata;
6046
6047         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6048         if (apedata != APE_SEG_SIG_MAGIC)
6049                 return;
6050
6051         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6052         if (!(apedata & APE_FW_STATUS_READY))
6053                 return;
6054
6055         /* Wait for up to 1 millisecond for APE to service previous event. */
6056         for (i = 0; i < 10; i++) {
6057                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6058                         return;
6059
6060                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6061
6062                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6063                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6064                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6065
6066                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6067
6068                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6069                         break;
6070
6071                 udelay(100);
6072         }
6073
6074         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6075                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6076 }
6077
6078 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6079 {
6080         u32 event;
6081         u32 apedata;
6082
6083         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6084                 return;
6085
6086         switch (kind) {
6087                 case RESET_KIND_INIT:
6088                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6089                                         APE_HOST_SEG_SIG_MAGIC);
6090                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6091                                         APE_HOST_SEG_LEN_MAGIC);
6092                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6093                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6094                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6095                                         APE_HOST_DRIVER_ID_MAGIC);
6096                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6097                                         APE_HOST_BEHAV_NO_PHYLOCK);
6098
6099                         event = APE_EVENT_STATUS_STATE_START;
6100                         break;
6101                 case RESET_KIND_SHUTDOWN:
6102                         /* With the interface we are currently using,
6103                          * APE does not track driver state.  Wiping
6104                          * out the HOST SEGMENT SIGNATURE forces
6105                          * the APE to assume OS absent status.
6106                          */
6107                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6108
6109                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6110                         break;
6111                 case RESET_KIND_SUSPEND:
6112                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6113                         break;
6114                 default:
6115                         return;
6116         }
6117
6118         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6119
6120         tg3_ape_send_event(tp, event);
6121 }
6122
6123 /* tp->lock is held. */
6124 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6125 {
6126         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6127                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6128
6129         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6130                 switch (kind) {
6131                 case RESET_KIND_INIT:
6132                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6133                                       DRV_STATE_START);
6134                         break;
6135
6136                 case RESET_KIND_SHUTDOWN:
6137                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6138                                       DRV_STATE_UNLOAD);
6139                         break;
6140
6141                 case RESET_KIND_SUSPEND:
6142                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6143                                       DRV_STATE_SUSPEND);
6144                         break;
6145
6146                 default:
6147                         break;
6148                 }
6149         }
6150
6151         if (kind == RESET_KIND_INIT ||
6152             kind == RESET_KIND_SUSPEND)
6153                 tg3_ape_driver_state_change(tp, kind);
6154 }
6155
6156 /* tp->lock is held. */
6157 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6158 {
6159         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6160                 switch (kind) {
6161                 case RESET_KIND_INIT:
6162                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6163                                       DRV_STATE_START_DONE);
6164                         break;
6165
6166                 case RESET_KIND_SHUTDOWN:
6167                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6168                                       DRV_STATE_UNLOAD_DONE);
6169                         break;
6170
6171                 default:
6172                         break;
6173                 }
6174         }
6175
6176         if (kind == RESET_KIND_SHUTDOWN)
6177                 tg3_ape_driver_state_change(tp, kind);
6178 }
6179
6180 /* tp->lock is held. */
6181 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6182 {
6183         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6184                 switch (kind) {
6185                 case RESET_KIND_INIT:
6186                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6187                                       DRV_STATE_START);
6188                         break;
6189
6190                 case RESET_KIND_SHUTDOWN:
6191                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6192                                       DRV_STATE_UNLOAD);
6193                         break;
6194
6195                 case RESET_KIND_SUSPEND:
6196                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6197                                       DRV_STATE_SUSPEND);
6198                         break;
6199
6200                 default:
6201                         break;
6202                 }
6203         }
6204 }
6205
6206 static int tg3_poll_fw(struct tg3 *tp)
6207 {
6208         int i;
6209         u32 val;
6210
6211         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6212                 /* Wait up to 20ms for init done. */
6213                 for (i = 0; i < 200; i++) {
6214                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6215                                 return 0;
6216                         udelay(100);
6217                 }
6218                 return -ENODEV;
6219         }
6220
6221         /* Wait for firmware initialization to complete. */
6222         for (i = 0; i < 100000; i++) {
6223                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6224                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6225                         break;
6226                 udelay(10);
6227         }
6228
6229         /* Chip might not be fitted with firmware.  Some Sun onboard
6230          * parts are configured like that.  So don't signal the timeout
6231          * of the above loop as an error, but do report the lack of
6232          * running firmware once.
6233          */
6234         if (i >= 100000 &&
6235             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6236                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6237
6238                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6239                        tp->dev->name);
6240         }
6241
6242         return 0;
6243 }
6244
6245 /* Save PCI command register before chip reset */
6246 static void tg3_save_pci_state(struct tg3 *tp)
6247 {
6248         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6249 }
6250
6251 /* Restore PCI state after chip reset */
6252 static void tg3_restore_pci_state(struct tg3 *tp)
6253 {
6254         u32 val;
6255
6256         /* Re-enable indirect register accesses. */
6257         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6258                                tp->misc_host_ctrl);
6259
6260         /* Set MAX PCI retry to zero. */
6261         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6262         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6263             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6264                 val |= PCISTATE_RETRY_SAME_DMA;
6265         /* Allow reads and writes to the APE register and memory space. */
6266         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6267                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6268                        PCISTATE_ALLOW_APE_SHMEM_WR;
6269         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6270
6271         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6272
6273         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6274                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6275                         pcie_set_readrq(tp->pdev, 4096);
6276                 else {
6277                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6278                                               tp->pci_cacheline_sz);
6279                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6280                                               tp->pci_lat_timer);
6281                 }
6282         }
6283
6284         /* Make sure PCI-X relaxed ordering bit is clear. */
6285         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6286                 u16 pcix_cmd;
6287
6288                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6289                                      &pcix_cmd);
6290                 pcix_cmd &= ~PCI_X_CMD_ERO;
6291                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6292                                       pcix_cmd);
6293         }
6294
6295         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6296
6297                 /* Chip reset on 5780 will reset MSI enable bit,
6298                  * so need to restore it.
6299                  */
6300                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6301                         u16 ctrl;
6302
6303                         pci_read_config_word(tp->pdev,
6304                                              tp->msi_cap + PCI_MSI_FLAGS,
6305                                              &ctrl);
6306                         pci_write_config_word(tp->pdev,
6307                                               tp->msi_cap + PCI_MSI_FLAGS,
6308                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6309                         val = tr32(MSGINT_MODE);
6310                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6311                 }
6312         }
6313 }
6314
6315 static void tg3_stop_fw(struct tg3 *);
6316
6317 /* tp->lock is held. */
6318 static int tg3_chip_reset(struct tg3 *tp)
6319 {
6320         u32 val;
6321         void (*write_op)(struct tg3 *, u32, u32);
6322         int i, err;
6323
6324         tg3_nvram_lock(tp);
6325
6326         tg3_mdio_stop(tp);
6327
6328         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6329
6330         /* No matching tg3_nvram_unlock() after this because
6331          * chip reset below will undo the nvram lock.
6332          */
6333         tp->nvram_lock_cnt = 0;
6334
6335         /* GRC_MISC_CFG core clock reset will clear the memory
6336          * enable bit in PCI register 4 and the MSI enable bit
6337          * on some chips, so we save relevant registers here.
6338          */
6339         tg3_save_pci_state(tp);
6340
6341         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6342             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6343                 tw32(GRC_FASTBOOT_PC, 0);
6344
6345         /*
6346          * We must avoid the readl() that normally takes place.
6347          * It locks machines, causes machine checks, and other
6348          * fun things.  So, temporarily disable the 5701
6349          * hardware workaround, while we do the reset.
6350          */
6351         write_op = tp->write32;
6352         if (write_op == tg3_write_flush_reg32)
6353                 tp->write32 = tg3_write32;
6354
6355         /* Prevent the irq handler from reading or writing PCI registers
6356          * during chip reset when the memory enable bit in the PCI command
6357          * register may be cleared.  The chip does not generate interrupt
6358          * at this time, but the irq handler may still be called due to irq
6359          * sharing or irqpoll.
6360          */
6361         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6362         for (i = 0; i < tp->irq_cnt; i++) {
6363                 struct tg3_napi *tnapi = &tp->napi[i];
6364                 if (tnapi->hw_status) {
6365                         tnapi->hw_status->status = 0;
6366                         tnapi->hw_status->status_tag = 0;
6367                 }
6368                 tnapi->last_tag = 0;
6369                 tnapi->last_irq_tag = 0;
6370         }
6371         smp_mb();
6372
6373         for (i = 0; i < tp->irq_cnt; i++)
6374                 synchronize_irq(tp->napi[i].irq_vec);
6375
6376         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6377                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6378                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6379         }
6380
6381         /* do the reset */
6382         val = GRC_MISC_CFG_CORECLK_RESET;
6383
6384         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6385                 if (tr32(0x7e2c) == 0x60) {
6386                         tw32(0x7e2c, 0x20);
6387                 }
6388                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6389                         tw32(GRC_MISC_CFG, (1 << 29));
6390                         val |= (1 << 29);
6391                 }
6392         }
6393
6394         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6395                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6396                 tw32(GRC_VCPU_EXT_CTRL,
6397                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6398         }
6399
6400         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6401                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6402         tw32(GRC_MISC_CFG, val);
6403
6404         /* restore 5701 hardware bug workaround write method */
6405         tp->write32 = write_op;
6406
6407         /* Unfortunately, we have to delay before the PCI read back.
6408          * Some 575X chips even will not respond to a PCI cfg access
6409          * when the reset command is given to the chip.
6410          *
6411          * How do these hardware designers expect things to work
6412          * properly if the PCI write is posted for a long period
6413          * of time?  It is always necessary to have some method by
6414          * which a register read back can occur to push the write
6415          * out which does the reset.
6416          *
6417          * For most tg3 variants the trick below was working.
6418          * Ho hum...
6419          */
6420         udelay(120);
6421
6422         /* Flush PCI posted writes.  The normal MMIO registers
6423          * are inaccessible at this time so this is the only
6424          * way to make this reliably (actually, this is no longer
6425          * the case, see above).  I tried to use indirect
6426          * register read/write but this upset some 5701 variants.
6427          */
6428         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6429
6430         udelay(120);
6431
6432         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6433                 u16 val16;
6434
6435                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6436                         int i;
6437                         u32 cfg_val;
6438
6439                         /* Wait for link training to complete.  */
6440                         for (i = 0; i < 5000; i++)
6441                                 udelay(100);
6442
6443                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6444                         pci_write_config_dword(tp->pdev, 0xc4,
6445                                                cfg_val | (1 << 15));
6446                 }
6447
6448                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6449                 pci_read_config_word(tp->pdev,
6450                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6451                                      &val16);
6452                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6453                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6454                 /*
6455                  * Older PCIe devices only support the 128 byte
6456                  * MPS setting.  Enforce the restriction.
6457                  */
6458                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6459                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6460                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6461                 pci_write_config_word(tp->pdev,
6462                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6463                                       val16);
6464
6465                 pcie_set_readrq(tp->pdev, 4096);
6466
6467                 /* Clear error status */
6468                 pci_write_config_word(tp->pdev,
6469                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6470                                       PCI_EXP_DEVSTA_CED |
6471                                       PCI_EXP_DEVSTA_NFED |
6472                                       PCI_EXP_DEVSTA_FED |
6473                                       PCI_EXP_DEVSTA_URD);
6474         }
6475
6476         tg3_restore_pci_state(tp);
6477
6478         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6479
6480         val = 0;
6481         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6482                 val = tr32(MEMARB_MODE);
6483         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6484
6485         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6486                 tg3_stop_fw(tp);
6487                 tw32(0x5000, 0x400);
6488         }
6489
6490         tw32(GRC_MODE, tp->grc_mode);
6491
6492         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6493                 val = tr32(0xc4);
6494
6495                 tw32(0xc4, val | (1 << 15));
6496         }
6497
6498         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6499             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6500                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6501                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6502                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6503                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6504         }
6505
6506         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6507                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6508                 tw32_f(MAC_MODE, tp->mac_mode);
6509         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6510                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6511                 tw32_f(MAC_MODE, tp->mac_mode);
6512         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6513                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6514                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6515                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6516                 tw32_f(MAC_MODE, tp->mac_mode);
6517         } else
6518                 tw32_f(MAC_MODE, 0);
6519         udelay(40);
6520
6521         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6522
6523         err = tg3_poll_fw(tp);
6524         if (err)
6525                 return err;
6526
6527         tg3_mdio_start(tp);
6528
6529         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6530             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6531                 val = tr32(0x7c00);
6532
6533                 tw32(0x7c00, val | (1 << 25));
6534         }
6535
6536         /* Reprobe ASF enable state.  */
6537         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6538         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6539         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6540         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6541                 u32 nic_cfg;
6542
6543                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6544                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6545                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6546                         tp->last_event_jiffies = jiffies;
6547                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6548                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6549                 }
6550         }
6551
6552         return 0;
6553 }
6554
6555 /* tp->lock is held. */
6556 static void tg3_stop_fw(struct tg3 *tp)
6557 {
6558         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6559            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6560                 /* Wait for RX cpu to ACK the previous event. */
6561                 tg3_wait_for_event_ack(tp);
6562
6563                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6564
6565                 tg3_generate_fw_event(tp);
6566
6567                 /* Wait for RX cpu to ACK this event. */
6568                 tg3_wait_for_event_ack(tp);
6569         }
6570 }
6571
6572 /* tp->lock is held. */
6573 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6574 {
6575         int err;
6576
6577         tg3_stop_fw(tp);
6578
6579         tg3_write_sig_pre_reset(tp, kind);
6580
6581         tg3_abort_hw(tp, silent);
6582         err = tg3_chip_reset(tp);
6583
6584         __tg3_set_mac_addr(tp, 0);
6585
6586         tg3_write_sig_legacy(tp, kind);
6587         tg3_write_sig_post_reset(tp, kind);
6588
6589         if (err)
6590                 return err;
6591
6592         return 0;
6593 }
6594
6595 #define RX_CPU_SCRATCH_BASE     0x30000
6596 #define RX_CPU_SCRATCH_SIZE     0x04000
6597 #define TX_CPU_SCRATCH_BASE     0x34000
6598 #define TX_CPU_SCRATCH_SIZE     0x04000
6599
6600 /* tp->lock is held. */
6601 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6602 {
6603         int i;
6604
6605         BUG_ON(offset == TX_CPU_BASE &&
6606             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6607
6608         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6609                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6610
6611                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6612                 return 0;
6613         }
6614         if (offset == RX_CPU_BASE) {
6615                 for (i = 0; i < 10000; i++) {
6616                         tw32(offset + CPU_STATE, 0xffffffff);
6617                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6618                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6619                                 break;
6620                 }
6621
6622                 tw32(offset + CPU_STATE, 0xffffffff);
6623                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6624                 udelay(10);
6625         } else {
6626                 for (i = 0; i < 10000; i++) {
6627                         tw32(offset + CPU_STATE, 0xffffffff);
6628                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6629                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6630                                 break;
6631                 }
6632         }
6633
6634         if (i >= 10000) {
6635                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6636                        "and %s CPU\n",
6637                        tp->dev->name,
6638                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6639                 return -ENODEV;
6640         }
6641
6642         /* Clear firmware's nvram arbitration. */
6643         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6644                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6645         return 0;
6646 }
6647
6648 struct fw_info {
6649         unsigned int fw_base;
6650         unsigned int fw_len;
6651         const __be32 *fw_data;
6652 };
6653
6654 /* tp->lock is held. */
6655 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6656                                  int cpu_scratch_size, struct fw_info *info)
6657 {
6658         int err, lock_err, i;
6659         void (*write_op)(struct tg3 *, u32, u32);
6660
6661         if (cpu_base == TX_CPU_BASE &&
6662             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6663                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6664                        "TX cpu firmware on %s which is 5705.\n",
6665                        tp->dev->name);
6666                 return -EINVAL;
6667         }
6668
6669         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6670                 write_op = tg3_write_mem;
6671         else
6672                 write_op = tg3_write_indirect_reg32;
6673
6674         /* It is possible that bootcode is still loading at this point.
6675          * Get the nvram lock first before halting the cpu.
6676          */
6677         lock_err = tg3_nvram_lock(tp);
6678         err = tg3_halt_cpu(tp, cpu_base);
6679         if (!lock_err)
6680                 tg3_nvram_unlock(tp);
6681         if (err)
6682                 goto out;
6683
6684         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6685                 write_op(tp, cpu_scratch_base + i, 0);
6686         tw32(cpu_base + CPU_STATE, 0xffffffff);
6687         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6688         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6689                 write_op(tp, (cpu_scratch_base +
6690                               (info->fw_base & 0xffff) +
6691                               (i * sizeof(u32))),
6692                               be32_to_cpu(info->fw_data[i]));
6693
6694         err = 0;
6695
6696 out:
6697         return err;
6698 }
6699
6700 /* tp->lock is held. */
6701 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6702 {
6703         struct fw_info info;
6704         const __be32 *fw_data;
6705         int err, i;
6706
6707         fw_data = (void *)tp->fw->data;
6708
6709         /* Firmware blob starts with version numbers, followed by
6710            start address and length. We are setting complete length.
6711            length = end_address_of_bss - start_address_of_text.
6712            Remainder is the blob to be loaded contiguously
6713            from start address. */
6714
6715         info.fw_base = be32_to_cpu(fw_data[1]);
6716         info.fw_len = tp->fw->size - 12;
6717         info.fw_data = &fw_data[3];
6718
6719         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6720                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6721                                     &info);
6722         if (err)
6723                 return err;
6724
6725         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6726                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6727                                     &info);
6728         if (err)
6729                 return err;
6730
6731         /* Now startup only the RX cpu. */
6732         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6733         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6734
6735         for (i = 0; i < 5; i++) {
6736                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6737                         break;
6738                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6739                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6740                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6741                 udelay(1000);
6742         }
6743         if (i >= 5) {
6744                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6745                        "to set RX CPU PC, is %08x should be %08x\n",
6746                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6747                        info.fw_base);
6748                 return -ENODEV;
6749         }
6750         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6751         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6752
6753         return 0;
6754 }
6755
6756 /* 5705 needs a special version of the TSO firmware.  */
6757
6758 /* tp->lock is held. */
6759 static int tg3_load_tso_firmware(struct tg3 *tp)
6760 {
6761         struct fw_info info;
6762         const __be32 *fw_data;
6763         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6764         int err, i;
6765
6766         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6767                 return 0;
6768
6769         fw_data = (void *)tp->fw->data;
6770
6771         /* Firmware blob starts with version numbers, followed by
6772            start address and length. We are setting complete length.
6773            length = end_address_of_bss - start_address_of_text.
6774            Remainder is the blob to be loaded contiguously
6775            from start address. */
6776
6777         info.fw_base = be32_to_cpu(fw_data[1]);
6778         cpu_scratch_size = tp->fw_len;
6779         info.fw_len = tp->fw->size - 12;
6780         info.fw_data = &fw_data[3];
6781
6782         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6783                 cpu_base = RX_CPU_BASE;
6784                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6785         } else {
6786                 cpu_base = TX_CPU_BASE;
6787                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6788                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6789         }
6790
6791         err = tg3_load_firmware_cpu(tp, cpu_base,
6792                                     cpu_scratch_base, cpu_scratch_size,
6793                                     &info);
6794         if (err)
6795                 return err;
6796
6797         /* Now startup the cpu. */
6798         tw32(cpu_base + CPU_STATE, 0xffffffff);
6799         tw32_f(cpu_base + CPU_PC, info.fw_base);
6800
6801         for (i = 0; i < 5; i++) {
6802                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6803                         break;
6804                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6805                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6806                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6807                 udelay(1000);
6808         }
6809         if (i >= 5) {
6810                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6811                        "to set CPU PC, is %08x should be %08x\n",
6812                        tp->dev->name, tr32(cpu_base + CPU_PC),
6813                        info.fw_base);
6814                 return -ENODEV;
6815         }
6816         tw32(cpu_base + CPU_STATE, 0xffffffff);
6817         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6818         return 0;
6819 }
6820
6821
6822 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6823 {
6824         struct tg3 *tp = netdev_priv(dev);
6825         struct sockaddr *addr = p;
6826         int err = 0, skip_mac_1 = 0;
6827
6828         if (!is_valid_ether_addr(addr->sa_data))
6829                 return -EINVAL;
6830
6831         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6832
6833         if (!netif_running(dev))
6834                 return 0;
6835
6836         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6837                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6838
6839                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6840                 addr0_low = tr32(MAC_ADDR_0_LOW);
6841                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6842                 addr1_low = tr32(MAC_ADDR_1_LOW);
6843
6844                 /* Skip MAC addr 1 if ASF is using it. */
6845                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6846                     !(addr1_high == 0 && addr1_low == 0))
6847                         skip_mac_1 = 1;
6848         }
6849         spin_lock_bh(&tp->lock);
6850         __tg3_set_mac_addr(tp, skip_mac_1);
6851         spin_unlock_bh(&tp->lock);
6852
6853         return err;
6854 }
6855
6856 /* tp->lock is held. */
6857 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6858                            dma_addr_t mapping, u32 maxlen_flags,
6859                            u32 nic_addr)
6860 {
6861         tg3_write_mem(tp,
6862                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6863                       ((u64) mapping >> 32));
6864         tg3_write_mem(tp,
6865                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6866                       ((u64) mapping & 0xffffffff));
6867         tg3_write_mem(tp,
6868                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6869                        maxlen_flags);
6870
6871         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6872                 tg3_write_mem(tp,
6873                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6874                               nic_addr);
6875 }
6876
6877 static void __tg3_set_rx_mode(struct net_device *);
6878 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6879 {
6880         int i;
6881
6882         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
6883                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6884                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6885                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6886
6887                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6888                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6889                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6890         } else {
6891                 tw32(HOSTCC_TXCOL_TICKS, 0);
6892                 tw32(HOSTCC_TXMAX_FRAMES, 0);
6893                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
6894
6895                 tw32(HOSTCC_RXCOL_TICKS, 0);
6896                 tw32(HOSTCC_RXMAX_FRAMES, 0);
6897                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
6898         }
6899
6900         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6901                 u32 val = ec->stats_block_coalesce_usecs;
6902
6903                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6904                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6905
6906                 if (!netif_carrier_ok(tp->dev))
6907                         val = 0;
6908
6909                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6910         }
6911
6912         for (i = 0; i < tp->irq_cnt - 1; i++) {
6913                 u32 reg;
6914
6915                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
6916                 tw32(reg, ec->rx_coalesce_usecs);
6917                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
6918                 tw32(reg, ec->tx_coalesce_usecs);
6919                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
6920                 tw32(reg, ec->rx_max_coalesced_frames);
6921                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
6922                 tw32(reg, ec->tx_max_coalesced_frames);
6923                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
6924                 tw32(reg, ec->rx_max_coalesced_frames_irq);
6925                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
6926                 tw32(reg, ec->tx_max_coalesced_frames_irq);
6927         }
6928
6929         for (; i < tp->irq_max - 1; i++) {
6930                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
6931                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
6932                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
6933                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
6934                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
6935                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
6936         }
6937 }
6938
6939 /* tp->lock is held. */
6940 static void tg3_rings_reset(struct tg3 *tp)
6941 {
6942         int i;
6943         u32 stblk, txrcb, rxrcb, limit;
6944         struct tg3_napi *tnapi = &tp->napi[0];
6945
6946         /* Disable all transmit rings but the first. */
6947         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6948                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
6949         else
6950                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6951
6952         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6953              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
6954                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
6955                               BDINFO_FLAGS_DISABLED);
6956
6957
6958         /* Disable all receive return rings but the first. */
6959         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6960                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
6961         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6962                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
6963         else
6964                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6965
6966         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6967              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
6968                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
6969                               BDINFO_FLAGS_DISABLED);
6970
6971         /* Disable interrupts */
6972         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
6973
6974         /* Zero mailbox registers. */
6975         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
6976                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
6977                         tp->napi[i].tx_prod = 0;
6978                         tp->napi[i].tx_cons = 0;
6979                         tw32_mailbox(tp->napi[i].prodmbox, 0);
6980                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
6981                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
6982                 }
6983         } else {
6984                 tp->napi[0].tx_prod = 0;
6985                 tp->napi[0].tx_cons = 0;
6986                 tw32_mailbox(tp->napi[0].prodmbox, 0);
6987                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
6988         }
6989
6990         /* Make sure the NIC-based send BD rings are disabled. */
6991         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6992                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6993                 for (i = 0; i < 16; i++)
6994                         tw32_tx_mbox(mbox + i * 8, 0);
6995         }
6996
6997         txrcb = NIC_SRAM_SEND_RCB;
6998         rxrcb = NIC_SRAM_RCV_RET_RCB;
6999
7000         /* Clear status block in ram. */
7001         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7002
7003         /* Set status block DMA address */
7004         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7005              ((u64) tnapi->status_mapping >> 32));
7006         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7007              ((u64) tnapi->status_mapping & 0xffffffff));
7008
7009         if (tnapi->tx_ring) {
7010                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7011                                (TG3_TX_RING_SIZE <<
7012                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7013                                NIC_SRAM_TX_BUFFER_DESC);
7014                 txrcb += TG3_BDINFO_SIZE;
7015         }
7016
7017         if (tnapi->rx_rcb) {
7018                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7019                                (TG3_RX_RCB_RING_SIZE(tp) <<
7020                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7021                 rxrcb += TG3_BDINFO_SIZE;
7022         }
7023
7024         stblk = HOSTCC_STATBLCK_RING1;
7025
7026         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7027                 u64 mapping = (u64)tnapi->status_mapping;
7028                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7029                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7030
7031                 /* Clear status block in ram. */
7032                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7033
7034                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7035                                (TG3_TX_RING_SIZE <<
7036                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7037                                NIC_SRAM_TX_BUFFER_DESC);
7038
7039                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7040                                (TG3_RX_RCB_RING_SIZE(tp) <<
7041                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7042
7043                 stblk += 8;
7044                 txrcb += TG3_BDINFO_SIZE;
7045                 rxrcb += TG3_BDINFO_SIZE;
7046         }
7047 }
7048
7049 /* tp->lock is held. */
7050 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7051 {
7052         u32 val, rdmac_mode;
7053         int i, err, limit;
7054         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7055
7056         tg3_disable_ints(tp);
7057
7058         tg3_stop_fw(tp);
7059
7060         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7061
7062         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7063                 tg3_abort_hw(tp, 1);
7064         }
7065
7066         if (reset_phy &&
7067             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7068                 tg3_phy_reset(tp);
7069
7070         err = tg3_chip_reset(tp);
7071         if (err)
7072                 return err;
7073
7074         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7075
7076         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7077                 val = tr32(TG3_CPMU_CTRL);
7078                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7079                 tw32(TG3_CPMU_CTRL, val);
7080
7081                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7082                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7083                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7084                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7085
7086                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7087                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7088                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7089                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7090
7091                 val = tr32(TG3_CPMU_HST_ACC);
7092                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7093                 val |= CPMU_HST_ACC_MACCLK_6_25;
7094                 tw32(TG3_CPMU_HST_ACC, val);
7095         }
7096
7097         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7098                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7099                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7100                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7101                 tw32(PCIE_PWR_MGMT_THRESH, val);
7102
7103                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7104                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7105
7106                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7107         }
7108
7109         if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
7110                 val = tr32(TG3_PCIE_LNKCTL);
7111                 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
7112                         val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7113                 else
7114                         val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7115                 tw32(TG3_PCIE_LNKCTL, val);
7116         }
7117
7118         /* This works around an issue with Athlon chipsets on
7119          * B3 tigon3 silicon.  This bit has no effect on any
7120          * other revision.  But do not set this on PCI Express
7121          * chips and don't even touch the clocks if the CPMU is present.
7122          */
7123         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7124                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7125                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7126                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7127         }
7128
7129         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7130             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7131                 val = tr32(TG3PCI_PCISTATE);
7132                 val |= PCISTATE_RETRY_SAME_DMA;
7133                 tw32(TG3PCI_PCISTATE, val);
7134         }
7135
7136         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7137                 /* Allow reads and writes to the
7138                  * APE register and memory space.
7139                  */
7140                 val = tr32(TG3PCI_PCISTATE);
7141                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7142                        PCISTATE_ALLOW_APE_SHMEM_WR;
7143                 tw32(TG3PCI_PCISTATE, val);
7144         }
7145
7146         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7147                 /* Enable some hw fixes.  */
7148                 val = tr32(TG3PCI_MSI_DATA);
7149                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7150                 tw32(TG3PCI_MSI_DATA, val);
7151         }
7152
7153         /* Descriptor ring init may make accesses to the
7154          * NIC SRAM area to setup the TX descriptors, so we
7155          * can only do this after the hardware has been
7156          * successfully reset.
7157          */
7158         err = tg3_init_rings(tp);
7159         if (err)
7160                 return err;
7161
7162         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7163             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7164                 /* This value is determined during the probe time DMA
7165                  * engine test, tg3_test_dma.
7166                  */
7167                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7168         }
7169
7170         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7171                           GRC_MODE_4X_NIC_SEND_RINGS |
7172                           GRC_MODE_NO_TX_PHDR_CSUM |
7173                           GRC_MODE_NO_RX_PHDR_CSUM);
7174         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7175
7176         /* Pseudo-header checksum is done by hardware logic and not
7177          * the offload processers, so make the chip do the pseudo-
7178          * header checksums on receive.  For transmit it is more
7179          * convenient to do the pseudo-header checksum in software
7180          * as Linux does that on transmit for us in all cases.
7181          */
7182         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7183
7184         tw32(GRC_MODE,
7185              tp->grc_mode |
7186              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7187
7188         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7189         val = tr32(GRC_MISC_CFG);
7190         val &= ~0xff;
7191         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7192         tw32(GRC_MISC_CFG, val);
7193
7194         /* Initialize MBUF/DESC pool. */
7195         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7196                 /* Do nothing.  */
7197         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7198                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7199                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7200                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7201                 else
7202                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7203                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7204                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7205         }
7206         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7207                 int fw_len;
7208
7209                 fw_len = tp->fw_len;
7210                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7211                 tw32(BUFMGR_MB_POOL_ADDR,
7212                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7213                 tw32(BUFMGR_MB_POOL_SIZE,
7214                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7215         }
7216
7217         if (tp->dev->mtu <= ETH_DATA_LEN) {
7218                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7219                      tp->bufmgr_config.mbuf_read_dma_low_water);
7220                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7221                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7222                 tw32(BUFMGR_MB_HIGH_WATER,
7223                      tp->bufmgr_config.mbuf_high_water);
7224         } else {
7225                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7226                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7227                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7228                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7229                 tw32(BUFMGR_MB_HIGH_WATER,
7230                      tp->bufmgr_config.mbuf_high_water_jumbo);
7231         }
7232         tw32(BUFMGR_DMA_LOW_WATER,
7233              tp->bufmgr_config.dma_low_water);
7234         tw32(BUFMGR_DMA_HIGH_WATER,
7235              tp->bufmgr_config.dma_high_water);
7236
7237         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7238         for (i = 0; i < 2000; i++) {
7239                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7240                         break;
7241                 udelay(10);
7242         }
7243         if (i >= 2000) {
7244                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7245                        tp->dev->name);
7246                 return -ENODEV;
7247         }
7248
7249         /* Setup replenish threshold. */
7250         val = tp->rx_pending / 8;
7251         if (val == 0)
7252                 val = 1;
7253         else if (val > tp->rx_std_max_post)
7254                 val = tp->rx_std_max_post;
7255         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7256                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7257                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7258
7259                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7260                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7261         }
7262
7263         tw32(RCVBDI_STD_THRESH, val);
7264
7265         /* Initialize TG3_BDINFO's at:
7266          *  RCVDBDI_STD_BD:     standard eth size rx ring
7267          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7268          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7269          *
7270          * like so:
7271          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7272          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7273          *                              ring attribute flags
7274          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7275          *
7276          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7277          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7278          *
7279          * The size of each ring is fixed in the firmware, but the location is
7280          * configurable.
7281          */
7282         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7283              ((u64) tpr->rx_std_mapping >> 32));
7284         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7285              ((u64) tpr->rx_std_mapping & 0xffffffff));
7286         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7287              NIC_SRAM_RX_BUFFER_DESC);
7288
7289         /* Disable the mini ring */
7290         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7291                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7292                      BDINFO_FLAGS_DISABLED);
7293
7294         /* Program the jumbo buffer descriptor ring control
7295          * blocks on those devices that have them.
7296          */
7297         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7298             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7299                 /* Setup replenish threshold. */
7300                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7301
7302                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7303                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7304                              ((u64) tpr->rx_jmb_mapping >> 32));
7305                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7306                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7307                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7308                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7309                              BDINFO_FLAGS_USE_EXT_RECV);
7310                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7311                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7312                 } else {
7313                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7314                              BDINFO_FLAGS_DISABLED);
7315                 }
7316
7317                 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7318         } else
7319                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7320
7321         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7322
7323         tpr->rx_std_ptr = tp->rx_pending;
7324         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7325                      tpr->rx_std_ptr);
7326
7327         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7328                           tp->rx_jumbo_pending : 0;
7329         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7330                      tpr->rx_jmb_ptr);
7331
7332         tg3_rings_reset(tp);
7333
7334         /* Initialize MAC address and backoff seed. */
7335         __tg3_set_mac_addr(tp, 0);
7336
7337         /* MTU + ethernet header + FCS + optional VLAN tag */
7338         tw32(MAC_RX_MTU_SIZE,
7339              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7340
7341         /* The slot time is changed by tg3_setup_phy if we
7342          * run at gigabit with half duplex.
7343          */
7344         tw32(MAC_TX_LENGTHS,
7345              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7346              (6 << TX_LENGTHS_IPG_SHIFT) |
7347              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7348
7349         /* Receive rules. */
7350         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7351         tw32(RCVLPC_CONFIG, 0x0181);
7352
7353         /* Calculate RDMAC_MODE setting early, we need it to determine
7354          * the RCVLPC_STATE_ENABLE mask.
7355          */
7356         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7357                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7358                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7359                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7360                       RDMAC_MODE_LNGREAD_ENAB);
7361
7362         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7363             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7364             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7365                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7366                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7367                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7368
7369         /* If statement applies to 5705 and 5750 PCI devices only */
7370         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7371              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7372             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7373                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7374                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7375                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7376                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7377                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7378                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7379                 }
7380         }
7381
7382         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7383                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7384
7385         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7386                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7387
7388         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7389             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7390                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7391
7392         /* Receive/send statistics. */
7393         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7394                 val = tr32(RCVLPC_STATS_ENABLE);
7395                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7396                 tw32(RCVLPC_STATS_ENABLE, val);
7397         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7398                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7399                 val = tr32(RCVLPC_STATS_ENABLE);
7400                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7401                 tw32(RCVLPC_STATS_ENABLE, val);
7402         } else {
7403                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7404         }
7405         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7406         tw32(SNDDATAI_STATSENAB, 0xffffff);
7407         tw32(SNDDATAI_STATSCTRL,
7408              (SNDDATAI_SCTRL_ENABLE |
7409               SNDDATAI_SCTRL_FASTUPD));
7410
7411         /* Setup host coalescing engine. */
7412         tw32(HOSTCC_MODE, 0);
7413         for (i = 0; i < 2000; i++) {
7414                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7415                         break;
7416                 udelay(10);
7417         }
7418
7419         __tg3_set_coalesce(tp, &tp->coal);
7420
7421         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7422                 /* Status/statistics block address.  See tg3_timer,
7423                  * the tg3_periodic_fetch_stats call there, and
7424                  * tg3_get_stats to see how this works for 5705/5750 chips.
7425                  */
7426                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7427                      ((u64) tp->stats_mapping >> 32));
7428                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7429                      ((u64) tp->stats_mapping & 0xffffffff));
7430                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7431
7432                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7433
7434                 /* Clear statistics and status block memory areas */
7435                 for (i = NIC_SRAM_STATS_BLK;
7436                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7437                      i += sizeof(u32)) {
7438                         tg3_write_mem(tp, i, 0);
7439                         udelay(40);
7440                 }
7441         }
7442
7443         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7444
7445         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7446         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7447         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7448                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7449
7450         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7451                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7452                 /* reset to prevent losing 1st rx packet intermittently */
7453                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7454                 udelay(10);
7455         }
7456
7457         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7458                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7459         else
7460                 tp->mac_mode = 0;
7461         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7462                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7463         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7464             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7465             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7466                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7467         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7468         udelay(40);
7469
7470         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7471          * If TG3_FLG2_IS_NIC is zero, we should read the
7472          * register to preserve the GPIO settings for LOMs. The GPIOs,
7473          * whether used as inputs or outputs, are set by boot code after
7474          * reset.
7475          */
7476         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7477                 u32 gpio_mask;
7478
7479                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7480                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7481                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7482
7483                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7484                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7485                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7486
7487                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7488                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7489
7490                 tp->grc_local_ctrl &= ~gpio_mask;
7491                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7492
7493                 /* GPIO1 must be driven high for eeprom write protect */
7494                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7495                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7496                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7497         }
7498         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7499         udelay(100);
7500
7501         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7502                 val = tr32(MSGINT_MODE);
7503                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7504                 tw32(MSGINT_MODE, val);
7505         }
7506
7507         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7508                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7509                 udelay(40);
7510         }
7511
7512         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7513                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7514                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7515                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7516                WDMAC_MODE_LNGREAD_ENAB);
7517
7518         /* If statement applies to 5705 and 5750 PCI devices only */
7519         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7520              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7521             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7522                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7523                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7524                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7525                         /* nothing */
7526                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7527                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7528                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7529                         val |= WDMAC_MODE_RX_ACCEL;
7530                 }
7531         }
7532
7533         /* Enable host coalescing bug fix */
7534         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7535                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7536
7537         tw32_f(WDMAC_MODE, val);
7538         udelay(40);
7539
7540         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7541                 u16 pcix_cmd;
7542
7543                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7544                                      &pcix_cmd);
7545                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7546                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7547                         pcix_cmd |= PCI_X_CMD_READ_2K;
7548                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7549                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7550                         pcix_cmd |= PCI_X_CMD_READ_2K;
7551                 }
7552                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7553                                       pcix_cmd);
7554         }
7555
7556         tw32_f(RDMAC_MODE, rdmac_mode);
7557         udelay(40);
7558
7559         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7560         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7561                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7562
7563         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7564                 tw32(SNDDATAC_MODE,
7565                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7566         else
7567                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7568
7569         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7570         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7571         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7572         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7573         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7574                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7575         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7576         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7577                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7578         tw32(SNDBDI_MODE, val);
7579         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7580
7581         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7582                 err = tg3_load_5701_a0_firmware_fix(tp);
7583                 if (err)
7584                         return err;
7585         }
7586
7587         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7588                 err = tg3_load_tso_firmware(tp);
7589                 if (err)
7590                         return err;
7591         }
7592
7593         tp->tx_mode = TX_MODE_ENABLE;
7594         tw32_f(MAC_TX_MODE, tp->tx_mode);
7595         udelay(100);
7596
7597         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7598                 u32 reg = MAC_RSS_INDIR_TBL_0;
7599                 u8 *ent = (u8 *)&val;
7600
7601                 /* Setup the indirection table */
7602                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7603                         int idx = i % sizeof(val);
7604
7605                         ent[idx] = i % (tp->irq_cnt - 1);
7606                         if (idx == sizeof(val) - 1) {
7607                                 tw32(reg, val);
7608                                 reg += 4;
7609                         }
7610                 }
7611
7612                 /* Setup the "secret" hash key. */
7613                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7614                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7615                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7616                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7617                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7618                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7619                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7620                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7621                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7622                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7623         }
7624
7625         tp->rx_mode = RX_MODE_ENABLE;
7626         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7627                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7628
7629         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7630                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7631                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7632                                RX_MODE_RSS_IPV6_HASH_EN |
7633                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7634                                RX_MODE_RSS_IPV4_HASH_EN |
7635                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7636
7637         tw32_f(MAC_RX_MODE, tp->rx_mode);
7638         udelay(10);
7639
7640         tw32(MAC_LED_CTRL, tp->led_ctrl);
7641
7642         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7643         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7644                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7645                 udelay(10);
7646         }
7647         tw32_f(MAC_RX_MODE, tp->rx_mode);
7648         udelay(10);
7649
7650         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7651                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7652                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7653                         /* Set drive transmission level to 1.2V  */
7654                         /* only if the signal pre-emphasis bit is not set  */
7655                         val = tr32(MAC_SERDES_CFG);
7656                         val &= 0xfffff000;
7657                         val |= 0x880;
7658                         tw32(MAC_SERDES_CFG, val);
7659                 }
7660                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7661                         tw32(MAC_SERDES_CFG, 0x616000);
7662         }
7663
7664         /* Prevent chip from dropping frames when flow control
7665          * is enabled.
7666          */
7667         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7668
7669         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7670             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7671                 /* Use hardware link auto-negotiation */
7672                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7673         }
7674
7675         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7676             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7677                 u32 tmp;
7678
7679                 tmp = tr32(SERDES_RX_CTRL);
7680                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7681                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7682                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7683                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7684         }
7685
7686         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7687                 if (tp->link_config.phy_is_low_power) {
7688                         tp->link_config.phy_is_low_power = 0;
7689                         tp->link_config.speed = tp->link_config.orig_speed;
7690                         tp->link_config.duplex = tp->link_config.orig_duplex;
7691                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7692                 }
7693
7694                 err = tg3_setup_phy(tp, 0);
7695                 if (err)
7696                         return err;
7697
7698                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7699                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7700                         u32 tmp;
7701
7702                         /* Clear CRC stats. */
7703                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7704                                 tg3_writephy(tp, MII_TG3_TEST1,
7705                                              tmp | MII_TG3_TEST1_CRC_EN);
7706                                 tg3_readphy(tp, 0x14, &tmp);
7707                         }
7708                 }
7709         }
7710
7711         __tg3_set_rx_mode(tp->dev);
7712
7713         /* Initialize receive rules. */
7714         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7715         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7716         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7717         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7718
7719         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7720             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7721                 limit = 8;
7722         else
7723                 limit = 16;
7724         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7725                 limit -= 4;
7726         switch (limit) {
7727         case 16:
7728                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7729         case 15:
7730                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7731         case 14:
7732                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7733         case 13:
7734                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7735         case 12:
7736                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7737         case 11:
7738                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7739         case 10:
7740                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7741         case 9:
7742                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7743         case 8:
7744                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7745         case 7:
7746                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7747         case 6:
7748                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7749         case 5:
7750                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7751         case 4:
7752                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7753         case 3:
7754                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7755         case 2:
7756         case 1:
7757
7758         default:
7759                 break;
7760         }
7761
7762         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7763                 /* Write our heartbeat update interval to APE. */
7764                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7765                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7766
7767         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7768
7769         return 0;
7770 }
7771
7772 /* Called at device open time to get the chip ready for
7773  * packet processing.  Invoked with tp->lock held.
7774  */
7775 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7776 {
7777         tg3_switch_clocks(tp);
7778
7779         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7780
7781         return tg3_reset_hw(tp, reset_phy);
7782 }
7783
7784 #define TG3_STAT_ADD32(PSTAT, REG) \
7785 do {    u32 __val = tr32(REG); \
7786         (PSTAT)->low += __val; \
7787         if ((PSTAT)->low < __val) \
7788                 (PSTAT)->high += 1; \
7789 } while (0)
7790
7791 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7792 {
7793         struct tg3_hw_stats *sp = tp->hw_stats;
7794
7795         if (!netif_carrier_ok(tp->dev))
7796                 return;
7797
7798         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7799         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7800         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7801         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7802         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7803         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7804         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7805         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7806         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7807         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7808         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7809         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7810         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7811
7812         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7813         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7814         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7815         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7816         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7817         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7818         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7819         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7820         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7821         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7822         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7823         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7824         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7825         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7826
7827         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7828         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7829         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7830 }
7831
7832 static void tg3_timer(unsigned long __opaque)
7833 {
7834         struct tg3 *tp = (struct tg3 *) __opaque;
7835
7836         if (tp->irq_sync)
7837                 goto restart_timer;
7838
7839         spin_lock(&tp->lock);
7840
7841         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7842                 /* All of this garbage is because when using non-tagged
7843                  * IRQ status the mailbox/status_block protocol the chip
7844                  * uses with the cpu is race prone.
7845                  */
7846                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7847                         tw32(GRC_LOCAL_CTRL,
7848                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7849                 } else {
7850                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7851                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7852                 }
7853
7854                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7855                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7856                         spin_unlock(&tp->lock);
7857                         schedule_work(&tp->reset_task);
7858                         return;
7859                 }
7860         }
7861
7862         /* This part only runs once per second. */
7863         if (!--tp->timer_counter) {
7864                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7865                         tg3_periodic_fetch_stats(tp);
7866
7867                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7868                         u32 mac_stat;
7869                         int phy_event;
7870
7871                         mac_stat = tr32(MAC_STATUS);
7872
7873                         phy_event = 0;
7874                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7875                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7876                                         phy_event = 1;
7877                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7878                                 phy_event = 1;
7879
7880                         if (phy_event)
7881                                 tg3_setup_phy(tp, 0);
7882                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7883                         u32 mac_stat = tr32(MAC_STATUS);
7884                         int need_setup = 0;
7885
7886                         if (netif_carrier_ok(tp->dev) &&
7887                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7888                                 need_setup = 1;
7889                         }
7890                         if (! netif_carrier_ok(tp->dev) &&
7891                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7892                                          MAC_STATUS_SIGNAL_DET))) {
7893                                 need_setup = 1;
7894                         }
7895                         if (need_setup) {
7896                                 if (!tp->serdes_counter) {
7897                                         tw32_f(MAC_MODE,
7898                                              (tp->mac_mode &
7899                                               ~MAC_MODE_PORT_MODE_MASK));
7900                                         udelay(40);
7901                                         tw32_f(MAC_MODE, tp->mac_mode);
7902                                         udelay(40);
7903                                 }
7904                                 tg3_setup_phy(tp, 0);
7905                         }
7906                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7907                         tg3_serdes_parallel_detect(tp);
7908
7909                 tp->timer_counter = tp->timer_multiplier;
7910         }
7911
7912         /* Heartbeat is only sent once every 2 seconds.
7913          *
7914          * The heartbeat is to tell the ASF firmware that the host
7915          * driver is still alive.  In the event that the OS crashes,
7916          * ASF needs to reset the hardware to free up the FIFO space
7917          * that may be filled with rx packets destined for the host.
7918          * If the FIFO is full, ASF will no longer function properly.
7919          *
7920          * Unintended resets have been reported on real time kernels
7921          * where the timer doesn't run on time.  Netpoll will also have
7922          * same problem.
7923          *
7924          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7925          * to check the ring condition when the heartbeat is expiring
7926          * before doing the reset.  This will prevent most unintended
7927          * resets.
7928          */
7929         if (!--tp->asf_counter) {
7930                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7931                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7932                         tg3_wait_for_event_ack(tp);
7933
7934                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7935                                       FWCMD_NICDRV_ALIVE3);
7936                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7937                         /* 5 seconds timeout */
7938                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7939
7940                         tg3_generate_fw_event(tp);
7941                 }
7942                 tp->asf_counter = tp->asf_multiplier;
7943         }
7944
7945         spin_unlock(&tp->lock);
7946
7947 restart_timer:
7948         tp->timer.expires = jiffies + tp->timer_offset;
7949         add_timer(&tp->timer);
7950 }
7951
7952 static int tg3_request_irq(struct tg3 *tp, int irq_num)
7953 {
7954         irq_handler_t fn;
7955         unsigned long flags;
7956         char *name;
7957         struct tg3_napi *tnapi = &tp->napi[irq_num];
7958
7959         if (tp->irq_cnt == 1)
7960                 name = tp->dev->name;
7961         else {
7962                 name = &tnapi->irq_lbl[0];
7963                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
7964                 name[IFNAMSIZ-1] = 0;
7965         }
7966
7967         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
7968                 fn = tg3_msi;
7969                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7970                         fn = tg3_msi_1shot;
7971                 flags = IRQF_SAMPLE_RANDOM;
7972         } else {
7973                 fn = tg3_interrupt;
7974                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7975                         fn = tg3_interrupt_tagged;
7976                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7977         }
7978
7979         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
7980 }
7981
7982 static int tg3_test_interrupt(struct tg3 *tp)
7983 {
7984         struct tg3_napi *tnapi = &tp->napi[0];
7985         struct net_device *dev = tp->dev;
7986         int err, i, intr_ok = 0;
7987
7988         if (!netif_running(dev))
7989                 return -ENODEV;
7990
7991         tg3_disable_ints(tp);
7992
7993         free_irq(tnapi->irq_vec, tnapi);
7994
7995         err = request_irq(tnapi->irq_vec, tg3_test_isr,
7996                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7997         if (err)
7998                 return err;
7999
8000         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8001         tg3_enable_ints(tp);
8002
8003         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8004                tnapi->coal_now);
8005
8006         for (i = 0; i < 5; i++) {
8007                 u32 int_mbox, misc_host_ctrl;
8008
8009                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8010                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8011
8012                 if ((int_mbox != 0) ||
8013                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8014                         intr_ok = 1;
8015                         break;
8016                 }
8017
8018                 msleep(10);
8019         }
8020
8021         tg3_disable_ints(tp);
8022
8023         free_irq(tnapi->irq_vec, tnapi);
8024
8025         err = tg3_request_irq(tp, 0);
8026
8027         if (err)
8028                 return err;
8029
8030         if (intr_ok)
8031                 return 0;
8032
8033         return -EIO;
8034 }
8035
8036 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8037  * successfully restored
8038  */
8039 static int tg3_test_msi(struct tg3 *tp)
8040 {
8041         int err;
8042         u16 pci_cmd;
8043
8044         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8045                 return 0;
8046
8047         /* Turn off SERR reporting in case MSI terminates with Master
8048          * Abort.
8049          */
8050         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8051         pci_write_config_word(tp->pdev, PCI_COMMAND,
8052                               pci_cmd & ~PCI_COMMAND_SERR);
8053
8054         err = tg3_test_interrupt(tp);
8055
8056         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8057
8058         if (!err)
8059                 return 0;
8060
8061         /* other failures */
8062         if (err != -EIO)
8063                 return err;
8064
8065         /* MSI test failed, go back to INTx mode */
8066         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8067                "switching to INTx mode. Please report this failure to "
8068                "the PCI maintainer and include system chipset information.\n",
8069                        tp->dev->name);
8070
8071         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8072
8073         pci_disable_msi(tp->pdev);
8074
8075         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8076
8077         err = tg3_request_irq(tp, 0);
8078         if (err)
8079                 return err;
8080
8081         /* Need to reset the chip because the MSI cycle may have terminated
8082          * with Master Abort.
8083          */
8084         tg3_full_lock(tp, 1);
8085
8086         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8087         err = tg3_init_hw(tp, 1);
8088
8089         tg3_full_unlock(tp);
8090
8091         if (err)
8092                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8093
8094         return err;
8095 }
8096
8097 static int tg3_request_firmware(struct tg3 *tp)
8098 {
8099         const __be32 *fw_data;
8100
8101         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8102                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8103                        tp->dev->name, tp->fw_needed);
8104                 return -ENOENT;
8105         }
8106
8107         fw_data = (void *)tp->fw->data;
8108
8109         /* Firmware blob starts with version numbers, followed by
8110          * start address and _full_ length including BSS sections
8111          * (which must be longer than the actual data, of course
8112          */
8113
8114         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8115         if (tp->fw_len < (tp->fw->size - 12)) {
8116                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8117                        tp->dev->name, tp->fw_len, tp->fw_needed);
8118                 release_firmware(tp->fw);
8119                 tp->fw = NULL;
8120                 return -EINVAL;
8121         }
8122
8123         /* We no longer need firmware; we have it. */
8124         tp->fw_needed = NULL;
8125         return 0;
8126 }
8127
8128 static bool tg3_enable_msix(struct tg3 *tp)
8129 {
8130         int i, rc, cpus = num_online_cpus();
8131         struct msix_entry msix_ent[tp->irq_max];
8132
8133         if (cpus == 1)
8134                 /* Just fallback to the simpler MSI mode. */
8135                 return false;
8136
8137         /*
8138          * We want as many rx rings enabled as there are cpus.
8139          * The first MSIX vector only deals with link interrupts, etc,
8140          * so we add one to the number of vectors we are requesting.
8141          */
8142         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8143
8144         for (i = 0; i < tp->irq_max; i++) {
8145                 msix_ent[i].entry  = i;
8146                 msix_ent[i].vector = 0;
8147         }
8148
8149         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8150         if (rc != 0) {
8151                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8152                         return false;
8153                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8154                         return false;
8155                 printk(KERN_NOTICE
8156                        "%s: Requested %d MSI-X vectors, received %d\n",
8157                        tp->dev->name, tp->irq_cnt, rc);
8158                 tp->irq_cnt = rc;
8159         }
8160
8161         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8162
8163         for (i = 0; i < tp->irq_max; i++)
8164                 tp->napi[i].irq_vec = msix_ent[i].vector;
8165
8166         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8167
8168         return true;
8169 }
8170
8171 static void tg3_ints_init(struct tg3 *tp)
8172 {
8173         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8174             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8175                 /* All MSI supporting chips should support tagged
8176                  * status.  Assert that this is the case.
8177                  */
8178                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8179                        "Not using MSI.\n", tp->dev->name);
8180                 goto defcfg;
8181         }
8182
8183         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8184                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8185         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8186                  pci_enable_msi(tp->pdev) == 0)
8187                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8188
8189         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8190                 u32 msi_mode = tr32(MSGINT_MODE);
8191                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8192                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8193                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8194         }
8195 defcfg:
8196         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8197                 tp->irq_cnt = 1;
8198                 tp->napi[0].irq_vec = tp->pdev->irq;
8199                 tp->dev->real_num_tx_queues = 1;
8200         }
8201 }
8202
8203 static void tg3_ints_fini(struct tg3 *tp)
8204 {
8205         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8206                 pci_disable_msix(tp->pdev);
8207         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8208                 pci_disable_msi(tp->pdev);
8209         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8210         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8211 }
8212
8213 static int tg3_open(struct net_device *dev)
8214 {
8215         struct tg3 *tp = netdev_priv(dev);
8216         int i, err;
8217
8218         if (tp->fw_needed) {
8219                 err = tg3_request_firmware(tp);
8220                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8221                         if (err)
8222                                 return err;
8223                 } else if (err) {
8224                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8225                                tp->dev->name);
8226                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8227                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8228                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8229                                tp->dev->name);
8230                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8231                 }
8232         }
8233
8234         netif_carrier_off(tp->dev);
8235
8236         err = tg3_set_power_state(tp, PCI_D0);
8237         if (err)
8238                 return err;
8239
8240         tg3_full_lock(tp, 0);
8241
8242         tg3_disable_ints(tp);
8243         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8244
8245         tg3_full_unlock(tp);
8246
8247         /*
8248          * Setup interrupts first so we know how
8249          * many NAPI resources to allocate
8250          */
8251         tg3_ints_init(tp);
8252
8253         /* The placement of this call is tied
8254          * to the setup and use of Host TX descriptors.
8255          */
8256         err = tg3_alloc_consistent(tp);
8257         if (err)
8258                 goto err_out1;
8259
8260         tg3_napi_enable(tp);
8261
8262         for (i = 0; i < tp->irq_cnt; i++) {
8263                 struct tg3_napi *tnapi = &tp->napi[i];
8264                 err = tg3_request_irq(tp, i);
8265                 if (err) {
8266                         for (i--; i >= 0; i--)
8267                                 free_irq(tnapi->irq_vec, tnapi);
8268                         break;
8269                 }
8270         }
8271
8272         if (err)
8273                 goto err_out2;
8274
8275         tg3_full_lock(tp, 0);
8276
8277         err = tg3_init_hw(tp, 1);
8278         if (err) {
8279                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8280                 tg3_free_rings(tp);
8281         } else {
8282                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8283                         tp->timer_offset = HZ;
8284                 else
8285                         tp->timer_offset = HZ / 10;
8286
8287                 BUG_ON(tp->timer_offset > HZ);
8288                 tp->timer_counter = tp->timer_multiplier =
8289                         (HZ / tp->timer_offset);
8290                 tp->asf_counter = tp->asf_multiplier =
8291                         ((HZ / tp->timer_offset) * 2);
8292
8293                 init_timer(&tp->timer);
8294                 tp->timer.expires = jiffies + tp->timer_offset;
8295                 tp->timer.data = (unsigned long) tp;
8296                 tp->timer.function = tg3_timer;
8297         }
8298
8299         tg3_full_unlock(tp);
8300
8301         if (err)
8302                 goto err_out3;
8303
8304         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8305                 err = tg3_test_msi(tp);
8306
8307                 if (err) {
8308                         tg3_full_lock(tp, 0);
8309                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8310                         tg3_free_rings(tp);
8311                         tg3_full_unlock(tp);
8312
8313                         goto err_out2;
8314                 }
8315
8316                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8317                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8318                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
8319
8320                                 tw32(PCIE_TRANSACTION_CFG,
8321                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
8322                         }
8323                 }
8324         }
8325
8326         tg3_phy_start(tp);
8327
8328         tg3_full_lock(tp, 0);
8329
8330         add_timer(&tp->timer);
8331         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8332         tg3_enable_ints(tp);
8333
8334         tg3_full_unlock(tp);
8335
8336         netif_tx_start_all_queues(dev);
8337
8338         return 0;
8339
8340 err_out3:
8341         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8342                 struct tg3_napi *tnapi = &tp->napi[i];
8343                 free_irq(tnapi->irq_vec, tnapi);
8344         }
8345
8346 err_out2:
8347         tg3_napi_disable(tp);
8348         tg3_free_consistent(tp);
8349
8350 err_out1:
8351         tg3_ints_fini(tp);
8352         return err;
8353 }
8354
8355 #if 0
8356 /*static*/ void tg3_dump_state(struct tg3 *tp)
8357 {
8358         u32 val32, val32_2, val32_3, val32_4, val32_5;
8359         u16 val16;
8360         int i;
8361         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8362
8363         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8364         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8365         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8366                val16, val32);
8367
8368         /* MAC block */
8369         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8370                tr32(MAC_MODE), tr32(MAC_STATUS));
8371         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8372                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8373         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8374                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8375         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8376                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8377
8378         /* Send data initiator control block */
8379         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8380                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8381         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8382                tr32(SNDDATAI_STATSCTRL));
8383
8384         /* Send data completion control block */
8385         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8386
8387         /* Send BD ring selector block */
8388         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8389                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8390
8391         /* Send BD initiator control block */
8392         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8393                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8394
8395         /* Send BD completion control block */
8396         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8397
8398         /* Receive list placement control block */
8399         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8400                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8401         printk("       RCVLPC_STATSCTRL[%08x]\n",
8402                tr32(RCVLPC_STATSCTRL));
8403
8404         /* Receive data and receive BD initiator control block */
8405         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8406                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8407
8408         /* Receive data completion control block */
8409         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8410                tr32(RCVDCC_MODE));
8411
8412         /* Receive BD initiator control block */
8413         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8414                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8415
8416         /* Receive BD completion control block */
8417         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8418                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8419
8420         /* Receive list selector control block */
8421         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8422                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8423
8424         /* Mbuf cluster free block */
8425         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8426                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8427
8428         /* Host coalescing control block */
8429         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8430                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8431         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8432                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8433                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8434         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8435                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8436                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8437         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8438                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8439         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8440                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8441
8442         /* Memory arbiter control block */
8443         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8444                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8445
8446         /* Buffer manager control block */
8447         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8448                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8449         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8450                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8451         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8452                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8453                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8454                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8455
8456         /* Read DMA control block */
8457         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8458                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8459
8460         /* Write DMA control block */
8461         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8462                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8463
8464         /* DMA completion block */
8465         printk("DEBUG: DMAC_MODE[%08x]\n",
8466                tr32(DMAC_MODE));
8467
8468         /* GRC block */
8469         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8470                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8471         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8472                tr32(GRC_LOCAL_CTRL));
8473
8474         /* TG3_BDINFOs */
8475         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8476                tr32(RCVDBDI_JUMBO_BD + 0x0),
8477                tr32(RCVDBDI_JUMBO_BD + 0x4),
8478                tr32(RCVDBDI_JUMBO_BD + 0x8),
8479                tr32(RCVDBDI_JUMBO_BD + 0xc));
8480         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8481                tr32(RCVDBDI_STD_BD + 0x0),
8482                tr32(RCVDBDI_STD_BD + 0x4),
8483                tr32(RCVDBDI_STD_BD + 0x8),
8484                tr32(RCVDBDI_STD_BD + 0xc));
8485         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8486                tr32(RCVDBDI_MINI_BD + 0x0),
8487                tr32(RCVDBDI_MINI_BD + 0x4),
8488                tr32(RCVDBDI_MINI_BD + 0x8),
8489                tr32(RCVDBDI_MINI_BD + 0xc));
8490
8491         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8492         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8493         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8494         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8495         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8496                val32, val32_2, val32_3, val32_4);
8497
8498         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8499         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8500         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8501         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8502         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8503                val32, val32_2, val32_3, val32_4);
8504
8505         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8506         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8507         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8508         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8509         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8510         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8511                val32, val32_2, val32_3, val32_4, val32_5);
8512
8513         /* SW status block */
8514         printk(KERN_DEBUG
8515          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8516                sblk->status,
8517                sblk->status_tag,
8518                sblk->rx_jumbo_consumer,
8519                sblk->rx_consumer,
8520                sblk->rx_mini_consumer,
8521                sblk->idx[0].rx_producer,
8522                sblk->idx[0].tx_consumer);
8523
8524         /* SW statistics block */
8525         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8526                ((u32 *)tp->hw_stats)[0],
8527                ((u32 *)tp->hw_stats)[1],
8528                ((u32 *)tp->hw_stats)[2],
8529                ((u32 *)tp->hw_stats)[3]);
8530
8531         /* Mailboxes */
8532         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8533                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8534                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8535                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8536                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8537
8538         /* NIC side send descriptors. */
8539         for (i = 0; i < 6; i++) {
8540                 unsigned long txd;
8541
8542                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8543                         + (i * sizeof(struct tg3_tx_buffer_desc));
8544                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8545                        i,
8546                        readl(txd + 0x0), readl(txd + 0x4),
8547                        readl(txd + 0x8), readl(txd + 0xc));
8548         }
8549
8550         /* NIC side RX descriptors. */
8551         for (i = 0; i < 6; i++) {
8552                 unsigned long rxd;
8553
8554                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8555                         + (i * sizeof(struct tg3_rx_buffer_desc));
8556                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8557                        i,
8558                        readl(rxd + 0x0), readl(rxd + 0x4),
8559                        readl(rxd + 0x8), readl(rxd + 0xc));
8560                 rxd += (4 * sizeof(u32));
8561                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8562                        i,
8563                        readl(rxd + 0x0), readl(rxd + 0x4),
8564                        readl(rxd + 0x8), readl(rxd + 0xc));
8565         }
8566
8567         for (i = 0; i < 6; i++) {
8568                 unsigned long rxd;
8569
8570                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8571                         + (i * sizeof(struct tg3_rx_buffer_desc));
8572                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8573                        i,
8574                        readl(rxd + 0x0), readl(rxd + 0x4),
8575                        readl(rxd + 0x8), readl(rxd + 0xc));
8576                 rxd += (4 * sizeof(u32));
8577                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8578                        i,
8579                        readl(rxd + 0x0), readl(rxd + 0x4),
8580                        readl(rxd + 0x8), readl(rxd + 0xc));
8581         }
8582 }
8583 #endif
8584
8585 static struct net_device_stats *tg3_get_stats(struct net_device *);
8586 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8587
8588 static int tg3_close(struct net_device *dev)
8589 {
8590         int i;
8591         struct tg3 *tp = netdev_priv(dev);
8592
8593         tg3_napi_disable(tp);
8594         cancel_work_sync(&tp->reset_task);
8595
8596         netif_tx_stop_all_queues(dev);
8597
8598         del_timer_sync(&tp->timer);
8599
8600         tg3_full_lock(tp, 1);
8601 #if 0
8602         tg3_dump_state(tp);
8603 #endif
8604
8605         tg3_disable_ints(tp);
8606
8607         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8608         tg3_free_rings(tp);
8609         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8610
8611         tg3_full_unlock(tp);
8612
8613         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8614                 struct tg3_napi *tnapi = &tp->napi[i];
8615                 free_irq(tnapi->irq_vec, tnapi);
8616         }
8617
8618         tg3_ints_fini(tp);
8619
8620         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8621                sizeof(tp->net_stats_prev));
8622         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8623                sizeof(tp->estats_prev));
8624
8625         tg3_free_consistent(tp);
8626
8627         tg3_set_power_state(tp, PCI_D3hot);
8628
8629         netif_carrier_off(tp->dev);
8630
8631         return 0;
8632 }
8633
8634 static inline unsigned long get_stat64(tg3_stat64_t *val)
8635 {
8636         unsigned long ret;
8637
8638 #if (BITS_PER_LONG == 32)
8639         ret = val->low;
8640 #else
8641         ret = ((u64)val->high << 32) | ((u64)val->low);
8642 #endif
8643         return ret;
8644 }
8645
8646 static inline u64 get_estat64(tg3_stat64_t *val)
8647 {
8648        return ((u64)val->high << 32) | ((u64)val->low);
8649 }
8650
8651 static unsigned long calc_crc_errors(struct tg3 *tp)
8652 {
8653         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8654
8655         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8656             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8657              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8658                 u32 val;
8659
8660                 spin_lock_bh(&tp->lock);
8661                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8662                         tg3_writephy(tp, MII_TG3_TEST1,
8663                                      val | MII_TG3_TEST1_CRC_EN);
8664                         tg3_readphy(tp, 0x14, &val);
8665                 } else
8666                         val = 0;
8667                 spin_unlock_bh(&tp->lock);
8668
8669                 tp->phy_crc_errors += val;
8670
8671                 return tp->phy_crc_errors;
8672         }
8673
8674         return get_stat64(&hw_stats->rx_fcs_errors);
8675 }
8676
8677 #define ESTAT_ADD(member) \
8678         estats->member =        old_estats->member + \
8679                                 get_estat64(&hw_stats->member)
8680
8681 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8682 {
8683         struct tg3_ethtool_stats *estats = &tp->estats;
8684         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8685         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8686
8687         if (!hw_stats)
8688                 return old_estats;
8689
8690         ESTAT_ADD(rx_octets);
8691         ESTAT_ADD(rx_fragments);
8692         ESTAT_ADD(rx_ucast_packets);
8693         ESTAT_ADD(rx_mcast_packets);
8694         ESTAT_ADD(rx_bcast_packets);
8695         ESTAT_ADD(rx_fcs_errors);
8696         ESTAT_ADD(rx_align_errors);
8697         ESTAT_ADD(rx_xon_pause_rcvd);
8698         ESTAT_ADD(rx_xoff_pause_rcvd);
8699         ESTAT_ADD(rx_mac_ctrl_rcvd);
8700         ESTAT_ADD(rx_xoff_entered);
8701         ESTAT_ADD(rx_frame_too_long_errors);
8702         ESTAT_ADD(rx_jabbers);
8703         ESTAT_ADD(rx_undersize_packets);
8704         ESTAT_ADD(rx_in_length_errors);
8705         ESTAT_ADD(rx_out_length_errors);
8706         ESTAT_ADD(rx_64_or_less_octet_packets);
8707         ESTAT_ADD(rx_65_to_127_octet_packets);
8708         ESTAT_ADD(rx_128_to_255_octet_packets);
8709         ESTAT_ADD(rx_256_to_511_octet_packets);
8710         ESTAT_ADD(rx_512_to_1023_octet_packets);
8711         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8712         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8713         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8714         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8715         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8716
8717         ESTAT_ADD(tx_octets);
8718         ESTAT_ADD(tx_collisions);
8719         ESTAT_ADD(tx_xon_sent);
8720         ESTAT_ADD(tx_xoff_sent);
8721         ESTAT_ADD(tx_flow_control);
8722         ESTAT_ADD(tx_mac_errors);
8723         ESTAT_ADD(tx_single_collisions);
8724         ESTAT_ADD(tx_mult_collisions);
8725         ESTAT_ADD(tx_deferred);
8726         ESTAT_ADD(tx_excessive_collisions);
8727         ESTAT_ADD(tx_late_collisions);
8728         ESTAT_ADD(tx_collide_2times);
8729         ESTAT_ADD(tx_collide_3times);
8730         ESTAT_ADD(tx_collide_4times);
8731         ESTAT_ADD(tx_collide_5times);
8732         ESTAT_ADD(tx_collide_6times);
8733         ESTAT_ADD(tx_collide_7times);
8734         ESTAT_ADD(tx_collide_8times);
8735         ESTAT_ADD(tx_collide_9times);
8736         ESTAT_ADD(tx_collide_10times);
8737         ESTAT_ADD(tx_collide_11times);
8738         ESTAT_ADD(tx_collide_12times);
8739         ESTAT_ADD(tx_collide_13times);
8740         ESTAT_ADD(tx_collide_14times);
8741         ESTAT_ADD(tx_collide_15times);
8742         ESTAT_ADD(tx_ucast_packets);
8743         ESTAT_ADD(tx_mcast_packets);
8744         ESTAT_ADD(tx_bcast_packets);
8745         ESTAT_ADD(tx_carrier_sense_errors);
8746         ESTAT_ADD(tx_discards);
8747         ESTAT_ADD(tx_errors);
8748
8749         ESTAT_ADD(dma_writeq_full);
8750         ESTAT_ADD(dma_write_prioq_full);
8751         ESTAT_ADD(rxbds_empty);
8752         ESTAT_ADD(rx_discards);
8753         ESTAT_ADD(rx_errors);
8754         ESTAT_ADD(rx_threshold_hit);
8755
8756         ESTAT_ADD(dma_readq_full);
8757         ESTAT_ADD(dma_read_prioq_full);
8758         ESTAT_ADD(tx_comp_queue_full);
8759
8760         ESTAT_ADD(ring_set_send_prod_index);
8761         ESTAT_ADD(ring_status_update);
8762         ESTAT_ADD(nic_irqs);
8763         ESTAT_ADD(nic_avoided_irqs);
8764         ESTAT_ADD(nic_tx_threshold_hit);
8765
8766         return estats;
8767 }
8768
8769 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8770 {
8771         struct tg3 *tp = netdev_priv(dev);
8772         struct net_device_stats *stats = &tp->net_stats;
8773         struct net_device_stats *old_stats = &tp->net_stats_prev;
8774         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8775
8776         if (!hw_stats)
8777                 return old_stats;
8778
8779         stats->rx_packets = old_stats->rx_packets +
8780                 get_stat64(&hw_stats->rx_ucast_packets) +
8781                 get_stat64(&hw_stats->rx_mcast_packets) +
8782                 get_stat64(&hw_stats->rx_bcast_packets);
8783
8784         stats->tx_packets = old_stats->tx_packets +
8785                 get_stat64(&hw_stats->tx_ucast_packets) +
8786                 get_stat64(&hw_stats->tx_mcast_packets) +
8787                 get_stat64(&hw_stats->tx_bcast_packets);
8788
8789         stats->rx_bytes = old_stats->rx_bytes +
8790                 get_stat64(&hw_stats->rx_octets);
8791         stats->tx_bytes = old_stats->tx_bytes +
8792                 get_stat64(&hw_stats->tx_octets);
8793
8794         stats->rx_errors = old_stats->rx_errors +
8795                 get_stat64(&hw_stats->rx_errors);
8796         stats->tx_errors = old_stats->tx_errors +
8797                 get_stat64(&hw_stats->tx_errors) +
8798                 get_stat64(&hw_stats->tx_mac_errors) +
8799                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8800                 get_stat64(&hw_stats->tx_discards);
8801
8802         stats->multicast = old_stats->multicast +
8803                 get_stat64(&hw_stats->rx_mcast_packets);
8804         stats->collisions = old_stats->collisions +
8805                 get_stat64(&hw_stats->tx_collisions);
8806
8807         stats->rx_length_errors = old_stats->rx_length_errors +
8808                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8809                 get_stat64(&hw_stats->rx_undersize_packets);
8810
8811         stats->rx_over_errors = old_stats->rx_over_errors +
8812                 get_stat64(&hw_stats->rxbds_empty);
8813         stats->rx_frame_errors = old_stats->rx_frame_errors +
8814                 get_stat64(&hw_stats->rx_align_errors);
8815         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8816                 get_stat64(&hw_stats->tx_discards);
8817         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8818                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8819
8820         stats->rx_crc_errors = old_stats->rx_crc_errors +
8821                 calc_crc_errors(tp);
8822
8823         stats->rx_missed_errors = old_stats->rx_missed_errors +
8824                 get_stat64(&hw_stats->rx_discards);
8825
8826         return stats;
8827 }
8828
8829 static inline u32 calc_crc(unsigned char *buf, int len)
8830 {
8831         u32 reg;
8832         u32 tmp;
8833         int j, k;
8834
8835         reg = 0xffffffff;
8836
8837         for (j = 0; j < len; j++) {
8838                 reg ^= buf[j];
8839
8840                 for (k = 0; k < 8; k++) {
8841                         tmp = reg & 0x01;
8842
8843                         reg >>= 1;
8844
8845                         if (tmp) {
8846                                 reg ^= 0xedb88320;
8847                         }
8848                 }
8849         }
8850
8851         return ~reg;
8852 }
8853
8854 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8855 {
8856         /* accept or reject all multicast frames */
8857         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8858         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8859         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8860         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8861 }
8862
8863 static void __tg3_set_rx_mode(struct net_device *dev)
8864 {
8865         struct tg3 *tp = netdev_priv(dev);
8866         u32 rx_mode;
8867
8868         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8869                                   RX_MODE_KEEP_VLAN_TAG);
8870
8871         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8872          * flag clear.
8873          */
8874 #if TG3_VLAN_TAG_USED
8875         if (!tp->vlgrp &&
8876             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8877                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8878 #else
8879         /* By definition, VLAN is disabled always in this
8880          * case.
8881          */
8882         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8883                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8884 #endif
8885
8886         if (dev->flags & IFF_PROMISC) {
8887                 /* Promiscuous mode. */
8888                 rx_mode |= RX_MODE_PROMISC;
8889         } else if (dev->flags & IFF_ALLMULTI) {
8890                 /* Accept all multicast. */
8891                 tg3_set_multi (tp, 1);
8892         } else if (dev->mc_count < 1) {
8893                 /* Reject all multicast. */
8894                 tg3_set_multi (tp, 0);
8895         } else {
8896                 /* Accept one or more multicast(s). */
8897                 struct dev_mc_list *mclist;
8898                 unsigned int i;
8899                 u32 mc_filter[4] = { 0, };
8900                 u32 regidx;
8901                 u32 bit;
8902                 u32 crc;
8903
8904                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8905                      i++, mclist = mclist->next) {
8906
8907                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8908                         bit = ~crc & 0x7f;
8909                         regidx = (bit & 0x60) >> 5;
8910                         bit &= 0x1f;
8911                         mc_filter[regidx] |= (1 << bit);
8912                 }
8913
8914                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8915                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8916                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8917                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8918         }
8919
8920         if (rx_mode != tp->rx_mode) {
8921                 tp->rx_mode = rx_mode;
8922                 tw32_f(MAC_RX_MODE, rx_mode);
8923                 udelay(10);
8924         }
8925 }
8926
8927 static void tg3_set_rx_mode(struct net_device *dev)
8928 {
8929         struct tg3 *tp = netdev_priv(dev);
8930
8931         if (!netif_running(dev))
8932                 return;
8933
8934         tg3_full_lock(tp, 0);
8935         __tg3_set_rx_mode(dev);
8936         tg3_full_unlock(tp);
8937 }
8938
8939 #define TG3_REGDUMP_LEN         (32 * 1024)
8940
8941 static int tg3_get_regs_len(struct net_device *dev)
8942 {
8943         return TG3_REGDUMP_LEN;
8944 }
8945
8946 static void tg3_get_regs(struct net_device *dev,
8947                 struct ethtool_regs *regs, void *_p)
8948 {
8949         u32 *p = _p;
8950         struct tg3 *tp = netdev_priv(dev);
8951         u8 *orig_p = _p;
8952         int i;
8953
8954         regs->version = 0;
8955
8956         memset(p, 0, TG3_REGDUMP_LEN);
8957
8958         if (tp->link_config.phy_is_low_power)
8959                 return;
8960
8961         tg3_full_lock(tp, 0);
8962
8963 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8964 #define GET_REG32_LOOP(base,len)                \
8965 do {    p = (u32 *)(orig_p + (base));           \
8966         for (i = 0; i < len; i += 4)            \
8967                 __GET_REG32((base) + i);        \
8968 } while (0)
8969 #define GET_REG32_1(reg)                        \
8970 do {    p = (u32 *)(orig_p + (reg));            \
8971         __GET_REG32((reg));                     \
8972 } while (0)
8973
8974         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8975         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8976         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8977         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8978         GET_REG32_1(SNDDATAC_MODE);
8979         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8980         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8981         GET_REG32_1(SNDBDC_MODE);
8982         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8983         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8984         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8985         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8986         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8987         GET_REG32_1(RCVDCC_MODE);
8988         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8989         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8990         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8991         GET_REG32_1(MBFREE_MODE);
8992         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8993         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8994         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8995         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8996         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8997         GET_REG32_1(RX_CPU_MODE);
8998         GET_REG32_1(RX_CPU_STATE);
8999         GET_REG32_1(RX_CPU_PGMCTR);
9000         GET_REG32_1(RX_CPU_HWBKPT);
9001         GET_REG32_1(TX_CPU_MODE);
9002         GET_REG32_1(TX_CPU_STATE);
9003         GET_REG32_1(TX_CPU_PGMCTR);
9004         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9005         GET_REG32_LOOP(FTQ_RESET, 0x120);
9006         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9007         GET_REG32_1(DMAC_MODE);
9008         GET_REG32_LOOP(GRC_MODE, 0x4c);
9009         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9010                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9011
9012 #undef __GET_REG32
9013 #undef GET_REG32_LOOP
9014 #undef GET_REG32_1
9015
9016         tg3_full_unlock(tp);
9017 }
9018
9019 static int tg3_get_eeprom_len(struct net_device *dev)
9020 {
9021         struct tg3 *tp = netdev_priv(dev);
9022
9023         return tp->nvram_size;
9024 }
9025
9026 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9027 {
9028         struct tg3 *tp = netdev_priv(dev);
9029         int ret;
9030         u8  *pd;
9031         u32 i, offset, len, b_offset, b_count;
9032         __be32 val;
9033
9034         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9035                 return -EINVAL;
9036
9037         if (tp->link_config.phy_is_low_power)
9038                 return -EAGAIN;
9039
9040         offset = eeprom->offset;
9041         len = eeprom->len;
9042         eeprom->len = 0;
9043
9044         eeprom->magic = TG3_EEPROM_MAGIC;
9045
9046         if (offset & 3) {
9047                 /* adjustments to start on required 4 byte boundary */
9048                 b_offset = offset & 3;
9049                 b_count = 4 - b_offset;
9050                 if (b_count > len) {
9051                         /* i.e. offset=1 len=2 */
9052                         b_count = len;
9053                 }
9054                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9055                 if (ret)
9056                         return ret;
9057                 memcpy(data, ((char*)&val) + b_offset, b_count);
9058                 len -= b_count;
9059                 offset += b_count;
9060                 eeprom->len += b_count;
9061         }
9062
9063         /* read bytes upto the last 4 byte boundary */
9064         pd = &data[eeprom->len];
9065         for (i = 0; i < (len - (len & 3)); i += 4) {
9066                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9067                 if (ret) {
9068                         eeprom->len += i;
9069                         return ret;
9070                 }
9071                 memcpy(pd + i, &val, 4);
9072         }
9073         eeprom->len += i;
9074
9075         if (len & 3) {
9076                 /* read last bytes not ending on 4 byte boundary */
9077                 pd = &data[eeprom->len];
9078                 b_count = len & 3;
9079                 b_offset = offset + len - b_count;
9080                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9081                 if (ret)
9082                         return ret;
9083                 memcpy(pd, &val, b_count);
9084                 eeprom->len += b_count;
9085         }
9086         return 0;
9087 }
9088
9089 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9090
9091 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9092 {
9093         struct tg3 *tp = netdev_priv(dev);
9094         int ret;
9095         u32 offset, len, b_offset, odd_len;
9096         u8 *buf;
9097         __be32 start, end;
9098
9099         if (tp->link_config.phy_is_low_power)
9100                 return -EAGAIN;
9101
9102         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9103             eeprom->magic != TG3_EEPROM_MAGIC)
9104                 return -EINVAL;
9105
9106         offset = eeprom->offset;
9107         len = eeprom->len;
9108
9109         if ((b_offset = (offset & 3))) {
9110                 /* adjustments to start on required 4 byte boundary */
9111                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9112                 if (ret)
9113                         return ret;
9114                 len += b_offset;
9115                 offset &= ~3;
9116                 if (len < 4)
9117                         len = 4;
9118         }
9119
9120         odd_len = 0;
9121         if (len & 3) {
9122                 /* adjustments to end on required 4 byte boundary */
9123                 odd_len = 1;
9124                 len = (len + 3) & ~3;
9125                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9126                 if (ret)
9127                         return ret;
9128         }
9129
9130         buf = data;
9131         if (b_offset || odd_len) {
9132                 buf = kmalloc(len, GFP_KERNEL);
9133                 if (!buf)
9134                         return -ENOMEM;
9135                 if (b_offset)
9136                         memcpy(buf, &start, 4);
9137                 if (odd_len)
9138                         memcpy(buf+len-4, &end, 4);
9139                 memcpy(buf + b_offset, data, eeprom->len);
9140         }
9141
9142         ret = tg3_nvram_write_block(tp, offset, len, buf);
9143
9144         if (buf != data)
9145                 kfree(buf);
9146
9147         return ret;
9148 }
9149
9150 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9151 {
9152         struct tg3 *tp = netdev_priv(dev);
9153
9154         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9155                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9156                         return -EAGAIN;
9157                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9158         }
9159
9160         cmd->supported = (SUPPORTED_Autoneg);
9161
9162         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9163                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9164                                    SUPPORTED_1000baseT_Full);
9165
9166         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9167                 cmd->supported |= (SUPPORTED_100baseT_Half |
9168                                   SUPPORTED_100baseT_Full |
9169                                   SUPPORTED_10baseT_Half |
9170                                   SUPPORTED_10baseT_Full |
9171                                   SUPPORTED_TP);
9172                 cmd->port = PORT_TP;
9173         } else {
9174                 cmd->supported |= SUPPORTED_FIBRE;
9175                 cmd->port = PORT_FIBRE;
9176         }
9177
9178         cmd->advertising = tp->link_config.advertising;
9179         if (netif_running(dev)) {
9180                 cmd->speed = tp->link_config.active_speed;
9181                 cmd->duplex = tp->link_config.active_duplex;
9182         }
9183         cmd->phy_address = PHY_ADDR;
9184         cmd->transceiver = XCVR_INTERNAL;
9185         cmd->autoneg = tp->link_config.autoneg;
9186         cmd->maxtxpkt = 0;
9187         cmd->maxrxpkt = 0;
9188         return 0;
9189 }
9190
9191 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9192 {
9193         struct tg3 *tp = netdev_priv(dev);
9194
9195         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9196                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9197                         return -EAGAIN;
9198                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9199         }
9200
9201         if (cmd->autoneg != AUTONEG_ENABLE &&
9202             cmd->autoneg != AUTONEG_DISABLE)
9203                 return -EINVAL;
9204
9205         if (cmd->autoneg == AUTONEG_DISABLE &&
9206             cmd->duplex != DUPLEX_FULL &&
9207             cmd->duplex != DUPLEX_HALF)
9208                 return -EINVAL;
9209
9210         if (cmd->autoneg == AUTONEG_ENABLE) {
9211                 u32 mask = ADVERTISED_Autoneg |
9212                            ADVERTISED_Pause |
9213                            ADVERTISED_Asym_Pause;
9214
9215                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9216                         mask |= ADVERTISED_1000baseT_Half |
9217                                 ADVERTISED_1000baseT_Full;
9218
9219                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9220                         mask |= ADVERTISED_100baseT_Half |
9221                                 ADVERTISED_100baseT_Full |
9222                                 ADVERTISED_10baseT_Half |
9223                                 ADVERTISED_10baseT_Full |
9224                                 ADVERTISED_TP;
9225                 else
9226                         mask |= ADVERTISED_FIBRE;
9227
9228                 if (cmd->advertising & ~mask)
9229                         return -EINVAL;
9230
9231                 mask &= (ADVERTISED_1000baseT_Half |
9232                          ADVERTISED_1000baseT_Full |
9233                          ADVERTISED_100baseT_Half |
9234                          ADVERTISED_100baseT_Full |
9235                          ADVERTISED_10baseT_Half |
9236                          ADVERTISED_10baseT_Full);
9237
9238                 cmd->advertising &= mask;
9239         } else {
9240                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9241                         if (cmd->speed != SPEED_1000)
9242                                 return -EINVAL;
9243
9244                         if (cmd->duplex != DUPLEX_FULL)
9245                                 return -EINVAL;
9246                 } else {
9247                         if (cmd->speed != SPEED_100 &&
9248                             cmd->speed != SPEED_10)
9249                                 return -EINVAL;
9250                 }
9251         }
9252
9253         tg3_full_lock(tp, 0);
9254
9255         tp->link_config.autoneg = cmd->autoneg;
9256         if (cmd->autoneg == AUTONEG_ENABLE) {
9257                 tp->link_config.advertising = (cmd->advertising |
9258                                               ADVERTISED_Autoneg);
9259                 tp->link_config.speed = SPEED_INVALID;
9260                 tp->link_config.duplex = DUPLEX_INVALID;
9261         } else {
9262                 tp->link_config.advertising = 0;
9263                 tp->link_config.speed = cmd->speed;
9264                 tp->link_config.duplex = cmd->duplex;
9265         }
9266
9267         tp->link_config.orig_speed = tp->link_config.speed;
9268         tp->link_config.orig_duplex = tp->link_config.duplex;
9269         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9270
9271         if (netif_running(dev))
9272                 tg3_setup_phy(tp, 1);
9273
9274         tg3_full_unlock(tp);
9275
9276         return 0;
9277 }
9278
9279 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9280 {
9281         struct tg3 *tp = netdev_priv(dev);
9282
9283         strcpy(info->driver, DRV_MODULE_NAME);
9284         strcpy(info->version, DRV_MODULE_VERSION);
9285         strcpy(info->fw_version, tp->fw_ver);
9286         strcpy(info->bus_info, pci_name(tp->pdev));
9287 }
9288
9289 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9290 {
9291         struct tg3 *tp = netdev_priv(dev);
9292
9293         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9294             device_can_wakeup(&tp->pdev->dev))
9295                 wol->supported = WAKE_MAGIC;
9296         else
9297                 wol->supported = 0;
9298         wol->wolopts = 0;
9299         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9300             device_can_wakeup(&tp->pdev->dev))
9301                 wol->wolopts = WAKE_MAGIC;
9302         memset(&wol->sopass, 0, sizeof(wol->sopass));
9303 }
9304
9305 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9306 {
9307         struct tg3 *tp = netdev_priv(dev);
9308         struct device *dp = &tp->pdev->dev;
9309
9310         if (wol->wolopts & ~WAKE_MAGIC)
9311                 return -EINVAL;
9312         if ((wol->wolopts & WAKE_MAGIC) &&
9313             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9314                 return -EINVAL;
9315
9316         spin_lock_bh(&tp->lock);
9317         if (wol->wolopts & WAKE_MAGIC) {
9318                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9319                 device_set_wakeup_enable(dp, true);
9320         } else {
9321                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9322                 device_set_wakeup_enable(dp, false);
9323         }
9324         spin_unlock_bh(&tp->lock);
9325
9326         return 0;
9327 }
9328
9329 static u32 tg3_get_msglevel(struct net_device *dev)
9330 {
9331         struct tg3 *tp = netdev_priv(dev);
9332         return tp->msg_enable;
9333 }
9334
9335 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9336 {
9337         struct tg3 *tp = netdev_priv(dev);
9338         tp->msg_enable = value;
9339 }
9340
9341 static int tg3_set_tso(struct net_device *dev, u32 value)
9342 {
9343         struct tg3 *tp = netdev_priv(dev);
9344
9345         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9346                 if (value)
9347                         return -EINVAL;
9348                 return 0;
9349         }
9350         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9351             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9352                 if (value) {
9353                         dev->features |= NETIF_F_TSO6;
9354                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9355                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9356                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9357                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9358                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9359                                 dev->features |= NETIF_F_TSO_ECN;
9360                 } else
9361                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9362         }
9363         return ethtool_op_set_tso(dev, value);
9364 }
9365
9366 static int tg3_nway_reset(struct net_device *dev)
9367 {
9368         struct tg3 *tp = netdev_priv(dev);
9369         int r;
9370
9371         if (!netif_running(dev))
9372                 return -EAGAIN;
9373
9374         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9375                 return -EINVAL;
9376
9377         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9378                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9379                         return -EAGAIN;
9380                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
9381         } else {
9382                 u32 bmcr;
9383
9384                 spin_lock_bh(&tp->lock);
9385                 r = -EINVAL;
9386                 tg3_readphy(tp, MII_BMCR, &bmcr);
9387                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9388                     ((bmcr & BMCR_ANENABLE) ||
9389                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9390                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9391                                                    BMCR_ANENABLE);
9392                         r = 0;
9393                 }
9394                 spin_unlock_bh(&tp->lock);
9395         }
9396
9397         return r;
9398 }
9399
9400 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9401 {
9402         struct tg3 *tp = netdev_priv(dev);
9403
9404         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9405         ering->rx_mini_max_pending = 0;
9406         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9407                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9408         else
9409                 ering->rx_jumbo_max_pending = 0;
9410
9411         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9412
9413         ering->rx_pending = tp->rx_pending;
9414         ering->rx_mini_pending = 0;
9415         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9416                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9417         else
9418                 ering->rx_jumbo_pending = 0;
9419
9420         ering->tx_pending = tp->napi[0].tx_pending;
9421 }
9422
9423 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9424 {
9425         struct tg3 *tp = netdev_priv(dev);
9426         int i, irq_sync = 0, err = 0;
9427
9428         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9429             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9430             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9431             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9432             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9433              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9434                 return -EINVAL;
9435
9436         if (netif_running(dev)) {
9437                 tg3_phy_stop(tp);
9438                 tg3_netif_stop(tp);
9439                 irq_sync = 1;
9440         }
9441
9442         tg3_full_lock(tp, irq_sync);
9443
9444         tp->rx_pending = ering->rx_pending;
9445
9446         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9447             tp->rx_pending > 63)
9448                 tp->rx_pending = 63;
9449         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9450
9451         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9452                 tp->napi[i].tx_pending = ering->tx_pending;
9453
9454         if (netif_running(dev)) {
9455                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9456                 err = tg3_restart_hw(tp, 1);
9457                 if (!err)
9458                         tg3_netif_start(tp);
9459         }
9460
9461         tg3_full_unlock(tp);
9462
9463         if (irq_sync && !err)
9464                 tg3_phy_start(tp);
9465
9466         return err;
9467 }
9468
9469 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9470 {
9471         struct tg3 *tp = netdev_priv(dev);
9472
9473         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9474
9475         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9476                 epause->rx_pause = 1;
9477         else
9478                 epause->rx_pause = 0;
9479
9480         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9481                 epause->tx_pause = 1;
9482         else
9483                 epause->tx_pause = 0;
9484 }
9485
9486 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9487 {
9488         struct tg3 *tp = netdev_priv(dev);
9489         int err = 0;
9490
9491         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9492                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9493                         return -EAGAIN;
9494
9495                 if (epause->autoneg) {
9496                         u32 newadv;
9497                         struct phy_device *phydev;
9498
9499                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9500
9501                         if (epause->rx_pause) {
9502                                 if (epause->tx_pause)
9503                                         newadv = ADVERTISED_Pause;
9504                                 else
9505                                         newadv = ADVERTISED_Pause |
9506                                                  ADVERTISED_Asym_Pause;
9507                         } else if (epause->tx_pause) {
9508                                 newadv = ADVERTISED_Asym_Pause;
9509                         } else
9510                                 newadv = 0;
9511
9512                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9513                                 u32 oldadv = phydev->advertising &
9514                                              (ADVERTISED_Pause |
9515                                               ADVERTISED_Asym_Pause);
9516                                 if (oldadv != newadv) {
9517                                         phydev->advertising &=
9518                                                 ~(ADVERTISED_Pause |
9519                                                   ADVERTISED_Asym_Pause);
9520                                         phydev->advertising |= newadv;
9521                                         err = phy_start_aneg(phydev);
9522                                 }
9523                         } else {
9524                                 tp->link_config.advertising &=
9525                                                 ~(ADVERTISED_Pause |
9526                                                   ADVERTISED_Asym_Pause);
9527                                 tp->link_config.advertising |= newadv;
9528                         }
9529                 } else {
9530                         if (epause->rx_pause)
9531                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9532                         else
9533                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9534
9535                         if (epause->tx_pause)
9536                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9537                         else
9538                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9539
9540                         if (netif_running(dev))
9541                                 tg3_setup_flow_control(tp, 0, 0);
9542                 }
9543         } else {
9544                 int irq_sync = 0;
9545
9546                 if (netif_running(dev)) {
9547                         tg3_netif_stop(tp);
9548                         irq_sync = 1;
9549                 }
9550
9551                 tg3_full_lock(tp, irq_sync);
9552
9553                 if (epause->autoneg)
9554                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9555                 else
9556                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9557                 if (epause->rx_pause)
9558                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9559                 else
9560                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9561                 if (epause->tx_pause)
9562                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9563                 else
9564                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9565
9566                 if (netif_running(dev)) {
9567                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9568                         err = tg3_restart_hw(tp, 1);
9569                         if (!err)
9570                                 tg3_netif_start(tp);
9571                 }
9572
9573                 tg3_full_unlock(tp);
9574         }
9575
9576         return err;
9577 }
9578
9579 static u32 tg3_get_rx_csum(struct net_device *dev)
9580 {
9581         struct tg3 *tp = netdev_priv(dev);
9582         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9583 }
9584
9585 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9586 {
9587         struct tg3 *tp = netdev_priv(dev);
9588
9589         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9590                 if (data != 0)
9591                         return -EINVAL;
9592                 return 0;
9593         }
9594
9595         spin_lock_bh(&tp->lock);
9596         if (data)
9597                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9598         else
9599                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9600         spin_unlock_bh(&tp->lock);
9601
9602         return 0;
9603 }
9604
9605 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9606 {
9607         struct tg3 *tp = netdev_priv(dev);
9608
9609         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9610                 if (data != 0)
9611                         return -EINVAL;
9612                 return 0;
9613         }
9614
9615         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9616                 ethtool_op_set_tx_ipv6_csum(dev, data);
9617         else
9618                 ethtool_op_set_tx_csum(dev, data);
9619
9620         return 0;
9621 }
9622
9623 static int tg3_get_sset_count (struct net_device *dev, int sset)
9624 {
9625         switch (sset) {
9626         case ETH_SS_TEST:
9627                 return TG3_NUM_TEST;
9628         case ETH_SS_STATS:
9629                 return TG3_NUM_STATS;
9630         default:
9631                 return -EOPNOTSUPP;
9632         }
9633 }
9634
9635 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9636 {
9637         switch (stringset) {
9638         case ETH_SS_STATS:
9639                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9640                 break;
9641         case ETH_SS_TEST:
9642                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9643                 break;
9644         default:
9645                 WARN_ON(1);     /* we need a WARN() */
9646                 break;
9647         }
9648 }
9649
9650 static int tg3_phys_id(struct net_device *dev, u32 data)
9651 {
9652         struct tg3 *tp = netdev_priv(dev);
9653         int i;
9654
9655         if (!netif_running(tp->dev))
9656                 return -EAGAIN;
9657
9658         if (data == 0)
9659                 data = UINT_MAX / 2;
9660
9661         for (i = 0; i < (data * 2); i++) {
9662                 if ((i % 2) == 0)
9663                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9664                                            LED_CTRL_1000MBPS_ON |
9665                                            LED_CTRL_100MBPS_ON |
9666                                            LED_CTRL_10MBPS_ON |
9667                                            LED_CTRL_TRAFFIC_OVERRIDE |
9668                                            LED_CTRL_TRAFFIC_BLINK |
9669                                            LED_CTRL_TRAFFIC_LED);
9670
9671                 else
9672                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9673                                            LED_CTRL_TRAFFIC_OVERRIDE);
9674
9675                 if (msleep_interruptible(500))
9676                         break;
9677         }
9678         tw32(MAC_LED_CTRL, tp->led_ctrl);
9679         return 0;
9680 }
9681
9682 static void tg3_get_ethtool_stats (struct net_device *dev,
9683                                    struct ethtool_stats *estats, u64 *tmp_stats)
9684 {
9685         struct tg3 *tp = netdev_priv(dev);
9686         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9687 }
9688
9689 #define NVRAM_TEST_SIZE 0x100
9690 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9691 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9692 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9693 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9694 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9695
9696 static int tg3_test_nvram(struct tg3 *tp)
9697 {
9698         u32 csum, magic;
9699         __be32 *buf;
9700         int i, j, k, err = 0, size;
9701
9702         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9703                 return 0;
9704
9705         if (tg3_nvram_read(tp, 0, &magic) != 0)
9706                 return -EIO;
9707
9708         if (magic == TG3_EEPROM_MAGIC)
9709                 size = NVRAM_TEST_SIZE;
9710         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9711                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9712                     TG3_EEPROM_SB_FORMAT_1) {
9713                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9714                         case TG3_EEPROM_SB_REVISION_0:
9715                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9716                                 break;
9717                         case TG3_EEPROM_SB_REVISION_2:
9718                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9719                                 break;
9720                         case TG3_EEPROM_SB_REVISION_3:
9721                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9722                                 break;
9723                         default:
9724                                 return 0;
9725                         }
9726                 } else
9727                         return 0;
9728         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9729                 size = NVRAM_SELFBOOT_HW_SIZE;
9730         else
9731                 return -EIO;
9732
9733         buf = kmalloc(size, GFP_KERNEL);
9734         if (buf == NULL)
9735                 return -ENOMEM;
9736
9737         err = -EIO;
9738         for (i = 0, j = 0; i < size; i += 4, j++) {
9739                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9740                 if (err)
9741                         break;
9742         }
9743         if (i < size)
9744                 goto out;
9745
9746         /* Selfboot format */
9747         magic = be32_to_cpu(buf[0]);
9748         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9749             TG3_EEPROM_MAGIC_FW) {
9750                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9751
9752                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9753                     TG3_EEPROM_SB_REVISION_2) {
9754                         /* For rev 2, the csum doesn't include the MBA. */
9755                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9756                                 csum8 += buf8[i];
9757                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9758                                 csum8 += buf8[i];
9759                 } else {
9760                         for (i = 0; i < size; i++)
9761                                 csum8 += buf8[i];
9762                 }
9763
9764                 if (csum8 == 0) {
9765                         err = 0;
9766                         goto out;
9767                 }
9768
9769                 err = -EIO;
9770                 goto out;
9771         }
9772
9773         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9774             TG3_EEPROM_MAGIC_HW) {
9775                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9776                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9777                 u8 *buf8 = (u8 *) buf;
9778
9779                 /* Separate the parity bits and the data bytes.  */
9780                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9781                         if ((i == 0) || (i == 8)) {
9782                                 int l;
9783                                 u8 msk;
9784
9785                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9786                                         parity[k++] = buf8[i] & msk;
9787                                 i++;
9788                         }
9789                         else if (i == 16) {
9790                                 int l;
9791                                 u8 msk;
9792
9793                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9794                                         parity[k++] = buf8[i] & msk;
9795                                 i++;
9796
9797                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9798                                         parity[k++] = buf8[i] & msk;
9799                                 i++;
9800                         }
9801                         data[j++] = buf8[i];
9802                 }
9803
9804                 err = -EIO;
9805                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9806                         u8 hw8 = hweight8(data[i]);
9807
9808                         if ((hw8 & 0x1) && parity[i])
9809                                 goto out;
9810                         else if (!(hw8 & 0x1) && !parity[i])
9811                                 goto out;
9812                 }
9813                 err = 0;
9814                 goto out;
9815         }
9816
9817         /* Bootstrap checksum at offset 0x10 */
9818         csum = calc_crc((unsigned char *) buf, 0x10);
9819         if (csum != be32_to_cpu(buf[0x10/4]))
9820                 goto out;
9821
9822         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9823         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9824         if (csum != be32_to_cpu(buf[0xfc/4]))
9825                 goto out;
9826
9827         err = 0;
9828
9829 out:
9830         kfree(buf);
9831         return err;
9832 }
9833
9834 #define TG3_SERDES_TIMEOUT_SEC  2
9835 #define TG3_COPPER_TIMEOUT_SEC  6
9836
9837 static int tg3_test_link(struct tg3 *tp)
9838 {
9839         int i, max;
9840
9841         if (!netif_running(tp->dev))
9842                 return -ENODEV;
9843
9844         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9845                 max = TG3_SERDES_TIMEOUT_SEC;
9846         else
9847                 max = TG3_COPPER_TIMEOUT_SEC;
9848
9849         for (i = 0; i < max; i++) {
9850                 if (netif_carrier_ok(tp->dev))
9851                         return 0;
9852
9853                 if (msleep_interruptible(1000))
9854                         break;
9855         }
9856
9857         return -EIO;
9858 }
9859
9860 /* Only test the commonly used registers */
9861 static int tg3_test_registers(struct tg3 *tp)
9862 {
9863         int i, is_5705, is_5750;
9864         u32 offset, read_mask, write_mask, val, save_val, read_val;
9865         static struct {
9866                 u16 offset;
9867                 u16 flags;
9868 #define TG3_FL_5705     0x1
9869 #define TG3_FL_NOT_5705 0x2
9870 #define TG3_FL_NOT_5788 0x4
9871 #define TG3_FL_NOT_5750 0x8
9872                 u32 read_mask;
9873                 u32 write_mask;
9874         } reg_tbl[] = {
9875                 /* MAC Control Registers */
9876                 { MAC_MODE, TG3_FL_NOT_5705,
9877                         0x00000000, 0x00ef6f8c },
9878                 { MAC_MODE, TG3_FL_5705,
9879                         0x00000000, 0x01ef6b8c },
9880                 { MAC_STATUS, TG3_FL_NOT_5705,
9881                         0x03800107, 0x00000000 },
9882                 { MAC_STATUS, TG3_FL_5705,
9883                         0x03800100, 0x00000000 },
9884                 { MAC_ADDR_0_HIGH, 0x0000,
9885                         0x00000000, 0x0000ffff },
9886                 { MAC_ADDR_0_LOW, 0x0000,
9887                         0x00000000, 0xffffffff },
9888                 { MAC_RX_MTU_SIZE, 0x0000,
9889                         0x00000000, 0x0000ffff },
9890                 { MAC_TX_MODE, 0x0000,
9891                         0x00000000, 0x00000070 },
9892                 { MAC_TX_LENGTHS, 0x0000,
9893                         0x00000000, 0x00003fff },
9894                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9895                         0x00000000, 0x000007fc },
9896                 { MAC_RX_MODE, TG3_FL_5705,
9897                         0x00000000, 0x000007dc },
9898                 { MAC_HASH_REG_0, 0x0000,
9899                         0x00000000, 0xffffffff },
9900                 { MAC_HASH_REG_1, 0x0000,
9901                         0x00000000, 0xffffffff },
9902                 { MAC_HASH_REG_2, 0x0000,
9903                         0x00000000, 0xffffffff },
9904                 { MAC_HASH_REG_3, 0x0000,
9905                         0x00000000, 0xffffffff },
9906
9907                 /* Receive Data and Receive BD Initiator Control Registers. */
9908                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9909                         0x00000000, 0xffffffff },
9910                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9911                         0x00000000, 0xffffffff },
9912                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9913                         0x00000000, 0x00000003 },
9914                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9915                         0x00000000, 0xffffffff },
9916                 { RCVDBDI_STD_BD+0, 0x0000,
9917                         0x00000000, 0xffffffff },
9918                 { RCVDBDI_STD_BD+4, 0x0000,
9919                         0x00000000, 0xffffffff },
9920                 { RCVDBDI_STD_BD+8, 0x0000,
9921                         0x00000000, 0xffff0002 },
9922                 { RCVDBDI_STD_BD+0xc, 0x0000,
9923                         0x00000000, 0xffffffff },
9924
9925                 /* Receive BD Initiator Control Registers. */
9926                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9927                         0x00000000, 0xffffffff },
9928                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9929                         0x00000000, 0x000003ff },
9930                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9931                         0x00000000, 0xffffffff },
9932
9933                 /* Host Coalescing Control Registers. */
9934                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9935                         0x00000000, 0x00000004 },
9936                 { HOSTCC_MODE, TG3_FL_5705,
9937                         0x00000000, 0x000000f6 },
9938                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9939                         0x00000000, 0xffffffff },
9940                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9941                         0x00000000, 0x000003ff },
9942                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9943                         0x00000000, 0xffffffff },
9944                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9945                         0x00000000, 0x000003ff },
9946                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9947                         0x00000000, 0xffffffff },
9948                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9949                         0x00000000, 0x000000ff },
9950                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9951                         0x00000000, 0xffffffff },
9952                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9953                         0x00000000, 0x000000ff },
9954                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9955                         0x00000000, 0xffffffff },
9956                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9957                         0x00000000, 0xffffffff },
9958                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9959                         0x00000000, 0xffffffff },
9960                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9961                         0x00000000, 0x000000ff },
9962                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9963                         0x00000000, 0xffffffff },
9964                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9965                         0x00000000, 0x000000ff },
9966                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9967                         0x00000000, 0xffffffff },
9968                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9969                         0x00000000, 0xffffffff },
9970                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9971                         0x00000000, 0xffffffff },
9972                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9973                         0x00000000, 0xffffffff },
9974                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9975                         0x00000000, 0xffffffff },
9976                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9977                         0xffffffff, 0x00000000 },
9978                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9979                         0xffffffff, 0x00000000 },
9980
9981                 /* Buffer Manager Control Registers. */
9982                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9983                         0x00000000, 0x007fff80 },
9984                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9985                         0x00000000, 0x007fffff },
9986                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9987                         0x00000000, 0x0000003f },
9988                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9989                         0x00000000, 0x000001ff },
9990                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9991                         0x00000000, 0x000001ff },
9992                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9993                         0xffffffff, 0x00000000 },
9994                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9995                         0xffffffff, 0x00000000 },
9996
9997                 /* Mailbox Registers */
9998                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9999                         0x00000000, 0x000001ff },
10000                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10001                         0x00000000, 0x000001ff },
10002                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10003                         0x00000000, 0x000007ff },
10004                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10005                         0x00000000, 0x000001ff },
10006
10007                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10008         };
10009
10010         is_5705 = is_5750 = 0;
10011         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10012                 is_5705 = 1;
10013                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10014                         is_5750 = 1;
10015         }
10016
10017         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10018                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10019                         continue;
10020
10021                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10022                         continue;
10023
10024                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10025                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10026                         continue;
10027
10028                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10029                         continue;
10030
10031                 offset = (u32) reg_tbl[i].offset;
10032                 read_mask = reg_tbl[i].read_mask;
10033                 write_mask = reg_tbl[i].write_mask;
10034
10035                 /* Save the original register content */
10036                 save_val = tr32(offset);
10037
10038                 /* Determine the read-only value. */
10039                 read_val = save_val & read_mask;
10040
10041                 /* Write zero to the register, then make sure the read-only bits
10042                  * are not changed and the read/write bits are all zeros.
10043                  */
10044                 tw32(offset, 0);
10045
10046                 val = tr32(offset);
10047
10048                 /* Test the read-only and read/write bits. */
10049                 if (((val & read_mask) != read_val) || (val & write_mask))
10050                         goto out;
10051
10052                 /* Write ones to all the bits defined by RdMask and WrMask, then
10053                  * make sure the read-only bits are not changed and the
10054                  * read/write bits are all ones.
10055                  */
10056                 tw32(offset, read_mask | write_mask);
10057
10058                 val = tr32(offset);
10059
10060                 /* Test the read-only bits. */
10061                 if ((val & read_mask) != read_val)
10062                         goto out;
10063
10064                 /* Test the read/write bits. */
10065                 if ((val & write_mask) != write_mask)
10066                         goto out;
10067
10068                 tw32(offset, save_val);
10069         }
10070
10071         return 0;
10072
10073 out:
10074         if (netif_msg_hw(tp))
10075                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10076                        offset);
10077         tw32(offset, save_val);
10078         return -EIO;
10079 }
10080
10081 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10082 {
10083         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10084         int i;
10085         u32 j;
10086
10087         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10088                 for (j = 0; j < len; j += 4) {
10089                         u32 val;
10090
10091                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10092                         tg3_read_mem(tp, offset + j, &val);
10093                         if (val != test_pattern[i])
10094                                 return -EIO;
10095                 }
10096         }
10097         return 0;
10098 }
10099
10100 static int tg3_test_memory(struct tg3 *tp)
10101 {
10102         static struct mem_entry {
10103                 u32 offset;
10104                 u32 len;
10105         } mem_tbl_570x[] = {
10106                 { 0x00000000, 0x00b50},
10107                 { 0x00002000, 0x1c000},
10108                 { 0xffffffff, 0x00000}
10109         }, mem_tbl_5705[] = {
10110                 { 0x00000100, 0x0000c},
10111                 { 0x00000200, 0x00008},
10112                 { 0x00004000, 0x00800},
10113                 { 0x00006000, 0x01000},
10114                 { 0x00008000, 0x02000},
10115                 { 0x00010000, 0x0e000},
10116                 { 0xffffffff, 0x00000}
10117         }, mem_tbl_5755[] = {
10118                 { 0x00000200, 0x00008},
10119                 { 0x00004000, 0x00800},
10120                 { 0x00006000, 0x00800},
10121                 { 0x00008000, 0x02000},
10122                 { 0x00010000, 0x0c000},
10123                 { 0xffffffff, 0x00000}
10124         }, mem_tbl_5906[] = {
10125                 { 0x00000200, 0x00008},
10126                 { 0x00004000, 0x00400},
10127                 { 0x00006000, 0x00400},
10128                 { 0x00008000, 0x01000},
10129                 { 0x00010000, 0x01000},
10130                 { 0xffffffff, 0x00000}
10131         };
10132         struct mem_entry *mem_tbl;
10133         int err = 0;
10134         int i;
10135
10136         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10137                 mem_tbl = mem_tbl_5755;
10138         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10139                 mem_tbl = mem_tbl_5906;
10140         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10141                 mem_tbl = mem_tbl_5705;
10142         else
10143                 mem_tbl = mem_tbl_570x;
10144
10145         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10146                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10147                     mem_tbl[i].len)) != 0)
10148                         break;
10149         }
10150
10151         return err;
10152 }
10153
10154 #define TG3_MAC_LOOPBACK        0
10155 #define TG3_PHY_LOOPBACK        1
10156
10157 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10158 {
10159         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10160         u32 desc_idx, coal_now;
10161         struct sk_buff *skb, *rx_skb;
10162         u8 *tx_data;
10163         dma_addr_t map;
10164         int num_pkts, tx_len, rx_len, i, err;
10165         struct tg3_rx_buffer_desc *desc;
10166         struct tg3_napi *tnapi, *rnapi;
10167         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10168
10169         tnapi = &tp->napi[0];
10170         rnapi = &tp->napi[0];
10171         coal_now = tnapi->coal_now | rnapi->coal_now;
10172
10173         if (loopback_mode == TG3_MAC_LOOPBACK) {
10174                 /* HW errata - mac loopback fails in some cases on 5780.
10175                  * Normal traffic and PHY loopback are not affected by
10176                  * errata.
10177                  */
10178                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10179                         return 0;
10180
10181                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10182                            MAC_MODE_PORT_INT_LPBACK;
10183                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10184                         mac_mode |= MAC_MODE_LINK_POLARITY;
10185                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10186                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10187                 else
10188                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10189                 tw32(MAC_MODE, mac_mode);
10190         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10191                 u32 val;
10192
10193                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10194                         tg3_phy_fet_toggle_apd(tp, false);
10195                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10196                 } else
10197                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10198
10199                 tg3_phy_toggle_automdix(tp, 0);
10200
10201                 tg3_writephy(tp, MII_BMCR, val);
10202                 udelay(40);
10203
10204                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10205                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10206                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10207                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10208                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10209                 } else
10210                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10211
10212                 /* reset to prevent losing 1st rx packet intermittently */
10213                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10214                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10215                         udelay(10);
10216                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10217                 }
10218                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10219                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10220                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10221                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10222                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10223                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10224                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10225                 }
10226                 tw32(MAC_MODE, mac_mode);
10227         }
10228         else
10229                 return -EINVAL;
10230
10231         err = -EIO;
10232
10233         tx_len = 1514;
10234         skb = netdev_alloc_skb(tp->dev, tx_len);
10235         if (!skb)
10236                 return -ENOMEM;
10237
10238         tx_data = skb_put(skb, tx_len);
10239         memcpy(tx_data, tp->dev->dev_addr, 6);
10240         memset(tx_data + 6, 0x0, 8);
10241
10242         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10243
10244         for (i = 14; i < tx_len; i++)
10245                 tx_data[i] = (u8) (i & 0xff);
10246
10247         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10248
10249         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10250                rnapi->coal_now);
10251
10252         udelay(10);
10253
10254         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10255
10256         num_pkts = 0;
10257
10258         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10259
10260         tnapi->tx_prod++;
10261         num_pkts++;
10262
10263         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10264         tr32_mailbox(tnapi->prodmbox);
10265
10266         udelay(10);
10267
10268         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
10269         for (i = 0; i < 25; i++) {
10270                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10271                        coal_now);
10272
10273                 udelay(10);
10274
10275                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10276                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10277                 if ((tx_idx == tnapi->tx_prod) &&
10278                     (rx_idx == (rx_start_idx + num_pkts)))
10279                         break;
10280         }
10281
10282         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10283         dev_kfree_skb(skb);
10284
10285         if (tx_idx != tnapi->tx_prod)
10286                 goto out;
10287
10288         if (rx_idx != rx_start_idx + num_pkts)
10289                 goto out;
10290
10291         desc = &rnapi->rx_rcb[rx_start_idx];
10292         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10293         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10294         if (opaque_key != RXD_OPAQUE_RING_STD)
10295                 goto out;
10296
10297         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10298             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10299                 goto out;
10300
10301         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10302         if (rx_len != tx_len)
10303                 goto out;
10304
10305         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10306
10307         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10308         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10309
10310         for (i = 14; i < tx_len; i++) {
10311                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10312                         goto out;
10313         }
10314         err = 0;
10315
10316         /* tg3_free_rings will unmap and free the rx_skb */
10317 out:
10318         return err;
10319 }
10320
10321 #define TG3_MAC_LOOPBACK_FAILED         1
10322 #define TG3_PHY_LOOPBACK_FAILED         2
10323 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10324                                          TG3_PHY_LOOPBACK_FAILED)
10325
10326 static int tg3_test_loopback(struct tg3 *tp)
10327 {
10328         int err = 0;
10329         u32 cpmuctrl = 0;
10330
10331         if (!netif_running(tp->dev))
10332                 return TG3_LOOPBACK_FAILED;
10333
10334         err = tg3_reset_hw(tp, 1);
10335         if (err)
10336                 return TG3_LOOPBACK_FAILED;
10337
10338         /* Turn off gphy autopowerdown. */
10339         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10340                 tg3_phy_toggle_apd(tp, false);
10341
10342         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10343                 int i;
10344                 u32 status;
10345
10346                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10347
10348                 /* Wait for up to 40 microseconds to acquire lock. */
10349                 for (i = 0; i < 4; i++) {
10350                         status = tr32(TG3_CPMU_MUTEX_GNT);
10351                         if (status == CPMU_MUTEX_GNT_DRIVER)
10352                                 break;
10353                         udelay(10);
10354                 }
10355
10356                 if (status != CPMU_MUTEX_GNT_DRIVER)
10357                         return TG3_LOOPBACK_FAILED;
10358
10359                 /* Turn off link-based power management. */
10360                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10361                 tw32(TG3_CPMU_CTRL,
10362                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10363                                   CPMU_CTRL_LINK_AWARE_MODE));
10364         }
10365
10366         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10367                 err |= TG3_MAC_LOOPBACK_FAILED;
10368
10369         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10370                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10371
10372                 /* Release the mutex */
10373                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10374         }
10375
10376         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10377             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10378                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10379                         err |= TG3_PHY_LOOPBACK_FAILED;
10380         }
10381
10382         /* Re-enable gphy autopowerdown. */
10383         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10384                 tg3_phy_toggle_apd(tp, true);
10385
10386         return err;
10387 }
10388
10389 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10390                           u64 *data)
10391 {
10392         struct tg3 *tp = netdev_priv(dev);
10393
10394         if (tp->link_config.phy_is_low_power)
10395                 tg3_set_power_state(tp, PCI_D0);
10396
10397         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10398
10399         if (tg3_test_nvram(tp) != 0) {
10400                 etest->flags |= ETH_TEST_FL_FAILED;
10401                 data[0] = 1;
10402         }
10403         if (tg3_test_link(tp) != 0) {
10404                 etest->flags |= ETH_TEST_FL_FAILED;
10405                 data[1] = 1;
10406         }
10407         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10408                 int err, err2 = 0, irq_sync = 0;
10409
10410                 if (netif_running(dev)) {
10411                         tg3_phy_stop(tp);
10412                         tg3_netif_stop(tp);
10413                         irq_sync = 1;
10414                 }
10415
10416                 tg3_full_lock(tp, irq_sync);
10417
10418                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10419                 err = tg3_nvram_lock(tp);
10420                 tg3_halt_cpu(tp, RX_CPU_BASE);
10421                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10422                         tg3_halt_cpu(tp, TX_CPU_BASE);
10423                 if (!err)
10424                         tg3_nvram_unlock(tp);
10425
10426                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10427                         tg3_phy_reset(tp);
10428
10429                 if (tg3_test_registers(tp) != 0) {
10430                         etest->flags |= ETH_TEST_FL_FAILED;
10431                         data[2] = 1;
10432                 }
10433                 if (tg3_test_memory(tp) != 0) {
10434                         etest->flags |= ETH_TEST_FL_FAILED;
10435                         data[3] = 1;
10436                 }
10437                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10438                         etest->flags |= ETH_TEST_FL_FAILED;
10439
10440                 tg3_full_unlock(tp);
10441
10442                 if (tg3_test_interrupt(tp) != 0) {
10443                         etest->flags |= ETH_TEST_FL_FAILED;
10444                         data[5] = 1;
10445                 }
10446
10447                 tg3_full_lock(tp, 0);
10448
10449                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10450                 if (netif_running(dev)) {
10451                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10452                         err2 = tg3_restart_hw(tp, 1);
10453                         if (!err2)
10454                                 tg3_netif_start(tp);
10455                 }
10456
10457                 tg3_full_unlock(tp);
10458
10459                 if (irq_sync && !err2)
10460                         tg3_phy_start(tp);
10461         }
10462         if (tp->link_config.phy_is_low_power)
10463                 tg3_set_power_state(tp, PCI_D3hot);
10464
10465 }
10466
10467 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10468 {
10469         struct mii_ioctl_data *data = if_mii(ifr);
10470         struct tg3 *tp = netdev_priv(dev);
10471         int err;
10472
10473         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10474                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10475                         return -EAGAIN;
10476                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10477         }
10478
10479         switch(cmd) {
10480         case SIOCGMIIPHY:
10481                 data->phy_id = PHY_ADDR;
10482
10483                 /* fallthru */
10484         case SIOCGMIIREG: {
10485                 u32 mii_regval;
10486
10487                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10488                         break;                  /* We have no PHY */
10489
10490                 if (tp->link_config.phy_is_low_power)
10491                         return -EAGAIN;
10492
10493                 spin_lock_bh(&tp->lock);
10494                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10495                 spin_unlock_bh(&tp->lock);
10496
10497                 data->val_out = mii_regval;
10498
10499                 return err;
10500         }
10501
10502         case SIOCSMIIREG:
10503                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10504                         break;                  /* We have no PHY */
10505
10506                 if (!capable(CAP_NET_ADMIN))
10507                         return -EPERM;
10508
10509                 if (tp->link_config.phy_is_low_power)
10510                         return -EAGAIN;
10511
10512                 spin_lock_bh(&tp->lock);
10513                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10514                 spin_unlock_bh(&tp->lock);
10515
10516                 return err;
10517
10518         default:
10519                 /* do nothing */
10520                 break;
10521         }
10522         return -EOPNOTSUPP;
10523 }
10524
10525 #if TG3_VLAN_TAG_USED
10526 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10527 {
10528         struct tg3 *tp = netdev_priv(dev);
10529
10530         if (!netif_running(dev)) {
10531                 tp->vlgrp = grp;
10532                 return;
10533         }
10534
10535         tg3_netif_stop(tp);
10536
10537         tg3_full_lock(tp, 0);
10538
10539         tp->vlgrp = grp;
10540
10541         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10542         __tg3_set_rx_mode(dev);
10543
10544         tg3_netif_start(tp);
10545
10546         tg3_full_unlock(tp);
10547 }
10548 #endif
10549
10550 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10551 {
10552         struct tg3 *tp = netdev_priv(dev);
10553
10554         memcpy(ec, &tp->coal, sizeof(*ec));
10555         return 0;
10556 }
10557
10558 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10559 {
10560         struct tg3 *tp = netdev_priv(dev);
10561         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10562         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10563
10564         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10565                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10566                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10567                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10568                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10569         }
10570
10571         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10572             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10573             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10574             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10575             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10576             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10577             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10578             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10579             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10580             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10581                 return -EINVAL;
10582
10583         /* No rx interrupts will be generated if both are zero */
10584         if ((ec->rx_coalesce_usecs == 0) &&
10585             (ec->rx_max_coalesced_frames == 0))
10586                 return -EINVAL;
10587
10588         /* No tx interrupts will be generated if both are zero */
10589         if ((ec->tx_coalesce_usecs == 0) &&
10590             (ec->tx_max_coalesced_frames == 0))
10591                 return -EINVAL;
10592
10593         /* Only copy relevant parameters, ignore all others. */
10594         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10595         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10596         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10597         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10598         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10599         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10600         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10601         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10602         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10603
10604         if (netif_running(dev)) {
10605                 tg3_full_lock(tp, 0);
10606                 __tg3_set_coalesce(tp, &tp->coal);
10607                 tg3_full_unlock(tp);
10608         }
10609         return 0;
10610 }
10611
10612 static const struct ethtool_ops tg3_ethtool_ops = {
10613         .get_settings           = tg3_get_settings,
10614         .set_settings           = tg3_set_settings,
10615         .get_drvinfo            = tg3_get_drvinfo,
10616         .get_regs_len           = tg3_get_regs_len,
10617         .get_regs               = tg3_get_regs,
10618         .get_wol                = tg3_get_wol,
10619         .set_wol                = tg3_set_wol,
10620         .get_msglevel           = tg3_get_msglevel,
10621         .set_msglevel           = tg3_set_msglevel,
10622         .nway_reset             = tg3_nway_reset,
10623         .get_link               = ethtool_op_get_link,
10624         .get_eeprom_len         = tg3_get_eeprom_len,
10625         .get_eeprom             = tg3_get_eeprom,
10626         .set_eeprom             = tg3_set_eeprom,
10627         .get_ringparam          = tg3_get_ringparam,
10628         .set_ringparam          = tg3_set_ringparam,
10629         .get_pauseparam         = tg3_get_pauseparam,
10630         .set_pauseparam         = tg3_set_pauseparam,
10631         .get_rx_csum            = tg3_get_rx_csum,
10632         .set_rx_csum            = tg3_set_rx_csum,
10633         .set_tx_csum            = tg3_set_tx_csum,
10634         .set_sg                 = ethtool_op_set_sg,
10635         .set_tso                = tg3_set_tso,
10636         .self_test              = tg3_self_test,
10637         .get_strings            = tg3_get_strings,
10638         .phys_id                = tg3_phys_id,
10639         .get_ethtool_stats      = tg3_get_ethtool_stats,
10640         .get_coalesce           = tg3_get_coalesce,
10641         .set_coalesce           = tg3_set_coalesce,
10642         .get_sset_count         = tg3_get_sset_count,
10643 };
10644
10645 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10646 {
10647         u32 cursize, val, magic;
10648
10649         tp->nvram_size = EEPROM_CHIP_SIZE;
10650
10651         if (tg3_nvram_read(tp, 0, &magic) != 0)
10652                 return;
10653
10654         if ((magic != TG3_EEPROM_MAGIC) &&
10655             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10656             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10657                 return;
10658
10659         /*
10660          * Size the chip by reading offsets at increasing powers of two.
10661          * When we encounter our validation signature, we know the addressing
10662          * has wrapped around, and thus have our chip size.
10663          */
10664         cursize = 0x10;
10665
10666         while (cursize < tp->nvram_size) {
10667                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10668                         return;
10669
10670                 if (val == magic)
10671                         break;
10672
10673                 cursize <<= 1;
10674         }
10675
10676         tp->nvram_size = cursize;
10677 }
10678
10679 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10680 {
10681         u32 val;
10682
10683         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10684             tg3_nvram_read(tp, 0, &val) != 0)
10685                 return;
10686
10687         /* Selfboot format */
10688         if (val != TG3_EEPROM_MAGIC) {
10689                 tg3_get_eeprom_size(tp);
10690                 return;
10691         }
10692
10693         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10694                 if (val != 0) {
10695                         /* This is confusing.  We want to operate on the
10696                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10697                          * call will read from NVRAM and byteswap the data
10698                          * according to the byteswapping settings for all
10699                          * other register accesses.  This ensures the data we
10700                          * want will always reside in the lower 16-bits.
10701                          * However, the data in NVRAM is in LE format, which
10702                          * means the data from the NVRAM read will always be
10703                          * opposite the endianness of the CPU.  The 16-bit
10704                          * byteswap then brings the data to CPU endianness.
10705                          */
10706                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10707                         return;
10708                 }
10709         }
10710         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10711 }
10712
10713 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10714 {
10715         u32 nvcfg1;
10716
10717         nvcfg1 = tr32(NVRAM_CFG1);
10718         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10719                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10720         } else {
10721                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10722                 tw32(NVRAM_CFG1, nvcfg1);
10723         }
10724
10725         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10726             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10727                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10728                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10729                         tp->nvram_jedecnum = JEDEC_ATMEL;
10730                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10731                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10732                         break;
10733                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10734                         tp->nvram_jedecnum = JEDEC_ATMEL;
10735                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10736                         break;
10737                 case FLASH_VENDOR_ATMEL_EEPROM:
10738                         tp->nvram_jedecnum = JEDEC_ATMEL;
10739                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10740                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10741                         break;
10742                 case FLASH_VENDOR_ST:
10743                         tp->nvram_jedecnum = JEDEC_ST;
10744                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10745                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10746                         break;
10747                 case FLASH_VENDOR_SAIFUN:
10748                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10749                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10750                         break;
10751                 case FLASH_VENDOR_SST_SMALL:
10752                 case FLASH_VENDOR_SST_LARGE:
10753                         tp->nvram_jedecnum = JEDEC_SST;
10754                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10755                         break;
10756                 }
10757         } else {
10758                 tp->nvram_jedecnum = JEDEC_ATMEL;
10759                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10760                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10761         }
10762 }
10763
10764 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10765 {
10766         u32 nvcfg1;
10767
10768         nvcfg1 = tr32(NVRAM_CFG1);
10769
10770         /* NVRAM protection for TPM */
10771         if (nvcfg1 & (1 << 27))
10772                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10773
10774         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10775         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10776         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10777                 tp->nvram_jedecnum = JEDEC_ATMEL;
10778                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10779                 break;
10780         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10781                 tp->nvram_jedecnum = JEDEC_ATMEL;
10782                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10783                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10784                 break;
10785         case FLASH_5752VENDOR_ST_M45PE10:
10786         case FLASH_5752VENDOR_ST_M45PE20:
10787         case FLASH_5752VENDOR_ST_M45PE40:
10788                 tp->nvram_jedecnum = JEDEC_ST;
10789                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10790                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10791                 break;
10792         }
10793
10794         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10795                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10796                 case FLASH_5752PAGE_SIZE_256:
10797                         tp->nvram_pagesize = 256;
10798                         break;
10799                 case FLASH_5752PAGE_SIZE_512:
10800                         tp->nvram_pagesize = 512;
10801                         break;
10802                 case FLASH_5752PAGE_SIZE_1K:
10803                         tp->nvram_pagesize = 1024;
10804                         break;
10805                 case FLASH_5752PAGE_SIZE_2K:
10806                         tp->nvram_pagesize = 2048;
10807                         break;
10808                 case FLASH_5752PAGE_SIZE_4K:
10809                         tp->nvram_pagesize = 4096;
10810                         break;
10811                 case FLASH_5752PAGE_SIZE_264:
10812                         tp->nvram_pagesize = 264;
10813                         break;
10814                 }
10815         } else {
10816                 /* For eeprom, set pagesize to maximum eeprom size */
10817                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10818
10819                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10820                 tw32(NVRAM_CFG1, nvcfg1);
10821         }
10822 }
10823
10824 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10825 {
10826         u32 nvcfg1, protect = 0;
10827
10828         nvcfg1 = tr32(NVRAM_CFG1);
10829
10830         /* NVRAM protection for TPM */
10831         if (nvcfg1 & (1 << 27)) {
10832                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10833                 protect = 1;
10834         }
10835
10836         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10837         switch (nvcfg1) {
10838         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10839         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10840         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10841         case FLASH_5755VENDOR_ATMEL_FLASH_5:
10842                 tp->nvram_jedecnum = JEDEC_ATMEL;
10843                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10844                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10845                 tp->nvram_pagesize = 264;
10846                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10847                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10848                         tp->nvram_size = (protect ? 0x3e200 :
10849                                           TG3_NVRAM_SIZE_512KB);
10850                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10851                         tp->nvram_size = (protect ? 0x1f200 :
10852                                           TG3_NVRAM_SIZE_256KB);
10853                 else
10854                         tp->nvram_size = (protect ? 0x1f200 :
10855                                           TG3_NVRAM_SIZE_128KB);
10856                 break;
10857         case FLASH_5752VENDOR_ST_M45PE10:
10858         case FLASH_5752VENDOR_ST_M45PE20:
10859         case FLASH_5752VENDOR_ST_M45PE40:
10860                 tp->nvram_jedecnum = JEDEC_ST;
10861                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10862                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10863                 tp->nvram_pagesize = 256;
10864                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10865                         tp->nvram_size = (protect ?
10866                                           TG3_NVRAM_SIZE_64KB :
10867                                           TG3_NVRAM_SIZE_128KB);
10868                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10869                         tp->nvram_size = (protect ?
10870                                           TG3_NVRAM_SIZE_64KB :
10871                                           TG3_NVRAM_SIZE_256KB);
10872                 else
10873                         tp->nvram_size = (protect ?
10874                                           TG3_NVRAM_SIZE_128KB :
10875                                           TG3_NVRAM_SIZE_512KB);
10876                 break;
10877         }
10878 }
10879
10880 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10881 {
10882         u32 nvcfg1;
10883
10884         nvcfg1 = tr32(NVRAM_CFG1);
10885
10886         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10887         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10888         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10889         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10890         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10891                 tp->nvram_jedecnum = JEDEC_ATMEL;
10892                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10893                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10894
10895                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10896                 tw32(NVRAM_CFG1, nvcfg1);
10897                 break;
10898         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10899         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10900         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10901         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10902                 tp->nvram_jedecnum = JEDEC_ATMEL;
10903                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10904                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10905                 tp->nvram_pagesize = 264;
10906                 break;
10907         case FLASH_5752VENDOR_ST_M45PE10:
10908         case FLASH_5752VENDOR_ST_M45PE20:
10909         case FLASH_5752VENDOR_ST_M45PE40:
10910                 tp->nvram_jedecnum = JEDEC_ST;
10911                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10912                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10913                 tp->nvram_pagesize = 256;
10914                 break;
10915         }
10916 }
10917
10918 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10919 {
10920         u32 nvcfg1, protect = 0;
10921
10922         nvcfg1 = tr32(NVRAM_CFG1);
10923
10924         /* NVRAM protection for TPM */
10925         if (nvcfg1 & (1 << 27)) {
10926                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10927                 protect = 1;
10928         }
10929
10930         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10931         switch (nvcfg1) {
10932         case FLASH_5761VENDOR_ATMEL_ADB021D:
10933         case FLASH_5761VENDOR_ATMEL_ADB041D:
10934         case FLASH_5761VENDOR_ATMEL_ADB081D:
10935         case FLASH_5761VENDOR_ATMEL_ADB161D:
10936         case FLASH_5761VENDOR_ATMEL_MDB021D:
10937         case FLASH_5761VENDOR_ATMEL_MDB041D:
10938         case FLASH_5761VENDOR_ATMEL_MDB081D:
10939         case FLASH_5761VENDOR_ATMEL_MDB161D:
10940                 tp->nvram_jedecnum = JEDEC_ATMEL;
10941                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10942                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10943                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10944                 tp->nvram_pagesize = 256;
10945                 break;
10946         case FLASH_5761VENDOR_ST_A_M45PE20:
10947         case FLASH_5761VENDOR_ST_A_M45PE40:
10948         case FLASH_5761VENDOR_ST_A_M45PE80:
10949         case FLASH_5761VENDOR_ST_A_M45PE16:
10950         case FLASH_5761VENDOR_ST_M_M45PE20:
10951         case FLASH_5761VENDOR_ST_M_M45PE40:
10952         case FLASH_5761VENDOR_ST_M_M45PE80:
10953         case FLASH_5761VENDOR_ST_M_M45PE16:
10954                 tp->nvram_jedecnum = JEDEC_ST;
10955                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10956                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10957                 tp->nvram_pagesize = 256;
10958                 break;
10959         }
10960
10961         if (protect) {
10962                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10963         } else {
10964                 switch (nvcfg1) {
10965                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10966                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10967                 case FLASH_5761VENDOR_ST_A_M45PE16:
10968                 case FLASH_5761VENDOR_ST_M_M45PE16:
10969                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10970                         break;
10971                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10972                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10973                 case FLASH_5761VENDOR_ST_A_M45PE80:
10974                 case FLASH_5761VENDOR_ST_M_M45PE80:
10975                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10976                         break;
10977                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10978                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10979                 case FLASH_5761VENDOR_ST_A_M45PE40:
10980                 case FLASH_5761VENDOR_ST_M_M45PE40:
10981                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10982                         break;
10983                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10984                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10985                 case FLASH_5761VENDOR_ST_A_M45PE20:
10986                 case FLASH_5761VENDOR_ST_M_M45PE20:
10987                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10988                         break;
10989                 }
10990         }
10991 }
10992
10993 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10994 {
10995         tp->nvram_jedecnum = JEDEC_ATMEL;
10996         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10997         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10998 }
10999
11000 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11001 {
11002         u32 nvcfg1;
11003
11004         nvcfg1 = tr32(NVRAM_CFG1);
11005
11006         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11007         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11008         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11009                 tp->nvram_jedecnum = JEDEC_ATMEL;
11010                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11011                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11012
11013                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11014                 tw32(NVRAM_CFG1, nvcfg1);
11015                 return;
11016         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11017         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11018         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11019         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11020         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11021         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11022         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11023                 tp->nvram_jedecnum = JEDEC_ATMEL;
11024                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11025                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11026
11027                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11028                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11029                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11030                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11031                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11032                         break;
11033                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11034                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11035                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11036                         break;
11037                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11038                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11039                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11040                         break;
11041                 }
11042                 break;
11043         case FLASH_5752VENDOR_ST_M45PE10:
11044         case FLASH_5752VENDOR_ST_M45PE20:
11045         case FLASH_5752VENDOR_ST_M45PE40:
11046                 tp->nvram_jedecnum = JEDEC_ST;
11047                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11048                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11049
11050                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11051                 case FLASH_5752VENDOR_ST_M45PE10:
11052                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11053                         break;
11054                 case FLASH_5752VENDOR_ST_M45PE20:
11055                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11056                         break;
11057                 case FLASH_5752VENDOR_ST_M45PE40:
11058                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11059                         break;
11060                 }
11061                 break;
11062         default:
11063                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11064                 return;
11065         }
11066
11067         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11068         case FLASH_5752PAGE_SIZE_256:
11069                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11070                 tp->nvram_pagesize = 256;
11071                 break;
11072         case FLASH_5752PAGE_SIZE_512:
11073                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11074                 tp->nvram_pagesize = 512;
11075                 break;
11076         case FLASH_5752PAGE_SIZE_1K:
11077                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11078                 tp->nvram_pagesize = 1024;
11079                 break;
11080         case FLASH_5752PAGE_SIZE_2K:
11081                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11082                 tp->nvram_pagesize = 2048;
11083                 break;
11084         case FLASH_5752PAGE_SIZE_4K:
11085                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11086                 tp->nvram_pagesize = 4096;
11087                 break;
11088         case FLASH_5752PAGE_SIZE_264:
11089                 tp->nvram_pagesize = 264;
11090                 break;
11091         case FLASH_5752PAGE_SIZE_528:
11092                 tp->nvram_pagesize = 528;
11093                 break;
11094         }
11095 }
11096
11097 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11098 static void __devinit tg3_nvram_init(struct tg3 *tp)
11099 {
11100         tw32_f(GRC_EEPROM_ADDR,
11101              (EEPROM_ADDR_FSM_RESET |
11102               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11103                EEPROM_ADDR_CLKPERD_SHIFT)));
11104
11105         msleep(1);
11106
11107         /* Enable seeprom accesses. */
11108         tw32_f(GRC_LOCAL_CTRL,
11109              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11110         udelay(100);
11111
11112         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11113             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11114                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11115
11116                 if (tg3_nvram_lock(tp)) {
11117                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11118                                "tg3_nvram_init failed.\n", tp->dev->name);
11119                         return;
11120                 }
11121                 tg3_enable_nvram_access(tp);
11122
11123                 tp->nvram_size = 0;
11124
11125                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11126                         tg3_get_5752_nvram_info(tp);
11127                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11128                         tg3_get_5755_nvram_info(tp);
11129                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11130                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11131                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11132                         tg3_get_5787_nvram_info(tp);
11133                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11134                         tg3_get_5761_nvram_info(tp);
11135                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11136                         tg3_get_5906_nvram_info(tp);
11137                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11138                         tg3_get_57780_nvram_info(tp);
11139                 else
11140                         tg3_get_nvram_info(tp);
11141
11142                 if (tp->nvram_size == 0)
11143                         tg3_get_nvram_size(tp);
11144
11145                 tg3_disable_nvram_access(tp);
11146                 tg3_nvram_unlock(tp);
11147
11148         } else {
11149                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11150
11151                 tg3_get_eeprom_size(tp);
11152         }
11153 }
11154
11155 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11156                                     u32 offset, u32 len, u8 *buf)
11157 {
11158         int i, j, rc = 0;
11159         u32 val;
11160
11161         for (i = 0; i < len; i += 4) {
11162                 u32 addr;
11163                 __be32 data;
11164
11165                 addr = offset + i;
11166
11167                 memcpy(&data, buf + i, 4);
11168
11169                 /*
11170                  * The SEEPROM interface expects the data to always be opposite
11171                  * the native endian format.  We accomplish this by reversing
11172                  * all the operations that would have been performed on the
11173                  * data from a call to tg3_nvram_read_be32().
11174                  */
11175                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11176
11177                 val = tr32(GRC_EEPROM_ADDR);
11178                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11179
11180                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11181                         EEPROM_ADDR_READ);
11182                 tw32(GRC_EEPROM_ADDR, val |
11183                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11184                         (addr & EEPROM_ADDR_ADDR_MASK) |
11185                         EEPROM_ADDR_START |
11186                         EEPROM_ADDR_WRITE);
11187
11188                 for (j = 0; j < 1000; j++) {
11189                         val = tr32(GRC_EEPROM_ADDR);
11190
11191                         if (val & EEPROM_ADDR_COMPLETE)
11192                                 break;
11193                         msleep(1);
11194                 }
11195                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11196                         rc = -EBUSY;
11197                         break;
11198                 }
11199         }
11200
11201         return rc;
11202 }
11203
11204 /* offset and length are dword aligned */
11205 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11206                 u8 *buf)
11207 {
11208         int ret = 0;
11209         u32 pagesize = tp->nvram_pagesize;
11210         u32 pagemask = pagesize - 1;
11211         u32 nvram_cmd;
11212         u8 *tmp;
11213
11214         tmp = kmalloc(pagesize, GFP_KERNEL);
11215         if (tmp == NULL)
11216                 return -ENOMEM;
11217
11218         while (len) {
11219                 int j;
11220                 u32 phy_addr, page_off, size;
11221
11222                 phy_addr = offset & ~pagemask;
11223
11224                 for (j = 0; j < pagesize; j += 4) {
11225                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11226                                                   (__be32 *) (tmp + j));
11227                         if (ret)
11228                                 break;
11229                 }
11230                 if (ret)
11231                         break;
11232
11233                 page_off = offset & pagemask;
11234                 size = pagesize;
11235                 if (len < size)
11236                         size = len;
11237
11238                 len -= size;
11239
11240                 memcpy(tmp + page_off, buf, size);
11241
11242                 offset = offset + (pagesize - page_off);
11243
11244                 tg3_enable_nvram_access(tp);
11245
11246                 /*
11247                  * Before we can erase the flash page, we need
11248                  * to issue a special "write enable" command.
11249                  */
11250                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11251
11252                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11253                         break;
11254
11255                 /* Erase the target page */
11256                 tw32(NVRAM_ADDR, phy_addr);
11257
11258                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11259                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11260
11261                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11262                         break;
11263
11264                 /* Issue another write enable to start the write. */
11265                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11266
11267                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11268                         break;
11269
11270                 for (j = 0; j < pagesize; j += 4) {
11271                         __be32 data;
11272
11273                         data = *((__be32 *) (tmp + j));
11274
11275                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11276
11277                         tw32(NVRAM_ADDR, phy_addr + j);
11278
11279                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11280                                 NVRAM_CMD_WR;
11281
11282                         if (j == 0)
11283                                 nvram_cmd |= NVRAM_CMD_FIRST;
11284                         else if (j == (pagesize - 4))
11285                                 nvram_cmd |= NVRAM_CMD_LAST;
11286
11287                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11288                                 break;
11289                 }
11290                 if (ret)
11291                         break;
11292         }
11293
11294         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11295         tg3_nvram_exec_cmd(tp, nvram_cmd);
11296
11297         kfree(tmp);
11298
11299         return ret;
11300 }
11301
11302 /* offset and length are dword aligned */
11303 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11304                 u8 *buf)
11305 {
11306         int i, ret = 0;
11307
11308         for (i = 0; i < len; i += 4, offset += 4) {
11309                 u32 page_off, phy_addr, nvram_cmd;
11310                 __be32 data;
11311
11312                 memcpy(&data, buf + i, 4);
11313                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11314
11315                 page_off = offset % tp->nvram_pagesize;
11316
11317                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11318
11319                 tw32(NVRAM_ADDR, phy_addr);
11320
11321                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11322
11323                 if ((page_off == 0) || (i == 0))
11324                         nvram_cmd |= NVRAM_CMD_FIRST;
11325                 if (page_off == (tp->nvram_pagesize - 4))
11326                         nvram_cmd |= NVRAM_CMD_LAST;
11327
11328                 if (i == (len - 4))
11329                         nvram_cmd |= NVRAM_CMD_LAST;
11330
11331                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11332                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11333                     (tp->nvram_jedecnum == JEDEC_ST) &&
11334                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11335
11336                         if ((ret = tg3_nvram_exec_cmd(tp,
11337                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11338                                 NVRAM_CMD_DONE)))
11339
11340                                 break;
11341                 }
11342                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11343                         /* We always do complete word writes to eeprom. */
11344                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11345                 }
11346
11347                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11348                         break;
11349         }
11350         return ret;
11351 }
11352
11353 /* offset and length are dword aligned */
11354 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11355 {
11356         int ret;
11357
11358         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11359                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11360                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11361                 udelay(40);
11362         }
11363
11364         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11365                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11366         }
11367         else {
11368                 u32 grc_mode;
11369
11370                 ret = tg3_nvram_lock(tp);
11371                 if (ret)
11372                         return ret;
11373
11374                 tg3_enable_nvram_access(tp);
11375                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11376                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11377                         tw32(NVRAM_WRITE1, 0x406);
11378
11379                 grc_mode = tr32(GRC_MODE);
11380                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11381
11382                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11383                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11384
11385                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11386                                 buf);
11387                 }
11388                 else {
11389                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11390                                 buf);
11391                 }
11392
11393                 grc_mode = tr32(GRC_MODE);
11394                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11395
11396                 tg3_disable_nvram_access(tp);
11397                 tg3_nvram_unlock(tp);
11398         }
11399
11400         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11401                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11402                 udelay(40);
11403         }
11404
11405         return ret;
11406 }
11407
11408 struct subsys_tbl_ent {
11409         u16 subsys_vendor, subsys_devid;
11410         u32 phy_id;
11411 };
11412
11413 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11414         /* Broadcom boards. */
11415         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11416         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11417         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11418         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11419         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11420         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11421         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11422         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11423         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11424         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11425         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11426
11427         /* 3com boards. */
11428         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11429         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11430         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11431         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11432         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11433
11434         /* DELL boards. */
11435         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11436         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11437         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11438         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11439
11440         /* Compaq boards. */
11441         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11442         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11443         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11444         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11445         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11446
11447         /* IBM boards. */
11448         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11449 };
11450
11451 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11452 {
11453         int i;
11454
11455         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11456                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11457                      tp->pdev->subsystem_vendor) &&
11458                     (subsys_id_to_phy_id[i].subsys_devid ==
11459                      tp->pdev->subsystem_device))
11460                         return &subsys_id_to_phy_id[i];
11461         }
11462         return NULL;
11463 }
11464
11465 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11466 {
11467         u32 val;
11468         u16 pmcsr;
11469
11470         /* On some early chips the SRAM cannot be accessed in D3hot state,
11471          * so need make sure we're in D0.
11472          */
11473         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11474         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11475         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11476         msleep(1);
11477
11478         /* Make sure register accesses (indirect or otherwise)
11479          * will function correctly.
11480          */
11481         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11482                                tp->misc_host_ctrl);
11483
11484         /* The memory arbiter has to be enabled in order for SRAM accesses
11485          * to succeed.  Normally on powerup the tg3 chip firmware will make
11486          * sure it is enabled, but other entities such as system netboot
11487          * code might disable it.
11488          */
11489         val = tr32(MEMARB_MODE);
11490         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11491
11492         tp->phy_id = PHY_ID_INVALID;
11493         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11494
11495         /* Assume an onboard device and WOL capable by default.  */
11496         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11497
11498         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11499                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11500                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11501                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11502                 }
11503                 val = tr32(VCPU_CFGSHDW);
11504                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11505                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11506                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11507                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11508                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11509                 goto done;
11510         }
11511
11512         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11513         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11514                 u32 nic_cfg, led_cfg;
11515                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11516                 int eeprom_phy_serdes = 0;
11517
11518                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11519                 tp->nic_sram_data_cfg = nic_cfg;
11520
11521                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11522                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11523                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11524                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11525                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11526                     (ver > 0) && (ver < 0x100))
11527                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11528
11529                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11530                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11531
11532                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11533                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11534                         eeprom_phy_serdes = 1;
11535
11536                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11537                 if (nic_phy_id != 0) {
11538                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11539                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11540
11541                         eeprom_phy_id  = (id1 >> 16) << 10;
11542                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11543                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11544                 } else
11545                         eeprom_phy_id = 0;
11546
11547                 tp->phy_id = eeprom_phy_id;
11548                 if (eeprom_phy_serdes) {
11549                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11550                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11551                         else
11552                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11553                 }
11554
11555                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11556                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11557                                     SHASTA_EXT_LED_MODE_MASK);
11558                 else
11559                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11560
11561                 switch (led_cfg) {
11562                 default:
11563                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11564                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11565                         break;
11566
11567                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11568                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11569                         break;
11570
11571                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11572                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11573
11574                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11575                          * read on some older 5700/5701 bootcode.
11576                          */
11577                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11578                             ASIC_REV_5700 ||
11579                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11580                             ASIC_REV_5701)
11581                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11582
11583                         break;
11584
11585                 case SHASTA_EXT_LED_SHARED:
11586                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11587                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11588                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11589                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11590                                                  LED_CTRL_MODE_PHY_2);
11591                         break;
11592
11593                 case SHASTA_EXT_LED_MAC:
11594                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11595                         break;
11596
11597                 case SHASTA_EXT_LED_COMBO:
11598                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11599                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11600                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11601                                                  LED_CTRL_MODE_PHY_2);
11602                         break;
11603
11604                 }
11605
11606                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11607                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11608                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11609                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11610
11611                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11612                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11613
11614                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11615                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11616                         if ((tp->pdev->subsystem_vendor ==
11617                              PCI_VENDOR_ID_ARIMA) &&
11618                             (tp->pdev->subsystem_device == 0x205a ||
11619                              tp->pdev->subsystem_device == 0x2063))
11620                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11621                 } else {
11622                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11623                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11624                 }
11625
11626                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11627                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11628                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11629                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11630                 }
11631
11632                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11633                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11634                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11635
11636                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11637                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11638                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11639
11640                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11641                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11642                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11643
11644                 if (cfg2 & (1 << 17))
11645                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11646
11647                 /* serdes signal pre-emphasis in register 0x590 set by */
11648                 /* bootcode if bit 18 is set */
11649                 if (cfg2 & (1 << 18))
11650                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11651
11652                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11653                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11654                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11655                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11656
11657                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11658                         u32 cfg3;
11659
11660                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11661                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11662                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11663                 }
11664
11665                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11666                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11667                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11668                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11669                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11670                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11671         }
11672 done:
11673         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11674         device_set_wakeup_enable(&tp->pdev->dev,
11675                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11676 }
11677
11678 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11679 {
11680         int i;
11681         u32 val;
11682
11683         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11684         tw32(OTP_CTRL, cmd);
11685
11686         /* Wait for up to 1 ms for command to execute. */
11687         for (i = 0; i < 100; i++) {
11688                 val = tr32(OTP_STATUS);
11689                 if (val & OTP_STATUS_CMD_DONE)
11690                         break;
11691                 udelay(10);
11692         }
11693
11694         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11695 }
11696
11697 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11698  * configuration is a 32-bit value that straddles the alignment boundary.
11699  * We do two 32-bit reads and then shift and merge the results.
11700  */
11701 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11702 {
11703         u32 bhalf_otp, thalf_otp;
11704
11705         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11706
11707         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11708                 return 0;
11709
11710         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11711
11712         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11713                 return 0;
11714
11715         thalf_otp = tr32(OTP_READ_DATA);
11716
11717         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11718
11719         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11720                 return 0;
11721
11722         bhalf_otp = tr32(OTP_READ_DATA);
11723
11724         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11725 }
11726
11727 static int __devinit tg3_phy_probe(struct tg3 *tp)
11728 {
11729         u32 hw_phy_id_1, hw_phy_id_2;
11730         u32 hw_phy_id, hw_phy_id_masked;
11731         int err;
11732
11733         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11734                 return tg3_phy_init(tp);
11735
11736         /* Reading the PHY ID register can conflict with ASF
11737          * firmware access to the PHY hardware.
11738          */
11739         err = 0;
11740         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11741             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11742                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11743         } else {
11744                 /* Now read the physical PHY_ID from the chip and verify
11745                  * that it is sane.  If it doesn't look good, we fall back
11746                  * to either the hard-coded table based PHY_ID and failing
11747                  * that the value found in the eeprom area.
11748                  */
11749                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11750                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11751
11752                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11753                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11754                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11755
11756                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11757         }
11758
11759         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11760                 tp->phy_id = hw_phy_id;
11761                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11762                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11763                 else
11764                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11765         } else {
11766                 if (tp->phy_id != PHY_ID_INVALID) {
11767                         /* Do nothing, phy ID already set up in
11768                          * tg3_get_eeprom_hw_cfg().
11769                          */
11770                 } else {
11771                         struct subsys_tbl_ent *p;
11772
11773                         /* No eeprom signature?  Try the hardcoded
11774                          * subsys device table.
11775                          */
11776                         p = lookup_by_subsys(tp);
11777                         if (!p)
11778                                 return -ENODEV;
11779
11780                         tp->phy_id = p->phy_id;
11781                         if (!tp->phy_id ||
11782                             tp->phy_id == PHY_ID_BCM8002)
11783                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11784                 }
11785         }
11786
11787         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11788             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11789             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11790                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11791
11792                 tg3_readphy(tp, MII_BMSR, &bmsr);
11793                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11794                     (bmsr & BMSR_LSTATUS))
11795                         goto skip_phy_reset;
11796
11797                 err = tg3_phy_reset(tp);
11798                 if (err)
11799                         return err;
11800
11801                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11802                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11803                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11804                 tg3_ctrl = 0;
11805                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11806                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11807                                     MII_TG3_CTRL_ADV_1000_FULL);
11808                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11809                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11810                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11811                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11812                 }
11813
11814                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11815                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11816                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11817                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11818                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11819
11820                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11821                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11822
11823                         tg3_writephy(tp, MII_BMCR,
11824                                      BMCR_ANENABLE | BMCR_ANRESTART);
11825                 }
11826                 tg3_phy_set_wirespeed(tp);
11827
11828                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11829                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11830                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11831         }
11832
11833 skip_phy_reset:
11834         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11835                 err = tg3_init_5401phy_dsp(tp);
11836                 if (err)
11837                         return err;
11838         }
11839
11840         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11841                 err = tg3_init_5401phy_dsp(tp);
11842         }
11843
11844         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11845                 tp->link_config.advertising =
11846                         (ADVERTISED_1000baseT_Half |
11847                          ADVERTISED_1000baseT_Full |
11848                          ADVERTISED_Autoneg |
11849                          ADVERTISED_FIBRE);
11850         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11851                 tp->link_config.advertising &=
11852                         ~(ADVERTISED_1000baseT_Half |
11853                           ADVERTISED_1000baseT_Full);
11854
11855         return err;
11856 }
11857
11858 static void __devinit tg3_read_partno(struct tg3 *tp)
11859 {
11860         unsigned char vpd_data[256];   /* in little-endian format */
11861         unsigned int i;
11862         u32 magic;
11863
11864         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11865             tg3_nvram_read(tp, 0x0, &magic))
11866                 goto out_not_found;
11867
11868         if (magic == TG3_EEPROM_MAGIC) {
11869                 for (i = 0; i < 256; i += 4) {
11870                         u32 tmp;
11871
11872                         /* The data is in little-endian format in NVRAM.
11873                          * Use the big-endian read routines to preserve
11874                          * the byte order as it exists in NVRAM.
11875                          */
11876                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11877                                 goto out_not_found;
11878
11879                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11880                 }
11881         } else {
11882                 int vpd_cap;
11883
11884                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11885                 for (i = 0; i < 256; i += 4) {
11886                         u32 tmp, j = 0;
11887                         __le32 v;
11888                         u16 tmp16;
11889
11890                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11891                                               i);
11892                         while (j++ < 100) {
11893                                 pci_read_config_word(tp->pdev, vpd_cap +
11894                                                      PCI_VPD_ADDR, &tmp16);
11895                                 if (tmp16 & 0x8000)
11896                                         break;
11897                                 msleep(1);
11898                         }
11899                         if (!(tmp16 & 0x8000))
11900                                 goto out_not_found;
11901
11902                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11903                                               &tmp);
11904                         v = cpu_to_le32(tmp);
11905                         memcpy(&vpd_data[i], &v, sizeof(v));
11906                 }
11907         }
11908
11909         /* Now parse and find the part number. */
11910         for (i = 0; i < 254; ) {
11911                 unsigned char val = vpd_data[i];
11912                 unsigned int block_end;
11913
11914                 if (val == 0x82 || val == 0x91) {
11915                         i = (i + 3 +
11916                              (vpd_data[i + 1] +
11917                               (vpd_data[i + 2] << 8)));
11918                         continue;
11919                 }
11920
11921                 if (val != 0x90)
11922                         goto out_not_found;
11923
11924                 block_end = (i + 3 +
11925                              (vpd_data[i + 1] +
11926                               (vpd_data[i + 2] << 8)));
11927                 i += 3;
11928
11929                 if (block_end > 256)
11930                         goto out_not_found;
11931
11932                 while (i < (block_end - 2)) {
11933                         if (vpd_data[i + 0] == 'P' &&
11934                             vpd_data[i + 1] == 'N') {
11935                                 int partno_len = vpd_data[i + 2];
11936
11937                                 i += 3;
11938                                 if (partno_len > 24 || (partno_len + i) > 256)
11939                                         goto out_not_found;
11940
11941                                 memcpy(tp->board_part_number,
11942                                        &vpd_data[i], partno_len);
11943
11944                                 /* Success. */
11945                                 return;
11946                         }
11947                         i += 3 + vpd_data[i + 2];
11948                 }
11949
11950                 /* Part number not found. */
11951                 goto out_not_found;
11952         }
11953
11954 out_not_found:
11955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11956                 strcpy(tp->board_part_number, "BCM95906");
11957         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11958                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11959                 strcpy(tp->board_part_number, "BCM57780");
11960         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11961                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11962                 strcpy(tp->board_part_number, "BCM57760");
11963         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11964                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11965                 strcpy(tp->board_part_number, "BCM57790");
11966         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11967                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11968                 strcpy(tp->board_part_number, "BCM57788");
11969         else
11970                 strcpy(tp->board_part_number, "none");
11971 }
11972
11973 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11974 {
11975         u32 val;
11976
11977         if (tg3_nvram_read(tp, offset, &val) ||
11978             (val & 0xfc000000) != 0x0c000000 ||
11979             tg3_nvram_read(tp, offset + 4, &val) ||
11980             val != 0)
11981                 return 0;
11982
11983         return 1;
11984 }
11985
11986 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11987 {
11988         u32 val, offset, start, ver_offset;
11989         int i;
11990         bool newver = false;
11991
11992         if (tg3_nvram_read(tp, 0xc, &offset) ||
11993             tg3_nvram_read(tp, 0x4, &start))
11994                 return;
11995
11996         offset = tg3_nvram_logical_addr(tp, offset);
11997
11998         if (tg3_nvram_read(tp, offset, &val))
11999                 return;
12000
12001         if ((val & 0xfc000000) == 0x0c000000) {
12002                 if (tg3_nvram_read(tp, offset + 4, &val))
12003                         return;
12004
12005                 if (val == 0)
12006                         newver = true;
12007         }
12008
12009         if (newver) {
12010                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12011                         return;
12012
12013                 offset = offset + ver_offset - start;
12014                 for (i = 0; i < 16; i += 4) {
12015                         __be32 v;
12016                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12017                                 return;
12018
12019                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12020                 }
12021         } else {
12022                 u32 major, minor;
12023
12024                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12025                         return;
12026
12027                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12028                         TG3_NVM_BCVER_MAJSFT;
12029                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12030                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12031         }
12032 }
12033
12034 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12035 {
12036         u32 val, major, minor;
12037
12038         /* Use native endian representation */
12039         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12040                 return;
12041
12042         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12043                 TG3_NVM_HWSB_CFG1_MAJSFT;
12044         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12045                 TG3_NVM_HWSB_CFG1_MINSFT;
12046
12047         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12048 }
12049
12050 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12051 {
12052         u32 offset, major, minor, build;
12053
12054         tp->fw_ver[0] = 's';
12055         tp->fw_ver[1] = 'b';
12056         tp->fw_ver[2] = '\0';
12057
12058         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12059                 return;
12060
12061         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12062         case TG3_EEPROM_SB_REVISION_0:
12063                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12064                 break;
12065         case TG3_EEPROM_SB_REVISION_2:
12066                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12067                 break;
12068         case TG3_EEPROM_SB_REVISION_3:
12069                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12070                 break;
12071         default:
12072                 return;
12073         }
12074
12075         if (tg3_nvram_read(tp, offset, &val))
12076                 return;
12077
12078         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12079                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12080         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12081                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12082         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12083
12084         if (minor > 99 || build > 26)
12085                 return;
12086
12087         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12088
12089         if (build > 0) {
12090                 tp->fw_ver[8] = 'a' + build - 1;
12091                 tp->fw_ver[9] = '\0';
12092         }
12093 }
12094
12095 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12096 {
12097         u32 val, offset, start;
12098         int i, vlen;
12099
12100         for (offset = TG3_NVM_DIR_START;
12101              offset < TG3_NVM_DIR_END;
12102              offset += TG3_NVM_DIRENT_SIZE) {
12103                 if (tg3_nvram_read(tp, offset, &val))
12104                         return;
12105
12106                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12107                         break;
12108         }
12109
12110         if (offset == TG3_NVM_DIR_END)
12111                 return;
12112
12113         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12114                 start = 0x08000000;
12115         else if (tg3_nvram_read(tp, offset - 4, &start))
12116                 return;
12117
12118         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12119             !tg3_fw_img_is_valid(tp, offset) ||
12120             tg3_nvram_read(tp, offset + 8, &val))
12121                 return;
12122
12123         offset += val - start;
12124
12125         vlen = strlen(tp->fw_ver);
12126
12127         tp->fw_ver[vlen++] = ',';
12128         tp->fw_ver[vlen++] = ' ';
12129
12130         for (i = 0; i < 4; i++) {
12131                 __be32 v;
12132                 if (tg3_nvram_read_be32(tp, offset, &v))
12133                         return;
12134
12135                 offset += sizeof(v);
12136
12137                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12138                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12139                         break;
12140                 }
12141
12142                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12143                 vlen += sizeof(v);
12144         }
12145 }
12146
12147 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12148 {
12149         int vlen;
12150         u32 apedata;
12151
12152         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12153             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12154                 return;
12155
12156         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12157         if (apedata != APE_SEG_SIG_MAGIC)
12158                 return;
12159
12160         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12161         if (!(apedata & APE_FW_STATUS_READY))
12162                 return;
12163
12164         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12165
12166         vlen = strlen(tp->fw_ver);
12167
12168         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12169                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12170                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12171                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12172                  (apedata & APE_FW_VERSION_BLDMSK));
12173 }
12174
12175 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12176 {
12177         u32 val;
12178
12179         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12180                 tp->fw_ver[0] = 's';
12181                 tp->fw_ver[1] = 'b';
12182                 tp->fw_ver[2] = '\0';
12183
12184                 return;
12185         }
12186
12187         if (tg3_nvram_read(tp, 0, &val))
12188                 return;
12189
12190         if (val == TG3_EEPROM_MAGIC)
12191                 tg3_read_bc_ver(tp);
12192         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12193                 tg3_read_sb_ver(tp, val);
12194         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12195                 tg3_read_hwsb_ver(tp);
12196         else
12197                 return;
12198
12199         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12200              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12201                 return;
12202
12203         tg3_read_mgmtfw_ver(tp);
12204
12205         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12206 }
12207
12208 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12209
12210 static int __devinit tg3_get_invariants(struct tg3 *tp)
12211 {
12212         static struct pci_device_id write_reorder_chipsets[] = {
12213                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12214                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12215                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12216                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12217                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12218                              PCI_DEVICE_ID_VIA_8385_0) },
12219                 { },
12220         };
12221         u32 misc_ctrl_reg;
12222         u32 pci_state_reg, grc_misc_cfg;
12223         u32 val;
12224         u16 pci_cmd;
12225         int err;
12226
12227         /* Force memory write invalidate off.  If we leave it on,
12228          * then on 5700_BX chips we have to enable a workaround.
12229          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12230          * to match the cacheline size.  The Broadcom driver have this
12231          * workaround but turns MWI off all the times so never uses
12232          * it.  This seems to suggest that the workaround is insufficient.
12233          */
12234         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12235         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12236         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12237
12238         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12239          * has the register indirect write enable bit set before
12240          * we try to access any of the MMIO registers.  It is also
12241          * critical that the PCI-X hw workaround situation is decided
12242          * before that as well.
12243          */
12244         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12245                               &misc_ctrl_reg);
12246
12247         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12248                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12249         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12250                 u32 prod_id_asic_rev;
12251
12252                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12253                                       &prod_id_asic_rev);
12254                 tp->pci_chip_rev_id = prod_id_asic_rev;
12255         }
12256
12257         /* Wrong chip ID in 5752 A0. This code can be removed later
12258          * as A0 is not in production.
12259          */
12260         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12261                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12262
12263         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12264          * we need to disable memory and use config. cycles
12265          * only to access all registers. The 5702/03 chips
12266          * can mistakenly decode the special cycles from the
12267          * ICH chipsets as memory write cycles, causing corruption
12268          * of register and memory space. Only certain ICH bridges
12269          * will drive special cycles with non-zero data during the
12270          * address phase which can fall within the 5703's address
12271          * range. This is not an ICH bug as the PCI spec allows
12272          * non-zero address during special cycles. However, only
12273          * these ICH bridges are known to drive non-zero addresses
12274          * during special cycles.
12275          *
12276          * Since special cycles do not cross PCI bridges, we only
12277          * enable this workaround if the 5703 is on the secondary
12278          * bus of these ICH bridges.
12279          */
12280         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12281             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12282                 static struct tg3_dev_id {
12283                         u32     vendor;
12284                         u32     device;
12285                         u32     rev;
12286                 } ich_chipsets[] = {
12287                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12288                           PCI_ANY_ID },
12289                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12290                           PCI_ANY_ID },
12291                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12292                           0xa },
12293                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12294                           PCI_ANY_ID },
12295                         { },
12296                 };
12297                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12298                 struct pci_dev *bridge = NULL;
12299
12300                 while (pci_id->vendor != 0) {
12301                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12302                                                 bridge);
12303                         if (!bridge) {
12304                                 pci_id++;
12305                                 continue;
12306                         }
12307                         if (pci_id->rev != PCI_ANY_ID) {
12308                                 if (bridge->revision > pci_id->rev)
12309                                         continue;
12310                         }
12311                         if (bridge->subordinate &&
12312                             (bridge->subordinate->number ==
12313                              tp->pdev->bus->number)) {
12314
12315                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12316                                 pci_dev_put(bridge);
12317                                 break;
12318                         }
12319                 }
12320         }
12321
12322         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12323                 static struct tg3_dev_id {
12324                         u32     vendor;
12325                         u32     device;
12326                 } bridge_chipsets[] = {
12327                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12328                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12329                         { },
12330                 };
12331                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12332                 struct pci_dev *bridge = NULL;
12333
12334                 while (pci_id->vendor != 0) {
12335                         bridge = pci_get_device(pci_id->vendor,
12336                                                 pci_id->device,
12337                                                 bridge);
12338                         if (!bridge) {
12339                                 pci_id++;
12340                                 continue;
12341                         }
12342                         if (bridge->subordinate &&
12343                             (bridge->subordinate->number <=
12344                              tp->pdev->bus->number) &&
12345                             (bridge->subordinate->subordinate >=
12346                              tp->pdev->bus->number)) {
12347                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12348                                 pci_dev_put(bridge);
12349                                 break;
12350                         }
12351                 }
12352         }
12353
12354         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12355          * DMA addresses > 40-bit. This bridge may have other additional
12356          * 57xx devices behind it in some 4-port NIC designs for example.
12357          * Any tg3 device found behind the bridge will also need the 40-bit
12358          * DMA workaround.
12359          */
12360         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12361             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12362                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12363                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12364                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12365         }
12366         else {
12367                 struct pci_dev *bridge = NULL;
12368
12369                 do {
12370                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12371                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12372                                                 bridge);
12373                         if (bridge && bridge->subordinate &&
12374                             (bridge->subordinate->number <=
12375                              tp->pdev->bus->number) &&
12376                             (bridge->subordinate->subordinate >=
12377                              tp->pdev->bus->number)) {
12378                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12379                                 pci_dev_put(bridge);
12380                                 break;
12381                         }
12382                 } while (bridge);
12383         }
12384
12385         /* Initialize misc host control in PCI block. */
12386         tp->misc_host_ctrl |= (misc_ctrl_reg &
12387                                MISC_HOST_CTRL_CHIPREV);
12388         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12389                                tp->misc_host_ctrl);
12390
12391         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12392             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12393                 tp->pdev_peer = tg3_find_peer(tp);
12394
12395         /* Intentionally exclude ASIC_REV_5906 */
12396         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12397             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12398             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12399             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12400             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12401             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12402                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12403
12404         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12405             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12406             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12407             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12408             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12409                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12410
12411         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12412             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12413                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12414
12415         /* 5700 B0 chips do not support checksumming correctly due
12416          * to hardware bugs.
12417          */
12418         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12419                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12420         else {
12421                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12422                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12423                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12424                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12425         }
12426
12427         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12428                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12429                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12430                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12431                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12432                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12433                      tp->pdev_peer == tp->pdev))
12434                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12435
12436                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12437                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12438                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12439                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12440                 } else {
12441                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12442                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12443                                 ASIC_REV_5750 &&
12444                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12445                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12446                 }
12447         }
12448
12449         tp->irq_max = 1;
12450
12451         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12452              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12453                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12454
12455         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12456                               &pci_state_reg);
12457
12458         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12459         if (tp->pcie_cap != 0) {
12460                 u16 lnkctl;
12461
12462                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12463
12464                 pcie_set_readrq(tp->pdev, 4096);
12465
12466                 pci_read_config_word(tp->pdev,
12467                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12468                                      &lnkctl);
12469                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12470                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12471                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12472                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12473                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12474                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12475                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12476                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12477                 }
12478         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12479                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12480         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12481                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12482                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12483                 if (!tp->pcix_cap) {
12484                         printk(KERN_ERR PFX "Cannot find PCI-X "
12485                                             "capability, aborting.\n");
12486                         return -EIO;
12487                 }
12488
12489                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12490                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12491         }
12492
12493         /* If we have an AMD 762 or VIA K8T800 chipset, write
12494          * reordering to the mailbox registers done by the host
12495          * controller can cause major troubles.  We read back from
12496          * every mailbox register write to force the writes to be
12497          * posted to the chip in order.
12498          */
12499         if (pci_dev_present(write_reorder_chipsets) &&
12500             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12501                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12502
12503         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12504                              &tp->pci_cacheline_sz);
12505         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12506                              &tp->pci_lat_timer);
12507         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12508             tp->pci_lat_timer < 64) {
12509                 tp->pci_lat_timer = 64;
12510                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12511                                       tp->pci_lat_timer);
12512         }
12513
12514         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12515                 /* 5700 BX chips need to have their TX producer index
12516                  * mailboxes written twice to workaround a bug.
12517                  */
12518                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12519
12520                 /* If we are in PCI-X mode, enable register write workaround.
12521                  *
12522                  * The workaround is to use indirect register accesses
12523                  * for all chip writes not to mailbox registers.
12524                  */
12525                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12526                         u32 pm_reg;
12527
12528                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12529
12530                         /* The chip can have it's power management PCI config
12531                          * space registers clobbered due to this bug.
12532                          * So explicitly force the chip into D0 here.
12533                          */
12534                         pci_read_config_dword(tp->pdev,
12535                                               tp->pm_cap + PCI_PM_CTRL,
12536                                               &pm_reg);
12537                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12538                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12539                         pci_write_config_dword(tp->pdev,
12540                                                tp->pm_cap + PCI_PM_CTRL,
12541                                                pm_reg);
12542
12543                         /* Also, force SERR#/PERR# in PCI command. */
12544                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12545                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12546                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12547                 }
12548         }
12549
12550         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12551                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12552         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12553                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12554
12555         /* Chip-specific fixup from Broadcom driver */
12556         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12557             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12558                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12559                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12560         }
12561
12562         /* Default fast path register access methods */
12563         tp->read32 = tg3_read32;
12564         tp->write32 = tg3_write32;
12565         tp->read32_mbox = tg3_read32;
12566         tp->write32_mbox = tg3_write32;
12567         tp->write32_tx_mbox = tg3_write32;
12568         tp->write32_rx_mbox = tg3_write32;
12569
12570         /* Various workaround register access methods */
12571         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12572                 tp->write32 = tg3_write_indirect_reg32;
12573         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12574                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12575                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12576                 /*
12577                  * Back to back register writes can cause problems on these
12578                  * chips, the workaround is to read back all reg writes
12579                  * except those to mailbox regs.
12580                  *
12581                  * See tg3_write_indirect_reg32().
12582                  */
12583                 tp->write32 = tg3_write_flush_reg32;
12584         }
12585
12586
12587         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12588             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12589                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12590                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12591                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12592         }
12593
12594         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12595                 tp->read32 = tg3_read_indirect_reg32;
12596                 tp->write32 = tg3_write_indirect_reg32;
12597                 tp->read32_mbox = tg3_read_indirect_mbox;
12598                 tp->write32_mbox = tg3_write_indirect_mbox;
12599                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12600                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12601
12602                 iounmap(tp->regs);
12603                 tp->regs = NULL;
12604
12605                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12606                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12607                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12608         }
12609         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12610                 tp->read32_mbox = tg3_read32_mbox_5906;
12611                 tp->write32_mbox = tg3_write32_mbox_5906;
12612                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12613                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12614         }
12615
12616         if (tp->write32 == tg3_write_indirect_reg32 ||
12617             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12618              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12619               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12620                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12621
12622         /* Get eeprom hw config before calling tg3_set_power_state().
12623          * In particular, the TG3_FLG2_IS_NIC flag must be
12624          * determined before calling tg3_set_power_state() so that
12625          * we know whether or not to switch out of Vaux power.
12626          * When the flag is set, it means that GPIO1 is used for eeprom
12627          * write protect and also implies that it is a LOM where GPIOs
12628          * are not used to switch power.
12629          */
12630         tg3_get_eeprom_hw_cfg(tp);
12631
12632         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12633                 /* Allow reads and writes to the
12634                  * APE register and memory space.
12635                  */
12636                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12637                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12638                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12639                                        pci_state_reg);
12640         }
12641
12642         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12643             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12644             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12645             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12646                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12647
12648         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12649          * GPIO1 driven high will bring 5700's external PHY out of reset.
12650          * It is also used as eeprom write protect on LOMs.
12651          */
12652         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12653         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12654             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12655                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12656                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12657         /* Unused GPIO3 must be driven as output on 5752 because there
12658          * are no pull-up resistors on unused GPIO pins.
12659          */
12660         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12661                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12662
12663         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12664             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12665                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12666
12667         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12668             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12669                 /* Turn off the debug UART. */
12670                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12671                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12672                         /* Keep VMain power. */
12673                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12674                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12675         }
12676
12677         /* Force the chip into D0. */
12678         err = tg3_set_power_state(tp, PCI_D0);
12679         if (err) {
12680                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12681                        pci_name(tp->pdev));
12682                 return err;
12683         }
12684
12685         /* Derive initial jumbo mode from MTU assigned in
12686          * ether_setup() via the alloc_etherdev() call
12687          */
12688         if (tp->dev->mtu > ETH_DATA_LEN &&
12689             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12690                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12691
12692         /* Determine WakeOnLan speed to use. */
12693         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12694             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12695             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12696             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12697                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12698         } else {
12699                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12700         }
12701
12702         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12703                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12704
12705         /* A few boards don't want Ethernet@WireSpeed phy feature */
12706         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12707             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12708              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12709              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12710             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12711             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12712                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12713
12714         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12715             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12716                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12717         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12718                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12719
12720         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12721             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12722             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12723             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12724                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12725                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12726                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12727                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12728                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12729                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12730                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12731                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12732                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12733                 } else
12734                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12735         }
12736
12737         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12738             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12739                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12740                 if (tp->phy_otp == 0)
12741                         tp->phy_otp = TG3_OTP_DEFAULT;
12742         }
12743
12744         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12745                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12746         else
12747                 tp->mi_mode = MAC_MI_MODE_BASE;
12748
12749         tp->coalesce_mode = 0;
12750         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12751             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12752                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12753
12754         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12755             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12756                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12757
12758         if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12759              tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12760             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12761                 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12762
12763         err = tg3_mdio_init(tp);
12764         if (err)
12765                 return err;
12766
12767         /* Initialize data/descriptor byte/word swapping. */
12768         val = tr32(GRC_MODE);
12769         val &= GRC_MODE_HOST_STACKUP;
12770         tw32(GRC_MODE, val | tp->grc_mode);
12771
12772         tg3_switch_clocks(tp);
12773
12774         /* Clear this out for sanity. */
12775         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12776
12777         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12778                               &pci_state_reg);
12779         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12780             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12781                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12782
12783                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12784                     chiprevid == CHIPREV_ID_5701_B0 ||
12785                     chiprevid == CHIPREV_ID_5701_B2 ||
12786                     chiprevid == CHIPREV_ID_5701_B5) {
12787                         void __iomem *sram_base;
12788
12789                         /* Write some dummy words into the SRAM status block
12790                          * area, see if it reads back correctly.  If the return
12791                          * value is bad, force enable the PCIX workaround.
12792                          */
12793                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12794
12795                         writel(0x00000000, sram_base);
12796                         writel(0x00000000, sram_base + 4);
12797                         writel(0xffffffff, sram_base + 4);
12798                         if (readl(sram_base) != 0x00000000)
12799                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12800                 }
12801         }
12802
12803         udelay(50);
12804         tg3_nvram_init(tp);
12805
12806         grc_misc_cfg = tr32(GRC_MISC_CFG);
12807         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12808
12809         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12810             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12811              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12812                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12813
12814         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12815             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12816                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12817         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12818                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12819                                       HOSTCC_MODE_CLRTICK_TXBD);
12820
12821                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12822                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12823                                        tp->misc_host_ctrl);
12824         }
12825
12826         /* Preserve the APE MAC_MODE bits */
12827         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12828                 tp->mac_mode = tr32(MAC_MODE) |
12829                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12830         else
12831                 tp->mac_mode = TG3_DEF_MAC_MODE;
12832
12833         /* these are limited to 10/100 only */
12834         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12835              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12836             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12837              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12838              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12839               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12840               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12841             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12842              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12843               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12844               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12845             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12846             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
12847                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12848
12849         err = tg3_phy_probe(tp);
12850         if (err) {
12851                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12852                        pci_name(tp->pdev), err);
12853                 /* ... but do not return immediately ... */
12854                 tg3_mdio_fini(tp);
12855         }
12856
12857         tg3_read_partno(tp);
12858         tg3_read_fw_ver(tp);
12859
12860         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12861                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12862         } else {
12863                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12864                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12865                 else
12866                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12867         }
12868
12869         /* 5700 {AX,BX} chips have a broken status block link
12870          * change bit implementation, so we must use the
12871          * status register in those cases.
12872          */
12873         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12874                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12875         else
12876                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12877
12878         /* The led_ctrl is set during tg3_phy_probe, here we might
12879          * have to force the link status polling mechanism based
12880          * upon subsystem IDs.
12881          */
12882         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12883             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12884             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12885                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12886                                   TG3_FLAG_USE_LINKCHG_REG);
12887         }
12888
12889         /* For all SERDES we poll the MAC status register. */
12890         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12891                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12892         else
12893                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12894
12895         tp->rx_offset = NET_IP_ALIGN;
12896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12897             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12898                 tp->rx_offset = 0;
12899
12900         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12901
12902         /* Increment the rx prod index on the rx std ring by at most
12903          * 8 for these chips to workaround hw errata.
12904          */
12905         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12906             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12907             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12908                 tp->rx_std_max_post = 8;
12909
12910         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12911                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12912                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12913
12914         return err;
12915 }
12916
12917 #ifdef CONFIG_SPARC
12918 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12919 {
12920         struct net_device *dev = tp->dev;
12921         struct pci_dev *pdev = tp->pdev;
12922         struct device_node *dp = pci_device_to_OF_node(pdev);
12923         const unsigned char *addr;
12924         int len;
12925
12926         addr = of_get_property(dp, "local-mac-address", &len);
12927         if (addr && len == 6) {
12928                 memcpy(dev->dev_addr, addr, 6);
12929                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12930                 return 0;
12931         }
12932         return -ENODEV;
12933 }
12934
12935 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12936 {
12937         struct net_device *dev = tp->dev;
12938
12939         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12940         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12941         return 0;
12942 }
12943 #endif
12944
12945 static int __devinit tg3_get_device_address(struct tg3 *tp)
12946 {
12947         struct net_device *dev = tp->dev;
12948         u32 hi, lo, mac_offset;
12949         int addr_ok = 0;
12950
12951 #ifdef CONFIG_SPARC
12952         if (!tg3_get_macaddr_sparc(tp))
12953                 return 0;
12954 #endif
12955
12956         mac_offset = 0x7c;
12957         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12958             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12959                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12960                         mac_offset = 0xcc;
12961                 if (tg3_nvram_lock(tp))
12962                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12963                 else
12964                         tg3_nvram_unlock(tp);
12965         }
12966         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12967                 mac_offset = 0x10;
12968
12969         /* First try to get it from MAC address mailbox. */
12970         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12971         if ((hi >> 16) == 0x484b) {
12972                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12973                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12974
12975                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12976                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12977                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12978                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12979                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12980
12981                 /* Some old bootcode may report a 0 MAC address in SRAM */
12982                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12983         }
12984         if (!addr_ok) {
12985                 /* Next, try NVRAM. */
12986                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12987                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12988                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12989                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12990                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12991                 }
12992                 /* Finally just fetch it out of the MAC control regs. */
12993                 else {
12994                         hi = tr32(MAC_ADDR_0_HIGH);
12995                         lo = tr32(MAC_ADDR_0_LOW);
12996
12997                         dev->dev_addr[5] = lo & 0xff;
12998                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12999                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13000                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13001                         dev->dev_addr[1] = hi & 0xff;
13002                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13003                 }
13004         }
13005
13006         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13007 #ifdef CONFIG_SPARC
13008                 if (!tg3_get_default_macaddr_sparc(tp))
13009                         return 0;
13010 #endif
13011                 return -EINVAL;
13012         }
13013         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13014         return 0;
13015 }
13016
13017 #define BOUNDARY_SINGLE_CACHELINE       1
13018 #define BOUNDARY_MULTI_CACHELINE        2
13019
13020 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13021 {
13022         int cacheline_size;
13023         u8 byte;
13024         int goal;
13025
13026         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13027         if (byte == 0)
13028                 cacheline_size = 1024;
13029         else
13030                 cacheline_size = (int) byte * 4;
13031
13032         /* On 5703 and later chips, the boundary bits have no
13033          * effect.
13034          */
13035         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13036             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13037             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13038                 goto out;
13039
13040 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13041         goal = BOUNDARY_MULTI_CACHELINE;
13042 #else
13043 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13044         goal = BOUNDARY_SINGLE_CACHELINE;
13045 #else
13046         goal = 0;
13047 #endif
13048 #endif
13049
13050         if (!goal)
13051                 goto out;
13052
13053         /* PCI controllers on most RISC systems tend to disconnect
13054          * when a device tries to burst across a cache-line boundary.
13055          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13056          *
13057          * Unfortunately, for PCI-E there are only limited
13058          * write-side controls for this, and thus for reads
13059          * we will still get the disconnects.  We'll also waste
13060          * these PCI cycles for both read and write for chips
13061          * other than 5700 and 5701 which do not implement the
13062          * boundary bits.
13063          */
13064         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13065             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13066                 switch (cacheline_size) {
13067                 case 16:
13068                 case 32:
13069                 case 64:
13070                 case 128:
13071                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13072                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13073                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13074                         } else {
13075                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13076                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13077                         }
13078                         break;
13079
13080                 case 256:
13081                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13082                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13083                         break;
13084
13085                 default:
13086                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13087                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13088                         break;
13089                 }
13090         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13091                 switch (cacheline_size) {
13092                 case 16:
13093                 case 32:
13094                 case 64:
13095                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13096                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13097                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13098                                 break;
13099                         }
13100                         /* fallthrough */
13101                 case 128:
13102                 default:
13103                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13104                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13105                         break;
13106                 }
13107         } else {
13108                 switch (cacheline_size) {
13109                 case 16:
13110                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13111                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13112                                         DMA_RWCTRL_WRITE_BNDRY_16);
13113                                 break;
13114                         }
13115                         /* fallthrough */
13116                 case 32:
13117                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13118                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13119                                         DMA_RWCTRL_WRITE_BNDRY_32);
13120                                 break;
13121                         }
13122                         /* fallthrough */
13123                 case 64:
13124                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13125                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13126                                         DMA_RWCTRL_WRITE_BNDRY_64);
13127                                 break;
13128                         }
13129                         /* fallthrough */
13130                 case 128:
13131                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13132                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13133                                         DMA_RWCTRL_WRITE_BNDRY_128);
13134                                 break;
13135                         }
13136                         /* fallthrough */
13137                 case 256:
13138                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13139                                 DMA_RWCTRL_WRITE_BNDRY_256);
13140                         break;
13141                 case 512:
13142                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13143                                 DMA_RWCTRL_WRITE_BNDRY_512);
13144                         break;
13145                 case 1024:
13146                 default:
13147                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13148                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13149                         break;
13150                 }
13151         }
13152
13153 out:
13154         return val;
13155 }
13156
13157 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13158 {
13159         struct tg3_internal_buffer_desc test_desc;
13160         u32 sram_dma_descs;
13161         int i, ret;
13162
13163         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13164
13165         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13166         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13167         tw32(RDMAC_STATUS, 0);
13168         tw32(WDMAC_STATUS, 0);
13169
13170         tw32(BUFMGR_MODE, 0);
13171         tw32(FTQ_RESET, 0);
13172
13173         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13174         test_desc.addr_lo = buf_dma & 0xffffffff;
13175         test_desc.nic_mbuf = 0x00002100;
13176         test_desc.len = size;
13177
13178         /*
13179          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13180          * the *second* time the tg3 driver was getting loaded after an
13181          * initial scan.
13182          *
13183          * Broadcom tells me:
13184          *   ...the DMA engine is connected to the GRC block and a DMA
13185          *   reset may affect the GRC block in some unpredictable way...
13186          *   The behavior of resets to individual blocks has not been tested.
13187          *
13188          * Broadcom noted the GRC reset will also reset all sub-components.
13189          */
13190         if (to_device) {
13191                 test_desc.cqid_sqid = (13 << 8) | 2;
13192
13193                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13194                 udelay(40);
13195         } else {
13196                 test_desc.cqid_sqid = (16 << 8) | 7;
13197
13198                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13199                 udelay(40);
13200         }
13201         test_desc.flags = 0x00000005;
13202
13203         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13204                 u32 val;
13205
13206                 val = *(((u32 *)&test_desc) + i);
13207                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13208                                        sram_dma_descs + (i * sizeof(u32)));
13209                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13210         }
13211         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13212
13213         if (to_device) {
13214                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13215         } else {
13216                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13217         }
13218
13219         ret = -ENODEV;
13220         for (i = 0; i < 40; i++) {
13221                 u32 val;
13222
13223                 if (to_device)
13224                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13225                 else
13226                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13227                 if ((val & 0xffff) == sram_dma_descs) {
13228                         ret = 0;
13229                         break;
13230                 }
13231
13232                 udelay(100);
13233         }
13234
13235         return ret;
13236 }
13237
13238 #define TEST_BUFFER_SIZE        0x2000
13239
13240 static int __devinit tg3_test_dma(struct tg3 *tp)
13241 {
13242         dma_addr_t buf_dma;
13243         u32 *buf, saved_dma_rwctrl;
13244         int ret;
13245
13246         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13247         if (!buf) {
13248                 ret = -ENOMEM;
13249                 goto out_nofree;
13250         }
13251
13252         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13253                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13254
13255         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13256
13257         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13258                 /* DMA read watermark not used on PCIE */
13259                 tp->dma_rwctrl |= 0x00180000;
13260         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13261                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13262                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13263                         tp->dma_rwctrl |= 0x003f0000;
13264                 else
13265                         tp->dma_rwctrl |= 0x003f000f;
13266         } else {
13267                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13268                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13269                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13270                         u32 read_water = 0x7;
13271
13272                         /* If the 5704 is behind the EPB bridge, we can
13273                          * do the less restrictive ONE_DMA workaround for
13274                          * better performance.
13275                          */
13276                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13277                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13278                                 tp->dma_rwctrl |= 0x8000;
13279                         else if (ccval == 0x6 || ccval == 0x7)
13280                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13281
13282                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13283                                 read_water = 4;
13284                         /* Set bit 23 to enable PCIX hw bug fix */
13285                         tp->dma_rwctrl |=
13286                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13287                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13288                                 (1 << 23);
13289                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13290                         /* 5780 always in PCIX mode */
13291                         tp->dma_rwctrl |= 0x00144000;
13292                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13293                         /* 5714 always in PCIX mode */
13294                         tp->dma_rwctrl |= 0x00148000;
13295                 } else {
13296                         tp->dma_rwctrl |= 0x001b000f;
13297                 }
13298         }
13299
13300         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13301             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13302                 tp->dma_rwctrl &= 0xfffffff0;
13303
13304         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13305             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13306                 /* Remove this if it causes problems for some boards. */
13307                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13308
13309                 /* On 5700/5701 chips, we need to set this bit.
13310                  * Otherwise the chip will issue cacheline transactions
13311                  * to streamable DMA memory with not all the byte
13312                  * enables turned on.  This is an error on several
13313                  * RISC PCI controllers, in particular sparc64.
13314                  *
13315                  * On 5703/5704 chips, this bit has been reassigned
13316                  * a different meaning.  In particular, it is used
13317                  * on those chips to enable a PCI-X workaround.
13318                  */
13319                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13320         }
13321
13322         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13323
13324 #if 0
13325         /* Unneeded, already done by tg3_get_invariants.  */
13326         tg3_switch_clocks(tp);
13327 #endif
13328
13329         ret = 0;
13330         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13331             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13332                 goto out;
13333
13334         /* It is best to perform DMA test with maximum write burst size
13335          * to expose the 5700/5701 write DMA bug.
13336          */
13337         saved_dma_rwctrl = tp->dma_rwctrl;
13338         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13339         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13340
13341         while (1) {
13342                 u32 *p = buf, i;
13343
13344                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13345                         p[i] = i;
13346
13347                 /* Send the buffer to the chip. */
13348                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13349                 if (ret) {
13350                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13351                         break;
13352                 }
13353
13354 #if 0
13355                 /* validate data reached card RAM correctly. */
13356                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13357                         u32 val;
13358                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13359                         if (le32_to_cpu(val) != p[i]) {
13360                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13361                                 /* ret = -ENODEV here? */
13362                         }
13363                         p[i] = 0;
13364                 }
13365 #endif
13366                 /* Now read it back. */
13367                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13368                 if (ret) {
13369                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13370
13371                         break;
13372                 }
13373
13374                 /* Verify it. */
13375                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13376                         if (p[i] == i)
13377                                 continue;
13378
13379                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13380                             DMA_RWCTRL_WRITE_BNDRY_16) {
13381                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13382                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13383                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13384                                 break;
13385                         } else {
13386                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13387                                 ret = -ENODEV;
13388                                 goto out;
13389                         }
13390                 }
13391
13392                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13393                         /* Success. */
13394                         ret = 0;
13395                         break;
13396                 }
13397         }
13398         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13399             DMA_RWCTRL_WRITE_BNDRY_16) {
13400                 static struct pci_device_id dma_wait_state_chipsets[] = {
13401                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13402                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13403                         { },
13404                 };
13405
13406                 /* DMA test passed without adjusting DMA boundary,
13407                  * now look for chipsets that are known to expose the
13408                  * DMA bug without failing the test.
13409                  */
13410                 if (pci_dev_present(dma_wait_state_chipsets)) {
13411                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13412                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13413                 }
13414                 else
13415                         /* Safe to use the calculated DMA boundary. */
13416                         tp->dma_rwctrl = saved_dma_rwctrl;
13417
13418                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13419         }
13420
13421 out:
13422         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13423 out_nofree:
13424         return ret;
13425 }
13426
13427 static void __devinit tg3_init_link_config(struct tg3 *tp)
13428 {
13429         tp->link_config.advertising =
13430                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13431                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13432                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13433                  ADVERTISED_Autoneg | ADVERTISED_MII);
13434         tp->link_config.speed = SPEED_INVALID;
13435         tp->link_config.duplex = DUPLEX_INVALID;
13436         tp->link_config.autoneg = AUTONEG_ENABLE;
13437         tp->link_config.active_speed = SPEED_INVALID;
13438         tp->link_config.active_duplex = DUPLEX_INVALID;
13439         tp->link_config.phy_is_low_power = 0;
13440         tp->link_config.orig_speed = SPEED_INVALID;
13441         tp->link_config.orig_duplex = DUPLEX_INVALID;
13442         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13443 }
13444
13445 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13446 {
13447         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13448                 tp->bufmgr_config.mbuf_read_dma_low_water =
13449                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13450                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13451                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13452                 tp->bufmgr_config.mbuf_high_water =
13453                         DEFAULT_MB_HIGH_WATER_5705;
13454                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13455                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13456                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13457                         tp->bufmgr_config.mbuf_high_water =
13458                                 DEFAULT_MB_HIGH_WATER_5906;
13459                 }
13460
13461                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13462                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13463                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13464                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13465                 tp->bufmgr_config.mbuf_high_water_jumbo =
13466                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13467         } else {
13468                 tp->bufmgr_config.mbuf_read_dma_low_water =
13469                         DEFAULT_MB_RDMA_LOW_WATER;
13470                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13471                         DEFAULT_MB_MACRX_LOW_WATER;
13472                 tp->bufmgr_config.mbuf_high_water =
13473                         DEFAULT_MB_HIGH_WATER;
13474
13475                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13476                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13477                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13478                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13479                 tp->bufmgr_config.mbuf_high_water_jumbo =
13480                         DEFAULT_MB_HIGH_WATER_JUMBO;
13481         }
13482
13483         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13484         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13485 }
13486
13487 static char * __devinit tg3_phy_string(struct tg3 *tp)
13488 {
13489         switch (tp->phy_id & PHY_ID_MASK) {
13490         case PHY_ID_BCM5400:    return "5400";
13491         case PHY_ID_BCM5401:    return "5401";
13492         case PHY_ID_BCM5411:    return "5411";
13493         case PHY_ID_BCM5701:    return "5701";
13494         case PHY_ID_BCM5703:    return "5703";
13495         case PHY_ID_BCM5704:    return "5704";
13496         case PHY_ID_BCM5705:    return "5705";
13497         case PHY_ID_BCM5750:    return "5750";
13498         case PHY_ID_BCM5752:    return "5752";
13499         case PHY_ID_BCM5714:    return "5714";
13500         case PHY_ID_BCM5780:    return "5780";
13501         case PHY_ID_BCM5755:    return "5755";
13502         case PHY_ID_BCM5787:    return "5787";
13503         case PHY_ID_BCM5784:    return "5784";
13504         case PHY_ID_BCM5756:    return "5722/5756";
13505         case PHY_ID_BCM5906:    return "5906";
13506         case PHY_ID_BCM5761:    return "5761";
13507         case PHY_ID_BCM8002:    return "8002/serdes";
13508         case 0:                 return "serdes";
13509         default:                return "unknown";
13510         }
13511 }
13512
13513 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13514 {
13515         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13516                 strcpy(str, "PCI Express");
13517                 return str;
13518         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13519                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13520
13521                 strcpy(str, "PCIX:");
13522
13523                 if ((clock_ctrl == 7) ||
13524                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13525                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13526                         strcat(str, "133MHz");
13527                 else if (clock_ctrl == 0)
13528                         strcat(str, "33MHz");
13529                 else if (clock_ctrl == 2)
13530                         strcat(str, "50MHz");
13531                 else if (clock_ctrl == 4)
13532                         strcat(str, "66MHz");
13533                 else if (clock_ctrl == 6)
13534                         strcat(str, "100MHz");
13535         } else {
13536                 strcpy(str, "PCI:");
13537                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13538                         strcat(str, "66MHz");
13539                 else
13540                         strcat(str, "33MHz");
13541         }
13542         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13543                 strcat(str, ":32-bit");
13544         else
13545                 strcat(str, ":64-bit");
13546         return str;
13547 }
13548
13549 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13550 {
13551         struct pci_dev *peer;
13552         unsigned int func, devnr = tp->pdev->devfn & ~7;
13553
13554         for (func = 0; func < 8; func++) {
13555                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13556                 if (peer && peer != tp->pdev)
13557                         break;
13558                 pci_dev_put(peer);
13559         }
13560         /* 5704 can be configured in single-port mode, set peer to
13561          * tp->pdev in that case.
13562          */
13563         if (!peer) {
13564                 peer = tp->pdev;
13565                 return peer;
13566         }
13567
13568         /*
13569          * We don't need to keep the refcount elevated; there's no way
13570          * to remove one half of this device without removing the other
13571          */
13572         pci_dev_put(peer);
13573
13574         return peer;
13575 }
13576
13577 static void __devinit tg3_init_coal(struct tg3 *tp)
13578 {
13579         struct ethtool_coalesce *ec = &tp->coal;
13580
13581         memset(ec, 0, sizeof(*ec));
13582         ec->cmd = ETHTOOL_GCOALESCE;
13583         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13584         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13585         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13586         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13587         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13588         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13589         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13590         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13591         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13592
13593         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13594                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13595                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13596                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13597                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13598                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13599         }
13600
13601         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13602                 ec->rx_coalesce_usecs_irq = 0;
13603                 ec->tx_coalesce_usecs_irq = 0;
13604                 ec->stats_block_coalesce_usecs = 0;
13605         }
13606 }
13607
13608 static const struct net_device_ops tg3_netdev_ops = {
13609         .ndo_open               = tg3_open,
13610         .ndo_stop               = tg3_close,
13611         .ndo_start_xmit         = tg3_start_xmit,
13612         .ndo_get_stats          = tg3_get_stats,
13613         .ndo_validate_addr      = eth_validate_addr,
13614         .ndo_set_multicast_list = tg3_set_rx_mode,
13615         .ndo_set_mac_address    = tg3_set_mac_addr,
13616         .ndo_do_ioctl           = tg3_ioctl,
13617         .ndo_tx_timeout         = tg3_tx_timeout,
13618         .ndo_change_mtu         = tg3_change_mtu,
13619 #if TG3_VLAN_TAG_USED
13620         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13621 #endif
13622 #ifdef CONFIG_NET_POLL_CONTROLLER
13623         .ndo_poll_controller    = tg3_poll_controller,
13624 #endif
13625 };
13626
13627 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13628         .ndo_open               = tg3_open,
13629         .ndo_stop               = tg3_close,
13630         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13631         .ndo_get_stats          = tg3_get_stats,
13632         .ndo_validate_addr      = eth_validate_addr,
13633         .ndo_set_multicast_list = tg3_set_rx_mode,
13634         .ndo_set_mac_address    = tg3_set_mac_addr,
13635         .ndo_do_ioctl           = tg3_ioctl,
13636         .ndo_tx_timeout         = tg3_tx_timeout,
13637         .ndo_change_mtu         = tg3_change_mtu,
13638 #if TG3_VLAN_TAG_USED
13639         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13640 #endif
13641 #ifdef CONFIG_NET_POLL_CONTROLLER
13642         .ndo_poll_controller    = tg3_poll_controller,
13643 #endif
13644 };
13645
13646 static int __devinit tg3_init_one(struct pci_dev *pdev,
13647                                   const struct pci_device_id *ent)
13648 {
13649         static int tg3_version_printed = 0;
13650         struct net_device *dev;
13651         struct tg3 *tp;
13652         int i, err, pm_cap;
13653         u32 sndmbx, rcvmbx, intmbx;
13654         char str[40];
13655         u64 dma_mask, persist_dma_mask;
13656
13657         if (tg3_version_printed++ == 0)
13658                 printk(KERN_INFO "%s", version);
13659
13660         err = pci_enable_device(pdev);
13661         if (err) {
13662                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13663                        "aborting.\n");
13664                 return err;
13665         }
13666
13667         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13668         if (err) {
13669                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13670                        "aborting.\n");
13671                 goto err_out_disable_pdev;
13672         }
13673
13674         pci_set_master(pdev);
13675
13676         /* Find power-management capability. */
13677         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13678         if (pm_cap == 0) {
13679                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13680                        "aborting.\n");
13681                 err = -EIO;
13682                 goto err_out_free_res;
13683         }
13684
13685         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13686         if (!dev) {
13687                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13688                 err = -ENOMEM;
13689                 goto err_out_free_res;
13690         }
13691
13692         SET_NETDEV_DEV(dev, &pdev->dev);
13693
13694 #if TG3_VLAN_TAG_USED
13695         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13696 #endif
13697
13698         tp = netdev_priv(dev);
13699         tp->pdev = pdev;
13700         tp->dev = dev;
13701         tp->pm_cap = pm_cap;
13702         tp->rx_mode = TG3_DEF_RX_MODE;
13703         tp->tx_mode = TG3_DEF_TX_MODE;
13704
13705         if (tg3_debug > 0)
13706                 tp->msg_enable = tg3_debug;
13707         else
13708                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13709
13710         /* The word/byte swap controls here control register access byte
13711          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13712          * setting below.
13713          */
13714         tp->misc_host_ctrl =
13715                 MISC_HOST_CTRL_MASK_PCI_INT |
13716                 MISC_HOST_CTRL_WORD_SWAP |
13717                 MISC_HOST_CTRL_INDIR_ACCESS |
13718                 MISC_HOST_CTRL_PCISTATE_RW;
13719
13720         /* The NONFRM (non-frame) byte/word swap controls take effect
13721          * on descriptor entries, anything which isn't packet data.
13722          *
13723          * The StrongARM chips on the board (one for tx, one for rx)
13724          * are running in big-endian mode.
13725          */
13726         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13727                         GRC_MODE_WSWAP_NONFRM_DATA);
13728 #ifdef __BIG_ENDIAN
13729         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13730 #endif
13731         spin_lock_init(&tp->lock);
13732         spin_lock_init(&tp->indirect_lock);
13733         INIT_WORK(&tp->reset_task, tg3_reset_task);
13734
13735         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13736         if (!tp->regs) {
13737                 printk(KERN_ERR PFX "Cannot map device registers, "
13738                        "aborting.\n");
13739                 err = -ENOMEM;
13740                 goto err_out_free_dev;
13741         }
13742
13743         tg3_init_link_config(tp);
13744
13745         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13746         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13747
13748         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13749         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13750         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13751         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13752                 struct tg3_napi *tnapi = &tp->napi[i];
13753
13754                 tnapi->tp = tp;
13755                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
13756
13757                 tnapi->int_mbox = intmbx;
13758                 if (i < 4)
13759                         intmbx += 0x8;
13760                 else
13761                         intmbx += 0x4;
13762
13763                 tnapi->consmbox = rcvmbx;
13764                 tnapi->prodmbox = sndmbx;
13765
13766                 if (i)
13767                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
13768                 else
13769                         tnapi->coal_now = HOSTCC_MODE_NOW;
13770
13771                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
13772                         break;
13773
13774                 /*
13775                  * If we support MSIX, we'll be using RSS.  If we're using
13776                  * RSS, the first vector only handles link interrupts and the
13777                  * remaining vectors handle rx and tx interrupts.  Reuse the
13778                  * mailbox values for the next iteration.  The values we setup
13779                  * above are still useful for the single vectored mode.
13780                  */
13781                 if (!i)
13782                         continue;
13783
13784                 rcvmbx += 0x8;
13785
13786                 if (sndmbx & 0x4)
13787                         sndmbx -= 0x4;
13788                 else
13789                         sndmbx += 0xc;
13790         }
13791
13792         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
13793         dev->ethtool_ops = &tg3_ethtool_ops;
13794         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13795         dev->irq = pdev->irq;
13796
13797         err = tg3_get_invariants(tp);
13798         if (err) {
13799                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13800                        "aborting.\n");
13801                 goto err_out_iounmap;
13802         }
13803
13804         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13805             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13806                 dev->netdev_ops = &tg3_netdev_ops;
13807         else
13808                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13809
13810
13811         /* The EPB bridge inside 5714, 5715, and 5780 and any
13812          * device behind the EPB cannot support DMA addresses > 40-bit.
13813          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13814          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13815          * do DMA address check in tg3_start_xmit().
13816          */
13817         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13818                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13819         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13820                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13821 #ifdef CONFIG_HIGHMEM
13822                 dma_mask = DMA_BIT_MASK(64);
13823 #endif
13824         } else
13825                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13826
13827         /* Configure DMA attributes. */
13828         if (dma_mask > DMA_BIT_MASK(32)) {
13829                 err = pci_set_dma_mask(pdev, dma_mask);
13830                 if (!err) {
13831                         dev->features |= NETIF_F_HIGHDMA;
13832                         err = pci_set_consistent_dma_mask(pdev,
13833                                                           persist_dma_mask);
13834                         if (err < 0) {
13835                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13836                                        "DMA for consistent allocations\n");
13837                                 goto err_out_iounmap;
13838                         }
13839                 }
13840         }
13841         if (err || dma_mask == DMA_BIT_MASK(32)) {
13842                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13843                 if (err) {
13844                         printk(KERN_ERR PFX "No usable DMA configuration, "
13845                                "aborting.\n");
13846                         goto err_out_iounmap;
13847                 }
13848         }
13849
13850         tg3_init_bufmgr_config(tp);
13851
13852         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13853                 tp->fw_needed = FIRMWARE_TG3;
13854
13855         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13856                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13857         }
13858         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13859             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13860             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13861             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13862             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13863                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13864         } else {
13865                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13866                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13867                         tp->fw_needed = FIRMWARE_TG3TSO5;
13868                 else
13869                         tp->fw_needed = FIRMWARE_TG3TSO;
13870         }
13871
13872         /* TSO is on by default on chips that support hardware TSO.
13873          * Firmware TSO on older chips gives lower performance, so it
13874          * is off by default, but can be enabled using ethtool.
13875          */
13876         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13877                 if (dev->features & NETIF_F_IP_CSUM)
13878                         dev->features |= NETIF_F_TSO;
13879                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13880                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13881                         dev->features |= NETIF_F_TSO6;
13882                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13883                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13884                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13885                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13886                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13887                         dev->features |= NETIF_F_TSO_ECN;
13888         }
13889
13890
13891         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13892             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13893             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13894                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13895                 tp->rx_pending = 63;
13896         }
13897
13898         err = tg3_get_device_address(tp);
13899         if (err) {
13900                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13901                        "aborting.\n");
13902                 goto err_out_fw;
13903         }
13904
13905         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13906                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13907                 if (!tp->aperegs) {
13908                         printk(KERN_ERR PFX "Cannot map APE registers, "
13909                                "aborting.\n");
13910                         err = -ENOMEM;
13911                         goto err_out_fw;
13912                 }
13913
13914                 tg3_ape_lock_init(tp);
13915
13916                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13917                         tg3_read_dash_ver(tp);
13918         }
13919
13920         /*
13921          * Reset chip in case UNDI or EFI driver did not shutdown
13922          * DMA self test will enable WDMAC and we'll see (spurious)
13923          * pending DMA on the PCI bus at that point.
13924          */
13925         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13926             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13927                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13928                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13929         }
13930
13931         err = tg3_test_dma(tp);
13932         if (err) {
13933                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13934                 goto err_out_apeunmap;
13935         }
13936
13937         /* flow control autonegotiation is default behavior */
13938         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13939         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13940
13941         tg3_init_coal(tp);
13942
13943         pci_set_drvdata(pdev, dev);
13944
13945         err = register_netdev(dev);
13946         if (err) {
13947                 printk(KERN_ERR PFX "Cannot register net device, "
13948                        "aborting.\n");
13949                 goto err_out_apeunmap;
13950         }
13951
13952         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13953                dev->name,
13954                tp->board_part_number,
13955                tp->pci_chip_rev_id,
13956                tg3_bus_string(tp, str),
13957                dev->dev_addr);
13958
13959         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13960                 printk(KERN_INFO
13961                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13962                        tp->dev->name,
13963                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13964                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13965         else
13966                 printk(KERN_INFO
13967                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13968                        tp->dev->name, tg3_phy_string(tp),
13969                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13970                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13971                          "10/100/1000Base-T")),
13972                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13973
13974         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13975                dev->name,
13976                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13977                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13978                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13979                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13980                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13981         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13982                dev->name, tp->dma_rwctrl,
13983                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13984                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13985
13986         return 0;
13987
13988 err_out_apeunmap:
13989         if (tp->aperegs) {
13990                 iounmap(tp->aperegs);
13991                 tp->aperegs = NULL;
13992         }
13993
13994 err_out_fw:
13995         if (tp->fw)
13996                 release_firmware(tp->fw);
13997
13998 err_out_iounmap:
13999         if (tp->regs) {
14000                 iounmap(tp->regs);
14001                 tp->regs = NULL;
14002         }
14003
14004 err_out_free_dev:
14005         free_netdev(dev);
14006
14007 err_out_free_res:
14008         pci_release_regions(pdev);
14009
14010 err_out_disable_pdev:
14011         pci_disable_device(pdev);
14012         pci_set_drvdata(pdev, NULL);
14013         return err;
14014 }
14015
14016 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14017 {
14018         struct net_device *dev = pci_get_drvdata(pdev);
14019
14020         if (dev) {
14021                 struct tg3 *tp = netdev_priv(dev);
14022
14023                 if (tp->fw)
14024                         release_firmware(tp->fw);
14025
14026                 flush_scheduled_work();
14027
14028                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14029                         tg3_phy_fini(tp);
14030                         tg3_mdio_fini(tp);
14031                 }
14032
14033                 unregister_netdev(dev);
14034                 if (tp->aperegs) {
14035                         iounmap(tp->aperegs);
14036                         tp->aperegs = NULL;
14037                 }
14038                 if (tp->regs) {
14039                         iounmap(tp->regs);
14040                         tp->regs = NULL;
14041                 }
14042                 free_netdev(dev);
14043                 pci_release_regions(pdev);
14044                 pci_disable_device(pdev);
14045                 pci_set_drvdata(pdev, NULL);
14046         }
14047 }
14048
14049 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14050 {
14051         struct net_device *dev = pci_get_drvdata(pdev);
14052         struct tg3 *tp = netdev_priv(dev);
14053         pci_power_t target_state;
14054         int err;
14055
14056         /* PCI register 4 needs to be saved whether netif_running() or not.
14057          * MSI address and data need to be saved if using MSI and
14058          * netif_running().
14059          */
14060         pci_save_state(pdev);
14061
14062         if (!netif_running(dev))
14063                 return 0;
14064
14065         flush_scheduled_work();
14066         tg3_phy_stop(tp);
14067         tg3_netif_stop(tp);
14068
14069         del_timer_sync(&tp->timer);
14070
14071         tg3_full_lock(tp, 1);
14072         tg3_disable_ints(tp);
14073         tg3_full_unlock(tp);
14074
14075         netif_device_detach(dev);
14076
14077         tg3_full_lock(tp, 0);
14078         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14079         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14080         tg3_full_unlock(tp);
14081
14082         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14083
14084         err = tg3_set_power_state(tp, target_state);
14085         if (err) {
14086                 int err2;
14087
14088                 tg3_full_lock(tp, 0);
14089
14090                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14091                 err2 = tg3_restart_hw(tp, 1);
14092                 if (err2)
14093                         goto out;
14094
14095                 tp->timer.expires = jiffies + tp->timer_offset;
14096                 add_timer(&tp->timer);
14097
14098                 netif_device_attach(dev);
14099                 tg3_netif_start(tp);
14100
14101 out:
14102                 tg3_full_unlock(tp);
14103
14104                 if (!err2)
14105                         tg3_phy_start(tp);
14106         }
14107
14108         return err;
14109 }
14110
14111 static int tg3_resume(struct pci_dev *pdev)
14112 {
14113         struct net_device *dev = pci_get_drvdata(pdev);
14114         struct tg3 *tp = netdev_priv(dev);
14115         int err;
14116
14117         pci_restore_state(tp->pdev);
14118
14119         if (!netif_running(dev))
14120                 return 0;
14121
14122         err = tg3_set_power_state(tp, PCI_D0);
14123         if (err)
14124                 return err;
14125
14126         netif_device_attach(dev);
14127
14128         tg3_full_lock(tp, 0);
14129
14130         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14131         err = tg3_restart_hw(tp, 1);
14132         if (err)
14133                 goto out;
14134
14135         tp->timer.expires = jiffies + tp->timer_offset;
14136         add_timer(&tp->timer);
14137
14138         tg3_netif_start(tp);
14139
14140 out:
14141         tg3_full_unlock(tp);
14142
14143         if (!err)
14144                 tg3_phy_start(tp);
14145
14146         return err;
14147 }
14148
14149 static struct pci_driver tg3_driver = {
14150         .name           = DRV_MODULE_NAME,
14151         .id_table       = tg3_pci_tbl,
14152         .probe          = tg3_init_one,
14153         .remove         = __devexit_p(tg3_remove_one),
14154         .suspend        = tg3_suspend,
14155         .resume         = tg3_resume
14156 };
14157
14158 static int __init tg3_init(void)
14159 {
14160         return pci_register_driver(&tg3_driver);
14161 }
14162
14163 static void __exit tg3_cleanup(void)
14164 {
14165         pci_unregister_driver(&tg3_driver);
14166 }
14167
14168 module_init(tg3_init);
14169 module_exit(tg3_cleanup);