drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/ip.h>
  38 #include <linux/tcp.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/prefetch.h>
  41 #include <linux/dma-mapping.h>
  42
  43 #include <net/checksum.h>
  44 #include <net/ip.h>
  45
  46 #include <asm/system.h>
  47 #include <asm/io.h>
  48 #include <asm/byteorder.h>
  49 #include <asm/uaccess.h>
  50
  51 #ifdef CONFIG_SPARC
  52 #include <asm/idprom.h>
  53 #include <asm/prom.h>
  54 #endif
  55
  56 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  57 #define TG3_VLAN_TAG_USED 1
  58 #else
  59 #define TG3_VLAN_TAG_USED 0
  60 #endif
  61
  62 #define TG3_TSO_SUPPORT 1
  63
  64 #include "tg3.h"
  65
  66 #define DRV_MODULE_NAME         "tg3"
  67 #define PFX DRV_MODULE_NAME     ": "
  68 #define DRV_MODULE_VERSION      "3.92"
  69 #define DRV_MODULE_RELDATE      "May 2, 2008"
  70
  71 #define TG3_DEF_MAC_MODE        0
  72 #define TG3_DEF_RX_MODE         0
  73 #define TG3_DEF_TX_MODE         0
  74 #define TG3_DEF_MSG_ENABLE        \
  75         (NETIF_MSG_DRV          | \
  76          NETIF_MSG_PROBE        | \
  77          NETIF_MSG_LINK         | \
  78          NETIF_MSG_TIMER        | \
  79          NETIF_MSG_IFDOWN       | \
  80          NETIF_MSG_IFUP         | \
  81          NETIF_MSG_RX_ERR       | \
  82          NETIF_MSG_TX_ERR)
  83
  84 /* length of time before we decide the hardware is borked,
  85  * and dev->tx_timeout() should be called to fix the problem
  86  */
  87 #define TG3_TX_TIMEOUT                  (5 * HZ)
  88
  89 /* hardware minimum and maximum for a single frame's data payload */
  90 #define TG3_MIN_MTU                     60
  91 #define TG3_MAX_MTU(tp) \
  92         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  93
  94 /* These numbers seem to be hard coded in the NIC firmware somehow.
  95  * You can't change the ring sizes, but you can change where you place
  96  * them in the NIC onboard memory.
  97  */
  98 #define TG3_RX_RING_SIZE                512
  99 #define TG3_DEF_RX_RING_PENDING         200
 100 #define TG3_RX_JUMBO_RING_SIZE          256
 101 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 102
 103 /* Do not place this n-ring entries value into the tp struct itself,
 104  * we really want to expose these constants to GCC so that modulo et
 105  * al.  operations are done with shifts and masks instead of with
 106  * hw multiply/modulo instructions.  Another solution would be to
 107  * replace things like '% foo' with '& (foo - 1)'.
 108  */
 109 #define TG3_RX_RCB_RING_SIZE(tp)        \
 110         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 111
 112 #define TG3_TX_RING_SIZE                512
 113 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 114
 115 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 116                                  TG3_RX_RING_SIZE)
 117 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 118                                  TG3_RX_JUMBO_RING_SIZE)
 119 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 120                                    TG3_RX_RCB_RING_SIZE(tp))
 121 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 122                                  TG3_TX_RING_SIZE)
 123 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 124
 125 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 126 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 127
 128 /* minimum number of free TX descriptors required to wake up TX process */
 129 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 130
 131 /* number of ETHTOOL_GSTATS u64's */
 132 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 133
 134 #define TG3_NUM_TEST            6
 135
 136 static char version[] __devinitdata =
 137         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 138
 139 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 140 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 141 MODULE_LICENSE("GPL");
 142 MODULE_VERSION(DRV_MODULE_VERSION);
 143
 144 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 145 module_param(tg3_debug, int, 0);
 146 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 147
 148 static struct pci_device_id tg3_pci_tbl[] = {
 149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 214         {}
 215 };
 216
 217 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 218
 219 static const struct {
 220         const char string[ETH_GSTRING_LEN];
 221 } ethtool_stats_keys[TG3_NUM_STATS] = {
 222         { "rx_octets" },
 223         { "rx_fragments" },
 224         { "rx_ucast_packets" },
 225         { "rx_mcast_packets" },
 226         { "rx_bcast_packets" },
 227         { "rx_fcs_errors" },
 228         { "rx_align_errors" },
 229         { "rx_xon_pause_rcvd" },
 230         { "rx_xoff_pause_rcvd" },
 231         { "rx_mac_ctrl_rcvd" },
 232         { "rx_xoff_entered" },
 233         { "rx_frame_too_long_errors" },
 234         { "rx_jabbers" },
 235         { "rx_undersize_packets" },
 236         { "rx_in_length_errors" },
 237         { "rx_out_length_errors" },
 238         { "rx_64_or_less_octet_packets" },
 239         { "rx_65_to_127_octet_packets" },
 240         { "rx_128_to_255_octet_packets" },
 241         { "rx_256_to_511_octet_packets" },
 242         { "rx_512_to_1023_octet_packets" },
 243         { "rx_1024_to_1522_octet_packets" },
 244         { "rx_1523_to_2047_octet_packets" },
 245         { "rx_2048_to_4095_octet_packets" },
 246         { "rx_4096_to_8191_octet_packets" },
 247         { "rx_8192_to_9022_octet_packets" },
 248
 249         { "tx_octets" },
 250         { "tx_collisions" },
 251
 252         { "tx_xon_sent" },
 253         { "tx_xoff_sent" },
 254         { "tx_flow_control" },
 255         { "tx_mac_errors" },
 256         { "tx_single_collisions" },
 257         { "tx_mult_collisions" },
 258         { "tx_deferred" },
 259         { "tx_excessive_collisions" },
 260         { "tx_late_collisions" },
 261         { "tx_collide_2times" },
 262         { "tx_collide_3times" },
 263         { "tx_collide_4times" },
 264         { "tx_collide_5times" },
 265         { "tx_collide_6times" },
 266         { "tx_collide_7times" },
 267         { "tx_collide_8times" },
 268         { "tx_collide_9times" },
 269         { "tx_collide_10times" },
 270         { "tx_collide_11times" },
 271         { "tx_collide_12times" },
 272         { "tx_collide_13times" },
 273         { "tx_collide_14times" },
 274         { "tx_collide_15times" },
 275         { "tx_ucast_packets" },
 276         { "tx_mcast_packets" },
 277         { "tx_bcast_packets" },
 278         { "tx_carrier_sense_errors" },
 279         { "tx_discards" },
 280         { "tx_errors" },
 281
 282         { "dma_writeq_full" },
 283         { "dma_write_prioq_full" },
 284         { "rxbds_empty" },
 285         { "rx_discards" },
 286         { "rx_errors" },
 287         { "rx_threshold_hit" },
 288
 289         { "dma_readq_full" },
 290         { "dma_read_prioq_full" },
 291         { "tx_comp_queue_full" },
 292
 293         { "ring_set_send_prod_index" },
 294         { "ring_status_update" },
 295         { "nic_irqs" },
 296         { "nic_avoided_irqs" },
 297         { "nic_tx_threshold_hit" }
 298 };
 299
 300 static const struct {
 301         const char string[ETH_GSTRING_LEN];
 302 } ethtool_test_keys[TG3_NUM_TEST] = {
 303         { "nvram test     (online) " },
 304         { "link test      (online) " },
 305         { "register test  (offline)" },
 306         { "memory test    (offline)" },
 307         { "loopback test  (offline)" },
 308         { "interrupt test (offline)" },
 309 };
 310
 311 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 312 {
 313         writel(val, tp->regs + off);
 314 }
 315
 316 static u32 tg3_read32(struct tg3 *tp, u32 off)
 317 {
 318         return (readl(tp->regs + off));
 319 }
 320
 321 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 322 {
 323         writel(val, tp->aperegs + off);
 324 }
 325
 326 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 327 {
 328         return (readl(tp->aperegs + off));
 329 }
 330
 331 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 332 {
 333         unsigned long flags;
 334
 335         spin_lock_irqsave(&tp->indirect_lock, flags);
 336         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 337         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 338         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 339 }
 340
 341 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 342 {
 343         writel(val, tp->regs + off);
 344         readl(tp->regs + off);
 345 }
 346
 347 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 348 {
 349         unsigned long flags;
 350         u32 val;
 351
 352         spin_lock_irqsave(&tp->indirect_lock, flags);
 353         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 354         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 355         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 356         return val;
 357 }
 358
 359 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 360 {
 361         unsigned long flags;
 362
 363         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 364                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 365                                        TG3_64BIT_REG_LOW, val);
 366                 return;
 367         }
 368         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 369                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 370                                        TG3_64BIT_REG_LOW, val);
 371                 return;
 372         }
 373
 374         spin_lock_irqsave(&tp->indirect_lock, flags);
 375         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 376         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 377         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 378
 379         /* In indirect mode when disabling interrupts, we also need
 380          * to clear the interrupt bit in the GRC local ctrl register.
 381          */
 382         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 383             (val == 0x1)) {
 384                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 385                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 386         }
 387 }
 388
 389 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 390 {
 391         unsigned long flags;
 392         u32 val;
 393
 394         spin_lock_irqsave(&tp->indirect_lock, flags);
 395         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 396         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 397         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 398         return val;
 399 }
 400
 401 /* usec_wait specifies the wait time in usec when writing to certain registers
 402  * where it is unsafe to read back the register without some delay.
 403  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 404  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 405  */
 406 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 407 {
 408         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 409             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 410                 /* Non-posted methods */
 411                 tp->write32(tp, off, val);
 412         else {
 413                 /* Posted method */
 414                 tg3_write32(tp, off, val);
 415                 if (usec_wait)
 416                         udelay(usec_wait);
 417                 tp->read32(tp, off);
 418         }
 419         /* Wait again after the read for the posted method to guarantee that
 420          * the wait time is met.
 421          */
 422         if (usec_wait)
 423                 udelay(usec_wait);
 424 }
 425
 426 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 427 {
 428         tp->write32_mbox(tp, off, val);
 429         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 430             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 431                 tp->read32_mbox(tp, off);
 432 }
 433
 434 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 435 {
 436         void __iomem *mbox = tp->regs + off;
 437         writel(val, mbox);
 438         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 439                 writel(val, mbox);
 440         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 441                 readl(mbox);
 442 }
 443
 444 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 445 {
 446         return (readl(tp->regs + off + GRCMBOX_BASE));
 447 }
 448
 449 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 450 {
 451         writel(val, tp->regs + off + GRCMBOX_BASE);
 452 }
 453
 454 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 455 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 456 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 457 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 458 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 459
 460 #define tw32(reg,val)           tp->write32(tp, reg, val)
 461 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 462 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 463 #define tr32(reg)               tp->read32(tp, reg)
 464
 465 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 466 {
 467         unsigned long flags;
 468
 469         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 470             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 471                 return;
 472
 473         spin_lock_irqsave(&tp->indirect_lock, flags);
 474         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 475                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 476                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 477
 478                 /* Always leave this as zero. */
 479                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 480         } else {
 481                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 482                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 483
 484                 /* Always leave this as zero. */
 485                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 486         }
 487         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 488 }
 489
 490 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 491 {
 492         unsigned long flags;
 493
 494         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 495             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 496                 *val = 0;
 497                 return;
 498         }
 499
 500         spin_lock_irqsave(&tp->indirect_lock, flags);
 501         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 502                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 503                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 504
 505                 /* Always leave this as zero. */
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 507         } else {
 508                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 509                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 510
 511                 /* Always leave this as zero. */
 512                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 513         }
 514         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 515 }
 516
 517 static void tg3_ape_lock_init(struct tg3 *tp)
 518 {
 519         int i;
 520
 521         /* Make sure the driver hasn't any stale locks. */
 522         for (i = 0; i < 8; i++)
 523                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 524                                 APE_LOCK_GRANT_DRIVER);
 525 }
 526
 527 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 528 {
 529         int i, off;
 530         int ret = 0;
 531         u32 status;
 532
 533         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 534                 return 0;
 535
 536         switch (locknum) {
 537                 case TG3_APE_LOCK_MEM:
 538                         break;
 539                 default:
 540                         return -EINVAL;
 541         }
 542
 543         off = 4 * locknum;
 544
 545         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 546
 547         /* Wait for up to 1 millisecond to acquire lock. */
 548         for (i = 0; i < 100; i++) {
 549                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 550                 if (status == APE_LOCK_GRANT_DRIVER)
 551                         break;
 552                 udelay(10);
 553         }
 554
 555         if (status != APE_LOCK_GRANT_DRIVER) {
 556                 /* Revoke the lock request. */
 557                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 558                                 APE_LOCK_GRANT_DRIVER);
 559
 560                 ret = -EBUSY;
 561         }
 562
 563         return ret;
 564 }
 565
 566 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 567 {
 568         int off;
 569
 570         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 571                 return;
 572
 573         switch (locknum) {
 574                 case TG3_APE_LOCK_MEM:
 575                         break;
 576                 default:
 577                         return;
 578         }
 579
 580         off = 4 * locknum;
 581         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 582 }
 583
 584 static void tg3_disable_ints(struct tg3 *tp)
 585 {
 586         tw32(TG3PCI_MISC_HOST_CTRL,
 587              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 588         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 589 }
 590
 591 static inline void tg3_cond_int(struct tg3 *tp)
 592 {
 593         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 594             (tp->hw_status->status & SD_STATUS_UPDATED))
 595                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 596         else
 597                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 598                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 599 }
 600
 601 static void tg3_enable_ints(struct tg3 *tp)
 602 {
 603         tp->irq_sync = 0;
 604         wmb();
 605
 606         tw32(TG3PCI_MISC_HOST_CTRL,
 607              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 608         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 609                        (tp->last_tag << 24));
 610         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 611                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 612                                (tp->last_tag << 24));
 613         tg3_cond_int(tp);
 614 }
 615
 616 static inline unsigned int tg3_has_work(struct tg3 *tp)
 617 {
 618         struct tg3_hw_status *sblk = tp->hw_status;
 619         unsigned int work_exists = 0;
 620
 621         /* check for phy events */
 622         if (!(tp->tg3_flags &
 623               (TG3_FLAG_USE_LINKCHG_REG |
 624                TG3_FLAG_POLL_SERDES))) {
 625                 if (sblk->status & SD_STATUS_LINK_CHG)
 626                         work_exists = 1;
 627         }
 628         /* check for RX/TX work to do */
 629         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 630             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 631                 work_exists = 1;
 632
 633         return work_exists;
 634 }
 635
 636 /* tg3_restart_ints
 637  *  similar to tg3_enable_ints, but it accurately determines whether there
 638  *  is new work pending and can return without flushing the PIO write
 639  *  which reenables interrupts
 640  */
 641 static void tg3_restart_ints(struct tg3 *tp)
 642 {
 643         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 644                      tp->last_tag << 24);
 645         mmiowb();
 646
 647         /* When doing tagged status, this work check is unnecessary.
 648          * The last_tag we write above tells the chip which piece of
 649          * work we've completed.
 650          */
 651         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 652             tg3_has_work(tp))
 653                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 654                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 655 }
 656
 657 static inline void tg3_netif_stop(struct tg3 *tp)
 658 {
 659         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 660         napi_disable(&tp->napi);
 661         netif_tx_disable(tp->dev);
 662 }
 663
 664 static inline void tg3_netif_start(struct tg3 *tp)
 665 {
 666         netif_wake_queue(tp->dev);
 667         /* NOTE: unconditional netif_wake_queue is only appropriate
 668          * so long as all callers are assured to have free tx slots
 669          * (such as after tg3_init_hw)
 670          */
 671         napi_enable(&tp->napi);
 672         tp->hw_status->status |= SD_STATUS_UPDATED;
 673         tg3_enable_ints(tp);
 674 }
 675
 676 static void tg3_switch_clocks(struct tg3 *tp)
 677 {
 678         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 679         u32 orig_clock_ctrl;
 680
 681         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 682             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 683                 return;
 684
 685         orig_clock_ctrl = clock_ctrl;
 686         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 687                        CLOCK_CTRL_CLKRUN_OENABLE |
 688                        0x1f);
 689         tp->pci_clock_ctrl = clock_ctrl;
 690
 691         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 692                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 693                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 694                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 695                 }
 696         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 697                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 698                             clock_ctrl |
 699                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 700                             40);
 701                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 702                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 703                             40);
 704         }
 705         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 706 }
 707
 708 #define PHY_BUSY_LOOPS  5000
 709
 710 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 711 {
 712         u32 frame_val;
 713         unsigned int loops;
 714         int ret;
 715
 716         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 717                 tw32_f(MAC_MI_MODE,
 718                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 719                 udelay(80);
 720         }
 721
 722         *val = 0x0;
 723
 724         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 725                       MI_COM_PHY_ADDR_MASK);
 726         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 727                       MI_COM_REG_ADDR_MASK);
 728         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 729
 730         tw32_f(MAC_MI_COM, frame_val);
 731
 732         loops = PHY_BUSY_LOOPS;
 733         while (loops != 0) {
 734                 udelay(10);
 735                 frame_val = tr32(MAC_MI_COM);
 736
 737                 if ((frame_val & MI_COM_BUSY) == 0) {
 738                         udelay(5);
 739                         frame_val = tr32(MAC_MI_COM);
 740                         break;
 741                 }
 742                 loops -= 1;
 743         }
 744
 745         ret = -EBUSY;
 746         if (loops != 0) {
 747                 *val = frame_val & MI_COM_DATA_MASK;
 748                 ret = 0;
 749         }
 750
 751         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 752                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 753                 udelay(80);
 754         }
 755
 756         return ret;
 757 }
 758
 759 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 760 {
 761         u32 frame_val;
 762         unsigned int loops;
 763         int ret;
 764
 765         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 766             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 767                 return 0;
 768
 769         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 770                 tw32_f(MAC_MI_MODE,
 771                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 772                 udelay(80);
 773         }
 774
 775         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 776                       MI_COM_PHY_ADDR_MASK);
 777         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 778                       MI_COM_REG_ADDR_MASK);
 779         frame_val |= (val & MI_COM_DATA_MASK);
 780         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 781
 782         tw32_f(MAC_MI_COM, frame_val);
 783
 784         loops = PHY_BUSY_LOOPS;
 785         while (loops != 0) {
 786                 udelay(10);
 787                 frame_val = tr32(MAC_MI_COM);
 788                 if ((frame_val & MI_COM_BUSY) == 0) {
 789                         udelay(5);
 790                         frame_val = tr32(MAC_MI_COM);
 791                         break;
 792                 }
 793                 loops -= 1;
 794         }
 795
 796         ret = -EBUSY;
 797         if (loops != 0)
 798                 ret = 0;
 799
 800         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 801                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 802                 udelay(80);
 803         }
 804
 805         return ret;
 806 }
 807
 808 static int tg3_bmcr_reset(struct tg3 *tp)
 809 {
 810         u32 phy_control;
 811         int limit, err;
 812
 813         /* OK, reset it, and poll the BMCR_RESET bit until it
 814          * clears or we time out.
 815          */
 816         phy_control = BMCR_RESET;
 817         err = tg3_writephy(tp, MII_BMCR, phy_control);
 818         if (err != 0)
 819                 return -EBUSY;
 820
 821         limit = 5000;
 822         while (limit--) {
 823                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 824                 if (err != 0)
 825                         return -EBUSY;
 826
 827                 if ((phy_control & BMCR_RESET) == 0) {
 828                         udelay(40);
 829                         break;
 830                 }
 831                 udelay(10);
 832         }
 833         if (limit <= 0)
 834                 return -EBUSY;
 835
 836         return 0;
 837 }
 838
 839 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 840 {
 841         struct tg3 *tp = (struct tg3 *)bp->priv;
 842         u32 val;
 843
 844         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 845                 return -EAGAIN;
 846
 847         if (tg3_readphy(tp, reg, &val))
 848                 return -EIO;
 849
 850         return val;
 851 }
 852
 853 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 854 {
 855         struct tg3 *tp = (struct tg3 *)bp->priv;
 856
 857         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 858                 return -EAGAIN;
 859
 860         if (tg3_writephy(tp, reg, val))
 861                 return -EIO;
 862
 863         return 0;
 864 }
 865
 866 static int tg3_mdio_reset(struct mii_bus *bp)
 867 {
 868         return 0;
 869 }
 870
 871 static void tg3_mdio_start(struct tg3 *tp)
 872 {
 873         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 874                 mutex_lock(&tp->mdio_bus.mdio_lock);
 875                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 876                 mutex_unlock(&tp->mdio_bus.mdio_lock);
 877         }
 878
 879         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 880         tw32_f(MAC_MI_MODE, tp->mi_mode);
 881         udelay(80);
 882 }
 883
 884 static void tg3_mdio_stop(struct tg3 *tp)
 885 {
 886         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 887                 mutex_lock(&tp->mdio_bus.mdio_lock);
 888                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
 889                 mutex_unlock(&tp->mdio_bus.mdio_lock);
 890         }
 891 }
 892
 893 static int tg3_mdio_init(struct tg3 *tp)
 894 {
 895         int i;
 896         u32 reg;
 897         struct mii_bus *mdio_bus = &tp->mdio_bus;
 898
 899         tg3_mdio_start(tp);
 900
 901         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
 902             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
 903                 return 0;
 904
 905         memset(mdio_bus, 0, sizeof(*mdio_bus));
 906
 907         mdio_bus->name     = "tg3 mdio bus";
 908         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
 909                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
 910         mdio_bus->priv     = tp;
 911         mdio_bus->dev      = &tp->pdev->dev;
 912         mdio_bus->read     = &tg3_mdio_read;
 913         mdio_bus->write    = &tg3_mdio_write;
 914         mdio_bus->reset    = &tg3_mdio_reset;
 915         mdio_bus->phy_mask = ~(1 << PHY_ADDR);
 916         mdio_bus->irq      = &tp->mdio_irq[0];
 917
 918         for (i = 0; i < PHY_MAX_ADDR; i++)
 919                 mdio_bus->irq[i] = PHY_POLL;
 920
 921         /* The bus registration will look for all the PHYs on the mdio bus.
 922          * Unfortunately, it does not ensure the PHY is powered up before
 923          * accessing the PHY ID registers.  A chip reset is the
 924          * quickest way to bring the device back to an operational state..
 925          */
 926         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
 927                 tg3_bmcr_reset(tp);
 928
 929         i = mdiobus_register(mdio_bus);
 930         if (!i)
 931                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
 932         else
 933                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
 934                         tp->dev->name, i);
 935
 936         return i;
 937 }
 938
 939 static void tg3_mdio_fini(struct tg3 *tp)
 940 {
 941         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 942                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
 943                 mdiobus_unregister(&tp->mdio_bus);
 944                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 945         }
 946 }
 947
 948 /* tp->lock is held. */
 949 static void tg3_wait_for_event_ack(struct tg3 *tp)
 950 {
 951         int i;
 952
 953         /* Wait for up to 2.5 milliseconds */
 954         for (i = 0; i < 250000; i++) {
 955                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
 956                         break;
 957                 udelay(10);
 958         }
 959 }
 960
 961 /* tp->lock is held. */
 962 static void tg3_ump_link_report(struct tg3 *tp)
 963 {
 964         u32 reg;
 965         u32 val;
 966
 967         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
 968             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
 969                 return;
 970
 971         tg3_wait_for_event_ack(tp);
 972
 973         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
 974
 975         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
 976
 977         val = 0;
 978         if (!tg3_readphy(tp, MII_BMCR, &reg))
 979                 val = reg << 16;
 980         if (!tg3_readphy(tp, MII_BMSR, &reg))
 981                 val |= (reg & 0xffff);
 982         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
 983
 984         val = 0;
 985         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
 986                 val = reg << 16;
 987         if (!tg3_readphy(tp, MII_LPA, &reg))
 988                 val |= (reg & 0xffff);
 989         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
 990
 991         val = 0;
 992         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
 993                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
 994                         val = reg << 16;
 995                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
 996                         val |= (reg & 0xffff);
 997         }
 998         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
 999
1000         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1001                 val = reg << 16;
1002         else
1003                 val = 0;
1004         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1005
1006         val = tr32(GRC_RX_CPU_EVENT);
1007         val |= GRC_RX_CPU_DRIVER_EVENT;
1008         tw32_f(GRC_RX_CPU_EVENT, val);
1009 }
1010
1011 static void tg3_link_report(struct tg3 *tp)
1012 {
1013         if (!netif_carrier_ok(tp->dev)) {
1014                 if (netif_msg_link(tp))
1015                         printk(KERN_INFO PFX "%s: Link is down.\n",
1016                                tp->dev->name);
1017                 tg3_ump_link_report(tp);
1018         } else if (netif_msg_link(tp)) {
1019                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1020                        tp->dev->name,
1021                        (tp->link_config.active_speed == SPEED_1000 ?
1022                         1000 :
1023                         (tp->link_config.active_speed == SPEED_100 ?
1024                          100 : 10)),
1025                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1026                         "full" : "half"));
1027
1028                 printk(KERN_INFO PFX
1029                        "%s: Flow control is %s for TX and %s for RX.\n",
1030                        tp->dev->name,
1031                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1032                        "on" : "off",
1033                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1034                        "on" : "off");
1035                 tg3_ump_link_report(tp);
1036         }
1037 }
1038
1039 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1040 {
1041         u16 miireg;
1042
1043         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1044                 miireg = ADVERTISE_PAUSE_CAP;
1045         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1046                 miireg = ADVERTISE_PAUSE_ASYM;
1047         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1048                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1049         else
1050                 miireg = 0;
1051
1052         return miireg;
1053 }
1054
1055 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1056 {
1057         u16 miireg;
1058
1059         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1060                 miireg = ADVERTISE_1000XPAUSE;
1061         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1062                 miireg = ADVERTISE_1000XPSE_ASYM;
1063         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1064                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1065         else
1066                 miireg = 0;
1067
1068         return miireg;
1069 }
1070
1071 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1072 {
1073         u8 cap = 0;
1074
1075         if (lcladv & ADVERTISE_PAUSE_CAP) {
1076                 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1077                         if (rmtadv & LPA_PAUSE_CAP)
1078                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1079                         else if (rmtadv & LPA_PAUSE_ASYM)
1080                                 cap = TG3_FLOW_CTRL_RX;
1081                 } else {
1082                         if (rmtadv & LPA_PAUSE_CAP)
1083                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1084                 }
1085         } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1086                 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1087                         cap = TG3_FLOW_CTRL_TX;
1088         }
1089
1090         return cap;
1091 }
1092
1093 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1094 {
1095         u8 cap = 0;
1096
1097         if (lcladv & ADVERTISE_1000XPAUSE) {
1098                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1099                         if (rmtadv & LPA_1000XPAUSE)
1100                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1101                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1102                                 cap = TG3_FLOW_CTRL_RX;
1103                 } else {
1104                         if (rmtadv & LPA_1000XPAUSE)
1105                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1106                 }
1107         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1108                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1109                         cap = TG3_FLOW_CTRL_TX;
1110         }
1111
1112         return cap;
1113 }
1114
1115 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1116 {
1117         u8 autoneg;
1118         u8 flowctrl = 0;
1119         u32 old_rx_mode = tp->rx_mode;
1120         u32 old_tx_mode = tp->tx_mode;
1121
1122         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1123                 autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
1124         else
1125                 autoneg = tp->link_config.autoneg;
1126
1127         if (autoneg == AUTONEG_ENABLE &&
1128             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1129                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1130                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1131                 else
1132                         flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1133         } else
1134                 flowctrl = tp->link_config.flowctrl;
1135
1136         tp->link_config.active_flowctrl = flowctrl;
1137
1138         if (flowctrl & TG3_FLOW_CTRL_RX)
1139                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1140         else
1141                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1142
1143         if (old_rx_mode != tp->rx_mode)
1144                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1145
1146         if (flowctrl & TG3_FLOW_CTRL_TX)
1147                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1148         else
1149                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1150
1151         if (old_tx_mode != tp->tx_mode)
1152                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1153 }
1154
1155 static void tg3_adjust_link(struct net_device *dev)
1156 {
1157         u8 oldflowctrl, linkmesg = 0;
1158         u32 mac_mode, lcl_adv, rmt_adv;
1159         struct tg3 *tp = netdev_priv(dev);
1160         struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1161
1162         spin_lock(&tp->lock);
1163
1164         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1165                                     MAC_MODE_HALF_DUPLEX);
1166
1167         oldflowctrl = tp->link_config.active_flowctrl;
1168
1169         if (phydev->link) {
1170                 lcl_adv = 0;
1171                 rmt_adv = 0;
1172
1173                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1174                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1175                 else
1176                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1177
1178                 if (phydev->duplex == DUPLEX_HALF)
1179                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1180                 else {
1181                         lcl_adv = tg3_advert_flowctrl_1000T(
1182                                   tp->link_config.flowctrl);
1183
1184                         if (phydev->pause)
1185                                 rmt_adv = LPA_PAUSE_CAP;
1186                         if (phydev->asym_pause)
1187                                 rmt_adv |= LPA_PAUSE_ASYM;
1188                 }
1189
1190                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1191         } else
1192                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1193
1194         if (mac_mode != tp->mac_mode) {
1195                 tp->mac_mode = mac_mode;
1196                 tw32_f(MAC_MODE, tp->mac_mode);
1197                 udelay(40);
1198         }
1199
1200         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1201                 tw32(MAC_TX_LENGTHS,
1202                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1203                       (6 << TX_LENGTHS_IPG_SHIFT) |
1204                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1205         else
1206                 tw32(MAC_TX_LENGTHS,
1207                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1208                       (6 << TX_LENGTHS_IPG_SHIFT) |
1209                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1210
1211         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1212             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1213             phydev->speed != tp->link_config.active_speed ||
1214             phydev->duplex != tp->link_config.active_duplex ||
1215             oldflowctrl != tp->link_config.active_flowctrl)
1216             linkmesg = 1;
1217
1218         tp->link_config.active_speed = phydev->speed;
1219         tp->link_config.active_duplex = phydev->duplex;
1220
1221         spin_unlock(&tp->lock);
1222
1223         if (linkmesg)
1224                 tg3_link_report(tp);
1225 }
1226
1227 static int tg3_phy_init(struct tg3 *tp)
1228 {
1229         struct phy_device *phydev;
1230
1231         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1232                 return 0;
1233
1234         /* Bring the PHY back to a known state. */
1235         tg3_bmcr_reset(tp);
1236
1237         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1238
1239         /* Attach the MAC to the PHY. */
1240         phydev = phy_connect(tp->dev, phydev->dev.bus_id,
1241                              tg3_adjust_link, 0, phydev->interface);
1242         if (IS_ERR(phydev)) {
1243                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1244                 return PTR_ERR(phydev);
1245         }
1246
1247         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1248
1249         /* Mask with MAC supported features. */
1250         phydev->supported &= (PHY_GBIT_FEATURES |
1251                               SUPPORTED_Pause |
1252                               SUPPORTED_Asym_Pause);
1253
1254         phydev->advertising = phydev->supported;
1255
1256         printk(KERN_INFO
1257                "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1258                tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1259
1260         return 0;
1261 }
1262
1263 static void tg3_phy_start(struct tg3 *tp)
1264 {
1265         struct phy_device *phydev;
1266
1267         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1268                 return;
1269
1270         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1271
1272         if (tp->link_config.phy_is_low_power) {
1273                 tp->link_config.phy_is_low_power = 0;
1274                 phydev->speed = tp->link_config.orig_speed;
1275                 phydev->duplex = tp->link_config.orig_duplex;
1276                 phydev->autoneg = tp->link_config.orig_autoneg;
1277                 phydev->advertising = tp->link_config.orig_advertising;
1278         }
1279
1280         phy_start(phydev);
1281
1282         phy_start_aneg(phydev);
1283 }
1284
1285 static void tg3_phy_stop(struct tg3 *tp)
1286 {
1287         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1288                 return;
1289
1290         phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
1291 }
1292
1293 static void tg3_phy_fini(struct tg3 *tp)
1294 {
1295         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1296                 phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
1297                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1298         }
1299 }
1300
1301 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1302 {
1303         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1304         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1305 }
1306
1307 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1308 {
1309         u32 phy;
1310
1311         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1312             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1313                 return;
1314
1315         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1316                 u32 ephy;
1317
1318                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1319                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1320                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1321                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1322                                 if (enable)
1323                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1324                                 else
1325                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1326                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1327                         }
1328                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1329                 }
1330         } else {
1331                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1332                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1333                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1334                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1335                         if (enable)
1336                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1337                         else
1338                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1339                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1340                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1341                 }
1342         }
1343 }
1344
1345 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1346 {
1347         u32 val;
1348
1349         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1350                 return;
1351
1352         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1353             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1354                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1355                              (val | (1 << 15) | (1 << 4)));
1356 }
1357
1358 static void tg3_phy_apply_otp(struct tg3 *tp)
1359 {
1360         u32 otp, phy;
1361
1362         if (!tp->phy_otp)
1363                 return;
1364
1365         otp = tp->phy_otp;
1366
1367         /* Enable SM_DSP clock and tx 6dB coding. */
1368         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1369               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1370               MII_TG3_AUXCTL_ACTL_TX_6DB;
1371         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1372
1373         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1374         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1375         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1376
1377         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1378               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1379         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1380
1381         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1382         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1383         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1384
1385         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1386         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1387
1388         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1389         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1390
1391         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1392               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1393         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1394
1395         /* Turn off SM_DSP clock. */
1396         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1397               MII_TG3_AUXCTL_ACTL_TX_6DB;
1398         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1399 }
1400
1401 static int tg3_wait_macro_done(struct tg3 *tp)
1402 {
1403         int limit = 100;
1404
1405         while (limit--) {
1406                 u32 tmp32;
1407
1408                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1409                         if ((tmp32 & 0x1000) == 0)
1410                                 break;
1411                 }
1412         }
1413         if (limit <= 0)
1414                 return -EBUSY;
1415
1416         return 0;
1417 }
1418
1419 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1420 {
1421         static const u32 test_pat[4][6] = {
1422         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1423         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1424         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1425         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1426         };
1427         int chan;
1428
1429         for (chan = 0; chan < 4; chan++) {
1430                 int i;
1431
1432                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1433                              (chan * 0x2000) | 0x0200);
1434                 tg3_writephy(tp, 0x16, 0x0002);
1435
1436                 for (i = 0; i < 6; i++)
1437                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1438                                      test_pat[chan][i]);
1439
1440                 tg3_writephy(tp, 0x16, 0x0202);
1441                 if (tg3_wait_macro_done(tp)) {
1442                         *resetp = 1;
1443                         return -EBUSY;
1444                 }
1445
1446                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1447                              (chan * 0x2000) | 0x0200);
1448                 tg3_writephy(tp, 0x16, 0x0082);
1449                 if (tg3_wait_macro_done(tp)) {
1450                         *resetp = 1;
1451                         return -EBUSY;
1452                 }
1453
1454                 tg3_writephy(tp, 0x16, 0x0802);
1455                 if (tg3_wait_macro_done(tp)) {
1456                         *resetp = 1;
1457                         return -EBUSY;
1458                 }
1459
1460                 for (i = 0; i < 6; i += 2) {
1461                         u32 low, high;
1462
1463                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1464                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1465                             tg3_wait_macro_done(tp)) {
1466                                 *resetp = 1;
1467                                 return -EBUSY;
1468                         }
1469                         low &= 0x7fff;
1470                         high &= 0x000f;
1471                         if (low != test_pat[chan][i] ||
1472                             high != test_pat[chan][i+1]) {
1473                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1474                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1475                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1476
1477                                 return -EBUSY;
1478                         }
1479                 }
1480         }
1481
1482         return 0;
1483 }
1484
1485 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1486 {
1487         int chan;
1488
1489         for (chan = 0; chan < 4; chan++) {
1490                 int i;
1491
1492                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1493                              (chan * 0x2000) | 0x0200);
1494                 tg3_writephy(tp, 0x16, 0x0002);
1495                 for (i = 0; i < 6; i++)
1496                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1497                 tg3_writephy(tp, 0x16, 0x0202);
1498                 if (tg3_wait_macro_done(tp))
1499                         return -EBUSY;
1500         }
1501
1502         return 0;
1503 }
1504
1505 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1506 {
1507         u32 reg32, phy9_orig;
1508         int retries, do_phy_reset, err;
1509
1510         retries = 10;
1511         do_phy_reset = 1;
1512         do {
1513                 if (do_phy_reset) {
1514                         err = tg3_bmcr_reset(tp);
1515                         if (err)
1516                                 return err;
1517                         do_phy_reset = 0;
1518                 }
1519
1520                 /* Disable transmitter and interrupt.  */
1521                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1522                         continue;
1523
1524                 reg32 |= 0x3000;
1525                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1526
1527                 /* Set full-duplex, 1000 mbps.  */
1528                 tg3_writephy(tp, MII_BMCR,
1529                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1530
1531                 /* Set to master mode.  */
1532                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1533                         continue;
1534
1535                 tg3_writephy(tp, MII_TG3_CTRL,
1536                              (MII_TG3_CTRL_AS_MASTER |
1537                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1538
1539                 /* Enable SM_DSP_CLOCK and 6dB.  */
1540                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1541
1542                 /* Block the PHY control access.  */
1543                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1544                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1545
1546                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1547                 if (!err)
1548                         break;
1549         } while (--retries);
1550
1551         err = tg3_phy_reset_chanpat(tp);
1552         if (err)
1553                 return err;
1554
1555         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1556         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1557
1558         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1559         tg3_writephy(tp, 0x16, 0x0000);
1560
1561         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1562             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1563                 /* Set Extended packet length bit for jumbo frames */
1564                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1565         }
1566         else {
1567                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1568         }
1569
1570         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1571
1572         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1573                 reg32 &= ~0x3000;
1574                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1575         } else if (!err)
1576                 err = -EBUSY;
1577
1578         return err;
1579 }
1580
1581 /* This will reset the tigon3 PHY if there is no valid
1582  * link unless the FORCE argument is non-zero.
1583  */
1584 static int tg3_phy_reset(struct tg3 *tp)
1585 {
1586         u32 cpmuctrl;
1587         u32 phy_status;
1588         int err;
1589
1590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1591                 u32 val;
1592
1593                 val = tr32(GRC_MISC_CFG);
1594                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1595                 udelay(40);
1596         }
1597         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1598         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1599         if (err != 0)
1600                 return -EBUSY;
1601
1602         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1603                 netif_carrier_off(tp->dev);
1604                 tg3_link_report(tp);
1605         }
1606
1607         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1608             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1609             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1610                 err = tg3_phy_reset_5703_4_5(tp);
1611                 if (err)
1612                         return err;
1613                 goto out;
1614         }
1615
1616         cpmuctrl = 0;
1617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1618             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1619                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1620                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1621                         tw32(TG3_CPMU_CTRL,
1622                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1623         }
1624
1625         err = tg3_bmcr_reset(tp);
1626         if (err)
1627                 return err;
1628
1629         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1630                 u32 phy;
1631
1632                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1633                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1634
1635                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1636         }
1637
1638         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1639                 u32 val;
1640
1641                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1642                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1643                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1644                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1645                         udelay(40);
1646                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1647                 }
1648
1649                 /* Disable GPHY autopowerdown. */
1650                 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1651                              MII_TG3_MISC_SHDW_WREN |
1652                              MII_TG3_MISC_SHDW_APD_SEL |
1653                              MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1654         }
1655
1656         tg3_phy_apply_otp(tp);
1657
1658 out:
1659         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1660                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1661                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1662                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1663                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1664                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1665                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1666         }
1667         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1668                 tg3_writephy(tp, 0x1c, 0x8d68);
1669                 tg3_writephy(tp, 0x1c, 0x8d68);
1670         }
1671         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1672                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1673                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1674                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1675                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1676                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1677                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1678                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1679                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1680         }
1681         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1682                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1683                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1684                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1685                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1686                         tg3_writephy(tp, MII_TG3_TEST1,
1687                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1688                 } else
1689                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1690                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1691         }
1692         /* Set Extended packet length bit (bit 14) on all chips that */
1693         /* support jumbo frames */
1694         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1695                 /* Cannot do read-modify-write on 5401 */
1696                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1697         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1698                 u32 phy_reg;
1699
1700                 /* Set bit 14 with read-modify-write to preserve other bits */
1701                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1702                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1703                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1704         }
1705
1706         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1707          * jumbo frames transmission.
1708          */
1709         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1710                 u32 phy_reg;
1711
1712                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1713                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1714                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1715         }
1716
1717         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1718                 /* adjust output voltage */
1719                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1720         }
1721
1722         tg3_phy_toggle_automdix(tp, 1);
1723         tg3_phy_set_wirespeed(tp);
1724         return 0;
1725 }
1726
1727 static void tg3_frob_aux_power(struct tg3 *tp)
1728 {
1729         struct tg3 *tp_peer = tp;
1730
1731         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1732                 return;
1733
1734         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1735             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1736                 struct net_device *dev_peer;
1737
1738                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1739                 /* remove_one() may have been run on the peer. */
1740                 if (!dev_peer)
1741                         tp_peer = tp;
1742                 else
1743                         tp_peer = netdev_priv(dev_peer);
1744         }
1745
1746         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1747             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1748             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1749             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1750                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1751                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1752                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1753                                     (GRC_LCLCTRL_GPIO_OE0 |
1754                                      GRC_LCLCTRL_GPIO_OE1 |
1755                                      GRC_LCLCTRL_GPIO_OE2 |
1756                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1757                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1758                                     100);
1759                 } else {
1760                         u32 no_gpio2;
1761                         u32 grc_local_ctrl = 0;
1762
1763                         if (tp_peer != tp &&
1764                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1765                                 return;
1766
1767                         /* Workaround to prevent overdrawing Amps. */
1768                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1769                             ASIC_REV_5714) {
1770                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1771                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1772                                             grc_local_ctrl, 100);
1773                         }
1774
1775                         /* On 5753 and variants, GPIO2 cannot be used. */
1776                         no_gpio2 = tp->nic_sram_data_cfg &
1777                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1778
1779                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1780                                          GRC_LCLCTRL_GPIO_OE1 |
1781                                          GRC_LCLCTRL_GPIO_OE2 |
1782                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1783                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1784                         if (no_gpio2) {
1785                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1786                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1787                         }
1788                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1789                                                     grc_local_ctrl, 100);
1790
1791                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1792
1793                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1794                                                     grc_local_ctrl, 100);
1795
1796                         if (!no_gpio2) {
1797                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1798                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1799                                             grc_local_ctrl, 100);
1800                         }
1801                 }
1802         } else {
1803                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1804                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1805                         if (tp_peer != tp &&
1806                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1807                                 return;
1808
1809                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1810                                     (GRC_LCLCTRL_GPIO_OE1 |
1811                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1812
1813                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1814                                     GRC_LCLCTRL_GPIO_OE1, 100);
1815
1816                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1817                                     (GRC_LCLCTRL_GPIO_OE1 |
1818                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1819                 }
1820         }
1821 }
1822
1823 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1824 {
1825         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1826                 return 1;
1827         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1828                 if (speed != SPEED_10)
1829                         return 1;
1830         } else if (speed == SPEED_10)
1831                 return 1;
1832
1833         return 0;
1834 }
1835
1836 static int tg3_setup_phy(struct tg3 *, int);
1837
1838 #define RESET_KIND_SHUTDOWN     0
1839 #define RESET_KIND_INIT         1
1840 #define RESET_KIND_SUSPEND      2
1841
1842 static void tg3_write_sig_post_reset(struct tg3 *, int);
1843 static int tg3_halt_cpu(struct tg3 *, u32);
1844 static int tg3_nvram_lock(struct tg3 *);
1845 static void tg3_nvram_unlock(struct tg3 *);
1846
1847 static void tg3_power_down_phy(struct tg3 *tp)
1848 {
1849         u32 val;
1850
1851         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1852                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1853                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1854                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1855
1856                         sg_dig_ctrl |=
1857                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1858                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1859                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1860                 }
1861                 return;
1862         }
1863
1864         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1865                 tg3_bmcr_reset(tp);
1866                 val = tr32(GRC_MISC_CFG);
1867                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1868                 udelay(40);
1869                 return;
1870         } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1871                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1872                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1873                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1874         }
1875
1876         /* The PHY should not be powered down on some chips because
1877          * of bugs.
1878          */
1879         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1880             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1881             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1882              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1883                 return;
1884
1885         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1886                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1887                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1888                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1889                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1890         }
1891
1892         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1893 }
1894
1895 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1896 {
1897         u32 misc_host_ctrl;
1898         u16 power_control, power_caps;
1899         int pm = tp->pm_cap;
1900
1901         /* Make sure register accesses (indirect or otherwise)
1902          * will function correctly.
1903          */
1904         pci_write_config_dword(tp->pdev,
1905                                TG3PCI_MISC_HOST_CTRL,
1906                                tp->misc_host_ctrl);
1907
1908         pci_read_config_word(tp->pdev,
1909                              pm + PCI_PM_CTRL,
1910                              &power_control);
1911         power_control |= PCI_PM_CTRL_PME_STATUS;
1912         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1913         switch (state) {
1914         case PCI_D0:
1915                 power_control |= 0;
1916                 pci_write_config_word(tp->pdev,
1917                                       pm + PCI_PM_CTRL,
1918                                       power_control);
1919                 udelay(100);    /* Delay after power state change */
1920
1921                 /* Switch out of Vaux if it is a NIC */
1922                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1923                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1924
1925                 return 0;
1926
1927         case PCI_D1:
1928                 power_control |= 1;
1929                 break;
1930
1931         case PCI_D2:
1932                 power_control |= 2;
1933                 break;
1934
1935         case PCI_D3hot:
1936                 power_control |= 3;
1937                 break;
1938
1939         default:
1940                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1941                        "requested.\n",
1942                        tp->dev->name, state);
1943                 return -EINVAL;
1944         };
1945
1946         power_control |= PCI_PM_CTRL_PME_ENABLE;
1947
1948         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1949         tw32(TG3PCI_MISC_HOST_CTRL,
1950              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1951
1952         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
1953                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
1954                     !tp->link_config.phy_is_low_power) {
1955                         struct phy_device *phydev;
1956                         u32 advertising;
1957
1958                         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1959
1960                         tp->link_config.phy_is_low_power = 1;
1961
1962                         tp->link_config.orig_speed = phydev->speed;
1963                         tp->link_config.orig_duplex = phydev->duplex;
1964                         tp->link_config.orig_autoneg = phydev->autoneg;
1965                         tp->link_config.orig_advertising = phydev->advertising;
1966
1967                         advertising = ADVERTISED_TP |
1968                                       ADVERTISED_Pause |
1969                                       ADVERTISED_Autoneg |
1970                                       ADVERTISED_10baseT_Half;
1971
1972                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
1973                             (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
1974                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1975                                         advertising |=
1976                                                 ADVERTISED_100baseT_Half |
1977                                                 ADVERTISED_100baseT_Full |
1978                                                 ADVERTISED_10baseT_Full;
1979                                 else
1980                                         advertising |= ADVERTISED_10baseT_Full;
1981                         }
1982
1983                         phydev->advertising = advertising;
1984
1985                         phy_start_aneg(phydev);
1986                 }
1987         } else {
1988                 if (tp->link_config.phy_is_low_power == 0) {
1989                         tp->link_config.phy_is_low_power = 1;
1990                         tp->link_config.orig_speed = tp->link_config.speed;
1991                         tp->link_config.orig_duplex = tp->link_config.duplex;
1992                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
1993                 }
1994
1995                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1996                         tp->link_config.speed = SPEED_10;
1997                         tp->link_config.duplex = DUPLEX_HALF;
1998                         tp->link_config.autoneg = AUTONEG_ENABLE;
1999                         tg3_setup_phy(tp, 0);
2000                 }
2001         }
2002
2003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2004                 u32 val;
2005
2006                 val = tr32(GRC_VCPU_EXT_CTRL);
2007                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2008         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2009                 int i;
2010                 u32 val;
2011
2012                 for (i = 0; i < 200; i++) {
2013                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2014                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2015                                 break;
2016                         msleep(1);
2017                 }
2018         }
2019         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2020                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2021                                                      WOL_DRV_STATE_SHUTDOWN |
2022                                                      WOL_DRV_WOL |
2023                                                      WOL_SET_MAGIC_PKT);
2024
2025         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
2026
2027         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
2028                 u32 mac_mode;
2029
2030                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2031                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
2032                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2033                                 udelay(40);
2034                         }
2035
2036                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2037                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2038                         else
2039                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2040
2041                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2042                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2043                             ASIC_REV_5700) {
2044                                 u32 speed = (tp->tg3_flags &
2045                                              TG3_FLAG_WOL_SPEED_100MB) ?
2046                                              SPEED_100 : SPEED_10;
2047                                 if (tg3_5700_link_polarity(tp, speed))
2048                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2049                                 else
2050                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2051                         }
2052                 } else {
2053                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2054                 }
2055
2056                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2057                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2058
2059                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
2060                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
2061                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2062
2063                 tw32_f(MAC_MODE, mac_mode);
2064                 udelay(100);
2065
2066                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2067                 udelay(10);
2068         }
2069
2070         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2071             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2072              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2073                 u32 base_val;
2074
2075                 base_val = tp->pci_clock_ctrl;
2076                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2077                              CLOCK_CTRL_TXCLK_DISABLE);
2078
2079                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2080                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2081         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2082                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2083                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2084                 /* do nothing */
2085         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2086                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2087                 u32 newbits1, newbits2;
2088
2089                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2090                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2091                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2092                                     CLOCK_CTRL_TXCLK_DISABLE |
2093                                     CLOCK_CTRL_ALTCLK);
2094                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2095                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2096                         newbits1 = CLOCK_CTRL_625_CORE;
2097                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2098                 } else {
2099                         newbits1 = CLOCK_CTRL_ALTCLK;
2100                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2101                 }
2102
2103                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2104                             40);
2105
2106                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2107                             40);
2108
2109                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2110                         u32 newbits3;
2111
2112                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2113                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2114                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2115                                             CLOCK_CTRL_TXCLK_DISABLE |
2116                                             CLOCK_CTRL_44MHZ_CORE);
2117                         } else {
2118                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2119                         }
2120
2121                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2122                                     tp->pci_clock_ctrl | newbits3, 40);
2123                 }
2124         }
2125
2126         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
2127             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
2128             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
2129                 tg3_power_down_phy(tp);
2130
2131         tg3_frob_aux_power(tp);
2132
2133         /* Workaround for unstable PLL clock */
2134         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2135             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2136                 u32 val = tr32(0x7d00);
2137
2138                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2139                 tw32(0x7d00, val);
2140                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2141                         int err;
2142
2143                         err = tg3_nvram_lock(tp);
2144                         tg3_halt_cpu(tp, RX_CPU_BASE);
2145                         if (!err)
2146                                 tg3_nvram_unlock(tp);
2147                 }
2148         }
2149
2150         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2151
2152         /* Finally, set the new power state. */
2153         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
2154         udelay(100);    /* Delay after power state change */
2155
2156         return 0;
2157 }
2158
2159 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2160 {
2161         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2162         case MII_TG3_AUX_STAT_10HALF:
2163                 *speed = SPEED_10;
2164                 *duplex = DUPLEX_HALF;
2165                 break;
2166
2167         case MII_TG3_AUX_STAT_10FULL:
2168                 *speed = SPEED_10;
2169                 *duplex = DUPLEX_FULL;
2170                 break;
2171
2172         case MII_TG3_AUX_STAT_100HALF:
2173                 *speed = SPEED_100;
2174                 *duplex = DUPLEX_HALF;
2175                 break;
2176
2177         case MII_TG3_AUX_STAT_100FULL:
2178                 *speed = SPEED_100;
2179                 *duplex = DUPLEX_FULL;
2180                 break;
2181
2182         case MII_TG3_AUX_STAT_1000HALF:
2183                 *speed = SPEED_1000;
2184                 *duplex = DUPLEX_HALF;
2185                 break;
2186
2187         case MII_TG3_AUX_STAT_1000FULL:
2188                 *speed = SPEED_1000;
2189                 *duplex = DUPLEX_FULL;
2190                 break;
2191
2192         default:
2193                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2194                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2195                                  SPEED_10;
2196                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2197                                   DUPLEX_HALF;
2198                         break;
2199                 }
2200                 *speed = SPEED_INVALID;
2201                 *duplex = DUPLEX_INVALID;
2202                 break;
2203         };
2204 }
2205
2206 static void tg3_phy_copper_begin(struct tg3 *tp)
2207 {
2208         u32 new_adv;
2209         int i;
2210
2211         if (tp->link_config.phy_is_low_power) {
2212                 /* Entering low power mode.  Disable gigabit and
2213                  * 100baseT advertisements.
2214                  */
2215                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2216
2217                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2218                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2219                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2220                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2221
2222                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2223         } else if (tp->link_config.speed == SPEED_INVALID) {
2224                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2225                         tp->link_config.advertising &=
2226                                 ~(ADVERTISED_1000baseT_Half |
2227                                   ADVERTISED_1000baseT_Full);
2228
2229                 new_adv = ADVERTISE_CSMA;
2230                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2231                         new_adv |= ADVERTISE_10HALF;
2232                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2233                         new_adv |= ADVERTISE_10FULL;
2234                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2235                         new_adv |= ADVERTISE_100HALF;
2236                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2237                         new_adv |= ADVERTISE_100FULL;
2238
2239                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2240
2241                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2242
2243                 if (tp->link_config.advertising &
2244                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2245                         new_adv = 0;
2246                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2247                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2248                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2249                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2250                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2251                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2252                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2253                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2254                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2255                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2256                 } else {
2257                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2258                 }
2259         } else {
2260                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2261                 new_adv |= ADVERTISE_CSMA;
2262
2263                 /* Asking for a specific link mode. */
2264                 if (tp->link_config.speed == SPEED_1000) {
2265                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2266
2267                         if (tp->link_config.duplex == DUPLEX_FULL)
2268                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2269                         else
2270                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2271                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2272                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2273                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2274                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2275                 } else {
2276                         if (tp->link_config.speed == SPEED_100) {
2277                                 if (tp->link_config.duplex == DUPLEX_FULL)
2278                                         new_adv |= ADVERTISE_100FULL;
2279                                 else
2280                                         new_adv |= ADVERTISE_100HALF;
2281                         } else {
2282                                 if (tp->link_config.duplex == DUPLEX_FULL)
2283                                         new_adv |= ADVERTISE_10FULL;
2284                                 else
2285                                         new_adv |= ADVERTISE_10HALF;
2286                         }
2287                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2288
2289                         new_adv = 0;
2290                 }
2291
2292                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2293         }
2294
2295         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2296             tp->link_config.speed != SPEED_INVALID) {
2297                 u32 bmcr, orig_bmcr;
2298
2299                 tp->link_config.active_speed = tp->link_config.speed;
2300                 tp->link_config.active_duplex = tp->link_config.duplex;
2301
2302                 bmcr = 0;
2303                 switch (tp->link_config.speed) {
2304                 default:
2305                 case SPEED_10:
2306                         break;
2307
2308                 case SPEED_100:
2309                         bmcr |= BMCR_SPEED100;
2310                         break;
2311
2312                 case SPEED_1000:
2313                         bmcr |= TG3_BMCR_SPEED1000;
2314                         break;
2315                 };
2316
2317                 if (tp->link_config.duplex == DUPLEX_FULL)
2318                         bmcr |= BMCR_FULLDPLX;
2319
2320                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2321                     (bmcr != orig_bmcr)) {
2322                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2323                         for (i = 0; i < 1500; i++) {
2324                                 u32 tmp;
2325
2326                                 udelay(10);
2327                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2328                                     tg3_readphy(tp, MII_BMSR, &tmp))
2329                                         continue;
2330                                 if (!(tmp & BMSR_LSTATUS)) {
2331                                         udelay(40);
2332                                         break;
2333                                 }
2334                         }
2335                         tg3_writephy(tp, MII_BMCR, bmcr);
2336                         udelay(40);
2337                 }
2338         } else {
2339                 tg3_writephy(tp, MII_BMCR,
2340                              BMCR_ANENABLE | BMCR_ANRESTART);
2341         }
2342 }
2343
2344 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2345 {
2346         int err;
2347
2348         /* Turn off tap power management. */
2349         /* Set Extended packet length bit */
2350         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2351
2352         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2353         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2354
2355         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2356         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2357
2358         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2359         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2360
2361         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2362         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2363
2364         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2365         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2366
2367         udelay(40);
2368
2369         return err;
2370 }
2371
2372 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2373 {
2374         u32 adv_reg, all_mask = 0;
2375
2376         if (mask & ADVERTISED_10baseT_Half)
2377                 all_mask |= ADVERTISE_10HALF;
2378         if (mask & ADVERTISED_10baseT_Full)
2379                 all_mask |= ADVERTISE_10FULL;
2380         if (mask & ADVERTISED_100baseT_Half)
2381                 all_mask |= ADVERTISE_100HALF;
2382         if (mask & ADVERTISED_100baseT_Full)
2383                 all_mask |= ADVERTISE_100FULL;
2384
2385         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2386                 return 0;
2387
2388         if ((adv_reg & all_mask) != all_mask)
2389                 return 0;
2390         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2391                 u32 tg3_ctrl;
2392
2393                 all_mask = 0;
2394                 if (mask & ADVERTISED_1000baseT_Half)
2395                         all_mask |= ADVERTISE_1000HALF;
2396                 if (mask & ADVERTISED_1000baseT_Full)
2397                         all_mask |= ADVERTISE_1000FULL;
2398
2399                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2400                         return 0;
2401
2402                 if ((tg3_ctrl & all_mask) != all_mask)
2403                         return 0;
2404         }
2405         return 1;
2406 }
2407
2408 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2409 {
2410         u32 curadv, reqadv;
2411
2412         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2413                 return 1;
2414
2415         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2416         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2417
2418         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2419                 if (curadv != reqadv)
2420                         return 0;
2421
2422                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2423                         tg3_readphy(tp, MII_LPA, rmtadv);
2424         } else {
2425                 /* Reprogram the advertisement register, even if it
2426                  * does not affect the current link.  If the link
2427                  * gets renegotiated in the future, we can save an
2428                  * additional renegotiation cycle by advertising
2429                  * it correctly in the first place.
2430                  */
2431                 if (curadv != reqadv) {
2432                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2433                                      ADVERTISE_PAUSE_ASYM);
2434                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2435                 }
2436         }
2437
2438         return 1;
2439 }
2440
2441 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2442 {
2443         int current_link_up;
2444         u32 bmsr, dummy;
2445         u32 lcl_adv, rmt_adv;
2446         u16 current_speed;
2447         u8 current_duplex;
2448         int i, err;
2449
2450         tw32(MAC_EVENT, 0);
2451
2452         tw32_f(MAC_STATUS,
2453              (MAC_STATUS_SYNC_CHANGED |
2454               MAC_STATUS_CFG_CHANGED |
2455               MAC_STATUS_MI_COMPLETION |
2456               MAC_STATUS_LNKSTATE_CHANGED));
2457         udelay(40);
2458
2459         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2460                 tw32_f(MAC_MI_MODE,
2461                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2462                 udelay(80);
2463         }
2464
2465         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2466
2467         /* Some third-party PHYs need to be reset on link going
2468          * down.
2469          */
2470         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2471              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2472              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2473             netif_carrier_ok(tp->dev)) {
2474                 tg3_readphy(tp, MII_BMSR, &bmsr);
2475                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2476                     !(bmsr & BMSR_LSTATUS))
2477                         force_reset = 1;
2478         }
2479         if (force_reset)
2480                 tg3_phy_reset(tp);
2481
2482         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2483                 tg3_readphy(tp, MII_BMSR, &bmsr);
2484                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2485                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2486                         bmsr = 0;
2487
2488                 if (!(bmsr & BMSR_LSTATUS)) {
2489                         err = tg3_init_5401phy_dsp(tp);
2490                         if (err)
2491                                 return err;
2492
2493                         tg3_readphy(tp, MII_BMSR, &bmsr);
2494                         for (i = 0; i < 1000; i++) {
2495                                 udelay(10);
2496                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2497                                     (bmsr & BMSR_LSTATUS)) {
2498                                         udelay(40);
2499                                         break;
2500                                 }
2501                         }
2502
2503                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2504                             !(bmsr & BMSR_LSTATUS) &&
2505                             tp->link_config.active_speed == SPEED_1000) {
2506                                 err = tg3_phy_reset(tp);
2507                                 if (!err)
2508                                         err = tg3_init_5401phy_dsp(tp);
2509                                 if (err)
2510                                         return err;
2511                         }
2512                 }
2513         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2514                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2515                 /* 5701 {A0,B0} CRC bug workaround */
2516                 tg3_writephy(tp, 0x15, 0x0a75);
2517                 tg3_writephy(tp, 0x1c, 0x8c68);
2518                 tg3_writephy(tp, 0x1c, 0x8d68);
2519                 tg3_writephy(tp, 0x1c, 0x8c68);
2520         }
2521
2522         /* Clear pending interrupts... */
2523         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2524         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2525
2526         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2527                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2528         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2529                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2530
2531         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2532             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2533                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2534                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2535                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2536                 else
2537                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2538         }
2539
2540         current_link_up = 0;
2541         current_speed = SPEED_INVALID;
2542         current_duplex = DUPLEX_INVALID;
2543
2544         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2545                 u32 val;
2546
2547                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2548                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2549                 if (!(val & (1 << 10))) {
2550                         val |= (1 << 10);
2551                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2552                         goto relink;
2553                 }
2554         }
2555
2556         bmsr = 0;
2557         for (i = 0; i < 100; i++) {
2558                 tg3_readphy(tp, MII_BMSR, &bmsr);
2559                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2560                     (bmsr & BMSR_LSTATUS))
2561                         break;
2562                 udelay(40);
2563         }
2564
2565         if (bmsr & BMSR_LSTATUS) {
2566                 u32 aux_stat, bmcr;
2567
2568                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2569                 for (i = 0; i < 2000; i++) {
2570                         udelay(10);
2571                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2572                             aux_stat)
2573                                 break;
2574                 }
2575
2576                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2577                                              &current_speed,
2578                                              &current_duplex);
2579
2580                 bmcr = 0;
2581                 for (i = 0; i < 200; i++) {
2582                         tg3_readphy(tp, MII_BMCR, &bmcr);
2583                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
2584                                 continue;
2585                         if (bmcr && bmcr != 0x7fff)
2586                                 break;
2587                         udelay(10);
2588                 }
2589
2590                 lcl_adv = 0;
2591                 rmt_adv = 0;
2592
2593                 tp->link_config.active_speed = current_speed;
2594                 tp->link_config.active_duplex = current_duplex;
2595
2596                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2597                         if ((bmcr & BMCR_ANENABLE) &&
2598                             tg3_copper_is_advertising_all(tp,
2599                                                 tp->link_config.advertising)) {
2600                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2601                                                                   &rmt_adv))
2602                                         current_link_up = 1;
2603                         }
2604                 } else {
2605                         if (!(bmcr & BMCR_ANENABLE) &&
2606                             tp->link_config.speed == current_speed &&
2607                             tp->link_config.duplex == current_duplex &&
2608                             tp->link_config.flowctrl ==
2609                             tp->link_config.active_flowctrl) {
2610                                 current_link_up = 1;
2611                         }
2612                 }
2613
2614                 if (current_link_up == 1 &&
2615                     tp->link_config.active_duplex == DUPLEX_FULL)
2616                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2617         }
2618
2619 relink:
2620         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2621                 u32 tmp;
2622
2623                 tg3_phy_copper_begin(tp);
2624
2625                 tg3_readphy(tp, MII_BMSR, &tmp);
2626                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2627                     (tmp & BMSR_LSTATUS))
2628                         current_link_up = 1;
2629         }
2630
2631         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2632         if (current_link_up == 1) {
2633                 if (tp->link_config.active_speed == SPEED_100 ||
2634                     tp->link_config.active_speed == SPEED_10)
2635                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2636                 else
2637                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2638         } else
2639                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2640
2641         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2642         if (tp->link_config.active_duplex == DUPLEX_HALF)
2643                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2644
2645         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2646                 if (current_link_up == 1 &&
2647                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2648                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2649                 else
2650                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2651         }
2652
2653         /* ??? Without this setting Netgear GA302T PHY does not
2654          * ??? send/receive packets...
2655          */
2656         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2657             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2658                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2659                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2660                 udelay(80);
2661         }
2662
2663         tw32_f(MAC_MODE, tp->mac_mode);
2664         udelay(40);
2665
2666         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2667                 /* Polled via timer. */
2668                 tw32_f(MAC_EVENT, 0);
2669         } else {
2670                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2671         }
2672         udelay(40);
2673
2674         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2675             current_link_up == 1 &&
2676             tp->link_config.active_speed == SPEED_1000 &&
2677             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2678              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2679                 udelay(120);
2680                 tw32_f(MAC_STATUS,
2681                      (MAC_STATUS_SYNC_CHANGED |
2682                       MAC_STATUS_CFG_CHANGED));
2683                 udelay(40);
2684                 tg3_write_mem(tp,
2685                               NIC_SRAM_FIRMWARE_MBOX,
2686                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2687         }
2688
2689         if (current_link_up != netif_carrier_ok(tp->dev)) {
2690                 if (current_link_up)
2691                         netif_carrier_on(tp->dev);
2692                 else
2693                         netif_carrier_off(tp->dev);
2694                 tg3_link_report(tp);
2695         }
2696
2697         return 0;
2698 }
2699
2700 struct tg3_fiber_aneginfo {
2701         int state;
2702 #define ANEG_STATE_UNKNOWN              0
2703 #define ANEG_STATE_AN_ENABLE            1
2704 #define ANEG_STATE_RESTART_INIT         2
2705 #define ANEG_STATE_RESTART              3
2706 #define ANEG_STATE_DISABLE_LINK_OK      4
2707 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2708 #define ANEG_STATE_ABILITY_DETECT       6
2709 #define ANEG_STATE_ACK_DETECT_INIT      7
2710 #define ANEG_STATE_ACK_DETECT           8
2711 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2712 #define ANEG_STATE_COMPLETE_ACK         10
2713 #define ANEG_STATE_IDLE_DETECT_INIT     11
2714 #define ANEG_STATE_IDLE_DETECT          12
2715 #define ANEG_STATE_LINK_OK              13
2716 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2717 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2718
2719         u32 flags;
2720 #define MR_AN_ENABLE            0x00000001
2721 #define MR_RESTART_AN           0x00000002
2722 #define MR_AN_COMPLETE          0x00000004
2723 #define MR_PAGE_RX              0x00000008
2724 #define MR_NP_LOADED            0x00000010
2725 #define MR_TOGGLE_TX            0x00000020
2726 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2727 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2728 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2729 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2730 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2731 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2732 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2733 #define MR_TOGGLE_RX            0x00002000
2734 #define MR_NP_RX                0x00004000
2735
2736 #define MR_LINK_OK              0x80000000
2737
2738         unsigned long link_time, cur_time;
2739
2740         u32 ability_match_cfg;
2741         int ability_match_count;
2742
2743         char ability_match, idle_match, ack_match;
2744
2745         u32 txconfig, rxconfig;
2746 #define ANEG_CFG_NP             0x00000080
2747 #define ANEG_CFG_ACK            0x00000040
2748 #define ANEG_CFG_RF2            0x00000020
2749 #define ANEG_CFG_RF1            0x00000010
2750 #define ANEG_CFG_PS2            0x00000001
2751 #define ANEG_CFG_PS1            0x00008000
2752 #define ANEG_CFG_HD             0x00004000
2753 #define ANEG_CFG_FD             0x00002000
2754 #define ANEG_CFG_INVAL          0x00001f06
2755
2756 };
2757 #define ANEG_OK         0
2758 #define ANEG_DONE       1
2759 #define ANEG_TIMER_ENAB 2
2760 #define ANEG_FAILED     -1
2761
2762 #define ANEG_STATE_SETTLE_TIME  10000
2763
2764 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2765                                    struct tg3_fiber_aneginfo *ap)
2766 {
2767         u16 flowctrl;
2768         unsigned long delta;
2769         u32 rx_cfg_reg;
2770         int ret;
2771
2772         if (ap->state == ANEG_STATE_UNKNOWN) {
2773                 ap->rxconfig = 0;
2774                 ap->link_time = 0;
2775                 ap->cur_time = 0;
2776                 ap->ability_match_cfg = 0;
2777                 ap->ability_match_count = 0;
2778                 ap->ability_match = 0;
2779                 ap->idle_match = 0;
2780                 ap->ack_match = 0;
2781         }
2782         ap->cur_time++;
2783
2784         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2785                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2786
2787                 if (rx_cfg_reg != ap->ability_match_cfg) {
2788                         ap->ability_match_cfg = rx_cfg_reg;
2789                         ap->ability_match = 0;
2790                         ap->ability_match_count = 0;
2791                 } else {
2792                         if (++ap->ability_match_count > 1) {
2793                                 ap->ability_match = 1;
2794                                 ap->ability_match_cfg = rx_cfg_reg;
2795                         }
2796                 }
2797                 if (rx_cfg_reg & ANEG_CFG_ACK)
2798                         ap->ack_match = 1;
2799                 else
2800                         ap->ack_match = 0;
2801
2802                 ap->idle_match = 0;
2803         } else {
2804                 ap->idle_match = 1;
2805                 ap->ability_match_cfg = 0;
2806                 ap->ability_match_count = 0;
2807                 ap->ability_match = 0;
2808                 ap->ack_match = 0;
2809
2810                 rx_cfg_reg = 0;
2811         }
2812
2813         ap->rxconfig = rx_cfg_reg;
2814         ret = ANEG_OK;
2815
2816         switch(ap->state) {
2817         case ANEG_STATE_UNKNOWN:
2818                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2819                         ap->state = ANEG_STATE_AN_ENABLE;
2820
2821                 /* fallthru */
2822         case ANEG_STATE_AN_ENABLE:
2823                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2824                 if (ap->flags & MR_AN_ENABLE) {
2825                         ap->link_time = 0;
2826                         ap->cur_time = 0;
2827                         ap->ability_match_cfg = 0;
2828                         ap->ability_match_count = 0;
2829                         ap->ability_match = 0;
2830                         ap->idle_match = 0;
2831                         ap->ack_match = 0;
2832
2833                         ap->state = ANEG_STATE_RESTART_INIT;
2834                 } else {
2835                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2836                 }
2837                 break;
2838
2839         case ANEG_STATE_RESTART_INIT:
2840                 ap->link_time = ap->cur_time;
2841                 ap->flags &= ~(MR_NP_LOADED);
2842                 ap->txconfig = 0;
2843                 tw32(MAC_TX_AUTO_NEG, 0);
2844                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2845                 tw32_f(MAC_MODE, tp->mac_mode);
2846                 udelay(40);
2847
2848                 ret = ANEG_TIMER_ENAB;
2849                 ap->state = ANEG_STATE_RESTART;
2850
2851                 /* fallthru */
2852         case ANEG_STATE_RESTART:
2853                 delta = ap->cur_time - ap->link_time;
2854                 if (delta > ANEG_STATE_SETTLE_TIME) {
2855                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2856                 } else {
2857                         ret = ANEG_TIMER_ENAB;
2858                 }
2859                 break;
2860
2861         case ANEG_STATE_DISABLE_LINK_OK:
2862                 ret = ANEG_DONE;
2863                 break;
2864
2865         case ANEG_STATE_ABILITY_DETECT_INIT:
2866                 ap->flags &= ~(MR_TOGGLE_TX);
2867                 ap->txconfig = ANEG_CFG_FD;
2868                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2869                 if (flowctrl & ADVERTISE_1000XPAUSE)
2870                         ap->txconfig |= ANEG_CFG_PS1;
2871                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2872                         ap->txconfig |= ANEG_CFG_PS2;
2873                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2874                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2875                 tw32_f(MAC_MODE, tp->mac_mode);
2876                 udelay(40);
2877
2878                 ap->state = ANEG_STATE_ABILITY_DETECT;
2879                 break;
2880
2881         case ANEG_STATE_ABILITY_DETECT:
2882                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2883                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2884                 }
2885                 break;
2886
2887         case ANEG_STATE_ACK_DETECT_INIT:
2888                 ap->txconfig |= ANEG_CFG_ACK;
2889                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2890                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2891                 tw32_f(MAC_MODE, tp->mac_mode);
2892                 udelay(40);
2893
2894                 ap->state = ANEG_STATE_ACK_DETECT;
2895
2896                 /* fallthru */
2897         case ANEG_STATE_ACK_DETECT:
2898                 if (ap->ack_match != 0) {
2899                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2900                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2901                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2902                         } else {
2903                                 ap->state = ANEG_STATE_AN_ENABLE;
2904                         }
2905                 } else if (ap->ability_match != 0 &&
2906                            ap->rxconfig == 0) {
2907                         ap->state = ANEG_STATE_AN_ENABLE;
2908                 }
2909                 break;
2910
2911         case ANEG_STATE_COMPLETE_ACK_INIT:
2912                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2913                         ret = ANEG_FAILED;
2914                         break;
2915                 }
2916                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2917                                MR_LP_ADV_HALF_DUPLEX |
2918                                MR_LP_ADV_SYM_PAUSE |
2919                                MR_LP_ADV_ASYM_PAUSE |
2920                                MR_LP_ADV_REMOTE_FAULT1 |
2921                                MR_LP_ADV_REMOTE_FAULT2 |
2922                                MR_LP_ADV_NEXT_PAGE |
2923                                MR_TOGGLE_RX |
2924                                MR_NP_RX);
2925                 if (ap->rxconfig & ANEG_CFG_FD)
2926                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2927                 if (ap->rxconfig & ANEG_CFG_HD)
2928                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2929                 if (ap->rxconfig & ANEG_CFG_PS1)
2930                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2931                 if (ap->rxconfig & ANEG_CFG_PS2)
2932                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2933                 if (ap->rxconfig & ANEG_CFG_RF1)
2934                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2935                 if (ap->rxconfig & ANEG_CFG_RF2)
2936                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2937                 if (ap->rxconfig & ANEG_CFG_NP)
2938                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2939
2940                 ap->link_time = ap->cur_time;
2941
2942                 ap->flags ^= (MR_TOGGLE_TX);
2943                 if (ap->rxconfig & 0x0008)
2944                         ap->flags |= MR_TOGGLE_RX;
2945                 if (ap->rxconfig & ANEG_CFG_NP)
2946                         ap->flags |= MR_NP_RX;
2947                 ap->flags |= MR_PAGE_RX;
2948
2949                 ap->state = ANEG_STATE_COMPLETE_ACK;
2950                 ret = ANEG_TIMER_ENAB;
2951                 break;
2952
2953         case ANEG_STATE_COMPLETE_ACK:
2954                 if (ap->ability_match != 0 &&
2955                     ap->rxconfig == 0) {
2956                         ap->state = ANEG_STATE_AN_ENABLE;
2957                         break;
2958                 }
2959                 delta = ap->cur_time - ap->link_time;
2960                 if (delta > ANEG_STATE_SETTLE_TIME) {
2961                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2962                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2963                         } else {
2964                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2965                                     !(ap->flags & MR_NP_RX)) {
2966                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2967                                 } else {
2968                                         ret = ANEG_FAILED;
2969                                 }
2970                         }
2971                 }
2972                 break;
2973
2974         case ANEG_STATE_IDLE_DETECT_INIT:
2975                 ap->link_time = ap->cur_time;
2976                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2977                 tw32_f(MAC_MODE, tp->mac_mode);
2978                 udelay(40);
2979
2980                 ap->state = ANEG_STATE_IDLE_DETECT;
2981                 ret = ANEG_TIMER_ENAB;
2982                 break;
2983
2984         case ANEG_STATE_IDLE_DETECT:
2985                 if (ap->ability_match != 0 &&
2986                     ap->rxconfig == 0) {
2987                         ap->state = ANEG_STATE_AN_ENABLE;
2988                         break;
2989                 }
2990                 delta = ap->cur_time - ap->link_time;
2991                 if (delta > ANEG_STATE_SETTLE_TIME) {
2992                         /* XXX another gem from the Broadcom driver :( */
2993                         ap->state = ANEG_STATE_LINK_OK;
2994                 }
2995                 break;
2996
2997         case ANEG_STATE_LINK_OK:
2998                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2999                 ret = ANEG_DONE;
3000                 break;
3001
3002         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3003                 /* ??? unimplemented */
3004                 break;
3005
3006         case ANEG_STATE_NEXT_PAGE_WAIT:
3007                 /* ??? unimplemented */
3008                 break;
3009
3010         default:
3011                 ret = ANEG_FAILED;
3012                 break;
3013         };
3014
3015         return ret;
3016 }
3017
3018 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3019 {
3020         int res = 0;
3021         struct tg3_fiber_aneginfo aninfo;
3022         int status = ANEG_FAILED;
3023         unsigned int tick;
3024         u32 tmp;
3025
3026         tw32_f(MAC_TX_AUTO_NEG, 0);
3027
3028         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3029         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3030         udelay(40);
3031
3032         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3033         udelay(40);
3034
3035         memset(&aninfo, 0, sizeof(aninfo));
3036         aninfo.flags |= MR_AN_ENABLE;
3037         aninfo.state = ANEG_STATE_UNKNOWN;
3038         aninfo.cur_time = 0;
3039         tick = 0;
3040         while (++tick < 195000) {
3041                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3042                 if (status == ANEG_DONE || status == ANEG_FAILED)
3043                         break;
3044
3045                 udelay(1);
3046         }
3047
3048         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3049         tw32_f(MAC_MODE, tp->mac_mode);
3050         udelay(40);
3051
3052         *txflags = aninfo.txconfig;
3053         *rxflags = aninfo.flags;
3054
3055         if (status == ANEG_DONE &&
3056             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3057                              MR_LP_ADV_FULL_DUPLEX)))
3058                 res = 1;
3059
3060         return res;
3061 }
3062
3063 static void tg3_init_bcm8002(struct tg3 *tp)
3064 {
3065         u32 mac_status = tr32(MAC_STATUS);
3066         int i;
3067
3068         /* Reset when initting first time or we have a link. */
3069         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3070             !(mac_status & MAC_STATUS_PCS_SYNCED))
3071                 return;
3072
3073         /* Set PLL lock range. */
3074         tg3_writephy(tp, 0x16, 0x8007);
3075
3076         /* SW reset */
3077         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3078
3079         /* Wait for reset to complete. */
3080         /* XXX schedule_timeout() ... */
3081         for (i = 0; i < 500; i++)
3082                 udelay(10);
3083
3084         /* Config mode; select PMA/Ch 1 regs. */
3085         tg3_writephy(tp, 0x10, 0x8411);
3086
3087         /* Enable auto-lock and comdet, select txclk for tx. */
3088         tg3_writephy(tp, 0x11, 0x0a10);
3089
3090         tg3_writephy(tp, 0x18, 0x00a0);
3091         tg3_writephy(tp, 0x16, 0x41ff);
3092
3093         /* Assert and deassert POR. */
3094         tg3_writephy(tp, 0x13, 0x0400);
3095         udelay(40);
3096         tg3_writephy(tp, 0x13, 0x0000);
3097
3098         tg3_writephy(tp, 0x11, 0x0a50);
3099         udelay(40);
3100         tg3_writephy(tp, 0x11, 0x0a10);
3101
3102         /* Wait for signal to stabilize */
3103         /* XXX schedule_timeout() ... */
3104         for (i = 0; i < 15000; i++)
3105                 udelay(10);
3106
3107         /* Deselect the channel register so we can read the PHYID
3108          * later.
3109          */
3110         tg3_writephy(tp, 0x10, 0x8011);
3111 }
3112
3113 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3114 {
3115         u16 flowctrl;
3116         u32 sg_dig_ctrl, sg_dig_status;
3117         u32 serdes_cfg, expected_sg_dig_ctrl;
3118         int workaround, port_a;
3119         int current_link_up;
3120
3121         serdes_cfg = 0;
3122         expected_sg_dig_ctrl = 0;
3123         workaround = 0;
3124         port_a = 1;
3125         current_link_up = 0;
3126
3127         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3128             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3129                 workaround = 1;
3130                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3131                         port_a = 0;
3132
3133                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3134                 /* preserve bits 20-23 for voltage regulator */
3135                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3136         }
3137
3138         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3139
3140         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3141                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3142                         if (workaround) {
3143                                 u32 val = serdes_cfg;
3144
3145                                 if (port_a)
3146                                         val |= 0xc010000;
3147                                 else
3148                                         val |= 0x4010000;
3149                                 tw32_f(MAC_SERDES_CFG, val);
3150                         }
3151
3152                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3153                 }
3154                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3155                         tg3_setup_flow_control(tp, 0, 0);
3156                         current_link_up = 1;
3157                 }
3158                 goto out;
3159         }
3160
3161         /* Want auto-negotiation.  */
3162         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3163
3164         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3165         if (flowctrl & ADVERTISE_1000XPAUSE)
3166                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3167         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3168                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3169
3170         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3171                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3172                     tp->serdes_counter &&
3173                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3174                                     MAC_STATUS_RCVD_CFG)) ==
3175                      MAC_STATUS_PCS_SYNCED)) {
3176                         tp->serdes_counter--;
3177                         current_link_up = 1;
3178                         goto out;
3179                 }
3180 restart_autoneg:
3181                 if (workaround)
3182                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3183                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3184                 udelay(5);
3185                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3186
3187                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3188                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3189         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3190                                  MAC_STATUS_SIGNAL_DET)) {
3191                 sg_dig_status = tr32(SG_DIG_STATUS);
3192                 mac_status = tr32(MAC_STATUS);
3193
3194                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3195                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3196                         u32 local_adv = 0, remote_adv = 0;
3197
3198                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3199                                 local_adv |= ADVERTISE_1000XPAUSE;
3200                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3201                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3202
3203                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3204                                 remote_adv |= LPA_1000XPAUSE;
3205                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3206                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3207
3208                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3209                         current_link_up = 1;
3210                         tp->serdes_counter = 0;
3211                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3212                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3213                         if (tp->serdes_counter)
3214                                 tp->serdes_counter--;
3215                         else {
3216                                 if (workaround) {
3217                                         u32 val = serdes_cfg;
3218
3219                                         if (port_a)
3220                                                 val |= 0xc010000;
3221                                         else
3222                                                 val |= 0x4010000;
3223
3224                                         tw32_f(MAC_SERDES_CFG, val);
3225                                 }
3226
3227                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3228                                 udelay(40);
3229
3230                                 /* Link parallel detection - link is up */
3231                                 /* only if we have PCS_SYNC and not */
3232                                 /* receiving config code words */
3233                                 mac_status = tr32(MAC_STATUS);
3234                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3235                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3236                                         tg3_setup_flow_control(tp, 0, 0);
3237                                         current_link_up = 1;
3238                                         tp->tg3_flags2 |=
3239                                                 TG3_FLG2_PARALLEL_DETECT;
3240                                         tp->serdes_counter =
3241                                                 SERDES_PARALLEL_DET_TIMEOUT;
3242                                 } else
3243                                         goto restart_autoneg;
3244                         }
3245                 }
3246         } else {
3247                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3248                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3249         }
3250
3251 out:
3252         return current_link_up;
3253 }
3254
3255 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3256 {
3257         int current_link_up = 0;
3258
3259         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3260                 goto out;
3261
3262         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3263                 u32 txflags, rxflags;
3264                 int i;
3265
3266                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3267                         u32 local_adv = 0, remote_adv = 0;
3268
3269                         if (txflags & ANEG_CFG_PS1)
3270                                 local_adv |= ADVERTISE_1000XPAUSE;
3271                         if (txflags & ANEG_CFG_PS2)
3272                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3273
3274                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3275                                 remote_adv |= LPA_1000XPAUSE;
3276                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3277                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3278
3279                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3280
3281                         current_link_up = 1;
3282                 }
3283                 for (i = 0; i < 30; i++) {
3284                         udelay(20);
3285                         tw32_f(MAC_STATUS,
3286                                (MAC_STATUS_SYNC_CHANGED |
3287                                 MAC_STATUS_CFG_CHANGED));
3288                         udelay(40);
3289                         if ((tr32(MAC_STATUS) &
3290                              (MAC_STATUS_SYNC_CHANGED |
3291                               MAC_STATUS_CFG_CHANGED)) == 0)
3292                                 break;
3293                 }
3294
3295                 mac_status = tr32(MAC_STATUS);
3296                 if (current_link_up == 0 &&
3297                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3298                     !(mac_status & MAC_STATUS_RCVD_CFG))
3299                         current_link_up = 1;
3300         } else {
3301                 tg3_setup_flow_control(tp, 0, 0);
3302
3303                 /* Forcing 1000FD link up. */
3304                 current_link_up = 1;
3305
3306                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3307                 udelay(40);
3308
3309                 tw32_f(MAC_MODE, tp->mac_mode);
3310                 udelay(40);
3311         }
3312
3313 out:
3314         return current_link_up;
3315 }
3316
3317 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3318 {
3319         u32 orig_pause_cfg;
3320         u16 orig_active_speed;
3321         u8 orig_active_duplex;
3322         u32 mac_status;
3323         int current_link_up;
3324         int i;
3325
3326         orig_pause_cfg = tp->link_config.active_flowctrl;
3327         orig_active_speed = tp->link_config.active_speed;
3328         orig_active_duplex = tp->link_config.active_duplex;
3329
3330         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3331             netif_carrier_ok(tp->dev) &&
3332             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3333                 mac_status = tr32(MAC_STATUS);
3334                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3335                                MAC_STATUS_SIGNAL_DET |
3336                                MAC_STATUS_CFG_CHANGED |
3337                                MAC_STATUS_RCVD_CFG);
3338                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3339                                    MAC_STATUS_SIGNAL_DET)) {
3340                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3341                                             MAC_STATUS_CFG_CHANGED));
3342                         return 0;
3343                 }
3344         }
3345
3346         tw32_f(MAC_TX_AUTO_NEG, 0);
3347
3348         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3349         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3350         tw32_f(MAC_MODE, tp->mac_mode);
3351         udelay(40);
3352
3353         if (tp->phy_id == PHY_ID_BCM8002)
3354                 tg3_init_bcm8002(tp);
3355
3356         /* Enable link change event even when serdes polling.  */
3357         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3358         udelay(40);
3359
3360         current_link_up = 0;
3361         mac_status = tr32(MAC_STATUS);
3362
3363         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3364                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3365         else
3366                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3367
3368         tp->hw_status->status =
3369                 (SD_STATUS_UPDATED |
3370                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3371
3372         for (i = 0; i < 100; i++) {
3373                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3374                                     MAC_STATUS_CFG_CHANGED));
3375                 udelay(5);
3376                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3377                                          MAC_STATUS_CFG_CHANGED |
3378                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3379                         break;
3380         }
3381
3382         mac_status = tr32(MAC_STATUS);
3383         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3384                 current_link_up = 0;
3385                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3386                     tp->serdes_counter == 0) {
3387                         tw32_f(MAC_MODE, (tp->mac_mode |
3388                                           MAC_MODE_SEND_CONFIGS));
3389                         udelay(1);
3390                         tw32_f(MAC_MODE, tp->mac_mode);
3391                 }
3392         }
3393
3394         if (current_link_up == 1) {
3395                 tp->link_config.active_speed = SPEED_1000;
3396                 tp->link_config.active_duplex = DUPLEX_FULL;
3397                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3398                                     LED_CTRL_LNKLED_OVERRIDE |
3399                                     LED_CTRL_1000MBPS_ON));
3400         } else {
3401                 tp->link_config.active_speed = SPEED_INVALID;
3402                 tp->link_config.active_duplex = DUPLEX_INVALID;
3403                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3404                                     LED_CTRL_LNKLED_OVERRIDE |
3405                                     LED_CTRL_TRAFFIC_OVERRIDE));
3406         }
3407
3408         if (current_link_up != netif_carrier_ok(tp->dev)) {
3409                 if (current_link_up)
3410                         netif_carrier_on(tp->dev);
3411                 else
3412                         netif_carrier_off(tp->dev);
3413                 tg3_link_report(tp);
3414         } else {
3415                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3416                 if (orig_pause_cfg != now_pause_cfg ||
3417                     orig_active_speed != tp->link_config.active_speed ||
3418                     orig_active_duplex != tp->link_config.active_duplex)
3419                         tg3_link_report(tp);
3420         }
3421
3422         return 0;
3423 }
3424
3425 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3426 {
3427         int current_link_up, err = 0;
3428         u32 bmsr, bmcr;
3429         u16 current_speed;
3430         u8 current_duplex;
3431         u32 local_adv, remote_adv;
3432
3433         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3434         tw32_f(MAC_MODE, tp->mac_mode);
3435         udelay(40);
3436
3437         tw32(MAC_EVENT, 0);
3438
3439         tw32_f(MAC_STATUS,
3440              (MAC_STATUS_SYNC_CHANGED |
3441               MAC_STATUS_CFG_CHANGED |
3442               MAC_STATUS_MI_COMPLETION |
3443               MAC_STATUS_LNKSTATE_CHANGED));
3444         udelay(40);
3445
3446         if (force_reset)
3447                 tg3_phy_reset(tp);
3448
3449         current_link_up = 0;
3450         current_speed = SPEED_INVALID;
3451         current_duplex = DUPLEX_INVALID;
3452
3453         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3454         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3455         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3456                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3457                         bmsr |= BMSR_LSTATUS;
3458                 else
3459                         bmsr &= ~BMSR_LSTATUS;
3460         }
3461
3462         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3463
3464         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3465             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3466              tp->link_config.flowctrl == tp->link_config.active_flowctrl) {
3467                 /* do nothing, just check for link up at the end */
3468         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3469                 u32 adv, new_adv;
3470
3471                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3472                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3473                                   ADVERTISE_1000XPAUSE |
3474                                   ADVERTISE_1000XPSE_ASYM |
3475                                   ADVERTISE_SLCT);
3476
3477                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3478
3479                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3480                         new_adv |= ADVERTISE_1000XHALF;
3481                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3482                         new_adv |= ADVERTISE_1000XFULL;
3483
3484                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3485                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3486                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3487                         tg3_writephy(tp, MII_BMCR, bmcr);
3488
3489                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3490                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3491                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3492
3493                         return err;
3494                 }
3495         } else {
3496                 u32 new_bmcr;
3497
3498                 bmcr &= ~BMCR_SPEED1000;
3499                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3500
3501                 if (tp->link_config.duplex == DUPLEX_FULL)
3502                         new_bmcr |= BMCR_FULLDPLX;
3503
3504                 if (new_bmcr != bmcr) {
3505                         /* BMCR_SPEED1000 is a reserved bit that needs
3506                          * to be set on write.
3507                          */
3508                         new_bmcr |= BMCR_SPEED1000;
3509
3510                         /* Force a linkdown */
3511                         if (netif_carrier_ok(tp->dev)) {
3512                                 u32 adv;
3513
3514                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3515                                 adv &= ~(ADVERTISE_1000XFULL |
3516                                          ADVERTISE_1000XHALF |
3517                                          ADVERTISE_SLCT);
3518                                 tg3_writephy(tp, MII_ADVERTISE, adv);
3519                                 tg3_writephy(tp, MII_BMCR, bmcr |
3520                                                            BMCR_ANRESTART |
3521                                                            BMCR_ANENABLE);
3522                                 udelay(10);
3523                                 netif_carrier_off(tp->dev);
3524                         }
3525                         tg3_writephy(tp, MII_BMCR, new_bmcr);
3526                         bmcr = new_bmcr;
3527                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3528                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3529                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3530                             ASIC_REV_5714) {
3531                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3532                                         bmsr |= BMSR_LSTATUS;
3533                                 else
3534                                         bmsr &= ~BMSR_LSTATUS;
3535                         }
3536                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3537                 }
3538         }
3539
3540         if (bmsr & BMSR_LSTATUS) {
3541                 current_speed = SPEED_1000;
3542                 current_link_up = 1;
3543                 if (bmcr & BMCR_FULLDPLX)
3544                         current_duplex = DUPLEX_FULL;
3545                 else
3546                         current_duplex = DUPLEX_HALF;
3547
3548                 local_adv = 0;
3549                 remote_adv = 0;
3550
3551                 if (bmcr & BMCR_ANENABLE) {
3552                         u32 common;
3553
3554                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3555                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3556                         common = local_adv & remote_adv;
3557                         if (common & (ADVERTISE_1000XHALF |
3558                                       ADVERTISE_1000XFULL)) {
3559                                 if (common & ADVERTISE_1000XFULL)
3560                                         current_duplex = DUPLEX_FULL;
3561                                 else
3562                                         current_duplex = DUPLEX_HALF;
3563                         }
3564                         else
3565                                 current_link_up = 0;
3566                 }
3567         }
3568
3569         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3570                 tg3_setup_flow_control(tp, local_adv, remote_adv);
3571
3572         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3573         if (tp->link_config.active_duplex == DUPLEX_HALF)
3574                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3575
3576         tw32_f(MAC_MODE, tp->mac_mode);
3577         udelay(40);
3578
3579         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3580
3581         tp->link_config.active_speed = current_speed;
3582         tp->link_config.active_duplex = current_duplex;
3583
3584         if (current_link_up != netif_carrier_ok(tp->dev)) {
3585                 if (current_link_up)
3586                         netif_carrier_on(tp->dev);
3587                 else {
3588                         netif_carrier_off(tp->dev);
3589                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3590                 }
3591                 tg3_link_report(tp);
3592         }
3593         return err;
3594 }
3595
3596 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3597 {
3598         if (tp->serdes_counter) {
3599                 /* Give autoneg time to complete. */
3600                 tp->serdes_counter--;
3601                 return;
3602         }
3603         if (!netif_carrier_ok(tp->dev) &&
3604             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3605                 u32 bmcr;
3606
3607                 tg3_readphy(tp, MII_BMCR, &bmcr);
3608                 if (bmcr & BMCR_ANENABLE) {
3609                         u32 phy1, phy2;
3610
3611                         /* Select shadow register 0x1f */
3612                         tg3_writephy(tp, 0x1c, 0x7c00);
3613                         tg3_readphy(tp, 0x1c, &phy1);
3614
3615                         /* Select expansion interrupt status register */
3616                         tg3_writephy(tp, 0x17, 0x0f01);
3617                         tg3_readphy(tp, 0x15, &phy2);
3618                         tg3_readphy(tp, 0x15, &phy2);
3619
3620                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3621                                 /* We have signal detect and not receiving
3622                                  * config code words, link is up by parallel
3623                                  * detection.
3624                                  */
3625
3626                                 bmcr &= ~BMCR_ANENABLE;
3627                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3628                                 tg3_writephy(tp, MII_BMCR, bmcr);
3629                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3630                         }
3631                 }
3632         }
3633         else if (netif_carrier_ok(tp->dev) &&
3634                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3635                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3636                 u32 phy2;
3637
3638                 /* Select expansion interrupt status register */
3639                 tg3_writephy(tp, 0x17, 0x0f01);
3640                 tg3_readphy(tp, 0x15, &phy2);
3641                 if (phy2 & 0x20) {
3642                         u32 bmcr;
3643
3644                         /* Config code words received, turn on autoneg. */
3645                         tg3_readphy(tp, MII_BMCR, &bmcr);
3646                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3647
3648                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3649
3650                 }
3651         }
3652 }
3653
3654 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3655 {
3656         int err;
3657
3658         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3659                 err = tg3_setup_fiber_phy(tp, force_reset);
3660         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3661                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3662         } else {
3663                 err = tg3_setup_copper_phy(tp, force_reset);
3664         }
3665
3666         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3667             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3668                 u32 val, scale;
3669
3670                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3671                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3672                         scale = 65;
3673                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3674                         scale = 6;
3675                 else
3676                         scale = 12;
3677
3678                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3679                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3680                 tw32(GRC_MISC_CFG, val);
3681         }
3682
3683         if (tp->link_config.active_speed == SPEED_1000 &&
3684             tp->link_config.active_duplex == DUPLEX_HALF)
3685                 tw32(MAC_TX_LENGTHS,
3686                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3687                       (6 << TX_LENGTHS_IPG_SHIFT) |
3688                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3689         else
3690                 tw32(MAC_TX_LENGTHS,
3691                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3692                       (6 << TX_LENGTHS_IPG_SHIFT) |
3693                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3694
3695         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3696                 if (netif_carrier_ok(tp->dev)) {
3697                         tw32(HOSTCC_STAT_COAL_TICKS,
3698                              tp->coal.stats_block_coalesce_usecs);
3699                 } else {
3700                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3701                 }
3702         }
3703
3704         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3705                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3706                 if (!netif_carrier_ok(tp->dev))
3707                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3708                               tp->pwrmgmt_thresh;
3709                 else
3710                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3711                 tw32(PCIE_PWR_MGMT_THRESH, val);
3712         }
3713
3714         return err;
3715 }
3716
3717 /* This is called whenever we suspect that the system chipset is re-
3718  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3719  * is bogus tx completions. We try to recover by setting the
3720  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3721  * in the workqueue.
3722  */
3723 static void tg3_tx_recover(struct tg3 *tp)
3724 {
3725         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3726                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3727
3728         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3729                "mapped I/O cycles to the network device, attempting to "
3730                "recover. Please report the problem to the driver maintainer "
3731                "and include system chipset information.\n", tp->dev->name);
3732
3733         spin_lock(&tp->lock);
3734         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3735         spin_unlock(&tp->lock);
3736 }
3737
3738 static inline u32 tg3_tx_avail(struct tg3 *tp)
3739 {
3740         smp_mb();
3741         return (tp->tx_pending -
3742                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3743 }
3744
3745 /* Tigon3 never reports partial packet sends.  So we do not
3746  * need special logic to handle SKBs that have not had all
3747  * of their frags sent yet, like SunGEM does.
3748  */
3749 static void tg3_tx(struct tg3 *tp)
3750 {
3751         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3752         u32 sw_idx = tp->tx_cons;
3753
3754         while (sw_idx != hw_idx) {
3755                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3756                 struct sk_buff *skb = ri->skb;
3757                 int i, tx_bug = 0;
3758
3759                 if (unlikely(skb == NULL)) {
3760                         tg3_tx_recover(tp);
3761                         return;
3762                 }
3763
3764                 pci_unmap_single(tp->pdev,
3765                                  pci_unmap_addr(ri, mapping),
3766                                  skb_headlen(skb),
3767                                  PCI_DMA_TODEVICE);
3768
3769                 ri->skb = NULL;
3770
3771                 sw_idx = NEXT_TX(sw_idx);
3772
3773                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3774                         ri = &tp->tx_buffers[sw_idx];
3775                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3776                                 tx_bug = 1;
3777
3778                         pci_unmap_page(tp->pdev,
3779                                        pci_unmap_addr(ri, mapping),
3780                                        skb_shinfo(skb)->frags[i].size,
3781                                        PCI_DMA_TODEVICE);
3782
3783                         sw_idx = NEXT_TX(sw_idx);
3784                 }
3785
3786                 dev_kfree_skb(skb);
3787
3788                 if (unlikely(tx_bug)) {
3789                         tg3_tx_recover(tp);
3790                         return;
3791                 }
3792         }
3793
3794         tp->tx_cons = sw_idx;
3795
3796         /* Need to make the tx_cons update visible to tg3_start_xmit()
3797          * before checking for netif_queue_stopped().  Without the
3798          * memory barrier, there is a small possibility that tg3_start_xmit()
3799          * will miss it and cause the queue to be stopped forever.
3800          */
3801         smp_mb();
3802
3803         if (unlikely(netif_queue_stopped(tp->dev) &&
3804                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3805                 netif_tx_lock(tp->dev);
3806                 if (netif_queue_stopped(tp->dev) &&
3807                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3808                         netif_wake_queue(tp->dev);
3809                 netif_tx_unlock(tp->dev);
3810         }
3811 }
3812
3813 /* Returns size of skb allocated or < 0 on error.
3814  *
3815  * We only need to fill in the address because the other members
3816  * of the RX descriptor are invariant, see tg3_init_rings.
3817  *
3818  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3819  * posting buffers we only dirty the first cache line of the RX
3820  * descriptor (containing the address).  Whereas for the RX status
3821  * buffers the cpu only reads the last cacheline of the RX descriptor
3822  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3823  */
3824 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3825                             int src_idx, u32 dest_idx_unmasked)
3826 {
3827         struct tg3_rx_buffer_desc *desc;
3828         struct ring_info *map, *src_map;
3829         struct sk_buff *skb;
3830         dma_addr_t mapping;
3831         int skb_size, dest_idx;
3832
3833         src_map = NULL;
3834         switch (opaque_key) {
3835         case RXD_OPAQUE_RING_STD:
3836                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3837                 desc = &tp->rx_std[dest_idx];
3838                 map = &tp->rx_std_buffers[dest_idx];
3839                 if (src_idx >= 0)
3840                         src_map = &tp->rx_std_buffers[src_idx];
3841                 skb_size = tp->rx_pkt_buf_sz;
3842                 break;
3843
3844         case RXD_OPAQUE_RING_JUMBO:
3845                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3846                 desc = &tp->rx_jumbo[dest_idx];
3847                 map = &tp->rx_jumbo_buffers[dest_idx];
3848                 if (src_idx >= 0)
3849                         src_map = &tp->rx_jumbo_buffers[src_idx];
3850                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3851                 break;
3852
3853         default:
3854                 return -EINVAL;
3855         };
3856
3857         /* Do not overwrite any of the map or rp information
3858          * until we are sure we can commit to a new buffer.
3859          *
3860          * Callers depend upon this behavior and assume that
3861          * we leave everything unchanged if we fail.
3862          */
3863         skb = netdev_alloc_skb(tp->dev, skb_size);
3864         if (skb == NULL)
3865                 return -ENOMEM;
3866
3867         skb_reserve(skb, tp->rx_offset);
3868
3869         mapping = pci_map_single(tp->pdev, skb->data,
3870                                  skb_size - tp->rx_offset,
3871                                  PCI_DMA_FROMDEVICE);
3872
3873         map->skb = skb;
3874         pci_unmap_addr_set(map, mapping, mapping);
3875
3876         if (src_map != NULL)
3877                 src_map->skb = NULL;
3878
3879         desc->addr_hi = ((u64)mapping >> 32);
3880         desc->addr_lo = ((u64)mapping & 0xffffffff);
3881
3882         return skb_size;
3883 }
3884
3885 /* We only need to move over in the address because the other
3886  * members of the RX descriptor are invariant.  See notes above
3887  * tg3_alloc_rx_skb for full details.
3888  */
3889 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3890                            int src_idx, u32 dest_idx_unmasked)
3891 {
3892         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3893         struct ring_info *src_map, *dest_map;
3894         int dest_idx;
3895
3896         switch (opaque_key) {
3897         case RXD_OPAQUE_RING_STD:
3898                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3899                 dest_desc = &tp->rx_std[dest_idx];
3900                 dest_map = &tp->rx_std_buffers[dest_idx];
3901                 src_desc = &tp->rx_std[src_idx];
3902                 src_map = &tp->rx_std_buffers[src_idx];
3903                 break;
3904
3905         case RXD_OPAQUE_RING_JUMBO:
3906                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3907                 dest_desc = &tp->rx_jumbo[dest_idx];
3908                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3909                 src_desc = &tp->rx_jumbo[src_idx];
3910                 src_map = &tp->rx_jumbo_buffers[src_idx];
3911                 break;
3912
3913         default:
3914                 return;
3915         };
3916
3917         dest_map->skb = src_map->skb;
3918         pci_unmap_addr_set(dest_map, mapping,
3919                            pci_unmap_addr(src_map, mapping));
3920         dest_desc->addr_hi = src_desc->addr_hi;
3921         dest_desc->addr_lo = src_desc->addr_lo;
3922
3923         src_map->skb = NULL;
3924 }
3925
3926 #if TG3_VLAN_TAG_USED
3927 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3928 {
3929         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3930 }
3931 #endif
3932
3933 /* The RX ring scheme is composed of multiple rings which post fresh
3934  * buffers to the chip, and one special ring the chip uses to report
3935  * status back to the host.
3936  *
3937  * The special ring reports the status of received packets to the
3938  * host.  The chip does not write into the original descriptor the
3939  * RX buffer was obtained from.  The chip simply takes the original
3940  * descriptor as provided by the host, updates the status and length
3941  * field, then writes this into the next status ring entry.
3942  *
3943  * Each ring the host uses to post buffers to the chip is described
3944  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3945  * it is first placed into the on-chip ram.  When the packet's length
3946  * is known, it walks down the TG3_BDINFO entries to select the ring.
3947  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3948  * which is within the range of the new packet's length is chosen.
3949  *
3950  * The "separate ring for rx status" scheme may sound queer, but it makes
3951  * sense from a cache coherency perspective.  If only the host writes
3952  * to the buffer post rings, and only the chip writes to the rx status
3953  * rings, then cache lines never move beyond shared-modified state.
3954  * If both the host and chip were to write into the same ring, cache line
3955  * eviction could occur since both entities want it in an exclusive state.
3956  */
3957 static int tg3_rx(struct tg3 *tp, int budget)
3958 {
3959         u32 work_mask, rx_std_posted = 0;
3960         u32 sw_idx = tp->rx_rcb_ptr;
3961         u16 hw_idx;
3962         int received;
3963
3964         hw_idx = tp->hw_status->idx[0].rx_producer;
3965         /*
3966          * We need to order the read of hw_idx and the read of
3967          * the opaque cookie.
3968          */
3969         rmb();
3970         work_mask = 0;
3971         received = 0;
3972         while (sw_idx != hw_idx && budget > 0) {
3973                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3974                 unsigned int len;
3975                 struct sk_buff *skb;
3976                 dma_addr_t dma_addr;
3977                 u32 opaque_key, desc_idx, *post_ptr;
3978
3979                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3980                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3981                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3982                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3983                                                   mapping);
3984                         skb = tp->rx_std_buffers[desc_idx].skb;
3985                         post_ptr = &tp->rx_std_ptr;
3986                         rx_std_posted++;
3987                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3988                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3989                                                   mapping);
3990                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3991                         post_ptr = &tp->rx_jumbo_ptr;
3992                 }
3993                 else {
3994                         goto next_pkt_nopost;
3995                 }
3996
3997                 work_mask |= opaque_key;
3998
3999                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4000                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4001                 drop_it:
4002                         tg3_recycle_rx(tp, opaque_key,
4003                                        desc_idx, *post_ptr);
4004                 drop_it_no_recycle:
4005                         /* Other statistics kept track of by card. */
4006                         tp->net_stats.rx_dropped++;
4007                         goto next_pkt;
4008                 }
4009
4010                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
4011
4012                 if (len > RX_COPY_THRESHOLD
4013                         && tp->rx_offset == 2
4014                         /* rx_offset != 2 iff this is a 5701 card running
4015                          * in PCI-X mode [see tg3_get_invariants()] */
4016                 ) {
4017                         int skb_size;
4018
4019                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4020                                                     desc_idx, *post_ptr);
4021                         if (skb_size < 0)
4022                                 goto drop_it;
4023
4024                         pci_unmap_single(tp->pdev, dma_addr,
4025                                          skb_size - tp->rx_offset,
4026                                          PCI_DMA_FROMDEVICE);
4027
4028                         skb_put(skb, len);
4029                 } else {
4030                         struct sk_buff *copy_skb;
4031
4032                         tg3_recycle_rx(tp, opaque_key,
4033                                        desc_idx, *post_ptr);
4034
4035                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
4036                         if (copy_skb == NULL)
4037                                 goto drop_it_no_recycle;
4038
4039                         skb_reserve(copy_skb, 2);
4040                         skb_put(copy_skb, len);
4041                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4042                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4043                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4044
4045                         /* We'll reuse the original ring buffer. */
4046                         skb = copy_skb;
4047                 }
4048
4049                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4050                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4051                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4052                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4053                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4054                 else
4055                         skb->ip_summed = CHECKSUM_NONE;
4056
4057                 skb->protocol = eth_type_trans(skb, tp->dev);
4058 #if TG3_VLAN_TAG_USED
4059                 if (tp->vlgrp != NULL &&
4060                     desc->type_flags & RXD_FLAG_VLAN) {
4061                         tg3_vlan_rx(tp, skb,
4062                                     desc->err_vlan & RXD_VLAN_MASK);
4063                 } else
4064 #endif
4065                         netif_receive_skb(skb);
4066
4067                 tp->dev->last_rx = jiffies;
4068                 received++;
4069                 budget--;
4070
4071 next_pkt:
4072                 (*post_ptr)++;
4073
4074                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4075                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4076
4077                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4078                                      TG3_64BIT_REG_LOW, idx);
4079                         work_mask &= ~RXD_OPAQUE_RING_STD;
4080                         rx_std_posted = 0;
4081                 }
4082 next_pkt_nopost:
4083                 sw_idx++;
4084                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4085
4086                 /* Refresh hw_idx to see if there is new work */
4087                 if (sw_idx == hw_idx) {
4088                         hw_idx = tp->hw_status->idx[0].rx_producer;
4089                         rmb();
4090                 }
4091         }
4092
4093         /* ACK the status ring. */
4094         tp->rx_rcb_ptr = sw_idx;
4095         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4096
4097         /* Refill RX ring(s). */
4098         if (work_mask & RXD_OPAQUE_RING_STD) {
4099                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4100                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4101                              sw_idx);
4102         }
4103         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4104                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4105                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4106                              sw_idx);
4107         }
4108         mmiowb();
4109
4110         return received;
4111 }
4112
4113 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4114 {
4115         struct tg3_hw_status *sblk = tp->hw_status;
4116
4117         /* handle link change and other phy events */
4118         if (!(tp->tg3_flags &
4119               (TG3_FLAG_USE_LINKCHG_REG |
4120                TG3_FLAG_POLL_SERDES))) {
4121                 if (sblk->status & SD_STATUS_LINK_CHG) {
4122                         sblk->status = SD_STATUS_UPDATED |
4123                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4124                         spin_lock(&tp->lock);
4125                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4126                                 tw32_f(MAC_STATUS,
4127                                      (MAC_STATUS_SYNC_CHANGED |
4128                                       MAC_STATUS_CFG_CHANGED |
4129                                       MAC_STATUS_MI_COMPLETION |
4130                                       MAC_STATUS_LNKSTATE_CHANGED));
4131                                 udelay(40);
4132                         } else
4133                                 tg3_setup_phy(tp, 0);
4134                         spin_unlock(&tp->lock);
4135                 }
4136         }
4137
4138         /* run TX completion thread */
4139         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4140                 tg3_tx(tp);
4141                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4142                         return work_done;
4143         }
4144
4145         /* run RX thread, within the bounds set by NAPI.
4146          * All RX "locking" is done by ensuring outside
4147          * code synchronizes with tg3->napi.poll()
4148          */
4149         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4150                 work_done += tg3_rx(tp, budget - work_done);
4151
4152         return work_done;
4153 }
4154
4155 static int tg3_poll(struct napi_struct *napi, int budget)
4156 {
4157         struct tg3 *tp = container_of(napi, struct tg3, napi);
4158         int work_done = 0;
4159         struct tg3_hw_status *sblk = tp->hw_status;
4160
4161         while (1) {
4162                 work_done = tg3_poll_work(tp, work_done, budget);
4163
4164                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4165                         goto tx_recovery;
4166
4167                 if (unlikely(work_done >= budget))
4168                         break;
4169
4170                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4171                         /* tp->last_tag is used in tg3_restart_ints() below
4172                          * to tell the hw how much work has been processed,
4173                          * so we must read it before checking for more work.
4174                          */
4175                         tp->last_tag = sblk->status_tag;
4176                         rmb();
4177                 } else
4178                         sblk->status &= ~SD_STATUS_UPDATED;
4179
4180                 if (likely(!tg3_has_work(tp))) {
4181                         netif_rx_complete(tp->dev, napi);
4182                         tg3_restart_ints(tp);
4183                         break;
4184                 }
4185         }
4186
4187         return work_done;
4188
4189 tx_recovery:
4190         /* work_done is guaranteed to be less than budget. */
4191         netif_rx_complete(tp->dev, napi);
4192         schedule_work(&tp->reset_task);
4193         return work_done;
4194 }
4195
4196 static void tg3_irq_quiesce(struct tg3 *tp)
4197 {
4198         BUG_ON(tp->irq_sync);
4199
4200         tp->irq_sync = 1;
4201         smp_mb();
4202
4203         synchronize_irq(tp->pdev->irq);
4204 }
4205
4206 static inline int tg3_irq_sync(struct tg3 *tp)
4207 {
4208         return tp->irq_sync;
4209 }
4210
4211 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4212  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4213  * with as well.  Most of the time, this is not necessary except when
4214  * shutting down the device.
4215  */
4216 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4217 {
4218         spin_lock_bh(&tp->lock);
4219         if (irq_sync)
4220                 tg3_irq_quiesce(tp);
4221 }
4222
4223 static inline void tg3_full_unlock(struct tg3 *tp)
4224 {
4225         spin_unlock_bh(&tp->lock);
4226 }
4227
4228 /* One-shot MSI handler - Chip automatically disables interrupt
4229  * after sending MSI so driver doesn't have to do it.
4230  */
4231 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4232 {
4233         struct net_device *dev = dev_id;
4234         struct tg3 *tp = netdev_priv(dev);
4235
4236         prefetch(tp->hw_status);
4237         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4238
4239         if (likely(!tg3_irq_sync(tp)))
4240                 netif_rx_schedule(dev, &tp->napi);
4241
4242         return IRQ_HANDLED;
4243 }
4244
4245 /* MSI ISR - No need to check for interrupt sharing and no need to
4246  * flush status block and interrupt mailbox. PCI ordering rules
4247  * guarantee that MSI will arrive after the status block.
4248  */
4249 static irqreturn_t tg3_msi(int irq, void *dev_id)
4250 {
4251         struct net_device *dev = dev_id;
4252         struct tg3 *tp = netdev_priv(dev);
4253
4254         prefetch(tp->hw_status);
4255         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4256         /*
4257          * Writing any value to intr-mbox-0 clears PCI INTA# and
4258          * chip-internal interrupt pending events.
4259          * Writing non-zero to intr-mbox-0 additional tells the
4260          * NIC to stop sending us irqs, engaging "in-intr-handler"
4261          * event coalescing.
4262          */
4263         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4264         if (likely(!tg3_irq_sync(tp)))
4265                 netif_rx_schedule(dev, &tp->napi);
4266
4267         return IRQ_RETVAL(1);
4268 }
4269
4270 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4271 {
4272         struct net_device *dev = dev_id;
4273         struct tg3 *tp = netdev_priv(dev);
4274         struct tg3_hw_status *sblk = tp->hw_status;
4275         unsigned int handled = 1;
4276
4277         /* In INTx mode, it is possible for the interrupt to arrive at
4278          * the CPU before the status block posted prior to the interrupt.
4279          * Reading the PCI State register will confirm whether the
4280          * interrupt is ours and will flush the status block.
4281          */
4282         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4283                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4284                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4285                         handled = 0;
4286                         goto out;
4287                 }
4288         }
4289
4290         /*
4291          * Writing any value to intr-mbox-0 clears PCI INTA# and
4292          * chip-internal interrupt pending events.
4293          * Writing non-zero to intr-mbox-0 additional tells the
4294          * NIC to stop sending us irqs, engaging "in-intr-handler"
4295          * event coalescing.
4296          *
4297          * Flush the mailbox to de-assert the IRQ immediately to prevent
4298          * spurious interrupts.  The flush impacts performance but
4299          * excessive spurious interrupts can be worse in some cases.
4300          */
4301         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4302         if (tg3_irq_sync(tp))
4303                 goto out;
4304         sblk->status &= ~SD_STATUS_UPDATED;
4305         if (likely(tg3_has_work(tp))) {
4306                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4307                 netif_rx_schedule(dev, &tp->napi);
4308         } else {
4309                 /* No work, shared interrupt perhaps?  re-enable
4310                  * interrupts, and flush that PCI write
4311                  */
4312                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4313                                0x00000000);
4314         }
4315 out:
4316         return IRQ_RETVAL(handled);
4317 }
4318
4319 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4320 {
4321         struct net_device *dev = dev_id;
4322         struct tg3 *tp = netdev_priv(dev);
4323         struct tg3_hw_status *sblk = tp->hw_status;
4324         unsigned int handled = 1;
4325
4326         /* In INTx mode, it is possible for the interrupt to arrive at
4327          * the CPU before the status block posted prior to the interrupt.
4328          * Reading the PCI State register will confirm whether the
4329          * interrupt is ours and will flush the status block.
4330          */
4331         if (unlikely(sblk->status_tag == tp->last_tag)) {
4332                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4333                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4334                         handled = 0;
4335                         goto out;
4336                 }
4337         }
4338
4339         /*
4340          * writing any value to intr-mbox-0 clears PCI INTA# and
4341          * chip-internal interrupt pending events.
4342          * writing non-zero to intr-mbox-0 additional tells the
4343          * NIC to stop sending us irqs, engaging "in-intr-handler"
4344          * event coalescing.
4345          *
4346          * Flush the mailbox to de-assert the IRQ immediately to prevent
4347          * spurious interrupts.  The flush impacts performance but
4348          * excessive spurious interrupts can be worse in some cases.
4349          */
4350         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4351         if (tg3_irq_sync(tp))
4352                 goto out;
4353         if (netif_rx_schedule_prep(dev, &tp->napi)) {
4354                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4355                 /* Update last_tag to mark that this status has been
4356                  * seen. Because interrupt may be shared, we may be
4357                  * racing with tg3_poll(), so only update last_tag
4358                  * if tg3_poll() is not scheduled.
4359                  */
4360                 tp->last_tag = sblk->status_tag;
4361                 __netif_rx_schedule(dev, &tp->napi);
4362         }
4363 out:
4364         return IRQ_RETVAL(handled);
4365 }
4366
4367 /* ISR for interrupt test */
4368 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4369 {
4370         struct net_device *dev = dev_id;
4371         struct tg3 *tp = netdev_priv(dev);
4372         struct tg3_hw_status *sblk = tp->hw_status;
4373
4374         if ((sblk->status & SD_STATUS_UPDATED) ||
4375             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4376                 tg3_disable_ints(tp);
4377                 return IRQ_RETVAL(1);
4378         }
4379         return IRQ_RETVAL(0);
4380 }
4381
4382 static int tg3_init_hw(struct tg3 *, int);
4383 static int tg3_halt(struct tg3 *, int, int);
4384
4385 /* Restart hardware after configuration changes, self-test, etc.
4386  * Invoked with tp->lock held.
4387  */
4388 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4389         __releases(tp->lock)
4390         __acquires(tp->lock)
4391 {
4392         int err;
4393
4394         err = tg3_init_hw(tp, reset_phy);
4395         if (err) {
4396                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4397                        "aborting.\n", tp->dev->name);
4398                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4399                 tg3_full_unlock(tp);
4400                 del_timer_sync(&tp->timer);
4401                 tp->irq_sync = 0;
4402                 napi_enable(&tp->napi);
4403                 dev_close(tp->dev);
4404                 tg3_full_lock(tp, 0);
4405         }
4406         return err;
4407 }
4408
4409 #ifdef CONFIG_NET_POLL_CONTROLLER
4410 static void tg3_poll_controller(struct net_device *dev)
4411 {
4412         struct tg3 *tp = netdev_priv(dev);
4413
4414         tg3_interrupt(tp->pdev->irq, dev);
4415 }
4416 #endif
4417
4418 static void tg3_reset_task(struct work_struct *work)
4419 {
4420         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4421         int err;
4422         unsigned int restart_timer;
4423
4424         tg3_full_lock(tp, 0);
4425
4426         if (!netif_running(tp->dev)) {
4427                 tg3_full_unlock(tp);
4428                 return;
4429         }
4430
4431         tg3_full_unlock(tp);
4432
4433         tg3_phy_stop(tp);
4434
4435         tg3_netif_stop(tp);
4436
4437         tg3_full_lock(tp, 1);
4438
4439         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4440         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4441
4442         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4443                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4444                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4445                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4446                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4447         }
4448
4449         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4450         err = tg3_init_hw(tp, 1);
4451         if (err)
4452                 goto out;
4453
4454         tg3_netif_start(tp);
4455
4456         if (restart_timer)
4457                 mod_timer(&tp->timer, jiffies + 1);
4458
4459 out:
4460         tg3_full_unlock(tp);
4461
4462         if (!err)
4463                 tg3_phy_start(tp);
4464 }
4465
4466 static void tg3_dump_short_state(struct tg3 *tp)
4467 {
4468         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4469                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4470         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4471                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4472 }
4473
4474 static void tg3_tx_timeout(struct net_device *dev)
4475 {
4476         struct tg3 *tp = netdev_priv(dev);
4477
4478         if (netif_msg_tx_err(tp)) {
4479                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4480                        dev->name);
4481                 tg3_dump_short_state(tp);
4482         }
4483
4484         schedule_work(&tp->reset_task);
4485 }
4486
4487 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4488 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4489 {
4490         u32 base = (u32) mapping & 0xffffffff;
4491
4492         return ((base > 0xffffdcc0) &&
4493                 (base + len + 8 < base));
4494 }
4495
4496 /* Test for DMA addresses > 40-bit */
4497 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4498                                           int len)
4499 {
4500 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4501         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4502                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4503         return 0;
4504 #else
4505         return 0;
4506 #endif
4507 }
4508
4509 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4510
4511 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4512 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4513                                        u32 last_plus_one, u32 *start,
4514                                        u32 base_flags, u32 mss)
4515 {
4516         struct sk_buff *new_skb;
4517         dma_addr_t new_addr = 0;
4518         u32 entry = *start;
4519         int i, ret = 0;
4520
4521         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4522                 new_skb = skb_copy(skb, GFP_ATOMIC);
4523         else {
4524                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4525
4526                 new_skb = skb_copy_expand(skb,
4527                                           skb_headroom(skb) + more_headroom,
4528                                           skb_tailroom(skb), GFP_ATOMIC);
4529         }
4530
4531         if (!new_skb) {
4532                 ret = -1;
4533         } else {
4534                 /* New SKB is guaranteed to be linear. */
4535                 entry = *start;
4536                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4537                                           PCI_DMA_TODEVICE);
4538                 /* Make sure new skb does not cross any 4G boundaries.
4539                  * Drop the packet if it does.
4540                  */
4541                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4542                         ret = -1;
4543                         dev_kfree_skb(new_skb);
4544                         new_skb = NULL;
4545                 } else {
4546                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
4547                                     base_flags, 1 | (mss << 1));
4548                         *start = NEXT_TX(entry);
4549                 }
4550         }
4551
4552         /* Now clean up the sw ring entries. */
4553         i = 0;
4554         while (entry != last_plus_one) {
4555                 int len;
4556
4557                 if (i == 0)
4558                         len = skb_headlen(skb);
4559                 else
4560                         len = skb_shinfo(skb)->frags[i-1].size;
4561                 pci_unmap_single(tp->pdev,
4562                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4563                                  len, PCI_DMA_TODEVICE);
4564                 if (i == 0) {
4565                         tp->tx_buffers[entry].skb = new_skb;
4566                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4567                 } else {
4568                         tp->tx_buffers[entry].skb = NULL;
4569                 }
4570                 entry = NEXT_TX(entry);
4571                 i++;
4572         }
4573
4574         dev_kfree_skb(skb);
4575
4576         return ret;
4577 }
4578
4579 static void tg3_set_txd(struct tg3 *tp, int entry,
4580                         dma_addr_t mapping, int len, u32 flags,
4581                         u32 mss_and_is_end)
4582 {
4583         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4584         int is_end = (mss_and_is_end & 0x1);
4585         u32 mss = (mss_and_is_end >> 1);
4586         u32 vlan_tag = 0;
4587
4588         if (is_end)
4589                 flags |= TXD_FLAG_END;
4590         if (flags & TXD_FLAG_VLAN) {
4591                 vlan_tag = flags >> 16;
4592                 flags &= 0xffff;
4593         }
4594         vlan_tag |= (mss << TXD_MSS_SHIFT);
4595
4596         txd->addr_hi = ((u64) mapping >> 32);
4597         txd->addr_lo = ((u64) mapping & 0xffffffff);
4598         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4599         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4600 }
4601
4602 /* hard_start_xmit for devices that don't have any bugs and
4603  * support TG3_FLG2_HW_TSO_2 only.
4604  */
4605 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4606 {
4607         struct tg3 *tp = netdev_priv(dev);
4608         dma_addr_t mapping;
4609         u32 len, entry, base_flags, mss;
4610
4611         len = skb_headlen(skb);
4612
4613         /* We are running in BH disabled context with netif_tx_lock
4614          * and TX reclaim runs via tp->napi.poll inside of a software
4615          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4616          * no IRQ context deadlocks to worry about either.  Rejoice!
4617          */
4618         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4619                 if (!netif_queue_stopped(dev)) {
4620                         netif_stop_queue(dev);
4621
4622                         /* This is a hard error, log it. */
4623                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4624                                "queue awake!\n", dev->name);
4625                 }
4626                 return NETDEV_TX_BUSY;
4627         }
4628
4629         entry = tp->tx_prod;
4630         base_flags = 0;
4631         mss = 0;
4632         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4633                 int tcp_opt_len, ip_tcp_len;
4634
4635                 if (skb_header_cloned(skb) &&
4636                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4637                         dev_kfree_skb(skb);
4638                         goto out_unlock;
4639                 }
4640
4641                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4642                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4643                 else {
4644                         struct iphdr *iph = ip_hdr(skb);
4645
4646                         tcp_opt_len = tcp_optlen(skb);
4647                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4648
4649                         iph->check = 0;
4650                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4651                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
4652                 }
4653
4654                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4655                                TXD_FLAG_CPU_POST_DMA);
4656
4657                 tcp_hdr(skb)->check = 0;
4658
4659         }
4660         else if (skb->ip_summed == CHECKSUM_PARTIAL)
4661                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4662 #if TG3_VLAN_TAG_USED
4663         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4664                 base_flags |= (TXD_FLAG_VLAN |
4665                                (vlan_tx_tag_get(skb) << 16));
4666 #endif
4667
4668         /* Queue skb data, a.k.a. the main skb fragment. */
4669         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4670
4671         tp->tx_buffers[entry].skb = skb;
4672         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4673
4674         tg3_set_txd(tp, entry, mapping, len, base_flags,
4675                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4676
4677         entry = NEXT_TX(entry);
4678
4679         /* Now loop through additional data fragments, and queue them. */
4680         if (skb_shinfo(skb)->nr_frags > 0) {
4681                 unsigned int i, last;
4682
4683                 last = skb_shinfo(skb)->nr_frags - 1;
4684                 for (i = 0; i <= last; i++) {
4685                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4686
4687                         len = frag->size;
4688                         mapping = pci_map_page(tp->pdev,
4689                                                frag->page,
4690                                                frag->page_offset,
4691                                                len, PCI_DMA_TODEVICE);
4692
4693                         tp->tx_buffers[entry].skb = NULL;
4694                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4695
4696                         tg3_set_txd(tp, entry, mapping, len,
4697                                     base_flags, (i == last) | (mss << 1));
4698
4699                         entry = NEXT_TX(entry);
4700                 }
4701         }
4702
4703         /* Packets are ready, update Tx producer idx local and on card. */
4704         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4705
4706         tp->tx_prod = entry;
4707         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4708                 netif_stop_queue(dev);
4709                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4710                         netif_wake_queue(tp->dev);
4711         }
4712
4713 out_unlock:
4714         mmiowb();
4715
4716         dev->trans_start = jiffies;
4717
4718         return NETDEV_TX_OK;
4719 }
4720
4721 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4722
4723 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4724  * TSO header is greater than 80 bytes.
4725  */
4726 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4727 {
4728         struct sk_buff *segs, *nskb;
4729
4730         /* Estimate the number of fragments in the worst case */
4731         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4732                 netif_stop_queue(tp->dev);
4733                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4734                         return NETDEV_TX_BUSY;
4735
4736                 netif_wake_queue(tp->dev);
4737         }
4738
4739         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4740         if (IS_ERR(segs))
4741                 goto tg3_tso_bug_end;
4742
4743         do {
4744                 nskb = segs;
4745                 segs = segs->next;
4746                 nskb->next = NULL;
4747                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4748         } while (segs);
4749
4750 tg3_tso_bug_end:
4751         dev_kfree_skb(skb);
4752
4753         return NETDEV_TX_OK;
4754 }
4755
4756 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4757  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4758  */
4759 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4760 {
4761         struct tg3 *tp = netdev_priv(dev);
4762         dma_addr_t mapping;
4763         u32 len, entry, base_flags, mss;
4764         int would_hit_hwbug;
4765
4766         len = skb_headlen(skb);
4767
4768         /* We are running in BH disabled context with netif_tx_lock
4769          * and TX reclaim runs via tp->napi.poll inside of a software
4770          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4771          * no IRQ context deadlocks to worry about either.  Rejoice!
4772          */
4773         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4774                 if (!netif_queue_stopped(dev)) {
4775                         netif_stop_queue(dev);
4776
4777                         /* This is a hard error, log it. */
4778                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4779                                "queue awake!\n", dev->name);
4780                 }
4781                 return NETDEV_TX_BUSY;
4782         }
4783
4784         entry = tp->tx_prod;
4785         base_flags = 0;
4786         if (skb->ip_summed == CHECKSUM_PARTIAL)
4787                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4788         mss = 0;
4789         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4790                 struct iphdr *iph;
4791                 int tcp_opt_len, ip_tcp_len, hdr_len;
4792
4793                 if (skb_header_cloned(skb) &&
4794                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4795                         dev_kfree_skb(skb);
4796                         goto out_unlock;
4797                 }
4798
4799                 tcp_opt_len = tcp_optlen(skb);
4800                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4801
4802                 hdr_len = ip_tcp_len + tcp_opt_len;
4803                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4804                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4805                         return (tg3_tso_bug(tp, skb));
4806
4807                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4808                                TXD_FLAG_CPU_POST_DMA);
4809
4810                 iph = ip_hdr(skb);
4811                 iph->check = 0;
4812                 iph->tot_len = htons(mss + hdr_len);
4813                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4814                         tcp_hdr(skb)->check = 0;
4815                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4816                 } else
4817                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4818                                                                  iph->daddr, 0,
4819                                                                  IPPROTO_TCP,
4820                                                                  0);
4821
4822                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4823                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4824                         if (tcp_opt_len || iph->ihl > 5) {
4825                                 int tsflags;
4826
4827                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4828                                 mss |= (tsflags << 11);
4829                         }
4830                 } else {
4831                         if (tcp_opt_len || iph->ihl > 5) {
4832                                 int tsflags;
4833
4834                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4835                                 base_flags |= tsflags << 12;
4836                         }
4837                 }
4838         }
4839 #if TG3_VLAN_TAG_USED
4840         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4841                 base_flags |= (TXD_FLAG_VLAN |
4842                                (vlan_tx_tag_get(skb) << 16));
4843 #endif
4844
4845         /* Queue skb data, a.k.a. the main skb fragment. */
4846         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4847
4848         tp->tx_buffers[entry].skb = skb;
4849         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4850
4851         would_hit_hwbug = 0;
4852
4853         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4854                 would_hit_hwbug = 1;
4855         else if (tg3_4g_overflow_test(mapping, len))
4856                 would_hit_hwbug = 1;
4857
4858         tg3_set_txd(tp, entry, mapping, len, base_flags,
4859                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4860
4861         entry = NEXT_TX(entry);
4862
4863         /* Now loop through additional data fragments, and queue them. */
4864         if (skb_shinfo(skb)->nr_frags > 0) {
4865                 unsigned int i, last;
4866
4867                 last = skb_shinfo(skb)->nr_frags - 1;
4868                 for (i = 0; i <= last; i++) {
4869                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4870
4871                         len = frag->size;
4872                         mapping = pci_map_page(tp->pdev,
4873                                                frag->page,
4874                                                frag->page_offset,
4875                                                len, PCI_DMA_TODEVICE);
4876
4877                         tp->tx_buffers[entry].skb = NULL;
4878                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4879
4880                         if (tg3_4g_overflow_test(mapping, len))
4881                                 would_hit_hwbug = 1;
4882
4883                         if (tg3_40bit_overflow_test(tp, mapping, len))
4884                                 would_hit_hwbug = 1;
4885
4886                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4887                                 tg3_set_txd(tp, entry, mapping, len,
4888                                             base_flags, (i == last)|(mss << 1));
4889                         else
4890                                 tg3_set_txd(tp, entry, mapping, len,
4891                                             base_flags, (i == last));
4892
4893                         entry = NEXT_TX(entry);
4894                 }
4895         }
4896
4897         if (would_hit_hwbug) {
4898                 u32 last_plus_one = entry;
4899                 u32 start;
4900
4901                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4902                 start &= (TG3_TX_RING_SIZE - 1);
4903
4904                 /* If the workaround fails due to memory/mapping
4905                  * failure, silently drop this packet.
4906                  */
4907                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4908                                                 &start, base_flags, mss))
4909                         goto out_unlock;
4910
4911                 entry = start;
4912         }
4913
4914         /* Packets are ready, update Tx producer idx local and on card. */
4915         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4916
4917         tp->tx_prod = entry;
4918         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4919                 netif_stop_queue(dev);
4920                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4921                         netif_wake_queue(tp->dev);
4922         }
4923
4924 out_unlock:
4925         mmiowb();
4926
4927         dev->trans_start = jiffies;
4928
4929         return NETDEV_TX_OK;
4930 }
4931
4932 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4933                                int new_mtu)
4934 {
4935         dev->mtu = new_mtu;
4936
4937         if (new_mtu > ETH_DATA_LEN) {
4938                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4939                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4940                         ethtool_op_set_tso(dev, 0);
4941                 }
4942                 else
4943                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4944         } else {
4945                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4946                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4947                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4948         }
4949 }
4950
4951 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4952 {
4953         struct tg3 *tp = netdev_priv(dev);
4954         int err;
4955
4956         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4957                 return -EINVAL;
4958
4959         if (!netif_running(dev)) {
4960                 /* We'll just catch it later when the
4961                  * device is up'd.
4962                  */
4963                 tg3_set_mtu(dev, tp, new_mtu);
4964                 return 0;
4965         }
4966
4967         tg3_phy_stop(tp);
4968
4969         tg3_netif_stop(tp);
4970
4971         tg3_full_lock(tp, 1);
4972
4973         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4974
4975         tg3_set_mtu(dev, tp, new_mtu);
4976
4977         err = tg3_restart_hw(tp, 0);
4978
4979         if (!err)
4980                 tg3_netif_start(tp);
4981
4982         tg3_full_unlock(tp);
4983
4984         if (!err)
4985                 tg3_phy_start(tp);
4986
4987         return err;
4988 }
4989
4990 /* Free up pending packets in all rx/tx rings.
4991  *
4992  * The chip has been shut down and the driver detached from
4993  * the networking, so no interrupts or new tx packets will
4994  * end up in the driver.  tp->{tx,}lock is not held and we are not
4995  * in an interrupt context and thus may sleep.
4996  */
4997 static void tg3_free_rings(struct tg3 *tp)
4998 {
4999         struct ring_info *rxp;
5000         int i;
5001
5002         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5003                 rxp = &tp->rx_std_buffers[i];
5004
5005                 if (rxp->skb == NULL)
5006                         continue;
5007                 pci_unmap_single(tp->pdev,
5008                                  pci_unmap_addr(rxp, mapping),
5009                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5010                                  PCI_DMA_FROMDEVICE);
5011                 dev_kfree_skb_any(rxp->skb);
5012                 rxp->skb = NULL;
5013         }
5014
5015         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5016                 rxp = &tp->rx_jumbo_buffers[i];
5017
5018                 if (rxp->skb == NULL)
5019                         continue;
5020                 pci_unmap_single(tp->pdev,
5021                                  pci_unmap_addr(rxp, mapping),
5022                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5023                                  PCI_DMA_FROMDEVICE);
5024                 dev_kfree_skb_any(rxp->skb);
5025                 rxp->skb = NULL;
5026         }
5027
5028         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5029                 struct tx_ring_info *txp;
5030                 struct sk_buff *skb;
5031                 int j;
5032
5033                 txp = &tp->tx_buffers[i];
5034                 skb = txp->skb;
5035
5036                 if (skb == NULL) {
5037                         i++;
5038                         continue;
5039                 }
5040
5041                 pci_unmap_single(tp->pdev,
5042                                  pci_unmap_addr(txp, mapping),
5043                                  skb_headlen(skb),
5044                                  PCI_DMA_TODEVICE);
5045                 txp->skb = NULL;
5046
5047                 i++;
5048
5049                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
5050                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
5051                         pci_unmap_page(tp->pdev,
5052                                        pci_unmap_addr(txp, mapping),
5053                                        skb_shinfo(skb)->frags[j].size,
5054                                        PCI_DMA_TODEVICE);
5055                         i++;
5056                 }
5057
5058                 dev_kfree_skb_any(skb);
5059         }
5060 }
5061
5062 /* Initialize tx/rx rings for packet processing.
5063  *
5064  * The chip has been shut down and the driver detached from
5065  * the networking, so no interrupts or new tx packets will
5066  * end up in the driver.  tp->{tx,}lock are held and thus
5067  * we may not sleep.
5068  */
5069 static int tg3_init_rings(struct tg3 *tp)
5070 {
5071         u32 i;
5072
5073         /* Free up all the SKBs. */
5074         tg3_free_rings(tp);
5075
5076         /* Zero out all descriptors. */
5077         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5078         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5079         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5080         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5081
5082         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5083         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5084             (tp->dev->mtu > ETH_DATA_LEN))
5085                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5086
5087         /* Initialize invariants of the rings, we only set this
5088          * stuff once.  This works because the card does not
5089          * write into the rx buffer posting rings.
5090          */
5091         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5092                 struct tg3_rx_buffer_desc *rxd;
5093
5094                 rxd = &tp->rx_std[i];
5095                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5096                         << RXD_LEN_SHIFT;
5097                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5098                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5099                                (i << RXD_OPAQUE_INDEX_SHIFT));
5100         }
5101
5102         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5103                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5104                         struct tg3_rx_buffer_desc *rxd;
5105
5106                         rxd = &tp->rx_jumbo[i];
5107                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5108                                 << RXD_LEN_SHIFT;
5109                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5110                                 RXD_FLAG_JUMBO;
5111                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5112                                (i << RXD_OPAQUE_INDEX_SHIFT));
5113                 }
5114         }
5115
5116         /* Now allocate fresh SKBs for each rx ring. */
5117         for (i = 0; i < tp->rx_pending; i++) {
5118                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5119                         printk(KERN_WARNING PFX
5120                                "%s: Using a smaller RX standard ring, "
5121                                "only %d out of %d buffers were allocated "
5122                                "successfully.\n",
5123                                tp->dev->name, i, tp->rx_pending);
5124                         if (i == 0)
5125                                 return -ENOMEM;
5126                         tp->rx_pending = i;
5127                         break;
5128                 }
5129         }
5130
5131         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5132                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5133                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5134                                              -1, i) < 0) {
5135                                 printk(KERN_WARNING PFX
5136                                        "%s: Using a smaller RX jumbo ring, "
5137                                        "only %d out of %d buffers were "
5138                                        "allocated successfully.\n",
5139                                        tp->dev->name, i, tp->rx_jumbo_pending);
5140                                 if (i == 0) {
5141                                         tg3_free_rings(tp);
5142                                         return -ENOMEM;
5143                                 }
5144                                 tp->rx_jumbo_pending = i;
5145                                 break;
5146                         }
5147                 }
5148         }
5149         return 0;
5150 }
5151
5152 /*
5153  * Must not be invoked with interrupt sources disabled and
5154  * the hardware shutdown down.
5155  */
5156 static void tg3_free_consistent(struct tg3 *tp)
5157 {
5158         kfree(tp->rx_std_buffers);
5159         tp->rx_std_buffers = NULL;
5160         if (tp->rx_std) {
5161                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5162                                     tp->rx_std, tp->rx_std_mapping);
5163                 tp->rx_std = NULL;
5164         }
5165         if (tp->rx_jumbo) {
5166                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5167                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5168                 tp->rx_jumbo = NULL;
5169         }
5170         if (tp->rx_rcb) {
5171                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5172                                     tp->rx_rcb, tp->rx_rcb_mapping);
5173                 tp->rx_rcb = NULL;
5174         }
5175         if (tp->tx_ring) {
5176                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5177                         tp->tx_ring, tp->tx_desc_mapping);
5178                 tp->tx_ring = NULL;
5179         }
5180         if (tp->hw_status) {
5181                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5182                                     tp->hw_status, tp->status_mapping);
5183                 tp->hw_status = NULL;
5184         }
5185         if (tp->hw_stats) {
5186                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5187                                     tp->hw_stats, tp->stats_mapping);
5188                 tp->hw_stats = NULL;
5189         }
5190 }
5191
5192 /*
5193  * Must not be invoked with interrupt sources disabled and
5194  * the hardware shutdown down.  Can sleep.
5195  */
5196 static int tg3_alloc_consistent(struct tg3 *tp)
5197 {
5198         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5199                                       (TG3_RX_RING_SIZE +
5200                                        TG3_RX_JUMBO_RING_SIZE)) +
5201                                      (sizeof(struct tx_ring_info) *
5202                                       TG3_TX_RING_SIZE),
5203                                      GFP_KERNEL);
5204         if (!tp->rx_std_buffers)
5205                 return -ENOMEM;
5206
5207         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5208         tp->tx_buffers = (struct tx_ring_info *)
5209                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5210
5211         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5212                                           &tp->rx_std_mapping);
5213         if (!tp->rx_std)
5214                 goto err_out;
5215
5216         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5217                                             &tp->rx_jumbo_mapping);
5218
5219         if (!tp->rx_jumbo)
5220                 goto err_out;
5221
5222         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5223                                           &tp->rx_rcb_mapping);
5224         if (!tp->rx_rcb)
5225                 goto err_out;
5226
5227         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5228                                            &tp->tx_desc_mapping);
5229         if (!tp->tx_ring)
5230                 goto err_out;
5231
5232         tp->hw_status = pci_alloc_consistent(tp->pdev,
5233                                              TG3_HW_STATUS_SIZE,
5234                                              &tp->status_mapping);
5235         if (!tp->hw_status)
5236                 goto err_out;
5237
5238         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5239                                             sizeof(struct tg3_hw_stats),
5240                                             &tp->stats_mapping);
5241         if (!tp->hw_stats)
5242                 goto err_out;
5243
5244         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5245         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5246
5247         return 0;
5248
5249 err_out:
5250         tg3_free_consistent(tp);
5251         return -ENOMEM;
5252 }
5253
5254 #define MAX_WAIT_CNT 1000
5255
5256 /* To stop a block, clear the enable bit and poll till it
5257  * clears.  tp->lock is held.
5258  */
5259 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5260 {
5261         unsigned int i;
5262         u32 val;
5263
5264         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5265                 switch (ofs) {
5266                 case RCVLSC_MODE:
5267                 case DMAC_MODE:
5268                 case MBFREE_MODE:
5269                 case BUFMGR_MODE:
5270                 case MEMARB_MODE:
5271                         /* We can't enable/disable these bits of the
5272                          * 5705/5750, just say success.
5273                          */
5274                         return 0;
5275
5276                 default:
5277                         break;
5278                 };
5279         }
5280
5281         val = tr32(ofs);
5282         val &= ~enable_bit;
5283         tw32_f(ofs, val);
5284
5285         for (i = 0; i < MAX_WAIT_CNT; i++) {
5286                 udelay(100);
5287                 val = tr32(ofs);
5288                 if ((val & enable_bit) == 0)
5289                         break;
5290         }
5291
5292         if (i == MAX_WAIT_CNT && !silent) {
5293                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5294                        "ofs=%lx enable_bit=%x\n",
5295                        ofs, enable_bit);
5296                 return -ENODEV;
5297         }
5298
5299         return 0;
5300 }
5301
5302 /* tp->lock is held. */
5303 static int tg3_abort_hw(struct tg3 *tp, int silent)
5304 {
5305         int i, err;
5306
5307         tg3_disable_ints(tp);
5308
5309         tp->rx_mode &= ~RX_MODE_ENABLE;
5310         tw32_f(MAC_RX_MODE, tp->rx_mode);
5311         udelay(10);
5312
5313         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5314         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5315         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5316         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5317         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5318         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5319
5320         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5321         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5322         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5323         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5324         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5325         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5326         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5327
5328         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5329         tw32_f(MAC_MODE, tp->mac_mode);
5330         udelay(40);
5331
5332         tp->tx_mode &= ~TX_MODE_ENABLE;
5333         tw32_f(MAC_TX_MODE, tp->tx_mode);
5334
5335         for (i = 0; i < MAX_WAIT_CNT; i++) {
5336                 udelay(100);
5337                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5338                         break;
5339         }
5340         if (i >= MAX_WAIT_CNT) {
5341                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5342                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5343                        tp->dev->name, tr32(MAC_TX_MODE));
5344                 err |= -ENODEV;
5345         }
5346
5347         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5348         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5349         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5350
5351         tw32(FTQ_RESET, 0xffffffff);
5352         tw32(FTQ_RESET, 0x00000000);
5353
5354         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5355         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5356
5357         if (tp->hw_status)
5358                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5359         if (tp->hw_stats)
5360                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5361
5362         return err;
5363 }
5364
5365 /* tp->lock is held. */
5366 static int tg3_nvram_lock(struct tg3 *tp)
5367 {
5368         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5369                 int i;
5370
5371                 if (tp->nvram_lock_cnt == 0) {
5372                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5373                         for (i = 0; i < 8000; i++) {
5374                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5375                                         break;
5376                                 udelay(20);
5377                         }
5378                         if (i == 8000) {
5379                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5380                                 return -ENODEV;
5381                         }
5382                 }
5383                 tp->nvram_lock_cnt++;
5384         }
5385         return 0;
5386 }
5387
5388 /* tp->lock is held. */
5389 static void tg3_nvram_unlock(struct tg3 *tp)
5390 {
5391         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5392                 if (tp->nvram_lock_cnt > 0)
5393                         tp->nvram_lock_cnt--;
5394                 if (tp->nvram_lock_cnt == 0)
5395                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5396         }
5397 }
5398
5399 /* tp->lock is held. */
5400 static void tg3_enable_nvram_access(struct tg3 *tp)
5401 {
5402         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5403             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5404                 u32 nvaccess = tr32(NVRAM_ACCESS);
5405
5406                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5407         }
5408 }
5409
5410 /* tp->lock is held. */
5411 static void tg3_disable_nvram_access(struct tg3 *tp)
5412 {
5413         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5414             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5415                 u32 nvaccess = tr32(NVRAM_ACCESS);
5416
5417                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5418         }
5419 }
5420
5421 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5422 {
5423         int i;
5424         u32 apedata;
5425
5426         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5427         if (apedata != APE_SEG_SIG_MAGIC)
5428                 return;
5429
5430         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5431         if (apedata != APE_FW_STATUS_READY)
5432                 return;
5433
5434         /* Wait for up to 1 millisecond for APE to service previous event. */
5435         for (i = 0; i < 10; i++) {
5436                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5437                         return;
5438
5439                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5440
5441                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5442                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5443                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5444
5445                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5446
5447                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5448                         break;
5449
5450                 udelay(100);
5451         }
5452
5453         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5454                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5455 }
5456
5457 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5458 {
5459         u32 event;
5460         u32 apedata;
5461
5462         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5463                 return;
5464
5465         switch (kind) {
5466                 case RESET_KIND_INIT:
5467                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5468                                         APE_HOST_SEG_SIG_MAGIC);
5469                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5470                                         APE_HOST_SEG_LEN_MAGIC);
5471                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5472                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5473                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5474                                         APE_HOST_DRIVER_ID_MAGIC);
5475                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5476                                         APE_HOST_BEHAV_NO_PHYLOCK);
5477
5478                         event = APE_EVENT_STATUS_STATE_START;
5479                         break;
5480                 case RESET_KIND_SHUTDOWN:
5481                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5482                         break;
5483                 case RESET_KIND_SUSPEND:
5484                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5485                         break;
5486                 default:
5487                         return;
5488         }
5489
5490         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5491
5492         tg3_ape_send_event(tp, event);
5493 }
5494
5495 /* tp->lock is held. */
5496 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5497 {
5498         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5499                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5500
5501         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5502                 switch (kind) {
5503                 case RESET_KIND_INIT:
5504                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5505                                       DRV_STATE_START);
5506                         break;
5507
5508                 case RESET_KIND_SHUTDOWN:
5509                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5510                                       DRV_STATE_UNLOAD);
5511                         break;
5512
5513                 case RESET_KIND_SUSPEND:
5514                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5515                                       DRV_STATE_SUSPEND);
5516                         break;
5517
5518                 default:
5519                         break;
5520                 };
5521         }
5522
5523         if (kind == RESET_KIND_INIT ||
5524             kind == RESET_KIND_SUSPEND)
5525                 tg3_ape_driver_state_change(tp, kind);
5526 }
5527
5528 /* tp->lock is held. */
5529 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5530 {
5531         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5532                 switch (kind) {
5533                 case RESET_KIND_INIT:
5534                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5535                                       DRV_STATE_START_DONE);
5536                         break;
5537
5538                 case RESET_KIND_SHUTDOWN:
5539                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5540                                       DRV_STATE_UNLOAD_DONE);
5541                         break;
5542
5543                 default:
5544                         break;
5545                 };
5546         }
5547
5548         if (kind == RESET_KIND_SHUTDOWN)
5549                 tg3_ape_driver_state_change(tp, kind);
5550 }
5551
5552 /* tp->lock is held. */
5553 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5554 {
5555         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5556                 switch (kind) {
5557                 case RESET_KIND_INIT:
5558                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5559                                       DRV_STATE_START);
5560                         break;
5561
5562                 case RESET_KIND_SHUTDOWN:
5563                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5564                                       DRV_STATE_UNLOAD);
5565                         break;
5566
5567                 case RESET_KIND_SUSPEND:
5568                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5569                                       DRV_STATE_SUSPEND);
5570                         break;
5571
5572                 default:
5573                         break;
5574                 };
5575         }
5576 }
5577
5578 static int tg3_poll_fw(struct tg3 *tp)
5579 {
5580         int i;
5581         u32 val;
5582
5583         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5584                 /* Wait up to 20ms for init done. */
5585                 for (i = 0; i < 200; i++) {
5586                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5587                                 return 0;
5588                         udelay(100);
5589                 }
5590                 return -ENODEV;
5591         }
5592
5593         /* Wait for firmware initialization to complete. */
5594         for (i = 0; i < 100000; i++) {
5595                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5596                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5597                         break;
5598                 udelay(10);
5599         }
5600
5601         /* Chip might not be fitted with firmware.  Some Sun onboard
5602          * parts are configured like that.  So don't signal the timeout
5603          * of the above loop as an error, but do report the lack of
5604          * running firmware once.
5605          */
5606         if (i >= 100000 &&
5607             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5608                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5609
5610                 printk(KERN_INFO PFX "%s: No firmware running.\n",
5611                        tp->dev->name);
5612         }
5613
5614         return 0;
5615 }
5616
5617 /* Save PCI command register before chip reset */
5618 static void tg3_save_pci_state(struct tg3 *tp)
5619 {
5620         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5621 }
5622
5623 /* Restore PCI state after chip reset */
5624 static void tg3_restore_pci_state(struct tg3 *tp)
5625 {
5626         u32 val;
5627
5628         /* Re-enable indirect register accesses. */
5629         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5630                                tp->misc_host_ctrl);
5631
5632         /* Set MAX PCI retry to zero. */
5633         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5634         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5635             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5636                 val |= PCISTATE_RETRY_SAME_DMA;
5637         /* Allow reads and writes to the APE register and memory space. */
5638         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5639                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5640                        PCISTATE_ALLOW_APE_SHMEM_WR;
5641         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5642
5643         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5644
5645         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5646                 pcie_set_readrq(tp->pdev, 4096);
5647         else {
5648                 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5649                                       tp->pci_cacheline_sz);
5650                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5651                                       tp->pci_lat_timer);
5652         }
5653
5654         /* Make sure PCI-X relaxed ordering bit is clear. */
5655         if (tp->pcix_cap) {
5656                 u16 pcix_cmd;
5657
5658                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5659                                      &pcix_cmd);
5660                 pcix_cmd &= ~PCI_X_CMD_ERO;
5661                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5662                                       pcix_cmd);
5663         }
5664
5665         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5666
5667                 /* Chip reset on 5780 will reset MSI enable bit,
5668                  * so need to restore it.
5669                  */
5670                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5671                         u16 ctrl;
5672
5673                         pci_read_config_word(tp->pdev,
5674                                              tp->msi_cap + PCI_MSI_FLAGS,
5675                                              &ctrl);
5676                         pci_write_config_word(tp->pdev,
5677                                               tp->msi_cap + PCI_MSI_FLAGS,
5678                                               ctrl | PCI_MSI_FLAGS_ENABLE);
5679                         val = tr32(MSGINT_MODE);
5680                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5681                 }
5682         }
5683 }
5684
5685 static void tg3_stop_fw(struct tg3 *);
5686
5687 /* tp->lock is held. */
5688 static int tg3_chip_reset(struct tg3 *tp)
5689 {
5690         u32 val;
5691         void (*write_op)(struct tg3 *, u32, u32);
5692         int err;
5693
5694         tg3_nvram_lock(tp);
5695
5696         tg3_mdio_stop(tp);
5697
5698         /* No matching tg3_nvram_unlock() after this because
5699          * chip reset below will undo the nvram lock.
5700          */
5701         tp->nvram_lock_cnt = 0;
5702
5703         /* GRC_MISC_CFG core clock reset will clear the memory
5704          * enable bit in PCI register 4 and the MSI enable bit
5705          * on some chips, so we save relevant registers here.
5706          */
5707         tg3_save_pci_state(tp);
5708
5709         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5710             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5711             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5712             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5713             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
5714                 tw32(GRC_FASTBOOT_PC, 0);
5715
5716         /*
5717          * We must avoid the readl() that normally takes place.
5718          * It locks machines, causes machine checks, and other
5719          * fun things.  So, temporarily disable the 5701
5720          * hardware workaround, while we do the reset.
5721          */
5722         write_op = tp->write32;
5723         if (write_op == tg3_write_flush_reg32)
5724                 tp->write32 = tg3_write32;
5725
5726         /* Prevent the irq handler from reading or writing PCI registers
5727          * during chip reset when the memory enable bit in the PCI command
5728          * register may be cleared.  The chip does not generate interrupt
5729          * at this time, but the irq handler may still be called due to irq
5730          * sharing or irqpoll.
5731          */
5732         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5733         if (tp->hw_status) {
5734                 tp->hw_status->status = 0;
5735                 tp->hw_status->status_tag = 0;
5736         }
5737         tp->last_tag = 0;
5738         smp_mb();
5739         synchronize_irq(tp->pdev->irq);
5740
5741         /* do the reset */
5742         val = GRC_MISC_CFG_CORECLK_RESET;
5743
5744         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5745                 if (tr32(0x7e2c) == 0x60) {
5746                         tw32(0x7e2c, 0x20);
5747                 }
5748                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5749                         tw32(GRC_MISC_CFG, (1 << 29));
5750                         val |= (1 << 29);
5751                 }
5752         }
5753
5754         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5755                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5756                 tw32(GRC_VCPU_EXT_CTRL,
5757                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5758         }
5759
5760         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5761                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5762         tw32(GRC_MISC_CFG, val);
5763
5764         /* restore 5701 hardware bug workaround write method */
5765         tp->write32 = write_op;
5766
5767         /* Unfortunately, we have to delay before the PCI read back.
5768          * Some 575X chips even will not respond to a PCI cfg access
5769          * when the reset command is given to the chip.
5770          *
5771          * How do these hardware designers expect things to work
5772          * properly if the PCI write is posted for a long period
5773          * of time?  It is always necessary to have some method by
5774          * which a register read back can occur to push the write
5775          * out which does the reset.
5776          *
5777          * For most tg3 variants the trick below was working.
5778          * Ho hum...
5779          */
5780         udelay(120);
5781
5782         /* Flush PCI posted writes.  The normal MMIO registers
5783          * are inaccessible at this time so this is the only
5784          * way to make this reliably (actually, this is no longer
5785          * the case, see above).  I tried to use indirect
5786          * register read/write but this upset some 5701 variants.
5787          */
5788         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5789
5790         udelay(120);
5791
5792         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5793                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5794                         int i;
5795                         u32 cfg_val;
5796
5797                         /* Wait for link training to complete.  */
5798                         for (i = 0; i < 5000; i++)
5799                                 udelay(100);
5800
5801                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5802                         pci_write_config_dword(tp->pdev, 0xc4,
5803                                                cfg_val | (1 << 15));
5804                 }
5805                 /* Set PCIE max payload size and clear error status.  */
5806                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5807         }
5808
5809         tg3_restore_pci_state(tp);
5810
5811         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5812
5813         val = 0;
5814         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5815                 val = tr32(MEMARB_MODE);
5816         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5817
5818         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5819                 tg3_stop_fw(tp);
5820                 tw32(0x5000, 0x400);
5821         }
5822
5823         tw32(GRC_MODE, tp->grc_mode);
5824
5825         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5826                 val = tr32(0xc4);
5827
5828                 tw32(0xc4, val | (1 << 15));
5829         }
5830
5831         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5832             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5833                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5834                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5835                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5836                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5837         }
5838
5839         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5840                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5841                 tw32_f(MAC_MODE, tp->mac_mode);
5842         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5843                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5844                 tw32_f(MAC_MODE, tp->mac_mode);
5845         } else
5846                 tw32_f(MAC_MODE, 0);
5847         udelay(40);
5848
5849         tg3_mdio_start(tp);
5850
5851         err = tg3_poll_fw(tp);
5852         if (err)
5853                 return err;
5854
5855         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5856             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5857                 val = tr32(0x7c00);
5858
5859                 tw32(0x7c00, val | (1 << 25));
5860         }
5861
5862         /* Reprobe ASF enable state.  */
5863         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5864         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5865         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5866         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5867                 u32 nic_cfg;
5868
5869                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5870                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5871                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5872                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5873                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5874                 }
5875         }
5876
5877         return 0;
5878 }
5879
5880 /* tp->lock is held. */
5881 static void tg3_stop_fw(struct tg3 *tp)
5882 {
5883         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5884            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5885                 u32 val;
5886
5887                 /* Wait for RX cpu to ACK the previous event. */
5888                 tg3_wait_for_event_ack(tp);
5889
5890                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5891                 val = tr32(GRC_RX_CPU_EVENT);
5892                 val |= GRC_RX_CPU_DRIVER_EVENT;
5893                 tw32(GRC_RX_CPU_EVENT, val);
5894
5895                 /* Wait for RX cpu to ACK this event. */
5896                 tg3_wait_for_event_ack(tp);
5897         }
5898 }
5899
5900 /* tp->lock is held. */
5901 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5902 {
5903         int err;
5904
5905         tg3_stop_fw(tp);
5906
5907         tg3_write_sig_pre_reset(tp, kind);
5908
5909         tg3_abort_hw(tp, silent);
5910         err = tg3_chip_reset(tp);
5911
5912         tg3_write_sig_legacy(tp, kind);
5913         tg3_write_sig_post_reset(tp, kind);
5914
5915         if (err)
5916                 return err;
5917
5918         return 0;
5919 }
5920
5921 #define TG3_FW_RELEASE_MAJOR    0x0
5922 #define TG3_FW_RELASE_MINOR     0x0
5923 #define TG3_FW_RELEASE_FIX      0x0
5924 #define TG3_FW_START_ADDR       0x08000000
5925 #define TG3_FW_TEXT_ADDR        0x08000000
5926 #define TG3_FW_TEXT_LEN         0x9c0
5927 #define TG3_FW_RODATA_ADDR      0x080009c0
5928 #define TG3_FW_RODATA_LEN       0x60
5929 #define TG3_FW_DATA_ADDR        0x08000a40
5930 #define TG3_FW_DATA_LEN         0x20
5931 #define TG3_FW_SBSS_ADDR        0x08000a60
5932 #define TG3_FW_SBSS_LEN         0xc
5933 #define TG3_FW_BSS_ADDR         0x08000a70
5934 #define TG3_FW_BSS_LEN          0x10
5935
5936 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5937         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5938         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5939         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5940         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5941         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5942         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5943         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5944         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5945         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5946         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5947         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5948         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5949         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5950         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5951         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5952         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5953         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5954         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5955         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5956         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5957         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5958         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5959         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5960         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5961         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5962         0, 0, 0, 0, 0, 0,
5963         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5964         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5965         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5966         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5967         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5968         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5969         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5970         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5971         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5972         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5973         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5974         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5975         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5976         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5977         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5978         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5979         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5980         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5981         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5982         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5983         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5984         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5985         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5986         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5987         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5988         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5989         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5990         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5991         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5992         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5993         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5994         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5995         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5996         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5997         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5998         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5999         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
6000         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
6001         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
6002         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
6003         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
6004         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
6005         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
6006         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
6007         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
6008         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
6009         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
6010         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
6011         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
6012         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
6013         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
6014         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
6015         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
6016         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
6017         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
6018         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
6019         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
6020         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
6021         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
6022         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
6023         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
6024         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
6025         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
6026         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
6027         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
6028 };
6029
6030 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
6031         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
6032         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
6033         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6034         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
6035         0x00000000
6036 };
6037
6038 #if 0 /* All zeros, don't eat up space with it. */
6039 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
6040         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6041         0x00000000, 0x00000000, 0x00000000, 0x00000000
6042 };
6043 #endif
6044
6045 #define RX_CPU_SCRATCH_BASE     0x30000
6046 #define RX_CPU_SCRATCH_SIZE     0x04000
6047 #define TX_CPU_SCRATCH_BASE     0x34000
6048 #define TX_CPU_SCRATCH_SIZE     0x04000
6049
6050 /* tp->lock is held. */
6051 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6052 {
6053         int i;
6054
6055         BUG_ON(offset == TX_CPU_BASE &&
6056             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6057
6058         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6059                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6060
6061                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6062                 return 0;
6063         }
6064         if (offset == RX_CPU_BASE) {
6065                 for (i = 0; i < 10000; i++) {
6066                         tw32(offset + CPU_STATE, 0xffffffff);
6067                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6068                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6069                                 break;
6070                 }
6071
6072                 tw32(offset + CPU_STATE, 0xffffffff);
6073                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6074                 udelay(10);
6075         } else {
6076                 for (i = 0; i < 10000; i++) {
6077                         tw32(offset + CPU_STATE, 0xffffffff);
6078                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6079                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6080                                 break;
6081                 }
6082         }
6083
6084         if (i >= 10000) {
6085                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6086                        "and %s CPU\n",
6087                        tp->dev->name,
6088                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6089                 return -ENODEV;
6090         }
6091
6092         /* Clear firmware's nvram arbitration. */
6093         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6094                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6095         return 0;
6096 }
6097
6098 struct fw_info {
6099         unsigned int text_base;
6100         unsigned int text_len;
6101         const u32 *text_data;
6102         unsigned int rodata_base;
6103         unsigned int rodata_len;
6104         const u32 *rodata_data;
6105         unsigned int data_base;
6106         unsigned int data_len;
6107         const u32 *data_data;
6108 };
6109
6110 /* tp->lock is held. */
6111 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6112                                  int cpu_scratch_size, struct fw_info *info)
6113 {
6114         int err, lock_err, i;
6115         void (*write_op)(struct tg3 *, u32, u32);
6116
6117         if (cpu_base == TX_CPU_BASE &&
6118             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6119                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6120                        "TX cpu firmware on %s which is 5705.\n",
6121                        tp->dev->name);
6122                 return -EINVAL;
6123         }
6124
6125         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6126                 write_op = tg3_write_mem;
6127         else
6128                 write_op = tg3_write_indirect_reg32;
6129
6130         /* It is possible that bootcode is still loading at this point.
6131          * Get the nvram lock first before halting the cpu.
6132          */
6133         lock_err = tg3_nvram_lock(tp);
6134         err = tg3_halt_cpu(tp, cpu_base);
6135         if (!lock_err)
6136                 tg3_nvram_unlock(tp);
6137         if (err)
6138                 goto out;
6139
6140         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6141                 write_op(tp, cpu_scratch_base + i, 0);
6142         tw32(cpu_base + CPU_STATE, 0xffffffff);
6143         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6144         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
6145                 write_op(tp, (cpu_scratch_base +
6146                               (info->text_base & 0xffff) +
6147                               (i * sizeof(u32))),
6148                          (info->text_data ?
6149                           info->text_data[i] : 0));
6150         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
6151                 write_op(tp, (cpu_scratch_base +
6152                               (info->rodata_base & 0xffff) +
6153                               (i * sizeof(u32))),
6154                          (info->rodata_data ?
6155                           info->rodata_data[i] : 0));
6156         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
6157                 write_op(tp, (cpu_scratch_base +
6158                               (info->data_base & 0xffff) +
6159                               (i * sizeof(u32))),
6160                          (info->data_data ?
6161                           info->data_data[i] : 0));
6162
6163         err = 0;
6164
6165 out:
6166         return err;
6167 }
6168
6169 /* tp->lock is held. */
6170 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6171 {
6172         struct fw_info info;
6173         int err, i;
6174
6175         info.text_base = TG3_FW_TEXT_ADDR;
6176         info.text_len = TG3_FW_TEXT_LEN;
6177         info.text_data = &tg3FwText[0];
6178         info.rodata_base = TG3_FW_RODATA_ADDR;
6179         info.rodata_len = TG3_FW_RODATA_LEN;
6180         info.rodata_data = &tg3FwRodata[0];
6181         info.data_base = TG3_FW_DATA_ADDR;
6182         info.data_len = TG3_FW_DATA_LEN;
6183         info.data_data = NULL;
6184
6185         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6186                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6187                                     &info);
6188         if (err)
6189                 return err;
6190
6191         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6192                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6193                                     &info);
6194         if (err)
6195                 return err;
6196
6197         /* Now startup only the RX cpu. */
6198         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6199         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
6200
6201         for (i = 0; i < 5; i++) {
6202                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
6203                         break;
6204                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6205                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6206                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
6207                 udelay(1000);
6208         }
6209         if (i >= 5) {
6210                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6211                        "to set RX CPU PC, is %08x should be %08x\n",
6212                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6213                        TG3_FW_TEXT_ADDR);
6214                 return -ENODEV;
6215         }
6216         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6217         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6218
6219         return 0;
6220 }
6221
6222
6223 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
6224 #define TG3_TSO_FW_RELASE_MINOR         0x6
6225 #define TG3_TSO_FW_RELEASE_FIX          0x0
6226 #define TG3_TSO_FW_START_ADDR           0x08000000
6227 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
6228 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
6229 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
6230 #define TG3_TSO_FW_RODATA_LEN           0x60
6231 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
6232 #define TG3_TSO_FW_DATA_LEN             0x30
6233 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
6234 #define TG3_TSO_FW_SBSS_LEN             0x2c
6235 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
6236 #define TG3_TSO_FW_BSS_LEN              0x894
6237
6238 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
6239         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
6240         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
6241         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6242         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
6243         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
6244         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
6245         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
6246         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
6247         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
6248         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
6249         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
6250         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
6251         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
6252         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
6253         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
6254         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
6255         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
6256         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
6257         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6258         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
6259         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
6260         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
6261         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
6262         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
6263         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
6264         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
6265         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
6266         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
6267         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
6268         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6269         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
6270         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
6271         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
6272         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
6273         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
6274         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
6275         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
6276         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
6277         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6278         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
6279         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
6280         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
6281         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
6282         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
6283         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
6284         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
6285         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
6286         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6287         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
6288         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6289         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
6290         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
6291         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
6292         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
6293         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
6294         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
6295         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
6296         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
6297         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
6298         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
6299         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
6300         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
6301         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
6302         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
6303         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
6304         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
6305         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
6306         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
6307         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
6308         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
6309         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
6310         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
6311         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
6312         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
6313         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
6314         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
6315         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
6316         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
6317         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
6318         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
6319         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
6320         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
6321         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
6322         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
6323         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
6324         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
6325         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
6326         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
6327         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
6328         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
6329         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
6330         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
6331         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
6332         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
6333         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
6334         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
6335         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
6336         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
6337         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
6338         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
6339         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
6340         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
6341         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
6342         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
6343         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
6344         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
6345         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
6346         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
6347         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
6348         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
6349         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
6350         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
6351         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
6352         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
6353         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
6354         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
6355         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
6356         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
6357         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
6358         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
6359         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
6360         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
6361         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
6362         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
6363         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
6364         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
6365         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
6366         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
6367         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
6368         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
6369         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
6370         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
6371         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
6372         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
6373         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
6374         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
6375         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
6376         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
6377         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6378         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
6379         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
6380         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
6381         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
6382         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
6383         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
6384         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6385         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6386         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6387         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6388         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6389         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6390         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6391         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6392         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6393         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6394         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6395         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6396         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6397         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6398         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6399         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6400         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6401         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6402         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6403         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6404         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6405         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6406         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6407         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6408         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6409         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6410         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6411         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6412         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6413         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6414         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6415         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6416         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6417         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6418         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6419         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6420         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6421         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6422         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6423         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6424         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6425         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6426         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6427         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6428         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6429         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6430         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6431         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6432         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6433         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6434         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6435         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6436         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6437         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6438         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6439         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6440         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6441         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6442         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6443         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6444         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6445         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6446         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6447         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6448         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6449         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6450         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6451         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6452         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6453         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6454         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6455         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6456         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6457         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6458         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6459         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6460         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6461         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6462         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6463         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6464         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6465         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6466         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6467         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6468         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6469         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6470         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6471         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6472         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6473         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6474         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6475         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6476         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6477         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6478         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6479         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6480         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6481         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6482         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6483         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6484         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6485         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6486         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6487         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6488         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6489         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6490         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6491         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6492         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6493         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6494         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6495         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6496         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6497         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6498         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6499         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6500         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6501         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6502         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6503         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6504         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6505         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6506         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6507         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6508         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6509         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6510         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6511         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6512         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6513         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6514         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6515         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6516         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6517         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6518         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6519         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6520         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6521         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6522         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6523 };
6524
6525 static const u32 tg3TsoFwRodata[] = {
6526         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6527         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6528         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6529         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6530         0x00000000,
6531 };
6532
6533 static const u32 tg3TsoFwData[] = {
6534         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6535         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6536         0x00000000,
6537 };
6538
6539 /* 5705 needs a special version of the TSO firmware.  */
6540 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
6541 #define TG3_TSO5_FW_RELASE_MINOR        0x2
6542 #define TG3_TSO5_FW_RELEASE_FIX         0x0
6543 #define TG3_TSO5_FW_START_ADDR          0x00010000
6544 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
6545 #define TG3_TSO5_FW_TEXT_LEN            0xe90
6546 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
6547 #define TG3_TSO5_FW_RODATA_LEN          0x50
6548 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
6549 #define TG3_TSO5_FW_DATA_LEN            0x20
6550 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
6551 #define TG3_TSO5_FW_SBSS_LEN            0x28
6552 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
6553 #define TG3_TSO5_FW_BSS_LEN             0x88
6554
6555 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6556         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6557         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6558         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6559         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6560         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6561         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6562         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6563         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6564         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6565         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6566         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6567         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6568         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6569         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6570         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6571         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6572         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6573         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6574         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6575         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6576         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6577         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6578         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6579         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6580         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6581         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6582         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6583         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6584         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6585         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6586         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6587         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6588         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6589         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6590         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6591         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6592         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6593         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6594         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6595         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6596         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6597         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6598         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6599         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6600         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6601         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6602         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6603         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6604         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6605         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6606         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6607         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6608         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6609         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6610         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6611         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6612         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6613         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6614         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6615         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6616         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6617         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6618         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6619         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6620         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6621         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6622         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6623         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6624         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6625         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6626         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6627         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6628         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6629         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6630         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6631         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6632         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6633         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6634         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6635         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6636         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6637         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6638         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6639         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6640         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6641         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6642         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6643         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6644         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6645         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6646         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6647         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6648         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6649         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6650         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6651         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6652         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6653         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6654         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6655         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6656         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6657         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6658         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6659         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6660         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6661         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6662         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6663         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6664         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6665         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6666         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6667         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6668         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6669         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6670         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6671         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6672         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6673         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6674         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6675         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6676         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6677         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6678         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6679         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6680         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6681         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6682         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6683         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6684         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6685         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6686         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6687         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6688         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6689         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6690         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6691         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6692         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6693         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6694         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6695         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6696         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6697         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6698         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6699         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6700         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6701         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6702         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6703         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6704         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6705         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6706         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6707         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6708         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6709         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6710         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6711         0x00000000, 0x00000000, 0x00000000,
6712 };
6713
6714 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
6715         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6716         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6717         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6718         0x00000000, 0x00000000, 0x00000000,
6719 };
6720
6721 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
6722         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6723         0x00000000, 0x00000000, 0x00000000,
6724 };
6725
6726 /* tp->lock is held. */
6727 static int tg3_load_tso_firmware(struct tg3 *tp)
6728 {
6729         struct fw_info info;
6730         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6731         int err, i;
6732
6733         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6734                 return 0;
6735
6736         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6737                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6738                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6739                 info.text_data = &tg3Tso5FwText[0];
6740                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6741                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6742                 info.rodata_data = &tg3Tso5FwRodata[0];
6743                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6744                 info.data_len = TG3_TSO5_FW_DATA_LEN;
6745                 info.data_data = &tg3Tso5FwData[0];
6746                 cpu_base = RX_CPU_BASE;
6747                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6748                 cpu_scratch_size = (info.text_len +
6749                                     info.rodata_len +
6750                                     info.data_len +
6751                                     TG3_TSO5_FW_SBSS_LEN +
6752                                     TG3_TSO5_FW_BSS_LEN);
6753         } else {
6754                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6755                 info.text_len = TG3_TSO_FW_TEXT_LEN;
6756                 info.text_data = &tg3TsoFwText[0];
6757                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6758                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6759                 info.rodata_data = &tg3TsoFwRodata[0];
6760                 info.data_base = TG3_TSO_FW_DATA_ADDR;
6761                 info.data_len = TG3_TSO_FW_DATA_LEN;
6762                 info.data_data = &tg3TsoFwData[0];
6763                 cpu_base = TX_CPU_BASE;
6764                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6765                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6766         }
6767
6768         err = tg3_load_firmware_cpu(tp, cpu_base,
6769                                     cpu_scratch_base, cpu_scratch_size,
6770                                     &info);
6771         if (err)
6772                 return err;
6773
6774         /* Now startup the cpu. */
6775         tw32(cpu_base + CPU_STATE, 0xffffffff);
6776         tw32_f(cpu_base + CPU_PC,    info.text_base);
6777
6778         for (i = 0; i < 5; i++) {
6779                 if (tr32(cpu_base + CPU_PC) == info.text_base)
6780                         break;
6781                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6782                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6783                 tw32_f(cpu_base + CPU_PC,    info.text_base);
6784                 udelay(1000);
6785         }
6786         if (i >= 5) {
6787                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6788                        "to set CPU PC, is %08x should be %08x\n",
6789                        tp->dev->name, tr32(cpu_base + CPU_PC),
6790                        info.text_base);
6791                 return -ENODEV;
6792         }
6793         tw32(cpu_base + CPU_STATE, 0xffffffff);
6794         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6795         return 0;
6796 }
6797
6798
6799 /* tp->lock is held. */
6800 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6801 {
6802         u32 addr_high, addr_low;
6803         int i;
6804
6805         addr_high = ((tp->dev->dev_addr[0] << 8) |
6806                      tp->dev->dev_addr[1]);
6807         addr_low = ((tp->dev->dev_addr[2] << 24) |
6808                     (tp->dev->dev_addr[3] << 16) |
6809                     (tp->dev->dev_addr[4] <<  8) |
6810                     (tp->dev->dev_addr[5] <<  0));
6811         for (i = 0; i < 4; i++) {
6812                 if (i == 1 && skip_mac_1)
6813                         continue;
6814                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6815                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6816         }
6817
6818         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6819             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6820                 for (i = 0; i < 12; i++) {
6821                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6822                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6823                 }
6824         }
6825
6826         addr_high = (tp->dev->dev_addr[0] +
6827                      tp->dev->dev_addr[1] +
6828                      tp->dev->dev_addr[2] +
6829                      tp->dev->dev_addr[3] +
6830                      tp->dev->dev_addr[4] +
6831                      tp->dev->dev_addr[5]) &
6832                 TX_BACKOFF_SEED_MASK;
6833         tw32(MAC_TX_BACKOFF_SEED, addr_high);
6834 }
6835
6836 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6837 {
6838         struct tg3 *tp = netdev_priv(dev);
6839         struct sockaddr *addr = p;
6840         int err = 0, skip_mac_1 = 0;
6841
6842         if (!is_valid_ether_addr(addr->sa_data))
6843                 return -EINVAL;
6844
6845         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6846
6847         if (!netif_running(dev))
6848                 return 0;
6849
6850         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6851                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6852
6853                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6854                 addr0_low = tr32(MAC_ADDR_0_LOW);
6855                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6856                 addr1_low = tr32(MAC_ADDR_1_LOW);
6857
6858                 /* Skip MAC addr 1 if ASF is using it. */
6859                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6860                     !(addr1_high == 0 && addr1_low == 0))
6861                         skip_mac_1 = 1;
6862         }
6863         spin_lock_bh(&tp->lock);
6864         __tg3_set_mac_addr(tp, skip_mac_1);
6865         spin_unlock_bh(&tp->lock);
6866
6867         return err;
6868 }
6869
6870 /* tp->lock is held. */
6871 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6872                            dma_addr_t mapping, u32 maxlen_flags,
6873                            u32 nic_addr)
6874 {
6875         tg3_write_mem(tp,
6876                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6877                       ((u64) mapping >> 32));
6878         tg3_write_mem(tp,
6879                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6880                       ((u64) mapping & 0xffffffff));
6881         tg3_write_mem(tp,
6882                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6883                        maxlen_flags);
6884
6885         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6886                 tg3_write_mem(tp,
6887                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6888                               nic_addr);
6889 }
6890
6891 static void __tg3_set_rx_mode(struct net_device *);
6892 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6893 {
6894         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6895         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6896         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6897         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6898         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6899                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6900                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6901         }
6902         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6903         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6904         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6905                 u32 val = ec->stats_block_coalesce_usecs;
6906
6907                 if (!netif_carrier_ok(tp->dev))
6908                         val = 0;
6909
6910                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6911         }
6912 }
6913
6914 /* tp->lock is held. */
6915 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6916 {
6917         u32 val, rdmac_mode;
6918         int i, err, limit;
6919
6920         tg3_disable_ints(tp);
6921
6922         tg3_stop_fw(tp);
6923
6924         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6925
6926         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6927                 tg3_abort_hw(tp, 1);
6928         }
6929
6930         if (reset_phy &&
6931             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6932                 tg3_phy_reset(tp);
6933
6934         err = tg3_chip_reset(tp);
6935         if (err)
6936                 return err;
6937
6938         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6939
6940         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
6941             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
6942                 val = tr32(TG3_CPMU_CTRL);
6943                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6944                 tw32(TG3_CPMU_CTRL, val);
6945
6946                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6947                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6948                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6949                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6950
6951                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6952                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6953                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6954                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6955
6956                 val = tr32(TG3_CPMU_HST_ACC);
6957                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6958                 val |= CPMU_HST_ACC_MACCLK_6_25;
6959                 tw32(TG3_CPMU_HST_ACC, val);
6960         }
6961
6962         /* This works around an issue with Athlon chipsets on
6963          * B3 tigon3 silicon.  This bit has no effect on any
6964          * other revision.  But do not set this on PCI Express
6965          * chips and don't even touch the clocks if the CPMU is present.
6966          */
6967         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6968                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6969                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6970                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6971         }
6972
6973         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6974             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6975                 val = tr32(TG3PCI_PCISTATE);
6976                 val |= PCISTATE_RETRY_SAME_DMA;
6977                 tw32(TG3PCI_PCISTATE, val);
6978         }
6979
6980         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6981                 /* Allow reads and writes to the
6982                  * APE register and memory space.
6983                  */
6984                 val = tr32(TG3PCI_PCISTATE);
6985                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6986                        PCISTATE_ALLOW_APE_SHMEM_WR;
6987                 tw32(TG3PCI_PCISTATE, val);
6988         }
6989
6990         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6991                 /* Enable some hw fixes.  */
6992                 val = tr32(TG3PCI_MSI_DATA);
6993                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6994                 tw32(TG3PCI_MSI_DATA, val);
6995         }
6996
6997         /* Descriptor ring init may make accesses to the
6998          * NIC SRAM area to setup the TX descriptors, so we
6999          * can only do this after the hardware has been
7000          * successfully reset.
7001          */
7002         err = tg3_init_rings(tp);
7003         if (err)
7004                 return err;
7005
7006         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7007             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7008                 /* This value is determined during the probe time DMA
7009                  * engine test, tg3_test_dma.
7010                  */
7011                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7012         }
7013
7014         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7015                           GRC_MODE_4X_NIC_SEND_RINGS |
7016                           GRC_MODE_NO_TX_PHDR_CSUM |
7017                           GRC_MODE_NO_RX_PHDR_CSUM);
7018         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7019
7020         /* Pseudo-header checksum is done by hardware logic and not
7021          * the offload processers, so make the chip do the pseudo-
7022          * header checksums on receive.  For transmit it is more
7023          * convenient to do the pseudo-header checksum in software
7024          * as Linux does that on transmit for us in all cases.
7025          */
7026         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7027
7028         tw32(GRC_MODE,
7029              tp->grc_mode |
7030              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7031
7032         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7033         val = tr32(GRC_MISC_CFG);
7034         val &= ~0xff;
7035         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7036         tw32(GRC_MISC_CFG, val);
7037
7038         /* Initialize MBUF/DESC pool. */
7039         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7040                 /* Do nothing.  */
7041         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7042                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7043                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7044                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7045                 else
7046                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7047                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7048                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7049         }
7050         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7051                 int fw_len;
7052
7053                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
7054                           TG3_TSO5_FW_RODATA_LEN +
7055                           TG3_TSO5_FW_DATA_LEN +
7056                           TG3_TSO5_FW_SBSS_LEN +
7057                           TG3_TSO5_FW_BSS_LEN);
7058                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7059                 tw32(BUFMGR_MB_POOL_ADDR,
7060                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7061                 tw32(BUFMGR_MB_POOL_SIZE,
7062                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7063         }
7064
7065         if (tp->dev->mtu <= ETH_DATA_LEN) {
7066                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7067                      tp->bufmgr_config.mbuf_read_dma_low_water);
7068                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7069                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7070                 tw32(BUFMGR_MB_HIGH_WATER,
7071                      tp->bufmgr_config.mbuf_high_water);
7072         } else {
7073                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7074                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7075                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7076                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7077                 tw32(BUFMGR_MB_HIGH_WATER,
7078                      tp->bufmgr_config.mbuf_high_water_jumbo);
7079         }
7080         tw32(BUFMGR_DMA_LOW_WATER,
7081              tp->bufmgr_config.dma_low_water);
7082         tw32(BUFMGR_DMA_HIGH_WATER,
7083              tp->bufmgr_config.dma_high_water);
7084
7085         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7086         for (i = 0; i < 2000; i++) {
7087                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7088                         break;
7089                 udelay(10);
7090         }
7091         if (i >= 2000) {
7092                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7093                        tp->dev->name);
7094                 return -ENODEV;
7095         }
7096
7097         /* Setup replenish threshold. */
7098         val = tp->rx_pending / 8;
7099         if (val == 0)
7100                 val = 1;
7101         else if (val > tp->rx_std_max_post)
7102                 val = tp->rx_std_max_post;
7103         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7104                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7105                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7106
7107                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7108                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7109         }
7110
7111         tw32(RCVBDI_STD_THRESH, val);
7112
7113         /* Initialize TG3_BDINFO's at:
7114          *  RCVDBDI_STD_BD:     standard eth size rx ring
7115          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7116          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7117          *
7118          * like so:
7119          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7120          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7121          *                              ring attribute flags
7122          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7123          *
7124          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7125          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7126          *
7127          * The size of each ring is fixed in the firmware, but the location is
7128          * configurable.
7129          */
7130         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7131              ((u64) tp->rx_std_mapping >> 32));
7132         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7133              ((u64) tp->rx_std_mapping & 0xffffffff));
7134         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7135              NIC_SRAM_RX_BUFFER_DESC);
7136
7137         /* Don't even try to program the JUMBO/MINI buffer descriptor
7138          * configs on 5705.
7139          */
7140         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7141                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7142                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
7143         } else {
7144                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7145                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7146
7147                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7148                      BDINFO_FLAGS_DISABLED);
7149
7150                 /* Setup replenish threshold. */
7151                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7152
7153                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7154                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7155                              ((u64) tp->rx_jumbo_mapping >> 32));
7156                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7157                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
7158                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7159                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7160                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7161                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7162                 } else {
7163                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7164                              BDINFO_FLAGS_DISABLED);
7165                 }
7166
7167         }
7168
7169         /* There is only one send ring on 5705/5750, no need to explicitly
7170          * disable the others.
7171          */
7172         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7173                 /* Clear out send RCB ring in SRAM. */
7174                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7175                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7176                                       BDINFO_FLAGS_DISABLED);
7177         }
7178
7179         tp->tx_prod = 0;
7180         tp->tx_cons = 0;
7181         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7182         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7183
7184         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7185                        tp->tx_desc_mapping,
7186                        (TG3_TX_RING_SIZE <<
7187                         BDINFO_FLAGS_MAXLEN_SHIFT),
7188                        NIC_SRAM_TX_BUFFER_DESC);
7189
7190         /* There is only one receive return ring on 5705/5750, no need
7191          * to explicitly disable the others.
7192          */
7193         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7194                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7195                      i += TG3_BDINFO_SIZE) {
7196                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7197                                       BDINFO_FLAGS_DISABLED);
7198                 }
7199         }
7200
7201         tp->rx_rcb_ptr = 0;
7202         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7203
7204         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7205                        tp->rx_rcb_mapping,
7206                        (TG3_RX_RCB_RING_SIZE(tp) <<
7207                         BDINFO_FLAGS_MAXLEN_SHIFT),
7208                        0);
7209
7210         tp->rx_std_ptr = tp->rx_pending;
7211         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7212                      tp->rx_std_ptr);
7213
7214         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7215                                                 tp->rx_jumbo_pending : 0;
7216         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7217                      tp->rx_jumbo_ptr);
7218
7219         /* Initialize MAC address and backoff seed. */
7220         __tg3_set_mac_addr(tp, 0);
7221
7222         /* MTU + ethernet header + FCS + optional VLAN tag */
7223         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
7224
7225         /* The slot time is changed by tg3_setup_phy if we
7226          * run at gigabit with half duplex.
7227          */
7228         tw32(MAC_TX_LENGTHS,
7229              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7230              (6 << TX_LENGTHS_IPG_SHIFT) |
7231              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7232
7233         /* Receive rules. */
7234         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7235         tw32(RCVLPC_CONFIG, 0x0181);
7236
7237         /* Calculate RDMAC_MODE setting early, we need it to determine
7238          * the RCVLPC_STATE_ENABLE mask.
7239          */
7240         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7241                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7242                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7243                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7244                       RDMAC_MODE_LNGREAD_ENAB);
7245
7246         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
7247                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7248                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7249                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7250
7251         /* If statement applies to 5705 and 5750 PCI devices only */
7252         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7253              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7254             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7255                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7256                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7257                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7258                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7259                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7260                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7261                 }
7262         }
7263
7264         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7265                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7266
7267         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7268                 rdmac_mode |= (1 << 27);
7269
7270         /* Receive/send statistics. */
7271         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7272                 val = tr32(RCVLPC_STATS_ENABLE);
7273                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7274                 tw32(RCVLPC_STATS_ENABLE, val);
7275         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7276                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7277                 val = tr32(RCVLPC_STATS_ENABLE);
7278                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7279                 tw32(RCVLPC_STATS_ENABLE, val);
7280         } else {
7281                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7282         }
7283         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7284         tw32(SNDDATAI_STATSENAB, 0xffffff);
7285         tw32(SNDDATAI_STATSCTRL,
7286              (SNDDATAI_SCTRL_ENABLE |
7287               SNDDATAI_SCTRL_FASTUPD));
7288
7289         /* Setup host coalescing engine. */
7290         tw32(HOSTCC_MODE, 0);
7291         for (i = 0; i < 2000; i++) {
7292                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7293                         break;
7294                 udelay(10);
7295         }
7296
7297         __tg3_set_coalesce(tp, &tp->coal);
7298
7299         /* set status block DMA address */
7300         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7301              ((u64) tp->status_mapping >> 32));
7302         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7303              ((u64) tp->status_mapping & 0xffffffff));
7304
7305         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7306                 /* Status/statistics block address.  See tg3_timer,
7307                  * the tg3_periodic_fetch_stats call there, and
7308                  * tg3_get_stats to see how this works for 5705/5750 chips.
7309                  */
7310                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7311                      ((u64) tp->stats_mapping >> 32));
7312                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7313                      ((u64) tp->stats_mapping & 0xffffffff));
7314                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7315                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7316         }
7317
7318         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7319
7320         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7321         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7322         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7323                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7324
7325         /* Clear statistics/status block in chip, and status block in ram. */
7326         for (i = NIC_SRAM_STATS_BLK;
7327              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7328              i += sizeof(u32)) {
7329                 tg3_write_mem(tp, i, 0);
7330                 udelay(40);
7331         }
7332         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7333
7334         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7335                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7336                 /* reset to prevent losing 1st rx packet intermittently */
7337                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7338                 udelay(10);
7339         }
7340
7341         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7342                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7343         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7344             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7345             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7346                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7347         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7348         udelay(40);
7349
7350         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7351          * If TG3_FLG2_IS_NIC is zero, we should read the
7352          * register to preserve the GPIO settings for LOMs. The GPIOs,
7353          * whether used as inputs or outputs, are set by boot code after
7354          * reset.
7355          */
7356         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7357                 u32 gpio_mask;
7358
7359                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7360                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7361                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7362
7363                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7364                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7365                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7366
7367                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7368                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7369
7370                 tp->grc_local_ctrl &= ~gpio_mask;
7371                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7372
7373                 /* GPIO1 must be driven high for eeprom write protect */
7374                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7375                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7376                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7377         }
7378         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7379         udelay(100);
7380
7381         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7382         tp->last_tag = 0;
7383
7384         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7385                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7386                 udelay(40);
7387         }
7388
7389         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7390                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7391                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7392                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7393                WDMAC_MODE_LNGREAD_ENAB);
7394
7395         /* If statement applies to 5705 and 5750 PCI devices only */
7396         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7397              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7398             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7399                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7400                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7401                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7402                         /* nothing */
7403                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7404                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7405                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7406                         val |= WDMAC_MODE_RX_ACCEL;
7407                 }
7408         }
7409
7410         /* Enable host coalescing bug fix */
7411         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7412             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7413             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7414             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761))
7415                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7416
7417         tw32_f(WDMAC_MODE, val);
7418         udelay(40);
7419
7420         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7421                 u16 pcix_cmd;
7422
7423                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7424                                      &pcix_cmd);
7425                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7426                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7427                         pcix_cmd |= PCI_X_CMD_READ_2K;
7428                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7429                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7430                         pcix_cmd |= PCI_X_CMD_READ_2K;
7431                 }
7432                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7433                                       pcix_cmd);
7434         }
7435
7436         tw32_f(RDMAC_MODE, rdmac_mode);
7437         udelay(40);
7438
7439         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7440         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7441                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7442
7443         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7444                 tw32(SNDDATAC_MODE,
7445                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7446         else
7447                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7448
7449         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7450         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7451         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7452         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7453         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7454                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7455         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7456         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7457
7458         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7459                 err = tg3_load_5701_a0_firmware_fix(tp);
7460                 if (err)
7461                         return err;
7462         }
7463
7464         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7465                 err = tg3_load_tso_firmware(tp);
7466                 if (err)
7467                         return err;
7468         }
7469
7470         tp->tx_mode = TX_MODE_ENABLE;
7471         tw32_f(MAC_TX_MODE, tp->tx_mode);
7472         udelay(100);
7473
7474         tp->rx_mode = RX_MODE_ENABLE;
7475         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7476             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7477                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7478
7479         tw32_f(MAC_RX_MODE, tp->rx_mode);
7480         udelay(10);
7481
7482         tw32(MAC_LED_CTRL, tp->led_ctrl);
7483
7484         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7485         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7486                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7487                 udelay(10);
7488         }
7489         tw32_f(MAC_RX_MODE, tp->rx_mode);
7490         udelay(10);
7491
7492         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7493                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7494                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7495                         /* Set drive transmission level to 1.2V  */
7496                         /* only if the signal pre-emphasis bit is not set  */
7497                         val = tr32(MAC_SERDES_CFG);
7498                         val &= 0xfffff000;
7499                         val |= 0x880;
7500                         tw32(MAC_SERDES_CFG, val);
7501                 }
7502                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7503                         tw32(MAC_SERDES_CFG, 0x616000);
7504         }
7505
7506         /* Prevent chip from dropping frames when flow control
7507          * is enabled.
7508          */
7509         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7510
7511         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7512             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7513                 /* Use hardware link auto-negotiation */
7514                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7515         }
7516
7517         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7518             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7519                 u32 tmp;
7520
7521                 tmp = tr32(SERDES_RX_CTRL);
7522                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7523                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7524                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7525                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7526         }
7527
7528         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7529                 if (tp->link_config.phy_is_low_power) {
7530                         tp->link_config.phy_is_low_power = 0;
7531                         tp->link_config.speed = tp->link_config.orig_speed;
7532                         tp->link_config.duplex = tp->link_config.orig_duplex;
7533                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7534                 }
7535
7536                 err = tg3_setup_phy(tp, 0);
7537                 if (err)
7538                         return err;
7539
7540                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7541                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7542                         u32 tmp;
7543
7544                         /* Clear CRC stats. */
7545                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7546                                 tg3_writephy(tp, MII_TG3_TEST1,
7547                                              tmp | MII_TG3_TEST1_CRC_EN);
7548                                 tg3_readphy(tp, 0x14, &tmp);
7549                         }
7550                 }
7551         }
7552
7553         __tg3_set_rx_mode(tp->dev);
7554
7555         /* Initialize receive rules. */
7556         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7557         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7558         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7559         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7560
7561         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7562             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7563                 limit = 8;
7564         else
7565                 limit = 16;
7566         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7567                 limit -= 4;
7568         switch (limit) {
7569         case 16:
7570                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7571         case 15:
7572                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7573         case 14:
7574                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7575         case 13:
7576                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7577         case 12:
7578                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7579         case 11:
7580                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7581         case 10:
7582                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7583         case 9:
7584                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7585         case 8:
7586                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7587         case 7:
7588                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7589         case 6:
7590                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7591         case 5:
7592                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7593         case 4:
7594                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7595         case 3:
7596                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7597         case 2:
7598         case 1:
7599
7600         default:
7601                 break;
7602         };
7603
7604         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7605                 /* Write our heartbeat update interval to APE. */
7606                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7607                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7608
7609         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7610
7611         return 0;
7612 }
7613
7614 /* Called at device open time to get the chip ready for
7615  * packet processing.  Invoked with tp->lock held.
7616  */
7617 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7618 {
7619         int err;
7620
7621         /* Force the chip into D0. */
7622         err = tg3_set_power_state(tp, PCI_D0);
7623         if (err)
7624                 goto out;
7625
7626         tg3_switch_clocks(tp);
7627
7628         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7629
7630         err = tg3_reset_hw(tp, reset_phy);
7631
7632 out:
7633         return err;
7634 }
7635
7636 #define TG3_STAT_ADD32(PSTAT, REG) \
7637 do {    u32 __val = tr32(REG); \
7638         (PSTAT)->low += __val; \
7639         if ((PSTAT)->low < __val) \
7640                 (PSTAT)->high += 1; \
7641 } while (0)
7642
7643 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7644 {
7645         struct tg3_hw_stats *sp = tp->hw_stats;
7646
7647         if (!netif_carrier_ok(tp->dev))
7648                 return;
7649
7650         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7651         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7652         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7653         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7654         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7655         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7656         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7657         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7658         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7659         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7660         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7661         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7662         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7663
7664         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7665         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7666         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7667         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7668         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7669         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7670         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7671         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7672         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7673         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7674         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7675         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7676         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7677         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7678
7679         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7680         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7681         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7682 }
7683
7684 static void tg3_timer(unsigned long __opaque)
7685 {
7686         struct tg3 *tp = (struct tg3 *) __opaque;
7687
7688         if (tp->irq_sync)
7689                 goto restart_timer;
7690
7691         spin_lock(&tp->lock);
7692
7693         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7694                 /* All of this garbage is because when using non-tagged
7695                  * IRQ status the mailbox/status_block protocol the chip
7696                  * uses with the cpu is race prone.
7697                  */
7698                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7699                         tw32(GRC_LOCAL_CTRL,
7700                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7701                 } else {
7702                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7703                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7704                 }
7705
7706                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7707                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7708                         spin_unlock(&tp->lock);
7709                         schedule_work(&tp->reset_task);
7710                         return;
7711                 }
7712         }
7713
7714         /* This part only runs once per second. */
7715         if (!--tp->timer_counter) {
7716                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7717                         tg3_periodic_fetch_stats(tp);
7718
7719                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7720                         u32 mac_stat;
7721                         int phy_event;
7722
7723                         mac_stat = tr32(MAC_STATUS);
7724
7725                         phy_event = 0;
7726                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7727                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7728                                         phy_event = 1;
7729                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7730                                 phy_event = 1;
7731
7732                         if (phy_event)
7733                                 tg3_setup_phy(tp, 0);
7734                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7735                         u32 mac_stat = tr32(MAC_STATUS);
7736                         int need_setup = 0;
7737
7738                         if (netif_carrier_ok(tp->dev) &&
7739                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7740                                 need_setup = 1;
7741                         }
7742                         if (! netif_carrier_ok(tp->dev) &&
7743                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7744                                          MAC_STATUS_SIGNAL_DET))) {
7745                                 need_setup = 1;
7746                         }
7747                         if (need_setup) {
7748                                 if (!tp->serdes_counter) {
7749                                         tw32_f(MAC_MODE,
7750                                              (tp->mac_mode &
7751                                               ~MAC_MODE_PORT_MODE_MASK));
7752                                         udelay(40);
7753                                         tw32_f(MAC_MODE, tp->mac_mode);
7754                                         udelay(40);
7755                                 }
7756                                 tg3_setup_phy(tp, 0);
7757                         }
7758                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7759                         tg3_serdes_parallel_detect(tp);
7760
7761                 tp->timer_counter = tp->timer_multiplier;
7762         }
7763
7764         /* Heartbeat is only sent once every 2 seconds.
7765          *
7766          * The heartbeat is to tell the ASF firmware that the host
7767          * driver is still alive.  In the event that the OS crashes,
7768          * ASF needs to reset the hardware to free up the FIFO space
7769          * that may be filled with rx packets destined for the host.
7770          * If the FIFO is full, ASF will no longer function properly.
7771          *
7772          * Unintended resets have been reported on real time kernels
7773          * where the timer doesn't run on time.  Netpoll will also have
7774          * same problem.
7775          *
7776          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7777          * to check the ring condition when the heartbeat is expiring
7778          * before doing the reset.  This will prevent most unintended
7779          * resets.
7780          */
7781         if (!--tp->asf_counter) {
7782                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7783                         u32 val;
7784
7785                         tg3_wait_for_event_ack(tp);
7786
7787                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7788                                       FWCMD_NICDRV_ALIVE3);
7789                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7790                         /* 5 seconds timeout */
7791                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7792                         val = tr32(GRC_RX_CPU_EVENT);
7793                         val |= GRC_RX_CPU_DRIVER_EVENT;
7794                         tw32_f(GRC_RX_CPU_EVENT, val);
7795                 }
7796                 tp->asf_counter = tp->asf_multiplier;
7797         }
7798
7799         spin_unlock(&tp->lock);
7800
7801 restart_timer:
7802         tp->timer.expires = jiffies + tp->timer_offset;
7803         add_timer(&tp->timer);
7804 }
7805
7806 static int tg3_request_irq(struct tg3 *tp)
7807 {
7808         irq_handler_t fn;
7809         unsigned long flags;
7810         struct net_device *dev = tp->dev;
7811
7812         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7813                 fn = tg3_msi;
7814                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7815                         fn = tg3_msi_1shot;
7816                 flags = IRQF_SAMPLE_RANDOM;
7817         } else {
7818                 fn = tg3_interrupt;
7819                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7820                         fn = tg3_interrupt_tagged;
7821                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7822         }
7823         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7824 }
7825
7826 static int tg3_test_interrupt(struct tg3 *tp)
7827 {
7828         struct net_device *dev = tp->dev;
7829         int err, i, intr_ok = 0;
7830
7831         if (!netif_running(dev))
7832                 return -ENODEV;
7833
7834         tg3_disable_ints(tp);
7835
7836         free_irq(tp->pdev->irq, dev);
7837
7838         err = request_irq(tp->pdev->irq, tg3_test_isr,
7839                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7840         if (err)
7841                 return err;
7842
7843         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7844         tg3_enable_ints(tp);
7845
7846         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7847                HOSTCC_MODE_NOW);
7848
7849         for (i = 0; i < 5; i++) {
7850                 u32 int_mbox, misc_host_ctrl;
7851
7852                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7853                                         TG3_64BIT_REG_LOW);
7854                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7855
7856                 if ((int_mbox != 0) ||
7857                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7858                         intr_ok = 1;
7859                         break;
7860                 }
7861
7862                 msleep(10);
7863         }
7864
7865         tg3_disable_ints(tp);
7866
7867         free_irq(tp->pdev->irq, dev);
7868
7869         err = tg3_request_irq(tp);
7870
7871         if (err)
7872                 return err;
7873
7874         if (intr_ok)
7875                 return 0;
7876
7877         return -EIO;
7878 }
7879
7880 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7881  * successfully restored
7882  */
7883 static int tg3_test_msi(struct tg3 *tp)
7884 {
7885         struct net_device *dev = tp->dev;
7886         int err;
7887         u16 pci_cmd;
7888
7889         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7890                 return 0;
7891
7892         /* Turn off SERR reporting in case MSI terminates with Master
7893          * Abort.
7894          */
7895         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7896         pci_write_config_word(tp->pdev, PCI_COMMAND,
7897                               pci_cmd & ~PCI_COMMAND_SERR);
7898
7899         err = tg3_test_interrupt(tp);
7900
7901         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7902
7903         if (!err)
7904                 return 0;
7905
7906         /* other failures */
7907         if (err != -EIO)
7908                 return err;
7909
7910         /* MSI test failed, go back to INTx mode */
7911         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7912                "switching to INTx mode. Please report this failure to "
7913                "the PCI maintainer and include system chipset information.\n",
7914                        tp->dev->name);
7915
7916         free_irq(tp->pdev->irq, dev);
7917         pci_disable_msi(tp->pdev);
7918
7919         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7920
7921         err = tg3_request_irq(tp);
7922         if (err)
7923                 return err;
7924
7925         /* Need to reset the chip because the MSI cycle may have terminated
7926          * with Master Abort.
7927          */
7928         tg3_full_lock(tp, 1);
7929
7930         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7931         err = tg3_init_hw(tp, 1);
7932
7933         tg3_full_unlock(tp);
7934
7935         if (err)
7936                 free_irq(tp->pdev->irq, dev);
7937
7938         return err;
7939 }
7940
7941 static int tg3_open(struct net_device *dev)
7942 {
7943         struct tg3 *tp = netdev_priv(dev);
7944         int err;
7945
7946         netif_carrier_off(tp->dev);
7947
7948         tg3_full_lock(tp, 0);
7949
7950         err = tg3_set_power_state(tp, PCI_D0);
7951         if (err) {
7952                 tg3_full_unlock(tp);
7953                 return err;
7954         }
7955
7956         tg3_disable_ints(tp);
7957         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7958
7959         tg3_full_unlock(tp);
7960
7961         /* The placement of this call is tied
7962          * to the setup and use of Host TX descriptors.
7963          */
7964         err = tg3_alloc_consistent(tp);
7965         if (err)
7966                 return err;
7967
7968         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7969                 /* All MSI supporting chips should support tagged
7970                  * status.  Assert that this is the case.
7971                  */
7972                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7973                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7974                                "Not using MSI.\n", tp->dev->name);
7975                 } else if (pci_enable_msi(tp->pdev) == 0) {
7976                         u32 msi_mode;
7977
7978                         msi_mode = tr32(MSGINT_MODE);
7979                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7980                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7981                 }
7982         }
7983         err = tg3_request_irq(tp);
7984
7985         if (err) {
7986                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7987                         pci_disable_msi(tp->pdev);
7988                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7989                 }
7990                 tg3_free_consistent(tp);
7991                 return err;
7992         }
7993
7994         napi_enable(&tp->napi);
7995
7996         tg3_full_lock(tp, 0);
7997
7998         err = tg3_init_hw(tp, 1);
7999         if (err) {
8000                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8001                 tg3_free_rings(tp);
8002         } else {
8003                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8004                         tp->timer_offset = HZ;
8005                 else
8006                         tp->timer_offset = HZ / 10;
8007
8008                 BUG_ON(tp->timer_offset > HZ);
8009                 tp->timer_counter = tp->timer_multiplier =
8010                         (HZ / tp->timer_offset);
8011                 tp->asf_counter = tp->asf_multiplier =
8012                         ((HZ / tp->timer_offset) * 2);
8013
8014                 init_timer(&tp->timer);
8015                 tp->timer.expires = jiffies + tp->timer_offset;
8016                 tp->timer.data = (unsigned long) tp;
8017                 tp->timer.function = tg3_timer;
8018         }
8019
8020         tg3_full_unlock(tp);
8021
8022         if (err) {
8023                 napi_disable(&tp->napi);
8024                 free_irq(tp->pdev->irq, dev);
8025                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8026                         pci_disable_msi(tp->pdev);
8027                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8028                 }
8029                 tg3_free_consistent(tp);
8030                 return err;
8031         }
8032
8033         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8034                 err = tg3_test_msi(tp);
8035
8036                 if (err) {
8037                         tg3_full_lock(tp, 0);
8038
8039                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8040                                 pci_disable_msi(tp->pdev);
8041                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8042                         }
8043                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8044                         tg3_free_rings(tp);
8045                         tg3_free_consistent(tp);
8046
8047                         tg3_full_unlock(tp);
8048
8049                         napi_disable(&tp->napi);
8050
8051                         return err;
8052                 }
8053
8054                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8055                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8056                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
8057
8058                                 tw32(PCIE_TRANSACTION_CFG,
8059                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
8060                         }
8061                 }
8062         }
8063
8064         tg3_phy_start(tp);
8065
8066         tg3_full_lock(tp, 0);
8067
8068         add_timer(&tp->timer);
8069         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8070         tg3_enable_ints(tp);
8071
8072         tg3_full_unlock(tp);
8073
8074         netif_start_queue(dev);
8075
8076         return 0;
8077 }
8078
8079 #if 0
8080 /*static*/ void tg3_dump_state(struct tg3 *tp)
8081 {
8082         u32 val32, val32_2, val32_3, val32_4, val32_5;
8083         u16 val16;
8084         int i;
8085
8086         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8087         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8088         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8089                val16, val32);
8090
8091         /* MAC block */
8092         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8093                tr32(MAC_MODE), tr32(MAC_STATUS));
8094         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8095                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8096         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8097                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8098         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8099                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8100
8101         /* Send data initiator control block */
8102         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8103                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8104         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8105                tr32(SNDDATAI_STATSCTRL));
8106
8107         /* Send data completion control block */
8108         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8109
8110         /* Send BD ring selector block */
8111         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8112                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8113
8114         /* Send BD initiator control block */
8115         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8116                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8117
8118         /* Send BD completion control block */
8119         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8120
8121         /* Receive list placement control block */
8122         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8123                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8124         printk("       RCVLPC_STATSCTRL[%08x]\n",
8125                tr32(RCVLPC_STATSCTRL));
8126
8127         /* Receive data and receive BD initiator control block */
8128         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8129                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8130
8131         /* Receive data completion control block */
8132         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8133                tr32(RCVDCC_MODE));
8134
8135         /* Receive BD initiator control block */
8136         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8137                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8138
8139         /* Receive BD completion control block */
8140         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8141                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8142
8143         /* Receive list selector control block */
8144         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8145                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8146
8147         /* Mbuf cluster free block */
8148         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8149                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8150
8151         /* Host coalescing control block */
8152         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8153                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8154         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8155                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8156                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8157         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8158                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8159                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8160         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8161                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8162         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8163                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8164
8165         /* Memory arbiter control block */
8166         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8167                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8168
8169         /* Buffer manager control block */
8170         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8171                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8172         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8173                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8174         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8175                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8176                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8177                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8178
8179         /* Read DMA control block */
8180         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8181                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8182
8183         /* Write DMA control block */
8184         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8185                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8186
8187         /* DMA completion block */
8188         printk("DEBUG: DMAC_MODE[%08x]\n",
8189                tr32(DMAC_MODE));
8190
8191         /* GRC block */
8192         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8193                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8194         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8195                tr32(GRC_LOCAL_CTRL));
8196
8197         /* TG3_BDINFOs */
8198         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8199                tr32(RCVDBDI_JUMBO_BD + 0x0),
8200                tr32(RCVDBDI_JUMBO_BD + 0x4),
8201                tr32(RCVDBDI_JUMBO_BD + 0x8),
8202                tr32(RCVDBDI_JUMBO_BD + 0xc));
8203         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8204                tr32(RCVDBDI_STD_BD + 0x0),
8205                tr32(RCVDBDI_STD_BD + 0x4),
8206                tr32(RCVDBDI_STD_BD + 0x8),
8207                tr32(RCVDBDI_STD_BD + 0xc));
8208         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8209                tr32(RCVDBDI_MINI_BD + 0x0),
8210                tr32(RCVDBDI_MINI_BD + 0x4),
8211                tr32(RCVDBDI_MINI_BD + 0x8),
8212                tr32(RCVDBDI_MINI_BD + 0xc));
8213
8214         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8215         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8216         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8217         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8218         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8219                val32, val32_2, val32_3, val32_4);
8220
8221         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8222         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8223         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8224         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8225         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8226                val32, val32_2, val32_3, val32_4);
8227
8228         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8229         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8230         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8231         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8232         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8233         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8234                val32, val32_2, val32_3, val32_4, val32_5);
8235
8236         /* SW status block */
8237         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8238                tp->hw_status->status,
8239                tp->hw_status->status_tag,
8240                tp->hw_status->rx_jumbo_consumer,
8241                tp->hw_status->rx_consumer,
8242                tp->hw_status->rx_mini_consumer,
8243                tp->hw_status->idx[0].rx_producer,
8244                tp->hw_status->idx[0].tx_consumer);
8245
8246         /* SW statistics block */
8247         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8248                ((u32 *)tp->hw_stats)[0],
8249                ((u32 *)tp->hw_stats)[1],
8250                ((u32 *)tp->hw_stats)[2],
8251                ((u32 *)tp->hw_stats)[3]);
8252
8253         /* Mailboxes */
8254         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8255                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8256                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8257                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8258                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8259
8260         /* NIC side send descriptors. */
8261         for (i = 0; i < 6; i++) {
8262                 unsigned long txd;
8263
8264                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8265                         + (i * sizeof(struct tg3_tx_buffer_desc));
8266                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8267                        i,
8268                        readl(txd + 0x0), readl(txd + 0x4),
8269                        readl(txd + 0x8), readl(txd + 0xc));
8270         }
8271
8272         /* NIC side RX descriptors. */
8273         for (i = 0; i < 6; i++) {
8274                 unsigned long rxd;
8275
8276                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8277                         + (i * sizeof(struct tg3_rx_buffer_desc));
8278                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8279                        i,
8280                        readl(rxd + 0x0), readl(rxd + 0x4),
8281                        readl(rxd + 0x8), readl(rxd + 0xc));
8282                 rxd += (4 * sizeof(u32));
8283                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8284                        i,
8285                        readl(rxd + 0x0), readl(rxd + 0x4),
8286                        readl(rxd + 0x8), readl(rxd + 0xc));
8287         }
8288
8289         for (i = 0; i < 6; i++) {
8290                 unsigned long rxd;
8291
8292                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8293                         + (i * sizeof(struct tg3_rx_buffer_desc));
8294                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8295                        i,
8296                        readl(rxd + 0x0), readl(rxd + 0x4),
8297                        readl(rxd + 0x8), readl(rxd + 0xc));
8298                 rxd += (4 * sizeof(u32));
8299                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8300                        i,
8301                        readl(rxd + 0x0), readl(rxd + 0x4),
8302                        readl(rxd + 0x8), readl(rxd + 0xc));
8303         }
8304 }
8305 #endif
8306
8307 static struct net_device_stats *tg3_get_stats(struct net_device *);
8308 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8309
8310 static int tg3_close(struct net_device *dev)
8311 {
8312         struct tg3 *tp = netdev_priv(dev);
8313
8314         napi_disable(&tp->napi);
8315         cancel_work_sync(&tp->reset_task);
8316
8317         netif_stop_queue(dev);
8318
8319         del_timer_sync(&tp->timer);
8320
8321         tg3_full_lock(tp, 1);
8322 #if 0
8323         tg3_dump_state(tp);
8324 #endif
8325
8326         tg3_disable_ints(tp);
8327
8328         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8329         tg3_free_rings(tp);
8330         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8331
8332         tg3_full_unlock(tp);
8333
8334         free_irq(tp->pdev->irq, dev);
8335         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8336                 pci_disable_msi(tp->pdev);
8337                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8338         }
8339
8340         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8341                sizeof(tp->net_stats_prev));
8342         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8343                sizeof(tp->estats_prev));
8344
8345         tg3_free_consistent(tp);
8346
8347         tg3_set_power_state(tp, PCI_D3hot);
8348
8349         netif_carrier_off(tp->dev);
8350
8351         return 0;
8352 }
8353
8354 static inline unsigned long get_stat64(tg3_stat64_t *val)
8355 {
8356         unsigned long ret;
8357
8358 #if (BITS_PER_LONG == 32)
8359         ret = val->low;
8360 #else
8361         ret = ((u64)val->high << 32) | ((u64)val->low);
8362 #endif
8363         return ret;
8364 }
8365
8366 static unsigned long calc_crc_errors(struct tg3 *tp)
8367 {
8368         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8369
8370         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8371             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8372              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8373                 u32 val;
8374
8375                 spin_lock_bh(&tp->lock);
8376                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8377                         tg3_writephy(tp, MII_TG3_TEST1,
8378                                      val | MII_TG3_TEST1_CRC_EN);
8379                         tg3_readphy(tp, 0x14, &val);
8380                 } else
8381                         val = 0;
8382                 spin_unlock_bh(&tp->lock);
8383
8384                 tp->phy_crc_errors += val;
8385
8386                 return tp->phy_crc_errors;
8387         }
8388
8389         return get_stat64(&hw_stats->rx_fcs_errors);
8390 }
8391
8392 #define ESTAT_ADD(member) \
8393         estats->member =        old_estats->member + \
8394                                 get_stat64(&hw_stats->member)
8395
8396 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8397 {
8398         struct tg3_ethtool_stats *estats = &tp->estats;
8399         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8400         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8401
8402         if (!hw_stats)
8403                 return old_estats;
8404
8405         ESTAT_ADD(rx_octets);
8406         ESTAT_ADD(rx_fragments);
8407         ESTAT_ADD(rx_ucast_packets);
8408         ESTAT_ADD(rx_mcast_packets);
8409         ESTAT_ADD(rx_bcast_packets);
8410         ESTAT_ADD(rx_fcs_errors);
8411         ESTAT_ADD(rx_align_errors);
8412         ESTAT_ADD(rx_xon_pause_rcvd);
8413         ESTAT_ADD(rx_xoff_pause_rcvd);
8414         ESTAT_ADD(rx_mac_ctrl_rcvd);
8415         ESTAT_ADD(rx_xoff_entered);
8416         ESTAT_ADD(rx_frame_too_long_errors);
8417         ESTAT_ADD(rx_jabbers);
8418         ESTAT_ADD(rx_undersize_packets);
8419         ESTAT_ADD(rx_in_length_errors);
8420         ESTAT_ADD(rx_out_length_errors);
8421         ESTAT_ADD(rx_64_or_less_octet_packets);
8422         ESTAT_ADD(rx_65_to_127_octet_packets);
8423         ESTAT_ADD(rx_128_to_255_octet_packets);
8424         ESTAT_ADD(rx_256_to_511_octet_packets);
8425         ESTAT_ADD(rx_512_to_1023_octet_packets);
8426         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8427         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8428         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8429         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8430         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8431
8432         ESTAT_ADD(tx_octets);
8433         ESTAT_ADD(tx_collisions);
8434         ESTAT_ADD(tx_xon_sent);
8435         ESTAT_ADD(tx_xoff_sent);
8436         ESTAT_ADD(tx_flow_control);
8437         ESTAT_ADD(tx_mac_errors);
8438         ESTAT_ADD(tx_single_collisions);
8439         ESTAT_ADD(tx_mult_collisions);
8440         ESTAT_ADD(tx_deferred);
8441         ESTAT_ADD(tx_excessive_collisions);
8442         ESTAT_ADD(tx_late_collisions);
8443         ESTAT_ADD(tx_collide_2times);
8444         ESTAT_ADD(tx_collide_3times);
8445         ESTAT_ADD(tx_collide_4times);
8446         ESTAT_ADD(tx_collide_5times);
8447         ESTAT_ADD(tx_collide_6times);
8448         ESTAT_ADD(tx_collide_7times);
8449         ESTAT_ADD(tx_collide_8times);
8450         ESTAT_ADD(tx_collide_9times);
8451         ESTAT_ADD(tx_collide_10times);
8452         ESTAT_ADD(tx_collide_11times);
8453         ESTAT_ADD(tx_collide_12times);
8454         ESTAT_ADD(tx_collide_13times);
8455         ESTAT_ADD(tx_collide_14times);
8456         ESTAT_ADD(tx_collide_15times);
8457         ESTAT_ADD(tx_ucast_packets);
8458         ESTAT_ADD(tx_mcast_packets);
8459         ESTAT_ADD(tx_bcast_packets);
8460         ESTAT_ADD(tx_carrier_sense_errors);
8461         ESTAT_ADD(tx_discards);
8462         ESTAT_ADD(tx_errors);
8463
8464         ESTAT_ADD(dma_writeq_full);
8465         ESTAT_ADD(dma_write_prioq_full);
8466         ESTAT_ADD(rxbds_empty);
8467         ESTAT_ADD(rx_discards);
8468         ESTAT_ADD(rx_errors);
8469         ESTAT_ADD(rx_threshold_hit);
8470
8471         ESTAT_ADD(dma_readq_full);
8472         ESTAT_ADD(dma_read_prioq_full);
8473         ESTAT_ADD(tx_comp_queue_full);
8474
8475         ESTAT_ADD(ring_set_send_prod_index);
8476         ESTAT_ADD(ring_status_update);
8477         ESTAT_ADD(nic_irqs);
8478         ESTAT_ADD(nic_avoided_irqs);
8479         ESTAT_ADD(nic_tx_threshold_hit);
8480
8481         return estats;
8482 }
8483
8484 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8485 {
8486         struct tg3 *tp = netdev_priv(dev);
8487         struct net_device_stats *stats = &tp->net_stats;
8488         struct net_device_stats *old_stats = &tp->net_stats_prev;
8489         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8490
8491         if (!hw_stats)
8492                 return old_stats;
8493
8494         stats->rx_packets = old_stats->rx_packets +
8495                 get_stat64(&hw_stats->rx_ucast_packets) +
8496                 get_stat64(&hw_stats->rx_mcast_packets) +
8497                 get_stat64(&hw_stats->rx_bcast_packets);
8498
8499         stats->tx_packets = old_stats->tx_packets +
8500                 get_stat64(&hw_stats->tx_ucast_packets) +
8501                 get_stat64(&hw_stats->tx_mcast_packets) +
8502                 get_stat64(&hw_stats->tx_bcast_packets);
8503
8504         stats->rx_bytes = old_stats->rx_bytes +
8505                 get_stat64(&hw_stats->rx_octets);
8506         stats->tx_bytes = old_stats->tx_bytes +
8507                 get_stat64(&hw_stats->tx_octets);
8508
8509         stats->rx_errors = old_stats->rx_errors +
8510                 get_stat64(&hw_stats->rx_errors);
8511         stats->tx_errors = old_stats->tx_errors +
8512                 get_stat64(&hw_stats->tx_errors) +
8513                 get_stat64(&hw_stats->tx_mac_errors) +
8514                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8515                 get_stat64(&hw_stats->tx_discards);
8516
8517         stats->multicast = old_stats->multicast +
8518                 get_stat64(&hw_stats->rx_mcast_packets);
8519         stats->collisions = old_stats->collisions +
8520                 get_stat64(&hw_stats->tx_collisions);
8521
8522         stats->rx_length_errors = old_stats->rx_length_errors +
8523                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8524                 get_stat64(&hw_stats->rx_undersize_packets);
8525
8526         stats->rx_over_errors = old_stats->rx_over_errors +
8527                 get_stat64(&hw_stats->rxbds_empty);
8528         stats->rx_frame_errors = old_stats->rx_frame_errors +
8529                 get_stat64(&hw_stats->rx_align_errors);
8530         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8531                 get_stat64(&hw_stats->tx_discards);
8532         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8533                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8534
8535         stats->rx_crc_errors = old_stats->rx_crc_errors +
8536                 calc_crc_errors(tp);
8537
8538         stats->rx_missed_errors = old_stats->rx_missed_errors +
8539                 get_stat64(&hw_stats->rx_discards);
8540
8541         return stats;
8542 }
8543
8544 static inline u32 calc_crc(unsigned char *buf, int len)
8545 {
8546         u32 reg;
8547         u32 tmp;
8548         int j, k;
8549
8550         reg = 0xffffffff;
8551
8552         for (j = 0; j < len; j++) {
8553                 reg ^= buf[j];
8554
8555                 for (k = 0; k < 8; k++) {
8556                         tmp = reg & 0x01;
8557
8558                         reg >>= 1;
8559
8560                         if (tmp) {
8561                                 reg ^= 0xedb88320;
8562                         }
8563                 }
8564         }
8565
8566         return ~reg;
8567 }
8568
8569 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8570 {
8571         /* accept or reject all multicast frames */
8572         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8573         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8574         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8575         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8576 }
8577
8578 static void __tg3_set_rx_mode(struct net_device *dev)
8579 {
8580         struct tg3 *tp = netdev_priv(dev);
8581         u32 rx_mode;
8582
8583         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8584                                   RX_MODE_KEEP_VLAN_TAG);
8585
8586         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8587          * flag clear.
8588          */
8589 #if TG3_VLAN_TAG_USED
8590         if (!tp->vlgrp &&
8591             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8592                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8593 #else
8594         /* By definition, VLAN is disabled always in this
8595          * case.
8596          */
8597         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8598                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8599 #endif
8600
8601         if (dev->flags & IFF_PROMISC) {
8602                 /* Promiscuous mode. */
8603                 rx_mode |= RX_MODE_PROMISC;
8604         } else if (dev->flags & IFF_ALLMULTI) {
8605                 /* Accept all multicast. */
8606                 tg3_set_multi (tp, 1);
8607         } else if (dev->mc_count < 1) {
8608                 /* Reject all multicast. */
8609                 tg3_set_multi (tp, 0);
8610         } else {
8611                 /* Accept one or more multicast(s). */
8612                 struct dev_mc_list *mclist;
8613                 unsigned int i;
8614                 u32 mc_filter[4] = { 0, };
8615                 u32 regidx;
8616                 u32 bit;
8617                 u32 crc;
8618
8619                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8620                      i++, mclist = mclist->next) {
8621
8622                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8623                         bit = ~crc & 0x7f;
8624                         regidx = (bit & 0x60) >> 5;
8625                         bit &= 0x1f;
8626                         mc_filter[regidx] |= (1 << bit);
8627                 }
8628
8629                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8630                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8631                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8632                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8633         }
8634
8635         if (rx_mode != tp->rx_mode) {
8636                 tp->rx_mode = rx_mode;
8637                 tw32_f(MAC_RX_MODE, rx_mode);
8638                 udelay(10);
8639         }
8640 }
8641
8642 static void tg3_set_rx_mode(struct net_device *dev)
8643 {
8644         struct tg3 *tp = netdev_priv(dev);
8645
8646         if (!netif_running(dev))
8647                 return;
8648
8649         tg3_full_lock(tp, 0);
8650         __tg3_set_rx_mode(dev);
8651         tg3_full_unlock(tp);
8652 }
8653
8654 #define TG3_REGDUMP_LEN         (32 * 1024)
8655
8656 static int tg3_get_regs_len(struct net_device *dev)
8657 {
8658         return TG3_REGDUMP_LEN;
8659 }
8660
8661 static void tg3_get_regs(struct net_device *dev,
8662                 struct ethtool_regs *regs, void *_p)
8663 {
8664         u32 *p = _p;
8665         struct tg3 *tp = netdev_priv(dev);
8666         u8 *orig_p = _p;
8667         int i;
8668
8669         regs->version = 0;
8670
8671         memset(p, 0, TG3_REGDUMP_LEN);
8672
8673         if (tp->link_config.phy_is_low_power)
8674                 return;
8675
8676         tg3_full_lock(tp, 0);
8677
8678 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8679 #define GET_REG32_LOOP(base,len)                \
8680 do {    p = (u32 *)(orig_p + (base));           \
8681         for (i = 0; i < len; i += 4)            \
8682                 __GET_REG32((base) + i);        \
8683 } while (0)
8684 #define GET_REG32_1(reg)                        \
8685 do {    p = (u32 *)(orig_p + (reg));            \
8686         __GET_REG32((reg));                     \
8687 } while (0)
8688
8689         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8690         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8691         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8692         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8693         GET_REG32_1(SNDDATAC_MODE);
8694         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8695         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8696         GET_REG32_1(SNDBDC_MODE);
8697         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8698         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8699         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8700         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8701         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8702         GET_REG32_1(RCVDCC_MODE);
8703         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8704         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8705         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8706         GET_REG32_1(MBFREE_MODE);
8707         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8708         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8709         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8710         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8711         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8712         GET_REG32_1(RX_CPU_MODE);
8713         GET_REG32_1(RX_CPU_STATE);
8714         GET_REG32_1(RX_CPU_PGMCTR);
8715         GET_REG32_1(RX_CPU_HWBKPT);
8716         GET_REG32_1(TX_CPU_MODE);
8717         GET_REG32_1(TX_CPU_STATE);
8718         GET_REG32_1(TX_CPU_PGMCTR);
8719         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8720         GET_REG32_LOOP(FTQ_RESET, 0x120);
8721         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8722         GET_REG32_1(DMAC_MODE);
8723         GET_REG32_LOOP(GRC_MODE, 0x4c);
8724         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8725                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8726
8727 #undef __GET_REG32
8728 #undef GET_REG32_LOOP
8729 #undef GET_REG32_1
8730
8731         tg3_full_unlock(tp);
8732 }
8733
8734 static int tg3_get_eeprom_len(struct net_device *dev)
8735 {
8736         struct tg3 *tp = netdev_priv(dev);
8737
8738         return tp->nvram_size;
8739 }
8740
8741 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8742 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8743 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8744
8745 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8746 {
8747         struct tg3 *tp = netdev_priv(dev);
8748         int ret;
8749         u8  *pd;
8750         u32 i, offset, len, b_offset, b_count;
8751         __le32 val;
8752
8753         if (tp->link_config.phy_is_low_power)
8754                 return -EAGAIN;
8755
8756         offset = eeprom->offset;
8757         len = eeprom->len;
8758         eeprom->len = 0;
8759
8760         eeprom->magic = TG3_EEPROM_MAGIC;
8761
8762         if (offset & 3) {
8763                 /* adjustments to start on required 4 byte boundary */
8764                 b_offset = offset & 3;
8765                 b_count = 4 - b_offset;
8766                 if (b_count > len) {
8767                         /* i.e. offset=1 len=2 */
8768                         b_count = len;
8769                 }
8770                 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
8771                 if (ret)
8772                         return ret;
8773                 memcpy(data, ((char*)&val) + b_offset, b_count);
8774                 len -= b_count;
8775                 offset += b_count;
8776                 eeprom->len += b_count;
8777         }
8778
8779         /* read bytes upto the last 4 byte boundary */
8780         pd = &data[eeprom->len];
8781         for (i = 0; i < (len - (len & 3)); i += 4) {
8782                 ret = tg3_nvram_read_le(tp, offset + i, &val);
8783                 if (ret) {
8784                         eeprom->len += i;
8785                         return ret;
8786                 }
8787                 memcpy(pd + i, &val, 4);
8788         }
8789         eeprom->len += i;
8790
8791         if (len & 3) {
8792                 /* read last bytes not ending on 4 byte boundary */
8793                 pd = &data[eeprom->len];
8794                 b_count = len & 3;
8795                 b_offset = offset + len - b_count;
8796                 ret = tg3_nvram_read_le(tp, b_offset, &val);
8797                 if (ret)
8798                         return ret;
8799                 memcpy(pd, &val, b_count);
8800                 eeprom->len += b_count;
8801         }
8802         return 0;
8803 }
8804
8805 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8806
8807 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8808 {
8809         struct tg3 *tp = netdev_priv(dev);
8810         int ret;
8811         u32 offset, len, b_offset, odd_len;
8812         u8 *buf;
8813         __le32 start, end;
8814
8815         if (tp->link_config.phy_is_low_power)
8816                 return -EAGAIN;
8817
8818         if (eeprom->magic != TG3_EEPROM_MAGIC)
8819                 return -EINVAL;
8820
8821         offset = eeprom->offset;
8822         len = eeprom->len;
8823
8824         if ((b_offset = (offset & 3))) {
8825                 /* adjustments to start on required 4 byte boundary */
8826                 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
8827                 if (ret)
8828                         return ret;
8829                 len += b_offset;
8830                 offset &= ~3;
8831                 if (len < 4)
8832                         len = 4;
8833         }
8834
8835         odd_len = 0;
8836         if (len & 3) {
8837                 /* adjustments to end on required 4 byte boundary */
8838                 odd_len = 1;
8839                 len = (len + 3) & ~3;
8840                 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
8841                 if (ret)
8842                         return ret;
8843         }
8844
8845         buf = data;
8846         if (b_offset || odd_len) {
8847                 buf = kmalloc(len, GFP_KERNEL);
8848                 if (!buf)
8849                         return -ENOMEM;
8850                 if (b_offset)
8851                         memcpy(buf, &start, 4);
8852                 if (odd_len)
8853                         memcpy(buf+len-4, &end, 4);
8854                 memcpy(buf + b_offset, data, eeprom->len);
8855         }
8856
8857         ret = tg3_nvram_write_block(tp, offset, len, buf);
8858
8859         if (buf != data)
8860                 kfree(buf);
8861
8862         return ret;
8863 }
8864
8865 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8866 {
8867         struct tg3 *tp = netdev_priv(dev);
8868
8869         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8870                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8871                         return -EAGAIN;
8872                 return phy_ethtool_gset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8873         }
8874
8875         cmd->supported = (SUPPORTED_Autoneg);
8876
8877         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8878                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8879                                    SUPPORTED_1000baseT_Full);
8880
8881         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8882                 cmd->supported |= (SUPPORTED_100baseT_Half |
8883                                   SUPPORTED_100baseT_Full |
8884                                   SUPPORTED_10baseT_Half |
8885                                   SUPPORTED_10baseT_Full |
8886                                   SUPPORTED_TP);
8887                 cmd->port = PORT_TP;
8888         } else {
8889                 cmd->supported |= SUPPORTED_FIBRE;
8890                 cmd->port = PORT_FIBRE;
8891         }
8892
8893         cmd->advertising = tp->link_config.advertising;
8894         if (netif_running(dev)) {
8895                 cmd->speed = tp->link_config.active_speed;
8896                 cmd->duplex = tp->link_config.active_duplex;
8897         }
8898         cmd->phy_address = PHY_ADDR;
8899         cmd->transceiver = 0;
8900         cmd->autoneg = tp->link_config.autoneg;
8901         cmd->maxtxpkt = 0;
8902         cmd->maxrxpkt = 0;
8903         return 0;
8904 }
8905
8906 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8907 {
8908         struct tg3 *tp = netdev_priv(dev);
8909
8910         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8911                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8912                         return -EAGAIN;
8913                 return phy_ethtool_sset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8914         }
8915
8916         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8917                 /* These are the only valid advertisement bits allowed.  */
8918                 if (cmd->autoneg == AUTONEG_ENABLE &&
8919                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8920                                           ADVERTISED_1000baseT_Full |
8921                                           ADVERTISED_Autoneg |
8922                                           ADVERTISED_FIBRE)))
8923                         return -EINVAL;
8924                 /* Fiber can only do SPEED_1000.  */
8925                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8926                          (cmd->speed != SPEED_1000))
8927                         return -EINVAL;
8928         /* Copper cannot force SPEED_1000.  */
8929         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8930                    (cmd->speed == SPEED_1000))
8931                 return -EINVAL;
8932         else if ((cmd->speed == SPEED_1000) &&
8933                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8934                 return -EINVAL;
8935
8936         tg3_full_lock(tp, 0);
8937
8938         tp->link_config.autoneg = cmd->autoneg;
8939         if (cmd->autoneg == AUTONEG_ENABLE) {
8940                 tp->link_config.advertising = (cmd->advertising |
8941                                               ADVERTISED_Autoneg);
8942                 tp->link_config.speed = SPEED_INVALID;
8943                 tp->link_config.duplex = DUPLEX_INVALID;
8944         } else {
8945                 tp->link_config.advertising = 0;
8946                 tp->link_config.speed = cmd->speed;
8947                 tp->link_config.duplex = cmd->duplex;
8948         }
8949
8950         tp->link_config.orig_speed = tp->link_config.speed;
8951         tp->link_config.orig_duplex = tp->link_config.duplex;
8952         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8953
8954         if (netif_running(dev))
8955                 tg3_setup_phy(tp, 1);
8956
8957         tg3_full_unlock(tp);
8958
8959         return 0;
8960 }
8961
8962 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8963 {
8964         struct tg3 *tp = netdev_priv(dev);
8965
8966         strcpy(info->driver, DRV_MODULE_NAME);
8967         strcpy(info->version, DRV_MODULE_VERSION);
8968         strcpy(info->fw_version, tp->fw_ver);
8969         strcpy(info->bus_info, pci_name(tp->pdev));
8970 }
8971
8972 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8973 {
8974         struct tg3 *tp = netdev_priv(dev);
8975
8976         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8977                 wol->supported = WAKE_MAGIC;
8978         else
8979                 wol->supported = 0;
8980         wol->wolopts = 0;
8981         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8982                 wol->wolopts = WAKE_MAGIC;
8983         memset(&wol->sopass, 0, sizeof(wol->sopass));
8984 }
8985
8986 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8987 {
8988         struct tg3 *tp = netdev_priv(dev);
8989
8990         if (wol->wolopts & ~WAKE_MAGIC)
8991                 return -EINVAL;
8992         if ((wol->wolopts & WAKE_MAGIC) &&
8993             !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8994                 return -EINVAL;
8995
8996         spin_lock_bh(&tp->lock);
8997         if (wol->wolopts & WAKE_MAGIC)
8998                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8999         else
9000                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9001         spin_unlock_bh(&tp->lock);
9002
9003         return 0;
9004 }
9005
9006 static u32 tg3_get_msglevel(struct net_device *dev)
9007 {
9008         struct tg3 *tp = netdev_priv(dev);
9009         return tp->msg_enable;
9010 }
9011
9012 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9013 {
9014         struct tg3 *tp = netdev_priv(dev);
9015         tp->msg_enable = value;
9016 }
9017
9018 static int tg3_set_tso(struct net_device *dev, u32 value)
9019 {
9020         struct tg3 *tp = netdev_priv(dev);
9021
9022         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9023                 if (value)
9024                         return -EINVAL;
9025                 return 0;
9026         }
9027         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
9028             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
9029                 if (value) {
9030                         dev->features |= NETIF_F_TSO6;
9031                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9032                                 dev->features |= NETIF_F_TSO_ECN;
9033                 } else
9034                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9035         }
9036         return ethtool_op_set_tso(dev, value);
9037 }
9038
9039 static int tg3_nway_reset(struct net_device *dev)
9040 {
9041         struct tg3 *tp = netdev_priv(dev);
9042         int r;
9043
9044         if (!netif_running(dev))
9045                 return -EAGAIN;
9046
9047         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9048                 return -EINVAL;
9049
9050         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9051                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9052                         return -EAGAIN;
9053                 r = phy_start_aneg(tp->mdio_bus.phy_map[PHY_ADDR]);
9054         } else {
9055                 u32 bmcr;
9056
9057                 spin_lock_bh(&tp->lock);
9058                 r = -EINVAL;
9059                 tg3_readphy(tp, MII_BMCR, &bmcr);
9060                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9061                     ((bmcr & BMCR_ANENABLE) ||
9062                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9063                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9064                                                    BMCR_ANENABLE);
9065                         r = 0;
9066                 }
9067                 spin_unlock_bh(&tp->lock);
9068         }
9069
9070         return r;
9071 }
9072
9073 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9074 {
9075         struct tg3 *tp = netdev_priv(dev);
9076
9077         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9078         ering->rx_mini_max_pending = 0;
9079         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9080                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9081         else
9082                 ering->rx_jumbo_max_pending = 0;
9083
9084         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9085
9086         ering->rx_pending = tp->rx_pending;
9087         ering->rx_mini_pending = 0;
9088         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9089                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9090         else
9091                 ering->rx_jumbo_pending = 0;
9092
9093         ering->tx_pending = tp->tx_pending;
9094 }
9095
9096 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9097 {
9098         struct tg3 *tp = netdev_priv(dev);
9099         int irq_sync = 0, err = 0;
9100
9101         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9102             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9103             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9104             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9105             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9106              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9107                 return -EINVAL;
9108
9109         if (netif_running(dev)) {
9110                 tg3_phy_stop(tp);
9111                 tg3_netif_stop(tp);
9112                 irq_sync = 1;
9113         }
9114
9115         tg3_full_lock(tp, irq_sync);
9116
9117         tp->rx_pending = ering->rx_pending;
9118
9119         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9120             tp->rx_pending > 63)
9121                 tp->rx_pending = 63;
9122         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9123         tp->tx_pending = ering->tx_pending;
9124
9125         if (netif_running(dev)) {
9126                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9127                 err = tg3_restart_hw(tp, 1);
9128                 if (!err)
9129                         tg3_netif_start(tp);
9130         }
9131
9132         tg3_full_unlock(tp);
9133
9134         if (irq_sync && !err)
9135                 tg3_phy_start(tp);
9136
9137         return err;
9138 }
9139
9140 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9141 {
9142         struct tg3 *tp = netdev_priv(dev);
9143
9144         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9145
9146         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
9147                 epause->rx_pause = 1;
9148         else
9149                 epause->rx_pause = 0;
9150
9151         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
9152                 epause->tx_pause = 1;
9153         else
9154                 epause->tx_pause = 0;
9155 }
9156
9157 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9158 {
9159         struct tg3 *tp = netdev_priv(dev);
9160         int err = 0;
9161
9162         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9163                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9164                         return -EAGAIN;
9165
9166                 if (epause->autoneg) {
9167                         u32 newadv;
9168                         struct phy_device *phydev;
9169
9170                         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
9171
9172                         if (epause->rx_pause) {
9173                                 if (epause->tx_pause)
9174                                         newadv = ADVERTISED_Pause;
9175                                 else
9176                                         newadv = ADVERTISED_Pause |
9177                                                  ADVERTISED_Asym_Pause;
9178                         } else if (epause->tx_pause) {
9179                                 newadv = ADVERTISED_Asym_Pause;
9180                         } else
9181                                 newadv = 0;
9182
9183                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9184                                 u32 oldadv = phydev->advertising &
9185                                              (ADVERTISED_Pause |
9186                                               ADVERTISED_Asym_Pause);
9187                                 if (oldadv != newadv) {
9188                                         phydev->advertising &=
9189                                                 ~(ADVERTISED_Pause |
9190                                                   ADVERTISED_Asym_Pause);
9191                                         phydev->advertising |= newadv;
9192                                         err = phy_start_aneg(phydev);
9193                                 }
9194                         } else {
9195                                 tp->link_config.advertising &=
9196                                                 ~(ADVERTISED_Pause |
9197                                                   ADVERTISED_Asym_Pause);
9198                                 tp->link_config.advertising |= newadv;
9199                         }
9200                 } else {
9201                         if (epause->rx_pause)
9202                                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9203                         else
9204                                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9205
9206                         if (epause->tx_pause)
9207                                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9208                         else
9209                                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9210
9211                         if (netif_running(dev))
9212                                 tg3_setup_flow_control(tp, 0, 0);
9213                 }
9214         } else {
9215                 int irq_sync = 0;
9216
9217                 if (netif_running(dev)) {
9218                         tg3_netif_stop(tp);
9219                         irq_sync = 1;
9220                 }
9221
9222                 tg3_full_lock(tp, irq_sync);
9223
9224                 if (epause->autoneg)
9225                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9226                 else
9227                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9228                 if (epause->rx_pause)
9229                         tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9230                 else
9231                         tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9232                 if (epause->tx_pause)
9233                         tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9234                 else
9235                         tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9236
9237                 if (netif_running(dev)) {
9238                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9239                         err = tg3_restart_hw(tp, 1);
9240                         if (!err)
9241                                 tg3_netif_start(tp);
9242                 }
9243
9244                 tg3_full_unlock(tp);
9245         }
9246
9247         return err;
9248 }
9249
9250 static u32 tg3_get_rx_csum(struct net_device *dev)
9251 {
9252         struct tg3 *tp = netdev_priv(dev);
9253         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9254 }
9255
9256 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9257 {
9258         struct tg3 *tp = netdev_priv(dev);
9259
9260         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9261                 if (data != 0)
9262                         return -EINVAL;
9263                 return 0;
9264         }
9265
9266         spin_lock_bh(&tp->lock);
9267         if (data)
9268                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9269         else
9270                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9271         spin_unlock_bh(&tp->lock);
9272
9273         return 0;
9274 }
9275
9276 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9277 {
9278         struct tg3 *tp = netdev_priv(dev);
9279
9280         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9281                 if (data != 0)
9282                         return -EINVAL;
9283                 return 0;
9284         }
9285
9286         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9287             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9288             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9289             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9290                 ethtool_op_set_tx_ipv6_csum(dev, data);
9291         else
9292                 ethtool_op_set_tx_csum(dev, data);
9293
9294         return 0;
9295 }
9296
9297 static int tg3_get_sset_count (struct net_device *dev, int sset)
9298 {
9299         switch (sset) {
9300         case ETH_SS_TEST:
9301                 return TG3_NUM_TEST;
9302         case ETH_SS_STATS:
9303                 return TG3_NUM_STATS;
9304         default:
9305                 return -EOPNOTSUPP;
9306         }
9307 }
9308
9309 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9310 {
9311         switch (stringset) {
9312         case ETH_SS_STATS:
9313                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9314                 break;
9315         case ETH_SS_TEST:
9316                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9317                 break;
9318         default:
9319                 WARN_ON(1);     /* we need a WARN() */
9320                 break;
9321         }
9322 }
9323
9324 static int tg3_phys_id(struct net_device *dev, u32 data)
9325 {
9326         struct tg3 *tp = netdev_priv(dev);
9327         int i;
9328
9329         if (!netif_running(tp->dev))
9330                 return -EAGAIN;
9331
9332         if (data == 0)
9333                 data = UINT_MAX / 2;
9334
9335         for (i = 0; i < (data * 2); i++) {
9336                 if ((i % 2) == 0)
9337                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9338                                            LED_CTRL_1000MBPS_ON |
9339                                            LED_CTRL_100MBPS_ON |
9340                                            LED_CTRL_10MBPS_ON |
9341                                            LED_CTRL_TRAFFIC_OVERRIDE |
9342                                            LED_CTRL_TRAFFIC_BLINK |
9343                                            LED_CTRL_TRAFFIC_LED);
9344
9345                 else
9346                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9347                                            LED_CTRL_TRAFFIC_OVERRIDE);
9348
9349                 if (msleep_interruptible(500))
9350                         break;
9351         }
9352         tw32(MAC_LED_CTRL, tp->led_ctrl);
9353         return 0;
9354 }
9355
9356 static void tg3_get_ethtool_stats (struct net_device *dev,
9357                                    struct ethtool_stats *estats, u64 *tmp_stats)
9358 {
9359         struct tg3 *tp = netdev_priv(dev);
9360         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9361 }
9362
9363 #define NVRAM_TEST_SIZE 0x100
9364 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9365 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9366 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9367 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9368 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9369
9370 static int tg3_test_nvram(struct tg3 *tp)
9371 {
9372         u32 csum, magic;
9373         __le32 *buf;
9374         int i, j, k, err = 0, size;
9375
9376         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9377                 return -EIO;
9378
9379         if (magic == TG3_EEPROM_MAGIC)
9380                 size = NVRAM_TEST_SIZE;
9381         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9382                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9383                     TG3_EEPROM_SB_FORMAT_1) {
9384                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9385                         case TG3_EEPROM_SB_REVISION_0:
9386                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9387                                 break;
9388                         case TG3_EEPROM_SB_REVISION_2:
9389                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9390                                 break;
9391                         case TG3_EEPROM_SB_REVISION_3:
9392                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9393                                 break;
9394                         default:
9395                                 return 0;
9396                         }
9397                 } else
9398                         return 0;
9399         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9400                 size = NVRAM_SELFBOOT_HW_SIZE;
9401         else
9402                 return -EIO;
9403
9404         buf = kmalloc(size, GFP_KERNEL);
9405         if (buf == NULL)
9406                 return -ENOMEM;
9407
9408         err = -EIO;
9409         for (i = 0, j = 0; i < size; i += 4, j++) {
9410                 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
9411                         break;
9412         }
9413         if (i < size)
9414                 goto out;
9415
9416         /* Selfboot format */
9417         magic = swab32(le32_to_cpu(buf[0]));
9418         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9419             TG3_EEPROM_MAGIC_FW) {
9420                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9421
9422                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9423                     TG3_EEPROM_SB_REVISION_2) {
9424                         /* For rev 2, the csum doesn't include the MBA. */
9425                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9426                                 csum8 += buf8[i];
9427                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9428                                 csum8 += buf8[i];
9429                 } else {
9430                         for (i = 0; i < size; i++)
9431                                 csum8 += buf8[i];
9432                 }
9433
9434                 if (csum8 == 0) {
9435                         err = 0;
9436                         goto out;
9437                 }
9438
9439                 err = -EIO;
9440                 goto out;
9441         }
9442
9443         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9444             TG3_EEPROM_MAGIC_HW) {
9445                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9446                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9447                 u8 *buf8 = (u8 *) buf;
9448
9449                 /* Separate the parity bits and the data bytes.  */
9450                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9451                         if ((i == 0) || (i == 8)) {
9452                                 int l;
9453                                 u8 msk;
9454
9455                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9456                                         parity[k++] = buf8[i] & msk;
9457                                 i++;
9458                         }
9459                         else if (i == 16) {
9460                                 int l;
9461                                 u8 msk;
9462
9463                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9464                                         parity[k++] = buf8[i] & msk;
9465                                 i++;
9466
9467                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9468                                         parity[k++] = buf8[i] & msk;
9469                                 i++;
9470                         }
9471                         data[j++] = buf8[i];
9472                 }
9473
9474                 err = -EIO;
9475                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9476                         u8 hw8 = hweight8(data[i]);
9477
9478                         if ((hw8 & 0x1) && parity[i])
9479                                 goto out;
9480                         else if (!(hw8 & 0x1) && !parity[i])
9481                                 goto out;
9482                 }
9483                 err = 0;
9484                 goto out;
9485         }
9486
9487         /* Bootstrap checksum at offset 0x10 */
9488         csum = calc_crc((unsigned char *) buf, 0x10);
9489         if(csum != le32_to_cpu(buf[0x10/4]))
9490                 goto out;
9491
9492         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9493         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9494         if (csum != le32_to_cpu(buf[0xfc/4]))
9495                  goto out;
9496
9497         err = 0;
9498
9499 out:
9500         kfree(buf);
9501         return err;
9502 }
9503
9504 #define TG3_SERDES_TIMEOUT_SEC  2
9505 #define TG3_COPPER_TIMEOUT_SEC  6
9506
9507 static int tg3_test_link(struct tg3 *tp)
9508 {
9509         int i, max;
9510
9511         if (!netif_running(tp->dev))
9512                 return -ENODEV;
9513
9514         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9515                 max = TG3_SERDES_TIMEOUT_SEC;
9516         else
9517                 max = TG3_COPPER_TIMEOUT_SEC;
9518
9519         for (i = 0; i < max; i++) {
9520                 if (netif_carrier_ok(tp->dev))
9521                         return 0;
9522
9523                 if (msleep_interruptible(1000))
9524                         break;
9525         }
9526
9527         return -EIO;
9528 }
9529
9530 /* Only test the commonly used registers */
9531 static int tg3_test_registers(struct tg3 *tp)
9532 {
9533         int i, is_5705, is_5750;
9534         u32 offset, read_mask, write_mask, val, save_val, read_val;
9535         static struct {
9536                 u16 offset;
9537                 u16 flags;
9538 #define TG3_FL_5705     0x1
9539 #define TG3_FL_NOT_5705 0x2
9540 #define TG3_FL_NOT_5788 0x4
9541 #define TG3_FL_NOT_5750 0x8
9542                 u32 read_mask;
9543                 u32 write_mask;
9544         } reg_tbl[] = {
9545                 /* MAC Control Registers */
9546                 { MAC_MODE, TG3_FL_NOT_5705,
9547                         0x00000000, 0x00ef6f8c },
9548                 { MAC_MODE, TG3_FL_5705,
9549                         0x00000000, 0x01ef6b8c },
9550                 { MAC_STATUS, TG3_FL_NOT_5705,
9551                         0x03800107, 0x00000000 },
9552                 { MAC_STATUS, TG3_FL_5705,
9553                         0x03800100, 0x00000000 },
9554                 { MAC_ADDR_0_HIGH, 0x0000,
9555                         0x00000000, 0x0000ffff },
9556                 { MAC_ADDR_0_LOW, 0x0000,
9557                         0x00000000, 0xffffffff },
9558                 { MAC_RX_MTU_SIZE, 0x0000,
9559                         0x00000000, 0x0000ffff },
9560                 { MAC_TX_MODE, 0x0000,
9561                         0x00000000, 0x00000070 },
9562                 { MAC_TX_LENGTHS, 0x0000,
9563                         0x00000000, 0x00003fff },
9564                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9565                         0x00000000, 0x000007fc },
9566                 { MAC_RX_MODE, TG3_FL_5705,
9567                         0x00000000, 0x000007dc },
9568                 { MAC_HASH_REG_0, 0x0000,
9569                         0x00000000, 0xffffffff },
9570                 { MAC_HASH_REG_1, 0x0000,
9571                         0x00000000, 0xffffffff },
9572                 { MAC_HASH_REG_2, 0x0000,
9573                         0x00000000, 0xffffffff },
9574                 { MAC_HASH_REG_3, 0x0000,
9575                         0x00000000, 0xffffffff },
9576
9577                 /* Receive Data and Receive BD Initiator Control Registers. */
9578                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9579                         0x00000000, 0xffffffff },
9580                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9581                         0x00000000, 0xffffffff },
9582                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9583                         0x00000000, 0x00000003 },
9584                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9585                         0x00000000, 0xffffffff },
9586                 { RCVDBDI_STD_BD+0, 0x0000,
9587                         0x00000000, 0xffffffff },
9588                 { RCVDBDI_STD_BD+4, 0x0000,
9589                         0x00000000, 0xffffffff },
9590                 { RCVDBDI_STD_BD+8, 0x0000,
9591                         0x00000000, 0xffff0002 },
9592                 { RCVDBDI_STD_BD+0xc, 0x0000,
9593                         0x00000000, 0xffffffff },
9594
9595                 /* Receive BD Initiator Control Registers. */
9596                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9597                         0x00000000, 0xffffffff },
9598                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9599                         0x00000000, 0x000003ff },
9600                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9601                         0x00000000, 0xffffffff },
9602
9603                 /* Host Coalescing Control Registers. */
9604                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9605                         0x00000000, 0x00000004 },
9606                 { HOSTCC_MODE, TG3_FL_5705,
9607                         0x00000000, 0x000000f6 },
9608                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9609                         0x00000000, 0xffffffff },
9610                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9611                         0x00000000, 0x000003ff },
9612                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9613                         0x00000000, 0xffffffff },
9614                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9615                         0x00000000, 0x000003ff },
9616                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9617                         0x00000000, 0xffffffff },
9618                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9619                         0x00000000, 0x000000ff },
9620                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9621                         0x00000000, 0xffffffff },
9622                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9623                         0x00000000, 0x000000ff },
9624                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9625                         0x00000000, 0xffffffff },
9626                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9627                         0x00000000, 0xffffffff },
9628                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9629                         0x00000000, 0xffffffff },
9630                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9631                         0x00000000, 0x000000ff },
9632                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9633                         0x00000000, 0xffffffff },
9634                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9635                         0x00000000, 0x000000ff },
9636                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9637                         0x00000000, 0xffffffff },
9638                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9639                         0x00000000, 0xffffffff },
9640                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9641                         0x00000000, 0xffffffff },
9642                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9643                         0x00000000, 0xffffffff },
9644                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9645                         0x00000000, 0xffffffff },
9646                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9647                         0xffffffff, 0x00000000 },
9648                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9649                         0xffffffff, 0x00000000 },
9650
9651                 /* Buffer Manager Control Registers. */
9652                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9653                         0x00000000, 0x007fff80 },
9654                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9655                         0x00000000, 0x007fffff },
9656                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9657                         0x00000000, 0x0000003f },
9658                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9659                         0x00000000, 0x000001ff },
9660                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9661                         0x00000000, 0x000001ff },
9662                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9663                         0xffffffff, 0x00000000 },
9664                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9665                         0xffffffff, 0x00000000 },
9666
9667                 /* Mailbox Registers */
9668                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9669                         0x00000000, 0x000001ff },
9670                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9671                         0x00000000, 0x000001ff },
9672                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9673                         0x00000000, 0x000007ff },
9674                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9675                         0x00000000, 0x000001ff },
9676
9677                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9678         };
9679
9680         is_5705 = is_5750 = 0;
9681         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9682                 is_5705 = 1;
9683                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9684                         is_5750 = 1;
9685         }
9686
9687         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9688                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9689                         continue;
9690
9691                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9692                         continue;
9693
9694                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9695                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9696                         continue;
9697
9698                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9699                         continue;
9700
9701                 offset = (u32) reg_tbl[i].offset;
9702                 read_mask = reg_tbl[i].read_mask;
9703                 write_mask = reg_tbl[i].write_mask;
9704
9705                 /* Save the original register content */
9706                 save_val = tr32(offset);
9707
9708                 /* Determine the read-only value. */
9709                 read_val = save_val & read_mask;
9710
9711                 /* Write zero to the register, then make sure the read-only bits
9712                  * are not changed and the read/write bits are all zeros.
9713                  */
9714                 tw32(offset, 0);
9715
9716                 val = tr32(offset);
9717
9718                 /* Test the read-only and read/write bits. */
9719                 if (((val & read_mask) != read_val) || (val & write_mask))
9720                         goto out;
9721
9722                 /* Write ones to all the bits defined by RdMask and WrMask, then
9723                  * make sure the read-only bits are not changed and the
9724                  * read/write bits are all ones.
9725                  */
9726                 tw32(offset, read_mask | write_mask);
9727
9728                 val = tr32(offset);
9729
9730                 /* Test the read-only bits. */
9731                 if ((val & read_mask) != read_val)
9732                         goto out;
9733
9734                 /* Test the read/write bits. */
9735                 if ((val & write_mask) != write_mask)
9736                         goto out;
9737
9738                 tw32(offset, save_val);
9739         }
9740
9741         return 0;
9742
9743 out:
9744         if (netif_msg_hw(tp))
9745                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9746                        offset);
9747         tw32(offset, save_val);
9748         return -EIO;
9749 }
9750
9751 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9752 {
9753         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9754         int i;
9755         u32 j;
9756
9757         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9758                 for (j = 0; j < len; j += 4) {
9759                         u32 val;
9760
9761                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9762                         tg3_read_mem(tp, offset + j, &val);
9763                         if (val != test_pattern[i])
9764                                 return -EIO;
9765                 }
9766         }
9767         return 0;
9768 }
9769
9770 static int tg3_test_memory(struct tg3 *tp)
9771 {
9772         static struct mem_entry {
9773                 u32 offset;
9774                 u32 len;
9775         } mem_tbl_570x[] = {
9776                 { 0x00000000, 0x00b50},
9777                 { 0x00002000, 0x1c000},
9778                 { 0xffffffff, 0x00000}
9779         }, mem_tbl_5705[] = {
9780                 { 0x00000100, 0x0000c},
9781                 { 0x00000200, 0x00008},
9782                 { 0x00004000, 0x00800},
9783                 { 0x00006000, 0x01000},
9784                 { 0x00008000, 0x02000},
9785                 { 0x00010000, 0x0e000},
9786                 { 0xffffffff, 0x00000}
9787         }, mem_tbl_5755[] = {
9788                 { 0x00000200, 0x00008},
9789                 { 0x00004000, 0x00800},
9790                 { 0x00006000, 0x00800},
9791                 { 0x00008000, 0x02000},
9792                 { 0x00010000, 0x0c000},
9793                 { 0xffffffff, 0x00000}
9794         }, mem_tbl_5906[] = {
9795                 { 0x00000200, 0x00008},
9796                 { 0x00004000, 0x00400},
9797                 { 0x00006000, 0x00400},
9798                 { 0x00008000, 0x01000},
9799                 { 0x00010000, 0x01000},
9800                 { 0xffffffff, 0x00000}
9801         };
9802         struct mem_entry *mem_tbl;
9803         int err = 0;
9804         int i;
9805
9806         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9807                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9808                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9809                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9810                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9811                         mem_tbl = mem_tbl_5755;
9812                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9813                         mem_tbl = mem_tbl_5906;
9814                 else
9815                         mem_tbl = mem_tbl_5705;
9816         } else
9817                 mem_tbl = mem_tbl_570x;
9818
9819         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9820                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9821                     mem_tbl[i].len)) != 0)
9822                         break;
9823         }
9824
9825         return err;
9826 }
9827
9828 #define TG3_MAC_LOOPBACK        0
9829 #define TG3_PHY_LOOPBACK        1
9830
9831 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9832 {
9833         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9834         u32 desc_idx;
9835         struct sk_buff *skb, *rx_skb;
9836         u8 *tx_data;
9837         dma_addr_t map;
9838         int num_pkts, tx_len, rx_len, i, err;
9839         struct tg3_rx_buffer_desc *desc;
9840
9841         if (loopback_mode == TG3_MAC_LOOPBACK) {
9842                 /* HW errata - mac loopback fails in some cases on 5780.
9843                  * Normal traffic and PHY loopback are not affected by
9844                  * errata.
9845                  */
9846                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9847                         return 0;
9848
9849                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9850                            MAC_MODE_PORT_INT_LPBACK;
9851                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9852                         mac_mode |= MAC_MODE_LINK_POLARITY;
9853                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9854                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9855                 else
9856                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9857                 tw32(MAC_MODE, mac_mode);
9858         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9859                 u32 val;
9860
9861                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9862                         u32 phytest;
9863
9864                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9865                                 u32 phy;
9866
9867                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9868                                              phytest | MII_TG3_EPHY_SHADOW_EN);
9869                                 if (!tg3_readphy(tp, 0x1b, &phy))
9870                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
9871                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9872                         }
9873                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9874                 } else
9875                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9876
9877                 tg3_phy_toggle_automdix(tp, 0);
9878
9879                 tg3_writephy(tp, MII_BMCR, val);
9880                 udelay(40);
9881
9882                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9883                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9884                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9885                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9886                 } else
9887                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9888
9889                 /* reset to prevent losing 1st rx packet intermittently */
9890                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9891                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9892                         udelay(10);
9893                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9894                 }
9895                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9896                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9897                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9898                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9899                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9900                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9901                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9902                 }
9903                 tw32(MAC_MODE, mac_mode);
9904         }
9905         else
9906                 return -EINVAL;
9907
9908         err = -EIO;
9909
9910         tx_len = 1514;
9911         skb = netdev_alloc_skb(tp->dev, tx_len);
9912         if (!skb)
9913                 return -ENOMEM;
9914
9915         tx_data = skb_put(skb, tx_len);
9916         memcpy(tx_data, tp->dev->dev_addr, 6);
9917         memset(tx_data + 6, 0x0, 8);
9918
9919         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9920
9921         for (i = 14; i < tx_len; i++)
9922                 tx_data[i] = (u8) (i & 0xff);
9923
9924         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9925
9926         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9927              HOSTCC_MODE_NOW);
9928
9929         udelay(10);
9930
9931         rx_start_idx = tp->hw_status->idx[0].rx_producer;
9932
9933         num_pkts = 0;
9934
9935         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9936
9937         tp->tx_prod++;
9938         num_pkts++;
9939
9940         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9941                      tp->tx_prod);
9942         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9943
9944         udelay(10);
9945
9946         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
9947         for (i = 0; i < 25; i++) {
9948                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9949                        HOSTCC_MODE_NOW);
9950
9951                 udelay(10);
9952
9953                 tx_idx = tp->hw_status->idx[0].tx_consumer;
9954                 rx_idx = tp->hw_status->idx[0].rx_producer;
9955                 if ((tx_idx == tp->tx_prod) &&
9956                     (rx_idx == (rx_start_idx + num_pkts)))
9957                         break;
9958         }
9959
9960         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9961         dev_kfree_skb(skb);
9962
9963         if (tx_idx != tp->tx_prod)
9964                 goto out;
9965
9966         if (rx_idx != rx_start_idx + num_pkts)
9967                 goto out;
9968
9969         desc = &tp->rx_rcb[rx_start_idx];
9970         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9971         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9972         if (opaque_key != RXD_OPAQUE_RING_STD)
9973                 goto out;
9974
9975         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9976             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9977                 goto out;
9978
9979         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9980         if (rx_len != tx_len)
9981                 goto out;
9982
9983         rx_skb = tp->rx_std_buffers[desc_idx].skb;
9984
9985         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9986         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9987
9988         for (i = 14; i < tx_len; i++) {
9989                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9990                         goto out;
9991         }
9992         err = 0;
9993
9994         /* tg3_free_rings will unmap and free the rx_skb */
9995 out:
9996         return err;
9997 }
9998
9999 #define TG3_MAC_LOOPBACK_FAILED         1
10000 #define TG3_PHY_LOOPBACK_FAILED         2
10001 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10002                                          TG3_PHY_LOOPBACK_FAILED)
10003
10004 static int tg3_test_loopback(struct tg3 *tp)
10005 {
10006         int err = 0;
10007         u32 cpmuctrl = 0;
10008
10009         if (!netif_running(tp->dev))
10010                 return TG3_LOOPBACK_FAILED;
10011
10012         err = tg3_reset_hw(tp, 1);
10013         if (err)
10014                 return TG3_LOOPBACK_FAILED;
10015
10016         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10017             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
10018                 int i;
10019                 u32 status;
10020
10021                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10022
10023                 /* Wait for up to 40 microseconds to acquire lock. */
10024                 for (i = 0; i < 4; i++) {
10025                         status = tr32(TG3_CPMU_MUTEX_GNT);
10026                         if (status == CPMU_MUTEX_GNT_DRIVER)
10027                                 break;
10028                         udelay(10);
10029                 }
10030
10031                 if (status != CPMU_MUTEX_GNT_DRIVER)
10032                         return TG3_LOOPBACK_FAILED;
10033
10034                 /* Turn off link-based power management. */
10035                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10036                 tw32(TG3_CPMU_CTRL,
10037                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10038                                   CPMU_CTRL_LINK_AWARE_MODE));
10039         }
10040
10041         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10042                 err |= TG3_MAC_LOOPBACK_FAILED;
10043
10044         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
10046                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10047
10048                 /* Release the mutex */
10049                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10050         }
10051
10052         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10053             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10054                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10055                         err |= TG3_PHY_LOOPBACK_FAILED;
10056         }
10057
10058         return err;
10059 }
10060
10061 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10062                           u64 *data)
10063 {
10064         struct tg3 *tp = netdev_priv(dev);
10065
10066         if (tp->link_config.phy_is_low_power)
10067                 tg3_set_power_state(tp, PCI_D0);
10068
10069         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10070
10071         if (tg3_test_nvram(tp) != 0) {
10072                 etest->flags |= ETH_TEST_FL_FAILED;
10073                 data[0] = 1;
10074         }
10075         if (tg3_test_link(tp) != 0) {
10076                 etest->flags |= ETH_TEST_FL_FAILED;
10077                 data[1] = 1;
10078         }
10079         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10080                 int err, err2 = 0, irq_sync = 0;
10081
10082                 if (netif_running(dev)) {
10083                         tg3_phy_stop(tp);
10084                         tg3_netif_stop(tp);
10085                         irq_sync = 1;
10086                 }
10087
10088                 tg3_full_lock(tp, irq_sync);
10089
10090                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10091                 err = tg3_nvram_lock(tp);
10092                 tg3_halt_cpu(tp, RX_CPU_BASE);
10093                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10094                         tg3_halt_cpu(tp, TX_CPU_BASE);
10095                 if (!err)
10096                         tg3_nvram_unlock(tp);
10097
10098                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10099                         tg3_phy_reset(tp);
10100
10101                 if (tg3_test_registers(tp) != 0) {
10102                         etest->flags |= ETH_TEST_FL_FAILED;
10103                         data[2] = 1;
10104                 }
10105                 if (tg3_test_memory(tp) != 0) {
10106                         etest->flags |= ETH_TEST_FL_FAILED;
10107                         data[3] = 1;
10108                 }
10109                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10110                         etest->flags |= ETH_TEST_FL_FAILED;
10111
10112                 tg3_full_unlock(tp);
10113
10114                 if (tg3_test_interrupt(tp) != 0) {
10115                         etest->flags |= ETH_TEST_FL_FAILED;
10116                         data[5] = 1;
10117                 }
10118
10119                 tg3_full_lock(tp, 0);
10120
10121                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10122                 if (netif_running(dev)) {
10123                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10124                         err2 = tg3_restart_hw(tp, 1);
10125                         if (!err2)
10126                                 tg3_netif_start(tp);
10127                 }
10128
10129                 tg3_full_unlock(tp);
10130
10131                 if (irq_sync && !err2)
10132                         tg3_phy_start(tp);
10133         }
10134         if (tp->link_config.phy_is_low_power)
10135                 tg3_set_power_state(tp, PCI_D3hot);
10136
10137 }
10138
10139 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10140 {
10141         struct mii_ioctl_data *data = if_mii(ifr);
10142         struct tg3 *tp = netdev_priv(dev);
10143         int err;
10144
10145         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10146                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10147                         return -EAGAIN;
10148                 return phy_mii_ioctl(tp->mdio_bus.phy_map[PHY_ADDR], data, cmd);
10149         }
10150
10151         switch(cmd) {
10152         case SIOCGMIIPHY:
10153                 data->phy_id = PHY_ADDR;
10154
10155                 /* fallthru */
10156         case SIOCGMIIREG: {
10157                 u32 mii_regval;
10158
10159                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10160                         break;                  /* We have no PHY */
10161
10162                 if (tp->link_config.phy_is_low_power)
10163                         return -EAGAIN;
10164
10165                 spin_lock_bh(&tp->lock);
10166                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10167                 spin_unlock_bh(&tp->lock);
10168
10169                 data->val_out = mii_regval;
10170
10171                 return err;
10172         }
10173
10174         case SIOCSMIIREG:
10175                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10176                         break;                  /* We have no PHY */
10177
10178                 if (!capable(CAP_NET_ADMIN))
10179                         return -EPERM;
10180
10181                 if (tp->link_config.phy_is_low_power)
10182                         return -EAGAIN;
10183
10184                 spin_lock_bh(&tp->lock);
10185                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10186                 spin_unlock_bh(&tp->lock);
10187
10188                 return err;
10189
10190         default:
10191                 /* do nothing */
10192                 break;
10193         }
10194         return -EOPNOTSUPP;
10195 }
10196
10197 #if TG3_VLAN_TAG_USED
10198 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10199 {
10200         struct tg3 *tp = netdev_priv(dev);
10201
10202         if (netif_running(dev))
10203                 tg3_netif_stop(tp);
10204
10205         tg3_full_lock(tp, 0);
10206
10207         tp->vlgrp = grp;
10208
10209         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10210         __tg3_set_rx_mode(dev);
10211
10212         if (netif_running(dev))
10213                 tg3_netif_start(tp);
10214
10215         tg3_full_unlock(tp);
10216 }
10217 #endif
10218
10219 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10220 {
10221         struct tg3 *tp = netdev_priv(dev);
10222
10223         memcpy(ec, &tp->coal, sizeof(*ec));
10224         return 0;
10225 }
10226
10227 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10228 {
10229         struct tg3 *tp = netdev_priv(dev);
10230         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10231         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10232
10233         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10234                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10235                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10236                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10237                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10238         }
10239
10240         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10241             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10242             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10243             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10244             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10245             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10246             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10247             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10248             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10249             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10250                 return -EINVAL;
10251
10252         /* No rx interrupts will be generated if both are zero */
10253         if ((ec->rx_coalesce_usecs == 0) &&
10254             (ec->rx_max_coalesced_frames == 0))
10255                 return -EINVAL;
10256
10257         /* No tx interrupts will be generated if both are zero */
10258         if ((ec->tx_coalesce_usecs == 0) &&
10259             (ec->tx_max_coalesced_frames == 0))
10260                 return -EINVAL;
10261
10262         /* Only copy relevant parameters, ignore all others. */
10263         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10264         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10265         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10266         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10267         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10268         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10269         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10270         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10271         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10272
10273         if (netif_running(dev)) {
10274                 tg3_full_lock(tp, 0);
10275                 __tg3_set_coalesce(tp, &tp->coal);
10276                 tg3_full_unlock(tp);
10277         }
10278         return 0;
10279 }
10280
10281 static const struct ethtool_ops tg3_ethtool_ops = {
10282         .get_settings           = tg3_get_settings,
10283         .set_settings           = tg3_set_settings,
10284         .get_drvinfo            = tg3_get_drvinfo,
10285         .get_regs_len           = tg3_get_regs_len,
10286         .get_regs               = tg3_get_regs,
10287         .get_wol                = tg3_get_wol,
10288         .set_wol                = tg3_set_wol,
10289         .get_msglevel           = tg3_get_msglevel,
10290         .set_msglevel           = tg3_set_msglevel,
10291         .nway_reset             = tg3_nway_reset,
10292         .get_link               = ethtool_op_get_link,
10293         .get_eeprom_len         = tg3_get_eeprom_len,
10294         .get_eeprom             = tg3_get_eeprom,
10295         .set_eeprom             = tg3_set_eeprom,
10296         .get_ringparam          = tg3_get_ringparam,
10297         .set_ringparam          = tg3_set_ringparam,
10298         .get_pauseparam         = tg3_get_pauseparam,
10299         .set_pauseparam         = tg3_set_pauseparam,
10300         .get_rx_csum            = tg3_get_rx_csum,
10301         .set_rx_csum            = tg3_set_rx_csum,
10302         .set_tx_csum            = tg3_set_tx_csum,
10303         .set_sg                 = ethtool_op_set_sg,
10304         .set_tso                = tg3_set_tso,
10305         .self_test              = tg3_self_test,
10306         .get_strings            = tg3_get_strings,
10307         .phys_id                = tg3_phys_id,
10308         .get_ethtool_stats      = tg3_get_ethtool_stats,
10309         .get_coalesce           = tg3_get_coalesce,
10310         .set_coalesce           = tg3_set_coalesce,
10311         .get_sset_count         = tg3_get_sset_count,
10312 };
10313
10314 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10315 {
10316         u32 cursize, val, magic;
10317
10318         tp->nvram_size = EEPROM_CHIP_SIZE;
10319
10320         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
10321                 return;
10322
10323         if ((magic != TG3_EEPROM_MAGIC) &&
10324             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10325             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10326                 return;
10327
10328         /*
10329          * Size the chip by reading offsets at increasing powers of two.
10330          * When we encounter our validation signature, we know the addressing
10331          * has wrapped around, and thus have our chip size.
10332          */
10333         cursize = 0x10;
10334
10335         while (cursize < tp->nvram_size) {
10336                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
10337                         return;
10338
10339                 if (val == magic)
10340                         break;
10341
10342                 cursize <<= 1;
10343         }
10344
10345         tp->nvram_size = cursize;
10346 }
10347
10348 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10349 {
10350         u32 val;
10351
10352         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
10353                 return;
10354
10355         /* Selfboot format */
10356         if (val != TG3_EEPROM_MAGIC) {
10357                 tg3_get_eeprom_size(tp);
10358                 return;
10359         }
10360
10361         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10362                 if (val != 0) {
10363                         tp->nvram_size = (val >> 16) * 1024;
10364                         return;
10365                 }
10366         }
10367         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10368 }
10369
10370 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10371 {
10372         u32 nvcfg1;
10373
10374         nvcfg1 = tr32(NVRAM_CFG1);
10375         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10376                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10377         }
10378         else {
10379                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10380                 tw32(NVRAM_CFG1, nvcfg1);
10381         }
10382
10383         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10384             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10385                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10386                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10387                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10388                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10389                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10390                                 break;
10391                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10392                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10393                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10394                                 break;
10395                         case FLASH_VENDOR_ATMEL_EEPROM:
10396                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10397                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10398                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10399                                 break;
10400                         case FLASH_VENDOR_ST:
10401                                 tp->nvram_jedecnum = JEDEC_ST;
10402                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10403                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10404                                 break;
10405                         case FLASH_VENDOR_SAIFUN:
10406                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
10407                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10408                                 break;
10409                         case FLASH_VENDOR_SST_SMALL:
10410                         case FLASH_VENDOR_SST_LARGE:
10411                                 tp->nvram_jedecnum = JEDEC_SST;
10412                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10413                                 break;
10414                 }
10415         }
10416         else {
10417                 tp->nvram_jedecnum = JEDEC_ATMEL;
10418                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10419                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10420         }
10421 }
10422
10423 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10424 {
10425         u32 nvcfg1;
10426
10427         nvcfg1 = tr32(NVRAM_CFG1);
10428
10429         /* NVRAM protection for TPM */
10430         if (nvcfg1 & (1 << 27))
10431                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10432
10433         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10434                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10435                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10436                         tp->nvram_jedecnum = JEDEC_ATMEL;
10437                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10438                         break;
10439                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10440                         tp->nvram_jedecnum = JEDEC_ATMEL;
10441                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10442                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10443                         break;
10444                 case FLASH_5752VENDOR_ST_M45PE10:
10445                 case FLASH_5752VENDOR_ST_M45PE20:
10446                 case FLASH_5752VENDOR_ST_M45PE40:
10447                         tp->nvram_jedecnum = JEDEC_ST;
10448                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10449                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10450                         break;
10451         }
10452
10453         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10454                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10455                         case FLASH_5752PAGE_SIZE_256:
10456                                 tp->nvram_pagesize = 256;
10457                                 break;
10458                         case FLASH_5752PAGE_SIZE_512:
10459                                 tp->nvram_pagesize = 512;
10460                                 break;
10461                         case FLASH_5752PAGE_SIZE_1K:
10462                                 tp->nvram_pagesize = 1024;
10463                                 break;
10464                         case FLASH_5752PAGE_SIZE_2K:
10465                                 tp->nvram_pagesize = 2048;
10466                                 break;
10467                         case FLASH_5752PAGE_SIZE_4K:
10468                                 tp->nvram_pagesize = 4096;
10469                                 break;
10470                         case FLASH_5752PAGE_SIZE_264:
10471                                 tp->nvram_pagesize = 264;
10472                                 break;
10473                 }
10474         }
10475         else {
10476                 /* For eeprom, set pagesize to maximum eeprom size */
10477                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10478
10479                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10480                 tw32(NVRAM_CFG1, nvcfg1);
10481         }
10482 }
10483
10484 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10485 {
10486         u32 nvcfg1, protect = 0;
10487
10488         nvcfg1 = tr32(NVRAM_CFG1);
10489
10490         /* NVRAM protection for TPM */
10491         if (nvcfg1 & (1 << 27)) {
10492                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10493                 protect = 1;
10494         }
10495
10496         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10497         switch (nvcfg1) {
10498                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10499                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10500                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10501                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10502                         tp->nvram_jedecnum = JEDEC_ATMEL;
10503                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10504                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10505                         tp->nvram_pagesize = 264;
10506                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10507                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10508                                 tp->nvram_size = (protect ? 0x3e200 :
10509                                                   TG3_NVRAM_SIZE_512KB);
10510                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10511                                 tp->nvram_size = (protect ? 0x1f200 :
10512                                                   TG3_NVRAM_SIZE_256KB);
10513                         else
10514                                 tp->nvram_size = (protect ? 0x1f200 :
10515                                                   TG3_NVRAM_SIZE_128KB);
10516                         break;
10517                 case FLASH_5752VENDOR_ST_M45PE10:
10518                 case FLASH_5752VENDOR_ST_M45PE20:
10519                 case FLASH_5752VENDOR_ST_M45PE40:
10520                         tp->nvram_jedecnum = JEDEC_ST;
10521                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10522                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10523                         tp->nvram_pagesize = 256;
10524                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10525                                 tp->nvram_size = (protect ?
10526                                                   TG3_NVRAM_SIZE_64KB :
10527                                                   TG3_NVRAM_SIZE_128KB);
10528                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10529                                 tp->nvram_size = (protect ?
10530                                                   TG3_NVRAM_SIZE_64KB :
10531                                                   TG3_NVRAM_SIZE_256KB);
10532                         else
10533                                 tp->nvram_size = (protect ?
10534                                                   TG3_NVRAM_SIZE_128KB :
10535                                                   TG3_NVRAM_SIZE_512KB);
10536                         break;
10537         }
10538 }
10539
10540 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10541 {
10542         u32 nvcfg1;
10543
10544         nvcfg1 = tr32(NVRAM_CFG1);
10545
10546         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10547                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10548                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10549                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10550                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10551                         tp->nvram_jedecnum = JEDEC_ATMEL;
10552                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10553                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10554
10555                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10556                         tw32(NVRAM_CFG1, nvcfg1);
10557                         break;
10558                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10559                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10560                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10561                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10562                         tp->nvram_jedecnum = JEDEC_ATMEL;
10563                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10564                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10565                         tp->nvram_pagesize = 264;
10566                         break;
10567                 case FLASH_5752VENDOR_ST_M45PE10:
10568                 case FLASH_5752VENDOR_ST_M45PE20:
10569                 case FLASH_5752VENDOR_ST_M45PE40:
10570                         tp->nvram_jedecnum = JEDEC_ST;
10571                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10572                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10573                         tp->nvram_pagesize = 256;
10574                         break;
10575         }
10576 }
10577
10578 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10579 {
10580         u32 nvcfg1, protect = 0;
10581
10582         nvcfg1 = tr32(NVRAM_CFG1);
10583
10584         /* NVRAM protection for TPM */
10585         if (nvcfg1 & (1 << 27)) {
10586                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10587                 protect = 1;
10588         }
10589
10590         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10591         switch (nvcfg1) {
10592                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10593                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10594                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10595                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10596                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10597                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10598                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10599                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10600                         tp->nvram_jedecnum = JEDEC_ATMEL;
10601                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10602                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10603                         tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10604                         tp->nvram_pagesize = 256;
10605                         break;
10606                 case FLASH_5761VENDOR_ST_A_M45PE20:
10607                 case FLASH_5761VENDOR_ST_A_M45PE40:
10608                 case FLASH_5761VENDOR_ST_A_M45PE80:
10609                 case FLASH_5761VENDOR_ST_A_M45PE16:
10610                 case FLASH_5761VENDOR_ST_M_M45PE20:
10611                 case FLASH_5761VENDOR_ST_M_M45PE40:
10612                 case FLASH_5761VENDOR_ST_M_M45PE80:
10613                 case FLASH_5761VENDOR_ST_M_M45PE16:
10614                         tp->nvram_jedecnum = JEDEC_ST;
10615                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10616                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10617                         tp->nvram_pagesize = 256;
10618                         break;
10619         }
10620
10621         if (protect) {
10622                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10623         } else {
10624                 switch (nvcfg1) {
10625                         case FLASH_5761VENDOR_ATMEL_ADB161D:
10626                         case FLASH_5761VENDOR_ATMEL_MDB161D:
10627                         case FLASH_5761VENDOR_ST_A_M45PE16:
10628                         case FLASH_5761VENDOR_ST_M_M45PE16:
10629                                 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10630                                 break;
10631                         case FLASH_5761VENDOR_ATMEL_ADB081D:
10632                         case FLASH_5761VENDOR_ATMEL_MDB081D:
10633                         case FLASH_5761VENDOR_ST_A_M45PE80:
10634                         case FLASH_5761VENDOR_ST_M_M45PE80:
10635                                 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10636                                 break;
10637                         case FLASH_5761VENDOR_ATMEL_ADB041D:
10638                         case FLASH_5761VENDOR_ATMEL_MDB041D:
10639                         case FLASH_5761VENDOR_ST_A_M45PE40:
10640                         case FLASH_5761VENDOR_ST_M_M45PE40:
10641                                 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10642                                 break;
10643                         case FLASH_5761VENDOR_ATMEL_ADB021D:
10644                         case FLASH_5761VENDOR_ATMEL_MDB021D:
10645                         case FLASH_5761VENDOR_ST_A_M45PE20:
10646                         case FLASH_5761VENDOR_ST_M_M45PE20:
10647                                 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10648                                 break;
10649                 }
10650         }
10651 }
10652
10653 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10654 {
10655         tp->nvram_jedecnum = JEDEC_ATMEL;
10656         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10657         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10658 }
10659
10660 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10661 static void __devinit tg3_nvram_init(struct tg3 *tp)
10662 {
10663         tw32_f(GRC_EEPROM_ADDR,
10664              (EEPROM_ADDR_FSM_RESET |
10665               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10666                EEPROM_ADDR_CLKPERD_SHIFT)));
10667
10668         msleep(1);
10669
10670         /* Enable seeprom accesses. */
10671         tw32_f(GRC_LOCAL_CTRL,
10672              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10673         udelay(100);
10674
10675         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10676             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10677                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10678
10679                 if (tg3_nvram_lock(tp)) {
10680                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10681                                "tg3_nvram_init failed.\n", tp->dev->name);
10682                         return;
10683                 }
10684                 tg3_enable_nvram_access(tp);
10685
10686                 tp->nvram_size = 0;
10687
10688                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10689                         tg3_get_5752_nvram_info(tp);
10690                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10691                         tg3_get_5755_nvram_info(tp);
10692                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10693                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
10694                         tg3_get_5787_nvram_info(tp);
10695                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10696                         tg3_get_5761_nvram_info(tp);
10697                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10698                         tg3_get_5906_nvram_info(tp);
10699                 else
10700                         tg3_get_nvram_info(tp);
10701
10702                 if (tp->nvram_size == 0)
10703                         tg3_get_nvram_size(tp);
10704
10705                 tg3_disable_nvram_access(tp);
10706                 tg3_nvram_unlock(tp);
10707
10708         } else {
10709                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10710
10711                 tg3_get_eeprom_size(tp);
10712         }
10713 }
10714
10715 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10716                                         u32 offset, u32 *val)
10717 {
10718         u32 tmp;
10719         int i;
10720
10721         if (offset > EEPROM_ADDR_ADDR_MASK ||
10722             (offset % 4) != 0)
10723                 return -EINVAL;
10724
10725         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10726                                         EEPROM_ADDR_DEVID_MASK |
10727                                         EEPROM_ADDR_READ);
10728         tw32(GRC_EEPROM_ADDR,
10729              tmp |
10730              (0 << EEPROM_ADDR_DEVID_SHIFT) |
10731              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10732               EEPROM_ADDR_ADDR_MASK) |
10733              EEPROM_ADDR_READ | EEPROM_ADDR_START);
10734
10735         for (i = 0; i < 1000; i++) {
10736                 tmp = tr32(GRC_EEPROM_ADDR);
10737
10738                 if (tmp & EEPROM_ADDR_COMPLETE)
10739                         break;
10740                 msleep(1);
10741         }
10742         if (!(tmp & EEPROM_ADDR_COMPLETE))
10743                 return -EBUSY;
10744
10745         *val = tr32(GRC_EEPROM_DATA);
10746         return 0;
10747 }
10748
10749 #define NVRAM_CMD_TIMEOUT 10000
10750
10751 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10752 {
10753         int i;
10754
10755         tw32(NVRAM_CMD, nvram_cmd);
10756         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10757                 udelay(10);
10758                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10759                         udelay(10);
10760                         break;
10761                 }
10762         }
10763         if (i == NVRAM_CMD_TIMEOUT) {
10764                 return -EBUSY;
10765         }
10766         return 0;
10767 }
10768
10769 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10770 {
10771         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10772             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10773             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10774            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10775             (tp->nvram_jedecnum == JEDEC_ATMEL))
10776
10777                 addr = ((addr / tp->nvram_pagesize) <<
10778                         ATMEL_AT45DB0X1B_PAGE_POS) +
10779                        (addr % tp->nvram_pagesize);
10780
10781         return addr;
10782 }
10783
10784 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10785 {
10786         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10787             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10788             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10789            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10790             (tp->nvram_jedecnum == JEDEC_ATMEL))
10791
10792                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10793                         tp->nvram_pagesize) +
10794                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10795
10796         return addr;
10797 }
10798
10799 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10800 {
10801         int ret;
10802
10803         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10804                 return tg3_nvram_read_using_eeprom(tp, offset, val);
10805
10806         offset = tg3_nvram_phys_addr(tp, offset);
10807
10808         if (offset > NVRAM_ADDR_MSK)
10809                 return -EINVAL;
10810
10811         ret = tg3_nvram_lock(tp);
10812         if (ret)
10813                 return ret;
10814
10815         tg3_enable_nvram_access(tp);
10816
10817         tw32(NVRAM_ADDR, offset);
10818         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10819                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10820
10821         if (ret == 0)
10822                 *val = swab32(tr32(NVRAM_RDDATA));
10823
10824         tg3_disable_nvram_access(tp);
10825
10826         tg3_nvram_unlock(tp);
10827
10828         return ret;
10829 }
10830
10831 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10832 {
10833         u32 v;
10834         int res = tg3_nvram_read(tp, offset, &v);
10835         if (!res)
10836                 *val = cpu_to_le32(v);
10837         return res;
10838 }
10839
10840 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10841 {
10842         int err;
10843         u32 tmp;
10844
10845         err = tg3_nvram_read(tp, offset, &tmp);
10846         *val = swab32(tmp);
10847         return err;
10848 }
10849
10850 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10851                                     u32 offset, u32 len, u8 *buf)
10852 {
10853         int i, j, rc = 0;
10854         u32 val;
10855
10856         for (i = 0; i < len; i += 4) {
10857                 u32 addr;
10858                 __le32 data;
10859
10860                 addr = offset + i;
10861
10862                 memcpy(&data, buf + i, 4);
10863
10864                 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
10865
10866                 val = tr32(GRC_EEPROM_ADDR);
10867                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10868
10869                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10870                         EEPROM_ADDR_READ);
10871                 tw32(GRC_EEPROM_ADDR, val |
10872                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10873                         (addr & EEPROM_ADDR_ADDR_MASK) |
10874                         EEPROM_ADDR_START |
10875                         EEPROM_ADDR_WRITE);
10876
10877                 for (j = 0; j < 1000; j++) {
10878                         val = tr32(GRC_EEPROM_ADDR);
10879
10880                         if (val & EEPROM_ADDR_COMPLETE)
10881                                 break;
10882                         msleep(1);
10883                 }
10884                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10885                         rc = -EBUSY;
10886                         break;
10887                 }
10888         }
10889
10890         return rc;
10891 }
10892
10893 /* offset and length are dword aligned */
10894 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10895                 u8 *buf)
10896 {
10897         int ret = 0;
10898         u32 pagesize = tp->nvram_pagesize;
10899         u32 pagemask = pagesize - 1;
10900         u32 nvram_cmd;
10901         u8 *tmp;
10902
10903         tmp = kmalloc(pagesize, GFP_KERNEL);
10904         if (tmp == NULL)
10905                 return -ENOMEM;
10906
10907         while (len) {
10908                 int j;
10909                 u32 phy_addr, page_off, size;
10910
10911                 phy_addr = offset & ~pagemask;
10912
10913                 for (j = 0; j < pagesize; j += 4) {
10914                         if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
10915                                                 (__le32 *) (tmp + j))))
10916                                 break;
10917                 }
10918                 if (ret)
10919                         break;
10920
10921                 page_off = offset & pagemask;
10922                 size = pagesize;
10923                 if (len < size)
10924                         size = len;
10925
10926                 len -= size;
10927
10928                 memcpy(tmp + page_off, buf, size);
10929
10930                 offset = offset + (pagesize - page_off);
10931
10932                 tg3_enable_nvram_access(tp);
10933
10934                 /*
10935                  * Before we can erase the flash page, we need
10936                  * to issue a special "write enable" command.
10937                  */
10938                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10939
10940                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10941                         break;
10942
10943                 /* Erase the target page */
10944                 tw32(NVRAM_ADDR, phy_addr);
10945
10946                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10947                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10948
10949                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10950                         break;
10951
10952                 /* Issue another write enable to start the write. */
10953                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10954
10955                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10956                         break;
10957
10958                 for (j = 0; j < pagesize; j += 4) {
10959                         __be32 data;
10960
10961                         data = *((__be32 *) (tmp + j));
10962                         /* swab32(le32_to_cpu(data)), actually */
10963                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
10964
10965                         tw32(NVRAM_ADDR, phy_addr + j);
10966
10967                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10968                                 NVRAM_CMD_WR;
10969
10970                         if (j == 0)
10971                                 nvram_cmd |= NVRAM_CMD_FIRST;
10972                         else if (j == (pagesize - 4))
10973                                 nvram_cmd |= NVRAM_CMD_LAST;
10974
10975                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10976                                 break;
10977                 }
10978                 if (ret)
10979                         break;
10980         }
10981
10982         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10983         tg3_nvram_exec_cmd(tp, nvram_cmd);
10984
10985         kfree(tmp);
10986
10987         return ret;
10988 }
10989
10990 /* offset and length are dword aligned */
10991 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10992                 u8 *buf)
10993 {
10994         int i, ret = 0;
10995
10996         for (i = 0; i < len; i += 4, offset += 4) {
10997                 u32 page_off, phy_addr, nvram_cmd;
10998                 __be32 data;
10999
11000                 memcpy(&data, buf + i, 4);
11001                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11002
11003                 page_off = offset % tp->nvram_pagesize;
11004
11005                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11006
11007                 tw32(NVRAM_ADDR, phy_addr);
11008
11009                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11010
11011                 if ((page_off == 0) || (i == 0))
11012                         nvram_cmd |= NVRAM_CMD_FIRST;
11013                 if (page_off == (tp->nvram_pagesize - 4))
11014                         nvram_cmd |= NVRAM_CMD_LAST;
11015
11016                 if (i == (len - 4))
11017                         nvram_cmd |= NVRAM_CMD_LAST;
11018
11019                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
11020                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
11021                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
11022                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
11023                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
11024                     (tp->nvram_jedecnum == JEDEC_ST) &&
11025                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11026
11027                         if ((ret = tg3_nvram_exec_cmd(tp,
11028                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11029                                 NVRAM_CMD_DONE)))
11030
11031                                 break;
11032                 }
11033                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11034                         /* We always do complete word writes to eeprom. */
11035                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11036                 }
11037
11038                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11039                         break;
11040         }
11041         return ret;
11042 }
11043
11044 /* offset and length are dword aligned */
11045 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11046 {
11047         int ret;
11048
11049         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11050                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11051                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11052                 udelay(40);
11053         }
11054
11055         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11056                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11057         }
11058         else {
11059                 u32 grc_mode;
11060
11061                 ret = tg3_nvram_lock(tp);
11062                 if (ret)
11063                         return ret;
11064
11065                 tg3_enable_nvram_access(tp);
11066                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11067                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11068                         tw32(NVRAM_WRITE1, 0x406);
11069
11070                 grc_mode = tr32(GRC_MODE);
11071                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11072
11073                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11074                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11075
11076                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11077                                 buf);
11078                 }
11079                 else {
11080                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11081                                 buf);
11082                 }
11083
11084                 grc_mode = tr32(GRC_MODE);
11085                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11086
11087                 tg3_disable_nvram_access(tp);
11088                 tg3_nvram_unlock(tp);
11089         }
11090
11091         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11092                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11093                 udelay(40);
11094         }
11095
11096         return ret;
11097 }
11098
11099 struct subsys_tbl_ent {
11100         u16 subsys_vendor, subsys_devid;
11101         u32 phy_id;
11102 };
11103
11104 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11105         /* Broadcom boards. */
11106         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11107         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11108         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11109         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11110         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11111         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11112         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11113         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11114         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11115         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11116         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11117
11118         /* 3com boards. */
11119         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11120         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11121         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11122         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11123         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11124
11125         /* DELL boards. */
11126         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11127         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11128         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11129         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11130
11131         /* Compaq boards. */
11132         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11133         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11134         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11135         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11136         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11137
11138         /* IBM boards. */
11139         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11140 };
11141
11142 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11143 {
11144         int i;
11145
11146         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11147                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11148                      tp->pdev->subsystem_vendor) &&
11149                     (subsys_id_to_phy_id[i].subsys_devid ==
11150                      tp->pdev->subsystem_device))
11151                         return &subsys_id_to_phy_id[i];
11152         }
11153         return NULL;
11154 }
11155
11156 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11157 {
11158         u32 val;
11159         u16 pmcsr;
11160
11161         /* On some early chips the SRAM cannot be accessed in D3hot state,
11162          * so need make sure we're in D0.
11163          */
11164         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11165         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11166         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11167         msleep(1);
11168
11169         /* Make sure register accesses (indirect or otherwise)
11170          * will function correctly.
11171          */
11172         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11173                                tp->misc_host_ctrl);
11174
11175         /* The memory arbiter has to be enabled in order for SRAM accesses
11176          * to succeed.  Normally on powerup the tg3 chip firmware will make
11177          * sure it is enabled, but other entities such as system netboot
11178          * code might disable it.
11179          */
11180         val = tr32(MEMARB_MODE);
11181         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11182
11183         tp->phy_id = PHY_ID_INVALID;
11184         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11185
11186         /* Assume an onboard device and WOL capable by default.  */
11187         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11188
11189         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11190                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11191                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11192                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11193                 }
11194                 val = tr32(VCPU_CFGSHDW);
11195                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11196                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11197                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11198                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11199                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11200                 return;
11201         }
11202
11203         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11204         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11205                 u32 nic_cfg, led_cfg;
11206                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
11207                 int eeprom_phy_serdes = 0;
11208
11209                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11210                 tp->nic_sram_data_cfg = nic_cfg;
11211
11212                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11213                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11214                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11215                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11216                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11217                     (ver > 0) && (ver < 0x100))
11218                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11219
11220                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11221                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11222                         eeprom_phy_serdes = 1;
11223
11224                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11225                 if (nic_phy_id != 0) {
11226                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11227                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11228
11229                         eeprom_phy_id  = (id1 >> 16) << 10;
11230                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11231                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11232                 } else
11233                         eeprom_phy_id = 0;
11234
11235                 tp->phy_id = eeprom_phy_id;
11236                 if (eeprom_phy_serdes) {
11237                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11238                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11239                         else
11240                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11241                 }
11242
11243                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11244                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11245                                     SHASTA_EXT_LED_MODE_MASK);
11246                 else
11247                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11248
11249                 switch (led_cfg) {
11250                 default:
11251                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11252                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11253                         break;
11254
11255                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11256                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11257                         break;
11258
11259                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11260                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11261
11262                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11263                          * read on some older 5700/5701 bootcode.
11264                          */
11265                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11266                             ASIC_REV_5700 ||
11267                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11268                             ASIC_REV_5701)
11269                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11270
11271                         break;
11272
11273                 case SHASTA_EXT_LED_SHARED:
11274                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11275                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11276                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11277                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11278                                                  LED_CTRL_MODE_PHY_2);
11279                         break;
11280
11281                 case SHASTA_EXT_LED_MAC:
11282                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11283                         break;
11284
11285                 case SHASTA_EXT_LED_COMBO:
11286                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11287                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11288                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11289                                                  LED_CTRL_MODE_PHY_2);
11290                         break;
11291
11292                 };
11293
11294                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11295                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11296                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11297                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11298
11299                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11300                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11301
11302                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11303                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11304                         if ((tp->pdev->subsystem_vendor ==
11305                              PCI_VENDOR_ID_ARIMA) &&
11306                             (tp->pdev->subsystem_device == 0x205a ||
11307                              tp->pdev->subsystem_device == 0x2063))
11308                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11309                 } else {
11310                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11311                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11312                 }
11313
11314                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11315                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11316                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11317                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11318                 }
11319                 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
11320                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11321                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11322                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11323                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11324
11325                 if (tp->tg3_flags & TG3_FLAG_WOL_CAP &&
11326                     nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)
11327                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11328
11329                 if (cfg2 & (1 << 17))
11330                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11331
11332                 /* serdes signal pre-emphasis in register 0x590 set by */
11333                 /* bootcode if bit 18 is set */
11334                 if (cfg2 & (1 << 18))
11335                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11336
11337                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11338                         u32 cfg3;
11339
11340                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11341                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11342                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11343                 }
11344         }
11345 }
11346
11347 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11348 {
11349         int i;
11350         u32 val;
11351
11352         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11353         tw32(OTP_CTRL, cmd);
11354
11355         /* Wait for up to 1 ms for command to execute. */
11356         for (i = 0; i < 100; i++) {
11357                 val = tr32(OTP_STATUS);
11358                 if (val & OTP_STATUS_CMD_DONE)
11359                         break;
11360                 udelay(10);
11361         }
11362
11363         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11364 }
11365
11366 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11367  * configuration is a 32-bit value that straddles the alignment boundary.
11368  * We do two 32-bit reads and then shift and merge the results.
11369  */
11370 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11371 {
11372         u32 bhalf_otp, thalf_otp;
11373
11374         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11375
11376         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11377                 return 0;
11378
11379         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11380
11381         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11382                 return 0;
11383
11384         thalf_otp = tr32(OTP_READ_DATA);
11385
11386         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11387
11388         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11389                 return 0;
11390
11391         bhalf_otp = tr32(OTP_READ_DATA);
11392
11393         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11394 }
11395
11396 static int __devinit tg3_phy_probe(struct tg3 *tp)
11397 {
11398         u32 hw_phy_id_1, hw_phy_id_2;
11399         u32 hw_phy_id, hw_phy_id_masked;
11400         int err;
11401
11402         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11403                 return tg3_phy_init(tp);
11404
11405         /* Reading the PHY ID register can conflict with ASF
11406          * firwmare access to the PHY hardware.
11407          */
11408         err = 0;
11409         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11410             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11411                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11412         } else {
11413                 /* Now read the physical PHY_ID from the chip and verify
11414                  * that it is sane.  If it doesn't look good, we fall back
11415                  * to either the hard-coded table based PHY_ID and failing
11416                  * that the value found in the eeprom area.
11417                  */
11418                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11419                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11420
11421                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11422                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11423                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11424
11425                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11426         }
11427
11428         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11429                 tp->phy_id = hw_phy_id;
11430                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11431                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11432                 else
11433                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11434         } else {
11435                 if (tp->phy_id != PHY_ID_INVALID) {
11436                         /* Do nothing, phy ID already set up in
11437                          * tg3_get_eeprom_hw_cfg().
11438                          */
11439                 } else {
11440                         struct subsys_tbl_ent *p;
11441
11442                         /* No eeprom signature?  Try the hardcoded
11443                          * subsys device table.
11444                          */
11445                         p = lookup_by_subsys(tp);
11446                         if (!p)
11447                                 return -ENODEV;
11448
11449                         tp->phy_id = p->phy_id;
11450                         if (!tp->phy_id ||
11451                             tp->phy_id == PHY_ID_BCM8002)
11452                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11453                 }
11454         }
11455
11456         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11457             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11458             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11459                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11460
11461                 tg3_readphy(tp, MII_BMSR, &bmsr);
11462                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11463                     (bmsr & BMSR_LSTATUS))
11464                         goto skip_phy_reset;
11465
11466                 err = tg3_phy_reset(tp);
11467                 if (err)
11468                         return err;
11469
11470                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11471                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11472                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11473                 tg3_ctrl = 0;
11474                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11475                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11476                                     MII_TG3_CTRL_ADV_1000_FULL);
11477                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11478                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11479                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11480                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11481                 }
11482
11483                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11484                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11485                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11486                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11487                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11488
11489                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11490                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11491
11492                         tg3_writephy(tp, MII_BMCR,
11493                                      BMCR_ANENABLE | BMCR_ANRESTART);
11494                 }
11495                 tg3_phy_set_wirespeed(tp);
11496
11497                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11498                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11499                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11500         }
11501
11502 skip_phy_reset:
11503         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11504                 err = tg3_init_5401phy_dsp(tp);
11505                 if (err)
11506                         return err;
11507         }
11508
11509         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11510                 err = tg3_init_5401phy_dsp(tp);
11511         }
11512
11513         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11514                 tp->link_config.advertising =
11515                         (ADVERTISED_1000baseT_Half |
11516                          ADVERTISED_1000baseT_Full |
11517                          ADVERTISED_Autoneg |
11518                          ADVERTISED_FIBRE);
11519         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11520                 tp->link_config.advertising &=
11521                         ~(ADVERTISED_1000baseT_Half |
11522                           ADVERTISED_1000baseT_Full);
11523
11524         return err;
11525 }
11526
11527 static void __devinit tg3_read_partno(struct tg3 *tp)
11528 {
11529         unsigned char vpd_data[256];
11530         unsigned int i;
11531         u32 magic;
11532
11533         if (tg3_nvram_read_swab(tp, 0x0, &magic))
11534                 goto out_not_found;
11535
11536         if (magic == TG3_EEPROM_MAGIC) {
11537                 for (i = 0; i < 256; i += 4) {
11538                         u32 tmp;
11539
11540                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11541                                 goto out_not_found;
11542
11543                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
11544                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
11545                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11546                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11547                 }
11548         } else {
11549                 int vpd_cap;
11550
11551                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11552                 for (i = 0; i < 256; i += 4) {
11553                         u32 tmp, j = 0;
11554                         __le32 v;
11555                         u16 tmp16;
11556
11557                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11558                                               i);
11559                         while (j++ < 100) {
11560                                 pci_read_config_word(tp->pdev, vpd_cap +
11561                                                      PCI_VPD_ADDR, &tmp16);
11562                                 if (tmp16 & 0x8000)
11563                                         break;
11564                                 msleep(1);
11565                         }
11566                         if (!(tmp16 & 0x8000))
11567                                 goto out_not_found;
11568
11569                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11570                                               &tmp);
11571                         v = cpu_to_le32(tmp);
11572                         memcpy(&vpd_data[i], &v, 4);
11573                 }
11574         }
11575
11576         /* Now parse and find the part number. */
11577         for (i = 0; i < 254; ) {
11578                 unsigned char val = vpd_data[i];
11579                 unsigned int block_end;
11580
11581                 if (val == 0x82 || val == 0x91) {
11582                         i = (i + 3 +
11583                              (vpd_data[i + 1] +
11584                               (vpd_data[i + 2] << 8)));
11585                         continue;
11586                 }
11587
11588                 if (val != 0x90)
11589                         goto out_not_found;
11590
11591                 block_end = (i + 3 +
11592                              (vpd_data[i + 1] +
11593                               (vpd_data[i + 2] << 8)));
11594                 i += 3;
11595
11596                 if (block_end > 256)
11597                         goto out_not_found;
11598
11599                 while (i < (block_end - 2)) {
11600                         if (vpd_data[i + 0] == 'P' &&
11601                             vpd_data[i + 1] == 'N') {
11602                                 int partno_len = vpd_data[i + 2];
11603
11604                                 i += 3;
11605                                 if (partno_len > 24 || (partno_len + i) > 256)
11606                                         goto out_not_found;
11607
11608                                 memcpy(tp->board_part_number,
11609                                        &vpd_data[i], partno_len);
11610
11611                                 /* Success. */
11612                                 return;
11613                         }
11614                         i += 3 + vpd_data[i + 2];
11615                 }
11616
11617                 /* Part number not found. */
11618                 goto out_not_found;
11619         }
11620
11621 out_not_found:
11622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11623                 strcpy(tp->board_part_number, "BCM95906");
11624         else
11625                 strcpy(tp->board_part_number, "none");
11626 }
11627
11628 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11629 {
11630         u32 val;
11631
11632         if (tg3_nvram_read_swab(tp, offset, &val) ||
11633             (val & 0xfc000000) != 0x0c000000 ||
11634             tg3_nvram_read_swab(tp, offset + 4, &val) ||
11635             val != 0)
11636                 return 0;
11637
11638         return 1;
11639 }
11640
11641 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11642 {
11643         u32 val, offset, start;
11644         u32 ver_offset;
11645         int i, bcnt;
11646
11647         if (tg3_nvram_read_swab(tp, 0, &val))
11648                 return;
11649
11650         if (val != TG3_EEPROM_MAGIC)
11651                 return;
11652
11653         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11654             tg3_nvram_read_swab(tp, 0x4, &start))
11655                 return;
11656
11657         offset = tg3_nvram_logical_addr(tp, offset);
11658
11659         if (!tg3_fw_img_is_valid(tp, offset) ||
11660             tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
11661                 return;
11662
11663         offset = offset + ver_offset - start;
11664         for (i = 0; i < 16; i += 4) {
11665                 __le32 v;
11666                 if (tg3_nvram_read_le(tp, offset + i, &v))
11667                         return;
11668
11669                 memcpy(tp->fw_ver + i, &v, 4);
11670         }
11671
11672         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11673              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11674                 return;
11675
11676         for (offset = TG3_NVM_DIR_START;
11677              offset < TG3_NVM_DIR_END;
11678              offset += TG3_NVM_DIRENT_SIZE) {
11679                 if (tg3_nvram_read_swab(tp, offset, &val))
11680                         return;
11681
11682                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11683                         break;
11684         }
11685
11686         if (offset == TG3_NVM_DIR_END)
11687                 return;
11688
11689         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11690                 start = 0x08000000;
11691         else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11692                 return;
11693
11694         if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11695             !tg3_fw_img_is_valid(tp, offset) ||
11696             tg3_nvram_read_swab(tp, offset + 8, &val))
11697                 return;
11698
11699         offset += val - start;
11700
11701         bcnt = strlen(tp->fw_ver);
11702
11703         tp->fw_ver[bcnt++] = ',';
11704         tp->fw_ver[bcnt++] = ' ';
11705
11706         for (i = 0; i < 4; i++) {
11707                 __le32 v;
11708                 if (tg3_nvram_read_le(tp, offset, &v))
11709                         return;
11710
11711                 offset += sizeof(v);
11712
11713                 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11714                         memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11715                         break;
11716                 }
11717
11718                 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11719                 bcnt += sizeof(v);
11720         }
11721
11722         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11723 }
11724
11725 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11726
11727 static int __devinit tg3_get_invariants(struct tg3 *tp)
11728 {
11729         static struct pci_device_id write_reorder_chipsets[] = {
11730                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11731                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11732                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11733                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11734                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11735                              PCI_DEVICE_ID_VIA_8385_0) },
11736                 { },
11737         };
11738         u32 misc_ctrl_reg;
11739         u32 cacheline_sz_reg;
11740         u32 pci_state_reg, grc_misc_cfg;
11741         u32 val;
11742         u16 pci_cmd;
11743         int err, pcie_cap;
11744
11745         /* Force memory write invalidate off.  If we leave it on,
11746          * then on 5700_BX chips we have to enable a workaround.
11747          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11748          * to match the cacheline size.  The Broadcom driver have this
11749          * workaround but turns MWI off all the times so never uses
11750          * it.  This seems to suggest that the workaround is insufficient.
11751          */
11752         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11753         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11754         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11755
11756         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11757          * has the register indirect write enable bit set before
11758          * we try to access any of the MMIO registers.  It is also
11759          * critical that the PCI-X hw workaround situation is decided
11760          * before that as well.
11761          */
11762         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11763                               &misc_ctrl_reg);
11764
11765         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11766                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11767         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11768                 u32 prod_id_asic_rev;
11769
11770                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11771                                       &prod_id_asic_rev);
11772                 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11773         }
11774
11775         /* Wrong chip ID in 5752 A0. This code can be removed later
11776          * as A0 is not in production.
11777          */
11778         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11779                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11780
11781         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11782          * we need to disable memory and use config. cycles
11783          * only to access all registers. The 5702/03 chips
11784          * can mistakenly decode the special cycles from the
11785          * ICH chipsets as memory write cycles, causing corruption
11786          * of register and memory space. Only certain ICH bridges
11787          * will drive special cycles with non-zero data during the
11788          * address phase which can fall within the 5703's address
11789          * range. This is not an ICH bug as the PCI spec allows
11790          * non-zero address during special cycles. However, only
11791          * these ICH bridges are known to drive non-zero addresses
11792          * during special cycles.
11793          *
11794          * Since special cycles do not cross PCI bridges, we only
11795          * enable this workaround if the 5703 is on the secondary
11796          * bus of these ICH bridges.
11797          */
11798         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11799             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11800                 static struct tg3_dev_id {
11801                         u32     vendor;
11802                         u32     device;
11803                         u32     rev;
11804                 } ich_chipsets[] = {
11805                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11806                           PCI_ANY_ID },
11807                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11808                           PCI_ANY_ID },
11809                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11810                           0xa },
11811                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11812                           PCI_ANY_ID },
11813                         { },
11814                 };
11815                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11816                 struct pci_dev *bridge = NULL;
11817
11818                 while (pci_id->vendor != 0) {
11819                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11820                                                 bridge);
11821                         if (!bridge) {
11822                                 pci_id++;
11823                                 continue;
11824                         }
11825                         if (pci_id->rev != PCI_ANY_ID) {
11826                                 if (bridge->revision > pci_id->rev)
11827                                         continue;
11828                         }
11829                         if (bridge->subordinate &&
11830                             (bridge->subordinate->number ==
11831                              tp->pdev->bus->number)) {
11832
11833                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11834                                 pci_dev_put(bridge);
11835                                 break;
11836                         }
11837                 }
11838         }
11839
11840         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11841                 static struct tg3_dev_id {
11842                         u32     vendor;
11843                         u32     device;
11844                 } bridge_chipsets[] = {
11845                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11846                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11847                         { },
11848                 };
11849                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11850                 struct pci_dev *bridge = NULL;
11851
11852                 while (pci_id->vendor != 0) {
11853                         bridge = pci_get_device(pci_id->vendor,
11854                                                 pci_id->device,
11855                                                 bridge);
11856                         if (!bridge) {
11857                                 pci_id++;
11858                                 continue;
11859                         }
11860                         if (bridge->subordinate &&
11861                             (bridge->subordinate->number <=
11862                              tp->pdev->bus->number) &&
11863                             (bridge->subordinate->subordinate >=
11864                              tp->pdev->bus->number)) {
11865                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11866                                 pci_dev_put(bridge);
11867                                 break;
11868                         }
11869                 }
11870         }
11871
11872         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11873          * DMA addresses > 40-bit. This bridge may have other additional
11874          * 57xx devices behind it in some 4-port NIC designs for example.
11875          * Any tg3 device found behind the bridge will also need the 40-bit
11876          * DMA workaround.
11877          */
11878         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11879             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11880                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11881                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11882                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11883         }
11884         else {
11885                 struct pci_dev *bridge = NULL;
11886
11887                 do {
11888                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11889                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
11890                                                 bridge);
11891                         if (bridge && bridge->subordinate &&
11892                             (bridge->subordinate->number <=
11893                              tp->pdev->bus->number) &&
11894                             (bridge->subordinate->subordinate >=
11895                              tp->pdev->bus->number)) {
11896                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11897                                 pci_dev_put(bridge);
11898                                 break;
11899                         }
11900                 } while (bridge);
11901         }
11902
11903         /* Initialize misc host control in PCI block. */
11904         tp->misc_host_ctrl |= (misc_ctrl_reg &
11905                                MISC_HOST_CTRL_CHIPREV);
11906         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11907                                tp->misc_host_ctrl);
11908
11909         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11910                               &cacheline_sz_reg);
11911
11912         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
11913         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
11914         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
11915         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
11916
11917         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11918             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11919                 tp->pdev_peer = tg3_find_peer(tp);
11920
11921         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11922             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11923             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11924             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11925             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11926             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11927             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11928             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11929                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11930
11931         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11932             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11933                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11934
11935         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11936                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11937                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11938                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11939                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11940                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11941                      tp->pdev_peer == tp->pdev))
11942                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11943
11944                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11945                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11946                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11947                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11948                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11949                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11950                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11951                 } else {
11952                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11953                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11954                                 ASIC_REV_5750 &&
11955                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
11956                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11957                 }
11958         }
11959
11960         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11961              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11962                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11963
11964         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11965         if (pcie_cap != 0) {
11966                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11967
11968                 pcie_set_readrq(tp->pdev, 4096);
11969
11970                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11971                         u16 lnkctl;
11972
11973                         pci_read_config_word(tp->pdev,
11974                                              pcie_cap + PCI_EXP_LNKCTL,
11975                                              &lnkctl);
11976                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
11977                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11978                 }
11979         }
11980
11981         /* If we have an AMD 762 or VIA K8T800 chipset, write
11982          * reordering to the mailbox registers done by the host
11983          * controller can cause major troubles.  We read back from
11984          * every mailbox register write to force the writes to be
11985          * posted to the chip in order.
11986          */
11987         if (pci_dev_present(write_reorder_chipsets) &&
11988             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11989                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11990
11991         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11992             tp->pci_lat_timer < 64) {
11993                 tp->pci_lat_timer = 64;
11994
11995                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
11996                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
11997                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
11998                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
11999
12000                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12001                                        cacheline_sz_reg);
12002         }
12003
12004         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12005             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12006                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12007                 if (!tp->pcix_cap) {
12008                         printk(KERN_ERR PFX "Cannot find PCI-X "
12009                                             "capability, aborting.\n");
12010                         return -EIO;
12011                 }
12012         }
12013
12014         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12015                               &pci_state_reg);
12016
12017         if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
12018                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12019
12020                 /* If this is a 5700 BX chipset, and we are in PCI-X
12021                  * mode, enable register write workaround.
12022                  *
12023                  * The workaround is to use indirect register accesses
12024                  * for all chip writes not to mailbox registers.
12025                  */
12026                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12027                         u32 pm_reg;
12028
12029                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12030
12031                         /* The chip can have it's power management PCI config
12032                          * space registers clobbered due to this bug.
12033                          * So explicitly force the chip into D0 here.
12034                          */
12035                         pci_read_config_dword(tp->pdev,
12036                                               tp->pm_cap + PCI_PM_CTRL,
12037                                               &pm_reg);
12038                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12039                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12040                         pci_write_config_dword(tp->pdev,
12041                                                tp->pm_cap + PCI_PM_CTRL,
12042                                                pm_reg);
12043
12044                         /* Also, force SERR#/PERR# in PCI command. */
12045                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12046                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12047                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12048                 }
12049         }
12050
12051         /* 5700 BX chips need to have their TX producer index mailboxes
12052          * written twice to workaround a bug.
12053          */
12054         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
12055                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12056
12057         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12058                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12059         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12060                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12061
12062         /* Chip-specific fixup from Broadcom driver */
12063         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12064             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12065                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12066                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12067         }
12068
12069         /* Default fast path register access methods */
12070         tp->read32 = tg3_read32;
12071         tp->write32 = tg3_write32;
12072         tp->read32_mbox = tg3_read32;
12073         tp->write32_mbox = tg3_write32;
12074         tp->write32_tx_mbox = tg3_write32;
12075         tp->write32_rx_mbox = tg3_write32;
12076
12077         /* Various workaround register access methods */
12078         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12079                 tp->write32 = tg3_write_indirect_reg32;
12080         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12081                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12082                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12083                 /*
12084                  * Back to back register writes can cause problems on these
12085                  * chips, the workaround is to read back all reg writes
12086                  * except those to mailbox regs.
12087                  *
12088                  * See tg3_write_indirect_reg32().
12089                  */
12090                 tp->write32 = tg3_write_flush_reg32;
12091         }
12092
12093
12094         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12095             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12096                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12097                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12098                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12099         }
12100
12101         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12102                 tp->read32 = tg3_read_indirect_reg32;
12103                 tp->write32 = tg3_write_indirect_reg32;
12104                 tp->read32_mbox = tg3_read_indirect_mbox;
12105                 tp->write32_mbox = tg3_write_indirect_mbox;
12106                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12107                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12108
12109                 iounmap(tp->regs);
12110                 tp->regs = NULL;
12111
12112                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12113                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12114                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12115         }
12116         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12117                 tp->read32_mbox = tg3_read32_mbox_5906;
12118                 tp->write32_mbox = tg3_write32_mbox_5906;
12119                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12120                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12121         }
12122
12123         if (tp->write32 == tg3_write_indirect_reg32 ||
12124             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12125              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12126               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12127                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12128
12129         /* Get eeprom hw config before calling tg3_set_power_state().
12130          * In particular, the TG3_FLG2_IS_NIC flag must be
12131          * determined before calling tg3_set_power_state() so that
12132          * we know whether or not to switch out of Vaux power.
12133          * When the flag is set, it means that GPIO1 is used for eeprom
12134          * write protect and also implies that it is a LOM where GPIOs
12135          * are not used to switch power.
12136          */
12137         tg3_get_eeprom_hw_cfg(tp);
12138
12139         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12140                 /* Allow reads and writes to the
12141                  * APE register and memory space.
12142                  */
12143                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12144                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12145                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12146                                        pci_state_reg);
12147         }
12148
12149         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12150             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12151                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12152
12153                 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
12154                     tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
12155                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
12156                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
12157                         tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
12158         }
12159
12160         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12161          * GPIO1 driven high will bring 5700's external PHY out of reset.
12162          * It is also used as eeprom write protect on LOMs.
12163          */
12164         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12165         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12166             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12167                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12168                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12169         /* Unused GPIO3 must be driven as output on 5752 because there
12170          * are no pull-up resistors on unused GPIO pins.
12171          */
12172         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12173                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12174
12175         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12176                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12177
12178         /* Force the chip into D0. */
12179         err = tg3_set_power_state(tp, PCI_D0);
12180         if (err) {
12181                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12182                        pci_name(tp->pdev));
12183                 return err;
12184         }
12185
12186         /* 5700 B0 chips do not support checksumming correctly due
12187          * to hardware bugs.
12188          */
12189         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12190                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12191
12192         /* Derive initial jumbo mode from MTU assigned in
12193          * ether_setup() via the alloc_etherdev() call
12194          */
12195         if (tp->dev->mtu > ETH_DATA_LEN &&
12196             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12197                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12198
12199         /* Determine WakeOnLan speed to use. */
12200         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12201             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12202             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12203             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12204                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12205         } else {
12206                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12207         }
12208
12209         /* A few boards don't want Ethernet@WireSpeed phy feature */
12210         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12211             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12212              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12213              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12214             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12215             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12216                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12217
12218         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12219             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12220                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12221         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12222                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12223
12224         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12225                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12226                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12227                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12228                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12229                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12230                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12231                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12232                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12233                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12234                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
12235                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12236         }
12237
12238         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12239             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12240                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12241                 if (tp->phy_otp == 0)
12242                         tp->phy_otp = TG3_OTP_DEFAULT;
12243         }
12244
12245         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12246                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12247         else
12248                 tp->mi_mode = MAC_MI_MODE_BASE;
12249
12250         tp->coalesce_mode = 0;
12251         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12252             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12253                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12254
12255         err = tg3_mdio_init(tp);
12256         if (err)
12257                 return err;
12258
12259         /* Initialize data/descriptor byte/word swapping. */
12260         val = tr32(GRC_MODE);
12261         val &= GRC_MODE_HOST_STACKUP;
12262         tw32(GRC_MODE, val | tp->grc_mode);
12263
12264         tg3_switch_clocks(tp);
12265
12266         /* Clear this out for sanity. */
12267         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12268
12269         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12270                               &pci_state_reg);
12271         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12272             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12273                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12274
12275                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12276                     chiprevid == CHIPREV_ID_5701_B0 ||
12277                     chiprevid == CHIPREV_ID_5701_B2 ||
12278                     chiprevid == CHIPREV_ID_5701_B5) {
12279                         void __iomem *sram_base;
12280
12281                         /* Write some dummy words into the SRAM status block
12282                          * area, see if it reads back correctly.  If the return
12283                          * value is bad, force enable the PCIX workaround.
12284                          */
12285                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12286
12287                         writel(0x00000000, sram_base);
12288                         writel(0x00000000, sram_base + 4);
12289                         writel(0xffffffff, sram_base + 4);
12290                         if (readl(sram_base) != 0x00000000)
12291                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12292                 }
12293         }
12294
12295         udelay(50);
12296         tg3_nvram_init(tp);
12297
12298         grc_misc_cfg = tr32(GRC_MISC_CFG);
12299         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12300
12301         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12302             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12303              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12304                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12305
12306         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12307             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12308                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12309         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12310                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12311                                       HOSTCC_MODE_CLRTICK_TXBD);
12312
12313                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12314                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12315                                        tp->misc_host_ctrl);
12316         }
12317
12318         /* these are limited to 10/100 only */
12319         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12320              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12321             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12322              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12323              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12324               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12325               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12326             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12327              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12328               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12329               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12330             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12331                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12332
12333         err = tg3_phy_probe(tp);
12334         if (err) {
12335                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12336                        pci_name(tp->pdev), err);
12337                 /* ... but do not return immediately ... */
12338                 tg3_mdio_fini(tp);
12339         }
12340
12341         tg3_read_partno(tp);
12342         tg3_read_fw_ver(tp);
12343
12344         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12345                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12346         } else {
12347                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12348                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12349                 else
12350                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12351         }
12352
12353         /* 5700 {AX,BX} chips have a broken status block link
12354          * change bit implementation, so we must use the
12355          * status register in those cases.
12356          */
12357         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12358                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12359         else
12360                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12361
12362         /* The led_ctrl is set during tg3_phy_probe, here we might
12363          * have to force the link status polling mechanism based
12364          * upon subsystem IDs.
12365          */
12366         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12367             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12368             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12369                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12370                                   TG3_FLAG_USE_LINKCHG_REG);
12371         }
12372
12373         /* For all SERDES we poll the MAC status register. */
12374         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12375                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12376         else
12377                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12378
12379         /* All chips before 5787 can get confused if TX buffers
12380          * straddle the 4GB address boundary in some cases.
12381          */
12382         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12383             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12384             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12385             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12386             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12387                 tp->dev->hard_start_xmit = tg3_start_xmit;
12388         else
12389                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
12390
12391         tp->rx_offset = 2;
12392         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12393             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12394                 tp->rx_offset = 0;
12395
12396         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12397
12398         /* Increment the rx prod index on the rx std ring by at most
12399          * 8 for these chips to workaround hw errata.
12400          */
12401         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12402             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12403             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12404                 tp->rx_std_max_post = 8;
12405
12406         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12407                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12408                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12409
12410         return err;
12411 }
12412
12413 #ifdef CONFIG_SPARC
12414 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12415 {
12416         struct net_device *dev = tp->dev;
12417         struct pci_dev *pdev = tp->pdev;
12418         struct device_node *dp = pci_device_to_OF_node(pdev);
12419         const unsigned char *addr;
12420         int len;
12421
12422         addr = of_get_property(dp, "local-mac-address", &len);
12423         if (addr && len == 6) {
12424                 memcpy(dev->dev_addr, addr, 6);
12425                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12426                 return 0;
12427         }
12428         return -ENODEV;
12429 }
12430
12431 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12432 {
12433         struct net_device *dev = tp->dev;
12434
12435         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12436         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12437         return 0;
12438 }
12439 #endif
12440
12441 static int __devinit tg3_get_device_address(struct tg3 *tp)
12442 {
12443         struct net_device *dev = tp->dev;
12444         u32 hi, lo, mac_offset;
12445         int addr_ok = 0;
12446
12447 #ifdef CONFIG_SPARC
12448         if (!tg3_get_macaddr_sparc(tp))
12449                 return 0;
12450 #endif
12451
12452         mac_offset = 0x7c;
12453         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12454             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12455                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12456                         mac_offset = 0xcc;
12457                 if (tg3_nvram_lock(tp))
12458                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12459                 else
12460                         tg3_nvram_unlock(tp);
12461         }
12462         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12463                 mac_offset = 0x10;
12464
12465         /* First try to get it from MAC address mailbox. */
12466         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12467         if ((hi >> 16) == 0x484b) {
12468                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12469                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12470
12471                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12472                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12473                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12474                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12475                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12476
12477                 /* Some old bootcode may report a 0 MAC address in SRAM */
12478                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12479         }
12480         if (!addr_ok) {
12481                 /* Next, try NVRAM. */
12482                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
12483                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12484                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
12485                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
12486                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
12487                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
12488                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
12489                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
12490                 }
12491                 /* Finally just fetch it out of the MAC control regs. */
12492                 else {
12493                         hi = tr32(MAC_ADDR_0_HIGH);
12494                         lo = tr32(MAC_ADDR_0_LOW);
12495
12496                         dev->dev_addr[5] = lo & 0xff;
12497                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12498                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12499                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12500                         dev->dev_addr[1] = hi & 0xff;
12501                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12502                 }
12503         }
12504
12505         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12506 #ifdef CONFIG_SPARC
12507                 if (!tg3_get_default_macaddr_sparc(tp))
12508                         return 0;
12509 #endif
12510                 return -EINVAL;
12511         }
12512         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12513         return 0;
12514 }
12515
12516 #define BOUNDARY_SINGLE_CACHELINE       1
12517 #define BOUNDARY_MULTI_CACHELINE        2
12518
12519 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12520 {
12521         int cacheline_size;
12522         u8 byte;
12523         int goal;
12524
12525         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12526         if (byte == 0)
12527                 cacheline_size = 1024;
12528         else
12529                 cacheline_size = (int) byte * 4;
12530
12531         /* On 5703 and later chips, the boundary bits have no
12532          * effect.
12533          */
12534         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12535             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12536             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12537                 goto out;
12538
12539 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12540         goal = BOUNDARY_MULTI_CACHELINE;
12541 #else
12542 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12543         goal = BOUNDARY_SINGLE_CACHELINE;
12544 #else
12545         goal = 0;
12546 #endif
12547 #endif
12548
12549         if (!goal)
12550                 goto out;
12551
12552         /* PCI controllers on most RISC systems tend to disconnect
12553          * when a device tries to burst across a cache-line boundary.
12554          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12555          *
12556          * Unfortunately, for PCI-E there are only limited
12557          * write-side controls for this, and thus for reads
12558          * we will still get the disconnects.  We'll also waste
12559          * these PCI cycles for both read and write for chips
12560          * other than 5700 and 5701 which do not implement the
12561          * boundary bits.
12562          */
12563         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12564             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12565                 switch (cacheline_size) {
12566                 case 16:
12567                 case 32:
12568                 case 64:
12569                 case 128:
12570                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12571                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12572                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12573                         } else {
12574                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12575                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12576                         }
12577                         break;
12578
12579                 case 256:
12580                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12581                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12582                         break;
12583
12584                 default:
12585                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12586                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12587                         break;
12588                 };
12589         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12590                 switch (cacheline_size) {
12591                 case 16:
12592                 case 32:
12593                 case 64:
12594                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12595                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12596                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12597                                 break;
12598                         }
12599                         /* fallthrough */
12600                 case 128:
12601                 default:
12602                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12603                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12604                         break;
12605                 };
12606         } else {
12607                 switch (cacheline_size) {
12608                 case 16:
12609                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12610                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12611                                         DMA_RWCTRL_WRITE_BNDRY_16);
12612                                 break;
12613                         }
12614                         /* fallthrough */
12615                 case 32:
12616                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12617                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12618                                         DMA_RWCTRL_WRITE_BNDRY_32);
12619                                 break;
12620                         }
12621                         /* fallthrough */
12622                 case 64:
12623                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12624                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12625                                         DMA_RWCTRL_WRITE_BNDRY_64);
12626                                 break;
12627                         }
12628                         /* fallthrough */
12629                 case 128:
12630                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12631                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12632                                         DMA_RWCTRL_WRITE_BNDRY_128);
12633                                 break;
12634                         }
12635                         /* fallthrough */
12636                 case 256:
12637                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12638                                 DMA_RWCTRL_WRITE_BNDRY_256);
12639                         break;
12640                 case 512:
12641                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12642                                 DMA_RWCTRL_WRITE_BNDRY_512);
12643                         break;
12644                 case 1024:
12645                 default:
12646                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12647                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12648                         break;
12649                 };
12650         }
12651
12652 out:
12653         return val;
12654 }
12655
12656 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12657 {
12658         struct tg3_internal_buffer_desc test_desc;
12659         u32 sram_dma_descs;
12660         int i, ret;
12661
12662         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12663
12664         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12665         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12666         tw32(RDMAC_STATUS, 0);
12667         tw32(WDMAC_STATUS, 0);
12668
12669         tw32(BUFMGR_MODE, 0);
12670         tw32(FTQ_RESET, 0);
12671
12672         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12673         test_desc.addr_lo = buf_dma & 0xffffffff;
12674         test_desc.nic_mbuf = 0x00002100;
12675         test_desc.len = size;
12676
12677         /*
12678          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12679          * the *second* time the tg3 driver was getting loaded after an
12680          * initial scan.
12681          *
12682          * Broadcom tells me:
12683          *   ...the DMA engine is connected to the GRC block and a DMA
12684          *   reset may affect the GRC block in some unpredictable way...
12685          *   The behavior of resets to individual blocks has not been tested.
12686          *
12687          * Broadcom noted the GRC reset will also reset all sub-components.
12688          */
12689         if (to_device) {
12690                 test_desc.cqid_sqid = (13 << 8) | 2;
12691
12692                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12693                 udelay(40);
12694         } else {
12695                 test_desc.cqid_sqid = (16 << 8) | 7;
12696
12697                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12698                 udelay(40);
12699         }
12700         test_desc.flags = 0x00000005;
12701
12702         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12703                 u32 val;
12704
12705                 val = *(((u32 *)&test_desc) + i);
12706                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12707                                        sram_dma_descs + (i * sizeof(u32)));
12708                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12709         }
12710         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12711
12712         if (to_device) {
12713                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12714         } else {
12715                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12716         }
12717
12718         ret = -ENODEV;
12719         for (i = 0; i < 40; i++) {
12720                 u32 val;
12721
12722                 if (to_device)
12723                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12724                 else
12725                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12726                 if ((val & 0xffff) == sram_dma_descs) {
12727                         ret = 0;
12728                         break;
12729                 }
12730
12731                 udelay(100);
12732         }
12733
12734         return ret;
12735 }
12736
12737 #define TEST_BUFFER_SIZE        0x2000
12738
12739 static int __devinit tg3_test_dma(struct tg3 *tp)
12740 {
12741         dma_addr_t buf_dma;
12742         u32 *buf, saved_dma_rwctrl;
12743         int ret;
12744
12745         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12746         if (!buf) {
12747                 ret = -ENOMEM;
12748                 goto out_nofree;
12749         }
12750
12751         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12752                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12753
12754         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12755
12756         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12757                 /* DMA read watermark not used on PCIE */
12758                 tp->dma_rwctrl |= 0x00180000;
12759         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12760                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12761                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12762                         tp->dma_rwctrl |= 0x003f0000;
12763                 else
12764                         tp->dma_rwctrl |= 0x003f000f;
12765         } else {
12766                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12767                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12768                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12769                         u32 read_water = 0x7;
12770
12771                         /* If the 5704 is behind the EPB bridge, we can
12772                          * do the less restrictive ONE_DMA workaround for
12773                          * better performance.
12774                          */
12775                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12776                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12777                                 tp->dma_rwctrl |= 0x8000;
12778                         else if (ccval == 0x6 || ccval == 0x7)
12779                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12780
12781                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12782                                 read_water = 4;
12783                         /* Set bit 23 to enable PCIX hw bug fix */
12784                         tp->dma_rwctrl |=
12785                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12786                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12787                                 (1 << 23);
12788                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12789                         /* 5780 always in PCIX mode */
12790                         tp->dma_rwctrl |= 0x00144000;
12791                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12792                         /* 5714 always in PCIX mode */
12793                         tp->dma_rwctrl |= 0x00148000;
12794                 } else {
12795                         tp->dma_rwctrl |= 0x001b000f;
12796                 }
12797         }
12798
12799         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12800             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12801                 tp->dma_rwctrl &= 0xfffffff0;
12802
12803         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12804             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12805                 /* Remove this if it causes problems for some boards. */
12806                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12807
12808                 /* On 5700/5701 chips, we need to set this bit.
12809                  * Otherwise the chip will issue cacheline transactions
12810                  * to streamable DMA memory with not all the byte
12811                  * enables turned on.  This is an error on several
12812                  * RISC PCI controllers, in particular sparc64.
12813                  *
12814                  * On 5703/5704 chips, this bit has been reassigned
12815                  * a different meaning.  In particular, it is used
12816                  * on those chips to enable a PCI-X workaround.
12817                  */
12818                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12819         }
12820
12821         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12822
12823 #if 0
12824         /* Unneeded, already done by tg3_get_invariants.  */
12825         tg3_switch_clocks(tp);
12826 #endif
12827
12828         ret = 0;
12829         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12830             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12831                 goto out;
12832
12833         /* It is best to perform DMA test with maximum write burst size
12834          * to expose the 5700/5701 write DMA bug.
12835          */
12836         saved_dma_rwctrl = tp->dma_rwctrl;
12837         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12838         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12839
12840         while (1) {
12841                 u32 *p = buf, i;
12842
12843                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12844                         p[i] = i;
12845
12846                 /* Send the buffer to the chip. */
12847                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12848                 if (ret) {
12849                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12850                         break;
12851                 }
12852
12853 #if 0
12854                 /* validate data reached card RAM correctly. */
12855                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12856                         u32 val;
12857                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
12858                         if (le32_to_cpu(val) != p[i]) {
12859                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
12860                                 /* ret = -ENODEV here? */
12861                         }
12862                         p[i] = 0;
12863                 }
12864 #endif
12865                 /* Now read it back. */
12866                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12867                 if (ret) {
12868                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12869
12870                         break;
12871                 }
12872
12873                 /* Verify it. */
12874                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12875                         if (p[i] == i)
12876                                 continue;
12877
12878                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12879                             DMA_RWCTRL_WRITE_BNDRY_16) {
12880                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12881                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12882                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12883                                 break;
12884                         } else {
12885                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12886                                 ret = -ENODEV;
12887                                 goto out;
12888                         }
12889                 }
12890
12891                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12892                         /* Success. */
12893                         ret = 0;
12894                         break;
12895                 }
12896         }
12897         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12898             DMA_RWCTRL_WRITE_BNDRY_16) {
12899                 static struct pci_device_id dma_wait_state_chipsets[] = {
12900                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12901                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12902                         { },
12903                 };
12904
12905                 /* DMA test passed without adjusting DMA boundary,
12906                  * now look for chipsets that are known to expose the
12907                  * DMA bug without failing the test.
12908                  */
12909                 if (pci_dev_present(dma_wait_state_chipsets)) {
12910                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12911                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12912                 }
12913                 else
12914                         /* Safe to use the calculated DMA boundary. */
12915                         tp->dma_rwctrl = saved_dma_rwctrl;
12916
12917                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12918         }
12919
12920 out:
12921         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12922 out_nofree:
12923         return ret;
12924 }
12925
12926 static void __devinit tg3_init_link_config(struct tg3 *tp)
12927 {
12928         tp->link_config.advertising =
12929                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12930                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12931                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12932                  ADVERTISED_Autoneg | ADVERTISED_MII);
12933         tp->link_config.speed = SPEED_INVALID;
12934         tp->link_config.duplex = DUPLEX_INVALID;
12935         tp->link_config.autoneg = AUTONEG_ENABLE;
12936         tp->link_config.active_speed = SPEED_INVALID;
12937         tp->link_config.active_duplex = DUPLEX_INVALID;
12938         tp->link_config.phy_is_low_power = 0;
12939         tp->link_config.orig_speed = SPEED_INVALID;
12940         tp->link_config.orig_duplex = DUPLEX_INVALID;
12941         tp->link_config.orig_autoneg = AUTONEG_INVALID;
12942 }
12943
12944 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12945 {
12946         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12947                 tp->bufmgr_config.mbuf_read_dma_low_water =
12948                         DEFAULT_MB_RDMA_LOW_WATER_5705;
12949                 tp->bufmgr_config.mbuf_mac_rx_low_water =
12950                         DEFAULT_MB_MACRX_LOW_WATER_5705;
12951                 tp->bufmgr_config.mbuf_high_water =
12952                         DEFAULT_MB_HIGH_WATER_5705;
12953                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12954                         tp->bufmgr_config.mbuf_mac_rx_low_water =
12955                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
12956                         tp->bufmgr_config.mbuf_high_water =
12957                                 DEFAULT_MB_HIGH_WATER_5906;
12958                 }
12959
12960                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12961                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12962                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12963                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12964                 tp->bufmgr_config.mbuf_high_water_jumbo =
12965                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12966         } else {
12967                 tp->bufmgr_config.mbuf_read_dma_low_water =
12968                         DEFAULT_MB_RDMA_LOW_WATER;
12969                 tp->bufmgr_config.mbuf_mac_rx_low_water =
12970                         DEFAULT_MB_MACRX_LOW_WATER;
12971                 tp->bufmgr_config.mbuf_high_water =
12972                         DEFAULT_MB_HIGH_WATER;
12973
12974                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12975                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12976                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12977                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12978                 tp->bufmgr_config.mbuf_high_water_jumbo =
12979                         DEFAULT_MB_HIGH_WATER_JUMBO;
12980         }
12981
12982         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12983         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12984 }
12985
12986 static char * __devinit tg3_phy_string(struct tg3 *tp)
12987 {
12988         switch (tp->phy_id & PHY_ID_MASK) {
12989         case PHY_ID_BCM5400:    return "5400";
12990         case PHY_ID_BCM5401:    return "5401";
12991         case PHY_ID_BCM5411:    return "5411";
12992         case PHY_ID_BCM5701:    return "5701";
12993         case PHY_ID_BCM5703:    return "5703";
12994         case PHY_ID_BCM5704:    return "5704";
12995         case PHY_ID_BCM5705:    return "5705";
12996         case PHY_ID_BCM5750:    return "5750";
12997         case PHY_ID_BCM5752:    return "5752";
12998         case PHY_ID_BCM5714:    return "5714";
12999         case PHY_ID_BCM5780:    return "5780";
13000         case PHY_ID_BCM5755:    return "5755";
13001         case PHY_ID_BCM5787:    return "5787";
13002         case PHY_ID_BCM5784:    return "5784";
13003         case PHY_ID_BCM5756:    return "5722/5756";
13004         case PHY_ID_BCM5906:    return "5906";
13005         case PHY_ID_BCM5761:    return "5761";
13006         case PHY_ID_BCM8002:    return "8002/serdes";
13007         case 0:                 return "serdes";
13008         default:                return "unknown";
13009         };
13010 }
13011
13012 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13013 {
13014         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13015                 strcpy(str, "PCI Express");
13016                 return str;
13017         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13018                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13019
13020                 strcpy(str, "PCIX:");
13021
13022                 if ((clock_ctrl == 7) ||
13023                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13024                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13025                         strcat(str, "133MHz");
13026                 else if (clock_ctrl == 0)
13027                         strcat(str, "33MHz");
13028                 else if (clock_ctrl == 2)
13029                         strcat(str, "50MHz");
13030                 else if (clock_ctrl == 4)
13031                         strcat(str, "66MHz");
13032                 else if (clock_ctrl == 6)
13033                         strcat(str, "100MHz");
13034         } else {
13035                 strcpy(str, "PCI:");
13036                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13037                         strcat(str, "66MHz");
13038                 else
13039                         strcat(str, "33MHz");
13040         }
13041         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13042                 strcat(str, ":32-bit");
13043         else
13044                 strcat(str, ":64-bit");
13045         return str;
13046 }
13047
13048 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13049 {
13050         struct pci_dev *peer;
13051         unsigned int func, devnr = tp->pdev->devfn & ~7;
13052
13053         for (func = 0; func < 8; func++) {
13054                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13055                 if (peer && peer != tp->pdev)
13056                         break;
13057                 pci_dev_put(peer);
13058         }
13059         /* 5704 can be configured in single-port mode, set peer to
13060          * tp->pdev in that case.
13061          */
13062         if (!peer) {
13063                 peer = tp->pdev;
13064                 return peer;
13065         }
13066
13067         /*
13068          * We don't need to keep the refcount elevated; there's no way
13069          * to remove one half of this device without removing the other
13070          */
13071         pci_dev_put(peer);
13072
13073         return peer;
13074 }
13075
13076 static void __devinit tg3_init_coal(struct tg3 *tp)
13077 {
13078         struct ethtool_coalesce *ec = &tp->coal;
13079
13080         memset(ec, 0, sizeof(*ec));
13081         ec->cmd = ETHTOOL_GCOALESCE;
13082         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13083         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13084         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13085         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13086         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13087         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13088         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13089         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13090         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13091
13092         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13093                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13094                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13095                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13096                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13097                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13098         }
13099
13100         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13101                 ec->rx_coalesce_usecs_irq = 0;
13102                 ec->tx_coalesce_usecs_irq = 0;
13103                 ec->stats_block_coalesce_usecs = 0;
13104         }
13105 }
13106
13107 static int __devinit tg3_init_one(struct pci_dev *pdev,
13108                                   const struct pci_device_id *ent)
13109 {
13110         static int tg3_version_printed = 0;
13111         resource_size_t tg3reg_base;
13112         unsigned long tg3reg_len;
13113         struct net_device *dev;
13114         struct tg3 *tp;
13115         int err, pm_cap;
13116         char str[40];
13117         u64 dma_mask, persist_dma_mask;
13118         DECLARE_MAC_BUF(mac);
13119
13120         if (tg3_version_printed++ == 0)
13121                 printk(KERN_INFO "%s", version);
13122
13123         err = pci_enable_device(pdev);
13124         if (err) {
13125                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13126                        "aborting.\n");
13127                 return err;
13128         }
13129
13130         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13131                 printk(KERN_ERR PFX "Cannot find proper PCI device "
13132                        "base address, aborting.\n");
13133                 err = -ENODEV;
13134                 goto err_out_disable_pdev;
13135         }
13136
13137         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13138         if (err) {
13139                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13140                        "aborting.\n");
13141                 goto err_out_disable_pdev;
13142         }
13143
13144         pci_set_master(pdev);
13145
13146         /* Find power-management capability. */
13147         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13148         if (pm_cap == 0) {
13149                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13150                        "aborting.\n");
13151                 err = -EIO;
13152                 goto err_out_free_res;
13153         }
13154
13155         tg3reg_base = pci_resource_start(pdev, 0);
13156         tg3reg_len = pci_resource_len(pdev, 0);
13157
13158         dev = alloc_etherdev(sizeof(*tp));
13159         if (!dev) {
13160                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13161                 err = -ENOMEM;
13162                 goto err_out_free_res;
13163         }
13164
13165         SET_NETDEV_DEV(dev, &pdev->dev);
13166
13167 #if TG3_VLAN_TAG_USED
13168         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13169         dev->vlan_rx_register = tg3_vlan_rx_register;
13170 #endif
13171
13172         tp = netdev_priv(dev);
13173         tp->pdev = pdev;
13174         tp->dev = dev;
13175         tp->pm_cap = pm_cap;
13176         tp->mac_mode = TG3_DEF_MAC_MODE;
13177         tp->rx_mode = TG3_DEF_RX_MODE;
13178         tp->tx_mode = TG3_DEF_TX_MODE;
13179
13180         if (tg3_debug > 0)
13181                 tp->msg_enable = tg3_debug;
13182         else
13183                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13184
13185         /* The word/byte swap controls here control register access byte
13186          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13187          * setting below.
13188          */
13189         tp->misc_host_ctrl =
13190                 MISC_HOST_CTRL_MASK_PCI_INT |
13191                 MISC_HOST_CTRL_WORD_SWAP |
13192                 MISC_HOST_CTRL_INDIR_ACCESS |
13193                 MISC_HOST_CTRL_PCISTATE_RW;
13194
13195         /* The NONFRM (non-frame) byte/word swap controls take effect
13196          * on descriptor entries, anything which isn't packet data.
13197          *
13198          * The StrongARM chips on the board (one for tx, one for rx)
13199          * are running in big-endian mode.
13200          */
13201         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13202                         GRC_MODE_WSWAP_NONFRM_DATA);
13203 #ifdef __BIG_ENDIAN
13204         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13205 #endif
13206         spin_lock_init(&tp->lock);
13207         spin_lock_init(&tp->indirect_lock);
13208         INIT_WORK(&tp->reset_task, tg3_reset_task);
13209
13210         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
13211         if (!tp->regs) {
13212                 printk(KERN_ERR PFX "Cannot map device registers, "
13213                        "aborting.\n");
13214                 err = -ENOMEM;
13215                 goto err_out_free_dev;
13216         }
13217
13218         tg3_init_link_config(tp);
13219
13220         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13221         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13222         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13223
13224         dev->open = tg3_open;
13225         dev->stop = tg3_close;
13226         dev->get_stats = tg3_get_stats;
13227         dev->set_multicast_list = tg3_set_rx_mode;
13228         dev->set_mac_address = tg3_set_mac_addr;
13229         dev->do_ioctl = tg3_ioctl;
13230         dev->tx_timeout = tg3_tx_timeout;
13231         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13232         dev->ethtool_ops = &tg3_ethtool_ops;
13233         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13234         dev->change_mtu = tg3_change_mtu;
13235         dev->irq = pdev->irq;
13236 #ifdef CONFIG_NET_POLL_CONTROLLER
13237         dev->poll_controller = tg3_poll_controller;
13238 #endif
13239
13240         err = tg3_get_invariants(tp);
13241         if (err) {
13242                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13243                        "aborting.\n");
13244                 goto err_out_iounmap;
13245         }
13246
13247         /* The EPB bridge inside 5714, 5715, and 5780 and any
13248          * device behind the EPB cannot support DMA addresses > 40-bit.
13249          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13250          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13251          * do DMA address check in tg3_start_xmit().
13252          */
13253         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13254                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13255         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13256                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13257 #ifdef CONFIG_HIGHMEM
13258                 dma_mask = DMA_64BIT_MASK;
13259 #endif
13260         } else
13261                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13262
13263         /* Configure DMA attributes. */
13264         if (dma_mask > DMA_32BIT_MASK) {
13265                 err = pci_set_dma_mask(pdev, dma_mask);
13266                 if (!err) {
13267                         dev->features |= NETIF_F_HIGHDMA;
13268                         err = pci_set_consistent_dma_mask(pdev,
13269                                                           persist_dma_mask);
13270                         if (err < 0) {
13271                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13272                                        "DMA for consistent allocations\n");
13273                                 goto err_out_iounmap;
13274                         }
13275                 }
13276         }
13277         if (err || dma_mask == DMA_32BIT_MASK) {
13278                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13279                 if (err) {
13280                         printk(KERN_ERR PFX "No usable DMA configuration, "
13281                                "aborting.\n");
13282                         goto err_out_iounmap;
13283                 }
13284         }
13285
13286         tg3_init_bufmgr_config(tp);
13287
13288         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13289                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13290         }
13291         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13292             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13293             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13294             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13295             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13296                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13297         } else {
13298                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13299         }
13300
13301         /* TSO is on by default on chips that support hardware TSO.
13302          * Firmware TSO on older chips gives lower performance, so it
13303          * is off by default, but can be enabled using ethtool.
13304          */
13305         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13306                 dev->features |= NETIF_F_TSO;
13307                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
13308                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
13309                         dev->features |= NETIF_F_TSO6;
13310                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
13311                         dev->features |= NETIF_F_TSO_ECN;
13312         }
13313
13314
13315         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13316             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13317             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13318                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13319                 tp->rx_pending = 63;
13320         }
13321
13322         err = tg3_get_device_address(tp);
13323         if (err) {
13324                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13325                        "aborting.\n");
13326                 goto err_out_iounmap;
13327         }
13328
13329         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13330                 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13331                         printk(KERN_ERR PFX "Cannot find proper PCI device "
13332                                "base address for APE, aborting.\n");
13333                         err = -ENODEV;
13334                         goto err_out_iounmap;
13335                 }
13336
13337                 tg3reg_base = pci_resource_start(pdev, 2);
13338                 tg3reg_len = pci_resource_len(pdev, 2);
13339
13340                 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
13341                 if (!tp->aperegs) {
13342                         printk(KERN_ERR PFX "Cannot map APE registers, "
13343                                "aborting.\n");
13344                         err = -ENOMEM;
13345                         goto err_out_iounmap;
13346                 }
13347
13348                 tg3_ape_lock_init(tp);
13349         }
13350
13351         /*
13352          * Reset chip in case UNDI or EFI driver did not shutdown
13353          * DMA self test will enable WDMAC and we'll see (spurious)
13354          * pending DMA on the PCI bus at that point.
13355          */
13356         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13357             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13358                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13359                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13360         }
13361
13362         err = tg3_test_dma(tp);
13363         if (err) {
13364                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13365                 goto err_out_apeunmap;
13366         }
13367
13368         /* Tigon3 can do ipv4 only... and some chips have buggy
13369          * checksumming.
13370          */
13371         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
13372                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13373                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13374                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13375                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13376                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
13377                         dev->features |= NETIF_F_IPV6_CSUM;
13378
13379                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13380         } else
13381                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
13382
13383         /* flow control autonegotiation is default behavior */
13384         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13385         tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
13386
13387         tg3_init_coal(tp);
13388
13389         pci_set_drvdata(pdev, dev);
13390
13391         err = register_netdev(dev);
13392         if (err) {
13393                 printk(KERN_ERR PFX "Cannot register net device, "
13394                        "aborting.\n");
13395                 goto err_out_apeunmap;
13396         }
13397
13398         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
13399                "(%s) %s Ethernet %s\n",
13400                dev->name,
13401                tp->board_part_number,
13402                tp->pci_chip_rev_id,
13403                tg3_phy_string(tp),
13404                tg3_bus_string(tp, str),
13405                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13406                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13407                  "10/100/1000Base-T")),
13408                print_mac(mac, dev->dev_addr));
13409
13410         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
13411                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
13412                dev->name,
13413                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13414                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13415                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13416                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13417                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
13418                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13419         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13420                dev->name, tp->dma_rwctrl,
13421                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13422                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13423
13424         return 0;
13425
13426 err_out_apeunmap:
13427         if (tp->aperegs) {
13428                 iounmap(tp->aperegs);
13429                 tp->aperegs = NULL;
13430         }
13431
13432 err_out_iounmap:
13433         if (tp->regs) {
13434                 iounmap(tp->regs);
13435                 tp->regs = NULL;
13436         }
13437
13438 err_out_free_dev:
13439         free_netdev(dev);
13440
13441 err_out_free_res:
13442         pci_release_regions(pdev);
13443
13444 err_out_disable_pdev:
13445         pci_disable_device(pdev);
13446         pci_set_drvdata(pdev, NULL);
13447         return err;
13448 }
13449
13450 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13451 {
13452         struct net_device *dev = pci_get_drvdata(pdev);
13453
13454         if (dev) {
13455                 struct tg3 *tp = netdev_priv(dev);
13456
13457                 flush_scheduled_work();
13458
13459                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13460                         tg3_phy_fini(tp);
13461                         tg3_mdio_fini(tp);
13462                 }
13463
13464                 unregister_netdev(dev);
13465                 if (tp->aperegs) {
13466                         iounmap(tp->aperegs);
13467                         tp->aperegs = NULL;
13468                 }
13469                 if (tp->regs) {
13470                         iounmap(tp->regs);
13471                         tp->regs = NULL;
13472                 }
13473                 free_netdev(dev);
13474                 pci_release_regions(pdev);
13475                 pci_disable_device(pdev);
13476                 pci_set_drvdata(pdev, NULL);
13477         }
13478 }
13479
13480 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13481 {
13482         struct net_device *dev = pci_get_drvdata(pdev);
13483         struct tg3 *tp = netdev_priv(dev);
13484         int err;
13485
13486         /* PCI register 4 needs to be saved whether netif_running() or not.
13487          * MSI address and data need to be saved if using MSI and
13488          * netif_running().
13489          */
13490         pci_save_state(pdev);
13491
13492         if (!netif_running(dev))
13493                 return 0;
13494
13495         flush_scheduled_work();
13496         tg3_phy_stop(tp);
13497         tg3_netif_stop(tp);
13498
13499         del_timer_sync(&tp->timer);
13500
13501         tg3_full_lock(tp, 1);
13502         tg3_disable_ints(tp);
13503         tg3_full_unlock(tp);
13504
13505         netif_device_detach(dev);
13506
13507         tg3_full_lock(tp, 0);
13508         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13509         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13510         tg3_full_unlock(tp);
13511
13512         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
13513         if (err) {
13514                 int err2;
13515
13516                 tg3_full_lock(tp, 0);
13517
13518                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13519                 err2 = tg3_restart_hw(tp, 1);
13520                 if (err2)
13521                         goto out;
13522
13523                 tp->timer.expires = jiffies + tp->timer_offset;
13524                 add_timer(&tp->timer);
13525
13526                 netif_device_attach(dev);
13527                 tg3_netif_start(tp);
13528
13529 out:
13530                 tg3_full_unlock(tp);
13531
13532                 if (!err2)
13533                         tg3_phy_start(tp);
13534         }
13535
13536         return err;
13537 }
13538
13539 static int tg3_resume(struct pci_dev *pdev)
13540 {
13541         struct net_device *dev = pci_get_drvdata(pdev);
13542         struct tg3 *tp = netdev_priv(dev);
13543         int err;
13544
13545         pci_restore_state(tp->pdev);
13546
13547         if (!netif_running(dev))
13548                 return 0;
13549
13550         err = tg3_set_power_state(tp, PCI_D0);
13551         if (err)
13552                 return err;
13553
13554         netif_device_attach(dev);
13555
13556         tg3_full_lock(tp, 0);
13557
13558         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13559         err = tg3_restart_hw(tp, 1);
13560         if (err)
13561                 goto out;
13562
13563         tp->timer.expires = jiffies + tp->timer_offset;
13564         add_timer(&tp->timer);
13565
13566         tg3_netif_start(tp);
13567
13568 out:
13569         tg3_full_unlock(tp);
13570
13571         if (!err)
13572                 tg3_phy_start(tp);
13573
13574         return err;
13575 }
13576
13577 static struct pci_driver tg3_driver = {
13578         .name           = DRV_MODULE_NAME,
13579         .id_table       = tg3_pci_tbl,
13580         .probe          = tg3_init_one,
13581         .remove         = __devexit_p(tg3_remove_one),
13582         .suspend        = tg3_suspend,
13583         .resume         = tg3_resume
13584 };
13585
13586 static int __init tg3_init(void)
13587 {
13588         return pci_register_driver(&tg3_driver);
13589 }
13590
13591 static void __exit tg3_cleanup(void)
13592 {
13593         pci_unregister_driver(&tg3_driver);
13594 }
13595
13596 module_init(tg3_init);
13597 module_exit(tg3_cleanup);