1 /*******************************************************************************
2 STMMAC Ethernet Driver -- MDIO bus implementation
3 Provides Bus interface for MII registers
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Carl Shaw <carl.shaw@st.com>
24 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 *******************************************************************************/
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/slab.h>
33 #define MII_BUSY 0x00000001
34 #define MII_WRITE 0x00000002
38 * @bus: points to the mii_bus structure
39 * @phyaddr: MII addr reg bits 15-11
40 * @phyreg: MII addr reg bits 10-6
41 * Description: it reads data from the MII register from within the phy device.
42 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
43 * accessing the PHY registers.
44 * Fortunately, it seems this has no drawback for the 7109 MAC.
46 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
48 struct net_device *ndev = bus->priv;
49 struct stmmac_priv *priv = netdev_priv(ndev);
50 unsigned int mii_address = priv->hw->mii.addr;
51 unsigned int mii_data = priv->hw->mii.data;
54 u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
55 ((phyreg << 6) & (0x000007C0)));
56 regValue |= MII_BUSY; /* in case of GMAC */
58 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
59 writel(regValue, priv->ioaddr + mii_address);
60 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
62 /* Read the data from the MII data register */
63 data = (int)readl(priv->ioaddr + mii_data);
70 * @bus: points to the mii_bus structure
71 * @phyaddr: MII addr reg bits 15-11
72 * @phyreg: MII addr reg bits 10-6
74 * Description: it writes the data into the MII register from within the device.
76 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
79 struct net_device *ndev = bus->priv;
80 struct stmmac_priv *priv = netdev_priv(ndev);
81 unsigned int mii_address = priv->hw->mii.addr;
82 unsigned int mii_data = priv->hw->mii.data;
85 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
90 /* Wait until any existing MII operation is complete */
91 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
93 /* Set the MII address register to write */
94 writel(phydata, priv->ioaddr + mii_data);
95 writel(value, priv->ioaddr + mii_address);
97 /* Wait until any existing MII operation is complete */
98 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
105 * @bus: points to the mii_bus structure
106 * Description: reset the MII bus
108 static int stmmac_mdio_reset(struct mii_bus *bus)
110 struct net_device *ndev = bus->priv;
111 struct stmmac_priv *priv = netdev_priv(ndev);
112 unsigned int mii_address = priv->hw->mii.addr;
114 if (priv->phy_reset) {
115 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
116 priv->phy_reset(priv->bsp_priv);
119 /* This is a workaround for problems with the STE101P PHY.
120 * It doesn't complete its reset until at least one clock cycle
121 * on MDC, so perform a dummy mdio read.
123 writel(0, priv->ioaddr + mii_address);
129 * stmmac_mdio_register
130 * @ndev: net device structure
131 * Description: it registers the MII bus
133 int stmmac_mdio_register(struct net_device *ndev)
136 struct mii_bus *new_bus;
138 struct stmmac_priv *priv = netdev_priv(ndev);
141 new_bus = mdiobus_alloc();
145 irqlist = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
146 if (irqlist == NULL) {
148 goto irqlist_alloc_fail;
151 /* Assign IRQ to phy at address phy_addr */
152 if (priv->phy_addr != -1)
153 irqlist[priv->phy_addr] = priv->phy_irq;
155 new_bus->name = "STMMAC MII Bus";
156 new_bus->read = &stmmac_mdio_read;
157 new_bus->write = &stmmac_mdio_write;
158 new_bus->reset = &stmmac_mdio_reset;
159 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
160 new_bus->priv = ndev;
161 new_bus->irq = irqlist;
162 new_bus->phy_mask = priv->phy_mask;
163 new_bus->parent = priv->device;
164 err = mdiobus_register(new_bus);
166 pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
167 goto bus_register_fail;
173 for (addr = 0; addr < 32; addr++) {
174 struct phy_device *phydev = new_bus->phy_map[addr];
176 if (priv->phy_addr == -1) {
177 priv->phy_addr = addr;
178 phydev->irq = priv->phy_irq;
179 irqlist[addr] = priv->phy_irq;
181 pr_info("%s: PHY ID %08x at %d IRQ %d (%s)%s\n",
182 ndev->name, phydev->phy_id, addr,
183 phydev->irq, dev_name(&phydev->dev),
184 (addr == priv->phy_addr) ? " active" : "");
190 pr_warning("%s: No PHY found\n", ndev->name);
201 * stmmac_mdio_unregister
202 * @ndev: net device structure
203 * Description: it unregisters the MII bus
205 int stmmac_mdio_unregister(struct net_device *ndev)
207 struct stmmac_priv *priv = netdev_priv(ndev);
209 mdiobus_unregister(priv->mii);
210 priv->mii->priv = NULL;