drivers/net/qlcnic/qlcnic_hw.c

   1 /*
   2  * Copyright (C) 2009 - QLogic Corporation.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called "COPYING".
  22  *
  23  */
  24
  25 #include "qlcnic.h"
  26
  27 #include <net/ip.h>
  28
  29 #define MASK(n) ((1ULL<<(n))-1)
  30 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  31
  32 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  33
  34 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  35 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  36 #define CRB_WINDOW_2M   (0x130060)
  37 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  38 #define CRB_INDIRECT_2M (0x1e0000UL)
  39
  40
  41 #ifndef readq
  42 static inline u64 readq(void __iomem *addr)
  43 {
  44         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  45 }
  46 #endif
  47
  48 #ifndef writeq
  49 static inline void writeq(u64 val, void __iomem *addr)
  50 {
  51         writel(((u32) (val)), (addr));
  52         writel(((u32) (val >> 32)), (addr + 4));
  53 }
  54 #endif
  55
  56 #define ADDR_IN_RANGE(addr, low, high)  \
  57         (((addr) < (high)) && ((addr) >= (low)))
  58
  59 #define PCI_OFFSET_FIRST_RANGE(adapter, off)    \
  60         ((adapter)->ahw.pci_base0 + (off))
  61
  62 static void __iomem *pci_base_offset(struct qlcnic_adapter *adapter,
  63                                             unsigned long off)
  64 {
  65         if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
  66                 return PCI_OFFSET_FIRST_RANGE(adapter, off);
  67
  68         return NULL;
  69 }
  70
  71 static const struct crb_128M_2M_block_map
  72 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  73     {{{0, 0,         0,         0} } },         /* 0: PCI */
  74     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  75           {1, 0x0110000, 0x0120000, 0x130000},
  76           {1, 0x0120000, 0x0122000, 0x124000},
  77           {1, 0x0130000, 0x0132000, 0x126000},
  78           {1, 0x0140000, 0x0142000, 0x128000},
  79           {1, 0x0150000, 0x0152000, 0x12a000},
  80           {1, 0x0160000, 0x0170000, 0x110000},
  81           {1, 0x0170000, 0x0172000, 0x12e000},
  82           {0, 0x0000000, 0x0000000, 0x000000},
  83           {0, 0x0000000, 0x0000000, 0x000000},
  84           {0, 0x0000000, 0x0000000, 0x000000},
  85           {0, 0x0000000, 0x0000000, 0x000000},
  86           {0, 0x0000000, 0x0000000, 0x000000},
  87           {0, 0x0000000, 0x0000000, 0x000000},
  88           {1, 0x01e0000, 0x01e0800, 0x122000},
  89           {0, 0x0000000, 0x0000000, 0x000000} } },
  90         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  91     {{{0, 0,         0,         0} } },     /* 3: */
  92     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  93     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  94     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  95     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  96     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  97       {0, 0x0000000, 0x0000000, 0x000000},
  98       {0, 0x0000000, 0x0000000, 0x000000},
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {0, 0x0000000, 0x0000000, 0x000000},
 108       {0, 0x0000000, 0x0000000, 0x000000},
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {1, 0x08f0000, 0x08f2000, 0x172000} } },
 112     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
 113       {0, 0x0000000, 0x0000000, 0x000000},
 114       {0, 0x0000000, 0x0000000, 0x000000},
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {0, 0x0000000, 0x0000000, 0x000000},
 124       {0, 0x0000000, 0x0000000, 0x000000},
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 128     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 129       {0, 0x0000000, 0x0000000, 0x000000},
 130       {0, 0x0000000, 0x0000000, 0x000000},
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {0, 0x0000000, 0x0000000, 0x000000},
 140       {0, 0x0000000, 0x0000000, 0x000000},
 141       {0, 0x0000000, 0x0000000, 0x000000},
 142       {0, 0x0000000, 0x0000000, 0x000000},
 143       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 144     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 145       {0, 0x0000000, 0x0000000, 0x000000},
 146       {0, 0x0000000, 0x0000000, 0x000000},
 147       {0, 0x0000000, 0x0000000, 0x000000},
 148       {0, 0x0000000, 0x0000000, 0x000000},
 149       {0, 0x0000000, 0x0000000, 0x000000},
 150       {0, 0x0000000, 0x0000000, 0x000000},
 151       {0, 0x0000000, 0x0000000, 0x000000},
 152       {0, 0x0000000, 0x0000000, 0x000000},
 153       {0, 0x0000000, 0x0000000, 0x000000},
 154       {0, 0x0000000, 0x0000000, 0x000000},
 155       {0, 0x0000000, 0x0000000, 0x000000},
 156       {0, 0x0000000, 0x0000000, 0x000000},
 157       {0, 0x0000000, 0x0000000, 0x000000},
 158       {0, 0x0000000, 0x0000000, 0x000000},
 159       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 160         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 161         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 162         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 163         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 164         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 165         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 166         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 167         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 168         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 169         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 170         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 171         {{{0, 0,         0,         0} } },     /* 23: */
 172         {{{0, 0,         0,         0} } },     /* 24: */
 173         {{{0, 0,         0,         0} } },     /* 25: */
 174         {{{0, 0,         0,         0} } },     /* 26: */
 175         {{{0, 0,         0,         0} } },     /* 27: */
 176         {{{0, 0,         0,         0} } },     /* 28: */
 177         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 178     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 179     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 180         {{{0} } },                              /* 32: PCI */
 181         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 182           {1, 0x2110000, 0x2120000, 0x130000},
 183           {1, 0x2120000, 0x2122000, 0x124000},
 184           {1, 0x2130000, 0x2132000, 0x126000},
 185           {1, 0x2140000, 0x2142000, 0x128000},
 186           {1, 0x2150000, 0x2152000, 0x12a000},
 187           {1, 0x2160000, 0x2170000, 0x110000},
 188           {1, 0x2170000, 0x2172000, 0x12e000},
 189           {0, 0x0000000, 0x0000000, 0x000000},
 190           {0, 0x0000000, 0x0000000, 0x000000},
 191           {0, 0x0000000, 0x0000000, 0x000000},
 192           {0, 0x0000000, 0x0000000, 0x000000},
 193           {0, 0x0000000, 0x0000000, 0x000000},
 194           {0, 0x0000000, 0x0000000, 0x000000},
 195           {0, 0x0000000, 0x0000000, 0x000000},
 196           {0, 0x0000000, 0x0000000, 0x000000} } },
 197         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 198         {{{0} } },                              /* 35: */
 199         {{{0} } },                              /* 36: */
 200         {{{0} } },                              /* 37: */
 201         {{{0} } },                              /* 38: */
 202         {{{0} } },                              /* 39: */
 203         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 204         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 205         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 206         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 207         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 208         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 209         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 210         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 211         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 212         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 213         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 214         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 215         {{{0} } },                              /* 52: */
 216         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 217         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 218         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 219         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 220         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 221         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 222         {{{0} } },                              /* 59: I2C0 */
 223         {{{0} } },                              /* 60: I2C1 */
 224         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 225         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 226         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 227 };
 228
 229 /*
 230  * top 12 bits of crb internal address (hub, agent)
 231  */
 232 static const unsigned crb_hub_agt[64] = {
 233         0,
 234         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 237         0,
 238         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 240         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 243         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 245         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 246         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 248         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 249         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 250         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 251         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 252         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 254         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 255         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 256         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 257         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 258         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 260         0,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 263         0,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 265         0,
 266         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 268         0,
 269         0,
 270         0,
 271         0,
 272         0,
 273         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 274         0,
 275         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 276         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 277         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 278         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 279         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 280         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 281         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 282         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 283         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 284         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 285         0,
 286         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 287         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 288         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 289         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 290         0,
 291         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 292         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 293         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 294         0,
 295         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 296         0,
 297 };
 298
 299 /*  PCI Windowing for DDR regions.  */
 300
 301 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 302
 303 int
 304 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 305 {
 306         int done = 0, timeout = 0;
 307
 308         while (!done) {
 309                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
 310                 if (done == 1)
 311                         break;
 312                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT)
 313                         return -EIO;
 314                 msleep(1);
 315         }
 316
 317         if (id_reg)
 318                 QLCWR32(adapter, id_reg, adapter->portnum);
 319
 320         return 0;
 321 }
 322
 323 void
 324 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 325 {
 326         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
 327 }
 328
 329 static int
 330 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 331                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 332 {
 333         u32 i, producer, consumer;
 334         struct qlcnic_cmd_buffer *pbuf;
 335         struct cmd_desc_type0 *cmd_desc;
 336         struct qlcnic_host_tx_ring *tx_ring;
 337
 338         i = 0;
 339
 340         if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
 341                 return -EIO;
 342
 343         tx_ring = adapter->tx_ring;
 344         __netif_tx_lock_bh(tx_ring->txq);
 345
 346         producer = tx_ring->producer;
 347         consumer = tx_ring->sw_consumer;
 348
 349         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 350                 netif_tx_stop_queue(tx_ring->txq);
 351                 __netif_tx_unlock_bh(tx_ring->txq);
 352                 adapter->stats.xmit_off++;
 353                 return -EBUSY;
 354         }
 355
 356         do {
 357                 cmd_desc = &cmd_desc_arr[i];
 358
 359                 pbuf = &tx_ring->cmd_buf_arr[producer];
 360                 pbuf->skb = NULL;
 361                 pbuf->frag_count = 0;
 362
 363                 memcpy(&tx_ring->desc_head[producer],
 364                         &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
 365
 366                 producer = get_next_index(producer, tx_ring->num_desc);
 367                 i++;
 368
 369         } while (i != nr_desc);
 370
 371         tx_ring->producer = producer;
 372
 373         qlcnic_update_cmd_producer(adapter, tx_ring);
 374
 375         __netif_tx_unlock_bh(tx_ring->txq);
 376
 377         return 0;
 378 }
 379
 380 static int
 381 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 382                                 unsigned op)
 383 {
 384         struct qlcnic_nic_req req;
 385         struct qlcnic_mac_req *mac_req;
 386         u64 word;
 387
 388         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 389         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 390
 391         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 392         req.req_hdr = cpu_to_le64(word);
 393
 394         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 395         mac_req->op = op;
 396         memcpy(mac_req->mac_addr, addr, 6);
 397
 398         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 399 }
 400
 401 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
 402 {
 403         struct list_head *head;
 404         struct qlcnic_mac_list_s *cur;
 405
 406         /* look up if already exists */
 407         list_for_each(head, &adapter->mac_list) {
 408                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 409                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
 410                         return 0;
 411         }
 412
 413         cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
 414         if (cur == NULL) {
 415                 dev_err(&adapter->netdev->dev,
 416                         "failed to add mac address filter\n");
 417                 return -ENOMEM;
 418         }
 419         memcpy(cur->mac_addr, addr, ETH_ALEN);
 420         list_add_tail(&cur->list, &adapter->mac_list);
 421
 422         return qlcnic_sre_macaddr_change(adapter,
 423                                 cur->mac_addr, QLCNIC_MAC_ADD);
 424 }
 425
 426 void qlcnic_set_multi(struct net_device *netdev)
 427 {
 428         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 429         struct dev_mc_list *mc_ptr;
 430         u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 431         u32 mode = VPORT_MISS_MODE_DROP;
 432
 433         if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
 434                 return;
 435
 436         qlcnic_nic_add_mac(adapter, adapter->mac_addr);
 437         qlcnic_nic_add_mac(adapter, bcast_addr);
 438
 439         if (netdev->flags & IFF_PROMISC) {
 440                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 441                 goto send_fw_cmd;
 442         }
 443
 444         if ((netdev->flags & IFF_ALLMULTI) ||
 445             (netdev_mc_count(netdev) > adapter->max_mc_count)) {
 446                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 447                 goto send_fw_cmd;
 448         }
 449
 450         if (!netdev_mc_empty(netdev)) {
 451                 netdev_for_each_mc_addr(mc_ptr, netdev) {
 452                         qlcnic_nic_add_mac(adapter, mc_ptr->dmi_addr);
 453                 }
 454         }
 455
 456 send_fw_cmd:
 457         qlcnic_nic_set_promisc(adapter, mode);
 458 }
 459
 460 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 461 {
 462         struct qlcnic_nic_req req;
 463         u64 word;
 464
 465         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 466
 467         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 468
 469         word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
 470                         ((u64)adapter->portnum << 16);
 471         req.req_hdr = cpu_to_le64(word);
 472
 473         req.words[0] = cpu_to_le64(mode);
 474
 475         return qlcnic_send_cmd_descs(adapter,
 476                                 (struct cmd_desc_type0 *)&req, 1);
 477 }
 478
 479 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
 480 {
 481         struct qlcnic_mac_list_s *cur;
 482         struct list_head *head = &adapter->mac_list;
 483
 484         while (!list_empty(head)) {
 485                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
 486                 qlcnic_sre_macaddr_change(adapter,
 487                                 cur->mac_addr, QLCNIC_MAC_DEL);
 488                 list_del(&cur->list);
 489                 kfree(cur);
 490         }
 491 }
 492
 493 #define QLCNIC_CONFIG_INTR_COALESCE     3
 494
 495 /*
 496  * Send the interrupt coalescing parameter set by ethtool to the card.
 497  */
 498 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
 499 {
 500         struct qlcnic_nic_req req;
 501         u64 word[6];
 502         int rv, i;
 503
 504         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 505
 506         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 507
 508         word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
 509         req.req_hdr = cpu_to_le64(word[0]);
 510
 511         memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
 512         for (i = 0; i < 6; i++)
 513                 req.words[i] = cpu_to_le64(word[i]);
 514
 515         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 516         if (rv != 0)
 517                 dev_err(&adapter->netdev->dev,
 518                         "Could not send interrupt coalescing parameters\n");
 519
 520         return rv;
 521 }
 522
 523 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 524 {
 525         struct qlcnic_nic_req req;
 526         u64 word;
 527         int rv;
 528
 529         if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
 530                 return 0;
 531
 532         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 533
 534         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 535
 536         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 537         req.req_hdr = cpu_to_le64(word);
 538
 539         req.words[0] = cpu_to_le64(enable);
 540
 541         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 542         if (rv != 0)
 543                 dev_err(&adapter->netdev->dev,
 544                         "Could not send configure hw lro request\n");
 545
 546         adapter->flags ^= QLCNIC_LRO_ENABLED;
 547
 548         return rv;
 549 }
 550
 551 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, int enable)
 552 {
 553         struct qlcnic_nic_req req;
 554         u64 word;
 555         int rv;
 556
 557         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 558                 return 0;
 559
 560         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 561
 562         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 563
 564         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 565                 ((u64)adapter->portnum << 16);
 566         req.req_hdr = cpu_to_le64(word);
 567
 568         req.words[0] = cpu_to_le64(enable);
 569
 570         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 571         if (rv != 0)
 572                 dev_err(&adapter->netdev->dev,
 573                         "Could not send configure bridge mode request\n");
 574
 575         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 576
 577         return rv;
 578 }
 579
 580
 581 #define RSS_HASHTYPE_IP_TCP     0x3
 582
 583 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
 584 {
 585         struct qlcnic_nic_req req;
 586         u64 word;
 587         int i, rv;
 588
 589         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 590                         0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 591                         0x255b0ec26d5a56daULL };
 592
 593
 594         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 595         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 596
 597         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 598         req.req_hdr = cpu_to_le64(word);
 599
 600         /*
 601          * RSS request:
 602          * bits 3-0: hash_method
 603          *      5-4: hash_type_ipv4
 604          *      7-6: hash_type_ipv6
 605          *        8: enable
 606          *        9: use indirection table
 607          *    47-10: reserved
 608          *    63-48: indirection table mask
 609          */
 610         word =  ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 611                 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 612                 ((u64)(enable & 0x1) << 8) |
 613                 ((0x7ULL) << 48);
 614         req.words[0] = cpu_to_le64(word);
 615         for (i = 0; i < 5; i++)
 616                 req.words[i+1] = cpu_to_le64(key[i]);
 617
 618         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 619         if (rv != 0)
 620                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 621
 622         return rv;
 623 }
 624
 625 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd)
 626 {
 627         struct qlcnic_nic_req req;
 628         u64 word;
 629         int rv;
 630
 631         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 632         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 633
 634         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 635         req.req_hdr = cpu_to_le64(word);
 636
 637         req.words[0] = cpu_to_le64(cmd);
 638         req.words[1] = cpu_to_le64(ip);
 639
 640         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 641         if (rv != 0)
 642                 dev_err(&adapter->netdev->dev,
 643                                 "could not notify %s IP 0x%x reuqest\n",
 644                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 645
 646         return rv;
 647 }
 648
 649 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 650 {
 651         struct qlcnic_nic_req req;
 652         u64 word;
 653         int rv;
 654
 655         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 656         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 657
 658         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 659         req.req_hdr = cpu_to_le64(word);
 660         req.words[0] = cpu_to_le64(enable | (enable << 8));
 661
 662         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 663         if (rv != 0)
 664                 dev_err(&adapter->netdev->dev,
 665                                 "could not configure link notification\n");
 666
 667         return rv;
 668 }
 669
 670 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 671 {
 672         struct qlcnic_nic_req req;
 673         u64 word;
 674         int rv;
 675
 676         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 677         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 678
 679         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 680                 ((u64)adapter->portnum << 16) |
 681                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 682
 683         req.req_hdr = cpu_to_le64(word);
 684
 685         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 686         if (rv != 0)
 687                 dev_err(&adapter->netdev->dev,
 688                                  "could not cleanup lro flows\n");
 689
 690         return rv;
 691 }
 692
 693 /*
 694  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 695  * @returns 0 on success, negative on failure
 696  */
 697
 698 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
 699 {
 700         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 701         int rc = 0;
 702
 703         if (mtu > P3_MAX_MTU) {
 704                 dev_err(&adapter->netdev->dev, "mtu > %d bytes unsupported\n",
 705                                                 P3_MAX_MTU);
 706                 return -EINVAL;
 707         }
 708
 709         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
 710
 711         if (!rc)
 712                 netdev->mtu = mtu;
 713
 714         return rc;
 715 }
 716
 717 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u64 *mac)
 718 {
 719         u32 crbaddr, mac_hi, mac_lo;
 720         int pci_func = adapter->ahw.pci_func;
 721
 722         crbaddr = CRB_MAC_BLOCK_START +
 723                 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
 724
 725         mac_lo = QLCRD32(adapter, crbaddr);
 726         mac_hi = QLCRD32(adapter, crbaddr+4);
 727
 728         if (pci_func & 1)
 729                 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
 730         else
 731                 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
 732
 733         return 0;
 734 }
 735
 736 /*
 737  * Changes the CRB window to the specified window.
 738  */
 739  /* Returns < 0 if off is not valid,
 740  *       1 if window access is needed. 'off' is set to offset from
 741  *         CRB space in 128M pci map
 742  *       0 if no window access is needed. 'off' is set to 2M addr
 743  * In: 'off' is offset from base in 128M pci map
 744  */
 745 static int
 746 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
 747                 ulong off, void __iomem **addr)
 748 {
 749         const struct crb_128M_2M_sub_block_map *m;
 750
 751         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
 752                 return -EINVAL;
 753
 754         off -= QLCNIC_PCI_CRBSPACE;
 755
 756         /*
 757          * Try direct map
 758          */
 759         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
 760
 761         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
 762                 *addr = adapter->ahw.pci_base0 + m->start_2M +
 763                         (off - m->start_128M);
 764                 return 0;
 765         }
 766
 767         /*
 768          * Not in direct map, use crb window
 769          */
 770         *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
 771         return 1;
 772 }
 773
 774 /*
 775  * In: 'off' is offset from CRB space in 128M pci map
 776  * Out: 'off' is 2M pci map addr
 777  * side effect: lock crb window
 778  */
 779 static void
 780 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
 781 {
 782         u32 window;
 783         void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
 784
 785         off -= QLCNIC_PCI_CRBSPACE;
 786
 787         window = CRB_HI(off);
 788
 789         if (adapter->ahw.crb_win == window)
 790                 return;
 791
 792         writel(window, addr);
 793         if (readl(addr) != window) {
 794                 if (printk_ratelimit())
 795                         dev_warn(&adapter->pdev->dev,
 796                                 "failed to set CRB window to %d off 0x%lx\n",
 797                                 window, off);
 798         }
 799         adapter->ahw.crb_win = window;
 800 }
 801
 802 int
 803 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
 804 {
 805         unsigned long flags;
 806         int rv;
 807         void __iomem *addr = NULL;
 808
 809         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 810
 811         if (rv == 0) {
 812                 writel(data, addr);
 813                 return 0;
 814         }
 815
 816         if (rv > 0) {
 817                 /* indirect access */
 818                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 819                 crb_win_lock(adapter);
 820                 qlcnic_pci_set_crbwindow_2M(adapter, off);
 821                 writel(data, addr);
 822                 crb_win_unlock(adapter);
 823                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 824                 return 0;
 825         }
 826
 827         dev_err(&adapter->pdev->dev,
 828                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 829         dump_stack();
 830         return -EIO;
 831 }
 832
 833 u32
 834 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
 835 {
 836         unsigned long flags;
 837         int rv;
 838         u32 data;
 839         void __iomem *addr = NULL;
 840
 841         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 842
 843         if (rv == 0)
 844                 return readl(addr);
 845
 846         if (rv > 0) {
 847                 /* indirect access */
 848                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 849                 crb_win_lock(adapter);
 850                 qlcnic_pci_set_crbwindow_2M(adapter, off);
 851                 data = readl(addr);
 852                 crb_win_unlock(adapter);
 853                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 854                 return data;
 855         }
 856
 857         dev_err(&adapter->pdev->dev,
 858                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 859         dump_stack();
 860         return -1;
 861 }
 862
 863
 864 void __iomem *
 865 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
 866 {
 867         void __iomem *addr = NULL;
 868
 869         WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
 870
 871         return addr;
 872 }
 873
 874
 875 static int
 876 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
 877                 u64 addr, u32 *start)
 878 {
 879         u32 window;
 880         struct pci_dev *pdev = adapter->pdev;
 881
 882         if ((addr & 0x00ff800) == 0xff800) {
 883                 if (printk_ratelimit())
 884                         dev_warn(&pdev->dev, "QM access not handled\n");
 885                 return -EIO;
 886         }
 887
 888         window = OCM_WIN_P3P(addr);
 889
 890         writel(window, adapter->ahw.ocm_win_crb);
 891         /* read back to flush */
 892         readl(adapter->ahw.ocm_win_crb);
 893
 894         adapter->ahw.ocm_win = window;
 895         *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
 896         return 0;
 897 }
 898
 899 static int
 900 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
 901                 u64 *data, int op)
 902 {
 903         void __iomem *addr, *mem_ptr = NULL;
 904         resource_size_t mem_base;
 905         int ret;
 906         u32 start;
 907
 908         mutex_lock(&adapter->ahw.mem_lock);
 909
 910         ret = qlcnic_pci_set_window_2M(adapter, off, &start);
 911         if (ret != 0)
 912                 goto unlock;
 913
 914         addr = pci_base_offset(adapter, start);
 915         if (addr)
 916                 goto noremap;
 917
 918         mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK);
 919
 920         mem_ptr = ioremap(mem_base, PAGE_SIZE);
 921         if (mem_ptr == NULL) {
 922                 ret = -EIO;
 923                 goto unlock;
 924         }
 925
 926         addr = mem_ptr + (start & (PAGE_SIZE - 1));
 927
 928 noremap:
 929         if (op == 0)    /* read */
 930                 *data = readq(addr);
 931         else            /* write */
 932                 writeq(*data, addr);
 933
 934 unlock:
 935         mutex_unlock(&adapter->ahw.mem_lock);
 936
 937         if (mem_ptr)
 938                 iounmap(mem_ptr);
 939         return ret;
 940 }
 941
 942 #define MAX_CTL_CHECK   1000
 943
 944 int
 945 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
 946                 u64 off, u64 data)
 947 {
 948         int i, j, ret;
 949         u32 temp, off8;
 950         u64 stride;
 951         void __iomem *mem_crb;
 952
 953         /* Only 64-bit aligned access */
 954         if (off & 7)
 955                 return -EIO;
 956
 957         /* P3 onward, test agent base for MIU and SIU is same */
 958         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
 959                                 QLCNIC_ADDR_QDR_NET_MAX_P3)) {
 960                 mem_crb = qlcnic_get_ioaddr(adapter,
 961                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
 962                 goto correct;
 963         }
 964
 965         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
 966                 mem_crb = qlcnic_get_ioaddr(adapter,
 967                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
 968                 goto correct;
 969         }
 970
 971         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
 972                 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
 973
 974         return -EIO;
 975
 976 correct:
 977         stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
 978
 979         off8 = off & ~(stride-1);
 980
 981         mutex_lock(&adapter->ahw.mem_lock);
 982
 983         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
 984         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
 985
 986         i = 0;
 987         if (stride == 16) {
 988                 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
 989                 writel((TA_CTL_START | TA_CTL_ENABLE),
 990                                 (mem_crb + TEST_AGT_CTRL));
 991
 992                 for (j = 0; j < MAX_CTL_CHECK; j++) {
 993                         temp = readl(mem_crb + TEST_AGT_CTRL);
 994                         if ((temp & TA_CTL_BUSY) == 0)
 995                                 break;
 996                 }
 997
 998                 if (j >= MAX_CTL_CHECK) {
 999                         ret = -EIO;
1000                         goto done;
1001                 }
1002
1003                 i = (off & 0xf) ? 0 : 2;
1004                 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1005                                 mem_crb + MIU_TEST_AGT_WRDATA(i));
1006                 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1007                                 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1008                 i = (off & 0xf) ? 2 : 0;
1009         }
1010
1011         writel(data & 0xffffffff,
1012                         mem_crb + MIU_TEST_AGT_WRDATA(i));
1013         writel((data >> 32) & 0xffffffff,
1014                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1015
1016         writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1017         writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1018                         (mem_crb + TEST_AGT_CTRL));
1019
1020         for (j = 0; j < MAX_CTL_CHECK; j++) {
1021                 temp = readl(mem_crb + TEST_AGT_CTRL);
1022                 if ((temp & TA_CTL_BUSY) == 0)
1023                         break;
1024         }
1025
1026         if (j >= MAX_CTL_CHECK) {
1027                 if (printk_ratelimit())
1028                         dev_err(&adapter->pdev->dev,
1029                                         "failed to write through agent\n");
1030                 ret = -EIO;
1031         } else
1032                 ret = 0;
1033
1034 done:
1035         mutex_unlock(&adapter->ahw.mem_lock);
1036
1037         return ret;
1038 }
1039
1040 int
1041 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1042                 u64 off, u64 *data)
1043 {
1044         int j, ret;
1045         u32 temp, off8;
1046         u64 val, stride;
1047         void __iomem *mem_crb;
1048
1049         /* Only 64-bit aligned access */
1050         if (off & 7)
1051                 return -EIO;
1052
1053         /* P3 onward, test agent base for MIU and SIU is same */
1054         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1055                                 QLCNIC_ADDR_QDR_NET_MAX_P3)) {
1056                 mem_crb = qlcnic_get_ioaddr(adapter,
1057                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1058                 goto correct;
1059         }
1060
1061         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1062                 mem_crb = qlcnic_get_ioaddr(adapter,
1063                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1064                 goto correct;
1065         }
1066
1067         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1068                 return qlcnic_pci_mem_access_direct(adapter,
1069                                 off, data, 0);
1070         }
1071
1072         return -EIO;
1073
1074 correct:
1075         stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1076
1077         off8 = off & ~(stride-1);
1078
1079         mutex_lock(&adapter->ahw.mem_lock);
1080
1081         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1082         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1083         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1084         writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1085
1086         for (j = 0; j < MAX_CTL_CHECK; j++) {
1087                 temp = readl(mem_crb + TEST_AGT_CTRL);
1088                 if ((temp & TA_CTL_BUSY) == 0)
1089                         break;
1090         }
1091
1092         if (j >= MAX_CTL_CHECK) {
1093                 if (printk_ratelimit())
1094                         dev_err(&adapter->pdev->dev,
1095                                         "failed to read through agent\n");
1096                 ret = -EIO;
1097         } else {
1098                 off8 = MIU_TEST_AGT_RDDATA_LO;
1099                 if ((stride == 16) && (off & 0xf))
1100                         off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1101
1102                 temp = readl(mem_crb + off8 + 4);
1103                 val = (u64)temp << 32;
1104                 val |= readl(mem_crb + off8);
1105                 *data = val;
1106                 ret = 0;
1107         }
1108
1109         mutex_unlock(&adapter->ahw.mem_lock);
1110
1111         return ret;
1112 }
1113
1114 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1115 {
1116         int offset, board_type, magic;
1117         struct pci_dev *pdev = adapter->pdev;
1118
1119         offset = QLCNIC_FW_MAGIC_OFFSET;
1120         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1121                 return -EIO;
1122
1123         if (magic != QLCNIC_BDINFO_MAGIC) {
1124                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1125                         magic);
1126                 return -EIO;
1127         }
1128
1129         offset = QLCNIC_BRDTYPE_OFFSET;
1130         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1131                 return -EIO;
1132
1133         adapter->ahw.board_type = board_type;
1134
1135         if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1136                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1137                 if ((gpio & 0x8000) == 0)
1138                         board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1139         }
1140
1141         switch (board_type) {
1142         case QLCNIC_BRDTYPE_P3_HMEZ:
1143         case QLCNIC_BRDTYPE_P3_XG_LOM:
1144         case QLCNIC_BRDTYPE_P3_10G_CX4:
1145         case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1146         case QLCNIC_BRDTYPE_P3_IMEZ:
1147         case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1148         case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1149         case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1150         case QLCNIC_BRDTYPE_P3_10G_XFP:
1151         case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1152                 adapter->ahw.port_type = QLCNIC_XGBE;
1153                 break;
1154         case QLCNIC_BRDTYPE_P3_REF_QG:
1155         case QLCNIC_BRDTYPE_P3_4_GB:
1156         case QLCNIC_BRDTYPE_P3_4_GB_MM:
1157                 adapter->ahw.port_type = QLCNIC_GBE;
1158                 break;
1159         case QLCNIC_BRDTYPE_P3_10G_TP:
1160                 adapter->ahw.port_type = (adapter->portnum < 2) ?
1161                         QLCNIC_XGBE : QLCNIC_GBE;
1162                 break;
1163         default:
1164                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1165                 adapter->ahw.port_type = QLCNIC_XGBE;
1166                 break;
1167         }
1168
1169         return 0;
1170 }
1171
1172 int
1173 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1174 {
1175         u32 wol_cfg;
1176
1177         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1178         if (wol_cfg & (1UL << adapter->portnum)) {
1179                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1180                 if (wol_cfg & (1 << adapter->portnum))
1181                         return 1;
1182         }
1183
1184         return 0;
1185 }
1186
1187 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1188 {
1189         struct qlcnic_nic_req   req;
1190         int rv;
1191         u64 word;
1192
1193         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1194         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1195
1196         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1197         req.req_hdr = cpu_to_le64(word);
1198
1199         req.words[0] = cpu_to_le64((u64)rate << 32);
1200         req.words[1] = cpu_to_le64(state);
1201
1202         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1203         if (rv)
1204                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1205
1206         return rv;
1207 }
1208
1209 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1210 {
1211         struct qlcnic_nic_req   req;
1212         int                     rv;
1213         u64                     word;
1214
1215         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1216         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1217
1218         word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1219                         ((u64)adapter->portnum << 16);
1220         req.req_hdr = cpu_to_le64(word);
1221         req.words[0] = cpu_to_le64(flag);
1222
1223         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1224         if (rv)
1225                 dev_err(&adapter->pdev->dev,
1226                         "%sting loopback mode failed.\n",
1227                                         flag ? "Set" : "Reset");
1228         return rv;
1229 }
1230
1231 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1232 {
1233         if (qlcnic_set_fw_loopback(adapter, 1))
1234                 return -EIO;
1235
1236         if (qlcnic_nic_set_promisc(adapter,
1237                                 VPORT_MISS_MODE_ACCEPT_ALL)) {
1238                 qlcnic_set_fw_loopback(adapter, 0);
1239                 return -EIO;
1240         }
1241
1242         msleep(1000);
1243         return 0;
1244 }
1245
1246 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1247 {
1248         int mode = VPORT_MISS_MODE_DROP;
1249         struct net_device *netdev = adapter->netdev;
1250
1251         qlcnic_set_fw_loopback(adapter, 0);
1252
1253         if (netdev->flags & IFF_PROMISC)
1254                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1255         else if (netdev->flags & IFF_ALLMULTI)
1256                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1257
1258         qlcnic_nic_set_promisc(adapter, mode);
1259 }