2 * Copyright (C) 2009 - QLogic Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/types.h>
31 #include <linux/ioport.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
37 #include <linux/tcp.h>
38 #include <linux/skbuff.h>
39 #include <linux/firmware.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/timer.h>
45 #include <linux/vmalloc.h>
48 #include <asm/byteorder.h>
50 #include "qlcnic_hdr.h"
52 #define _QLCNIC_LINUX_MAJOR 5
53 #define _QLCNIC_LINUX_MINOR 0
54 #define _QLCNIC_LINUX_SUBVERSION 7
55 #define QLCNIC_LINUX_VERSIONID "5.0.7"
56 #define QLCNIC_DRV_IDC_VER 0x01
58 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
59 #define _major(v) (((v) >> 24) & 0xff)
60 #define _minor(v) (((v) >> 16) & 0xff)
61 #define _build(v) ((v) & 0xffff)
63 /* version in image has weird encoding:
66 * 31:16 - build (little endian)
68 #define QLCNIC_DECODE_VERSION(v) \
69 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
71 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
72 #define QLCNIC_NUM_FLASH_SECTORS (64)
73 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
74 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
75 * QLCNIC_FLASH_SECTOR_SIZE)
77 #define RCV_DESC_RINGSIZE(rds_ring) \
78 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
79 #define RCV_BUFF_RINGSIZE(rds_ring) \
80 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
81 #define STATUS_DESC_RINGSIZE(sds_ring) \
82 (sizeof(struct status_desc) * (sds_ring)->num_desc)
83 #define TX_BUFF_RINGSIZE(tx_ring) \
84 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
85 #define TX_DESC_RINGSIZE(tx_ring) \
86 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
88 #define QLCNIC_P3P_A0 0x50
90 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
92 #define FIRST_PAGE_GROUP_START 0
93 #define FIRST_PAGE_GROUP_END 0x100000
95 #define P3_MAX_MTU (9600)
96 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
98 #define QLCNIC_P3_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
99 #define QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3_MAX_MTU)
100 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
101 #define QLCNIC_LRO_BUFFER_EXTRA 2048
103 /* Opcodes to be used with the commands */
104 #define TX_ETHER_PKT 0x01
105 #define TX_TCP_PKT 0x02
106 #define TX_UDP_PKT 0x03
107 #define TX_IP_PKT 0x04
108 #define TX_TCP_LSO 0x05
109 #define TX_TCP_LSO6 0x06
110 #define TX_IPSEC 0x07
111 #define TX_IPSEC_CMD 0x0a
112 #define TX_TCPV6_PKT 0x0b
113 #define TX_UDPV6_PKT 0x0c
116 #define MAX_TSO_HEADER_DESC 2
117 #define MGMT_CMD_DESC_RESV 4
118 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
119 + MGMT_CMD_DESC_RESV)
120 #define QLCNIC_MAX_TX_TIMEOUTS 2
123 * Following are the states of the Phantom. Phantom will set them and
124 * Host will read to check if the fields are correct.
126 #define PHAN_INITIALIZE_FAILED 0xffff
127 #define PHAN_INITIALIZE_COMPLETE 0xff01
129 /* Host writes the following to notify that it has done the init-handshake */
130 #define PHAN_INITIALIZE_ACK 0xf00f
131 #define PHAN_PEG_RCV_INITIALIZED 0xff01
133 #define NUM_RCV_DESC_RINGS 3
134 #define NUM_STS_DESC_RINGS 4
136 #define RCV_RING_NORMAL 0
137 #define RCV_RING_JUMBO 1
139 #define MIN_CMD_DESCRIPTORS 64
140 #define MIN_RCV_DESCRIPTORS 64
141 #define MIN_JUMBO_DESCRIPTORS 32
143 #define MAX_CMD_DESCRIPTORS 1024
144 #define MAX_RCV_DESCRIPTORS_1G 4096
145 #define MAX_RCV_DESCRIPTORS_10G 8192
146 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
147 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
149 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
150 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
151 #define MAX_RDS_RINGS 2
153 #define get_next_index(index, length) \
154 (((index) + 1) & ((length) - 1))
157 * Following data structures describe the descriptors that will be used.
158 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
159 * we are doing LSO (above the 1500 size packet) only.
162 #define FLAGS_VLAN_TAGGED 0x10
163 #define FLAGS_VLAN_OOB 0x40
165 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
166 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
167 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
168 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
169 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
170 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
172 #define qlcnic_set_tx_port(_desc, _port) \
173 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
175 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
176 ((_desc)->flags_opcode = \
177 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
179 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
180 ((_desc)->nfrags__length = \
181 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
183 struct cmd_desc_type0 {
184 u8 tcp_hdr_offset; /* For LSO only */
185 u8 ip_hdr_offset; /* For LSO only */
186 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
187 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
191 __le16 reference_handle;
193 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
194 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
195 __le16 conn_id; /* IPSec offoad only */
200 __le16 buffer_length[4];
204 u8 eth_addr[ETH_ALEN];
207 } __attribute__ ((aligned(64)));
209 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
211 __le16 reference_handle;
213 __le32 buffer_length; /* allocated buffer length (usually 2K) */
217 /* opcode field in status_desc */
218 #define QLCNIC_SYN_OFFLOAD 0x03
219 #define QLCNIC_RXPKT_DESC 0x04
220 #define QLCNIC_OLD_RXPKT_DESC 0x3f
221 #define QLCNIC_RESPONSE_DESC 0x05
222 #define QLCNIC_LRO_DESC 0x12
224 /* for status field in status_desc */
225 #define STATUS_CKSUM_OK (2)
227 /* owner bits of status_desc */
228 #define STATUS_OWNER_HOST (0x1ULL << 56)
229 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
231 /* Status descriptor:
232 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
233 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
234 53-55 desc_cnt, 56-57 owner, 58-63 opcode
236 #define qlcnic_get_sts_port(sts_data) \
238 #define qlcnic_get_sts_status(sts_data) \
239 (((sts_data) >> 4) & 0x0F)
240 #define qlcnic_get_sts_type(sts_data) \
241 (((sts_data) >> 8) & 0x0F)
242 #define qlcnic_get_sts_totallength(sts_data) \
243 (((sts_data) >> 12) & 0xFFFF)
244 #define qlcnic_get_sts_refhandle(sts_data) \
245 (((sts_data) >> 28) & 0xFFFF)
246 #define qlcnic_get_sts_prot(sts_data) \
247 (((sts_data) >> 44) & 0x0F)
248 #define qlcnic_get_sts_pkt_offset(sts_data) \
249 (((sts_data) >> 48) & 0x1F)
250 #define qlcnic_get_sts_desc_cnt(sts_data) \
251 (((sts_data) >> 53) & 0x7)
252 #define qlcnic_get_sts_opcode(sts_data) \
253 (((sts_data) >> 58) & 0x03F)
255 #define qlcnic_get_lro_sts_refhandle(sts_data) \
256 ((sts_data) & 0x0FFFF)
257 #define qlcnic_get_lro_sts_length(sts_data) \
258 (((sts_data) >> 16) & 0x0FFFF)
259 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
260 (((sts_data) >> 32) & 0x0FF)
261 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
262 (((sts_data) >> 40) & 0x0FF)
263 #define qlcnic_get_lro_sts_timestamp(sts_data) \
264 (((sts_data) >> 48) & 0x1)
265 #define qlcnic_get_lro_sts_type(sts_data) \
266 (((sts_data) >> 49) & 0x7)
267 #define qlcnic_get_lro_sts_push_flag(sts_data) \
268 (((sts_data) >> 52) & 0x1)
269 #define qlcnic_get_lro_sts_seq_number(sts_data) \
270 ((sts_data) & 0x0FFFFFFFF)
274 __le64 status_desc_data[2];
275 } __attribute__ ((aligned(16)));
277 /* UNIFIED ROMIMAGE */
278 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
279 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
280 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
281 #define QLCNIC_UNI_DIR_SECT_FW 0x7
284 #define QLCNIC_UNI_CHIP_REV_OFF 10
285 #define QLCNIC_UNI_FLAGS_OFF 11
286 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
287 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
288 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
290 struct uni_table_desc{
297 struct uni_data_desc{
303 /* Magic number to let user know flash is programmed */
304 #define QLCNIC_BDINFO_MAGIC 0x12345678
306 #define QLCNIC_BRDTYPE_P3_REF_QG 0x0021
307 #define QLCNIC_BRDTYPE_P3_HMEZ 0x0022
308 #define QLCNIC_BRDTYPE_P3_10G_CX4_LP 0x0023
309 #define QLCNIC_BRDTYPE_P3_4_GB 0x0024
310 #define QLCNIC_BRDTYPE_P3_IMEZ 0x0025
311 #define QLCNIC_BRDTYPE_P3_10G_SFP_PLUS 0x0026
312 #define QLCNIC_BRDTYPE_P3_10000_BASE_T 0x0027
313 #define QLCNIC_BRDTYPE_P3_XG_LOM 0x0028
314 #define QLCNIC_BRDTYPE_P3_4_GB_MM 0x0029
315 #define QLCNIC_BRDTYPE_P3_10G_SFP_CT 0x002a
316 #define QLCNIC_BRDTYPE_P3_10G_SFP_QT 0x002b
317 #define QLCNIC_BRDTYPE_P3_10G_CX4 0x0031
318 #define QLCNIC_BRDTYPE_P3_10G_XFP 0x0032
319 #define QLCNIC_BRDTYPE_P3_10G_TP 0x0080
321 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
323 /* Flash memory map */
324 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
325 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
326 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
327 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
329 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
330 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
331 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
332 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
334 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
335 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
337 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
338 #define QLCNIC_UNIFIED_ROMIMAGE 0
339 #define QLCNIC_FLASH_ROMIMAGE 1
340 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
342 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
343 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
345 extern char qlcnic_driver_name[];
347 /* Number of status descriptors to handle per interrupt */
348 #define MAX_STATUS_HANDLE (64)
351 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
352 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
354 struct qlcnic_skb_frag {
359 struct qlcnic_recv_crb {
360 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
361 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
362 u32 sw_int_mask[NUM_STS_DESC_RINGS];
365 /* Following defines are for the state of the buffers */
366 #define QLCNIC_BUFFER_FREE 0
367 #define QLCNIC_BUFFER_BUSY 1
370 * There will be one qlcnic_buffer per skb packet. These will be
371 * used to save the dma info for pci_unmap_page()
373 struct qlcnic_cmd_buffer {
375 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
379 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
380 struct qlcnic_rx_buffer {
381 struct list_head list;
388 #define QLCNIC_GBE 0x01
389 #define QLCNIC_XGBE 0x02
392 * One hardware_context{} per adapter
393 * contains interrupt info as well shared hardware info.
395 struct qlcnic_hardware_context {
396 void __iomem *pci_base0;
397 void __iomem *ocm_win_crb;
399 unsigned long pci_len0;
402 struct mutex mem_lock;
411 struct qlcnic_adapter_stats {
425 u64 skb_alloc_failure;
427 u64 rx_dma_map_error;
428 u64 tx_dma_map_error;
432 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
433 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
435 struct qlcnic_host_rds_ring {
441 void __iomem *crb_rcv_producer;
442 struct rcv_desc *desc_head;
443 struct qlcnic_rx_buffer *rx_buf_arr;
444 struct list_head free_list;
446 dma_addr_t phys_addr;
449 struct qlcnic_host_sds_ring {
452 void __iomem *crb_sts_consumer;
453 void __iomem *crb_intr_mask;
455 struct status_desc *desc_head;
456 struct qlcnic_adapter *adapter;
457 struct napi_struct napi;
458 struct list_head free_list[NUM_RCV_DESC_RINGS];
462 dma_addr_t phys_addr;
463 char name[IFNAMSIZ+4];
466 struct qlcnic_host_tx_ring {
470 void __iomem *crb_cmd_producer;
473 struct netdev_queue *txq;
475 struct qlcnic_cmd_buffer *cmd_buf_arr;
476 struct cmd_desc_type0 *desc_head;
477 dma_addr_t phys_addr;
478 dma_addr_t hw_cons_phys_addr;
482 * Receive context. There is one such structure per instance of the
483 * receive processing. Any state information that is relevant to
484 * the receive, and is must be in this structure. The global data may be
487 struct qlcnic_recv_context {
492 struct qlcnic_host_rds_ring *rds_rings;
493 struct qlcnic_host_sds_ring *sds_rings;
496 /* HW context creation */
498 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
499 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
500 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
502 #define QLCNIC_CDRP_CMD_BIT 0x80000000
505 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
506 * in the crb QLCNIC_CDRP_CRB_OFFSET.
508 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
509 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
511 #define QLCNIC_CDRP_RSP_OK 0x00000001
512 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
513 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
516 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
517 * the crb QLCNIC_CDRP_CRB_OFFSET.
519 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
520 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
522 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
523 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
524 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
525 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
526 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
527 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
528 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
529 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
530 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
531 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
532 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
533 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
534 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
535 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
536 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
537 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
538 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
539 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
540 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
541 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
542 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
543 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
544 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
545 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
546 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
547 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
548 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
550 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
551 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
552 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
553 #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023
554 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
555 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
556 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
557 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
558 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
559 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
561 #define QLCNIC_RCODE_SUCCESS 0
562 #define QLCNIC_RCODE_TIMEOUT 17
563 #define QLCNIC_DESTROY_CTX_RESET 0
566 * Capabilities Announced
568 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
569 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
570 #define QLCNIC_CAP0_LSO (1 << 6)
571 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
572 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
573 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
578 #define QLCNIC_HOST_CTX_STATE_FREED 0
579 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
585 struct qlcnic_hostrq_sds_ring {
586 __le64 host_phys_addr; /* Ring base addr */
587 __le32 ring_size; /* Ring entries */
589 __le16 rsvd; /* Padding */
592 struct qlcnic_hostrq_rds_ring {
593 __le64 host_phys_addr; /* Ring base addr */
594 __le64 buff_size; /* Packet buffer size */
595 __le32 ring_size; /* Ring entries */
596 __le32 ring_kind; /* Class of ring */
599 struct qlcnic_hostrq_rx_ctx {
600 __le64 host_rsp_dma_addr; /* Response dma'd here */
601 __le32 capabilities[4]; /* Flag bit vector */
602 __le32 host_int_crb_mode; /* Interrupt crb usage */
603 __le32 host_rds_crb_mode; /* RDS crb usage */
604 /* These ring offsets are relative to data[0] below */
605 __le32 rds_ring_offset; /* Offset to RDS config */
606 __le32 sds_ring_offset; /* Offset to SDS config */
607 __le16 num_rds_rings; /* Count of RDS rings */
608 __le16 num_sds_rings; /* Count of SDS rings */
609 __le16 valid_field_offset;
612 u8 reserved[128]; /* reserve space for future expansion*/
613 /* MUST BE 64-bit aligned.
614 The following is packed:
616 - N hostrq_sds_rings */
620 struct qlcnic_cardrsp_rds_ring{
621 __le32 host_producer_crb; /* Crb to use */
622 __le32 rsvd1; /* Padding */
625 struct qlcnic_cardrsp_sds_ring {
626 __le32 host_consumer_crb; /* Crb to use */
627 __le32 interrupt_crb; /* Crb to use */
630 struct qlcnic_cardrsp_rx_ctx {
631 /* These ring offsets are relative to data[0] below */
632 __le32 rds_ring_offset; /* Offset to RDS config */
633 __le32 sds_ring_offset; /* Offset to SDS config */
634 __le32 host_ctx_state; /* Starting State */
635 __le32 num_fn_per_port; /* How many PCI fn share the port */
636 __le16 num_rds_rings; /* Count of RDS rings */
637 __le16 num_sds_rings; /* Count of SDS rings */
638 __le16 context_id; /* Handle for context */
639 u8 phys_port; /* Physical id of port */
640 u8 virt_port; /* Virtual/Logical id of port */
641 u8 reserved[128]; /* save space for future expansion */
642 /* MUST BE 64-bit aligned.
643 The following is packed:
644 - N cardrsp_rds_rings
645 - N cardrs_sds_rings */
649 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
650 (sizeof(HOSTRQ_RX) + \
651 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
652 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
654 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
655 (sizeof(CARDRSP_RX) + \
656 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
657 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
663 struct qlcnic_hostrq_cds_ring {
664 __le64 host_phys_addr; /* Ring base addr */
665 __le32 ring_size; /* Ring entries */
666 __le32 rsvd; /* Padding */
669 struct qlcnic_hostrq_tx_ctx {
670 __le64 host_rsp_dma_addr; /* Response dma'd here */
671 __le64 cmd_cons_dma_addr; /* */
672 __le64 dummy_dma_addr; /* */
673 __le32 capabilities[4]; /* Flag bit vector */
674 __le32 host_int_crb_mode; /* Interrupt crb usage */
675 __le32 rsvd1; /* Padding */
676 __le16 rsvd2; /* Padding */
677 __le16 interrupt_ctl;
679 __le16 rsvd3; /* Padding */
680 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
681 u8 reserved[128]; /* future expansion */
684 struct qlcnic_cardrsp_cds_ring {
685 __le32 host_producer_crb; /* Crb to use */
686 __le32 interrupt_crb; /* Crb to use */
689 struct qlcnic_cardrsp_tx_ctx {
690 __le32 host_ctx_state; /* Starting state */
691 __le16 context_id; /* Handle for context */
692 u8 phys_port; /* Physical id of port */
693 u8 virt_port; /* Virtual/Logical id of port */
694 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
695 u8 reserved[128]; /* future expansion */
698 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
699 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
703 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
704 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
705 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
706 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
708 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
709 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
710 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
711 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
712 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
717 #define MC_COUNT_P3 38
719 #define QLCNIC_MAC_NOOP 0
720 #define QLCNIC_MAC_ADD 1
721 #define QLCNIC_MAC_DEL 2
723 struct qlcnic_mac_list_s {
724 struct list_head list;
725 uint8_t mac_addr[ETH_ALEN+2];
729 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
730 * adjusted based on configured MTU.
732 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
733 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
734 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
735 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
737 #define QLCNIC_INTR_DEFAULT 0x04
739 union qlcnic_nic_intr_coalesce_data {
749 struct qlcnic_nic_intr_coalesce {
751 u16 rate_sample_time;
756 union qlcnic_nic_intr_coalesce_data normal;
757 union qlcnic_nic_intr_coalesce_data low;
758 union qlcnic_nic_intr_coalesce_data high;
759 union qlcnic_nic_intr_coalesce_data irq;
762 #define QLCNIC_HOST_REQUEST 0x13
763 #define QLCNIC_REQUEST 0x14
765 #define QLCNIC_MAC_EVENT 0x1
767 #define QLCNIC_IP_UP 2
768 #define QLCNIC_IP_DOWN 3
771 * Driver --> Firmware
773 #define QLCNIC_H2C_OPCODE_START 0
774 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
775 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
776 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
777 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
778 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
779 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
780 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
781 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
782 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
783 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
784 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
785 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
786 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
787 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
788 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
789 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
790 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
791 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
792 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19
793 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
794 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
795 #define QLCNIC_C2C_OPCODE 22
796 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
797 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
798 #define QLCNIC_H2C_OPCODE_LAST 25
800 * Firmware --> Driver
803 #define QLCNIC_C2H_OPCODE_START 128
804 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
805 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
806 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
807 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
808 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
809 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
810 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
811 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
812 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
813 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
814 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
815 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
816 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
817 #define QLCNIC_C2H_OPCODE_LAST 142
819 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
820 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
821 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
823 #define QLCNIC_LRO_REQUEST_CLEANUP 4
825 /* Capabilites received */
826 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
827 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
828 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
829 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
832 #define LINKEVENT_MODULE_NOT_PRESENT 1
833 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
834 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
835 #define LINKEVENT_MODULE_OPTICAL_LRM 4
836 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
837 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
838 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
839 #define LINKEVENT_MODULE_TWINAX 8
841 #define LINKSPEED_10GBPS 10000
842 #define LINKSPEED_1GBPS 1000
843 #define LINKSPEED_100MBPS 100
844 #define LINKSPEED_10MBPS 10
846 #define LINKSPEED_ENCODED_10MBPS 0
847 #define LINKSPEED_ENCODED_100MBPS 1
848 #define LINKSPEED_ENCODED_1GBPS 2
850 #define LINKEVENT_AUTONEG_DISABLED 0
851 #define LINKEVENT_AUTONEG_ENABLED 1
853 #define LINKEVENT_HALF_DUPLEX 0
854 #define LINKEVENT_FULL_DUPLEX 1
856 #define LINKEVENT_LINKSPEED_MBPS 0
857 #define LINKEVENT_LINKSPEED_ENCODED 1
859 #define AUTO_FW_RESET_ENABLED 0x01
860 /* firmware response header:
861 * 63:58 - message type
865 * 47:40 - completion id
870 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
871 ((msg_hdr >> 32) & 0xFF)
873 struct qlcnic_fw_msg {
883 struct qlcnic_nic_req {
889 struct qlcnic_mac_req {
895 #define QLCNIC_MSI_ENABLED 0x02
896 #define QLCNIC_MSIX_ENABLED 0x04
897 #define QLCNIC_LRO_ENABLED 0x08
898 #define QLCNIC_LRO_DISABLED 0x00
899 #define QLCNIC_BRIDGE_ENABLED 0X10
900 #define QLCNIC_DIAG_ENABLED 0x20
901 #define QLCNIC_ESWITCH_ENABLED 0x40
902 #define QLCNIC_IS_MSI_FAMILY(adapter) \
903 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
905 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
906 #define QLCNIC_MSIX_TBL_SPACE 8192
907 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
908 #define QLCNIC_MSIX_TBL_PGSIZE 4096
910 #define QLCNIC_NETDEV_WEIGHT 128
911 #define QLCNIC_ADAPTER_UP_MAGIC 777
913 #define __QLCNIC_FW_ATTACHED 0
914 #define __QLCNIC_DEV_UP 1
915 #define __QLCNIC_RESETTING 2
916 #define __QLCNIC_START_FW 4
917 #define __QLCNIC_AER 5
919 #define QLCNIC_INTERRUPT_TEST 1
920 #define QLCNIC_LOOPBACK_TEST 2
922 struct qlcnic_adapter {
923 struct qlcnic_hardware_context ahw;
925 struct net_device *netdev;
926 struct pci_dev *pdev;
927 struct list_head mac_list;
929 spinlock_t tx_clean_lock;
984 u8 mac_addr[ETH_ALEN];
988 struct qlcnic_npar_info *npars;
989 struct qlcnic_eswitch *eswitch;
990 struct qlcnic_nic_template *nic_ops;
992 struct qlcnic_adapter_stats stats;
994 struct qlcnic_recv_context recv_ctx;
995 struct qlcnic_host_tx_ring *tx_ring;
997 void __iomem *tgt_mask_reg;
998 void __iomem *tgt_status_reg;
999 void __iomem *crb_int_state_reg;
1000 void __iomem *isr_int_vec;
1002 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1004 struct delayed_work fw_work;
1006 struct qlcnic_nic_intr_coalesce coal;
1008 unsigned long state;
1009 __le32 file_prd_off; /*File fw product offset*/
1011 const struct firmware *fw;
1014 struct qlcnic_info {
1016 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1018 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1020 __le32 capabilities;
1032 struct qlcnic_pci_info {
1033 __le16 id; /* pci function id */
1034 __le16 active; /* 1 = Enabled */
1035 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1036 __le16 default_port; /* default port number */
1038 __le16 tx_min_bw; /* Multiple of 100mbpc */
1040 __le16 reserved1[2];
1046 struct qlcnic_npar_info {
1060 struct qlcnic_eswitch {
1064 u8 active_ucast_filters;
1065 u8 max_ucast_filters;
1066 u8 max_active_vlans;
1069 #define QLCNIC_SWITCH_ENABLE BIT_1
1070 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1071 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1072 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1076 /* Return codes for Error handling */
1077 #define QL_STATUS_INVALID_PARAM -1
1081 #define MAX_VLAN_ID 4095
1082 #define MIN_VLAN_ID 2
1083 #define MAX_TX_QUEUES 1
1084 #define MAX_RX_QUEUES 4
1085 #define DEFAULT_MAC_LEARN 1
1087 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan <= MAX_VLAN_ID)
1088 #define IS_VALID_BW(bw) (bw >= MIN_BW && bw <= MAX_BW)
1089 #define IS_VALID_TX_QUEUES(que) (que > 0 && que <= MAX_TX_QUEUES)
1090 #define IS_VALID_RX_QUEUES(que) (que > 0 && que <= MAX_RX_QUEUES)
1091 #define IS_VALID_MODE(mode) (mode == 0 || mode == 1)
1093 struct qlcnic_pci_func_cfg {
1103 struct qlcnic_npar_func_cfg {
1114 struct qlcnic_pm_func_cfg {
1121 struct qlcnic_esw_func_cfg {
1131 #define QLCNIC_STATS_VERSION 1
1132 #define QLCNIC_STATS_PORT 1
1133 #define QLCNIC_STATS_ESWITCH 2
1134 #define QLCNIC_QUERY_RX_COUNTER 0
1135 #define QLCNIC_QUERY_TX_COUNTER 1
1136 struct __qlcnic_esw_statistics {
1141 __le64 unicast_frames;
1142 __le64 multicast_frames;
1143 __le64 broadcast_frames;
1144 __le64 dropped_frames;
1146 __le64 local_frames;
1151 struct qlcnic_esw_statistics {
1152 struct __qlcnic_esw_statistics rx;
1153 struct __qlcnic_esw_statistics tx;
1156 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1157 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1159 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1160 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1161 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1162 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1163 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1164 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1166 #define ADDR_IN_RANGE(addr, low, high) \
1167 (((addr) < (high)) && ((addr) >= (low)))
1169 #define QLCRD32(adapter, off) \
1170 (qlcnic_hw_read_wx_2M(adapter, off))
1171 #define QLCWR32(adapter, off, val) \
1172 (qlcnic_hw_write_wx_2M(adapter, off, val))
1174 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1175 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1177 #define qlcnic_rom_lock(a) \
1178 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1179 #define qlcnic_rom_unlock(a) \
1180 qlcnic_pcie_sem_unlock((a), 2)
1181 #define qlcnic_phy_lock(a) \
1182 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1183 #define qlcnic_phy_unlock(a) \
1184 qlcnic_pcie_sem_unlock((a), 3)
1185 #define qlcnic_api_lock(a) \
1186 qlcnic_pcie_sem_lock((a), 5, 0)
1187 #define qlcnic_api_unlock(a) \
1188 qlcnic_pcie_sem_unlock((a), 5)
1189 #define qlcnic_sw_lock(a) \
1190 qlcnic_pcie_sem_lock((a), 6, 0)
1191 #define qlcnic_sw_unlock(a) \
1192 qlcnic_pcie_sem_unlock((a), 6)
1193 #define crb_win_lock(a) \
1194 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1195 #define crb_win_unlock(a) \
1196 qlcnic_pcie_sem_unlock((a), 7)
1198 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1199 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1200 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1202 /* Functions from qlcnic_init.c */
1203 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1204 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1205 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1206 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1207 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1208 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1209 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1211 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1212 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1213 u8 *bytes, size_t size);
1214 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1215 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1217 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1219 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1220 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1222 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1223 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1225 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1226 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1227 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1229 int qlcnic_init_firmware(struct qlcnic_adapter *adapter);
1230 void qlcnic_watchdog_task(struct work_struct *work);
1231 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
1232 struct qlcnic_host_rds_ring *rds_ring);
1233 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1234 void qlcnic_set_multi(struct net_device *netdev);
1235 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1236 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1237 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1238 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1239 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd);
1240 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1241 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1243 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1244 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1245 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1246 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1247 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1248 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1249 struct qlcnic_host_tx_ring *tx_ring);
1250 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u8 *mac);
1251 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter);
1252 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter);
1253 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1255 /* Functions from qlcnic_main.c */
1256 int qlcnic_reset_context(struct qlcnic_adapter *);
1257 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1258 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1259 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1260 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1261 int qlcnic_check_loopback_buff(unsigned char *data);
1262 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1263 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1265 /* Management functions */
1266 int qlcnic_set_mac_address(struct qlcnic_adapter *, u8*);
1267 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1268 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1269 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1270 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1271 int qlcnic_reset_partition(struct qlcnic_adapter *, u8);
1273 /* eSwitch management functions */
1274 int qlcnic_get_eswitch_capabilities(struct qlcnic_adapter *, u8,
1275 struct qlcnic_eswitch *);
1276 int qlcnic_get_eswitch_status(struct qlcnic_adapter *, u8,
1277 struct qlcnic_eswitch *);
1278 int qlcnic_toggle_eswitch(struct qlcnic_adapter *, u8, u8);
1279 int qlcnic_config_switch_port(struct qlcnic_adapter *, u8, int, u8, u8,
1281 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1282 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1283 struct __qlcnic_esw_statistics *);
1284 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1285 struct __qlcnic_esw_statistics *);
1286 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1287 extern int qlcnic_config_tso;
1290 * QLOGIC Board information
1293 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1294 struct qlcnic_brdinfo {
1295 unsigned short vendor;
1296 unsigned short device;
1297 unsigned short sub_vendor;
1298 unsigned short sub_device;
1299 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1302 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1303 {0x1077, 0x8020, 0x1077, 0x203,
1304 "8200 Series Single Port 10GbE Converged Network Adapter "
1305 "(TCP/IP Networking)"},
1306 {0x1077, 0x8020, 0x1077, 0x207,
1307 "8200 Series Dual Port 10GbE Converged Network Adapter "
1308 "(TCP/IP Networking)"},
1309 {0x1077, 0x8020, 0x1077, 0x20b,
1310 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1311 {0x1077, 0x8020, 0x1077, 0x20c,
1312 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1313 {0x1077, 0x8020, 0x1077, 0x20f,
1314 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1315 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1318 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1320 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1323 if (tx_ring->producer < tx_ring->sw_consumer)
1324 return tx_ring->sw_consumer - tx_ring->producer;
1326 return tx_ring->sw_consumer + tx_ring->num_desc -
1330 extern const struct ethtool_ops qlcnic_ethtool_ops;
1332 struct qlcnic_nic_template {
1333 int (*get_mac_addr) (struct qlcnic_adapter *, u8*);
1334 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1335 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1336 int (*start_firmware) (struct qlcnic_adapter *);
1339 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1340 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1341 printk(KERN_INFO "%s: %s: " _fmt, \
1342 dev_name(&adapter->pdev->dev), \
1343 __func__, ##_args); \
1346 #endif /* __QLCNIC_H_ */