2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2009 Cavium Networks
9 #include <linux/capability.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/if_vlan.h>
16 #include <linux/phy.h>
17 #include <linux/spinlock.h>
19 #include <asm/octeon/octeon.h>
20 #include <asm/octeon/cvmx-mixx-defs.h>
21 #include <asm/octeon/cvmx-agl-defs.h>
23 #define DRV_NAME "octeon_mgmt"
24 #define DRV_VERSION "2.0"
25 #define DRV_DESCRIPTION \
26 "Cavium Networks Octeon MII (management) port Network Driver"
28 #define OCTEON_MGMT_NAPI_WEIGHT 16
31 * Ring sizes that are powers of two allow for more efficient modulo
34 #define OCTEON_MGMT_RX_RING_SIZE 512
35 #define OCTEON_MGMT_TX_RING_SIZE 128
37 /* Allow 8 bytes for vlan and FCS. */
38 #define OCTEON_MGMT_RX_HEADROOM (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
40 union mgmt_port_ring_entry {
44 /* Length of the buffer/packet in bytes */
46 /* For TX, signals that the packet should be timestamped */
48 /* The RX error code */
50 #define RING_ENTRY_CODE_DONE 0xf
51 #define RING_ENTRY_CODE_MORE 0x10
52 /* Physical address of the buffer */
58 struct net_device *netdev;
62 dma_addr_t tx_ring_handle;
64 unsigned int tx_next_clean;
65 unsigned int tx_current_fill;
66 /* The tx_list lock also protects the ring related variables */
67 struct sk_buff_head tx_list;
69 /* RX variables only touched in napi_poll. No locking necessary. */
71 dma_addr_t rx_ring_handle;
73 unsigned int rx_next_fill;
74 unsigned int rx_current_fill;
75 struct sk_buff_head rx_list;
78 unsigned int last_duplex;
79 unsigned int last_link;
81 struct napi_struct napi;
82 struct tasklet_struct tx_clean_tasklet;
83 struct phy_device *phydev;
86 static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable)
89 union cvmx_mixx_intena mix_intena;
92 spin_lock_irqsave(&p->lock, flags);
93 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
94 mix_intena.s.ithena = enable ? 1 : 0;
95 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
96 spin_unlock_irqrestore(&p->lock, flags);
99 static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable)
102 union cvmx_mixx_intena mix_intena;
105 spin_lock_irqsave(&p->lock, flags);
106 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
107 mix_intena.s.othena = enable ? 1 : 0;
108 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
109 spin_unlock_irqrestore(&p->lock, flags);
112 static inline void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p)
114 octeon_mgmt_set_rx_irq(p, 1);
117 static inline void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p)
119 octeon_mgmt_set_rx_irq(p, 0);
122 static inline void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p)
124 octeon_mgmt_set_tx_irq(p, 1);
127 static inline void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p)
129 octeon_mgmt_set_tx_irq(p, 0);
132 static unsigned int ring_max_fill(unsigned int ring_size)
134 return ring_size - 8;
137 static unsigned int ring_size_to_bytes(unsigned int ring_size)
139 return ring_size * sizeof(union mgmt_port_ring_entry);
142 static void octeon_mgmt_rx_fill_ring(struct net_device *netdev)
144 struct octeon_mgmt *p = netdev_priv(netdev);
147 while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) {
149 union mgmt_port_ring_entry re;
152 /* CN56XX pass 1 needs 8 bytes of padding. */
153 size = netdev->mtu + OCTEON_MGMT_RX_HEADROOM + 8 + NET_IP_ALIGN;
155 skb = netdev_alloc_skb(netdev, size);
158 skb_reserve(skb, NET_IP_ALIGN);
159 __skb_queue_tail(&p->rx_list, skb);
163 re.s.addr = dma_map_single(p->dev, skb->data,
167 /* Put it in the ring. */
168 p->rx_ring[p->rx_next_fill] = re.d64;
169 dma_sync_single_for_device(p->dev, p->rx_ring_handle,
170 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
173 (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE;
174 p->rx_current_fill++;
176 cvmx_write_csr(CVMX_MIXX_IRING2(port), 1);
180 static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p)
183 union cvmx_mixx_orcnt mix_orcnt;
184 union mgmt_port_ring_entry re;
189 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
190 while (mix_orcnt.s.orcnt) {
191 dma_sync_single_for_cpu(p->dev, p->tx_ring_handle,
192 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
195 spin_lock_irqsave(&p->tx_list.lock, flags);
197 re.d64 = p->tx_ring[p->tx_next_clean];
199 (p->tx_next_clean + 1) % OCTEON_MGMT_TX_RING_SIZE;
200 skb = __skb_dequeue(&p->tx_list);
203 mix_orcnt.s.orcnt = 1;
205 /* Acknowledge to hardware that we have the buffer. */
206 cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64);
207 p->tx_current_fill--;
209 spin_unlock_irqrestore(&p->tx_list.lock, flags);
211 dma_unmap_single(p->dev, re.s.addr, re.s.len,
213 dev_kfree_skb_any(skb);
216 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
219 if (cleaned && netif_queue_stopped(p->netdev))
220 netif_wake_queue(p->netdev);
223 static void octeon_mgmt_clean_tx_tasklet(unsigned long arg)
225 struct octeon_mgmt *p = (struct octeon_mgmt *)arg;
226 octeon_mgmt_clean_tx_buffers(p);
227 octeon_mgmt_enable_tx_irq(p);
230 static void octeon_mgmt_update_rx_stats(struct net_device *netdev)
232 struct octeon_mgmt *p = netdev_priv(netdev);
237 /* These reads also clear the count registers. */
238 drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port));
239 bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port));
242 /* Do an atomic update. */
243 spin_lock_irqsave(&p->lock, flags);
244 netdev->stats.rx_errors += bad;
245 netdev->stats.rx_dropped += drop;
246 spin_unlock_irqrestore(&p->lock, flags);
250 static void octeon_mgmt_update_tx_stats(struct net_device *netdev)
252 struct octeon_mgmt *p = netdev_priv(netdev);
256 union cvmx_agl_gmx_txx_stat0 s0;
257 union cvmx_agl_gmx_txx_stat1 s1;
259 /* These reads also clear the count registers. */
260 s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port));
261 s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port));
263 if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) {
264 /* Do an atomic update. */
265 spin_lock_irqsave(&p->lock, flags);
266 netdev->stats.tx_errors += s0.s.xsdef + s0.s.xscol;
267 netdev->stats.collisions += s1.s.scol + s1.s.mcol;
268 spin_unlock_irqrestore(&p->lock, flags);
273 * Dequeue a receive skb and its corresponding ring entry. The ring
274 * entry is returned, *pskb is updated to point to the skb.
276 static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p,
277 struct sk_buff **pskb)
279 union mgmt_port_ring_entry re;
281 dma_sync_single_for_cpu(p->dev, p->rx_ring_handle,
282 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
285 re.d64 = p->rx_ring[p->rx_next];
286 p->rx_next = (p->rx_next + 1) % OCTEON_MGMT_RX_RING_SIZE;
287 p->rx_current_fill--;
288 *pskb = __skb_dequeue(&p->rx_list);
290 dma_unmap_single(p->dev, re.s.addr,
291 ETH_FRAME_LEN + OCTEON_MGMT_RX_HEADROOM,
298 static int octeon_mgmt_receive_one(struct octeon_mgmt *p)
301 struct net_device *netdev = p->netdev;
302 union cvmx_mixx_ircnt mix_ircnt;
303 union mgmt_port_ring_entry re;
305 struct sk_buff *skb2;
306 struct sk_buff *skb_new;
307 union mgmt_port_ring_entry re2;
311 re.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb);
312 if (likely(re.s.code == RING_ENTRY_CODE_DONE)) {
313 /* A good packet, send it up. */
314 skb_put(skb, re.s.len);
316 skb->protocol = eth_type_trans(skb, netdev);
317 netdev->stats.rx_packets++;
318 netdev->stats.rx_bytes += skb->len;
319 netdev->last_rx = jiffies;
320 netif_receive_skb(skb);
322 } else if (re.s.code == RING_ENTRY_CODE_MORE) {
324 * Packet split across skbs. This can happen if we
325 * increase the MTU. Buffers that are already in the
326 * rx ring can then end up being too small. As the rx
327 * ring is refilled, buffers sized for the new MTU
328 * will be used and we should go back to the normal
331 skb_put(skb, re.s.len);
333 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
334 if (re2.s.code != RING_ENTRY_CODE_MORE
335 && re2.s.code != RING_ENTRY_CODE_DONE)
337 skb_put(skb2, re2.s.len);
338 skb_new = skb_copy_expand(skb, 0, skb2->len,
342 if (skb_copy_bits(skb2, 0, skb_tail_pointer(skb_new),
345 skb_put(skb_new, skb2->len);
346 dev_kfree_skb_any(skb);
347 dev_kfree_skb_any(skb2);
349 } while (re2.s.code == RING_ENTRY_CODE_MORE);
352 /* Some other error, discard it. */
353 dev_kfree_skb_any(skb);
355 * Error statistics are accumulated in
356 * octeon_mgmt_update_rx_stats.
361 /* Discard the whole mess. */
362 dev_kfree_skb_any(skb);
363 dev_kfree_skb_any(skb2);
364 while (re2.s.code == RING_ENTRY_CODE_MORE) {
365 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
366 dev_kfree_skb_any(skb2);
368 netdev->stats.rx_errors++;
371 /* Tell the hardware we processed a packet. */
373 mix_ircnt.s.ircnt = 1;
374 cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64);
379 static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget)
382 unsigned int work_done = 0;
383 union cvmx_mixx_ircnt mix_ircnt;
387 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
388 while (work_done < budget && mix_ircnt.s.ircnt) {
390 rc = octeon_mgmt_receive_one(p);
394 /* Check for more packets. */
395 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
398 octeon_mgmt_rx_fill_ring(p->netdev);
403 static int octeon_mgmt_napi_poll(struct napi_struct *napi, int budget)
405 struct octeon_mgmt *p = container_of(napi, struct octeon_mgmt, napi);
406 struct net_device *netdev = p->netdev;
407 unsigned int work_done = 0;
409 work_done = octeon_mgmt_receive_packets(p, budget);
411 if (work_done < budget) {
412 /* We stopped because no more packets were available. */
414 octeon_mgmt_enable_rx_irq(p);
416 octeon_mgmt_update_rx_stats(netdev);
421 /* Reset the hardware to clean state. */
422 static void octeon_mgmt_reset_hw(struct octeon_mgmt *p)
424 union cvmx_mixx_ctl mix_ctl;
425 union cvmx_mixx_bist mix_bist;
426 union cvmx_agl_gmx_bist agl_gmx_bist;
429 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
431 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port));
432 } while (mix_ctl.s.busy);
434 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
435 cvmx_read_csr(CVMX_MIXX_CTL(p->port));
438 mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port));
440 dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n",
441 (unsigned long long)mix_bist.u64);
443 agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);
444 if (agl_gmx_bist.u64)
445 dev_warn(p->dev, "AGL failed BIST (0x%016llx)\n",
446 (unsigned long long)agl_gmx_bist.u64);
449 struct octeon_mgmt_cam_state {
455 static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs,
460 for (i = 0; i < 6; i++)
461 cs->cam[i] |= (u64)addr[i] << (8 * (cs->cam_index));
462 cs->cam_mask |= (1ULL << cs->cam_index);
466 static void octeon_mgmt_set_rx_filtering(struct net_device *netdev)
468 struct octeon_mgmt *p = netdev_priv(netdev);
471 union cvmx_agl_gmx_rxx_adr_ctl adr_ctl;
472 union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx;
474 unsigned int prev_packet_enable;
475 unsigned int cam_mode = 1; /* 1 - Accept on CAM match */
476 unsigned int multicast_mode = 1; /* 1 - Reject all multicast. */
477 struct octeon_mgmt_cam_state cam_state;
478 struct dev_addr_list *list;
479 struct list_head *pos;
480 int available_cam_entries;
482 memset(&cam_state, 0, sizeof(cam_state));
484 if ((netdev->flags & IFF_PROMISC) || netdev->dev_addrs.count > 7) {
486 available_cam_entries = 8;
489 * One CAM entry for the primary address, leaves seven
490 * for the secondary addresses.
492 available_cam_entries = 7 - netdev->dev_addrs.count;
495 if (netdev->flags & IFF_MULTICAST) {
496 if (cam_mode == 0 || (netdev->flags & IFF_ALLMULTI)
497 || netdev->mc_count > available_cam_entries)
498 multicast_mode = 2; /* 1 - Accept all multicast. */
500 multicast_mode = 0; /* 0 - Use CAM. */
504 /* Add primary address. */
505 octeon_mgmt_cam_state_add(&cam_state, netdev->dev_addr);
506 list_for_each(pos, &netdev->dev_addrs.list) {
507 struct netdev_hw_addr *hw_addr;
508 hw_addr = list_entry(pos, struct netdev_hw_addr, list);
509 octeon_mgmt_cam_state_add(&cam_state, hw_addr->addr);
513 if (multicast_mode == 0) {
514 i = netdev->mc_count;
515 list = netdev->mc_list;
517 octeon_mgmt_cam_state_add(&cam_state, list->da_addr);
523 spin_lock_irqsave(&p->lock, flags);
525 /* Disable packet I/O. */
526 agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
527 prev_packet_enable = agl_gmx_prtx.s.en;
528 agl_gmx_prtx.s.en = 0;
529 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
533 adr_ctl.s.cam_mode = cam_mode;
534 adr_ctl.s.mcst = multicast_mode;
535 adr_ctl.s.bcst = 1; /* Allow broadcast */
537 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64);
539 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]);
540 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]);
541 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]);
542 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]);
543 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]);
544 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]);
545 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask);
547 /* Restore packet I/O. */
548 agl_gmx_prtx.s.en = prev_packet_enable;
549 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
551 spin_unlock_irqrestore(&p->lock, flags);
554 static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr)
556 struct sockaddr *sa = addr;
558 if (!is_valid_ether_addr(sa->sa_data))
559 return -EADDRNOTAVAIL;
561 memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
563 octeon_mgmt_set_rx_filtering(netdev);
568 static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu)
570 struct octeon_mgmt *p = netdev_priv(netdev);
572 int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM;
575 * Limit the MTU to make sure the ethernet packets are between
576 * 64 bytes and 16383 bytes.
578 if (size_without_fcs < 64 || size_without_fcs > 16383) {
579 dev_warn(p->dev, "MTU must be between %d and %d.\n",
580 64 - OCTEON_MGMT_RX_HEADROOM,
581 16383 - OCTEON_MGMT_RX_HEADROOM);
585 netdev->mtu = new_mtu;
587 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs);
588 cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port),
589 (size_without_fcs + 7) & 0xfff8);
594 static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id)
596 struct net_device *netdev = dev_id;
597 struct octeon_mgmt *p = netdev_priv(netdev);
599 union cvmx_mixx_isr mixx_isr;
601 mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port));
603 /* Clear any pending interrupts */
604 cvmx_write_csr(CVMX_MIXX_ISR(port),
605 cvmx_read_csr(CVMX_MIXX_ISR(port)));
606 cvmx_read_csr(CVMX_MIXX_ISR(port));
608 if (mixx_isr.s.irthresh) {
609 octeon_mgmt_disable_rx_irq(p);
610 napi_schedule(&p->napi);
612 if (mixx_isr.s.orthresh) {
613 octeon_mgmt_disable_tx_irq(p);
614 tasklet_schedule(&p->tx_clean_tasklet);
620 static int octeon_mgmt_ioctl(struct net_device *netdev,
621 struct ifreq *rq, int cmd)
623 struct octeon_mgmt *p = netdev_priv(netdev);
625 if (!netif_running(netdev))
631 return phy_mii_ioctl(p->phydev, if_mii(rq), cmd);
634 static void octeon_mgmt_adjust_link(struct net_device *netdev)
636 struct octeon_mgmt *p = netdev_priv(netdev);
638 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
640 int link_changed = 0;
642 spin_lock_irqsave(&p->lock, flags);
643 if (p->phydev->link) {
646 if (p->last_duplex != p->phydev->duplex) {
647 p->last_duplex = p->phydev->duplex;
649 cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
650 prtx_cfg.s.duplex = p->phydev->duplex;
651 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port),
658 p->last_link = p->phydev->link;
659 spin_unlock_irqrestore(&p->lock, flags);
661 if (link_changed != 0) {
662 if (link_changed > 0) {
663 netif_carrier_on(netdev);
664 pr_info("%s: Link is up - %d/%s\n", netdev->name,
666 DUPLEX_FULL == p->phydev->duplex ?
669 netif_carrier_off(netdev);
670 pr_info("%s: Link is down\n", netdev->name);
675 static int octeon_mgmt_init_phy(struct net_device *netdev)
677 struct octeon_mgmt *p = netdev_priv(netdev);
680 if (octeon_is_simulation()) {
681 /* No PHYs in the simulator. */
682 netif_carrier_on(netdev);
686 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", p->port);
688 p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0,
689 PHY_INTERFACE_MODE_MII);
691 if (IS_ERR(p->phydev)) {
696 phy_start_aneg(p->phydev);
701 static int octeon_mgmt_open(struct net_device *netdev)
703 struct octeon_mgmt *p = netdev_priv(netdev);
705 union cvmx_mixx_ctl mix_ctl;
706 union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode;
707 union cvmx_mixx_oring1 oring1;
708 union cvmx_mixx_iring1 iring1;
709 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
710 union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl;
711 union cvmx_mixx_irhwm mix_irhwm;
712 union cvmx_mixx_orhwm mix_orhwm;
713 union cvmx_mixx_intena mix_intena;
716 /* Allocate ring buffers. */
717 p->tx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
722 dma_map_single(p->dev, p->tx_ring,
723 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
726 p->tx_next_clean = 0;
727 p->tx_current_fill = 0;
730 p->rx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
735 dma_map_single(p->dev, p->rx_ring,
736 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
741 p->rx_current_fill = 0;
743 octeon_mgmt_reset_hw(p);
745 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
747 /* Bring it out of reset if needed. */
748 if (mix_ctl.s.reset) {
750 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
752 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
753 } while (mix_ctl.s.reset);
756 agl_gmx_inf_mode.u64 = 0;
757 agl_gmx_inf_mode.s.en = 1;
758 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
761 oring1.s.obase = p->tx_ring_handle >> 3;
762 oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE;
763 cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64);
766 iring1.s.ibase = p->rx_ring_handle >> 3;
767 iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE;
768 cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64);
770 /* Disable packet I/O. */
771 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
773 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
775 memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN);
776 octeon_mgmt_set_mac_address(netdev, &sa);
778 octeon_mgmt_change_mtu(netdev, netdev->mtu);
781 * Enable the port HW. Packets are not allowed until
782 * cvmx_mgmt_port_enable() is called.
785 mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */
786 mix_ctl.s.en = 1; /* Enable the port */
787 mix_ctl.s.nbtarb = 0; /* Arbitration mode */
788 /* MII CB-request FIFO programmable high watermark */
789 mix_ctl.s.mrq_hwm = 1;
790 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
792 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
793 || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
795 * Force compensation values, as they are not
796 * determined properly by HW
798 union cvmx_agl_gmx_drv_ctl drv_ctl;
800 drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);
802 drv_ctl.s.byp_en1 = 1;
806 drv_ctl.s.byp_en = 1;
810 cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
813 octeon_mgmt_rx_fill_ring(netdev);
815 /* Clear statistics. */
817 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1);
818 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0);
819 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0);
821 cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1);
822 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0);
823 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0);
825 /* Clear any pending interrupts */
826 cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port)));
828 if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name,
830 dev_err(p->dev, "request_irq(%d) failed.\n", p->irq);
834 /* Interrupt every single RX packet */
836 mix_irhwm.s.irhwm = 0;
837 cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64);
839 /* Interrupt when we have 5 or more packets to clean. */
841 mix_orhwm.s.orhwm = 5;
842 cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64);
844 /* Enable receive and transmit interrupts */
846 mix_intena.s.ithena = 1;
847 mix_intena.s.othena = 1;
848 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
851 /* Enable packet I/O. */
854 rxx_frm_ctl.s.pre_align = 1;
856 * When set, disables the length check for non-min sized pkts
857 * with padding in the client data.
859 rxx_frm_ctl.s.pad_len = 1;
860 /* When set, disables the length check for VLAN pkts */
861 rxx_frm_ctl.s.vlan_len = 1;
862 /* When set, PREAMBLE checking is less strict */
863 rxx_frm_ctl.s.pre_free = 1;
864 /* Control Pause Frames can match station SMAC */
865 rxx_frm_ctl.s.ctl_smac = 0;
866 /* Control Pause Frames can match globally assign Multicast address */
867 rxx_frm_ctl.s.ctl_mcst = 1;
868 /* Forward pause information to TX block */
869 rxx_frm_ctl.s.ctl_bck = 1;
870 /* Drop Control Pause Frames */
871 rxx_frm_ctl.s.ctl_drp = 1;
872 /* Strip off the preamble */
873 rxx_frm_ctl.s.pre_strp = 1;
875 * This port is configured to send PREAMBLE+SFD to begin every
876 * frame. GMX checks that the PREAMBLE is sent correctly.
878 rxx_frm_ctl.s.pre_chk = 1;
879 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64);
881 /* Enable the AGL block */
882 agl_gmx_inf_mode.u64 = 0;
883 agl_gmx_inf_mode.s.en = 1;
884 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
886 /* Configure the port duplex and enables */
887 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
888 prtx_cfg.s.tx_en = 1;
889 prtx_cfg.s.rx_en = 1;
892 prtx_cfg.s.duplex = p->last_duplex;
893 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
896 netif_carrier_off(netdev);
898 if (octeon_mgmt_init_phy(netdev)) {
899 dev_err(p->dev, "Cannot initialize PHY.\n");
903 netif_wake_queue(netdev);
904 napi_enable(&p->napi);
908 octeon_mgmt_reset_hw(p);
909 dma_unmap_single(p->dev, p->rx_ring_handle,
910 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
914 dma_unmap_single(p->dev, p->tx_ring_handle,
915 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
921 static int octeon_mgmt_stop(struct net_device *netdev)
923 struct octeon_mgmt *p = netdev_priv(netdev);
925 napi_disable(&p->napi);
926 netif_stop_queue(netdev);
929 phy_disconnect(p->phydev);
931 netif_carrier_off(netdev);
933 octeon_mgmt_reset_hw(p);
936 free_irq(p->irq, netdev);
938 /* dma_unmap is a nop on Octeon, so just free everything. */
939 skb_queue_purge(&p->tx_list);
940 skb_queue_purge(&p->rx_list);
942 dma_unmap_single(p->dev, p->rx_ring_handle,
943 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
947 dma_unmap_single(p->dev, p->tx_ring_handle,
948 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
956 static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev)
958 struct octeon_mgmt *p = netdev_priv(netdev);
960 union mgmt_port_ring_entry re;
965 re.s.addr = dma_map_single(p->dev, skb->data,
969 spin_lock_irqsave(&p->tx_list.lock, flags);
971 if (unlikely(p->tx_current_fill >=
972 ring_max_fill(OCTEON_MGMT_TX_RING_SIZE))) {
973 spin_unlock_irqrestore(&p->tx_list.lock, flags);
975 dma_unmap_single(p->dev, re.s.addr, re.s.len,
978 netif_stop_queue(netdev);
979 return NETDEV_TX_BUSY;
982 __skb_queue_tail(&p->tx_list, skb);
984 /* Put it in the ring. */
985 p->tx_ring[p->tx_next] = re.d64;
986 p->tx_next = (p->tx_next + 1) % OCTEON_MGMT_TX_RING_SIZE;
987 p->tx_current_fill++;
989 spin_unlock_irqrestore(&p->tx_list.lock, flags);
991 dma_sync_single_for_device(p->dev, p->tx_ring_handle,
992 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
995 netdev->stats.tx_packets++;
996 netdev->stats.tx_bytes += skb->len;
999 cvmx_write_csr(CVMX_MIXX_ORING2(port), 1);
1001 netdev->trans_start = jiffies;
1002 octeon_mgmt_clean_tx_buffers(p);
1003 octeon_mgmt_update_tx_stats(netdev);
1004 return NETDEV_TX_OK;
1007 #ifdef CONFIG_NET_POLL_CONTROLLER
1008 static void octeon_mgmt_poll_controller(struct net_device *netdev)
1010 struct octeon_mgmt *p = netdev_priv(netdev);
1012 octeon_mgmt_receive_packets(p, 16);
1013 octeon_mgmt_update_rx_stats(netdev);
1018 static void octeon_mgmt_get_drvinfo(struct net_device *netdev,
1019 struct ethtool_drvinfo *info)
1021 strncpy(info->driver, DRV_NAME, sizeof(info->driver));
1022 strncpy(info->version, DRV_VERSION, sizeof(info->version));
1023 strncpy(info->fw_version, "N/A", sizeof(info->fw_version));
1024 strncpy(info->bus_info, "N/A", sizeof(info->bus_info));
1026 info->testinfo_len = 0;
1027 info->regdump_len = 0;
1028 info->eedump_len = 0;
1031 static int octeon_mgmt_get_settings(struct net_device *netdev,
1032 struct ethtool_cmd *cmd)
1034 struct octeon_mgmt *p = netdev_priv(netdev);
1037 return phy_ethtool_gset(p->phydev, cmd);
1042 static int octeon_mgmt_set_settings(struct net_device *netdev,
1043 struct ethtool_cmd *cmd)
1045 struct octeon_mgmt *p = netdev_priv(netdev);
1047 if (!capable(CAP_NET_ADMIN))
1051 return phy_ethtool_sset(p->phydev, cmd);
1056 static const struct ethtool_ops octeon_mgmt_ethtool_ops = {
1057 .get_drvinfo = octeon_mgmt_get_drvinfo,
1058 .get_link = ethtool_op_get_link,
1059 .get_settings = octeon_mgmt_get_settings,
1060 .set_settings = octeon_mgmt_set_settings
1063 static const struct net_device_ops octeon_mgmt_ops = {
1064 .ndo_open = octeon_mgmt_open,
1065 .ndo_stop = octeon_mgmt_stop,
1066 .ndo_start_xmit = octeon_mgmt_xmit,
1067 .ndo_set_rx_mode = octeon_mgmt_set_rx_filtering,
1068 .ndo_set_multicast_list = octeon_mgmt_set_rx_filtering,
1069 .ndo_set_mac_address = octeon_mgmt_set_mac_address,
1070 .ndo_do_ioctl = octeon_mgmt_ioctl,
1071 .ndo_change_mtu = octeon_mgmt_change_mtu,
1072 #ifdef CONFIG_NET_POLL_CONTROLLER
1073 .ndo_poll_controller = octeon_mgmt_poll_controller,
1077 static int __init octeon_mgmt_probe(struct platform_device *pdev)
1079 struct resource *res_irq;
1080 struct net_device *netdev;
1081 struct octeon_mgmt *p;
1084 netdev = alloc_etherdev(sizeof(struct octeon_mgmt));
1088 dev_set_drvdata(&pdev->dev, netdev);
1089 p = netdev_priv(netdev);
1090 netif_napi_add(netdev, &p->napi, octeon_mgmt_napi_poll,
1091 OCTEON_MGMT_NAPI_WEIGHT);
1094 p->dev = &pdev->dev;
1097 snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port);
1099 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1103 p->irq = res_irq->start;
1104 spin_lock_init(&p->lock);
1106 skb_queue_head_init(&p->tx_list);
1107 skb_queue_head_init(&p->rx_list);
1108 tasklet_init(&p->tx_clean_tasklet,
1109 octeon_mgmt_clean_tx_tasklet, (unsigned long)p);
1111 netdev->netdev_ops = &octeon_mgmt_ops;
1112 netdev->ethtool_ops = &octeon_mgmt_ethtool_ops;
1115 /* The mgmt ports get the first N MACs. */
1116 for (i = 0; i < 6; i++)
1117 netdev->dev_addr[i] = octeon_bootinfo->mac_addr_base[i];
1118 netdev->dev_addr[5] += p->port;
1120 if (p->port >= octeon_bootinfo->mac_addr_count)
1122 "Error %s: Using MAC outside of the assigned range: "
1123 "%02x:%02x:%02x:%02x:%02x:%02x\n", netdev->name,
1124 netdev->dev_addr[0], netdev->dev_addr[1],
1125 netdev->dev_addr[2], netdev->dev_addr[3],
1126 netdev->dev_addr[4], netdev->dev_addr[5]);
1128 if (register_netdev(netdev))
1131 dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
1134 free_netdev(netdev);
1138 static int __exit octeon_mgmt_remove(struct platform_device *pdev)
1140 struct net_device *netdev = dev_get_drvdata(&pdev->dev);
1142 unregister_netdev(netdev);
1143 free_netdev(netdev);
1147 static struct platform_driver octeon_mgmt_driver = {
1149 .name = "octeon_mgmt",
1150 .owner = THIS_MODULE,
1152 .probe = octeon_mgmt_probe,
1153 .remove = __exit_p(octeon_mgmt_remove),
1156 extern void octeon_mdiobus_force_mod_depencency(void);
1158 static int __init octeon_mgmt_mod_init(void)
1160 /* Force our mdiobus driver module to be loaded first. */
1161 octeon_mdiobus_force_mod_depencency();
1162 return platform_driver_register(&octeon_mgmt_driver);
1165 static void __exit octeon_mgmt_mod_exit(void)
1167 platform_driver_unregister(&octeon_mgmt_driver);
1170 module_init(octeon_mgmt_mod_init);
1171 module_exit(octeon_mgmt_mod_exit);
1173 MODULE_DESCRIPTION(DRV_DESCRIPTION);
1174 MODULE_AUTHOR("David Daney");
1175 MODULE_LICENSE("GPL");
1176 MODULE_VERSION(DRV_VERSION);