2 * drivers/net/ks8851_mll.c
3 * Copyright (c) 2009 Micrel Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 * KS8851 16bit MLL chip from Micrel Inc.
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/cache.h>
32 #include <linux/crc32.h>
33 #include <linux/mii.h>
34 #include <linux/platform_device.h>
35 #include <linux/delay.h>
37 #define DRV_NAME "ks8851_mll"
39 static u8 KS_DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 };
40 #define MAX_RECV_FRAMES 32
41 #define MAX_BUF_SIZE 2048
42 #define TX_BUF_SIZE 2000
43 #define RX_BUF_SIZE 2000
46 #define CCR_EEPROM (1 << 9)
47 #define CCR_SPI (1 << 8)
48 #define CCR_8BIT (1 << 7)
49 #define CCR_16BIT (1 << 6)
50 #define CCR_32BIT (1 << 5)
51 #define CCR_SHARED (1 << 4)
52 #define CCR_32PIN (1 << 0)
54 /* MAC address registers */
60 #define OBCR_ODS_16MA (1 << 6)
63 #define EEPCR_EESA (1 << 4)
64 #define EEPCR_EESB (1 << 3)
65 #define EEPCR_EEDO (1 << 2)
66 #define EEPCR_EESCK (1 << 1)
67 #define EEPCR_EECS (1 << 0)
70 #define MBIR_TXMBF (1 << 12)
71 #define MBIR_TXMBFA (1 << 11)
72 #define MBIR_RXMBF (1 << 4)
73 #define MBIR_RXMBFA (1 << 3)
76 #define GRR_QMU (1 << 1)
77 #define GRR_GSR (1 << 0)
80 #define WFCR_MPRXE (1 << 7)
81 #define WFCR_WF3E (1 << 3)
82 #define WFCR_WF2E (1 << 2)
83 #define WFCR_WF1E (1 << 1)
84 #define WFCR_WF0E (1 << 0)
86 #define KS_WF0CRC0 0x30
87 #define KS_WF0CRC1 0x32
88 #define KS_WF0BM0 0x34
89 #define KS_WF0BM1 0x36
90 #define KS_WF0BM2 0x38
91 #define KS_WF0BM3 0x3A
93 #define KS_WF1CRC0 0x40
94 #define KS_WF1CRC1 0x42
95 #define KS_WF1BM0 0x44
96 #define KS_WF1BM1 0x46
97 #define KS_WF1BM2 0x48
98 #define KS_WF1BM3 0x4A
100 #define KS_WF2CRC0 0x50
101 #define KS_WF2CRC1 0x52
102 #define KS_WF2BM0 0x54
103 #define KS_WF2BM1 0x56
104 #define KS_WF2BM2 0x58
105 #define KS_WF2BM3 0x5A
107 #define KS_WF3CRC0 0x60
108 #define KS_WF3CRC1 0x62
109 #define KS_WF3BM0 0x64
110 #define KS_WF3BM1 0x66
111 #define KS_WF3BM2 0x68
112 #define KS_WF3BM3 0x6A
115 #define TXCR_TCGICMP (1 << 8)
116 #define TXCR_TCGUDP (1 << 7)
117 #define TXCR_TCGTCP (1 << 6)
118 #define TXCR_TCGIP (1 << 5)
119 #define TXCR_FTXQ (1 << 4)
120 #define TXCR_TXFCE (1 << 3)
121 #define TXCR_TXPE (1 << 2)
122 #define TXCR_TXCRC (1 << 1)
123 #define TXCR_TXE (1 << 0)
126 #define TXSR_TXLC (1 << 13)
127 #define TXSR_TXMC (1 << 12)
128 #define TXSR_TXFID_MASK (0x3f << 0)
129 #define TXSR_TXFID_SHIFT (0)
130 #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
133 #define KS_RXCR1 0x74
134 #define RXCR1_FRXQ (1 << 15)
135 #define RXCR1_RXUDPFCC (1 << 14)
136 #define RXCR1_RXTCPFCC (1 << 13)
137 #define RXCR1_RXIPFCC (1 << 12)
138 #define RXCR1_RXPAFMA (1 << 11)
139 #define RXCR1_RXFCE (1 << 10)
140 #define RXCR1_RXEFE (1 << 9)
141 #define RXCR1_RXMAFMA (1 << 8)
142 #define RXCR1_RXBE (1 << 7)
143 #define RXCR1_RXME (1 << 6)
144 #define RXCR1_RXUE (1 << 5)
145 #define RXCR1_RXAE (1 << 4)
146 #define RXCR1_RXINVF (1 << 1)
147 #define RXCR1_RXE (1 << 0)
148 #define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
149 RXCR1_RXMAFMA | RXCR1_RXPAFMA)
151 #define KS_RXCR2 0x76
152 #define RXCR2_SRDBL_MASK (0x7 << 5)
153 #define RXCR2_SRDBL_SHIFT (5)
154 #define RXCR2_SRDBL_4B (0x0 << 5)
155 #define RXCR2_SRDBL_8B (0x1 << 5)
156 #define RXCR2_SRDBL_16B (0x2 << 5)
157 #define RXCR2_SRDBL_32B (0x3 << 5)
158 /* #define RXCR2_SRDBL_FRAME (0x4 << 5) */
159 #define RXCR2_IUFFP (1 << 4)
160 #define RXCR2_RXIUFCEZ (1 << 3)
161 #define RXCR2_UDPLFE (1 << 2)
162 #define RXCR2_RXICMPFCC (1 << 1)
163 #define RXCR2_RXSAF (1 << 0)
165 #define KS_TXMIR 0x78
167 #define KS_RXFHSR 0x7C
168 #define RXFSHR_RXFV (1 << 15)
169 #define RXFSHR_RXICMPFCS (1 << 13)
170 #define RXFSHR_RXIPFCS (1 << 12)
171 #define RXFSHR_RXTCPFCS (1 << 11)
172 #define RXFSHR_RXUDPFCS (1 << 10)
173 #define RXFSHR_RXBF (1 << 7)
174 #define RXFSHR_RXMF (1 << 6)
175 #define RXFSHR_RXUF (1 << 5)
176 #define RXFSHR_RXMR (1 << 4)
177 #define RXFSHR_RXFT (1 << 3)
178 #define RXFSHR_RXFTL (1 << 2)
179 #define RXFSHR_RXRF (1 << 1)
180 #define RXFSHR_RXCE (1 << 0)
181 #define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\
182 RXFSHR_RXFTL | RXFSHR_RXMR |\
183 RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
185 #define KS_RXFHBCR 0x7E
186 #define RXFHBCR_CNT_MASK 0x0FFF
188 #define KS_TXQCR 0x80
189 #define TXQCR_AETFE (1 << 2)
190 #define TXQCR_TXQMAM (1 << 1)
191 #define TXQCR_METFE (1 << 0)
193 #define KS_RXQCR 0x82
194 #define RXQCR_RXDTTS (1 << 12)
195 #define RXQCR_RXDBCTS (1 << 11)
196 #define RXQCR_RXFCTS (1 << 10)
197 #define RXQCR_RXIPHTOE (1 << 9)
198 #define RXQCR_RXDTTE (1 << 7)
199 #define RXQCR_RXDBCTE (1 << 6)
200 #define RXQCR_RXFCTE (1 << 5)
201 #define RXQCR_ADRFE (1 << 4)
202 #define RXQCR_SDA (1 << 3)
203 #define RXQCR_RRXEF (1 << 0)
204 #define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
206 #define KS_TXFDPR 0x84
207 #define TXFDPR_TXFPAI (1 << 14)
208 #define TXFDPR_TXFP_MASK (0x7ff << 0)
209 #define TXFDPR_TXFP_SHIFT (0)
211 #define KS_RXFDPR 0x86
212 #define RXFDPR_RXFPAI (1 << 14)
214 #define KS_RXDTTR 0x8C
215 #define KS_RXDBCTR 0x8E
219 #define IRQ_LCI (1 << 15)
220 #define IRQ_TXI (1 << 14)
221 #define IRQ_RXI (1 << 13)
222 #define IRQ_RXOI (1 << 11)
223 #define IRQ_TXPSI (1 << 9)
224 #define IRQ_RXPSI (1 << 8)
225 #define IRQ_TXSAI (1 << 6)
226 #define IRQ_RXWFDI (1 << 5)
227 #define IRQ_RXMPDI (1 << 4)
228 #define IRQ_LDI (1 << 3)
229 #define IRQ_EDI (1 << 2)
230 #define IRQ_SPIBEI (1 << 1)
231 #define IRQ_DEDI (1 << 0)
233 #define KS_RXFCTR 0x9C
234 #define RXFCTR_THRESHOLD_MASK 0x00FF
237 #define RXFCTR_RXFC_MASK (0xff << 8)
238 #define RXFCTR_RXFC_SHIFT (8)
239 #define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
240 #define RXFCTR_RXFCT_MASK (0xff << 0)
241 #define RXFCTR_RXFCT_SHIFT (0)
243 #define KS_TXNTFSR 0x9E
245 #define KS_MAHTR0 0xA0
246 #define KS_MAHTR1 0xA2
247 #define KS_MAHTR2 0xA4
248 #define KS_MAHTR3 0xA6
250 #define KS_FCLWR 0xB0
251 #define KS_FCHWR 0xB2
252 #define KS_FCOWR 0xB4
254 #define KS_CIDER 0xC0
255 #define CIDER_ID 0x8870
256 #define CIDER_REV_MASK (0x7 << 1)
257 #define CIDER_REV_SHIFT (1)
258 #define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
262 #define IACR_RDEN (1 << 12)
263 #define IACR_TSEL_MASK (0x3 << 10)
264 #define IACR_TSEL_SHIFT (10)
265 #define IACR_TSEL_MIB (0x3 << 10)
266 #define IACR_ADDR_MASK (0x1f << 0)
267 #define IACR_ADDR_SHIFT (0)
269 #define KS_IADLR 0xD0
270 #define KS_IAHDR 0xD2
272 #define KS_PMECR 0xD4
273 #define PMECR_PME_DELAY (1 << 14)
274 #define PMECR_PME_POL (1 << 12)
275 #define PMECR_WOL_WAKEUP (1 << 11)
276 #define PMECR_WOL_MAGICPKT (1 << 10)
277 #define PMECR_WOL_LINKUP (1 << 9)
278 #define PMECR_WOL_ENERGY (1 << 8)
279 #define PMECR_AUTO_WAKE_EN (1 << 7)
280 #define PMECR_WAKEUP_NORMAL (1 << 6)
281 #define PMECR_WKEVT_MASK (0xf << 2)
282 #define PMECR_WKEVT_SHIFT (2)
283 #define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
284 #define PMECR_WKEVT_ENERGY (0x1 << 2)
285 #define PMECR_WKEVT_LINK (0x2 << 2)
286 #define PMECR_WKEVT_MAGICPKT (0x4 << 2)
287 #define PMECR_WKEVT_FRAME (0x8 << 2)
288 #define PMECR_PM_MASK (0x3 << 0)
289 #define PMECR_PM_SHIFT (0)
290 #define PMECR_PM_NORMAL (0x0 << 0)
291 #define PMECR_PM_ENERGY (0x1 << 0)
292 #define PMECR_PM_SOFTDOWN (0x2 << 0)
293 #define PMECR_PM_POWERSAVE (0x3 << 0)
295 /* Standard MII PHY data */
296 #define KS_P1MBCR 0xE4
297 #define P1MBCR_FORCE_FDX (1 << 8)
299 #define KS_P1MBSR 0xE6
300 #define P1MBSR_AN_COMPLETE (1 << 5)
301 #define P1MBSR_AN_CAPABLE (1 << 3)
302 #define P1MBSR_LINK_UP (1 << 2)
304 #define KS_PHY1ILR 0xE8
305 #define KS_PHY1IHR 0xEA
306 #define KS_P1ANAR 0xEC
307 #define KS_P1ANLPR 0xEE
309 #define KS_P1SCLMD 0xF4
310 #define P1SCLMD_LEDOFF (1 << 15)
311 #define P1SCLMD_TXIDS (1 << 14)
312 #define P1SCLMD_RESTARTAN (1 << 13)
313 #define P1SCLMD_DISAUTOMDIX (1 << 10)
314 #define P1SCLMD_FORCEMDIX (1 << 9)
315 #define P1SCLMD_AUTONEGEN (1 << 7)
316 #define P1SCLMD_FORCE100 (1 << 6)
317 #define P1SCLMD_FORCEFDX (1 << 5)
318 #define P1SCLMD_ADV_FLOW (1 << 4)
319 #define P1SCLMD_ADV_100BT_FDX (1 << 3)
320 #define P1SCLMD_ADV_100BT_HDX (1 << 2)
321 #define P1SCLMD_ADV_10BT_FDX (1 << 1)
322 #define P1SCLMD_ADV_10BT_HDX (1 << 0)
325 #define P1CR_HP_MDIX (1 << 15)
326 #define P1CR_REV_POL (1 << 13)
327 #define P1CR_OP_100M (1 << 10)
328 #define P1CR_OP_FDX (1 << 9)
329 #define P1CR_OP_MDI (1 << 7)
330 #define P1CR_AN_DONE (1 << 6)
331 #define P1CR_LINK_GOOD (1 << 5)
332 #define P1CR_PNTR_FLOW (1 << 4)
333 #define P1CR_PNTR_100BT_FDX (1 << 3)
334 #define P1CR_PNTR_100BT_HDX (1 << 2)
335 #define P1CR_PNTR_10BT_FDX (1 << 1)
336 #define P1CR_PNTR_10BT_HDX (1 << 0)
338 /* TX Frame control */
340 #define TXFR_TXIC (1 << 15)
341 #define TXFR_TXFID_MASK (0x3f << 0)
342 #define TXFR_TXFID_SHIFT (0)
345 #define P1SR_HP_MDIX (1 << 15)
346 #define P1SR_REV_POL (1 << 13)
347 #define P1SR_OP_100M (1 << 10)
348 #define P1SR_OP_FDX (1 << 9)
349 #define P1SR_OP_MDI (1 << 7)
350 #define P1SR_AN_DONE (1 << 6)
351 #define P1SR_LINK_GOOD (1 << 5)
352 #define P1SR_PNTR_FLOW (1 << 4)
353 #define P1SR_PNTR_100BT_FDX (1 << 3)
354 #define P1SR_PNTR_100BT_HDX (1 << 2)
355 #define P1SR_PNTR_10BT_FDX (1 << 1)
356 #define P1SR_PNTR_10BT_HDX (1 << 0)
358 #define ENUM_BUS_NONE 0
359 #define ENUM_BUS_8BIT 1
360 #define ENUM_BUS_16BIT 2
361 #define ENUM_BUS_32BIT 3
363 #define MAX_MCAST_LST 32
364 #define HW_MCAST_SIZE 8
365 #define MAC_ADDR_LEN 6
368 * union ks_tx_hdr - tx header data
369 * @txb: The header as bytes
370 * @txw: The header as 16bit, little-endian words
372 * A dual representation of the tx header data to allow
373 * access to individual bytes, and to allow 16bit accesses
374 * with 16bit alignment.
382 * struct ks_net - KS8851 driver private data
383 * @net_device : The network device we're bound to
384 * @hw_addr : start address of data register.
385 * @hw_addr_cmd : start address of command register.
386 * @txh : temporaly buffer to save status/length.
387 * @lock : Lock to ensure that the device is not accessed when busy.
388 * @pdev : Pointer to platform device.
389 * @mii : The MII state information for the mii calls.
390 * @frame_head_info : frame header information for multi-pkt rx.
391 * @statelock : Lock on this structure for tx list.
392 * @msg_enable : The message flags controlling driver output (see ethtool).
393 * @frame_cnt : number of frames received.
394 * @bus_width : i/o bus width.
395 * @irq : irq number assigned to this device.
396 * @rc_rxqcr : Cached copy of KS_RXQCR.
397 * @rc_txcr : Cached copy of KS_TXCR.
398 * @rc_ier : Cached copy of KS_IER.
399 * @sharedbus : Multipex(addr and data bus) mode indicator.
400 * @cmd_reg_cache : command register cached.
401 * @cmd_reg_cache_int : command register cached. Used in the irq handler.
402 * @promiscuous : promiscuous mode indicator.
403 * @all_mcast : mutlicast indicator.
404 * @mcast_lst_size : size of multicast list.
405 * @mcast_lst : multicast list.
406 * @mcast_bits : multicast enabed.
407 * @mac_addr : MAC address assigned to this device.
409 * @extra_byte : number of extra byte prepended rx pkt.
410 * @enabled : indicator this device works.
412 * The @lock ensures that the chip is protected when certain operations are
413 * in progress. When the read or write packet transfer is in progress, most
414 * of the chip registers are not accessible until the transfer is finished and
415 * the DMA has been de-asserted.
417 * The @statelock is used to protect information in the structure which may
418 * need to be accessed via several sources, such as the network driver layer
419 * or one of the work queues.
423 /* Receive multiplex framer header info */
424 struct type_frame_head {
425 u16 sts; /* Frame status */
426 u16 len; /* Byte count */
430 struct net_device *netdev;
431 void __iomem *hw_addr;
432 void __iomem *hw_addr_cmd;
433 union ks_tx_hdr txh ____cacheline_aligned;
434 struct mutex lock; /* spinlock to be interrupt safe */
435 struct platform_device *pdev;
436 struct mii_if_info mii;
437 struct type_frame_head *frame_head_info;
438 spinlock_t statelock;
449 u16 cmd_reg_cache_int;
453 u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN];
454 u8 mcast_bits[HW_MCAST_SIZE];
461 static int msg_enable;
463 #define BE3 0x8000 /* Byte Enable 3 */
464 #define BE2 0x4000 /* Byte Enable 2 */
465 #define BE1 0x2000 /* Byte Enable 1 */
466 #define BE0 0x1000 /* Byte Enable 0 */
469 * register read/write calls.
471 * All these calls issue transactions to access the chip's registers. They
472 * all require that the necessary lock is held to prevent accesses when the
473 * chip is busy transfering packet data (RX/TX FIFO accesses).
477 * ks_rdreg8 - read 8 bit register from device
478 * @ks : The chip information
479 * @offset: The register address
481 * Read a 8bit register from the chip, returning the result
483 static u8 ks_rdreg8(struct ks_net *ks, int offset)
486 u8 shift_bit = offset & 0x03;
487 u8 shift_data = (offset & 1) << 3;
488 ks->cmd_reg_cache = (u16) offset | (u16)(BE0 << shift_bit);
489 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
490 data = ioread16(ks->hw_addr);
491 return (u8)(data >> shift_data);
495 * ks_rdreg16 - read 16 bit register from device
496 * @ks : The chip information
497 * @offset: The register address
499 * Read a 16bit register from the chip, returning the result
502 static u16 ks_rdreg16(struct ks_net *ks, int offset)
504 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
505 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
506 return ioread16(ks->hw_addr);
510 * ks_wrreg8 - write 8bit register value to chip
511 * @ks: The chip information
512 * @offset: The register address
513 * @value: The value to write
516 static void ks_wrreg8(struct ks_net *ks, int offset, u8 value)
518 u8 shift_bit = (offset & 0x03);
519 u16 value_write = (u16)(value << ((offset & 1) << 3));
520 ks->cmd_reg_cache = (u16)offset | (BE0 << shift_bit);
521 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
522 iowrite16(value_write, ks->hw_addr);
526 * ks_wrreg16 - write 16bit register value to chip
527 * @ks: The chip information
528 * @offset: The register address
529 * @value: The value to write
533 static void ks_wrreg16(struct ks_net *ks, int offset, u16 value)
535 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
536 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
537 iowrite16(value, ks->hw_addr);
541 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode enabled.
542 * @ks: The chip state
543 * @wptr: buffer address to save data
544 * @len: length in byte to read
547 static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
551 *wptr++ = (u16)ioread16(ks->hw_addr);
555 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
556 * @ks: The chip information
557 * @wptr: buffer address
558 * @len: length in byte to write
561 static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
565 iowrite16(*wptr++, ks->hw_addr);
568 static void ks_disable_int(struct ks_net *ks)
570 ks_wrreg16(ks, KS_IER, 0x0000);
571 } /* ks_disable_int */
573 static void ks_enable_int(struct ks_net *ks)
575 ks_wrreg16(ks, KS_IER, ks->rc_ier);
576 } /* ks_enable_int */
579 * ks_tx_fifo_space - return the available hardware buffer size.
580 * @ks: The chip information
583 static inline u16 ks_tx_fifo_space(struct ks_net *ks)
585 return ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
589 * ks_save_cmd_reg - save the command register from the cache.
590 * @ks: The chip information
593 static inline void ks_save_cmd_reg(struct ks_net *ks)
595 /*ks8851 MLL has a bug to read back the command register.
596 * So rely on software to save the content of command register.
598 ks->cmd_reg_cache_int = ks->cmd_reg_cache;
602 * ks_restore_cmd_reg - restore the command register from the cache and
603 * write to hardware register.
604 * @ks: The chip information
607 static inline void ks_restore_cmd_reg(struct ks_net *ks)
609 ks->cmd_reg_cache = ks->cmd_reg_cache_int;
610 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
614 * ks_set_powermode - set power mode of the device
615 * @ks: The chip information
616 * @pwrmode: The power mode value to write to KS_PMECR.
618 * Change the power mode of the chip.
620 static void ks_set_powermode(struct ks_net *ks, unsigned pwrmode)
624 netif_dbg(ks, hw, ks->netdev, "setting power mode %d\n", pwrmode);
626 ks_rdreg16(ks, KS_GRR);
627 pmecr = ks_rdreg16(ks, KS_PMECR);
628 pmecr &= ~PMECR_PM_MASK;
631 ks_wrreg16(ks, KS_PMECR, pmecr);
635 * ks_read_config - read chip configuration of bus width.
636 * @ks: The chip information
639 static void ks_read_config(struct ks_net *ks)
643 /* Regardless of bus width, 8 bit read should always work.*/
644 reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
645 reg_data |= ks_rdreg8(ks, KS_CCR+1) << 8;
647 /* addr/data bus are multiplexed */
648 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
650 /* There are garbage data when reading data from QMU,
651 depending on bus-width.
654 if (reg_data & CCR_8BIT) {
655 ks->bus_width = ENUM_BUS_8BIT;
657 } else if (reg_data & CCR_16BIT) {
658 ks->bus_width = ENUM_BUS_16BIT;
661 ks->bus_width = ENUM_BUS_32BIT;
667 * ks_soft_reset - issue one of the soft reset to the device
668 * @ks: The device state.
669 * @op: The bit(s) to set in the GRR
671 * Issue the relevant soft-reset command to the device's GRR register
674 * Note, the delays are in there as a caution to ensure that the reset
675 * has time to take effect and then complete. Since the datasheet does
676 * not currently specify the exact sequence, we have chosen something
677 * that seems to work with our device.
679 static void ks_soft_reset(struct ks_net *ks, unsigned op)
681 /* Disable interrupt first */
682 ks_wrreg16(ks, KS_IER, 0x0000);
683 ks_wrreg16(ks, KS_GRR, op);
684 mdelay(10); /* wait a short time to effect reset */
685 ks_wrreg16(ks, KS_GRR, 0);
686 mdelay(1); /* wait for condition to clear */
690 void ks_enable_qmu(struct ks_net *ks)
694 w = ks_rdreg16(ks, KS_TXCR);
695 /* Enables QMU Transmit (TXCR). */
696 ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
699 * RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame
703 w = ks_rdreg16(ks, KS_RXQCR);
704 ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
706 /* Enables QMU Receive (RXCR1). */
707 w = ks_rdreg16(ks, KS_RXCR1);
708 ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
710 } /* ks_enable_qmu */
712 static void ks_disable_qmu(struct ks_net *ks)
716 w = ks_rdreg16(ks, KS_TXCR);
718 /* Disables QMU Transmit (TXCR). */
720 ks_wrreg16(ks, KS_TXCR, w);
722 /* Disables QMU Receive (RXCR1). */
723 w = ks_rdreg16(ks, KS_RXCR1);
725 ks_wrreg16(ks, KS_RXCR1, w);
729 } /* ks_disable_qmu */
732 * ks_read_qmu - read 1 pkt data from the QMU.
733 * @ks: The chip information
734 * @buf: buffer address to save 1 pkt
736 * Here is the sequence to read 1 pkt:
737 * 1. set sudo DMA mode
738 * 2. read prepend data
740 * 4. reset sudo DMA Mode
742 static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
744 u32 r = ks->extra_byte & 0x1 ;
745 u32 w = ks->extra_byte - r;
747 /* 1. set sudo DMA mode */
748 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
749 ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
751 /* 2. read prepend data */
753 * read 4 + extra bytes and discard them.
754 * extra bytes for dummy, 2 for status, 2 for len
757 /* use likely(r) for 8 bit access for performance */
759 ioread8(ks->hw_addr);
760 ks_inblk(ks, buf, w + 2 + 2);
762 /* 3. read pkt data */
763 ks_inblk(ks, buf, ALIGN(len, 4));
765 /* 4. reset sudo DMA Mode */
766 ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr);
770 * ks_rcv - read multiple pkts data from the QMU.
771 * @ks: The chip information
772 * @netdev: The network device being opened.
774 * Read all of header information before reading pkt content.
775 * It is not allowed only port of pkts in QMU after issuing
778 static void ks_rcv(struct ks_net *ks, struct net_device *netdev)
781 struct type_frame_head *frame_hdr = ks->frame_head_info;
784 ks->frame_cnt = ks_rdreg16(ks, KS_RXFCTR) >> 8;
786 /* read all header information */
787 for (i = 0; i < ks->frame_cnt; i++) {
788 /* Checking Received packet status */
789 frame_hdr->sts = ks_rdreg16(ks, KS_RXFHSR);
790 /* Get packet len from hardware */
791 frame_hdr->len = ks_rdreg16(ks, KS_RXFHBCR);
795 frame_hdr = ks->frame_head_info;
796 while (ks->frame_cnt--) {
797 skb = dev_alloc_skb(frame_hdr->len + 16);
798 if (likely(skb && (frame_hdr->sts & RXFSHR_RXFV) &&
799 (frame_hdr->len < RX_BUF_SIZE) && frame_hdr->len)) {
801 /* read data block including CRC 4 bytes */
802 ks_read_qmu(ks, (u16 *)skb->data, frame_hdr->len);
803 skb_put(skb, frame_hdr->len);
805 skb->protocol = eth_type_trans(skb, netdev);
808 pr_err("%s: err:skb alloc\n", __func__);
809 ks_wrreg16(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
811 dev_kfree_skb_irq(skb);
818 * ks_update_link_status - link status update.
819 * @netdev: The network device being opened.
820 * @ks: The chip information
824 static void ks_update_link_status(struct net_device *netdev, struct ks_net *ks)
826 /* check the status of the link */
828 if (ks_rdreg16(ks, KS_P1SR) & P1SR_LINK_GOOD) {
829 netif_carrier_on(netdev);
830 link_up_status = true;
832 netif_carrier_off(netdev);
833 link_up_status = false;
835 netif_dbg(ks, link, ks->netdev,
836 "%s: %s\n", __func__, link_up_status ? "UP" : "DOWN");
840 * ks_irq - device interrupt handler
841 * @irq: Interrupt number passed from the IRQ hnalder.
842 * @pw: The private word passed to register_irq(), our struct ks_net.
844 * This is the handler invoked to find out what happened
846 * Read the interrupt status, work out what needs to be done and then clear
847 * any of the interrupts that are not needed.
850 static irqreturn_t ks_irq(int irq, void *pw)
852 struct net_device *netdev = pw;
853 struct ks_net *ks = netdev_priv(netdev);
856 /*this should be the first in IRQ handler */
859 status = ks_rdreg16(ks, KS_ISR);
860 if (unlikely(!status)) {
861 ks_restore_cmd_reg(ks);
865 ks_wrreg16(ks, KS_ISR, status);
867 if (likely(status & IRQ_RXI))
870 if (unlikely(status & IRQ_LCI))
871 ks_update_link_status(netdev, ks);
873 if (unlikely(status & IRQ_TXI))
874 netif_wake_queue(netdev);
876 if (unlikely(status & IRQ_LDI)) {
878 u16 pmecr = ks_rdreg16(ks, KS_PMECR);
879 pmecr &= ~PMECR_WKEVT_MASK;
880 ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
883 /* this should be the last in IRQ handler*/
884 ks_restore_cmd_reg(ks);
890 * ks_net_open - open network device
891 * @netdev: The network device being opened.
893 * Called when the network device is marked active, such as a user executing
894 * 'ifconfig up' on the device.
896 static int ks_net_open(struct net_device *netdev)
898 struct ks_net *ks = netdev_priv(netdev);
901 #define KS_INT_FLAGS (IRQF_DISABLED|IRQF_TRIGGER_LOW)
902 /* lock the card, even if we may not actually do anything
903 * else at the moment.
906 netif_dbg(ks, ifup, ks->netdev, "%s - entry\n", __func__);
909 err = request_irq(ks->irq, ks_irq, KS_INT_FLAGS, DRV_NAME, netdev);
912 pr_err("Failed to request IRQ: %d: %d\n", ks->irq, err);
916 /* wake up powermode to normal mode */
917 ks_set_powermode(ks, PMECR_PM_NORMAL);
918 mdelay(1); /* wait for normal mode to take effect */
920 ks_wrreg16(ks, KS_ISR, 0xffff);
923 netif_start_queue(ks->netdev);
925 netif_dbg(ks, ifup, ks->netdev, "network device up\n");
931 * ks_net_stop - close network device
932 * @netdev: The device being closed.
934 * Called to close down a network device which has been active. Cancell any
935 * work, shutdown the RX and TX process and then place the chip into a low
936 * power state whilst it is not being used.
938 static int ks_net_stop(struct net_device *netdev)
940 struct ks_net *ks = netdev_priv(netdev);
942 netif_info(ks, ifdown, netdev, "shutting down\n");
944 netif_stop_queue(netdev);
946 mutex_lock(&ks->lock);
948 /* turn off the IRQs and ack any outstanding */
949 ks_wrreg16(ks, KS_IER, 0x0000);
950 ks_wrreg16(ks, KS_ISR, 0xffff);
952 /* shutdown RX/TX QMU */
955 /* set powermode to soft power down to save power */
956 ks_set_powermode(ks, PMECR_PM_SOFTDOWN);
957 free_irq(ks->irq, netdev);
958 mutex_unlock(&ks->lock);
964 * ks_write_qmu - write 1 pkt data to the QMU.
965 * @ks: The chip information
966 * @pdata: buffer address to save 1 pkt
967 * @len: Pkt length in byte
968 * Here is the sequence to write 1 pkt:
969 * 1. set sudo DMA mode
970 * 2. write status/length
972 * 4. reset sudo DMA Mode
973 * 5. reset sudo DMA mode
974 * 6. Wait until pkt is out
976 static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
978 /* start header at txb[0] to align txw entries */
980 ks->txh.txw[1] = cpu_to_le16(len);
982 /* 1. set sudo-DMA mode */
983 ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
984 /* 2. write status/lenth info */
985 ks_outblk(ks, ks->txh.txw, 4);
986 /* 3. write pkt data */
987 ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
988 /* 4. reset sudo-DMA mode */
989 ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr);
990 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
991 ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
992 /* 6. wait until TXQCR_METFE is auto-cleared */
993 while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE)
998 * ks_start_xmit - transmit packet
999 * @skb : The buffer to transmit
1000 * @netdev : The device used to transmit the packet.
1002 * Called by the network layer to transmit the @skb.
1003 * spin_lock_irqsave is required because tx and rx should be mutual exclusive.
1004 * So while tx is in-progress, prevent IRQ interrupt from happenning.
1006 static int ks_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1008 int retv = NETDEV_TX_OK;
1009 struct ks_net *ks = netdev_priv(netdev);
1011 disable_irq(netdev->irq);
1013 spin_lock(&ks->statelock);
1015 /* Extra space are required:
1016 * 4 byte for alignment, 4 for status/length, 4 for CRC
1019 if (likely(ks_tx_fifo_space(ks) >= skb->len + 12)) {
1020 ks_write_qmu(ks, skb->data, skb->len);
1023 retv = NETDEV_TX_BUSY;
1024 spin_unlock(&ks->statelock);
1026 enable_irq(netdev->irq);
1031 * ks_start_rx - ready to serve pkts
1032 * @ks : The chip information
1035 static void ks_start_rx(struct ks_net *ks)
1039 /* Enables QMU Receive (RXCR1). */
1040 cntl = ks_rdreg16(ks, KS_RXCR1);
1042 ks_wrreg16(ks, KS_RXCR1, cntl);
1046 * ks_stop_rx - stop to serve pkts
1047 * @ks : The chip information
1050 static void ks_stop_rx(struct ks_net *ks)
1054 /* Disables QMU Receive (RXCR1). */
1055 cntl = ks_rdreg16(ks, KS_RXCR1);
1056 cntl &= ~RXCR1_RXE ;
1057 ks_wrreg16(ks, KS_RXCR1, cntl);
1061 static unsigned long const ethernet_polynomial = 0x04c11db7U;
1063 static unsigned long ether_gen_crc(int length, u8 *data)
1066 while (--length >= 0) {
1067 u8 current_octet = *data++;
1070 for (bit = 0; bit < 8; bit++, current_octet >>= 1) {
1072 ((crc < 0) ^ (current_octet & 1) ?
1073 ethernet_polynomial : 0);
1076 return (unsigned long)crc;
1077 } /* ether_gen_crc */
1080 * ks_set_grpaddr - set multicast information
1081 * @ks : The chip information
1084 static void ks_set_grpaddr(struct ks_net *ks)
1087 u32 index, position, value;
1089 memset(ks->mcast_bits, 0, sizeof(u8) * HW_MCAST_SIZE);
1091 for (i = 0; i < ks->mcast_lst_size; i++) {
1092 position = (ether_gen_crc(6, ks->mcast_lst[i]) >> 26) & 0x3f;
1093 index = position >> 3;
1094 value = 1 << (position & 7);
1095 ks->mcast_bits[index] |= (u8)value;
1098 for (i = 0; i < HW_MCAST_SIZE; i++) {
1100 ks_wrreg16(ks, (u16)((KS_MAHTR0 + i) & ~1),
1101 (ks->mcast_bits[i] << 8) |
1102 ks->mcast_bits[i - 1]);
1105 } /* ks_set_grpaddr */
1108 * ks_clear_mcast - clear multicast information
1110 * @ks : The chip information
1111 * This routine removes all mcast addresses set in the hardware.
1114 static void ks_clear_mcast(struct ks_net *ks)
1117 for (i = 0; i < HW_MCAST_SIZE; i++)
1118 ks->mcast_bits[i] = 0;
1120 mcast_size = HW_MCAST_SIZE >> 2;
1121 for (i = 0; i < mcast_size; i++)
1122 ks_wrreg16(ks, KS_MAHTR0 + (2*i), 0);
1125 static void ks_set_promis(struct ks_net *ks, u16 promiscuous_mode)
1128 ks->promiscuous = promiscuous_mode;
1129 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1130 cntl = ks_rdreg16(ks, KS_RXCR1);
1132 cntl &= ~RXCR1_FILTER_MASK;
1133 if (promiscuous_mode)
1134 /* Enable Promiscuous mode */
1135 cntl |= RXCR1_RXAE | RXCR1_RXINVF;
1137 /* Disable Promiscuous mode (default normal mode) */
1138 cntl |= RXCR1_RXPAFMA;
1140 ks_wrreg16(ks, KS_RXCR1, cntl);
1145 } /* ks_set_promis */
1147 static void ks_set_mcast(struct ks_net *ks, u16 mcast)
1151 ks->all_mcast = mcast;
1152 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1153 cntl = ks_rdreg16(ks, KS_RXCR1);
1154 cntl &= ~RXCR1_FILTER_MASK;
1156 /* Enable "Perfect with Multicast address passed mode" */
1157 cntl |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
1160 * Disable "Perfect with Multicast address passed
1161 * mode" (normal mode).
1163 cntl |= RXCR1_RXPAFMA;
1165 ks_wrreg16(ks, KS_RXCR1, cntl);
1169 } /* ks_set_mcast */
1171 static void ks_set_rx_mode(struct net_device *netdev)
1173 struct ks_net *ks = netdev_priv(netdev);
1174 struct dev_mc_list *ptr;
1176 /* Turn on/off promiscuous mode. */
1177 if ((netdev->flags & IFF_PROMISC) == IFF_PROMISC)
1179 (u16)((netdev->flags & IFF_PROMISC) == IFF_PROMISC));
1180 /* Turn on/off all mcast mode. */
1181 else if ((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI)
1183 (u16)((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI));
1185 ks_set_promis(ks, false);
1187 if ((netdev->flags & IFF_MULTICAST) && netdev_mc_count(netdev)) {
1188 if (netdev_mc_count(netdev) <= MAX_MCAST_LST) {
1191 netdev_for_each_mc_addr(ptr, netdev) {
1192 if (!(*ptr->dmi_addr & 1))
1194 if (i >= MAX_MCAST_LST)
1196 memcpy(ks->mcast_lst[i++], ptr->dmi_addr,
1199 ks->mcast_lst_size = (u8)i;
1203 * List too big to support so
1204 * turn on all mcast mode.
1206 ks->mcast_lst_size = MAX_MCAST_LST;
1207 ks_set_mcast(ks, true);
1210 ks->mcast_lst_size = 0;
1213 } /* ks_set_rx_mode */
1215 static void ks_set_mac(struct ks_net *ks, u8 *data)
1217 u16 *pw = (u16 *)data;
1220 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1223 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1224 ks_wrreg16(ks, KS_MARH, w);
1227 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1228 ks_wrreg16(ks, KS_MARM, w);
1231 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1232 ks_wrreg16(ks, KS_MARL, w);
1234 memcpy(ks->mac_addr, data, 6);
1240 static int ks_set_mac_address(struct net_device *netdev, void *paddr)
1242 struct ks_net *ks = netdev_priv(netdev);
1243 struct sockaddr *addr = paddr;
1246 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1248 da = (u8 *)netdev->dev_addr;
1254 static int ks_net_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
1256 struct ks_net *ks = netdev_priv(netdev);
1258 if (!netif_running(netdev))
1261 return generic_mii_ioctl(&ks->mii, if_mii(req), cmd, NULL);
1264 static const struct net_device_ops ks_netdev_ops = {
1265 .ndo_open = ks_net_open,
1266 .ndo_stop = ks_net_stop,
1267 .ndo_do_ioctl = ks_net_ioctl,
1268 .ndo_start_xmit = ks_start_xmit,
1269 .ndo_set_mac_address = ks_set_mac_address,
1270 .ndo_set_rx_mode = ks_set_rx_mode,
1271 .ndo_change_mtu = eth_change_mtu,
1272 .ndo_validate_addr = eth_validate_addr,
1275 /* ethtool support */
1277 static void ks_get_drvinfo(struct net_device *netdev,
1278 struct ethtool_drvinfo *di)
1280 strlcpy(di->driver, DRV_NAME, sizeof(di->driver));
1281 strlcpy(di->version, "1.00", sizeof(di->version));
1282 strlcpy(di->bus_info, dev_name(netdev->dev.parent),
1283 sizeof(di->bus_info));
1286 static u32 ks_get_msglevel(struct net_device *netdev)
1288 struct ks_net *ks = netdev_priv(netdev);
1289 return ks->msg_enable;
1292 static void ks_set_msglevel(struct net_device *netdev, u32 to)
1294 struct ks_net *ks = netdev_priv(netdev);
1295 ks->msg_enable = to;
1298 static int ks_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1300 struct ks_net *ks = netdev_priv(netdev);
1301 return mii_ethtool_gset(&ks->mii, cmd);
1304 static int ks_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1306 struct ks_net *ks = netdev_priv(netdev);
1307 return mii_ethtool_sset(&ks->mii, cmd);
1310 static u32 ks_get_link(struct net_device *netdev)
1312 struct ks_net *ks = netdev_priv(netdev);
1313 return mii_link_ok(&ks->mii);
1316 static int ks_nway_reset(struct net_device *netdev)
1318 struct ks_net *ks = netdev_priv(netdev);
1319 return mii_nway_restart(&ks->mii);
1322 static const struct ethtool_ops ks_ethtool_ops = {
1323 .get_drvinfo = ks_get_drvinfo,
1324 .get_msglevel = ks_get_msglevel,
1325 .set_msglevel = ks_set_msglevel,
1326 .get_settings = ks_get_settings,
1327 .set_settings = ks_set_settings,
1328 .get_link = ks_get_link,
1329 .nway_reset = ks_nway_reset,
1332 /* MII interface controls */
1335 * ks_phy_reg - convert MII register into a KS8851 register
1336 * @reg: MII register number.
1338 * Return the KS8851 register number for the corresponding MII PHY register
1339 * if possible. Return zero if the MII register has no direct mapping to the
1340 * KS8851 register set.
1342 static int ks_phy_reg(int reg)
1363 * ks_phy_read - MII interface PHY register read.
1364 * @netdev: The network device the PHY is on.
1365 * @phy_addr: Address of PHY (ignored as we only have one)
1366 * @reg: The register to read.
1368 * This call reads data from the PHY register specified in @reg. Since the
1369 * device does not support all the MII registers, the non-existant values
1370 * are always returned as zero.
1372 * We return zero for unsupported registers as the MII code does not check
1373 * the value returned for any error status, and simply returns it to the
1374 * caller. The mii-tool that the driver was tested with takes any -ve error
1375 * as real PHY capabilities, thus displaying incorrect data to the user.
1377 static int ks_phy_read(struct net_device *netdev, int phy_addr, int reg)
1379 struct ks_net *ks = netdev_priv(netdev);
1383 ksreg = ks_phy_reg(reg);
1385 return 0x0; /* no error return allowed, so use zero */
1387 mutex_lock(&ks->lock);
1388 result = ks_rdreg16(ks, ksreg);
1389 mutex_unlock(&ks->lock);
1394 static void ks_phy_write(struct net_device *netdev,
1395 int phy, int reg, int value)
1397 struct ks_net *ks = netdev_priv(netdev);
1400 ksreg = ks_phy_reg(reg);
1402 mutex_lock(&ks->lock);
1403 ks_wrreg16(ks, ksreg, value);
1404 mutex_unlock(&ks->lock);
1409 * ks_read_selftest - read the selftest memory info.
1410 * @ks: The device state
1412 * Read and check the TX/RX memory selftest information.
1414 static int ks_read_selftest(struct ks_net *ks)
1416 unsigned both_done = MBIR_TXMBF | MBIR_RXMBF;
1420 rd = ks_rdreg16(ks, KS_MBIR);
1422 if ((rd & both_done) != both_done) {
1423 netdev_warn(ks->netdev, "Memory selftest not finished\n");
1427 if (rd & MBIR_TXMBFA) {
1428 netdev_err(ks->netdev, "TX memory selftest fails\n");
1432 if (rd & MBIR_RXMBFA) {
1433 netdev_err(ks->netdev, "RX memory selftest fails\n");
1437 netdev_info(ks->netdev, "the selftest passes\n");
1441 static void ks_setup(struct ks_net *ks)
1446 * Configure QMU Transmit
1449 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
1450 ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
1452 /* Setup Receive Frame Data Pointer Auto-Increment */
1453 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
1455 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
1456 ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
1458 /* Setup RxQ Command Control (RXQCR) */
1459 ks->rc_rxqcr = RXQCR_CMD_CNTL;
1460 ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
1463 * set the force mode to half duplex, default is full duplex
1464 * because if the auto-negotiation fails, most switch uses
1468 w = ks_rdreg16(ks, KS_P1MBCR);
1469 w &= ~P1MBCR_FORCE_FDX;
1470 ks_wrreg16(ks, KS_P1MBCR, w);
1472 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
1473 ks_wrreg16(ks, KS_TXCR, w);
1475 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
1477 if (ks->promiscuous) /* bPromiscuous */
1478 w |= (RXCR1_RXAE | RXCR1_RXINVF);
1479 else if (ks->all_mcast) /* Multicast address passed mode */
1480 w |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
1481 else /* Normal mode */
1484 ks_wrreg16(ks, KS_RXCR1, w);
1488 static void ks_setup_int(struct ks_net *ks)
1491 /* Clear the interrupts status of the hardware. */
1492 ks_wrreg16(ks, KS_ISR, 0xffff);
1494 /* Enables the interrupts of the hardware. */
1495 ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
1496 } /* ks_setup_int */
1498 static int ks_hw_init(struct ks_net *ks)
1500 #define MHEADER_SIZE (sizeof(struct type_frame_head) * MAX_RECV_FRAMES)
1501 ks->promiscuous = 0;
1503 ks->mcast_lst_size = 0;
1505 ks->frame_head_info = (struct type_frame_head *) \
1506 kmalloc(MHEADER_SIZE, GFP_KERNEL);
1507 if (!ks->frame_head_info) {
1508 pr_err("Error: Fail to allocate frame memory\n");
1512 ks_set_mac(ks, KS_DEFAULT_MAC_ADDRESS);
1517 static int __devinit ks8851_probe(struct platform_device *pdev)
1520 struct resource *io_d, *io_c;
1521 struct net_device *netdev;
1525 io_d = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1526 io_c = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1528 if (!request_mem_region(io_d->start, resource_size(io_d), DRV_NAME))
1529 goto err_mem_region;
1531 if (!request_mem_region(io_c->start, resource_size(io_c), DRV_NAME))
1532 goto err_mem_region1;
1534 netdev = alloc_etherdev(sizeof(struct ks_net));
1536 goto err_alloc_etherdev;
1538 SET_NETDEV_DEV(netdev, &pdev->dev);
1540 ks = netdev_priv(netdev);
1541 ks->netdev = netdev;
1542 ks->hw_addr = ioremap(io_d->start, resource_size(io_d));
1547 ks->hw_addr_cmd = ioremap(io_c->start, resource_size(io_c));
1548 if (!ks->hw_addr_cmd)
1551 ks->irq = platform_get_irq(pdev, 0);
1560 mutex_init(&ks->lock);
1561 spin_lock_init(&ks->statelock);
1563 netdev->netdev_ops = &ks_netdev_ops;
1564 netdev->ethtool_ops = &ks_ethtool_ops;
1566 /* setup mii state */
1567 ks->mii.dev = netdev;
1569 ks->mii.phy_id_mask = 1;
1570 ks->mii.reg_num_mask = 0xf;
1571 ks->mii.mdio_read = ks_phy_read;
1572 ks->mii.mdio_write = ks_phy_write;
1574 netdev_info(netdev, "message enable is %d\n", msg_enable);
1575 /* set the default message enable */
1576 ks->msg_enable = netif_msg_init(msg_enable, (NETIF_MSG_DRV |
1581 /* simple check for a valid chip being connected to the bus */
1582 if ((ks_rdreg16(ks, KS_CIDER) & ~CIDER_REV_MASK) != CIDER_ID) {
1583 netdev_err(netdev, "failed to read device ID\n");
1588 if (ks_read_selftest(ks)) {
1589 netdev_err(netdev, "failed to read device ID\n");
1594 err = register_netdev(netdev);
1598 platform_set_drvdata(pdev, netdev);
1600 ks_soft_reset(ks, GRR_GSR);
1605 memcpy(netdev->dev_addr, ks->mac_addr, 6);
1607 data = ks_rdreg16(ks, KS_OBCR);
1608 ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
1611 * If you want to use the default MAC addr,
1612 * comment out the 2 functions below.
1615 random_ether_addr(netdev->dev_addr);
1616 ks_set_mac(ks, netdev->dev_addr);
1618 id = ks_rdreg16(ks, KS_CIDER);
1620 netdev_info(netdev, "Found chip, family: 0x%x, id: 0x%x, rev: 0x%x\n",
1621 (id >> 8) & 0xff, (id >> 4) & 0xf, (id >> 1) & 0x7);
1626 iounmap(ks->hw_addr_cmd);
1628 iounmap(ks->hw_addr);
1630 free_netdev(netdev);
1632 release_mem_region(io_c->start, resource_size(io_c));
1634 release_mem_region(io_d->start, resource_size(io_d));
1639 static int __devexit ks8851_remove(struct platform_device *pdev)
1641 struct net_device *netdev = platform_get_drvdata(pdev);
1642 struct ks_net *ks = netdev_priv(netdev);
1643 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1645 kfree(ks->frame_head_info);
1646 unregister_netdev(netdev);
1647 iounmap(ks->hw_addr);
1648 free_netdev(netdev);
1649 release_mem_region(iomem->start, resource_size(iomem));
1650 platform_set_drvdata(pdev, NULL);
1655 static struct platform_driver ks8851_platform_driver = {
1658 .owner = THIS_MODULE,
1660 .probe = ks8851_probe,
1661 .remove = __devexit_p(ks8851_remove),
1664 static int __init ks8851_init(void)
1666 return platform_driver_register(&ks8851_platform_driver);
1669 static void __exit ks8851_exit(void)
1671 platform_driver_unregister(&ks8851_platform_driver);
1674 module_init(ks8851_init);
1675 module_exit(ks8851_exit);
1677 MODULE_DESCRIPTION("KS8851 MLL Network driver");
1678 MODULE_AUTHOR("David Choi <david.choi@micrel.com>");
1679 MODULE_LICENSE("GPL");
1680 module_param_named(message, msg_enable, int, 0);
1681 MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");